Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.72 98.27 93.44 96.79 80.92 96.87 96.58 93.15


Total test records in report: 968
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T785 /workspace/coverage/default/23.edn_disable_auto_req_mode.2771393909 Mar 14 12:49:01 PM PDT 24 Mar 14 12:49:02 PM PDT 24 50694283 ps
T786 /workspace/coverage/default/23.edn_alert_test.322086023 Mar 14 12:48:56 PM PDT 24 Mar 14 12:48:57 PM PDT 24 46292915 ps
T787 /workspace/coverage/default/25.edn_stress_all.3617412474 Mar 14 12:49:06 PM PDT 24 Mar 14 12:49:08 PM PDT 24 206240674 ps
T788 /workspace/coverage/default/5.edn_regwen.3655065254 Mar 14 12:48:23 PM PDT 24 Mar 14 12:48:24 PM PDT 24 28929621 ps
T79 /workspace/coverage/default/88.edn_err.2295548870 Mar 14 12:49:51 PM PDT 24 Mar 14 12:49:53 PM PDT 24 90057763 ps
T292 /workspace/coverage/default/214.edn_genbits.1407860355 Mar 14 12:50:20 PM PDT 24 Mar 14 12:50:25 PM PDT 24 99796213 ps
T789 /workspace/coverage/default/102.edn_genbits.1910900122 Mar 14 12:50:05 PM PDT 24 Mar 14 12:50:08 PM PDT 24 38087282 ps
T790 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1162677691 Mar 14 12:49:08 PM PDT 24 Mar 14 01:08:32 PM PDT 24 532087197794 ps
T151 /workspace/coverage/default/33.edn_disable.2414527510 Mar 14 12:49:16 PM PDT 24 Mar 14 12:49:17 PM PDT 24 78406941 ps
T791 /workspace/coverage/default/12.edn_err.3284507311 Mar 14 12:48:43 PM PDT 24 Mar 14 12:48:44 PM PDT 24 39947356 ps
T792 /workspace/coverage/default/71.edn_genbits.3529382433 Mar 14 12:49:50 PM PDT 24 Mar 14 12:49:52 PM PDT 24 40699007 ps
T280 /workspace/coverage/default/9.edn_genbits.887160539 Mar 14 12:48:37 PM PDT 24 Mar 14 12:48:39 PM PDT 24 42335936 ps
T793 /workspace/coverage/default/120.edn_genbits.3915215889 Mar 14 12:50:05 PM PDT 24 Mar 14 12:50:08 PM PDT 24 73643069 ps
T794 /workspace/coverage/default/49.edn_disable_auto_req_mode.485391544 Mar 14 12:49:36 PM PDT 24 Mar 14 12:49:38 PM PDT 24 67686016 ps
T795 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1113385387 Mar 14 12:49:40 PM PDT 24 Mar 14 01:11:58 PM PDT 24 85203310839 ps
T796 /workspace/coverage/default/221.edn_genbits.3020986648 Mar 14 12:50:20 PM PDT 24 Mar 14 12:50:25 PM PDT 24 62325933 ps
T797 /workspace/coverage/default/27.edn_disable.3973922037 Mar 14 12:49:09 PM PDT 24 Mar 14 12:49:11 PM PDT 24 157098856 ps
T798 /workspace/coverage/default/91.edn_err.7721125 Mar 14 12:49:51 PM PDT 24 Mar 14 12:49:53 PM PDT 24 32205361 ps
T799 /workspace/coverage/default/49.edn_smoke.1533153020 Mar 14 12:49:39 PM PDT 24 Mar 14 12:49:40 PM PDT 24 27537699 ps
T800 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2628442642 Mar 14 12:49:18 PM PDT 24 Mar 14 01:38:51 PM PDT 24 712057464313 ps
T801 /workspace/coverage/default/50.edn_genbits.234201881 Mar 14 12:49:36 PM PDT 24 Mar 14 12:49:38 PM PDT 24 49457597 ps
T802 /workspace/coverage/default/11.edn_disable_auto_req_mode.220238164 Mar 14 12:48:43 PM PDT 24 Mar 14 12:48:45 PM PDT 24 56386272 ps
T803 /workspace/coverage/default/186.edn_genbits.2730172145 Mar 14 12:50:05 PM PDT 24 Mar 14 12:50:08 PM PDT 24 74194504 ps
T804 /workspace/coverage/default/32.edn_intr.2182316692 Mar 14 12:49:10 PM PDT 24 Mar 14 12:49:11 PM PDT 24 38107809 ps
T805 /workspace/coverage/default/28.edn_stress_all.2582363213 Mar 14 12:49:10 PM PDT 24 Mar 14 12:49:16 PM PDT 24 203000946 ps
T806 /workspace/coverage/default/6.edn_smoke.4178324978 Mar 14 12:48:21 PM PDT 24 Mar 14 12:48:22 PM PDT 24 55334781 ps
T807 /workspace/coverage/default/250.edn_genbits.260165125 Mar 14 12:50:18 PM PDT 24 Mar 14 12:50:23 PM PDT 24 94866161 ps
T808 /workspace/coverage/default/45.edn_alert_test.1828142736 Mar 14 12:49:33 PM PDT 24 Mar 14 12:49:34 PM PDT 24 12739306 ps
T809 /workspace/coverage/default/48.edn_stress_all.1336609787 Mar 14 12:49:35 PM PDT 24 Mar 14 12:49:38 PM PDT 24 317378400 ps
T810 /workspace/coverage/default/216.edn_genbits.1065086156 Mar 14 12:50:15 PM PDT 24 Mar 14 12:50:19 PM PDT 24 160794248 ps
T154 /workspace/coverage/default/99.edn_err.3842506426 Mar 14 12:50:03 PM PDT 24 Mar 14 12:50:07 PM PDT 24 35704887 ps
T811 /workspace/coverage/default/4.edn_smoke.915058750 Mar 14 12:48:24 PM PDT 24 Mar 14 12:48:26 PM PDT 24 62288403 ps
T812 /workspace/coverage/default/42.edn_alert.517913777 Mar 14 12:49:26 PM PDT 24 Mar 14 12:49:27 PM PDT 24 24800924 ps
T813 /workspace/coverage/default/15.edn_smoke.2662608885 Mar 14 12:48:45 PM PDT 24 Mar 14 12:48:46 PM PDT 24 24287052 ps
T814 /workspace/coverage/default/144.edn_genbits.3413409241 Mar 14 12:50:05 PM PDT 24 Mar 14 12:50:07 PM PDT 24 77660664 ps
T815 /workspace/coverage/default/7.edn_alert_test.1467603714 Mar 14 12:48:28 PM PDT 24 Mar 14 12:48:29 PM PDT 24 23168235 ps
T816 /workspace/coverage/default/20.edn_stress_all.1605923621 Mar 14 12:48:59 PM PDT 24 Mar 14 12:49:04 PM PDT 24 441181998 ps
T817 /workspace/coverage/default/128.edn_genbits.961449969 Mar 14 12:50:03 PM PDT 24 Mar 14 12:50:06 PM PDT 24 22958216 ps
T818 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2853647797 Mar 14 12:49:23 PM PDT 24 Mar 14 01:46:51 PM PDT 24 531823139237 ps
T819 /workspace/coverage/default/34.edn_smoke.2753780986 Mar 14 12:49:19 PM PDT 24 Mar 14 12:49:20 PM PDT 24 27627033 ps
T820 /workspace/coverage/default/46.edn_genbits.240394027 Mar 14 12:49:27 PM PDT 24 Mar 14 12:49:29 PM PDT 24 52654659 ps
T821 /workspace/coverage/default/236.edn_genbits.1280488724 Mar 14 12:50:14 PM PDT 24 Mar 14 12:50:18 PM PDT 24 59337068 ps
T822 /workspace/coverage/default/26.edn_genbits.1507182140 Mar 14 12:49:06 PM PDT 24 Mar 14 12:49:07 PM PDT 24 47943739 ps
T823 /workspace/coverage/default/220.edn_genbits.2163369932 Mar 14 12:50:11 PM PDT 24 Mar 14 12:50:12 PM PDT 24 59964836 ps
T824 /workspace/coverage/default/277.edn_genbits.2932470437 Mar 14 12:50:18 PM PDT 24 Mar 14 12:50:23 PM PDT 24 51873826 ps
T825 /workspace/coverage/default/3.edn_err.1543303990 Mar 14 12:48:20 PM PDT 24 Mar 14 12:48:21 PM PDT 24 24198990 ps
T826 /workspace/coverage/default/2.edn_stress_all.2547390069 Mar 14 12:48:24 PM PDT 24 Mar 14 12:48:30 PM PDT 24 226588573 ps
T827 /workspace/coverage/default/244.edn_genbits.1348103320 Mar 14 12:50:15 PM PDT 24 Mar 14 12:50:19 PM PDT 24 108724113 ps
T828 /workspace/coverage/default/270.edn_genbits.700991022 Mar 14 12:50:20 PM PDT 24 Mar 14 12:50:26 PM PDT 24 227179783 ps
T829 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2609474476 Mar 14 12:48:41 PM PDT 24 Mar 14 01:02:54 PM PDT 24 35972395970 ps
T830 /workspace/coverage/default/25.edn_alert.1666171969 Mar 14 12:49:09 PM PDT 24 Mar 14 12:49:12 PM PDT 24 45562814 ps
T831 /workspace/coverage/default/32.edn_disable.1532621634 Mar 14 12:49:14 PM PDT 24 Mar 14 12:49:15 PM PDT 24 76455425 ps
T832 /workspace/coverage/default/42.edn_alert_test.406515445 Mar 14 12:49:30 PM PDT 24 Mar 14 12:49:31 PM PDT 24 18392937 ps
T833 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1766064308 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 57246345 ps
T214 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1580269732 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 120422985 ps
T834 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1673005233 Mar 14 12:28:33 PM PDT 24 Mar 14 12:28:35 PM PDT 24 22208632 ps
T835 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2611253079 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:28 PM PDT 24 188548527 ps
T215 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4085764503 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 133821904 ps
T836 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4051491119 Mar 14 12:28:26 PM PDT 24 Mar 14 12:28:27 PM PDT 24 29051204 ps
T837 /workspace/coverage/cover_reg_top/8.edn_csr_rw.621638676 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 41372710 ps
T838 /workspace/coverage/cover_reg_top/6.edn_intr_test.877823047 Mar 14 12:28:16 PM PDT 24 Mar 14 12:28:17 PM PDT 24 51723075 ps
T216 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3232008283 Mar 14 12:28:22 PM PDT 24 Mar 14 12:28:23 PM PDT 24 32211990 ps
T839 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.27233259 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:33 PM PDT 24 20810598 ps
T840 /workspace/coverage/cover_reg_top/38.edn_intr_test.1294939021 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:40 PM PDT 24 16020246 ps
T841 /workspace/coverage/cover_reg_top/18.edn_intr_test.2623809258 Mar 14 12:28:26 PM PDT 24 Mar 14 12:28:28 PM PDT 24 16086272 ps
T842 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3654733490 Mar 14 12:28:19 PM PDT 24 Mar 14 12:28:27 PM PDT 24 221094250 ps
T233 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3188630412 Mar 14 12:28:32 PM PDT 24 Mar 14 12:28:33 PM PDT 24 14618671 ps
T217 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1122458367 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:39 PM PDT 24 72603840 ps
T218 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.409002700 Mar 14 12:28:18 PM PDT 24 Mar 14 12:28:20 PM PDT 24 61134528 ps
T843 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3772345753 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:26 PM PDT 24 75835420 ps
T844 /workspace/coverage/cover_reg_top/4.edn_intr_test.3747679058 Mar 14 12:28:25 PM PDT 24 Mar 14 12:28:26 PM PDT 24 61183752 ps
T845 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3142451002 Mar 14 12:28:28 PM PDT 24 Mar 14 12:28:30 PM PDT 24 194683557 ps
T234 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1054281132 Mar 14 12:28:28 PM PDT 24 Mar 14 12:28:29 PM PDT 24 24011542 ps
T846 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2498913197 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:43 PM PDT 24 126375116 ps
T847 /workspace/coverage/cover_reg_top/3.edn_intr_test.2725567530 Mar 14 12:28:06 PM PDT 24 Mar 14 12:28:07 PM PDT 24 52165016 ps
T848 /workspace/coverage/cover_reg_top/2.edn_intr_test.4240467473 Mar 14 12:28:30 PM PDT 24 Mar 14 12:28:31 PM PDT 24 24135230 ps
T236 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3637969285 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:25 PM PDT 24 124754234 ps
T849 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4261207618 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:40 PM PDT 24 102547078 ps
T237 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.628703306 Mar 14 12:28:22 PM PDT 24 Mar 14 12:28:24 PM PDT 24 475677479 ps
T850 /workspace/coverage/cover_reg_top/5.edn_intr_test.690106373 Mar 14 12:28:47 PM PDT 24 Mar 14 12:28:49 PM PDT 24 65911514 ps
T851 /workspace/coverage/cover_reg_top/46.edn_intr_test.3896255234 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:42 PM PDT 24 121358965 ps
T238 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2201254869 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:41 PM PDT 24 309337859 ps
T852 /workspace/coverage/cover_reg_top/25.edn_intr_test.2269747302 Mar 14 12:28:27 PM PDT 24 Mar 14 12:28:28 PM PDT 24 35210359 ps
T853 /workspace/coverage/cover_reg_top/6.edn_tl_errors.642645949 Mar 14 12:28:25 PM PDT 24 Mar 14 12:28:28 PM PDT 24 84915073 ps
T219 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1736673696 Mar 14 12:28:28 PM PDT 24 Mar 14 12:28:29 PM PDT 24 180453052 ps
T235 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3276770231 Mar 14 12:28:17 PM PDT 24 Mar 14 12:28:18 PM PDT 24 14864042 ps
T854 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3587293820 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:43 PM PDT 24 233726397 ps
T855 /workspace/coverage/cover_reg_top/47.edn_intr_test.1721237484 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:38 PM PDT 24 11514784 ps
T220 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3850232100 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:37 PM PDT 24 79560641 ps
T221 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3812745991 Mar 14 12:28:33 PM PDT 24 Mar 14 12:28:34 PM PDT 24 44668606 ps
T222 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3209714744 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:41 PM PDT 24 12989101 ps
T253 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1401503847 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:26 PM PDT 24 83017688 ps
T856 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1491058896 Mar 14 12:28:28 PM PDT 24 Mar 14 12:28:29 PM PDT 24 11932454 ps
T857 /workspace/coverage/cover_reg_top/33.edn_intr_test.2105354096 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:39 PM PDT 24 43608032 ps
T251 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1288717933 Mar 14 12:28:45 PM PDT 24 Mar 14 12:28:48 PM PDT 24 74785481 ps
T231 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.13358279 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:25 PM PDT 24 35671251 ps
T223 /workspace/coverage/cover_reg_top/12.edn_csr_rw.672968252 Mar 14 12:28:26 PM PDT 24 Mar 14 12:28:27 PM PDT 24 36560894 ps
T858 /workspace/coverage/cover_reg_top/17.edn_intr_test.2440795895 Mar 14 12:28:43 PM PDT 24 Mar 14 12:28:44 PM PDT 24 51545557 ps
T859 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1305090996 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:43 PM PDT 24 71435793 ps
T860 /workspace/coverage/cover_reg_top/9.edn_intr_test.916861828 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:24 PM PDT 24 17696396 ps
T861 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2723141845 Mar 14 12:28:20 PM PDT 24 Mar 14 12:28:23 PM PDT 24 201439590 ps
T254 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2156524510 Mar 14 12:29:16 PM PDT 24 Mar 14 12:29:19 PM PDT 24 93830138 ps
T232 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.325293075 Mar 14 12:28:26 PM PDT 24 Mar 14 12:28:27 PM PDT 24 54259742 ps
T862 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1693680196 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:42 PM PDT 24 139973918 ps
T863 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.7555448 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:37 PM PDT 24 196099793 ps
T864 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3758570208 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:38 PM PDT 24 98879772 ps
T865 /workspace/coverage/cover_reg_top/37.edn_intr_test.3655619568 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:32 PM PDT 24 88559239 ps
T866 /workspace/coverage/cover_reg_top/0.edn_intr_test.1315041694 Mar 14 12:28:18 PM PDT 24 Mar 14 12:28:20 PM PDT 24 41106929 ps
T867 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3353336833 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:44 PM PDT 24 54590388 ps
T868 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3266269770 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:41 PM PDT 24 260380477 ps
T869 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2740877718 Mar 14 12:28:13 PM PDT 24 Mar 14 12:28:14 PM PDT 24 17114797 ps
T870 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3755495928 Mar 14 12:28:16 PM PDT 24 Mar 14 12:28:19 PM PDT 24 416693751 ps
T224 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2814598110 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:39 PM PDT 24 66567065 ps
T871 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1011259215 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:33 PM PDT 24 182897070 ps
T872 /workspace/coverage/cover_reg_top/14.edn_intr_test.4271381055 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:42 PM PDT 24 22042449 ps
T225 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3404854469 Mar 14 12:28:14 PM PDT 24 Mar 14 12:28:15 PM PDT 24 127360242 ps
T252 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4020200023 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:37 PM PDT 24 90598129 ps
T873 /workspace/coverage/cover_reg_top/21.edn_intr_test.1740651979 Mar 14 12:28:21 PM PDT 24 Mar 14 12:28:22 PM PDT 24 24845414 ps
T874 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3668729312 Mar 14 12:28:19 PM PDT 24 Mar 14 12:28:21 PM PDT 24 33001834 ps
T875 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3118526997 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:36 PM PDT 24 209901716 ps
T876 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1172775421 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:43 PM PDT 24 153901951 ps
T877 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3963431258 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:25 PM PDT 24 37370346 ps
T878 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1658496936 Mar 14 12:29:13 PM PDT 24 Mar 14 12:29:14 PM PDT 24 48282036 ps
T879 /workspace/coverage/cover_reg_top/12.edn_intr_test.96915140 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 37897261 ps
T880 /workspace/coverage/cover_reg_top/19.edn_intr_test.1899464011 Mar 14 12:28:44 PM PDT 24 Mar 14 12:28:45 PM PDT 24 31573590 ps
T881 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3529546404 Mar 14 12:28:15 PM PDT 24 Mar 14 12:28:17 PM PDT 24 52166785 ps
T882 /workspace/coverage/cover_reg_top/11.edn_intr_test.1503177129 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:25 PM PDT 24 19715055 ps
T883 /workspace/coverage/cover_reg_top/48.edn_intr_test.3729219774 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:43 PM PDT 24 15362345 ps
T884 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3068375743 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:33 PM PDT 24 40374853 ps
T885 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1615739861 Mar 14 12:28:17 PM PDT 24 Mar 14 12:28:19 PM PDT 24 163075795 ps
T886 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3853347762 Mar 14 12:28:22 PM PDT 24 Mar 14 12:28:23 PM PDT 24 24197114 ps
T887 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3846225804 Mar 14 12:28:32 PM PDT 24 Mar 14 12:28:34 PM PDT 24 45939392 ps
T888 /workspace/coverage/cover_reg_top/20.edn_intr_test.1375764564 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:41 PM PDT 24 46531912 ps
T889 /workspace/coverage/cover_reg_top/39.edn_intr_test.608027326 Mar 14 12:28:18 PM PDT 24 Mar 14 12:28:20 PM PDT 24 25649898 ps
T890 /workspace/coverage/cover_reg_top/41.edn_intr_test.1004575436 Mar 14 12:28:30 PM PDT 24 Mar 14 12:28:30 PM PDT 24 37677875 ps
T891 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3490879391 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:40 PM PDT 24 13057467 ps
T892 /workspace/coverage/cover_reg_top/42.edn_intr_test.2089593025 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:37 PM PDT 24 20984889 ps
T893 /workspace/coverage/cover_reg_top/10.edn_csr_rw.510163096 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:25 PM PDT 24 24730692 ps
T226 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3922023451 Mar 14 12:28:12 PM PDT 24 Mar 14 12:28:20 PM PDT 24 217064332 ps
T894 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3483428751 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 86057779 ps
T895 /workspace/coverage/cover_reg_top/30.edn_intr_test.523641991 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:40 PM PDT 24 39601561 ps
T896 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2356854271 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:48 PM PDT 24 69214374 ps
T897 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1696219529 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:40 PM PDT 24 57780282 ps
T898 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1947566578 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:41 PM PDT 24 70714987 ps
T899 /workspace/coverage/cover_reg_top/36.edn_intr_test.4072351401 Mar 14 12:28:44 PM PDT 24 Mar 14 12:28:45 PM PDT 24 26892973 ps
T900 /workspace/coverage/cover_reg_top/45.edn_intr_test.1038274869 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:40 PM PDT 24 14497795 ps
T901 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.362385810 Mar 14 12:28:29 PM PDT 24 Mar 14 12:28:35 PM PDT 24 21725234 ps
T227 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.496066378 Mar 14 12:28:10 PM PDT 24 Mar 14 12:28:12 PM PDT 24 132490484 ps
T902 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2769188977 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:41 PM PDT 24 181316856 ps
T903 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1254263812 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:24 PM PDT 24 24468958 ps
T904 /workspace/coverage/cover_reg_top/26.edn_intr_test.40175605 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 30794929 ps
T228 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.206042704 Mar 14 12:28:11 PM PDT 24 Mar 14 12:28:12 PM PDT 24 15416861 ps
T905 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.103474613 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:32 PM PDT 24 20367522 ps
T906 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.66170156 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 23690317 ps
T907 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2521921959 Mar 14 12:28:32 PM PDT 24 Mar 14 12:28:37 PM PDT 24 422285037 ps
T908 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4141241738 Mar 14 12:28:02 PM PDT 24 Mar 14 12:28:06 PM PDT 24 446985845 ps
T909 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.560474979 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:44 PM PDT 24 59028857 ps
T229 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2024376689 Mar 14 12:28:11 PM PDT 24 Mar 14 12:28:12 PM PDT 24 15838357 ps
T910 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1142717023 Mar 14 12:28:18 PM PDT 24 Mar 14 12:28:21 PM PDT 24 78496576 ps
T911 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1871663092 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:25 PM PDT 24 119372654 ps
T912 /workspace/coverage/cover_reg_top/1.edn_intr_test.3940431669 Mar 14 12:28:43 PM PDT 24 Mar 14 12:28:44 PM PDT 24 22270634 ps
T913 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3027683867 Mar 14 12:28:30 PM PDT 24 Mar 14 12:28:31 PM PDT 24 17755407 ps
T914 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3129691652 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:41 PM PDT 24 36424584 ps
T915 /workspace/coverage/cover_reg_top/13.edn_intr_test.3389459327 Mar 14 12:28:21 PM PDT 24 Mar 14 12:28:22 PM PDT 24 14202468 ps
T916 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2398884404 Mar 14 12:28:32 PM PDT 24 Mar 14 12:28:34 PM PDT 24 56746786 ps
T917 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2850914061 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:36 PM PDT 24 166412159 ps
T918 /workspace/coverage/cover_reg_top/7.edn_csr_rw.4128577263 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:32 PM PDT 24 11792405 ps
T919 /workspace/coverage/cover_reg_top/15.edn_tl_errors.813672087 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:44 PM PDT 24 82964279 ps
T920 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3663858243 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:33 PM PDT 24 327238584 ps
T921 /workspace/coverage/cover_reg_top/32.edn_intr_test.2401892914 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:32 PM PDT 24 47909655 ps
T922 /workspace/coverage/cover_reg_top/28.edn_intr_test.3642371198 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:24 PM PDT 24 44656579 ps
T923 /workspace/coverage/cover_reg_top/34.edn_intr_test.1828098696 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:39 PM PDT 24 15102751 ps
T924 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1374239047 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:44 PM PDT 24 132454874 ps
T925 /workspace/coverage/cover_reg_top/17.edn_tl_errors.4081867528 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:38 PM PDT 24 19640273 ps
T926 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3017872934 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:39 PM PDT 24 20221794 ps
T927 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3390022255 Mar 14 12:28:13 PM PDT 24 Mar 14 12:28:14 PM PDT 24 22621804 ps
T928 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1630016926 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 57263716 ps
T929 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1945579488 Mar 14 12:28:14 PM PDT 24 Mar 14 12:28:15 PM PDT 24 81887479 ps
T930 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2220560399 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 12637581 ps
T931 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2251328478 Mar 14 12:28:21 PM PDT 24 Mar 14 12:28:25 PM PDT 24 372684669 ps
T932 /workspace/coverage/cover_reg_top/35.edn_intr_test.1687110813 Mar 14 12:28:34 PM PDT 24 Mar 14 12:28:35 PM PDT 24 15942761 ps
T933 /workspace/coverage/cover_reg_top/44.edn_intr_test.2969570179 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:37 PM PDT 24 17285260 ps
T934 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.829527267 Mar 14 12:28:44 PM PDT 24 Mar 14 12:28:46 PM PDT 24 102038887 ps
T935 /workspace/coverage/cover_reg_top/16.edn_intr_test.2565302257 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:42 PM PDT 24 11574979 ps
T936 /workspace/coverage/cover_reg_top/23.edn_intr_test.2508960607 Mar 14 12:28:26 PM PDT 24 Mar 14 12:28:27 PM PDT 24 35033162 ps
T937 /workspace/coverage/cover_reg_top/49.edn_intr_test.2249254065 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:39 PM PDT 24 17101134 ps
T938 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.142573323 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:37 PM PDT 24 23005094 ps
T939 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3023316159 Mar 14 12:28:17 PM PDT 24 Mar 14 12:28:19 PM PDT 24 14449164 ps
T940 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1848069110 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:24 PM PDT 24 30995455 ps
T941 /workspace/coverage/cover_reg_top/27.edn_intr_test.3153072967 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:38 PM PDT 24 38212646 ps
T942 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1719388106 Mar 14 12:28:20 PM PDT 24 Mar 14 12:28:21 PM PDT 24 37906497 ps
T943 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3284645032 Mar 14 12:28:28 PM PDT 24 Mar 14 12:28:31 PM PDT 24 190797210 ps
T944 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1158319354 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:37 PM PDT 24 46948470 ps
T945 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.449047450 Mar 14 12:28:21 PM PDT 24 Mar 14 12:28:23 PM PDT 24 85263469 ps
T946 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3071557425 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:41 PM PDT 24 23119597 ps
T947 /workspace/coverage/cover_reg_top/40.edn_intr_test.753502616 Mar 14 12:28:43 PM PDT 24 Mar 14 12:28:44 PM PDT 24 13694727 ps
T948 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.626259702 Mar 14 12:28:17 PM PDT 24 Mar 14 12:28:27 PM PDT 24 349615726 ps
T949 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1814635409 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:38 PM PDT 24 417993690 ps
T950 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4051047407 Mar 14 12:28:31 PM PDT 24 Mar 14 12:28:33 PM PDT 24 26369623 ps
T951 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1751021913 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:40 PM PDT 24 35597530 ps
T952 /workspace/coverage/cover_reg_top/8.edn_intr_test.983531320 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:24 PM PDT 24 48212590 ps
T953 /workspace/coverage/cover_reg_top/22.edn_intr_test.276453321 Mar 14 12:28:48 PM PDT 24 Mar 14 12:28:49 PM PDT 24 22532047 ps
T954 /workspace/coverage/cover_reg_top/43.edn_intr_test.146578292 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 22623754 ps
T955 /workspace/coverage/cover_reg_top/24.edn_intr_test.1643356038 Mar 14 12:28:49 PM PDT 24 Mar 14 12:28:50 PM PDT 24 27349269 ps
T956 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1097468665 Mar 14 12:28:26 PM PDT 24 Mar 14 12:28:32 PM PDT 24 15819960 ps
T957 /workspace/coverage/cover_reg_top/15.edn_intr_test.91673378 Mar 14 12:28:29 PM PDT 24 Mar 14 12:28:31 PM PDT 24 17717250 ps
T958 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3141192031 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 53704550 ps
T959 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.779507976 Mar 14 12:28:14 PM PDT 24 Mar 14 12:28:15 PM PDT 24 160185125 ps
T960 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3797983815 Mar 14 12:28:47 PM PDT 24 Mar 14 12:28:50 PM PDT 24 105479709 ps
T961 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2163178250 Mar 14 12:28:16 PM PDT 24 Mar 14 12:28:19 PM PDT 24 115662511 ps
T230 /workspace/coverage/cover_reg_top/18.edn_csr_rw.759745785 Mar 14 12:28:25 PM PDT 24 Mar 14 12:28:31 PM PDT 24 47699150 ps
T962 /workspace/coverage/cover_reg_top/10.edn_intr_test.3088198909 Mar 14 12:28:23 PM PDT 24 Mar 14 12:28:24 PM PDT 24 20322502 ps
T963 /workspace/coverage/cover_reg_top/7.edn_intr_test.2173529638 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:38 PM PDT 24 16108821 ps
T964 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3063906720 Mar 14 12:28:18 PM PDT 24 Mar 14 12:28:20 PM PDT 24 27678794 ps
T965 /workspace/coverage/cover_reg_top/31.edn_intr_test.751574467 Mar 14 12:28:44 PM PDT 24 Mar 14 12:28:45 PM PDT 24 17130735 ps
T966 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.647718954 Mar 14 12:28:35 PM PDT 24 Mar 14 12:28:36 PM PDT 24 73812121 ps
T967 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4276473124 Mar 14 12:28:32 PM PDT 24 Mar 14 12:28:38 PM PDT 24 202500797 ps
T968 /workspace/coverage/cover_reg_top/29.edn_intr_test.3231965784 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:40 PM PDT 24 12423419 ps

Test location /workspace/coverage/default/62.edn_genbits.3936813314
Short name T24
Test name
Test status
Simulation time 101666324 ps
CPU time 1.09 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 216404 kb
Host smart-1f723e06-ecc7-4be7-899d-8889c509569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936813314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3936813314
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1670154431
Short name T27
Test name
Test status
Simulation time 675981109061 ps
CPU time 1888.31 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 01:20:07 PM PDT 24
Peak memory 224128 kb
Host smart-bcecc81f-7f26-45ed-a7ec-32a03456e79f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670154431 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1670154431
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3571263250
Short name T20
Test name
Test status
Simulation time 642556657 ps
CPU time 3.12 seconds
Started Mar 14 12:48:20 PM PDT 24
Finished Mar 14 12:48:23 PM PDT 24
Peak memory 235548 kb
Host smart-00557668-dfb8-48c3-abbf-81c30108eccc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571263250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3571263250
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/131.edn_genbits.3204498466
Short name T9
Test name
Test status
Simulation time 82116081 ps
CPU time 1.17 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 217744 kb
Host smart-4d139cdf-14e4-48f4-a117-8b22a30d5793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204498466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3204498466
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_alert.2435030943
Short name T17
Test name
Test status
Simulation time 76297224 ps
CPU time 1.13 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 215212 kb
Host smart-2c8bf72b-6db0-4488-a36e-314296b86810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435030943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2435030943
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/41.edn_disable.680871710
Short name T56
Test name
Test status
Simulation time 16104170 ps
CPU time 0.84 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 215460 kb
Host smart-b5ad809e-90b1-43f5-9f1a-081bdeba7594
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680871710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.680871710
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/94.edn_err.2065000580
Short name T6
Test name
Test status
Simulation time 92955543 ps
CPU time 1.24 seconds
Started Mar 14 12:49:54 PM PDT 24
Finished Mar 14 12:49:56 PM PDT 24
Peak memory 233084 kb
Host smart-50ee53e2-1c8f-47e9-b5a1-1ce8250a39c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065000580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2065000580
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/33.edn_alert.1949253861
Short name T18
Test name
Test status
Simulation time 73139949 ps
CPU time 1.21 seconds
Started Mar 14 12:49:20 PM PDT 24
Finished Mar 14 12:49:21 PM PDT 24
Peak memory 215200 kb
Host smart-607f9f29-867e-434e-a842-2fbd54244cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949253861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1949253861
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.373877536
Short name T81
Test name
Test status
Simulation time 57177857 ps
CPU time 1.21 seconds
Started Mar 14 12:49:31 PM PDT 24
Finished Mar 14 12:49:33 PM PDT 24
Peak memory 218316 kb
Host smart-62fb639d-dfe8-4a61-9726-bc9b0d41719b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373877536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.373877536
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.804775724
Short name T193
Test name
Test status
Simulation time 50288457546 ps
CPU time 641.21 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 01:00:12 PM PDT 24
Peak memory 217884 kb
Host smart-09fd4aa5-8aba-4e85-8347-7bcef24cc9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804775724 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.804775724
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1509271368
Short name T19
Test name
Test status
Simulation time 23762787 ps
CPU time 1.13 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 12:49:19 PM PDT 24
Peak memory 215244 kb
Host smart-a4910bec-3779-4adc-8d56-5c61c60925a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509271368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1509271368
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/24.edn_intr.2769383163
Short name T52
Test name
Test status
Simulation time 25157321 ps
CPU time 0.96 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:04 PM PDT 24
Peak memory 215408 kb
Host smart-c8ee8466-fd7d-4848-8e16-d7eee1d626ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769383163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2769383163
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3167658382
Short name T267
Test name
Test status
Simulation time 27770367 ps
CPU time 0.84 seconds
Started Mar 14 12:48:30 PM PDT 24
Finished Mar 14 12:48:31 PM PDT 24
Peak memory 206760 kb
Host smart-c457571e-c402-41fd-a0b4-1aefda95309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167658382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3167658382
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4020200023
Short name T252
Test name
Test status
Simulation time 90598129 ps
CPU time 2.46 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206052 kb
Host smart-31c37e79-247a-4645-aa2e-ab72e7961131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020200023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4020200023
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/default/225.edn_genbits.766375676
Short name T182
Test name
Test status
Simulation time 89136730 ps
CPU time 2.93 seconds
Started Mar 14 12:50:24 PM PDT 24
Finished Mar 14 12:50:28 PM PDT 24
Peak memory 214996 kb
Host smart-f72e7977-f347-433a-a55c-02a3b743150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766375676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.766375676
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1580269732
Short name T214
Test name
Test status
Simulation time 120422985 ps
CPU time 0.81 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 205800 kb
Host smart-7bbde759-953b-4bc1-827a-e355c633e41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580269732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1580269732
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/default/22.edn_alert.2698764144
Short name T66
Test name
Test status
Simulation time 27093238 ps
CPU time 1.2 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 215200 kb
Host smart-59486299-9d32-4ac1-b301-5c50bbc7924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698764144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2698764144
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/49.edn_disable.3291008931
Short name T103
Test name
Test status
Simulation time 39909206 ps
CPU time 0.91 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 215388 kb
Host smart-807324e3-286b-4453-ba7c-2472fc53d303
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291008931 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3291008931
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1887814240
Short name T88
Test name
Test status
Simulation time 45657944 ps
CPU time 1.41 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 216152 kb
Host smart-705bed50-ddd0-43ae-9d45-fabae5dc71a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887814240 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1887814240
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable.2951612493
Short name T152
Test name
Test status
Simulation time 68140675 ps
CPU time 0.87 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 215280 kb
Host smart-7322df18-2672-4d1c-93b7-dc77f48d1bd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951612493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2951612493
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4223488418
Short name T150
Test name
Test status
Simulation time 66252976 ps
CPU time 1.11 seconds
Started Mar 14 12:48:42 PM PDT 24
Finished Mar 14 12:48:43 PM PDT 24
Peak memory 216032 kb
Host smart-813261e3-fc24-42b3-8b9d-16d84e2ad4f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223488418 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4223488418
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2285101598
Short name T43
Test name
Test status
Simulation time 33348241 ps
CPU time 0.94 seconds
Started Mar 14 12:48:50 PM PDT 24
Finished Mar 14 12:48:51 PM PDT 24
Peak memory 231984 kb
Host smart-f9891d45-eeeb-47f3-a5b4-96a12ce463a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285101598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2285101598
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/150.edn_genbits.726485457
Short name T50
Test name
Test status
Simulation time 128907114 ps
CPU time 1.5 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217980 kb
Host smart-2739059d-cde9-4ce2-887c-705f5d99ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726485457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.726485457
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.690892259
Short name T142
Test name
Test status
Simulation time 21027348 ps
CPU time 1.02 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 215364 kb
Host smart-b8cf0f4f-2b3f-4d37-b674-cef2db9c37e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690892259 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.690892259
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/38.edn_alert_test.1041031920
Short name T40
Test name
Test status
Simulation time 16567060 ps
CPU time 0.92 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 206512 kb
Host smart-86b07f32-85f2-4ba8-b77c-18237e488dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041031920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1041031920
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_alert.2659237397
Short name T486
Test name
Test status
Simulation time 28072299 ps
CPU time 1.19 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 215260 kb
Host smart-a46c734f-3274-4e3f-8459-64e3532188a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659237397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2659237397
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1554324849
Short name T94
Test name
Test status
Simulation time 71573145 ps
CPU time 1.34 seconds
Started Mar 14 12:49:22 PM PDT 24
Finished Mar 14 12:49:24 PM PDT 24
Peak memory 215892 kb
Host smart-9cd65752-63da-4b3d-ab37-f0d33a44a7a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554324849 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1554324849
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/78.edn_genbits.263520539
Short name T10
Test name
Test status
Simulation time 104648901 ps
CPU time 2.51 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 218116 kb
Host smart-6707fc88-9bd6-4e46-9105-565fa742b887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263520539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.263520539
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_disable.2999760566
Short name T186
Test name
Test status
Simulation time 20027855 ps
CPU time 0.86 seconds
Started Mar 14 12:49:01 PM PDT 24
Finished Mar 14 12:49:02 PM PDT 24
Peak memory 215008 kb
Host smart-29a33842-7cbf-4efa-80f1-91b2914857a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999760566 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2999760566
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable.3870388445
Short name T178
Test name
Test status
Simulation time 45067342 ps
CPU time 0.85 seconds
Started Mar 14 12:49:31 PM PDT 24
Finished Mar 14 12:49:32 PM PDT 24
Peak memory 215420 kb
Host smart-222d076f-1f52-44da-9942-ed83889b0ee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870388445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3870388445
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/26.edn_intr.2913505304
Short name T134
Test name
Test status
Simulation time 22462219 ps
CPU time 0.92 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 215276 kb
Host smart-ae0e87ff-332c-4d3e-be33-353f967668fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913505304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2913505304
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.3629284727
Short name T146
Test name
Test status
Simulation time 11160344 ps
CPU time 0.84 seconds
Started Mar 14 12:48:36 PM PDT 24
Finished Mar 14 12:48:37 PM PDT 24
Peak memory 215284 kb
Host smart-68175d1e-252f-48a2-8b86-ee924fdd0390
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629284727 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3629284727
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1410582518
Short name T76
Test name
Test status
Simulation time 105419431 ps
CPU time 1.14 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 216112 kb
Host smart-5218c021-a5e2-4ecb-8bc2-7bbf68cb1d36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410582518 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1410582518
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.2310586762
Short name T766
Test name
Test status
Simulation time 9992926 ps
CPU time 0.84 seconds
Started Mar 14 12:48:55 PM PDT 24
Finished Mar 14 12:48:57 PM PDT 24
Peak memory 215436 kb
Host smart-6e0b1306-781c-4f38-a817-607e577dacb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310586762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2310586762
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.406957401
Short name T89
Test name
Test status
Simulation time 101086650 ps
CPU time 1.19 seconds
Started Mar 14 12:49:05 PM PDT 24
Finished Mar 14 12:49:07 PM PDT 24
Peak memory 216164 kb
Host smart-52a838a4-cf78-41db-9855-188ed7e2ba03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406957401 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.406957401
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_genbits.3763077684
Short name T244
Test name
Test status
Simulation time 37613798 ps
CPU time 1.31 seconds
Started Mar 14 12:48:52 PM PDT 24
Finished Mar 14 12:48:54 PM PDT 24
Peak memory 218788 kb
Host smart-d0624f36-d2e4-40ad-b3de-3029a208442f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763077684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3763077684
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2567109506
Short name T250
Test name
Test status
Simulation time 101445271 ps
CPU time 1.61 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216544 kb
Host smart-8f299b26-c201-4a13-aa17-a8eb49633556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567109506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2567109506
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_genbits.857357373
Short name T299
Test name
Test status
Simulation time 68370719 ps
CPU time 2.09 seconds
Started Mar 14 12:49:41 PM PDT 24
Finished Mar 14 12:49:43 PM PDT 24
Peak memory 218708 kb
Host smart-93b736b3-358b-4359-9ca6-cec79d2ee1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857357373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.857357373
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.826060896
Short name T28
Test name
Test status
Simulation time 57484956916 ps
CPU time 605 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:58:30 PM PDT 24
Peak memory 223236 kb
Host smart-4a1c90f7-f3b0-4bcd-affb-852451ac5040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826060896 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.826060896
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_regwen.450678261
Short name T126
Test name
Test status
Simulation time 30580362 ps
CPU time 0.95 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206620 kb
Host smart-a7d40073-83e3-41a4-b3c1-bbb4d714afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450678261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.450678261
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_stress_all.2908622621
Short name T713
Test name
Test status
Simulation time 131290972 ps
CPU time 1.51 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 216244 kb
Host smart-77741316-2197-47be-b342-b3897bb74a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908622621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2908622621
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/114.edn_genbits.831954702
Short name T286
Test name
Test status
Simulation time 61356364 ps
CPU time 1.29 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 217784 kb
Host smart-d9669b9d-be7b-4056-8ca2-513c71de294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831954702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.831954702
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1233990952
Short name T64
Test name
Test status
Simulation time 83889651 ps
CPU time 1.25 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 215244 kb
Host smart-b0208e51-9a1a-44d5-95a6-f53c5952e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233990952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1233990952
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/7.edn_regwen.1228234561
Short name T256
Test name
Test status
Simulation time 45697847 ps
CPU time 0.91 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206740 kb
Host smart-419820d6-1a0e-4ff6-91e1-fe9182dde77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228234561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1228234561
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/110.edn_genbits.2306435929
Short name T208
Test name
Test status
Simulation time 36819502 ps
CPU time 1.32 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 218664 kb
Host smart-5e3c62bb-7782-49dd-8dc7-9e7ec2b04446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306435929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2306435929
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3404854469
Short name T225
Test name
Test status
Simulation time 127360242 ps
CPU time 1.1 seconds
Started Mar 14 12:28:14 PM PDT 24
Finished Mar 14 12:28:15 PM PDT 24
Peak memory 206052 kb
Host smart-45fe6c48-b0a5-4753-8e51-d2c5cf75156f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404854469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3404854469
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/10.edn_genbits.3994195206
Short name T290
Test name
Test status
Simulation time 120199452 ps
CPU time 2.71 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 216528 kb
Host smart-c3af7a9d-6e85-4631-bf0a-00f01a27ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994195206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3994195206
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.4175643049
Short name T664
Test name
Test status
Simulation time 66237341 ps
CPU time 1.21 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216344 kb
Host smart-c80e2e00-0899-4c58-86b1-372b0ac5ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175643049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4175643049
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_genbits.2457156957
Short name T274
Test name
Test status
Simulation time 52024674 ps
CPU time 1.32 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:43 PM PDT 24
Peak memory 217896 kb
Host smart-71af56cc-4c20-4dcf-ba9b-35c14c5d6cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457156957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2457156957
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3413409241
Short name T814
Test name
Test status
Simulation time 77660664 ps
CPU time 1.15 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216232 kb
Host smart-8394f2d7-bd4c-43e2-b882-886cceed5fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413409241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3413409241
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all.3656478368
Short name T522
Test name
Test status
Simulation time 934014304 ps
CPU time 2.35 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 216168 kb
Host smart-d704fd27-83d1-4252-a12e-2a8d2394600c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656478368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3656478368
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/169.edn_genbits.2254642984
Short name T278
Test name
Test status
Simulation time 88724061 ps
CPU time 1.24 seconds
Started Mar 14 12:50:08 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 217696 kb
Host smart-2a7ade5c-a710-4099-9400-bfa445279edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254642984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2254642984
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1245203559
Short name T285
Test name
Test status
Simulation time 76801763 ps
CPU time 1.37 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217748 kb
Host smart-65edfe25-6554-461d-931b-5f2ac45369e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245203559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1245203559
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_alert.667872549
Short name T260
Test name
Test status
Simulation time 161784448 ps
CPU time 1.15 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:12 PM PDT 24
Peak memory 215168 kb
Host smart-e2f3441b-7a9b-4be0-9514-2855297e70a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667872549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.667872549
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/39.edn_genbits.3269095548
Short name T297
Test name
Test status
Simulation time 53882263 ps
CPU time 1.72 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 217348 kb
Host smart-a4149e2f-6f11-4c20-bc64-733fe1b32d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269095548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3269095548
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_genbits.2503989699
Short name T293
Test name
Test status
Simulation time 252783295 ps
CPU time 1.42 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 219128 kb
Host smart-3c7ab80a-1ec2-474b-b81c-66cd0293c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503989699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2503989699
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_genbits.1723134899
Short name T289
Test name
Test status
Simulation time 40330192 ps
CPU time 1.27 seconds
Started Mar 14 12:49:31 PM PDT 24
Finished Mar 14 12:49:32 PM PDT 24
Peak memory 216544 kb
Host smart-f534fbc3-385a-4c2d-b7f7-b2ea95704ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723134899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1723134899
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2974738264
Short name T143
Test name
Test status
Simulation time 67948014 ps
CPU time 0.84 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 215200 kb
Host smart-3b09f2c9-991c-4994-854d-ac266d8009c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974738264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2974738264
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/15.edn_disable.1536350620
Short name T670
Test name
Test status
Simulation time 18277019 ps
CPU time 0.81 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 215052 kb
Host smart-4a97f401-6a00-441e-ae89-98ac2de012e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536350620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1536350620
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/195.edn_genbits.912783205
Short name T631
Test name
Test status
Simulation time 40088612 ps
CPU time 1.63 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 216424 kb
Host smart-cc3eeb41-58b1-421f-89c3-5b0b0a47fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912783205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.912783205
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3922023451
Short name T226
Test name
Test status
Simulation time 217064332 ps
CPU time 3.05 seconds
Started Mar 14 12:28:12 PM PDT 24
Finished Mar 14 12:28:20 PM PDT 24
Peak memory 206068 kb
Host smart-f7cc1d5c-24ce-4ad9-9b4c-e78e2e3d5e4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922023451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3922023451
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1658496936
Short name T878
Test name
Test status
Simulation time 48282036 ps
CPU time 0.86 seconds
Started Mar 14 12:29:13 PM PDT 24
Finished Mar 14 12:29:14 PM PDT 24
Peak memory 205736 kb
Host smart-b41142db-541d-4ce2-b938-84fa953a5ec4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658496936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1658496936
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3529546404
Short name T881
Test name
Test status
Simulation time 52166785 ps
CPU time 1.43 seconds
Started Mar 14 12:28:15 PM PDT 24
Finished Mar 14 12:28:17 PM PDT 24
Peak memory 217344 kb
Host smart-a78e0b03-0c98-4486-8e04-bfa923bd7575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529546404 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3529546404
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2024376689
Short name T229
Test name
Test status
Simulation time 15838357 ps
CPU time 0.88 seconds
Started Mar 14 12:28:11 PM PDT 24
Finished Mar 14 12:28:12 PM PDT 24
Peak memory 205976 kb
Host smart-8d032c79-498c-4fdf-9488-06a066c53f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024376689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2024376689
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1315041694
Short name T866
Test name
Test status
Simulation time 41106929 ps
CPU time 0.79 seconds
Started Mar 14 12:28:18 PM PDT 24
Finished Mar 14 12:28:20 PM PDT 24
Peak memory 205868 kb
Host smart-67176d79-6630-4c58-82e3-1a378182e224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315041694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1315041694
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.13358279
Short name T231
Test name
Test status
Simulation time 35671251 ps
CPU time 1.41 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 206312 kb
Host smart-ed593062-8cbe-48ec-9d0c-a7645e7a416a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13358279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs
tanding.13358279
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4141241738
Short name T908
Test name
Test status
Simulation time 446985845 ps
CPU time 4.02 seconds
Started Mar 14 12:28:02 PM PDT 24
Finished Mar 14 12:28:06 PM PDT 24
Peak memory 214360 kb
Host smart-924a9375-e5e8-4825-a244-6f4147b325c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141241738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4141241738
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2156524510
Short name T254
Test name
Test status
Simulation time 93830138 ps
CPU time 2.38 seconds
Started Mar 14 12:29:16 PM PDT 24
Finished Mar 14 12:29:19 PM PDT 24
Peak memory 206232 kb
Host smart-485321d5-58ff-4e04-a59b-ae7fee593d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156524510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2156524510
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.409002700
Short name T218
Test name
Test status
Simulation time 61134528 ps
CPU time 1.42 seconds
Started Mar 14 12:28:18 PM PDT 24
Finished Mar 14 12:28:20 PM PDT 24
Peak memory 206120 kb
Host smart-99538d46-149a-4fab-addc-2f6f8be791b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409002700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.409002700
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2521921959
Short name T907
Test name
Test status
Simulation time 422285037 ps
CPU time 5 seconds
Started Mar 14 12:28:32 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206076 kb
Host smart-2fef15ee-403b-4018-a08e-e4746348ee2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521921959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2521921959
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.206042704
Short name T228
Test name
Test status
Simulation time 15416861 ps
CPU time 0.91 seconds
Started Mar 14 12:28:11 PM PDT 24
Finished Mar 14 12:28:12 PM PDT 24
Peak memory 206020 kb
Host smart-4648f16e-7ee3-4a9a-84e5-08bd8ac4bf26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206042704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.206042704
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4051047407
Short name T950
Test name
Test status
Simulation time 26369623 ps
CPU time 1.27 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:33 PM PDT 24
Peak memory 214492 kb
Host smart-c302eee9-f165-4963-905e-b04d5139ae25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051047407 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4051047407
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3390022255
Short name T927
Test name
Test status
Simulation time 22621804 ps
CPU time 0.85 seconds
Started Mar 14 12:28:13 PM PDT 24
Finished Mar 14 12:28:14 PM PDT 24
Peak memory 206056 kb
Host smart-a8da8c33-98fc-4c34-a1ae-74831b6b6a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390022255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3390022255
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3940431669
Short name T912
Test name
Test status
Simulation time 22270634 ps
CPU time 0.82 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 206036 kb
Host smart-75c279f8-4723-4305-8f39-3ac994bfca4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940431669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3940431669
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1736673696
Short name T219
Test name
Test status
Simulation time 180453052 ps
CPU time 1.01 seconds
Started Mar 14 12:28:28 PM PDT 24
Finished Mar 14 12:28:29 PM PDT 24
Peak memory 206344 kb
Host smart-e0d07c79-ede8-4be7-b99d-b1f728b72f3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736673696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1736673696
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1814635409
Short name T949
Test name
Test status
Simulation time 417993690 ps
CPU time 3.65 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 214576 kb
Host smart-442cd956-f7fd-4ea3-b1de-c4a1320cfb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814635409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1814635409
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.560474979
Short name T909
Test name
Test status
Simulation time 59028857 ps
CPU time 1.65 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 206156 kb
Host smart-3b88b9b5-6bac-4858-9ce3-8be17739a7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560474979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.560474979
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3668729312
Short name T874
Test name
Test status
Simulation time 33001834 ps
CPU time 1.94 seconds
Started Mar 14 12:28:19 PM PDT 24
Finished Mar 14 12:28:21 PM PDT 24
Peak memory 214416 kb
Host smart-1a0f4f29-6c24-4656-8b31-4a1a9661e236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668729312 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3668729312
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.510163096
Short name T893
Test name
Test status
Simulation time 24730692 ps
CPU time 0.84 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 206020 kb
Host smart-833adf41-1714-4b19-9524-0cbd6524c4fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510163096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.510163096
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3088198909
Short name T962
Test name
Test status
Simulation time 20322502 ps
CPU time 0.79 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 205876 kb
Host smart-dedbee53-e565-4ac1-9c50-5e3f1e35047b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088198909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3088198909
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3023316159
Short name T939
Test name
Test status
Simulation time 14449164 ps
CPU time 0.95 seconds
Started Mar 14 12:28:17 PM PDT 24
Finished Mar 14 12:28:19 PM PDT 24
Peak memory 206264 kb
Host smart-93c04829-03ae-4207-8c2f-882403811e91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023316159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3023316159
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3758570208
Short name T864
Test name
Test status
Simulation time 98879772 ps
CPU time 2.56 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 214556 kb
Host smart-74433a5c-119f-4071-9008-5159c618f058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758570208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3758570208
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.829527267
Short name T934
Test name
Test status
Simulation time 102038887 ps
CPU time 1.64 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 206200 kb
Host smart-f8ae22be-1e86-4d8d-b277-f412dcbee2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829527267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.829527267
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3142451002
Short name T845
Test name
Test status
Simulation time 194683557 ps
CPU time 2.11 seconds
Started Mar 14 12:28:28 PM PDT 24
Finished Mar 14 12:28:30 PM PDT 24
Peak memory 214464 kb
Host smart-9e6667a4-b65c-4486-b48f-b8ba01b58eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142451002 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3142451002
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3209714744
Short name T222
Test name
Test status
Simulation time 12989101 ps
CPU time 0.85 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 206116 kb
Host smart-f787f28f-661c-4a09-8093-00a884d8ab7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209714744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3209714744
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1503177129
Short name T882
Test name
Test status
Simulation time 19715055 ps
CPU time 0.79 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 205800 kb
Host smart-04a86bb5-1480-4045-8d74-18ca3966aeca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503177129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1503177129
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1871663092
Short name T911
Test name
Test status
Simulation time 119372654 ps
CPU time 1.35 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 206300 kb
Host smart-03bc93fd-964e-4fe4-a799-ba906416a544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871663092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1871663092
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1751021913
Short name T951
Test name
Test status
Simulation time 35597530 ps
CPU time 1.23 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 214452 kb
Host smart-fc66378b-a123-4364-be8c-32e7e4b3c493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751021913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1751021913
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1142717023
Short name T910
Test name
Test status
Simulation time 78496576 ps
CPU time 2.17 seconds
Started Mar 14 12:28:18 PM PDT 24
Finished Mar 14 12:28:21 PM PDT 24
Peak memory 206188 kb
Host smart-050dfa3c-944e-4fde-9758-ab9a2e504fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142717023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1142717023
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.27233259
Short name T839
Test name
Test status
Simulation time 20810598 ps
CPU time 1.36 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:33 PM PDT 24
Peak memory 214524 kb
Host smart-7bb1cde7-f4e7-45e1-95c3-139364868697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233259 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.27233259
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.672968252
Short name T223
Test name
Test status
Simulation time 36560894 ps
CPU time 0.81 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 205836 kb
Host smart-813f2272-aaa5-4d7e-be54-c6ba63a88900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672968252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.672968252
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.96915140
Short name T879
Test name
Test status
Simulation time 37897261 ps
CPU time 0.82 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 205868 kb
Host smart-fc02a714-6726-4c7b-9ebe-325458273725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96915140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.96915140
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.142573323
Short name T938
Test name
Test status
Simulation time 23005094 ps
CPU time 1 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206252 kb
Host smart-252ef032-4e4a-409d-8245-e45fdead7a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142573323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.142573323
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3654733490
Short name T842
Test name
Test status
Simulation time 221094250 ps
CPU time 3.57 seconds
Started Mar 14 12:28:19 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 214596 kb
Host smart-7a59c4a6-daa7-4cf4-9eb6-4318c195a293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654733490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3654733490
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1615739861
Short name T885
Test name
Test status
Simulation time 163075795 ps
CPU time 2.24 seconds
Started Mar 14 12:28:17 PM PDT 24
Finished Mar 14 12:28:19 PM PDT 24
Peak memory 206284 kb
Host smart-3ebbb439-bbc4-4487-8ab2-1c446f13612a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615739861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1615739861
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3846225804
Short name T887
Test name
Test status
Simulation time 45939392 ps
CPU time 1.16 seconds
Started Mar 14 12:28:32 PM PDT 24
Finished Mar 14 12:28:34 PM PDT 24
Peak memory 214492 kb
Host smart-aa8b7135-9719-4fc0-a28d-786091a08aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846225804 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3846225804
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1054281132
Short name T234
Test name
Test status
Simulation time 24011542 ps
CPU time 0.82 seconds
Started Mar 14 12:28:28 PM PDT 24
Finished Mar 14 12:28:29 PM PDT 24
Peak memory 205968 kb
Host smart-21af174b-aea3-431f-9f1b-851dbbb50a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054281132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1054281132
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3389459327
Short name T915
Test name
Test status
Simulation time 14202468 ps
CPU time 0.86 seconds
Started Mar 14 12:28:21 PM PDT 24
Finished Mar 14 12:28:22 PM PDT 24
Peak memory 205992 kb
Host smart-6f0b7082-f978-411f-9198-e5242ac7d4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389459327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3389459327
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1848069110
Short name T940
Test name
Test status
Simulation time 30995455 ps
CPU time 1.04 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 206172 kb
Host smart-62f26b2b-f18c-4ee7-81f9-921d00854a36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848069110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1848069110
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2163178250
Short name T961
Test name
Test status
Simulation time 115662511 ps
CPU time 2.12 seconds
Started Mar 14 12:28:16 PM PDT 24
Finished Mar 14 12:28:19 PM PDT 24
Peak memory 214752 kb
Host smart-bc941b50-e7ad-43de-a525-739ff3387644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163178250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2163178250
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2769188977
Short name T902
Test name
Test status
Simulation time 181316856 ps
CPU time 1.95 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 206148 kb
Host smart-fbb636cd-ebec-4ff8-b3d4-b655c7fef90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769188977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2769188977
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3129691652
Short name T914
Test name
Test status
Simulation time 36424584 ps
CPU time 1.52 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 214484 kb
Host smart-afaf2471-ad32-4286-88ac-337265534b16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129691652 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3129691652
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1158319354
Short name T944
Test name
Test status
Simulation time 46948470 ps
CPU time 0.84 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206116 kb
Host smart-86d7ca72-ef27-483f-a0ff-4c6b8c0b2392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158319354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1158319354
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4271381055
Short name T872
Test name
Test status
Simulation time 22042449 ps
CPU time 0.8 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 206020 kb
Host smart-16b5759a-0436-411f-85c1-6f1d8467bfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271381055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4271381055
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1696219529
Short name T897
Test name
Test status
Simulation time 57780282 ps
CPU time 0.95 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 206280 kb
Host smart-a5a35af3-eb2e-4a2a-bdc3-2c4eb113ea7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696219529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1696219529
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2498913197
Short name T846
Test name
Test status
Simulation time 126375116 ps
CPU time 3.44 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 214504 kb
Host smart-7ee394cc-f193-4d1d-81f1-c08a36c599f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498913197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2498913197
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2850914061
Short name T917
Test name
Test status
Simulation time 166412159 ps
CPU time 2.36 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 206184 kb
Host smart-5a3424d3-6adc-44a0-adb9-6039a2fb45a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850914061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2850914061
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1630016926
Short name T928
Test name
Test status
Simulation time 57263716 ps
CPU time 1.39 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 214580 kb
Host smart-d6f59524-8a90-4bc7-8b38-5e72ef47e38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630016926 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1630016926
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2220560399
Short name T930
Test name
Test status
Simulation time 12637581 ps
CPU time 0.89 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 205984 kb
Host smart-5dec9f87-ea28-466a-b0fa-09304a14d791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220560399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2220560399
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.91673378
Short name T957
Test name
Test status
Simulation time 17717250 ps
CPU time 0.82 seconds
Started Mar 14 12:28:29 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 206052 kb
Host smart-2ea01d1b-0a36-4307-b25b-6441575bef37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91673378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.91673378
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3068375743
Short name T884
Test name
Test status
Simulation time 40374853 ps
CPU time 1.37 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:33 PM PDT 24
Peak memory 206236 kb
Host smart-010089e5-19b0-4adf-a52d-1f6dd68e4d10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068375743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3068375743
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.813672087
Short name T919
Test name
Test status
Simulation time 82964279 ps
CPU time 2.9 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 214468 kb
Host smart-467b7e55-d9a7-4ce8-8bcf-8e3de10c989e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813672087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.813672087
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3353336833
Short name T867
Test name
Test status
Simulation time 54590388 ps
CPU time 1.69 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 206248 kb
Host smart-2e8081b1-6b11-4ab4-a29c-d1299badcb18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353336833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3353336833
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2356854271
Short name T896
Test name
Test status
Simulation time 69214374 ps
CPU time 1.04 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 214416 kb
Host smart-ce8f58b1-e668-42ca-a71b-9cbdd4fdced3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356854271 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2356854271
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3490879391
Short name T891
Test name
Test status
Simulation time 13057467 ps
CPU time 0.84 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 206040 kb
Host smart-b976bf01-ff4c-417f-af8d-70ef899c02b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490879391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3490879391
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2565302257
Short name T935
Test name
Test status
Simulation time 11574979 ps
CPU time 0.81 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 206032 kb
Host smart-0d1442e3-d84a-4394-93b9-9b5696ac4fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565302257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2565302257
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.103474613
Short name T905
Test name
Test status
Simulation time 20367522 ps
CPU time 1.07 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:32 PM PDT 24
Peak memory 206212 kb
Host smart-f7c126a1-1fba-4c3d-8cc9-2b58a6df8f19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103474613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.103474613
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3587293820
Short name T854
Test name
Test status
Simulation time 233726397 ps
CPU time 3.22 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 214472 kb
Host smart-03db9806-f82b-49ff-9de3-00830017673e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587293820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3587293820
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.628703306
Short name T237
Test name
Test status
Simulation time 475677479 ps
CPU time 2.17 seconds
Started Mar 14 12:28:22 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 206152 kb
Host smart-39c81332-acb4-42a2-b48b-e2e5fb0539f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628703306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.628703306
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3017872934
Short name T926
Test name
Test status
Simulation time 20221794 ps
CPU time 1.03 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 214564 kb
Host smart-3bb8053f-a5b9-422d-b039-9e84b726d2c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017872934 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3017872934
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2814598110
Short name T224
Test name
Test status
Simulation time 66567065 ps
CPU time 0.83 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 206120 kb
Host smart-0c1a96c9-7769-4f06-86d4-5c4d50badfe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814598110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2814598110
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2440795895
Short name T858
Test name
Test status
Simulation time 51545557 ps
CPU time 0.87 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 206064 kb
Host smart-c4df7659-2777-407a-924f-e57e605d7634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440795895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2440795895
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3850232100
Short name T220
Test name
Test status
Simulation time 79560641 ps
CPU time 1.4 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206284 kb
Host smart-97214b86-a85a-4c58-9f46-d6525dfd5a07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850232100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3850232100
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4081867528
Short name T925
Test name
Test status
Simulation time 19640273 ps
CPU time 1.34 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 214428 kb
Host smart-cfc8f8fe-7096-475d-a965-deae14dd9d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081867528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4081867528
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2201254869
Short name T238
Test name
Test status
Simulation time 309337859 ps
CPU time 3.42 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 206200 kb
Host smart-b14bf970-f83f-4bd9-b202-07e07bbc50bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201254869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2201254869
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1719388106
Short name T942
Test name
Test status
Simulation time 37906497 ps
CPU time 1.05 seconds
Started Mar 14 12:28:20 PM PDT 24
Finished Mar 14 12:28:21 PM PDT 24
Peak memory 215584 kb
Host smart-058b5dac-6fe5-4f07-a746-ffee01e5d900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719388106 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1719388106
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.759745785
Short name T230
Test name
Test status
Simulation time 47699150 ps
CPU time 0.88 seconds
Started Mar 14 12:28:25 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 206120 kb
Host smart-d3b47904-e88e-491b-a36f-1c669ce82a28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759745785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.759745785
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2623809258
Short name T841
Test name
Test status
Simulation time 16086272 ps
CPU time 0.84 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 206032 kb
Host smart-1e9f676f-fecb-4700-b3df-a9eef713d9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623809258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2623809258
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3071557425
Short name T946
Test name
Test status
Simulation time 23119597 ps
CPU time 1.04 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 206200 kb
Host smart-8417bebe-a6fe-4545-85bd-c9fb65e47494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071557425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3071557425
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3266269770
Short name T868
Test name
Test status
Simulation time 260380477 ps
CPU time 4.12 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 214620 kb
Host smart-b7b7c2b6-2281-4408-8602-0601af75b150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266269770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3266269770
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3797983815
Short name T960
Test name
Test status
Simulation time 105479709 ps
CPU time 2.15 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 206148 kb
Host smart-57d43879-99ba-4fc1-876a-a58f9f9a14f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797983815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3797983815
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1172775421
Short name T876
Test name
Test status
Simulation time 153901951 ps
CPU time 0.97 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 214460 kb
Host smart-2fafb4b3-1714-4003-9e9d-34ab3fc8ee07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172775421 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1172775421
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3812745991
Short name T221
Test name
Test status
Simulation time 44668606 ps
CPU time 0.91 seconds
Started Mar 14 12:28:33 PM PDT 24
Finished Mar 14 12:28:34 PM PDT 24
Peak memory 206016 kb
Host smart-d195f01f-ac27-45d8-9ece-941a23139696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812745991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3812745991
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1899464011
Short name T880
Test name
Test status
Simulation time 31573590 ps
CPU time 0.91 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 206032 kb
Host smart-551bedde-c492-4d1b-a270-32d726fa1c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899464011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1899464011
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1693680196
Short name T862
Test name
Test status
Simulation time 139973918 ps
CPU time 1.35 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 206208 kb
Host smart-3ad372ee-cd06-4400-abb4-efdaaf4e8e69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693680196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1693680196
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1947566578
Short name T898
Test name
Test status
Simulation time 70714987 ps
CPU time 2.23 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 214528 kb
Host smart-d316617d-eb19-4fa9-9711-1f4a4645d2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947566578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1947566578
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1288717933
Short name T251
Test name
Test status
Simulation time 74785481 ps
CPU time 2.21 seconds
Started Mar 14 12:28:45 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 206220 kb
Host smart-d7640f6e-23a2-4759-bf23-5f3c64dea02d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288717933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1288717933
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4085764503
Short name T215
Test name
Test status
Simulation time 133821904 ps
CPU time 1.41 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 206124 kb
Host smart-84452a7a-4e7d-4ab3-9aa8-b90c7ba7d431
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085764503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4085764503
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1374239047
Short name T924
Test name
Test status
Simulation time 132454874 ps
CPU time 1.93 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 205976 kb
Host smart-e23c3f3b-c191-40ce-a56a-dc080b89ed52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374239047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1374239047
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3141192031
Short name T958
Test name
Test status
Simulation time 53704550 ps
CPU time 0.96 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 205992 kb
Host smart-ec8b1afa-9d6d-415a-bfb1-0198dc8ae039
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141192031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3141192031
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1766064308
Short name T833
Test name
Test status
Simulation time 57246345 ps
CPU time 1.11 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 214464 kb
Host smart-6f3c4c7c-0384-42a7-9290-4e4c28023bc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766064308 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1766064308
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1491058896
Short name T856
Test name
Test status
Simulation time 11932454 ps
CPU time 0.83 seconds
Started Mar 14 12:28:28 PM PDT 24
Finished Mar 14 12:28:29 PM PDT 24
Peak memory 206020 kb
Host smart-8f1b5ab6-142c-4e95-b363-49de00f619f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491058896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1491058896
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4240467473
Short name T848
Test name
Test status
Simulation time 24135230 ps
CPU time 0.86 seconds
Started Mar 14 12:28:30 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 206020 kb
Host smart-2110c435-36cb-43f4-96ad-1d9cbda071ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240467473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4240467473
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3963431258
Short name T877
Test name
Test status
Simulation time 37370346 ps
CPU time 1.04 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 206312 kb
Host smart-606cf0b5-8e43-4bc4-a1a6-71a6f0fde705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963431258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3963431258
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3772345753
Short name T843
Test name
Test status
Simulation time 75835420 ps
CPU time 1.64 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:26 PM PDT 24
Peak memory 214600 kb
Host smart-948e270d-95b6-4b65-b1d7-b2d72bc4d600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772345753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3772345753
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3637969285
Short name T236
Test name
Test status
Simulation time 124754234 ps
CPU time 1.99 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 206156 kb
Host smart-34d3fef7-dd6a-4ddb-8f30-fce2dd28b39d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637969285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3637969285
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1375764564
Short name T888
Test name
Test status
Simulation time 46531912 ps
CPU time 0.81 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 206064 kb
Host smart-42c28d03-33e4-4371-974b-161b728d1181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375764564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1375764564
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1740651979
Short name T873
Test name
Test status
Simulation time 24845414 ps
CPU time 0.85 seconds
Started Mar 14 12:28:21 PM PDT 24
Finished Mar 14 12:28:22 PM PDT 24
Peak memory 205984 kb
Host smart-fe1b6c5a-44ff-4341-b852-f5e3c36d2b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740651979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1740651979
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.276453321
Short name T953
Test name
Test status
Simulation time 22532047 ps
CPU time 0.83 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 206028 kb
Host smart-b925ea49-9856-46f9-9fcc-d0c0c684ecb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276453321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.276453321
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2508960607
Short name T936
Test name
Test status
Simulation time 35033162 ps
CPU time 0.77 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 205860 kb
Host smart-e629932b-6e69-417f-ab92-8d07a6c53ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508960607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2508960607
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1643356038
Short name T955
Test name
Test status
Simulation time 27349269 ps
CPU time 0.87 seconds
Started Mar 14 12:28:49 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 206016 kb
Host smart-fc539385-ebd0-4d6d-ab9a-cec5806742df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643356038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1643356038
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2269747302
Short name T852
Test name
Test status
Simulation time 35210359 ps
CPU time 0.79 seconds
Started Mar 14 12:28:27 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 205808 kb
Host smart-04b8c531-8ef4-479f-9aec-b02c475bf209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269747302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2269747302
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.40175605
Short name T904
Test name
Test status
Simulation time 30794929 ps
CPU time 0.86 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 205996 kb
Host smart-a09516f7-5eb3-41de-b19c-5dff4277729f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.40175605
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3153072967
Short name T941
Test name
Test status
Simulation time 38212646 ps
CPU time 0.84 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 205924 kb
Host smart-43bc3ae2-4127-4f7a-aa09-7e1d42dd8bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153072967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3153072967
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3642371198
Short name T922
Test name
Test status
Simulation time 44656579 ps
CPU time 0.85 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 206044 kb
Host smart-1cdb2f64-5c6a-44d6-94bf-56a099217b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642371198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3642371198
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3231965784
Short name T968
Test name
Test status
Simulation time 12423419 ps
CPU time 0.81 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 206136 kb
Host smart-b4d8d263-96be-4673-8d70-89d3eea36b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231965784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3231965784
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3483428751
Short name T894
Test name
Test status
Simulation time 86057779 ps
CPU time 1.1 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 206040 kb
Host smart-c6fe5b4c-c43d-49c5-88b9-91492fab5f0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483428751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3483428751
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.626259702
Short name T948
Test name
Test status
Simulation time 349615726 ps
CPU time 5 seconds
Started Mar 14 12:28:17 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 206060 kb
Host smart-01e43455-7c35-4d3a-9b11-c17185f980c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626259702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.626259702
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1254263812
Short name T903
Test name
Test status
Simulation time 24468958 ps
CPU time 0.82 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 206104 kb
Host smart-b72dddf6-3236-45c0-bb3e-0185b06edacb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254263812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1254263812
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2611253079
Short name T835
Test name
Test status
Simulation time 188548527 ps
CPU time 1.47 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 214428 kb
Host smart-d8eb62a8-1a07-47de-aafc-a6289936aa6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611253079 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2611253079
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3232008283
Short name T216
Test name
Test status
Simulation time 32211990 ps
CPU time 0.79 seconds
Started Mar 14 12:28:22 PM PDT 24
Finished Mar 14 12:28:23 PM PDT 24
Peak memory 205836 kb
Host smart-62d07fcd-655f-4acc-b4bc-6481cd4c116b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232008283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3232008283
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2725567530
Short name T847
Test name
Test status
Simulation time 52165016 ps
CPU time 0.78 seconds
Started Mar 14 12:28:06 PM PDT 24
Finished Mar 14 12:28:07 PM PDT 24
Peak memory 205888 kb
Host smart-e207aabd-60bf-4ec3-ad88-76f40c246e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725567530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2725567530
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1945579488
Short name T929
Test name
Test status
Simulation time 81887479 ps
CPU time 0.99 seconds
Started Mar 14 12:28:14 PM PDT 24
Finished Mar 14 12:28:15 PM PDT 24
Peak memory 206260 kb
Host smart-e0163025-94cc-4c4e-a0e0-87027ff250ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945579488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1945579488
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2251328478
Short name T931
Test name
Test status
Simulation time 372684669 ps
CPU time 3.39 seconds
Started Mar 14 12:28:21 PM PDT 24
Finished Mar 14 12:28:25 PM PDT 24
Peak memory 214432 kb
Host smart-6f287de7-68ef-49ea-a350-bac7fce281d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251328478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2251328478
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3284645032
Short name T943
Test name
Test status
Simulation time 190797210 ps
CPU time 2 seconds
Started Mar 14 12:28:28 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 206172 kb
Host smart-56d2351c-ce58-439d-b5b4-ff83166eaf0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284645032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3284645032
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.523641991
Short name T895
Test name
Test status
Simulation time 39601561 ps
CPU time 0.73 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 205756 kb
Host smart-eb761147-5819-4c2b-b5fb-a4fd077fe923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523641991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.523641991
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.751574467
Short name T965
Test name
Test status
Simulation time 17130735 ps
CPU time 0.86 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 206060 kb
Host smart-3f2ecf5c-cf99-4a3e-9ebf-ef6a7a2bb123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751574467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.751574467
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2401892914
Short name T921
Test name
Test status
Simulation time 47909655 ps
CPU time 0.82 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:32 PM PDT 24
Peak memory 206004 kb
Host smart-48996ef1-8006-482a-923c-48a066213366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401892914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2401892914
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2105354096
Short name T857
Test name
Test status
Simulation time 43608032 ps
CPU time 0.75 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 205964 kb
Host smart-24638bea-5aba-4608-a26a-0e92f03eadb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105354096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2105354096
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1828098696
Short name T923
Test name
Test status
Simulation time 15102751 ps
CPU time 0.89 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 206136 kb
Host smart-48c2091b-1bf8-4bad-83f7-b023ac56a509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828098696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1828098696
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1687110813
Short name T932
Test name
Test status
Simulation time 15942761 ps
CPU time 0.88 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 205968 kb
Host smart-02c5e7c3-0154-4960-9585-32251aa7dd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687110813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1687110813
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4072351401
Short name T899
Test name
Test status
Simulation time 26892973 ps
CPU time 0.87 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 206004 kb
Host smart-a05751b7-d089-4571-afa0-fb3254a8e341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072351401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4072351401
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3655619568
Short name T865
Test name
Test status
Simulation time 88559239 ps
CPU time 0.83 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:32 PM PDT 24
Peak memory 205868 kb
Host smart-408844bb-42c1-416c-9292-7602efca9eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655619568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3655619568
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1294939021
Short name T840
Test name
Test status
Simulation time 16020246 ps
CPU time 0.81 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 206032 kb
Host smart-b668784f-bac9-476b-bfc9-2cbd3e4d6637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294939021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1294939021
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.608027326
Short name T889
Test name
Test status
Simulation time 25649898 ps
CPU time 0.9 seconds
Started Mar 14 12:28:18 PM PDT 24
Finished Mar 14 12:28:20 PM PDT 24
Peak memory 205976 kb
Host smart-f1384315-b98e-4790-b527-885cad1c0d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608027326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.608027326
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.496066378
Short name T227
Test name
Test status
Simulation time 132490484 ps
CPU time 1.42 seconds
Started Mar 14 12:28:10 PM PDT 24
Finished Mar 14 12:28:12 PM PDT 24
Peak memory 206100 kb
Host smart-13cc4b59-4588-440d-9a85-4c2ec823c27e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496066378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.496066378
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4276473124
Short name T967
Test name
Test status
Simulation time 202500797 ps
CPU time 5.04 seconds
Started Mar 14 12:28:32 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 206124 kb
Host smart-92cdf715-7091-46f1-9060-2f9019c04db9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276473124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4276473124
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1097468665
Short name T956
Test name
Test status
Simulation time 15819960 ps
CPU time 0.89 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:32 PM PDT 24
Peak memory 206012 kb
Host smart-173d4399-187a-481d-be5a-aa3c5b151a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097468665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1097468665
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2740877718
Short name T869
Test name
Test status
Simulation time 17114797 ps
CPU time 1 seconds
Started Mar 14 12:28:13 PM PDT 24
Finished Mar 14 12:28:14 PM PDT 24
Peak memory 206208 kb
Host smart-a0438412-425d-4d8d-9e4a-abeb59710f49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740877718 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2740877718
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3276770231
Short name T235
Test name
Test status
Simulation time 14864042 ps
CPU time 0.91 seconds
Started Mar 14 12:28:17 PM PDT 24
Finished Mar 14 12:28:18 PM PDT 24
Peak memory 206072 kb
Host smart-b7686855-5a13-46d4-9bbb-f165e4a6c15c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276770231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3276770231
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3747679058
Short name T844
Test name
Test status
Simulation time 61183752 ps
CPU time 0.77 seconds
Started Mar 14 12:28:25 PM PDT 24
Finished Mar 14 12:28:26 PM PDT 24
Peak memory 205948 kb
Host smart-eaab5957-edfa-48c3-8189-645d1aa1c69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747679058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3747679058
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.325293075
Short name T232
Test name
Test status
Simulation time 54259742 ps
CPU time 0.9 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 206232 kb
Host smart-490a6b02-aabf-424c-98df-08f0825f2267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325293075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.325293075
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1673005233
Short name T834
Test name
Test status
Simulation time 22208632 ps
CPU time 1.35 seconds
Started Mar 14 12:28:33 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 214528 kb
Host smart-7d798b43-8063-48fc-a032-017e8b60ca59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673005233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1673005233
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1305090996
Short name T859
Test name
Test status
Simulation time 71435793 ps
CPU time 2.13 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 206232 kb
Host smart-f0ab4a37-c65e-47f2-9a26-c3e5329bbdbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305090996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1305090996
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.753502616
Short name T947
Test name
Test status
Simulation time 13694727 ps
CPU time 0.86 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 205984 kb
Host smart-6fc7ea64-9e6f-4174-a3f1-f45ea8452d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753502616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.753502616
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1004575436
Short name T890
Test name
Test status
Simulation time 37677875 ps
CPU time 0.81 seconds
Started Mar 14 12:28:30 PM PDT 24
Finished Mar 14 12:28:30 PM PDT 24
Peak memory 206008 kb
Host smart-6d749765-287a-4639-b147-1745f36b0088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004575436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1004575436
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2089593025
Short name T892
Test name
Test status
Simulation time 20984889 ps
CPU time 0.81 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206116 kb
Host smart-4103c2e0-6a03-48ad-a294-8f44c81c599c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089593025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2089593025
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.146578292
Short name T954
Test name
Test status
Simulation time 22623754 ps
CPU time 0.81 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 206108 kb
Host smart-f9de67e7-75d6-49c5-91a9-392122ecb9ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146578292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.146578292
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2969570179
Short name T933
Test name
Test status
Simulation time 17285260 ps
CPU time 0.9 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206108 kb
Host smart-4b4c230c-b379-411d-a044-2ced3abc1b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969570179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2969570179
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1038274869
Short name T900
Test name
Test status
Simulation time 14497795 ps
CPU time 0.83 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 206108 kb
Host smart-5c29e60b-957b-4d74-91df-6889e95f72d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038274869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1038274869
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3896255234
Short name T851
Test name
Test status
Simulation time 121358965 ps
CPU time 0.87 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 206028 kb
Host smart-b0c7f00c-54a4-43fb-a36f-fe9b3dae0957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896255234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3896255234
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1721237484
Short name T855
Test name
Test status
Simulation time 11514784 ps
CPU time 0.82 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 206028 kb
Host smart-d326b4ee-2e25-4237-87f0-a1de4a57879b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721237484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1721237484
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3729219774
Short name T883
Test name
Test status
Simulation time 15362345 ps
CPU time 0.79 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 205688 kb
Host smart-88d2353a-6247-491a-ae27-8a267a11d08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729219774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3729219774
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2249254065
Short name T937
Test name
Test status
Simulation time 17101134 ps
CPU time 0.78 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 206044 kb
Host smart-4067930e-7dab-4139-a072-226585470081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249254065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2249254065
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.449047450
Short name T945
Test name
Test status
Simulation time 85263469 ps
CPU time 1.46 seconds
Started Mar 14 12:28:21 PM PDT 24
Finished Mar 14 12:28:23 PM PDT 24
Peak memory 216780 kb
Host smart-32ec8d3e-09fc-479d-a599-4b30c9d6952c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449047450 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.449047450
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3853347762
Short name T886
Test name
Test status
Simulation time 24197114 ps
CPU time 0.86 seconds
Started Mar 14 12:28:22 PM PDT 24
Finished Mar 14 12:28:23 PM PDT 24
Peak memory 205976 kb
Host smart-13e8d5e8-944a-42d9-9bd5-5f1c70759797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853347762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3853347762
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.690106373
Short name T850
Test name
Test status
Simulation time 65911514 ps
CPU time 0.82 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 206060 kb
Host smart-9c01886a-13e2-46c3-a165-56c3a7e7ff1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690106373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.690106373
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.66170156
Short name T906
Test name
Test status
Simulation time 23690317 ps
CPU time 1 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 206100 kb
Host smart-81a1c65d-b05f-4bc4-b164-c7c7e0b63269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66170156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outs
tanding.66170156
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3063906720
Short name T964
Test name
Test status
Simulation time 27678794 ps
CPU time 1.73 seconds
Started Mar 14 12:28:18 PM PDT 24
Finished Mar 14 12:28:20 PM PDT 24
Peak memory 214528 kb
Host smart-85b1d32c-4e47-492f-9e85-8460524a6c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063906720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3063906720
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1011259215
Short name T871
Test name
Test status
Simulation time 182897070 ps
CPU time 1.69 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:33 PM PDT 24
Peak memory 206216 kb
Host smart-4c9fcbc3-8545-4ee0-973a-58990f6ca7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011259215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1011259215
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.362385810
Short name T901
Test name
Test status
Simulation time 21725234 ps
CPU time 0.98 seconds
Started Mar 14 12:28:29 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 214572 kb
Host smart-47e39cbb-c5dc-4103-b7a1-8d2aea56115f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362385810 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.362385810
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3188630412
Short name T233
Test name
Test status
Simulation time 14618671 ps
CPU time 0.85 seconds
Started Mar 14 12:28:32 PM PDT 24
Finished Mar 14 12:28:33 PM PDT 24
Peak memory 206016 kb
Host smart-963446f9-db53-42c3-8ef9-0562bec17168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188630412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3188630412
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.877823047
Short name T838
Test name
Test status
Simulation time 51723075 ps
CPU time 0.85 seconds
Started Mar 14 12:28:16 PM PDT 24
Finished Mar 14 12:28:17 PM PDT 24
Peak memory 206060 kb
Host smart-c3e4b5cf-827a-4ba0-b593-5a7bdfe3dfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877823047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.877823047
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.779507976
Short name T959
Test name
Test status
Simulation time 160185125 ps
CPU time 1.37 seconds
Started Mar 14 12:28:14 PM PDT 24
Finished Mar 14 12:28:15 PM PDT 24
Peak memory 206160 kb
Host smart-5edbbb93-3946-4d79-a17a-38312a0c1275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779507976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.779507976
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.642645949
Short name T853
Test name
Test status
Simulation time 84915073 ps
CPU time 2.72 seconds
Started Mar 14 12:28:25 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 214460 kb
Host smart-a101b7ed-69f0-4edd-a587-b1ef837531b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642645949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.642645949
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1401503847
Short name T253
Test name
Test status
Simulation time 83017688 ps
CPU time 2.34 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:26 PM PDT 24
Peak memory 206220 kb
Host smart-574699b5-db86-4546-b91f-245a95984f37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401503847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1401503847
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2398884404
Short name T916
Test name
Test status
Simulation time 56746786 ps
CPU time 1.49 seconds
Started Mar 14 12:28:32 PM PDT 24
Finished Mar 14 12:28:34 PM PDT 24
Peak memory 214504 kb
Host smart-30669c9a-d38e-471d-8188-bb0a21c8c59f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398884404 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2398884404
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4128577263
Short name T918
Test name
Test status
Simulation time 11792405 ps
CPU time 0.88 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:32 PM PDT 24
Peak memory 206032 kb
Host smart-be287667-6555-448e-8c39-e9e92f642672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128577263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4128577263
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2173529638
Short name T963
Test name
Test status
Simulation time 16108821 ps
CPU time 0.91 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 205884 kb
Host smart-1ec9c451-f022-4c13-bd64-97fdaae294e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173529638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2173529638
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1122458367
Short name T217
Test name
Test status
Simulation time 72603840 ps
CPU time 1.45 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 205996 kb
Host smart-85d61d5d-1a12-49d9-9023-364a7bfdd2c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122458367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1122458367
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2723141845
Short name T861
Test name
Test status
Simulation time 201439590 ps
CPU time 3.13 seconds
Started Mar 14 12:28:20 PM PDT 24
Finished Mar 14 12:28:23 PM PDT 24
Peak memory 214388 kb
Host smart-f31ffad1-827f-48a1-be0b-ab1fa422df92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723141845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2723141845
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.7555448
Short name T863
Test name
Test status
Simulation time 196099793 ps
CPU time 0.95 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 206364 kb
Host smart-9223aa08-d25f-4a16-b385-3423f9ebae17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7555448 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.7555448
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.621638676
Short name T837
Test name
Test status
Simulation time 41372710 ps
CPU time 0.81 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:35 PM PDT 24
Peak memory 205844 kb
Host smart-00b3d6e0-27be-4eb2-9df6-60c9bfd164dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621638676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.621638676
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.983531320
Short name T952
Test name
Test status
Simulation time 48212590 ps
CPU time 0.75 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 205876 kb
Host smart-07111a11-a0a1-4cab-92a8-fd7d10b9dfa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983531320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.983531320
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3027683867
Short name T913
Test name
Test status
Simulation time 17755407 ps
CPU time 1.02 seconds
Started Mar 14 12:28:30 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 206184 kb
Host smart-bcb3bc87-198f-4942-b2cb-8fb52e586547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027683867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3027683867
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3755495928
Short name T870
Test name
Test status
Simulation time 416693751 ps
CPU time 3.21 seconds
Started Mar 14 12:28:16 PM PDT 24
Finished Mar 14 12:28:19 PM PDT 24
Peak memory 214576 kb
Host smart-1c64135e-d906-490c-8c86-25cb347fe885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755495928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3755495928
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3118526997
Short name T875
Test name
Test status
Simulation time 209901716 ps
CPU time 1.5 seconds
Started Mar 14 12:28:34 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 206220 kb
Host smart-12dd644b-f476-427e-b099-4c2e5df70363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118526997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3118526997
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4051491119
Short name T836
Test name
Test status
Simulation time 29051204 ps
CPU time 1.39 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 214492 kb
Host smart-7a16613b-d489-4d13-8278-2193c3b5d5d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051491119 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4051491119
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.916861828
Short name T860
Test name
Test status
Simulation time 17696396 ps
CPU time 0.92 seconds
Started Mar 14 12:28:23 PM PDT 24
Finished Mar 14 12:28:24 PM PDT 24
Peak memory 206060 kb
Host smart-398ca6e3-6861-4b26-a30f-d2c54d9d662b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916861828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.916861828
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.647718954
Short name T966
Test name
Test status
Simulation time 73812121 ps
CPU time 1.04 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:36 PM PDT 24
Peak memory 206140 kb
Host smart-984750ce-60cb-4fd1-b45c-b75522143fc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647718954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.647718954
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4261207618
Short name T849
Test name
Test status
Simulation time 102547078 ps
CPU time 2.51 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 214524 kb
Host smart-0939649f-a215-4f0f-8db5-c8e9b2bce725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261207618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4261207618
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3663858243
Short name T920
Test name
Test status
Simulation time 327238584 ps
CPU time 1.54 seconds
Started Mar 14 12:28:31 PM PDT 24
Finished Mar 14 12:28:33 PM PDT 24
Peak memory 206196 kb
Host smart-41d7dad0-777b-4782-92a2-d24b3d063b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663858243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3663858243
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3243542401
Short name T779
Test name
Test status
Simulation time 44205445 ps
CPU time 1.08 seconds
Started Mar 14 12:48:12 PM PDT 24
Finished Mar 14 12:48:14 PM PDT 24
Peak memory 215272 kb
Host smart-50ad259c-fd05-473a-a36a-7d0e92325602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243542401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3243542401
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.602497663
Short name T175
Test name
Test status
Simulation time 182005736 ps
CPU time 0.91 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206260 kb
Host smart-9db0dcb6-b33a-4009-b4c3-5c7597286b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602497663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.602497663
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2291864024
Short name T329
Test name
Test status
Simulation time 23151075 ps
CPU time 0.9 seconds
Started Mar 14 12:48:13 PM PDT 24
Finished Mar 14 12:48:14 PM PDT 24
Peak memory 215248 kb
Host smart-b6bc8e1d-6aed-4016-a1a7-bf30d4a9a8d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291864024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2291864024
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.716015024
Short name T372
Test name
Test status
Simulation time 39960612 ps
CPU time 1.06 seconds
Started Mar 14 12:48:13 PM PDT 24
Finished Mar 14 12:48:14 PM PDT 24
Peak memory 217344 kb
Host smart-0e3c2a20-2193-49ea-8040-30da8e3c38e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716015024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.716015024
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.331591306
Short name T492
Test name
Test status
Simulation time 19461219 ps
CPU time 1.04 seconds
Started Mar 14 12:48:13 PM PDT 24
Finished Mar 14 12:48:14 PM PDT 24
Peak memory 217544 kb
Host smart-dca4e5b9-bd16-4c1e-a59d-f15b000dcac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331591306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.331591306
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.699045607
Short name T496
Test name
Test status
Simulation time 48729210 ps
CPU time 1.54 seconds
Started Mar 14 12:48:12 PM PDT 24
Finished Mar 14 12:48:13 PM PDT 24
Peak memory 216224 kb
Host smart-e1d2dc34-4c03-47b7-8b75-759df77f9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699045607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.699045607
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1422675149
Short name T781
Test name
Test status
Simulation time 22997792 ps
CPU time 1.11 seconds
Started Mar 14 12:48:13 PM PDT 24
Finished Mar 14 12:48:14 PM PDT 24
Peak memory 215012 kb
Host smart-00c1523b-11bb-4076-9201-8358002b58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422675149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1422675149
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.425451384
Short name T127
Test name
Test status
Simulation time 40616297 ps
CPU time 0.94 seconds
Started Mar 14 12:48:16 PM PDT 24
Finished Mar 14 12:48:17 PM PDT 24
Peak memory 206596 kb
Host smart-a4cb4220-73da-4fb1-b72d-6443e49a392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425451384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.425451384
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2564564451
Short name T302
Test name
Test status
Simulation time 17241385 ps
CPU time 1 seconds
Started Mar 14 12:48:15 PM PDT 24
Finished Mar 14 12:48:16 PM PDT 24
Peak memory 214808 kb
Host smart-32a64b17-abb4-4ef3-b5b0-a07c1f3a82c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564564451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2564564451
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1235850053
Short name T526
Test name
Test status
Simulation time 177360194 ps
CPU time 1.67 seconds
Started Mar 14 12:48:21 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 216348 kb
Host smart-29e7f7a4-8cef-4303-9865-232e156af634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235850053 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1235850053
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3825918649
Short name T482
Test name
Test status
Simulation time 16826069816 ps
CPU time 228.69 seconds
Started Mar 14 12:48:15 PM PDT 24
Finished Mar 14 12:52:04 PM PDT 24
Peak memory 218136 kb
Host smart-218fd360-ff93-4093-8836-6550fee4aea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825918649 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3825918649
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.977898455
Short name T84
Test name
Test status
Simulation time 173366457 ps
CPU time 1.21 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 215208 kb
Host smart-d73c9a9c-5076-4904-9ac8-18a0abce00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977898455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.977898455
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3628362565
Short name T408
Test name
Test status
Simulation time 13891375 ps
CPU time 0.87 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206572 kb
Host smart-013fa2b0-9f65-4ba2-a04e-8343e1a7f6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628362565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3628362565
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2025759968
Short name T123
Test name
Test status
Simulation time 11865690 ps
CPU time 0.88 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 215632 kb
Host smart-da8b73e2-68d1-498d-b7dd-15f2b05e5843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025759968 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2025759968
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.234070707
Short name T488
Test name
Test status
Simulation time 173296260 ps
CPU time 1.13 seconds
Started Mar 14 12:48:21 PM PDT 24
Finished Mar 14 12:48:22 PM PDT 24
Peak memory 217484 kb
Host smart-e1bf9379-fab7-49b4-b7f6-726282101950
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234070707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.234070707
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3087459621
Short name T101
Test name
Test status
Simulation time 27699518 ps
CPU time 0.9 seconds
Started Mar 14 12:48:26 PM PDT 24
Finished Mar 14 12:48:28 PM PDT 24
Peak memory 217388 kb
Host smart-0fbc360b-d9b2-49fa-b54b-3620275b0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087459621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3087459621
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2017159231
Short name T38
Test name
Test status
Simulation time 48720099 ps
CPU time 1.59 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 216268 kb
Host smart-8a2af4e2-1782-4c89-8c5b-a22d2c4a95d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017159231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2017159231
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3265163740
Short name T22
Test name
Test status
Simulation time 839300741 ps
CPU time 7.89 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 234032 kb
Host smart-dd2e7b7d-cddc-4527-a8d6-a3e07474ff55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265163740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3265163740
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.44799063
Short name T557
Test name
Test status
Simulation time 16343051 ps
CPU time 1.01 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 214984 kb
Host smart-e44607f4-d599-427d-a954-e6e96f5234e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44799063 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.44799063
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3379557713
Short name T368
Test name
Test status
Simulation time 44747629502 ps
CPU time 1059.1 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 01:06:04 PM PDT 24
Peak memory 218024 kb
Host smart-52481ea6-97c0-4318-9fde-291e6702b0bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379557713 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3379557713
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3876377290
Short name T242
Test name
Test status
Simulation time 23247884 ps
CPU time 1.12 seconds
Started Mar 14 12:48:29 PM PDT 24
Finished Mar 14 12:48:31 PM PDT 24
Peak memory 215236 kb
Host smart-31f9a0ac-b641-4ab5-a148-7985d2400af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876377290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3876377290
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.583442016
Short name T550
Test name
Test status
Simulation time 29619646 ps
CPU time 1.2 seconds
Started Mar 14 12:48:37 PM PDT 24
Finished Mar 14 12:48:38 PM PDT 24
Peak memory 206156 kb
Host smart-a5bdd5c7-b9d5-4aa5-83cd-752a31bfb789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583442016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.583442016
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.880046806
Short name T98
Test name
Test status
Simulation time 28994919 ps
CPU time 0.8 seconds
Started Mar 14 12:48:31 PM PDT 24
Finished Mar 14 12:48:32 PM PDT 24
Peak memory 215020 kb
Host smart-90893206-72c4-4481-b8b3-23a5488be250
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880046806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.880046806
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.38742116
Short name T536
Test name
Test status
Simulation time 48846364 ps
CPU time 0.99 seconds
Started Mar 14 12:48:37 PM PDT 24
Finished Mar 14 12:48:38 PM PDT 24
Peak memory 215160 kb
Host smart-a7cb17a0-58cc-4384-9510-f3e4bf7e7991
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38742116 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_dis
able_auto_req_mode.38742116
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3684036139
Short name T730
Test name
Test status
Simulation time 38567342 ps
CPU time 1.08 seconds
Started Mar 14 12:48:30 PM PDT 24
Finished Mar 14 12:48:31 PM PDT 24
Peak memory 217532 kb
Host smart-9c26a544-55a5-48ef-8d32-3a516d219b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684036139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3684036139
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.304804330
Short name T680
Test name
Test status
Simulation time 42987370 ps
CPU time 0.78 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 215040 kb
Host smart-cebf9f8e-c6bc-4e6d-851e-00d6b87fc706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304804330 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.304804330
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.606781781
Short name T207
Test name
Test status
Simulation time 17240215 ps
CPU time 0.94 seconds
Started Mar 14 12:48:31 PM PDT 24
Finished Mar 14 12:48:32 PM PDT 24
Peak memory 214936 kb
Host smart-6dec9dc1-b300-4a5f-b147-b1401a9ee747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606781781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.606781781
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1064117800
Short name T707
Test name
Test status
Simulation time 91793257 ps
CPU time 1.57 seconds
Started Mar 14 12:48:37 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 214888 kb
Host smart-416856b7-a393-4b64-89b0-2164ea249974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064117800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1064117800
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3713071183
Short name T194
Test name
Test status
Simulation time 35435913327 ps
CPU time 327.47 seconds
Started Mar 14 12:48:43 PM PDT 24
Finished Mar 14 12:54:11 PM PDT 24
Peak memory 217032 kb
Host smart-45d0629c-430c-44f0-b36a-2ed940b7e285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713071183 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3713071183
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2479566091
Short name T356
Test name
Test status
Simulation time 44845234 ps
CPU time 1.03 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216444 kb
Host smart-f04a204e-1e71-447c-8153-6195e1d7292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479566091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2479566091
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.396464069
Short name T780
Test name
Test status
Simulation time 52654588 ps
CPU time 1.81 seconds
Started Mar 14 12:50:08 PM PDT 24
Finished Mar 14 12:50:10 PM PDT 24
Peak memory 217540 kb
Host smart-ab2a4e1f-7c6c-45d7-8afb-e090efd3f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396464069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.396464069
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1910900122
Short name T789
Test name
Test status
Simulation time 38087282 ps
CPU time 1.34 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 216508 kb
Host smart-90415909-aba0-4093-9a5e-96b6589ba384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910900122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1910900122
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1241055480
Short name T184
Test name
Test status
Simulation time 67211850 ps
CPU time 1.45 seconds
Started Mar 14 12:50:10 PM PDT 24
Finished Mar 14 12:50:12 PM PDT 24
Peak memory 217780 kb
Host smart-54873b51-72b2-4abb-b5c1-6cc8534b40fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241055480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1241055480
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.3431118553
Short name T749
Test name
Test status
Simulation time 31007674 ps
CPU time 1.5 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 217392 kb
Host smart-8a02adc1-040a-4f84-924f-a851da318b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431118553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3431118553
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.885092912
Short name T537
Test name
Test status
Simulation time 58261195 ps
CPU time 1.5 seconds
Started Mar 14 12:50:01 PM PDT 24
Finished Mar 14 12:50:02 PM PDT 24
Peak memory 217900 kb
Host smart-9ecae3f8-22f8-4834-ada0-63f2f78bf8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885092912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.885092912
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1972866665
Short name T139
Test name
Test status
Simulation time 70882851 ps
CPU time 2.52 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 218488 kb
Host smart-cbf87e89-9e77-4cfb-9140-9e171101c2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972866665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1972866665
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.153125086
Short name T699
Test name
Test status
Simulation time 53600484 ps
CPU time 1.79 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216400 kb
Host smart-1ca6c08f-4963-4093-abbc-f725bae5e72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153125086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.153125086
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1913826518
Short name T291
Test name
Test status
Simulation time 56821010 ps
CPU time 1.2 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 216624 kb
Host smart-d110040e-9ec7-48ed-9adb-852f55a1a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913826518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1913826518
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2956633804
Short name T204
Test name
Test status
Simulation time 44527833 ps
CPU time 1.16 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 218364 kb
Host smart-b8323421-e695-4a90-9cdc-187c2f841249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956633804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2956633804
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.9556361
Short name T770
Test name
Test status
Simulation time 76442928 ps
CPU time 1.19 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 215248 kb
Host smart-e68bf4cc-7fdf-437a-be2e-cb825d77b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9556361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.9556361
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.459052388
Short name T558
Test name
Test status
Simulation time 28157309 ps
CPU time 0.9 seconds
Started Mar 14 12:48:37 PM PDT 24
Finished Mar 14 12:48:38 PM PDT 24
Peak memory 206452 kb
Host smart-0111721c-64a1-4efd-976c-c7b77c521f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459052388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.459052388
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3075493491
Short name T313
Test name
Test status
Simulation time 12140855 ps
CPU time 0.89 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 215240 kb
Host smart-c2226934-0021-4037-9a9c-c625a3e896f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075493491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3075493491
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.220238164
Short name T802
Test name
Test status
Simulation time 56386272 ps
CPU time 0.98 seconds
Started Mar 14 12:48:43 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 217268 kb
Host smart-4cdcdcd1-e667-404d-a1a2-dbef82994948
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220238164 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.220238164
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2940523367
Short name T722
Test name
Test status
Simulation time 26671559 ps
CPU time 0.83 seconds
Started Mar 14 12:48:37 PM PDT 24
Finished Mar 14 12:48:38 PM PDT 24
Peak memory 217196 kb
Host smart-422bc860-d3a3-46c0-b865-71811a8a8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940523367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2940523367
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.4074783074
Short name T137
Test name
Test status
Simulation time 45146129 ps
CPU time 1.19 seconds
Started Mar 14 12:48:33 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 218684 kb
Host smart-c9a8d3c9-8218-4abe-8521-cddd7ad40f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074783074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4074783074
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2526495744
Short name T424
Test name
Test status
Simulation time 27356539 ps
CPU time 0.91 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 215004 kb
Host smart-be824f95-a2e4-4c03-ac0b-c15d2ceb4f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526495744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2526495744
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.82347519
Short name T210
Test name
Test status
Simulation time 17660109 ps
CPU time 0.99 seconds
Started Mar 14 12:48:31 PM PDT 24
Finished Mar 14 12:48:32 PM PDT 24
Peak memory 206768 kb
Host smart-4f752d6e-cc28-42ba-8f16-769bccbfe6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82347519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.82347519
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2059341972
Short name T396
Test name
Test status
Simulation time 464422951 ps
CPU time 3.59 seconds
Started Mar 14 12:48:30 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 216156 kb
Host smart-63a376a0-023a-490f-b06c-4dc7de663b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059341972 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2059341972
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2094658635
Short name T761
Test name
Test status
Simulation time 95387610155 ps
CPU time 812.46 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 01:02:17 PM PDT 24
Peak memory 221856 kb
Host smart-7db80591-5bfa-4f46-b4a3-547ab18e7467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094658635 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2094658635
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.569050634
Short name T589
Test name
Test status
Simulation time 109006147 ps
CPU time 0.91 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 216352 kb
Host smart-30abe530-44ed-424a-8378-d503cc0b3516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569050634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.569050634
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2678317593
Short name T189
Test name
Test status
Simulation time 41599062 ps
CPU time 1.82 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217680 kb
Host smart-d076f65c-f119-4d95-bb8e-85f635b65fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678317593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2678317593
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.70163339
Short name T585
Test name
Test status
Simulation time 62731864 ps
CPU time 1.36 seconds
Started Mar 14 12:50:08 PM PDT 24
Finished Mar 14 12:50:10 PM PDT 24
Peak memory 217652 kb
Host smart-7524898f-cc90-4b01-bf94-be79f7dc2daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70163339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.70163339
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2548323741
Short name T412
Test name
Test status
Simulation time 452879985 ps
CPU time 4.38 seconds
Started Mar 14 12:49:56 PM PDT 24
Finished Mar 14 12:50:01 PM PDT 24
Peak memory 217488 kb
Host smart-41ad7d71-5e1f-48da-9a59-7172c649e3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548323741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2548323741
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.379678113
Short name T583
Test name
Test status
Simulation time 41327225 ps
CPU time 1.42 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217644 kb
Host smart-43d54abe-1abc-49a6-bb38-66a6406f9a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379678113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.379678113
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.4219545470
Short name T764
Test name
Test status
Simulation time 53353904 ps
CPU time 0.97 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 216240 kb
Host smart-576d6b18-b499-48cd-a0ea-f01989a7df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219545470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4219545470
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.4180449819
Short name T740
Test name
Test status
Simulation time 47068984 ps
CPU time 1.37 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 218148 kb
Host smart-c37e466b-da03-4d9d-bd0c-49cf6fc5dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180449819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4180449819
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3051244409
Short name T266
Test name
Test status
Simulation time 49467997 ps
CPU time 1.14 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 215244 kb
Host smart-472313a8-4ed1-4f30-9f29-7a2c55f02ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051244409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3051244409
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1291263430
Short name T784
Test name
Test status
Simulation time 19627736 ps
CPU time 0.83 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 205520 kb
Host smart-098d59cb-91ca-4c1c-b94d-5e52808f2112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291263430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1291263430
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.3284507311
Short name T791
Test name
Test status
Simulation time 39947356 ps
CPU time 0.83 seconds
Started Mar 14 12:48:43 PM PDT 24
Finished Mar 14 12:48:44 PM PDT 24
Peak memory 214820 kb
Host smart-471f33dd-3fb2-4559-b725-82bcc3aabfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284507311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3284507311
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3061749871
Short name T394
Test name
Test status
Simulation time 48864481 ps
CPU time 1.43 seconds
Started Mar 14 12:48:35 PM PDT 24
Finished Mar 14 12:48:37 PM PDT 24
Peak memory 217396 kb
Host smart-1f31d91d-0a99-4501-afce-0e6bdb729977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061749871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3061749871
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4286657752
Short name T128
Test name
Test status
Simulation time 30258150 ps
CPU time 0.93 seconds
Started Mar 14 12:48:31 PM PDT 24
Finished Mar 14 12:48:32 PM PDT 24
Peak memory 215172 kb
Host smart-74343899-6603-4717-ae97-74929ec12c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286657752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4286657752
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2576599196
Short name T665
Test name
Test status
Simulation time 30027166 ps
CPU time 0.97 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 214932 kb
Host smart-c7cf7f13-ebf9-49f2-8f6b-c843d8a55b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576599196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2576599196
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2661931679
Short name T729
Test name
Test status
Simulation time 2765702791 ps
CPU time 4.44 seconds
Started Mar 14 12:48:30 PM PDT 24
Finished Mar 14 12:48:35 PM PDT 24
Peak memory 216264 kb
Host smart-96d77b9f-fdf9-4dbd-b02a-c8917926affe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661931679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2661931679
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2740103851
Short name T192
Test name
Test status
Simulation time 33860957887 ps
CPU time 472.34 seconds
Started Mar 14 12:48:31 PM PDT 24
Finished Mar 14 12:56:23 PM PDT 24
Peak memory 223428 kb
Host smart-b0d1aa22-1731-474c-bcf2-f76d57af4836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740103851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2740103851
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3915215889
Short name T793
Test name
Test status
Simulation time 73643069 ps
CPU time 1.38 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217900 kb
Host smart-84d0c616-4d70-43d4-8832-858eae7e177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915215889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3915215889
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1434950163
Short name T376
Test name
Test status
Simulation time 191192530 ps
CPU time 2.55 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218944 kb
Host smart-40b0c5cd-b0c7-46e5-90ad-ca1284fcac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434950163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1434950163
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.368081751
Short name T325
Test name
Test status
Simulation time 60990467 ps
CPU time 1.35 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217784 kb
Host smart-6914e92a-2b54-45fb-893f-e3664647fd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368081751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.368081751
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1445405942
Short name T436
Test name
Test status
Simulation time 58976985 ps
CPU time 1.4 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 217784 kb
Host smart-8c6094f1-87de-418d-859c-22b8c458d807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445405942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1445405942
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.523571652
Short name T340
Test name
Test status
Simulation time 41969799 ps
CPU time 1.66 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217508 kb
Host smart-06179eb6-4f6e-4990-be66-081e763ab026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523571652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.523571652
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.4034949457
Short name T763
Test name
Test status
Simulation time 124022556 ps
CPU time 1.31 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217596 kb
Host smart-78c70d61-ab50-4df9-95ce-722e46166c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034949457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4034949457
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1872271533
Short name T698
Test name
Test status
Simulation time 37363349 ps
CPU time 1.49 seconds
Started Mar 14 12:50:00 PM PDT 24
Finished Mar 14 12:50:02 PM PDT 24
Peak memory 216496 kb
Host smart-1aa43eee-974b-4144-a494-fab665238b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872271533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1872271533
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.961449969
Short name T817
Test name
Test status
Simulation time 22958216 ps
CPU time 1.12 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 216436 kb
Host smart-0b17025c-69dd-403d-a227-fa3b4022a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961449969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.961449969
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1033865417
Short name T334
Test name
Test status
Simulation time 78179439 ps
CPU time 1.24 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 218952 kb
Host smart-05ab2533-5d28-4b9d-a0eb-ffd26fc7b7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033865417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1033865417
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3931267508
Short name T638
Test name
Test status
Simulation time 18362294 ps
CPU time 0.82 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 205496 kb
Host smart-d8d21e19-1dab-4b8d-8fab-60c780a98d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931267508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3931267508
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3160066428
Short name T656
Test name
Test status
Simulation time 67389825 ps
CPU time 1.31 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 215240 kb
Host smart-0b01782f-d068-44b0-8359-fbc3f347522a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160066428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3160066428
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1374908403
Short name T120
Test name
Test status
Simulation time 29215940 ps
CPU time 0.86 seconds
Started Mar 14 12:48:45 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 217548 kb
Host smart-8a7937ed-bd8b-44b6-a104-e4598cb1577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374908403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1374908403
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1235445918
Short name T355
Test name
Test status
Simulation time 23971766 ps
CPU time 1.15 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 218460 kb
Host smart-ecf3234b-ab65-466a-b8c7-3d6b021d7aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235445918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1235445918
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.3500131548
Short name T471
Test name
Test status
Simulation time 60573920 ps
CPU time 0.94 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 214820 kb
Host smart-526ad5e8-6a19-4954-a270-4fdadfdea0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500131548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3500131548
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1928775643
Short name T433
Test name
Test status
Simulation time 486082939 ps
CPU time 2.83 seconds
Started Mar 14 12:48:39 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 214944 kb
Host smart-e48a651e-27c2-42da-aab6-64add148dfeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928775643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1928775643
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2609474476
Short name T829
Test name
Test status
Simulation time 35972395970 ps
CPU time 853.03 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 01:02:54 PM PDT 24
Peak memory 217348 kb
Host smart-0b9f1e18-3b69-4bc4-8498-2fed5661bb9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609474476 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2609474476
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2098573549
Short name T1
Test name
Test status
Simulation time 87046658 ps
CPU time 1.09 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:03 PM PDT 24
Peak memory 217360 kb
Host smart-f758ab63-e271-4b3e-a146-7e0f7e2f2256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098573549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2098573549
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1066838995
Short name T409
Test name
Test status
Simulation time 119376773 ps
CPU time 1.01 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 216388 kb
Host smart-be1c1a2d-478a-4269-ab9d-90e50f48925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066838995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1066838995
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3365847877
Short name T767
Test name
Test status
Simulation time 82282148 ps
CPU time 1.11 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217740 kb
Host smart-cf78f2e6-8070-415a-a8ce-91e825acebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365847877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3365847877
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2299935617
Short name T246
Test name
Test status
Simulation time 43151817 ps
CPU time 1.11 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 216444 kb
Host smart-fee0e24a-5133-4d22-a0ab-88bafd73fac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299935617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2299935617
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1430829220
Short name T630
Test name
Test status
Simulation time 53811530 ps
CPU time 1.23 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217588 kb
Host smart-15dc8ba0-7ce8-490b-ace1-42f847fe1b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430829220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1430829220
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.4024147832
Short name T455
Test name
Test status
Simulation time 56017176 ps
CPU time 1.45 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217644 kb
Host smart-29d05765-be96-438d-b082-27294760c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024147832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4024147832
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1352431399
Short name T36
Test name
Test status
Simulation time 26859567 ps
CPU time 1.07 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 217580 kb
Host smart-19794026-7b75-4b1c-886d-ace4e2a30628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352431399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1352431399
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1400392541
Short name T529
Test name
Test status
Simulation time 32007977 ps
CPU time 1.18 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 217672 kb
Host smart-fbcadba6-3537-4d90-8d43-45d5ab7ea0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400392541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1400392541
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.4253532622
Short name T185
Test name
Test status
Simulation time 49327120 ps
CPU time 1.89 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 219128 kb
Host smart-ee9e6812-a464-40c7-82ee-08f8f8a990e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253532622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4253532622
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3881948062
Short name T715
Test name
Test status
Simulation time 69446009 ps
CPU time 1.12 seconds
Started Mar 14 12:48:39 PM PDT 24
Finished Mar 14 12:48:40 PM PDT 24
Peak memory 215184 kb
Host smart-e6f4f1f1-81c5-42f2-98f6-5a1fd66b0693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881948062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3881948062
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3447066720
Short name T309
Test name
Test status
Simulation time 25570766 ps
CPU time 0.88 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:41 PM PDT 24
Peak memory 205336 kb
Host smart-cd30d02b-d390-4fc0-b1c3-316fa213a15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447066720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3447066720
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2588040851
Short name T456
Test name
Test status
Simulation time 35418928 ps
CPU time 0.81 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:41 PM PDT 24
Peak memory 215240 kb
Host smart-44640326-b2d4-4333-8dc8-9a4735ed2272
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588040851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2588040851
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.952624445
Short name T47
Test name
Test status
Simulation time 18464516 ps
CPU time 1 seconds
Started Mar 14 12:48:39 PM PDT 24
Finished Mar 14 12:48:41 PM PDT 24
Peak memory 217600 kb
Host smart-1e24ae27-0053-4de4-bc9a-0fea640d2fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952624445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.952624445
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.3772675367
Short name T531
Test name
Test status
Simulation time 22489703 ps
CPU time 0.98 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:41 PM PDT 24
Peak memory 215308 kb
Host smart-5dab7ca1-db30-4c55-8788-e130eaf2b32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772675367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3772675367
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3448835967
Short name T26
Test name
Test status
Simulation time 17117192 ps
CPU time 0.98 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 214952 kb
Host smart-797414d2-6e9c-4c33-ac9f-05f929d45c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448835967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3448835967
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.765708680
Short name T209
Test name
Test status
Simulation time 790690688 ps
CPU time 6.47 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:48 PM PDT 24
Peak memory 214928 kb
Host smart-089422d2-68a4-40a3-94f9-308d29dcf96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765708680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.765708680
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.43584763
Short name T448
Test name
Test status
Simulation time 159059045717 ps
CPU time 1824.55 seconds
Started Mar 14 12:48:45 PM PDT 24
Finished Mar 14 01:19:09 PM PDT 24
Peak memory 225292 kb
Host smart-c592c5d1-6ae6-437f-b5fc-db111f371801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43584763 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.43584763
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1457789377
Short name T248
Test name
Test status
Simulation time 72325682 ps
CPU time 1.29 seconds
Started Mar 14 12:50:01 PM PDT 24
Finished Mar 14 12:50:03 PM PDT 24
Peak memory 216328 kb
Host smart-bdc7bbdd-e7b3-4f5c-bb55-6adef91563ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457789377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1457789377
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3287723095
Short name T624
Test name
Test status
Simulation time 47150223 ps
CPU time 1.36 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 216416 kb
Host smart-4dae7a9e-d632-43d9-beeb-9d27fa87736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287723095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3287723095
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2828089241
Short name T685
Test name
Test status
Simulation time 39592229 ps
CPU time 1.38 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:03 PM PDT 24
Peak memory 216328 kb
Host smart-861a51d5-6a23-4f89-955d-a82e121edd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828089241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2828089241
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.826827603
Short name T11
Test name
Test status
Simulation time 39350188 ps
CPU time 1.61 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 216536 kb
Host smart-85d5f375-858f-4e72-9e30-00744dcd1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826827603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.826827603
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.4035021248
Short name T533
Test name
Test status
Simulation time 42181673 ps
CPU time 1.32 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217432 kb
Host smart-d58922a0-9176-4e56-8a06-dec1314c0ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035021248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4035021248
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.743060939
Short name T655
Test name
Test status
Simulation time 46894627 ps
CPU time 1.17 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217544 kb
Host smart-29ba68c7-3ae9-4d2f-a8cf-a7aacef34ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743060939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.743060939
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.788289106
Short name T32
Test name
Test status
Simulation time 86434993 ps
CPU time 1.21 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217752 kb
Host smart-766c7145-2195-452e-8189-203705cab21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788289106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.788289106
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.260319665
Short name T397
Test name
Test status
Simulation time 70470100 ps
CPU time 2.34 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 218904 kb
Host smart-71b4c988-afa4-4333-9931-be393134ce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260319665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.260319665
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1231966617
Short name T662
Test name
Test status
Simulation time 48233133 ps
CPU time 1.67 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 217464 kb
Host smart-d735378f-f94b-4745-9cd7-afac6c77b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231966617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1231966617
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2450776301
Short name T262
Test name
Test status
Simulation time 91000934 ps
CPU time 1.2 seconds
Started Mar 14 12:48:39 PM PDT 24
Finished Mar 14 12:48:40 PM PDT 24
Peak memory 215244 kb
Host smart-486b7ea3-685b-471d-9c95-9522f6533093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450776301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2450776301
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1694656975
Short name T505
Test name
Test status
Simulation time 15289948 ps
CPU time 0.92 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 206576 kb
Host smart-c289a676-60f3-4a44-9eb4-0fe53f95714c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694656975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1694656975
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2148132491
Short name T71
Test name
Test status
Simulation time 54346230 ps
CPU time 1.48 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 215904 kb
Host smart-b6321a7a-a1cd-41b5-a0d8-87503543356f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148132491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2148132491
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.66326292
Short name T23
Test name
Test status
Simulation time 20093450 ps
CPU time 0.97 seconds
Started Mar 14 12:48:38 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 217464 kb
Host smart-549eaf41-33f0-4d16-87b5-441750ca85d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66326292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.66326292
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1058570072
Short name T330
Test name
Test status
Simulation time 56377110 ps
CPU time 1.95 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 217672 kb
Host smart-2a92c910-3354-4d07-a112-0007433e5573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058570072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1058570072
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.787344366
Short name T333
Test name
Test status
Simulation time 35555181 ps
CPU time 0.9 seconds
Started Mar 14 12:48:45 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 215008 kb
Host smart-11eb9b0c-c68a-4353-83f5-57028f5636d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787344366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.787344366
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2662608885
Short name T813
Test name
Test status
Simulation time 24287052 ps
CPU time 0.92 seconds
Started Mar 14 12:48:45 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 214948 kb
Host smart-d2d28687-95d6-4924-9d2f-23b655e9f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662608885 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2662608885
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1255965575
Short name T342
Test name
Test status
Simulation time 30522163 ps
CPU time 0.94 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 205588 kb
Host smart-5f54a1ed-15ae-44da-ab0d-7d020935c050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255965575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1255965575
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3121682854
Short name T202
Test name
Test status
Simulation time 77134653092 ps
CPU time 451.66 seconds
Started Mar 14 12:48:39 PM PDT 24
Finished Mar 14 12:56:11 PM PDT 24
Peak memory 218708 kb
Host smart-48bcbe94-ef0a-4e7a-8fd6-5b16edd269b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121682854 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3121682854
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.edn_genbits.41371178
Short name T366
Test name
Test status
Simulation time 154261292 ps
CPU time 1.74 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217788 kb
Host smart-3aebdea7-c0dd-423c-bfdf-cad62625f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41371178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.41371178
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.379624291
Short name T203
Test name
Test status
Simulation time 46837420 ps
CPU time 1.43 seconds
Started Mar 14 12:50:00 PM PDT 24
Finished Mar 14 12:50:02 PM PDT 24
Peak memory 218304 kb
Host smart-1d58ff28-7140-4224-9975-e1a590cd85de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379624291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.379624291
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3734251663
Short name T689
Test name
Test status
Simulation time 159944501 ps
CPU time 1.14 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216736 kb
Host smart-c6160202-31f4-41cc-8e20-d73c593189f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734251663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3734251663
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.4037937367
Short name T617
Test name
Test status
Simulation time 27526807 ps
CPU time 1.39 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 219132 kb
Host smart-0d6ba10e-5323-4b5b-bb3e-7cb6745c11f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037937367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4037937367
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1949083191
Short name T30
Test name
Test status
Simulation time 129643196 ps
CPU time 1.69 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 217872 kb
Host smart-016c216e-2ffa-45ab-acbc-08084c8abc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949083191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1949083191
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1759851182
Short name T598
Test name
Test status
Simulation time 91816374 ps
CPU time 1.43 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217812 kb
Host smart-60c7a749-66d2-48c5-8475-ff2676d9c68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759851182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1759851182
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.466586431
Short name T706
Test name
Test status
Simulation time 47351197 ps
CPU time 1.7 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 216416 kb
Host smart-5cd114f4-5c71-4bda-bf1e-32ee223e81a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466586431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.466586431
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2461717305
Short name T651
Test name
Test status
Simulation time 45285408 ps
CPU time 1.47 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217580 kb
Host smart-7d49bf3b-2ca1-4c10-a202-fa99be42df0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461717305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2461717305
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4014364558
Short name T746
Test name
Test status
Simulation time 62019927 ps
CPU time 1.11 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217620 kb
Host smart-86399ecd-bf2d-43f4-810f-e761aa1ee6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014364558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4014364558
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2301082625
Short name T679
Test name
Test status
Simulation time 48466711 ps
CPU time 1.08 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 215212 kb
Host smart-45f5cfb4-7ddc-4a1d-b78c-5d9f10eb4ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301082625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2301082625
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1824557329
Short name T453
Test name
Test status
Simulation time 113015063 ps
CPU time 0.85 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 206188 kb
Host smart-7fcd7bb1-0a65-4ee4-9e89-441abeb75dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824557329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1824557329
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1152117658
Short name T727
Test name
Test status
Simulation time 16596061 ps
CPU time 0.8 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:44 PM PDT 24
Peak memory 215536 kb
Host smart-ff972283-cbab-41c9-a8bd-243bd75583c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152117658 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1152117658
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.3665273653
Short name T460
Test name
Test status
Simulation time 23927073 ps
CPU time 1.04 seconds
Started Mar 14 12:48:45 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 231036 kb
Host smart-c5edb007-225f-481c-8f30-2c4f093ef4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665273653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3665273653
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.782189824
Short name T346
Test name
Test status
Simulation time 36527034 ps
CPU time 1.45 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:43 PM PDT 24
Peak memory 217508 kb
Host smart-fbc2c6d4-6ce9-4869-819b-b48d74bf7f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782189824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.782189824
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.703406258
Short name T129
Test name
Test status
Simulation time 20391504 ps
CPU time 1.14 seconds
Started Mar 14 12:48:41 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 215300 kb
Host smart-edf7c2ac-a60d-407c-9b31-f24f2170aa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703406258 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.703406258
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3135328906
Short name T465
Test name
Test status
Simulation time 27568632 ps
CPU time 0.9 seconds
Started Mar 14 12:48:45 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 214996 kb
Host smart-62384793-db36-4e5c-b13f-54101931657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135328906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3135328906
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/160.edn_genbits.3535052742
Short name T378
Test name
Test status
Simulation time 34195395 ps
CPU time 1.61 seconds
Started Mar 14 12:50:08 PM PDT 24
Finished Mar 14 12:50:10 PM PDT 24
Peak memory 217492 kb
Host smart-4d935b68-4457-4e2f-ad04-0d9be3d20802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535052742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3535052742
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1022270923
Short name T546
Test name
Test status
Simulation time 39262844 ps
CPU time 1.38 seconds
Started Mar 14 12:50:01 PM PDT 24
Finished Mar 14 12:50:02 PM PDT 24
Peak memory 217432 kb
Host smart-02cdc537-d09c-4579-bcc5-09496b1a278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022270923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1022270923
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.666220289
Short name T358
Test name
Test status
Simulation time 176162421 ps
CPU time 1.52 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217732 kb
Host smart-7027d208-63b8-437f-ab36-594048f309ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666220289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.666220289
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3462282435
Short name T320
Test name
Test status
Simulation time 39109665 ps
CPU time 1.49 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 216364 kb
Host smart-89dc22a4-941f-404f-a907-2d86f3e586b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462282435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3462282435
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1502789132
Short name T719
Test name
Test status
Simulation time 230657426 ps
CPU time 2.76 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 217884 kb
Host smart-054f7708-5b9c-441a-b96b-a7dee344a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502789132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1502789132
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.1340649575
Short name T478
Test name
Test status
Simulation time 31549342 ps
CPU time 1.2 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216288 kb
Host smart-07f896da-b771-4529-b44b-5c9b27918478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340649575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1340649575
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3229762855
Short name T741
Test name
Test status
Simulation time 101043587 ps
CPU time 1.25 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217804 kb
Host smart-ad88eb4c-b9f3-4164-89f1-2ed5923f6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229762855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3229762855
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2496253796
Short name T461
Test name
Test status
Simulation time 272856974 ps
CPU time 2.73 seconds
Started Mar 14 12:50:10 PM PDT 24
Finished Mar 14 12:50:13 PM PDT 24
Peak memory 216440 kb
Host smart-8aae2504-8816-4ad2-8ac0-c54ec3f0f246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496253796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2496253796
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.914743295
Short name T417
Test name
Test status
Simulation time 55790180 ps
CPU time 1.1 seconds
Started Mar 14 12:50:08 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 215088 kb
Host smart-335fcbc0-5f60-4162-a1b0-f3df10b7c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914743295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.914743295
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3155818130
Short name T718
Test name
Test status
Simulation time 43694983 ps
CPU time 1.06 seconds
Started Mar 14 12:48:50 PM PDT 24
Finished Mar 14 12:48:51 PM PDT 24
Peak memory 215256 kb
Host smart-6510cf77-4a72-4659-842b-8e0543b99780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155818130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3155818130
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.460124137
Short name T305
Test name
Test status
Simulation time 15693052 ps
CPU time 0.89 seconds
Started Mar 14 12:48:49 PM PDT 24
Finished Mar 14 12:48:50 PM PDT 24
Peak memory 206108 kb
Host smart-b0e2b52f-b93a-4ea5-8fa4-bd1cc0d4bc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460124137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.460124137
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2015396637
Short name T119
Test name
Test status
Simulation time 11780191 ps
CPU time 0.88 seconds
Started Mar 14 12:48:51 PM PDT 24
Finished Mar 14 12:48:52 PM PDT 24
Peak memory 215372 kb
Host smart-8c755b87-bf75-4522-af2e-95be1cf2c7dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015396637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2015396637
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1859861909
Short name T466
Test name
Test status
Simulation time 32115155 ps
CPU time 1.16 seconds
Started Mar 14 12:48:48 PM PDT 24
Finished Mar 14 12:48:50 PM PDT 24
Peak memory 215940 kb
Host smart-b91c116b-432c-4c8a-913c-2ab998ef7b10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859861909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1859861909
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1592491821
Short name T121
Test name
Test status
Simulation time 25584750 ps
CPU time 1.08 seconds
Started Mar 14 12:48:54 PM PDT 24
Finished Mar 14 12:48:56 PM PDT 24
Peak memory 232240 kb
Host smart-b722111c-b73a-4a23-97ba-c1ec4d27223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592491821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1592491821
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2789074640
Short name T360
Test name
Test status
Simulation time 269023569 ps
CPU time 3.79 seconds
Started Mar 14 12:48:51 PM PDT 24
Finished Mar 14 12:48:55 PM PDT 24
Peak memory 217720 kb
Host smart-ce737822-e759-4643-a3b5-0be872563ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789074640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2789074640
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2107277849
Short name T144
Test name
Test status
Simulation time 25999211 ps
CPU time 0.92 seconds
Started Mar 14 12:48:51 PM PDT 24
Finished Mar 14 12:48:52 PM PDT 24
Peak memory 215288 kb
Host smart-0c0b67f4-d0b4-4b3f-a25b-975fedb9e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107277849 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2107277849
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3568185
Short name T739
Test name
Test status
Simulation time 24712270 ps
CPU time 0.92 seconds
Started Mar 14 12:48:40 PM PDT 24
Finished Mar 14 12:48:42 PM PDT 24
Peak memory 214928 kb
Host smart-6bab8a79-03c4-4075-8ac4-d75ac0efd9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3568185
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1870904530
Short name T5
Test name
Test status
Simulation time 1117937184 ps
CPU time 2.91 seconds
Started Mar 14 12:48:54 PM PDT 24
Finished Mar 14 12:48:57 PM PDT 24
Peak memory 216024 kb
Host smart-7e17c4d1-44b5-48f5-9320-92e54fd071e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870904530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1870904530
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3456918344
Short name T425
Test name
Test status
Simulation time 1358791832578 ps
CPU time 2261.5 seconds
Started Mar 14 12:48:51 PM PDT 24
Finished Mar 14 01:26:33 PM PDT 24
Peak memory 229124 kb
Host smart-002ede4f-f465-4a99-a749-4de1424b1eca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456918344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3456918344
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1621437032
Short name T287
Test name
Test status
Simulation time 58560311 ps
CPU time 1.14 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 219136 kb
Host smart-cd7388a6-f959-4649-8596-ba970630bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621437032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1621437032
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1763538338
Short name T733
Test name
Test status
Simulation time 252653669 ps
CPU time 1.44 seconds
Started Mar 14 12:50:10 PM PDT 24
Finished Mar 14 12:50:12 PM PDT 24
Peak memory 218292 kb
Host smart-477b123d-9652-44ed-9f11-700b4c21af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763538338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1763538338
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3047836874
Short name T632
Test name
Test status
Simulation time 73683337 ps
CPU time 1.55 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 218444 kb
Host smart-3a424fdd-335a-4ae6-af69-484501928b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047836874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3047836874
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1323597840
Short name T463
Test name
Test status
Simulation time 75428161 ps
CPU time 1.25 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 219480 kb
Host smart-5f7fb492-a35c-41c7-be12-e86bcad272f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323597840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1323597840
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.445682780
Short name T565
Test name
Test status
Simulation time 37517128 ps
CPU time 1.27 seconds
Started Mar 14 12:50:10 PM PDT 24
Finished Mar 14 12:50:12 PM PDT 24
Peak memory 217564 kb
Host smart-de25b0e9-95b0-4ded-b152-ff04bbb46f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445682780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.445682780
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2089889314
Short name T593
Test name
Test status
Simulation time 51099543 ps
CPU time 1.02 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217880 kb
Host smart-874c9b39-c8f3-49c0-953c-2b46c2876860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089889314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2089889314
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.874702053
Short name T249
Test name
Test status
Simulation time 38286262 ps
CPU time 1.22 seconds
Started Mar 14 12:50:10 PM PDT 24
Finished Mar 14 12:50:12 PM PDT 24
Peak memory 217736 kb
Host smart-ce5b7981-b38c-4e8e-b597-c8c506ee36ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874702053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.874702053
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3174765861
Short name T570
Test name
Test status
Simulation time 68428059 ps
CPU time 2.51 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:09 PM PDT 24
Peak memory 219108 kb
Host smart-a007d3b2-92a7-453d-aaab-36974cb5f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174765861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3174765861
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.172330515
Short name T357
Test name
Test status
Simulation time 74340577 ps
CPU time 2.59 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:10 PM PDT 24
Peak memory 216616 kb
Host smart-0d061ba2-ef41-4dda-8d88-d9135d7103db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172330515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.172330515
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.4251461390
Short name T188
Test name
Test status
Simulation time 162542852 ps
CPU time 1.7 seconds
Started Mar 14 12:50:01 PM PDT 24
Finished Mar 14 12:50:03 PM PDT 24
Peak memory 217416 kb
Host smart-6f9b6a6a-3e15-4e4b-939d-0e2fc2095c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251461390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4251461390
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.837056879
Short name T172
Test name
Test status
Simulation time 69094173 ps
CPU time 1.15 seconds
Started Mar 14 12:48:54 PM PDT 24
Finished Mar 14 12:48:55 PM PDT 24
Peak memory 215248 kb
Host smart-c943744a-f958-4c36-9af2-cd03de7f57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837056879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.837056879
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3452789933
Short name T753
Test name
Test status
Simulation time 43143422 ps
CPU time 0.83 seconds
Started Mar 14 12:48:50 PM PDT 24
Finished Mar 14 12:48:51 PM PDT 24
Peak memory 205808 kb
Host smart-436d6d2a-7ac1-4e7f-b7d7-48367efe25f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452789933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3452789933
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3710115978
Short name T757
Test name
Test status
Simulation time 13754378 ps
CPU time 0.94 seconds
Started Mar 14 12:48:49 PM PDT 24
Finished Mar 14 12:48:51 PM PDT 24
Peak memory 215200 kb
Host smart-c87899f0-fa8b-4afa-a655-57a3f7e1f17a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710115978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3710115978
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_genbits.1175972251
Short name T564
Test name
Test status
Simulation time 41753540 ps
CPU time 1.61 seconds
Started Mar 14 12:48:50 PM PDT 24
Finished Mar 14 12:48:52 PM PDT 24
Peak memory 217456 kb
Host smart-0c36c6f4-8faf-48a2-947a-48ea1346cc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175972251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1175972251
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2219697369
Short name T691
Test name
Test status
Simulation time 24395336 ps
CPU time 1.03 seconds
Started Mar 14 12:48:49 PM PDT 24
Finished Mar 14 12:48:51 PM PDT 24
Peak memory 223764 kb
Host smart-e1656bfd-239c-4a10-aeb8-bd1f8d9911ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219697369 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2219697369
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3124983212
Short name T387
Test name
Test status
Simulation time 54926313 ps
CPU time 0.95 seconds
Started Mar 14 12:48:50 PM PDT 24
Finished Mar 14 12:48:51 PM PDT 24
Peak memory 214984 kb
Host smart-609e56ba-147d-417e-aca7-eab47ea36660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124983212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3124983212
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1830149411
Short name T41
Test name
Test status
Simulation time 1038795161 ps
CPU time 4.04 seconds
Started Mar 14 12:48:51 PM PDT 24
Finished Mar 14 12:48:55 PM PDT 24
Peak memory 214972 kb
Host smart-76efa1e1-5f29-4197-8446-c2cbadda4509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830149411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1830149411
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1104778549
Short name T629
Test name
Test status
Simulation time 179431625512 ps
CPU time 2306.99 seconds
Started Mar 14 12:48:49 PM PDT 24
Finished Mar 14 01:27:16 PM PDT 24
Peak memory 230124 kb
Host smart-215634c0-f712-4d3e-8f09-f3f447cf7a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104778549 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1104778549
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4055642500
Short name T712
Test name
Test status
Simulation time 90277755 ps
CPU time 2.97 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217528 kb
Host smart-08b86321-be50-4ef8-ac62-b82e8d51b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055642500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4055642500
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3808269881
Short name T518
Test name
Test status
Simulation time 44815908 ps
CPU time 1.4 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218800 kb
Host smart-a0823aed-a5c5-4558-bad3-1c8252690b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808269881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3808269881
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.4140798379
Short name T430
Test name
Test status
Simulation time 45869711 ps
CPU time 1.94 seconds
Started Mar 14 12:50:08 PM PDT 24
Finished Mar 14 12:50:10 PM PDT 24
Peak memory 218332 kb
Host smart-823fa89d-af39-46c2-937f-bedce75362a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140798379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.4140798379
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1069847733
Short name T694
Test name
Test status
Simulation time 36116193 ps
CPU time 1.45 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 217764 kb
Host smart-14a20ff4-27fe-4e3e-82f6-2d2074eafcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069847733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1069847733
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3188300490
Short name T775
Test name
Test status
Simulation time 280840272 ps
CPU time 1.14 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 216272 kb
Host smart-cc1efa4b-f2a4-4503-8eca-ed6b90fd3a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188300490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3188300490
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1543695208
Short name T532
Test name
Test status
Simulation time 36221420 ps
CPU time 1.36 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218560 kb
Host smart-b6fbc161-acdb-4a53-a9f6-9c575379b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543695208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1543695208
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2730172145
Short name T803
Test name
Test status
Simulation time 74194504 ps
CPU time 1.65 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218064 kb
Host smart-e4ca6fbb-13b4-4e19-89c1-e82be0a37da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730172145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2730172145
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2503113276
Short name T343
Test name
Test status
Simulation time 155365916 ps
CPU time 1.55 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217680 kb
Host smart-7b8b17f3-4a42-4205-8e68-d61a3ed19cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503113276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2503113276
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.435614319
Short name T31
Test name
Test status
Simulation time 98193432 ps
CPU time 1.53 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218092 kb
Host smart-6b05c3cb-72df-4c31-a01d-467aac7e18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435614319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.435614319
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1326013515
Short name T239
Test name
Test status
Simulation time 264132352 ps
CPU time 1.38 seconds
Started Mar 14 12:48:50 PM PDT 24
Finished Mar 14 12:48:52 PM PDT 24
Peak memory 215116 kb
Host smart-aeb6f4f6-96d5-4ebd-9030-3233d96032ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326013515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1326013515
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1395037931
Short name T468
Test name
Test status
Simulation time 15302216 ps
CPU time 0.93 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 206216 kb
Host smart-1361596c-ed59-45b8-8c54-29b7b07ebf28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395037931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1395037931
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.4219153678
Short name T657
Test name
Test status
Simulation time 14503071 ps
CPU time 0.81 seconds
Started Mar 14 12:48:56 PM PDT 24
Finished Mar 14 12:48:57 PM PDT 24
Peak memory 215008 kb
Host smart-6ba14c66-4727-415f-b4d1-ab3ceb5cb9d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219153678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4219153678
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1578570904
Short name T155
Test name
Test status
Simulation time 97917235 ps
CPU time 1.12 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 215968 kb
Host smart-7149bb27-7cdc-4e54-ad70-a03b97ce8d77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578570904 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1578570904
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2934446144
Short name T414
Test name
Test status
Simulation time 48625193 ps
CPU time 0.81 seconds
Started Mar 14 12:48:49 PM PDT 24
Finished Mar 14 12:48:50 PM PDT 24
Peak memory 217636 kb
Host smart-66f58fd7-b034-4ff9-b850-759c860b6b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934446144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2934446144
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.168884531
Short name T4
Test name
Test status
Simulation time 23689576 ps
CPU time 1.1 seconds
Started Mar 14 12:48:51 PM PDT 24
Finished Mar 14 12:48:52 PM PDT 24
Peak memory 223748 kb
Host smart-d5af99e7-cd16-48bd-a85f-0a1852d500f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168884531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.168884531
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.419099980
Short name T164
Test name
Test status
Simulation time 17712045 ps
CPU time 1.01 seconds
Started Mar 14 12:48:49 PM PDT 24
Finished Mar 14 12:48:50 PM PDT 24
Peak memory 215028 kb
Host smart-9016e8f3-43d2-4786-aa6e-99a319cc008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419099980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.419099980
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.415612495
Short name T485
Test name
Test status
Simulation time 989501127 ps
CPU time 5.24 seconds
Started Mar 14 12:48:48 PM PDT 24
Finished Mar 14 12:48:54 PM PDT 24
Peak memory 216216 kb
Host smart-f0463013-b133-4d01-92d3-5280850acc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415612495 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.415612495
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1482161495
Short name T199
Test name
Test status
Simulation time 34508378354 ps
CPU time 756.69 seconds
Started Mar 14 12:48:47 PM PDT 24
Finished Mar 14 01:01:23 PM PDT 24
Peak memory 218052 kb
Host smart-ee91d1eb-21f9-43f6-93f0-4246a172f092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482161495 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1482161495
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1204075415
Short name T769
Test name
Test status
Simulation time 121558069 ps
CPU time 1.65 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217536 kb
Host smart-4f4b9a0c-47ed-4a63-9496-fe36d5954243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204075415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1204075415
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2464432798
Short name T572
Test name
Test status
Simulation time 49081020 ps
CPU time 1.57 seconds
Started Mar 14 12:50:10 PM PDT 24
Finished Mar 14 12:50:12 PM PDT 24
Peak memory 216360 kb
Host smart-9dc9fedf-d35e-45d5-8ab1-b934e2063d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464432798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2464432798
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1298502842
Short name T324
Test name
Test status
Simulation time 38704482 ps
CPU time 1.31 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217560 kb
Host smart-e5bbebd3-9fe7-4dfe-9aae-39919331256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298502842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1298502842
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1504050657
Short name T445
Test name
Test status
Simulation time 41266464 ps
CPU time 1.4 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 217328 kb
Host smart-f46eeec7-f215-4c3f-b11b-0817a2f658a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504050657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1504050657
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3020912530
Short name T410
Test name
Test status
Simulation time 65679051 ps
CPU time 1.1 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 218752 kb
Host smart-fa26d786-22f4-42ba-aff9-948092b95d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020912530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3020912530
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3754548414
Short name T743
Test name
Test status
Simulation time 66041457 ps
CPU time 1.32 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216252 kb
Host smart-75f1b2db-390d-4460-bf58-b24021f5087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754548414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3754548414
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3767249757
Short name T423
Test name
Test status
Simulation time 79626098 ps
CPU time 1.16 seconds
Started Mar 14 12:50:04 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 216292 kb
Host smart-0718b4ac-59cd-4381-9792-fc45709ad58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767249757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3767249757
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3587208208
Short name T281
Test name
Test status
Simulation time 121798069 ps
CPU time 2.31 seconds
Started Mar 14 12:50:07 PM PDT 24
Finished Mar 14 12:50:10 PM PDT 24
Peak memory 218980 kb
Host smart-e4cbf7a2-6f54-453b-b1a2-c199675cfb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587208208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3587208208
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1991887482
Short name T605
Test name
Test status
Simulation time 34616919 ps
CPU time 1.33 seconds
Started Mar 14 12:50:05 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218600 kb
Host smart-75ea4e4a-3630-45eb-ade9-ac1887291d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991887482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1991887482
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2846331078
Short name T735
Test name
Test status
Simulation time 57936662 ps
CPU time 1.14 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215184 kb
Host smart-bb614e47-c61d-4048-bb29-8f6cb7e69c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846331078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2846331078
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.833306660
Short name T682
Test name
Test status
Simulation time 15323593 ps
CPU time 0.92 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 206204 kb
Host smart-2a7ac5fa-ea4a-459b-8603-5b4675381a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833306660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.833306660
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1697238311
Short name T34
Test name
Test status
Simulation time 36149521 ps
CPU time 0.9 seconds
Started Mar 14 12:48:26 PM PDT 24
Finished Mar 14 12:48:28 PM PDT 24
Peak memory 214964 kb
Host smart-fb148ca3-8174-4651-8b84-75bf972c878d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697238311 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1697238311
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3129811187
Short name T751
Test name
Test status
Simulation time 35134099 ps
CPU time 1.23 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 218768 kb
Host smart-7db9f726-f808-4396-86ec-cbb59efff317
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129811187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3129811187
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1968019214
Short name T86
Test name
Test status
Simulation time 34268794 ps
CPU time 1 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 219748 kb
Host smart-a0fb62b8-2ea1-4cbe-b034-d2528d7791cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968019214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1968019214
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.903028456
Short name T542
Test name
Test status
Simulation time 60128420 ps
CPU time 1.35 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 217424 kb
Host smart-a63d0a61-ff1c-44f6-83d6-af5e41a58ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903028456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.903028456
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2653220786
Short name T370
Test name
Test status
Simulation time 23842818 ps
CPU time 1.02 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 223712 kb
Host smart-8e09cd82-a514-4762-980a-c1cae994d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653220786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2653220786
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1342917949
Short name T264
Test name
Test status
Simulation time 18734791 ps
CPU time 1.09 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 206524 kb
Host smart-3d876498-21b0-4b53-b0c1-bd5c52021298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342917949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1342917949
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2506450015
Short name T615
Test name
Test status
Simulation time 26151335 ps
CPU time 0.96 seconds
Started Mar 14 12:48:26 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 214952 kb
Host smart-49a8c2b6-1170-46da-a404-bb1e021fccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506450015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2506450015
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2547390069
Short name T826
Test name
Test status
Simulation time 226588573 ps
CPU time 4.6 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:30 PM PDT 24
Peak memory 216180 kb
Host smart-b4ac5eac-1408-44a1-92a5-009c343861ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547390069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2547390069
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4241828637
Short name T755
Test name
Test status
Simulation time 59957843243 ps
CPU time 623.07 seconds
Started Mar 14 12:48:20 PM PDT 24
Finished Mar 14 12:58:43 PM PDT 24
Peak memory 221080 kb
Host smart-3fa55e37-d2ac-418f-8c7c-59a97379b14f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241828637 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4241828637
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2046190305
Short name T649
Test name
Test status
Simulation time 51329266 ps
CPU time 1.19 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 215204 kb
Host smart-4f222cc2-a33b-44ea-903f-8d1147e5968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046190305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2046190305
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2543725274
Short name T446
Test name
Test status
Simulation time 15408574 ps
CPU time 0.86 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 205540 kb
Host smart-e41be6af-9349-401f-a7f6-56b1d1c78338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543725274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2543725274
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.264758437
Short name T306
Test name
Test status
Simulation time 11717968 ps
CPU time 0.88 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 215144 kb
Host smart-bd540415-d134-4570-9b1c-0b5a4f1ebc9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264758437 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.264758437
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1353667103
Short name T95
Test name
Test status
Simulation time 102962520 ps
CPU time 1.05 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:04 PM PDT 24
Peak memory 215988 kb
Host smart-7713fd73-8bef-4a0e-91cc-82805722f0f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353667103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1353667103
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1667744906
Short name T415
Test name
Test status
Simulation time 31136073 ps
CPU time 0.85 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 217432 kb
Host smart-84acf497-8871-4856-9b96-00b4fbe53241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667744906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1667744906
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.4001501731
Short name T442
Test name
Test status
Simulation time 137020035 ps
CPU time 1.22 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 216252 kb
Host smart-37dad6f3-309d-4825-ad6c-b3a7c57c84fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001501731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.4001501731
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1855203627
Short name T421
Test name
Test status
Simulation time 29185055 ps
CPU time 1.03 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 223780 kb
Host smart-727c25c6-eca9-4d21-a27d-b6dbc6c705c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855203627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1855203627
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1831106133
Short name T650
Test name
Test status
Simulation time 50355825 ps
CPU time 0.89 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 214984 kb
Host smart-45fdcab1-9b06-477f-b24c-d9196360c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831106133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1831106133
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1605923621
Short name T816
Test name
Test status
Simulation time 441181998 ps
CPU time 4.82 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:04 PM PDT 24
Peak memory 216288 kb
Host smart-8dd43afc-91a6-4575-9536-644fe8989dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605923621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1605923621
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.295514181
Short name T197
Test name
Test status
Simulation time 164171670431 ps
CPU time 966.78 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 01:05:04 PM PDT 24
Peak memory 223300 kb
Host smart-cd8c7349-4f43-45cc-96a5-fa263cd11477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295514181 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.295514181
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3094470032
Short name T294
Test name
Test status
Simulation time 69767091 ps
CPU time 1.07 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:16 PM PDT 24
Peak memory 216292 kb
Host smart-c4690543-4e95-46b5-b093-7387a7fae5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094470032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3094470032
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3498033399
Short name T674
Test name
Test status
Simulation time 54096730 ps
CPU time 1.01 seconds
Started Mar 14 12:50:13 PM PDT 24
Finished Mar 14 12:50:15 PM PDT 24
Peak memory 216204 kb
Host smart-d168029f-f9b7-4333-9d2f-5f498dca3939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498033399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3498033399
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3600848078
Short name T524
Test name
Test status
Simulation time 28078499 ps
CPU time 1.25 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 219008 kb
Host smart-70be221c-b86a-4b08-a185-16b5f3b9c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600848078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3600848078
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.504532200
Short name T296
Test name
Test status
Simulation time 37967278 ps
CPU time 1.31 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 217356 kb
Host smart-0f9b63a9-1d0d-4759-b06a-afe19f19f98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504532200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.504532200
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4263205368
Short name T732
Test name
Test status
Simulation time 73235354 ps
CPU time 2.58 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:21 PM PDT 24
Peak memory 219180 kb
Host smart-cd688717-1acc-43da-a3a1-059821f11d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263205368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4263205368
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1285553628
Short name T666
Test name
Test status
Simulation time 50992056 ps
CPU time 1.54 seconds
Started Mar 14 12:50:15 PM PDT 24
Finished Mar 14 12:50:20 PM PDT 24
Peak memory 218456 kb
Host smart-95bfeb16-4c97-4fd9-ba34-0b49d199ca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285553628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1285553628
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.629323114
Short name T374
Test name
Test status
Simulation time 39052571 ps
CPU time 1.39 seconds
Started Mar 14 12:50:24 PM PDT 24
Finished Mar 14 12:50:27 PM PDT 24
Peak memory 217476 kb
Host smart-88f36a5c-f4e0-4335-abb2-7429561e83b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629323114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.629323114
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2080094802
Short name T381
Test name
Test status
Simulation time 23772957 ps
CPU time 1.16 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 218992 kb
Host smart-493cc5fb-eb59-4dc9-a818-f241e94770ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080094802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2080094802
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.44677243
Short name T686
Test name
Test status
Simulation time 39545207 ps
CPU time 1.56 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 217392 kb
Host smart-aae12698-9fdb-4a33-b704-8d492c1b1590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44677243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.44677243
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4058601523
Short name T552
Test name
Test status
Simulation time 2318636285 ps
CPU time 72.63 seconds
Started Mar 14 12:50:19 PM PDT 24
Finished Mar 14 12:51:35 PM PDT 24
Peak memory 216564 kb
Host smart-dc09544e-34c9-4a4e-9d34-4a04a8cab146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058601523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4058601523
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3681624997
Short name T683
Test name
Test status
Simulation time 28916865 ps
CPU time 1.17 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:04 PM PDT 24
Peak memory 215260 kb
Host smart-8e80ad36-a4bb-4901-bd57-1996f0b843bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681624997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3681624997
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.934072572
Short name T385
Test name
Test status
Simulation time 108980846 ps
CPU time 0.83 seconds
Started Mar 14 12:48:56 PM PDT 24
Finished Mar 14 12:48:57 PM PDT 24
Peak memory 205232 kb
Host smart-b04844dd-6279-4873-9a4c-fa92db8d43ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934072572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.934072572
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3041490466
Short name T723
Test name
Test status
Simulation time 33833447 ps
CPU time 0.82 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 215124 kb
Host smart-79777db8-70d4-4069-b164-b9eb74b24afc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041490466 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3041490466
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1387577679
Short name T96
Test name
Test status
Simulation time 246548258 ps
CPU time 1.09 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:05 PM PDT 24
Peak memory 216092 kb
Host smart-ba09c1c5-6f4e-4e04-8d2d-e7c55ba47c7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387577679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1387577679
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3771105584
Short name T74
Test name
Test status
Simulation time 43734740 ps
CPU time 0.93 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 216352 kb
Host smart-8936c4d7-df53-4309-94ef-20b190a243cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771105584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3771105584
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2153546583
Short name T462
Test name
Test status
Simulation time 152132569 ps
CPU time 3.3 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:06 PM PDT 24
Peak memory 216616 kb
Host smart-ba49d61b-599f-4ff3-a9cd-448f0a8d330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153546583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2153546583
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2168803115
Short name T711
Test name
Test status
Simulation time 25130613 ps
CPU time 0.93 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:04 PM PDT 24
Peak memory 215364 kb
Host smart-01fa6f6d-35d9-4e1c-a3b0-c2274bae1639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168803115 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2168803115
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2580603099
Short name T515
Test name
Test status
Simulation time 30373967 ps
CPU time 0.98 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 214976 kb
Host smart-6781f9f3-421b-4b61-9134-4043e498d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580603099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2580603099
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.523782216
Short name T610
Test name
Test status
Simulation time 1703253946 ps
CPU time 3.12 seconds
Started Mar 14 12:48:56 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 216036 kb
Host smart-3d65de1c-7d6e-43d9-bb7b-ccc32463309e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523782216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.523782216
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.163055227
Short name T195
Test name
Test status
Simulation time 35256082182 ps
CPU time 802.74 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 01:02:22 PM PDT 24
Peak memory 217632 kb
Host smart-c5120fbe-1229-4a2f-9bc6-6549f9fedda8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163055227 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.163055227
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1429699150
Short name T432
Test name
Test status
Simulation time 38490290 ps
CPU time 1.31 seconds
Started Mar 14 12:50:19 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 216248 kb
Host smart-63c36bb6-ccae-426b-b70c-8da90add837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429699150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1429699150
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.767476825
Short name T14
Test name
Test status
Simulation time 51296597 ps
CPU time 1.66 seconds
Started Mar 14 12:50:26 PM PDT 24
Finished Mar 14 12:50:28 PM PDT 24
Peak memory 218940 kb
Host smart-0a77021b-2467-435d-bc22-40d8f0af82fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767476825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.767476825
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3306645476
Short name T279
Test name
Test status
Simulation time 163519294 ps
CPU time 1.26 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:17 PM PDT 24
Peak memory 217656 kb
Host smart-d3d7378b-b730-4284-8d6b-60cddb0286df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306645476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3306645476
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2051691856
Short name T276
Test name
Test status
Simulation time 92737131 ps
CPU time 1.41 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:25 PM PDT 24
Peak memory 216440 kb
Host smart-fe285906-b376-4a26-a979-cccc0dc4f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051691856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2051691856
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1407860355
Short name T292
Test name
Test status
Simulation time 99796213 ps
CPU time 2.01 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:25 PM PDT 24
Peak memory 218980 kb
Host smart-3c189cad-ee32-49f1-9ce8-ec476d045944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407860355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1407860355
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.71488791
Short name T169
Test name
Test status
Simulation time 234802266 ps
CPU time 3.4 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 219268 kb
Host smart-bda637ce-7775-4abc-96e1-96084afdb8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71488791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.71488791
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1065086156
Short name T810
Test name
Test status
Simulation time 160794248 ps
CPU time 1 seconds
Started Mar 14 12:50:15 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 216248 kb
Host smart-448e2d20-e8f0-4393-ae9b-4125c51b8fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065086156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1065086156
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1984875413
Short name T383
Test name
Test status
Simulation time 39018314 ps
CPU time 1.64 seconds
Started Mar 14 12:50:15 PM PDT 24
Finished Mar 14 12:50:21 PM PDT 24
Peak memory 217584 kb
Host smart-6a36393d-1204-4816-8d84-f1dcda60408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984875413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1984875413
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.523186632
Short name T49
Test name
Test status
Simulation time 40145047 ps
CPU time 1.09 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 214956 kb
Host smart-408be0a7-18b1-4a3e-9a70-c368d137b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523186632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.523186632
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1227257140
Short name T12
Test name
Test status
Simulation time 42596620 ps
CPU time 1.28 seconds
Started Mar 14 12:50:24 PM PDT 24
Finished Mar 14 12:50:27 PM PDT 24
Peak memory 216680 kb
Host smart-f67cb1d3-07d7-40f0-b47d-1ddbd9d9073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227257140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1227257140
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.2837861115
Short name T502
Test name
Test status
Simulation time 46143638 ps
CPU time 0.88 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 206336 kb
Host smart-ecac1ae8-958a-48fe-a918-0bd048d6fe5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837861115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2837861115
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.74444953
Short name T8
Test name
Test status
Simulation time 40687101 ps
CPU time 1.01 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:05 PM PDT 24
Peak memory 229440 kb
Host smart-5ebb3d9a-25b5-4ad5-8d4f-b522c40c68e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74444953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.74444953
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2434842638
Short name T688
Test name
Test status
Simulation time 277860917 ps
CPU time 1.24 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 216324 kb
Host smart-af647ab1-e5d5-460c-bcf8-5099669afe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434842638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2434842638
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2931384996
Short name T132
Test name
Test status
Simulation time 25996574 ps
CPU time 0.94 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:58 PM PDT 24
Peak memory 215380 kb
Host smart-a0f189d0-d4a1-4035-9cc2-2f7784d42c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931384996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2931384996
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1616515210
Short name T480
Test name
Test status
Simulation time 24504856 ps
CPU time 0.88 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 214912 kb
Host smart-cdfd5812-64a3-40a5-b0b5-f3e771eaece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616515210 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1616515210
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.343644821
Short name T213
Test name
Test status
Simulation time 121811170 ps
CPU time 2.79 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 218964 kb
Host smart-2d5e7196-dce5-4239-9f1d-db02b88094fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343644821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.343644821
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2234405522
Short name T592
Test name
Test status
Simulation time 48954541004 ps
CPU time 539.25 seconds
Started Mar 14 12:49:04 PM PDT 24
Finished Mar 14 12:58:04 PM PDT 24
Peak memory 217492 kb
Host smart-8b16f69c-8a61-4ffd-ac8e-cad85899b9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234405522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2234405522
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2163369932
Short name T823
Test name
Test status
Simulation time 59964836 ps
CPU time 1.35 seconds
Started Mar 14 12:50:11 PM PDT 24
Finished Mar 14 12:50:12 PM PDT 24
Peak memory 217412 kb
Host smart-00a844d6-9cb9-4844-9eb6-cdc467e27489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163369932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2163369932
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3020986648
Short name T796
Test name
Test status
Simulation time 62325933 ps
CPU time 1.3 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:25 PM PDT 24
Peak memory 216552 kb
Host smart-b1437a62-5bdb-47fb-b9ca-92750b7b9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020986648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3020986648
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.742311561
Short name T752
Test name
Test status
Simulation time 134840309 ps
CPU time 1.87 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:16 PM PDT 24
Peak memory 216660 kb
Host smart-5e8cd024-fbd0-45e3-abec-32322361f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742311561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.742311561
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2505388523
Short name T484
Test name
Test status
Simulation time 131853431 ps
CPU time 1.05 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:20 PM PDT 24
Peak memory 216408 kb
Host smart-c298d2bb-8f24-426f-adfa-3ae0f07f48f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505388523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2505388523
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.732931298
Short name T571
Test name
Test status
Simulation time 48291057 ps
CPU time 1.51 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:25 PM PDT 24
Peak memory 217364 kb
Host smart-edb25dc2-7624-465d-a1ba-3f71ea7db1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732931298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.732931298
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1411095471
Short name T33
Test name
Test status
Simulation time 47947232 ps
CPU time 1.1 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 217308 kb
Host smart-c55a2364-71eb-4424-939d-820b1b888080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411095471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1411095471
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1512186344
Short name T574
Test name
Test status
Simulation time 53604359 ps
CPU time 1.22 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 217580 kb
Host smart-c0a8806d-6a10-4b09-9ee4-ba23b029991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512186344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1512186344
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3447986668
Short name T668
Test name
Test status
Simulation time 61439564 ps
CPU time 1.63 seconds
Started Mar 14 12:50:26 PM PDT 24
Finished Mar 14 12:50:28 PM PDT 24
Peak memory 217588 kb
Host smart-60c09cf4-6a0a-4846-ac57-5d9a483c6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447986668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3447986668
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2970870749
Short name T623
Test name
Test status
Simulation time 77307100 ps
CPU time 1.17 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217896 kb
Host smart-48f884e3-5708-477a-a622-42288edfdbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970870749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2970870749
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.322086023
Short name T786
Test name
Test status
Simulation time 46292915 ps
CPU time 0.88 seconds
Started Mar 14 12:48:56 PM PDT 24
Finished Mar 14 12:48:57 PM PDT 24
Peak memory 206292 kb
Host smart-368840b9-f60d-4cfd-8bfa-825f72ca0f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322086023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.322086023
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1871090713
Short name T118
Test name
Test status
Simulation time 11183351 ps
CPU time 0.94 seconds
Started Mar 14 12:49:04 PM PDT 24
Finished Mar 14 12:49:06 PM PDT 24
Peak memory 215272 kb
Host smart-1904223d-3b4a-49ed-9386-bc379a261eba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871090713 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1871090713
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2771393909
Short name T785
Test name
Test status
Simulation time 50694283 ps
CPU time 1.11 seconds
Started Mar 14 12:49:01 PM PDT 24
Finished Mar 14 12:49:02 PM PDT 24
Peak memory 217560 kb
Host smart-e72ff9d4-ada4-4e6b-bc65-86b3828c8278
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771393909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2771393909
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3023239279
Short name T521
Test name
Test status
Simulation time 30512813 ps
CPU time 0.83 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 217636 kb
Host smart-e1c51532-6076-4235-a0ef-63345c9627eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023239279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3023239279
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4150805882
Short name T582
Test name
Test status
Simulation time 81792225 ps
CPU time 1.11 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 12:48:59 PM PDT 24
Peak memory 217504 kb
Host smart-25570ded-422e-457e-8c0a-e61b585ddffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150805882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4150805882
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1545701279
Short name T16
Test name
Test status
Simulation time 24830988 ps
CPU time 1.11 seconds
Started Mar 14 12:49:03 PM PDT 24
Finished Mar 14 12:49:04 PM PDT 24
Peak memory 232256 kb
Host smart-dd4a4dc3-6721-41d8-be69-233551ab85c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545701279 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1545701279
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.682646136
Short name T709
Test name
Test status
Simulation time 18398910 ps
CPU time 0.95 seconds
Started Mar 14 12:48:59 PM PDT 24
Finished Mar 14 12:49:01 PM PDT 24
Peak memory 214932 kb
Host smart-2c1b36bd-d6ca-43fd-bb95-c3e1e45fcd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682646136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.682646136
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.458677158
Short name T495
Test name
Test status
Simulation time 270318655 ps
CPU time 1.94 seconds
Started Mar 14 12:48:54 PM PDT 24
Finished Mar 14 12:48:57 PM PDT 24
Peak memory 214804 kb
Host smart-5982cfb7-ce56-4fa1-9c54-f6731fb21a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458677158 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.458677158
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2299340771
Short name T431
Test name
Test status
Simulation time 273893615127 ps
CPU time 616.29 seconds
Started Mar 14 12:49:01 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 218736 kb
Host smart-dafc5cf3-bd3c-4f20-a95a-23ee8c0d561d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299340771 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2299340771
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3117957659
Short name T497
Test name
Test status
Simulation time 70314743 ps
CPU time 1.14 seconds
Started Mar 14 12:50:12 PM PDT 24
Finished Mar 14 12:50:14 PM PDT 24
Peak memory 218808 kb
Host smart-8e275888-37a8-4af5-a113-2fd9fec4257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117957659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3117957659
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.477444943
Short name T702
Test name
Test status
Simulation time 57436741 ps
CPU time 1.15 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 218884 kb
Host smart-ed6c41ad-ee69-419e-8293-b207fe861612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477444943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.477444943
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2341120063
Short name T642
Test name
Test status
Simulation time 51512853 ps
CPU time 1.64 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217528 kb
Host smart-39eca03a-2a97-4a9e-b4e9-a2ab7f9b6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341120063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2341120063
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1619703591
Short name T312
Test name
Test status
Simulation time 25338864 ps
CPU time 1.09 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 216300 kb
Host smart-25f36f0c-dc2e-4d09-bddb-2c8f07f392e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619703591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1619703591
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2690849996
Short name T619
Test name
Test status
Simulation time 85676322 ps
CPU time 1.11 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 219152 kb
Host smart-a45fd0fb-f635-43eb-bbd6-515bbd737920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690849996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2690849996
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1127523331
Short name T37
Test name
Test status
Simulation time 48393830 ps
CPU time 1.34 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:18 PM PDT 24
Peak memory 217532 kb
Host smart-bfdd005c-6530-4907-bd34-9b908c726660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127523331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1127523331
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1280488724
Short name T821
Test name
Test status
Simulation time 59337068 ps
CPU time 1.16 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:18 PM PDT 24
Peak memory 216240 kb
Host smart-505219bd-9b1e-4c29-9ede-a4aadfc8aa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280488724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1280488724
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2396728930
Short name T549
Test name
Test status
Simulation time 28475685 ps
CPU time 1.22 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217416 kb
Host smart-1fd3e4df-92cc-455a-925c-13cc7e7ed3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396728930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2396728930
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.211457725
Short name T245
Test name
Test status
Simulation time 40855316 ps
CPU time 1.6 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 216440 kb
Host smart-20c26802-caba-4a3d-b63d-2523d2238a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211457725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.211457725
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.402148571
Short name T422
Test name
Test status
Simulation time 110113644 ps
CPU time 1.33 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 217844 kb
Host smart-c849fae1-2a36-4695-bd86-1fab3d0f7e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402148571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.402148571
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3316702988
Short name T269
Test name
Test status
Simulation time 23708889 ps
CPU time 1.18 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 215192 kb
Host smart-a8183b91-90a2-437e-b570-2509ff7a4c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316702988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3316702988
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1858849845
Short name T647
Test name
Test status
Simulation time 30760079 ps
CPU time 0.81 seconds
Started Mar 14 12:49:04 PM PDT 24
Finished Mar 14 12:49:05 PM PDT 24
Peak memory 205252 kb
Host smart-ff23cd6c-0e6a-4df6-b838-92aecf8882e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858849845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1858849845
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_err.1071067490
Short name T116
Test name
Test status
Simulation time 27628020 ps
CPU time 0.91 seconds
Started Mar 14 12:48:58 PM PDT 24
Finished Mar 14 12:49:00 PM PDT 24
Peak memory 231956 kb
Host smart-9ec5df5e-3620-416b-b537-14202598807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071067490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1071067490
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3343166411
Short name T687
Test name
Test status
Simulation time 76670865 ps
CPU time 1.46 seconds
Started Mar 14 12:49:00 PM PDT 24
Finished Mar 14 12:49:02 PM PDT 24
Peak memory 218544 kb
Host smart-9fc64480-4b90-4998-b028-48b6712d8451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343166411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3343166411
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.4101227270
Short name T405
Test name
Test status
Simulation time 43015842 ps
CPU time 0.93 seconds
Started Mar 14 12:49:04 PM PDT 24
Finished Mar 14 12:49:05 PM PDT 24
Peak memory 214952 kb
Host smart-20e43f76-4869-41d5-bf0d-0efc05e500cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101227270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4101227270
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3714913470
Short name T754
Test name
Test status
Simulation time 124675157 ps
CPU time 1.98 seconds
Started Mar 14 12:49:00 PM PDT 24
Finished Mar 14 12:49:02 PM PDT 24
Peak memory 214976 kb
Host smart-8b3912fb-6287-4e48-9f53-2cf4c5352a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714913470 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3714913470
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3255097882
Short name T167
Test name
Test status
Simulation time 364902564326 ps
CPU time 1455.65 seconds
Started Mar 14 12:48:57 PM PDT 24
Finished Mar 14 01:13:14 PM PDT 24
Peak memory 222936 kb
Host smart-a5b4331e-7cbb-49fb-944b-68a4e6a9f0f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255097882 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3255097882
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4180842058
Short name T643
Test name
Test status
Simulation time 66523202 ps
CPU time 1.37 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 217824 kb
Host smart-1173836b-704b-4de0-a291-c64e7ca80263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180842058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4180842058
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.4091337034
Short name T418
Test name
Test status
Simulation time 41183083 ps
CPU time 1.45 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 219196 kb
Host smart-daba6189-4455-4eef-b7d8-14564309e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091337034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.4091337034
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1333902459
Short name T750
Test name
Test status
Simulation time 833096407 ps
CPU time 5.69 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:27 PM PDT 24
Peak memory 219196 kb
Host smart-90c636e3-0433-4e73-9d23-a26e1b575127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333902459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1333902459
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3635030156
Short name T341
Test name
Test status
Simulation time 35578819 ps
CPU time 1.25 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 216328 kb
Host smart-1adaa95d-0106-4262-8ac8-ef04a1c6d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635030156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3635030156
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1348103320
Short name T827
Test name
Test status
Simulation time 108724113 ps
CPU time 1.21 seconds
Started Mar 14 12:50:15 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 217664 kb
Host smart-8295bdab-4a4e-4053-bede-2033cd8e3884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348103320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1348103320
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.38024328
Short name T599
Test name
Test status
Simulation time 116622795 ps
CPU time 1.21 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 217772 kb
Host smart-e7df246c-7826-4186-b80a-b6f8758a5870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38024328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.38024328
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3788588235
Short name T390
Test name
Test status
Simulation time 82181810 ps
CPU time 1.24 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 218020 kb
Host smart-6eb9cbf6-b446-418f-93fc-c0d70de38d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788588235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3788588235
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3816447539
Short name T569
Test name
Test status
Simulation time 35796251 ps
CPU time 1.34 seconds
Started Mar 14 12:50:25 PM PDT 24
Finished Mar 14 12:50:28 PM PDT 24
Peak memory 216464 kb
Host smart-e5fbd7e9-4a2e-424e-84f1-259614022f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816447539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3816447539
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2061198330
Short name T684
Test name
Test status
Simulation time 35606984 ps
CPU time 1.28 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:21 PM PDT 24
Peak memory 217384 kb
Host smart-207cb1af-6132-4a88-8041-54314c27ec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061198330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2061198330
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2692559428
Short name T695
Test name
Test status
Simulation time 34963414 ps
CPU time 1.31 seconds
Started Mar 14 12:50:21 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 218768 kb
Host smart-c51aa460-f2ed-478d-8e72-84ab4d518dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692559428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2692559428
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1666171969
Short name T830
Test name
Test status
Simulation time 45562814 ps
CPU time 1.36 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:12 PM PDT 24
Peak memory 215160 kb
Host smart-be3ab75b-6964-4e2c-82b1-90bf035a3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666171969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1666171969
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1760381144
Short name T373
Test name
Test status
Simulation time 122137247 ps
CPU time 0.87 seconds
Started Mar 14 12:49:12 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 206496 kb
Host smart-fb20ff99-1492-40e8-a711-4897ba734c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760381144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1760381144
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.914608093
Short name T587
Test name
Test status
Simulation time 11805760 ps
CPU time 0.88 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 215432 kb
Host smart-c2104b69-efaf-435e-bb22-f1a6270463a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914608093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.914608093
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1281996089
Short name T693
Test name
Test status
Simulation time 34036520 ps
CPU time 1.17 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 217380 kb
Host smart-4cd2a285-83b3-4bfa-b75f-9d2bba696a29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281996089 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1281996089
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.4098318123
Short name T567
Test name
Test status
Simulation time 23761021 ps
CPU time 1.21 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 217628 kb
Host smart-b3bb99c0-84f5-4e40-ace4-ed206976b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098318123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4098318123
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.277333898
Short name T13
Test name
Test status
Simulation time 84023309 ps
CPU time 1.23 seconds
Started Mar 14 12:49:05 PM PDT 24
Finished Mar 14 12:49:06 PM PDT 24
Peak memory 216584 kb
Host smart-b4954754-5113-403d-99ab-faeac29c10aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277333898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.277333898
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2483463746
Short name T563
Test name
Test status
Simulation time 23325580 ps
CPU time 1.12 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 223748 kb
Host smart-9fd59209-4e87-4640-bcd6-5b55672c493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483463746 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2483463746
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1148163119
Short name T447
Test name
Test status
Simulation time 65471884 ps
CPU time 0.93 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 214844 kb
Host smart-1ca78541-156e-42cf-8cd3-4c9ffacab459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148163119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1148163119
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3617412474
Short name T787
Test name
Test status
Simulation time 206240674 ps
CPU time 1.55 seconds
Started Mar 14 12:49:06 PM PDT 24
Finished Mar 14 12:49:08 PM PDT 24
Peak memory 206752 kb
Host smart-df8aecdd-b52b-40a8-922e-06c64669678c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617412474 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3617412474
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.25844306
Short name T29
Test name
Test status
Simulation time 66773836711 ps
CPU time 1680.4 seconds
Started Mar 14 12:49:06 PM PDT 24
Finished Mar 14 01:17:07 PM PDT 24
Peak memory 225316 kb
Host smart-7fc93f85-08d9-4df4-a84f-9b609347bb23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844306 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.25844306
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.260165125
Short name T807
Test name
Test status
Simulation time 94866161 ps
CPU time 1.25 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217708 kb
Host smart-f8ba9282-41de-4d01-b20d-db0c4ff5f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260165125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.260165125
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.81531160
Short name T283
Test name
Test status
Simulation time 46631347 ps
CPU time 1.58 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 217304 kb
Host smart-a421b7ef-74ed-4fa2-94d6-c60de0d6887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81531160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.81531160
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.439855712
Short name T474
Test name
Test status
Simulation time 160515425 ps
CPU time 2.09 seconds
Started Mar 14 12:50:26 PM PDT 24
Finished Mar 14 12:50:29 PM PDT 24
Peak memory 218964 kb
Host smart-aa234ef6-f766-4f1c-8c5d-c817d8d24e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439855712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.439855712
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1102803096
Short name T640
Test name
Test status
Simulation time 288095100 ps
CPU time 3.32 seconds
Started Mar 14 12:50:13 PM PDT 24
Finished Mar 14 12:50:18 PM PDT 24
Peak memory 216496 kb
Host smart-ad61e01b-e8b1-4b2c-995b-3cd2e72e8fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102803096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1102803096
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2281681103
Short name T317
Test name
Test status
Simulation time 157552271 ps
CPU time 3.25 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:26 PM PDT 24
Peak memory 216500 kb
Host smart-2e1b12c8-4d01-43b7-afa5-64ff31de143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281681103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2281681103
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.364063331
Short name T352
Test name
Test status
Simulation time 39061785 ps
CPU time 1.25 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 217340 kb
Host smart-b60c2cb5-b595-4c9d-92f6-af1c5c1462ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364063331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.364063331
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3198580832
Short name T469
Test name
Test status
Simulation time 177406944 ps
CPU time 1.19 seconds
Started Mar 14 12:50:21 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 216376 kb
Host smart-6053c40d-dc42-4cd3-bd6f-fca792136748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198580832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3198580832
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3707788354
Short name T777
Test name
Test status
Simulation time 62740325 ps
CPU time 1.51 seconds
Started Mar 14 12:50:12 PM PDT 24
Finished Mar 14 12:50:13 PM PDT 24
Peak memory 217468 kb
Host smart-2e2f83b6-5fee-43b8-a22b-b9098105105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707788354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3707788354
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1977294885
Short name T543
Test name
Test status
Simulation time 66678001 ps
CPU time 2.02 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:26 PM PDT 24
Peak memory 217656 kb
Host smart-f52d9460-ca15-458e-b994-563a7b397865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977294885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1977294885
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3139714273
Short name T419
Test name
Test status
Simulation time 89554797 ps
CPU time 1.22 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 219044 kb
Host smart-db8f0cb5-d22d-4dc6-80b9-8f85b5e0132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139714273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3139714273
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.363008127
Short name T547
Test name
Test status
Simulation time 55172697 ps
CPU time 1.3 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 215176 kb
Host smart-c7be0310-fa27-4500-a89c-874aec385c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363008127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.363008127
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3929544662
Short name T510
Test name
Test status
Simulation time 30299523 ps
CPU time 0.96 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:12 PM PDT 24
Peak memory 206524 kb
Host smart-890140f8-2e50-471d-9097-d7ef0f8cfc7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929544662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3929544662
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3018691978
Short name T441
Test name
Test status
Simulation time 25983315 ps
CPU time 0.83 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 215008 kb
Host smart-cfe99d2e-d299-49c7-bad1-8e351e0f98f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018691978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3018691978
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1805160291
Short name T161
Test name
Test status
Simulation time 28962224 ps
CPU time 1.32 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 223972 kb
Host smart-fe5815f3-8c9b-47ca-b416-7345ab827e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805160291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1805160291
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1507182140
Short name T822
Test name
Test status
Simulation time 47943739 ps
CPU time 1.21 seconds
Started Mar 14 12:49:06 PM PDT 24
Finished Mar 14 12:49:07 PM PDT 24
Peak memory 216568 kb
Host smart-83d72056-fdc6-4a07-a193-bf178ab6fe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507182140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1507182140
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.2633375007
Short name T692
Test name
Test status
Simulation time 39117683 ps
CPU time 0.87 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 214940 kb
Host smart-a52b0ece-444b-47a0-84ca-66cd9bbed2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633375007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2633375007
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1281908515
Short name T554
Test name
Test status
Simulation time 1041751554 ps
CPU time 4.31 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:16 PM PDT 24
Peak memory 216120 kb
Host smart-c4c77164-8658-4746-b11c-fd7e1dcdbc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281908515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1281908515
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4160009108
Short name T545
Test name
Test status
Simulation time 469866382049 ps
CPU time 1848.1 seconds
Started Mar 14 12:49:12 PM PDT 24
Finished Mar 14 01:20:01 PM PDT 24
Peak memory 227564 kb
Host smart-baf05b9b-2d15-4f03-ae60-9b17353782da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160009108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4160009108
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1083775082
Short name T240
Test name
Test status
Simulation time 28479680 ps
CPU time 1.21 seconds
Started Mar 14 12:50:12 PM PDT 24
Finished Mar 14 12:50:14 PM PDT 24
Peak memory 217676 kb
Host smart-c34ea533-41a3-4b9e-a7e1-3dbe66aa9118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083775082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1083775082
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1854655058
Short name T538
Test name
Test status
Simulation time 143144749 ps
CPU time 1.19 seconds
Started Mar 14 12:50:19 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 216384 kb
Host smart-78d754cf-a1dd-4488-81c7-1a0137c2bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854655058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1854655058
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.982929260
Short name T395
Test name
Test status
Simulation time 60404963 ps
CPU time 1.28 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 217300 kb
Host smart-56c52041-38ab-43d6-9e0d-ffcf9514af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982929260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.982929260
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1176505118
Short name T639
Test name
Test status
Simulation time 45166046 ps
CPU time 1.61 seconds
Started Mar 14 12:50:19 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 216380 kb
Host smart-ea3b00e3-1e68-4105-807c-d2198a43778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176505118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1176505118
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3470702557
Short name T369
Test name
Test status
Simulation time 35821565 ps
CPU time 0.96 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 217416 kb
Host smart-c5d25c97-4b2d-4bae-b844-cfe110c68e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470702557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3470702557
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2542801184
Short name T696
Test name
Test status
Simulation time 136204251 ps
CPU time 0.97 seconds
Started Mar 14 12:50:13 PM PDT 24
Finished Mar 14 12:50:14 PM PDT 24
Peak memory 216332 kb
Host smart-1f4e2743-cdbe-44a5-9155-46857693d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542801184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2542801184
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4011540020
Short name T762
Test name
Test status
Simulation time 51206149 ps
CPU time 2 seconds
Started Mar 14 12:50:21 PM PDT 24
Finished Mar 14 12:50:25 PM PDT 24
Peak memory 217624 kb
Host smart-6330c2a2-b85e-4d84-b51b-81c94f0ff13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011540020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4011540020
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2180668060
Short name T140
Test name
Test status
Simulation time 44912234 ps
CPU time 1.82 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217828 kb
Host smart-0844ce0e-ba11-45ae-aecf-e8376546c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180668060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2180668060
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4157062264
Short name T407
Test name
Test status
Simulation time 40628061 ps
CPU time 1.27 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 217560 kb
Host smart-eb765dad-2ae0-4cf2-8e61-453a7daefbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157062264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4157062264
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3397471106
Short name T335
Test name
Test status
Simulation time 72769428 ps
CPU time 1.47 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 217856 kb
Host smart-a392fb67-77e3-46d0-b591-81693d112249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397471106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3397471106
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2310076294
Short name T553
Test name
Test status
Simulation time 27349736 ps
CPU time 1.22 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:12 PM PDT 24
Peak memory 215348 kb
Host smart-256ba60f-e699-4ad4-8374-26257760ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310076294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2310076294
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.671857147
Short name T322
Test name
Test status
Simulation time 26554562 ps
CPU time 1.06 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 206140 kb
Host smart-19d91948-8218-4214-a214-8f0c8e5c537b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671857147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.671857147
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3973922037
Short name T797
Test name
Test status
Simulation time 157098856 ps
CPU time 0.88 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215400 kb
Host smart-6d7205a8-088e-4386-b527-54845f08c14a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973922037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3973922037
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2536474259
Short name T7
Test name
Test status
Simulation time 25340420 ps
CPU time 1.01 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 218840 kb
Host smart-c04c6e37-c8e5-47f3-88f9-ce3b9fb46eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536474259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2536474259
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2174739633
Short name T772
Test name
Test status
Simulation time 295762713 ps
CPU time 3.76 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:14 PM PDT 24
Peak memory 219444 kb
Host smart-cbf16eb9-8833-4ef9-94e2-2791bd9a9ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174739633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2174739633
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2234710235
Short name T348
Test name
Test status
Simulation time 34722674 ps
CPU time 0.97 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 223416 kb
Host smart-f5a528fc-d40e-467e-ba40-3d0877bdc66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234710235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2234710235
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3660225827
Short name T504
Test name
Test status
Simulation time 16712469 ps
CPU time 0.99 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215000 kb
Host smart-f200087d-9645-43c3-aadf-fa388a44a823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660225827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3660225827
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2694846971
Short name T211
Test name
Test status
Simulation time 54309897 ps
CPU time 1.07 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 205392 kb
Host smart-fa69eef4-2d50-4100-a592-9b0fb04294ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694846971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2694846971
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1162677691
Short name T790
Test name
Test status
Simulation time 532087197794 ps
CPU time 1163.26 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 01:08:32 PM PDT 24
Peak memory 223340 kb
Host smart-0d75f6c5-0f4d-46fb-949f-d7b1cc1fa0e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162677691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1162677691
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.700991022
Short name T828
Test name
Test status
Simulation time 227179783 ps
CPU time 3.34 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:26 PM PDT 24
Peak memory 216452 kb
Host smart-3741bbb4-b49d-4e5f-921c-8dbd30dae582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700991022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.700991022
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2257867873
Short name T607
Test name
Test status
Simulation time 53354596 ps
CPU time 1.24 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217556 kb
Host smart-189f5806-fce4-4a6d-8651-391497285cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257867873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2257867873
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.550036612
Short name T523
Test name
Test status
Simulation time 49121371 ps
CPU time 1.6 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 216360 kb
Host smart-911e3da1-bb36-4c95-9953-3f4f5d05cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550036612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.550036612
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4036424950
Short name T277
Test name
Test status
Simulation time 38882865 ps
CPU time 1.39 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 216648 kb
Host smart-6b655509-fd26-4bdc-a56f-7acdc3304f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036424950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4036424950
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.936721685
Short name T288
Test name
Test status
Simulation time 73371852 ps
CPU time 1.22 seconds
Started Mar 14 12:50:19 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 218520 kb
Host smart-7d8bb2f3-823c-435a-b653-87756c941f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936721685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.936721685
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3493524439
Short name T620
Test name
Test status
Simulation time 78205779 ps
CPU time 1.36 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:21 PM PDT 24
Peak memory 218244 kb
Host smart-6e36250e-a10b-4cb0-9cfb-95f235195d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493524439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3493524439
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2599162293
Short name T338
Test name
Test status
Simulation time 62019659 ps
CPU time 1.35 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 217376 kb
Host smart-f7cc6df1-ab92-4f26-a51d-77098af3d054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599162293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2599162293
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2932470437
Short name T824
Test name
Test status
Simulation time 51873826 ps
CPU time 1.17 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 216312 kb
Host smart-acd1d8db-79be-486a-9383-19a04a0b3b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932470437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2932470437
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.192727877
Short name T503
Test name
Test status
Simulation time 38059054 ps
CPU time 1.37 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 216444 kb
Host smart-ea6e099d-20e2-4372-a1e2-aff96d771b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192727877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.192727877
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.243911483
Short name T731
Test name
Test status
Simulation time 56008173 ps
CPU time 1.39 seconds
Started Mar 14 12:50:13 PM PDT 24
Finished Mar 14 12:50:15 PM PDT 24
Peak memory 217500 kb
Host smart-488ddf76-465c-4e46-8395-0ce8b80fb38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243911483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.243911483
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2388212674
Short name T177
Test name
Test status
Simulation time 46576289 ps
CPU time 1.19 seconds
Started Mar 14 12:49:07 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 215256 kb
Host smart-cad349b9-21c3-4f2e-89a4-39d558289d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388212674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2388212674
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4058202019
Short name T626
Test name
Test status
Simulation time 20654456 ps
CPU time 0.85 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 205568 kb
Host smart-e8778160-1ebf-4423-9f09-b25221991e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058202019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4058202019
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1315936743
Short name T606
Test name
Test status
Simulation time 14033625 ps
CPU time 1 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215248 kb
Host smart-914b9711-214a-45c7-916a-528037f01fff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315936743 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1315936743
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3459342546
Short name T63
Test name
Test status
Simulation time 38721494 ps
CPU time 1.24 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 217268 kb
Host smart-adc49d3f-5177-4b43-b6c2-68b9683be7c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459342546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3459342546
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.883458788
Short name T80
Test name
Test status
Simulation time 22398919 ps
CPU time 1.15 seconds
Started Mar 14 12:49:07 PM PDT 24
Finished Mar 14 12:49:08 PM PDT 24
Peak memory 229400 kb
Host smart-ec32ba38-6116-4152-aad0-244d961f0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883458788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.883458788
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3710986392
Short name T677
Test name
Test status
Simulation time 66906023 ps
CPU time 1.16 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 216456 kb
Host smart-25aca3be-9de1-491e-906c-587e5b2ea60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710986392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3710986392
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.74017431
Short name T205
Test name
Test status
Simulation time 21538522 ps
CPU time 1.07 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215372 kb
Host smart-67969083-f572-4c81-ac42-d51fc22f40ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74017431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.74017431
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2201015151
Short name T616
Test name
Test status
Simulation time 48887551 ps
CPU time 0.99 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 214976 kb
Host smart-be3be2e2-952e-41d8-a6fe-140fdf3f9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201015151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2201015151
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2582363213
Short name T805
Test name
Test status
Simulation time 203000946 ps
CPU time 4.32 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:16 PM PDT 24
Peak memory 216480 kb
Host smart-ae6d1587-c30c-4a1d-ab8d-6b8b72b177e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582363213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2582363213
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.640479250
Short name T196
Test name
Test status
Simulation time 274718525065 ps
CPU time 1677.61 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 01:17:08 PM PDT 24
Peak memory 223716 kb
Host smart-b3db888f-c471-40f7-8555-933dc812a051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640479250 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.640479250
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.927177745
Short name T295
Test name
Test status
Simulation time 47149492 ps
CPU time 1.51 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:16 PM PDT 24
Peak memory 217616 kb
Host smart-d8b9b135-5e57-4017-a4ea-9e00c92c5f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927177745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.927177745
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3594246471
Short name T361
Test name
Test status
Simulation time 67764367 ps
CPU time 1.24 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 218780 kb
Host smart-9512f1f9-7134-4d98-876f-638e78870905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594246471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3594246471
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3775401650
Short name T386
Test name
Test status
Simulation time 54524620 ps
CPU time 0.96 seconds
Started Mar 14 12:50:15 PM PDT 24
Finished Mar 14 12:50:20 PM PDT 24
Peak memory 216388 kb
Host smart-d3821f6a-4d42-4e1d-adb0-b0616abf5f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775401650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3775401650
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3581784828
Short name T275
Test name
Test status
Simulation time 49575239 ps
CPU time 1.91 seconds
Started Mar 14 12:50:15 PM PDT 24
Finished Mar 14 12:50:20 PM PDT 24
Peak memory 217588 kb
Host smart-b6cb3480-9be3-45d5-8653-de6a16f6a84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581784828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3581784828
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3068282486
Short name T467
Test name
Test status
Simulation time 64944001 ps
CPU time 1.14 seconds
Started Mar 14 12:50:16 PM PDT 24
Finished Mar 14 12:50:19 PM PDT 24
Peak memory 218784 kb
Host smart-ac3f5edd-9d31-4b9a-b3b7-a1fc868d892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068282486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3068282486
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.193767914
Short name T519
Test name
Test status
Simulation time 50152152 ps
CPU time 1.8 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217468 kb
Host smart-aaed9201-a23a-48bf-bad4-5cd6fa67e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193767914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.193767914
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2926800058
Short name T284
Test name
Test status
Simulation time 81185507 ps
CPU time 1.26 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:16 PM PDT 24
Peak memory 217728 kb
Host smart-c1eda9d9-fa52-45cb-8c6d-fa028b7a342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926800058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2926800058
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.545142009
Short name T2
Test name
Test status
Simulation time 31039239 ps
CPU time 1.37 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217332 kb
Host smart-5fcf9d95-6958-4085-b36e-cf9f8ceb1abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545142009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.545142009
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2690226274
Short name T271
Test name
Test status
Simulation time 64518313 ps
CPU time 1.05 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 216336 kb
Host smart-67f49639-f0f7-4bdf-9302-908e2f40d2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690226274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2690226274
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2128053804
Short name T477
Test name
Test status
Simulation time 191761767 ps
CPU time 2.85 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 218936 kb
Host smart-b566847d-8f8c-44ae-9147-1a6ff26a058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128053804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2128053804
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.218463318
Short name T110
Test name
Test status
Simulation time 24978723 ps
CPU time 1.12 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215120 kb
Host smart-c4a11ad1-e4d8-46e6-8e77-8bb0a4df8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218463318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.218463318
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1729825904
Short name T716
Test name
Test status
Simulation time 20675787 ps
CPU time 0.79 seconds
Started Mar 14 12:49:07 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 205384 kb
Host smart-9fefcfc0-2335-4d08-912e-b406c945f67a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729825904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1729825904
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1047143493
Short name T48
Test name
Test status
Simulation time 19064986 ps
CPU time 0.85 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 215376 kb
Host smart-f1ee13ff-82d1-4e8d-8ee9-afacf39bab4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047143493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1047143493
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2197157991
Short name T516
Test name
Test status
Simulation time 24435514 ps
CPU time 1.05 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 231016 kb
Host smart-fb27874c-291b-49c3-96b4-c54fbb1bfc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197157991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2197157991
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.641326875
Short name T646
Test name
Test status
Simulation time 121016620 ps
CPU time 1.48 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 217656 kb
Host smart-20e98589-530a-489b-863c-c5db6d01e59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641326875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.641326875
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2706675066
Short name T54
Test name
Test status
Simulation time 22765751 ps
CPU time 1.05 seconds
Started Mar 14 12:49:05 PM PDT 24
Finished Mar 14 12:49:06 PM PDT 24
Peak memory 214944 kb
Host smart-5eb224d8-0001-4bc2-b55c-b4257448c775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706675066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2706675066
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3127228093
Short name T413
Test name
Test status
Simulation time 30515940 ps
CPU time 0.93 seconds
Started Mar 14 12:49:07 PM PDT 24
Finished Mar 14 12:49:08 PM PDT 24
Peak memory 214976 kb
Host smart-f9e815a8-e72a-4088-bde7-4cbd09df7e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127228093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3127228093
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1956206017
Short name T778
Test name
Test status
Simulation time 599769123 ps
CPU time 3.59 seconds
Started Mar 14 12:49:07 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215016 kb
Host smart-469d144b-d609-4108-8f73-6ea58817740b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956206017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1956206017
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2608708456
Short name T489
Test name
Test status
Simulation time 31672565163 ps
CPU time 210.45 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:52:40 PM PDT 24
Peak memory 215212 kb
Host smart-fcb51de1-e73b-4853-939b-c4bba903433c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608708456 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2608708456
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3712557406
Short name T25
Test name
Test status
Simulation time 46821825 ps
CPU time 1.24 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 216344 kb
Host smart-b36f1b31-1e85-4b36-8023-77216e003ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712557406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3712557406
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2679302612
Short name T725
Test name
Test status
Simulation time 58977448 ps
CPU time 1.92 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217672 kb
Host smart-0b05c9d9-02d0-4eae-92e9-6b3f53d9a7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679302612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2679302612
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.152906347
Short name T697
Test name
Test status
Simulation time 37415325 ps
CPU time 1.07 seconds
Started Mar 14 12:50:14 PM PDT 24
Finished Mar 14 12:50:17 PM PDT 24
Peak memory 216220 kb
Host smart-62881886-99a7-4c15-8a93-761e672d649e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152906347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.152906347
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.406263683
Short name T319
Test name
Test status
Simulation time 43794806 ps
CPU time 1.31 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 217512 kb
Host smart-f705d661-3734-44a5-beba-67a9988082a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406263683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.406263683
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.20952414
Short name T774
Test name
Test status
Simulation time 277298556 ps
CPU time 1.18 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:23 PM PDT 24
Peak memory 218988 kb
Host smart-94cb6a52-fdff-4dab-b1b9-997d3a02b7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20952414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.20952414
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2361248049
Short name T726
Test name
Test status
Simulation time 63124035 ps
CPU time 1.31 seconds
Started Mar 14 12:50:18 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 218268 kb
Host smart-daf634b0-1bd8-4366-840d-e853060114e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361248049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2361248049
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3788976678
Short name T590
Test name
Test status
Simulation time 42445090 ps
CPU time 1.44 seconds
Started Mar 14 12:50:17 PM PDT 24
Finished Mar 14 12:50:21 PM PDT 24
Peak memory 217620 kb
Host smart-540076ae-1095-4259-bb57-13e6807a33ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788976678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3788976678
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2919235455
Short name T392
Test name
Test status
Simulation time 80067347 ps
CPU time 1.4 seconds
Started Mar 14 12:50:20 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 218008 kb
Host smart-df105f4b-d5cf-40e3-b43a-cbe0b26af102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919235455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2919235455
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.573554706
Short name T457
Test name
Test status
Simulation time 970406882 ps
CPU time 5.38 seconds
Started Mar 14 12:50:38 PM PDT 24
Finished Mar 14 12:50:44 PM PDT 24
Peak memory 218932 kb
Host smart-6726db87-020e-46f2-bbb0-fa82af5b3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573554706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.573554706
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1921029654
Short name T612
Test name
Test status
Simulation time 76304190 ps
CPU time 1.06 seconds
Started Mar 14 12:50:24 PM PDT 24
Finished Mar 14 12:50:26 PM PDT 24
Peak memory 216524 kb
Host smart-c4dc0e7e-41d9-4f2f-ab40-99988aa9304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921029654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1921029654
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2936345569
Short name T661
Test name
Test status
Simulation time 69861784 ps
CPU time 1.07 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 215216 kb
Host smart-8b0dc73b-8936-4f1b-be1b-c1250931ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936345569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2936345569
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2015098417
Short name T382
Test name
Test status
Simulation time 25490147 ps
CPU time 0.86 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206560 kb
Host smart-6333d21a-dad7-43d4-832b-7514d2db6b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015098417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2015098417
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2326783834
Short name T344
Test name
Test status
Simulation time 28745081 ps
CPU time 0.79 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:23 PM PDT 24
Peak memory 215160 kb
Host smart-61eb057f-bf8f-4330-b507-6c8945ddaa35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326783834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2326783834
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2629357585
Short name T148
Test name
Test status
Simulation time 54190131 ps
CPU time 1.54 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 216008 kb
Host smart-ad1bb2fa-48db-4534-aa75-f7d0c758f55a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629357585 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2629357585
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1543303990
Short name T825
Test name
Test status
Simulation time 24198990 ps
CPU time 0.87 seconds
Started Mar 14 12:48:20 PM PDT 24
Finished Mar 14 12:48:21 PM PDT 24
Peak memory 217252 kb
Host smart-1b95d056-7b92-4c45-82d7-69d5984378e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543303990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1543303990
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.983651962
Short name T671
Test name
Test status
Simulation time 45740627 ps
CPU time 1.25 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 217448 kb
Host smart-da0fa222-d6f4-4e7d-8fc4-98d373172da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983651962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.983651962
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.734884364
Short name T168
Test name
Test status
Simulation time 27628150 ps
CPU time 1 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215052 kb
Host smart-a85ab6ed-d690-44be-b170-928a179f98e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734884364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.734884364
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3576831097
Short name T783
Test name
Test status
Simulation time 164967906 ps
CPU time 0.88 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206608 kb
Host smart-63117ec0-0ac2-443c-9504-0da6511bab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576831097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3576831097
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.118306089
Short name T21
Test name
Test status
Simulation time 165193484 ps
CPU time 3.2 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 233924 kb
Host smart-b368d193-bbd4-43cc-a3db-804eeb7d0a42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118306089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.118306089
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.93840444
Short name T314
Test name
Test status
Simulation time 19364746 ps
CPU time 0.96 seconds
Started Mar 14 12:48:26 PM PDT 24
Finished Mar 14 12:48:28 PM PDT 24
Peak memory 214936 kb
Host smart-1bdc30ca-dc44-4eaf-ad63-1e0c4b226631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93840444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.93840444
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.419448924
Short name T568
Test name
Test status
Simulation time 1838144502 ps
CPU time 3.1 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 216236 kb
Host smart-0507575d-8fdd-4c59-9e27-f4c9cb731e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419448924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.419448924
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert_test.1978535241
Short name T588
Test name
Test status
Simulation time 41305170 ps
CPU time 0.83 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 206384 kb
Host smart-6002d7dd-4c48-423a-8b9b-2372544bdeb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978535241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1978535241
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2121421613
Short name T39
Test name
Test status
Simulation time 36386291 ps
CPU time 0.81 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:12 PM PDT 24
Peak memory 215028 kb
Host smart-42ca2b1d-c9f0-459f-8232-a52c45762729
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121421613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2121421613
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2059752545
Short name T255
Test name
Test status
Simulation time 97668348 ps
CPU time 1.13 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:12 PM PDT 24
Peak memory 216216 kb
Host smart-d8b8df56-8203-43e6-942c-1b60a59ccaae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059752545 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2059752545
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3997842376
Short name T87
Test name
Test status
Simulation time 39450568 ps
CPU time 1.21 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 229396 kb
Host smart-654e05f4-15be-4a27-afa8-24425fe18718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997842376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3997842376
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1329858071
Short name T596
Test name
Test status
Simulation time 59987176 ps
CPU time 2.24 seconds
Started Mar 14 12:49:12 PM PDT 24
Finished Mar 14 12:49:15 PM PDT 24
Peak memory 217628 kb
Host smart-635c44ca-d8b7-4ce2-91dc-0ada998c8457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329858071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1329858071
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.507568316
Short name T429
Test name
Test status
Simulation time 34587343 ps
CPU time 0.9 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 215052 kb
Host smart-8ef6d4df-ce43-4f00-95cc-47dce76a3454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507568316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.507568316
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1205501992
Short name T601
Test name
Test status
Simulation time 29381678 ps
CPU time 0.91 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 214892 kb
Host smart-0fe5f4ef-46f5-4761-b070-27160abfebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205501992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1205501992
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4144200196
Short name T171
Test name
Test status
Simulation time 293989360 ps
CPU time 5.44 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:14 PM PDT 24
Peak memory 216216 kb
Host smart-d94e4a92-7657-4823-a234-7ebd14133041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144200196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4144200196
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2101462970
Short name T614
Test name
Test status
Simulation time 294440059001 ps
CPU time 889.25 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 01:03:58 PM PDT 24
Peak memory 223348 kb
Host smart-614375cb-2fd2-43de-85cb-ae5d734448c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101462970 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2101462970
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1248783161
Short name T268
Test name
Test status
Simulation time 103584447 ps
CPU time 1.18 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 215236 kb
Host smart-4010ad79-2ae5-430a-987b-44167d55cec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248783161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1248783161
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1762514635
Short name T704
Test name
Test status
Simulation time 36458379 ps
CPU time 0.85 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 205308 kb
Host smart-2bf8c8bd-2073-435d-ab67-0f6535ae7e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762514635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1762514635
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2865641951
Short name T113
Test name
Test status
Simulation time 41238682 ps
CPU time 0.87 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:10 PM PDT 24
Peak memory 215536 kb
Host smart-337bd80b-1c48-4b4e-9d69-d6b75e50c1a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865641951 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2865641951
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3316759968
Short name T62
Test name
Test status
Simulation time 430109706 ps
CPU time 1.02 seconds
Started Mar 14 12:49:14 PM PDT 24
Finished Mar 14 12:49:15 PM PDT 24
Peak memory 216076 kb
Host smart-ef69e30e-a0fe-48b9-a35c-36d3d3697b09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316759968 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3316759968
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4286421142
Short name T61
Test name
Test status
Simulation time 60546591 ps
CPU time 1.06 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 219928 kb
Host smart-5a1cb20f-cac8-4d0b-a2d9-3a80c317558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286421142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4286421142
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.250099525
Short name T540
Test name
Test status
Simulation time 308761983 ps
CPU time 2.64 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 218772 kb
Host smart-0f31c7d9-fd36-479d-8e63-44ae271518d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250099525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.250099525
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2725950807
Short name T438
Test name
Test status
Simulation time 21196955 ps
CPU time 1.28 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 223740 kb
Host smart-b5f868fe-e502-42e4-b466-abac157b5309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725950807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2725950807
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1317203418
Short name T548
Test name
Test status
Simulation time 18081492 ps
CPU time 0.99 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 214916 kb
Host smart-0f4f23d4-7786-496c-b33b-915d24465b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317203418 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1317203418
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1626026001
Short name T273
Test name
Test status
Simulation time 357483391 ps
CPU time 3.97 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 216392 kb
Host smart-f820933f-7c7e-4d68-a600-b98f4f8fa2af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626026001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1626026001
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4028223549
Short name T377
Test name
Test status
Simulation time 164659074572 ps
CPU time 2250.95 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 01:26:43 PM PDT 24
Peak memory 229228 kb
Host smart-948d1d28-371e-4560-bdba-26c573ce444e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028223549 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4028223549
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.346749188
Short name T580
Test name
Test status
Simulation time 36500639 ps
CPU time 1.18 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 215248 kb
Host smart-44f20a4a-58c5-403b-923d-c59088c9ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346749188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.346749188
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3273731393
Short name T439
Test name
Test status
Simulation time 113334934 ps
CPU time 1.12 seconds
Started Mar 14 12:49:15 PM PDT 24
Finished Mar 14 12:49:16 PM PDT 24
Peak memory 206240 kb
Host smart-d6e38e65-6f82-4f57-b8d4-fb4a261addb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273731393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3273731393
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1532621634
Short name T831
Test name
Test status
Simulation time 76455425 ps
CPU time 0.85 seconds
Started Mar 14 12:49:14 PM PDT 24
Finished Mar 14 12:49:15 PM PDT 24
Peak memory 215052 kb
Host smart-9dc9b8fb-157c-4233-bf94-8ebb803f5157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532621634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1532621634
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2717615498
Short name T600
Test name
Test status
Simulation time 25853073 ps
CPU time 1.03 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 216396 kb
Host smart-b4bead9c-f293-4945-9121-f956f0141d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717615498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2717615498
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1955904717
Short name T561
Test name
Test status
Simulation time 45793888 ps
CPU time 1.41 seconds
Started Mar 14 12:49:07 PM PDT 24
Finished Mar 14 12:49:08 PM PDT 24
Peak memory 217380 kb
Host smart-92d5789e-c662-4735-b2de-7929e351dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955904717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1955904717
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2182316692
Short name T804
Test name
Test status
Simulation time 38107809 ps
CPU time 0.88 seconds
Started Mar 14 12:49:10 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 214888 kb
Host smart-18a0848d-d5b2-401c-b00f-9752595d2f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182316692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2182316692
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1652978986
Short name T165
Test name
Test status
Simulation time 80153539 ps
CPU time 0.88 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:49:09 PM PDT 24
Peak memory 214924 kb
Host smart-6c687512-525d-4b94-b32d-f04a786fe28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652978986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1652978986
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2953536404
Short name T618
Test name
Test status
Simulation time 311107187 ps
CPU time 3.53 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:15 PM PDT 24
Peak memory 214984 kb
Host smart-0ba995aa-ccf2-47d8-81ca-ce99a7073414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953536404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2953536404
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3238594935
Short name T191
Test name
Test status
Simulation time 26182467029 ps
CPU time 588.81 seconds
Started Mar 14 12:49:08 PM PDT 24
Finished Mar 14 12:58:58 PM PDT 24
Peak memory 217980 kb
Host smart-f56ec378-82c4-4bff-b808-88fc7961ad3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238594935 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3238594935
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.2792888457
Short name T539
Test name
Test status
Simulation time 20562962 ps
CPU time 0.8 seconds
Started Mar 14 12:49:20 PM PDT 24
Finished Mar 14 12:49:21 PM PDT 24
Peak memory 205468 kb
Host smart-966f610a-fa20-4b71-817b-4150f42f0d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792888457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2792888457
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2414527510
Short name T151
Test name
Test status
Simulation time 78406941 ps
CPU time 0.81 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 12:49:17 PM PDT 24
Peak memory 215360 kb
Host smart-7c33e592-22ad-4eab-8735-ddcc9ef43a24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414527510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2414527510
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1070958955
Short name T311
Test name
Test status
Simulation time 76474441 ps
CPU time 1.04 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 217500 kb
Host smart-64777ad0-c2a5-4116-926d-968d86d3f8c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070958955 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1070958955
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3637927841
Short name T102
Test name
Test status
Simulation time 61622012 ps
CPU time 1.09 seconds
Started Mar 14 12:49:17 PM PDT 24
Finished Mar 14 12:49:18 PM PDT 24
Peak memory 218832 kb
Host smart-0bca0c45-fef1-4ea3-b200-284a0284e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637927841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3637927841
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.671093249
Short name T586
Test name
Test status
Simulation time 57580429 ps
CPU time 1.31 seconds
Started Mar 14 12:49:09 PM PDT 24
Finished Mar 14 12:49:11 PM PDT 24
Peak memory 218480 kb
Host smart-bad678e9-1400-4403-99d3-6a537f88506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671093249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.671093249
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2664343433
Short name T364
Test name
Test status
Simulation time 26928681 ps
CPU time 0.94 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 215068 kb
Host smart-98238252-05b2-499e-bd7c-ab901b7709c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664343433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2664343433
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.599127444
Short name T402
Test name
Test status
Simulation time 21440324 ps
CPU time 0.95 seconds
Started Mar 14 12:49:11 PM PDT 24
Finished Mar 14 12:49:13 PM PDT 24
Peak memory 214968 kb
Host smart-6069aa90-c1de-4f35-a1be-5d56429a533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599127444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.599127444
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2795699268
Short name T748
Test name
Test status
Simulation time 975203611 ps
CPU time 3.69 seconds
Started Mar 14 12:49:12 PM PDT 24
Finished Mar 14 12:49:16 PM PDT 24
Peak memory 216232 kb
Host smart-c42b192e-0334-4a9a-b7d8-8a5529ae39ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795699268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2795699268
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.359331013
Short name T527
Test name
Test status
Simulation time 31177293847 ps
CPU time 796.57 seconds
Started Mar 14 12:49:12 PM PDT 24
Finished Mar 14 01:02:29 PM PDT 24
Peak memory 217764 kb
Host smart-2568a8e3-0b1b-496e-9272-eff9798b1932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359331013 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.359331013
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.4236957041
Short name T173
Test name
Test status
Simulation time 28945004 ps
CPU time 1.13 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 12:49:19 PM PDT 24
Peak memory 215216 kb
Host smart-64ee1805-b3df-401b-9848-0f9170c68af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236957041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4236957041
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1936190487
Short name T724
Test name
Test status
Simulation time 49580946 ps
CPU time 0.9 seconds
Started Mar 14 12:49:20 PM PDT 24
Finished Mar 14 12:49:21 PM PDT 24
Peak memory 206208 kb
Host smart-ba30fdf3-50c0-45ed-b332-eeb35484e689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936190487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1936190487
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.4243188204
Short name T776
Test name
Test status
Simulation time 12467305 ps
CPU time 0.95 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 12:49:17 PM PDT 24
Peak memory 215448 kb
Host smart-fce09c1b-3e20-4b6c-a42f-b2719ff1fb84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243188204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4243188204
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2062550887
Short name T323
Test name
Test status
Simulation time 36168124 ps
CPU time 1.3 seconds
Started Mar 14 12:49:20 PM PDT 24
Finished Mar 14 12:49:22 PM PDT 24
Peak memory 217524 kb
Host smart-39097aa0-6ddd-42a8-8a65-26391846b07c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062550887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2062550887
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3361752357
Short name T506
Test name
Test status
Simulation time 31380217 ps
CPU time 0.95 seconds
Started Mar 14 12:49:21 PM PDT 24
Finished Mar 14 12:49:22 PM PDT 24
Peak memory 218820 kb
Host smart-f6ffa78a-4382-43a7-b396-a51403bb3736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361752357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3361752357
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3685376566
Short name T307
Test name
Test status
Simulation time 56544204 ps
CPU time 1.98 seconds
Started Mar 14 12:49:15 PM PDT 24
Finished Mar 14 12:49:17 PM PDT 24
Peak memory 217564 kb
Host smart-d47dc1dd-1bdd-4011-a2a3-5396c8e340ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685376566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3685376566
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3984230526
Short name T345
Test name
Test status
Simulation time 36990960 ps
CPU time 0.85 seconds
Started Mar 14 12:49:20 PM PDT 24
Finished Mar 14 12:49:21 PM PDT 24
Peak memory 214948 kb
Host smart-55f1970b-d422-491c-9348-f99efdd943c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984230526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3984230526
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2753780986
Short name T819
Test name
Test status
Simulation time 27627033 ps
CPU time 0.94 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 214916 kb
Host smart-6fc2893c-fb19-4aa9-acd1-0327696f44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753780986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2753780986
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.5912143
Short name T350
Test name
Test status
Simulation time 276554653 ps
CPU time 3.28 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:22 PM PDT 24
Peak memory 214992 kb
Host smart-a0644f3f-2cd4-4fba-a95d-78b68804a771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5912143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.5912143
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.915522140
Short name T720
Test name
Test status
Simulation time 383829655126 ps
CPU time 782.71 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 01:02:19 PM PDT 24
Peak memory 221004 kb
Host smart-ac8d314d-b3b7-417e-b969-94a10081a5d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915522140 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.915522140
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.4036870479
Short name T443
Test name
Test status
Simulation time 42912219 ps
CPU time 0.92 seconds
Started Mar 14 12:49:22 PM PDT 24
Finished Mar 14 12:49:23 PM PDT 24
Peak memory 206448 kb
Host smart-24500f66-d804-49c5-925b-ac555d666fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036870479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4036870479
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.4074352197
Short name T179
Test name
Test status
Simulation time 10268496 ps
CPU time 0.84 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 214996 kb
Host smart-e4972c34-a1eb-4ec0-8fee-d5b994d94aa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074352197 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4074352197
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1744989384
Short name T69
Test name
Test status
Simulation time 59428275 ps
CPU time 1.18 seconds
Started Mar 14 12:49:22 PM PDT 24
Finished Mar 14 12:49:23 PM PDT 24
Peak memory 216044 kb
Host smart-e5d8beda-b222-49b7-8719-aa215a4b6927
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744989384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1744989384
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4034734946
Short name T509
Test name
Test status
Simulation time 19931880 ps
CPU time 1 seconds
Started Mar 14 12:49:17 PM PDT 24
Finished Mar 14 12:49:18 PM PDT 24
Peak memory 217624 kb
Host smart-b2636b20-538b-446f-9ded-8a60107bec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034734946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4034734946
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1878849124
Short name T388
Test name
Test status
Simulation time 130304097 ps
CPU time 1.04 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 216272 kb
Host smart-ac33acbf-bc7d-4cf7-b50b-81a7db753bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878849124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1878849124
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3698148168
Short name T130
Test name
Test status
Simulation time 30548533 ps
CPU time 0.9 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 215328 kb
Host smart-4183b228-9edb-45f6-ae4c-d686c2c309ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698148168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3698148168
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4227565524
Short name T332
Test name
Test status
Simulation time 19982149 ps
CPU time 0.99 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 12:49:19 PM PDT 24
Peak memory 214904 kb
Host smart-5bb9ca35-ed7e-43fa-8af4-a474f3746747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227565524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4227565524
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2189435024
Short name T272
Test name
Test status
Simulation time 525544426 ps
CPU time 3.24 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 219120 kb
Host smart-3eddd18e-2a08-44b9-9ca8-3005b01ba3d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189435024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2189435024
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.272848669
Short name T434
Test name
Test status
Simulation time 42832017044 ps
CPU time 708.91 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 01:01:07 PM PDT 24
Peak memory 223432 kb
Host smart-482c32d6-6d49-4d0f-9769-f3607117b529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272848669 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.272848669
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3423341238
Short name T65
Test name
Test status
Simulation time 23821934 ps
CPU time 1.23 seconds
Started Mar 14 12:49:17 PM PDT 24
Finished Mar 14 12:49:19 PM PDT 24
Peak memory 215236 kb
Host smart-d972a702-b44e-48b6-87c5-5e723412f033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423341238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3423341238
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1837483208
Short name T384
Test name
Test status
Simulation time 37750512 ps
CPU time 0.85 seconds
Started Mar 14 12:49:23 PM PDT 24
Finished Mar 14 12:49:24 PM PDT 24
Peak memory 206112 kb
Host smart-c4f228be-1eed-44f3-9392-8847ebb621e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837483208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1837483208
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1168544968
Short name T181
Test name
Test status
Simulation time 12791702 ps
CPU time 0.89 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 215016 kb
Host smart-4d4d86ed-6a5d-4462-9588-c244a41510a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168544968 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1168544968
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.1144484636
Short name T156
Test name
Test status
Simulation time 74225288 ps
CPU time 1.05 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 12:49:17 PM PDT 24
Peak memory 214840 kb
Host smart-259523ef-79bd-4aa7-b73d-fe04bc65044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144484636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1144484636
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2751173983
Short name T690
Test name
Test status
Simulation time 56830244 ps
CPU time 2.08 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:22 PM PDT 24
Peak memory 216776 kb
Host smart-459327e2-0511-434c-b38c-6b383d74e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751173983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2751173983
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3490992485
Short name T362
Test name
Test status
Simulation time 20967428 ps
CPU time 1.17 seconds
Started Mar 14 12:49:23 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 223728 kb
Host smart-72a8e05d-e647-46f2-bddd-7e7b29097492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490992485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3490992485
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1908555684
Short name T375
Test name
Test status
Simulation time 36038678 ps
CPU time 0.95 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 214988 kb
Host smart-d53da093-8b76-4d11-b225-e0aa6ff1e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908555684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1908555684
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2458631657
Short name T303
Test name
Test status
Simulation time 907366880 ps
CPU time 2.07 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 216312 kb
Host smart-c6fbe308-dd0f-40d8-a07b-e6f1f419bef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458631657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2458631657
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2628442642
Short name T800
Test name
Test status
Simulation time 712057464313 ps
CPU time 2972.67 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 01:38:51 PM PDT 24
Peak memory 229664 kb
Host smart-fb36b294-2803-4ed5-8c8b-c81e091ffde0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628442642 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2628442642
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3888400379
Short name T261
Test name
Test status
Simulation time 40502232 ps
CPU time 1.13 seconds
Started Mar 14 12:49:23 PM PDT 24
Finished Mar 14 12:49:24 PM PDT 24
Peak memory 215208 kb
Host smart-fa8bfd1f-f418-4ff3-b101-936ac8c44a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888400379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3888400379
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.215946699
Short name T556
Test name
Test status
Simulation time 33124864 ps
CPU time 0.95 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 206480 kb
Host smart-23564a14-b5e3-442a-8504-fa0e7e4acdbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215946699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.215946699
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1635060411
Short name T122
Test name
Test status
Simulation time 29595337 ps
CPU time 0.84 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 215392 kb
Host smart-59e562d0-bb94-4ee6-bc7d-ef8c560f7313
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635060411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1635060411
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.3450651450
Short name T701
Test name
Test status
Simulation time 48982057 ps
CPU time 0.93 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 12:49:17 PM PDT 24
Peak memory 231848 kb
Host smart-6adab4c6-ccbc-4f60-b392-330adff05f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450651450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3450651450
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2364879115
Short name T331
Test name
Test status
Simulation time 39751896 ps
CPU time 1.66 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 12:49:17 PM PDT 24
Peak memory 216260 kb
Host smart-7413b02a-49a8-4582-ad8f-16abf76a9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364879115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2364879115
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1090429897
Short name T660
Test name
Test status
Simulation time 22247610 ps
CPU time 1.17 seconds
Started Mar 14 12:49:22 PM PDT 24
Finished Mar 14 12:49:23 PM PDT 24
Peak memory 223720 kb
Host smart-f157f569-043b-4dff-990b-e984aa46d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090429897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1090429897
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2611624470
Short name T310
Test name
Test status
Simulation time 44360995 ps
CPU time 0.9 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 12:49:19 PM PDT 24
Peak memory 214992 kb
Host smart-0c17db1b-b048-4d6c-bf78-71507307872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611624470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2611624470
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2084827931
Short name T560
Test name
Test status
Simulation time 245807074 ps
CPU time 5 seconds
Started Mar 14 12:49:17 PM PDT 24
Finished Mar 14 12:49:22 PM PDT 24
Peak memory 214896 kb
Host smart-6de08ab7-5c08-49be-bcd5-c14e2e1bd41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084827931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2084827931
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.348319685
Short name T653
Test name
Test status
Simulation time 358415399645 ps
CPU time 925.82 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 01:04:50 PM PDT 24
Peak memory 220180 kb
Host smart-39d86b9a-87c0-4525-9e9d-9bc09b3ca547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348319685 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.348319685
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2601332966
Short name T258
Test name
Test status
Simulation time 153617548 ps
CPU time 1.32 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 215224 kb
Host smart-c780c719-9b81-4930-96bc-090ea93eb72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601332966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2601332966
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable.1916315147
Short name T157
Test name
Test status
Simulation time 19303723 ps
CPU time 0.85 seconds
Started Mar 14 12:49:18 PM PDT 24
Finished Mar 14 12:49:19 PM PDT 24
Peak memory 215412 kb
Host smart-5bd0b21d-5353-455e-9e12-c768cd7a6409
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916315147 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1916315147
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3960051270
Short name T663
Test name
Test status
Simulation time 103304174 ps
CPU time 1.09 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 218692 kb
Host smart-b272ade7-4fb6-4b01-8075-d1945e465eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960051270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3960051270
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.255745314
Short name T645
Test name
Test status
Simulation time 46889609 ps
CPU time 1.49 seconds
Started Mar 14 12:49:15 PM PDT 24
Finished Mar 14 12:49:16 PM PDT 24
Peak memory 217256 kb
Host smart-c16a8f65-8e0d-490f-a78f-677c41eb6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255745314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.255745314
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2310718381
Short name T133
Test name
Test status
Simulation time 21731850 ps
CPU time 1.12 seconds
Started Mar 14 12:49:19 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 215544 kb
Host smart-a2374c0d-6645-4349-acad-f140e5e31d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310718381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2310718381
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3425484293
Short name T708
Test name
Test status
Simulation time 28328332 ps
CPU time 0.92 seconds
Started Mar 14 12:49:22 PM PDT 24
Finished Mar 14 12:49:24 PM PDT 24
Peak memory 214948 kb
Host smart-0107ea59-96ef-4908-bad9-78a6a61a611d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425484293 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3425484293
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.378110214
Short name T391
Test name
Test status
Simulation time 351063340 ps
CPU time 3.87 seconds
Started Mar 14 12:49:16 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 216148 kb
Host smart-9613806b-78a2-43d2-afe6-9c9e79132403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378110214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.378110214
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2853647797
Short name T818
Test name
Test status
Simulation time 531823139237 ps
CPU time 3447.2 seconds
Started Mar 14 12:49:23 PM PDT 24
Finished Mar 14 01:46:51 PM PDT 24
Peak memory 237356 kb
Host smart-27ffffcf-d2c2-4358-8ac7-e9362960cf39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853647797 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2853647797
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3575817862
Short name T243
Test name
Test status
Simulation time 39598423 ps
CPU time 1.09 seconds
Started Mar 14 12:49:21 PM PDT 24
Finished Mar 14 12:49:22 PM PDT 24
Peak memory 215308 kb
Host smart-9e2795ae-83d9-4252-9597-e6f2418dcc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575817862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3575817862
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.809237585
Short name T339
Test name
Test status
Simulation time 75915932 ps
CPU time 0.84 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 205300 kb
Host smart-c78d9f91-7e82-420d-ba6d-3e0629e693bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809237585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.809237585
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2352454625
Short name T437
Test name
Test status
Simulation time 33779410 ps
CPU time 0.87 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 214992 kb
Host smart-9bb5d205-a12a-4673-ba65-30ed6ef23eda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352454625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2352454625
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3455506806
Short name T451
Test name
Test status
Simulation time 337974323 ps
CPU time 1.03 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 217312 kb
Host smart-2ce0caf7-6c5d-4c4f-ae30-f0b03c13e86a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455506806 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3455506806
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.484888987
Short name T159
Test name
Test status
Simulation time 45522035 ps
CPU time 1.11 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 218864 kb
Host smart-f0f70ae6-4fb3-4192-927b-92ec29bc8dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484888987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.484888987
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_intr.448228519
Short name T747
Test name
Test status
Simulation time 20659829 ps
CPU time 0.98 seconds
Started Mar 14 12:49:17 PM PDT 24
Finished Mar 14 12:49:18 PM PDT 24
Peak memory 215416 kb
Host smart-37c4b3ac-e7cb-4b69-9a6f-e6eaeb1ff288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448228519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.448228519
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3301159588
Short name T454
Test name
Test status
Simulation time 49110380 ps
CPU time 0.92 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 214896 kb
Host smart-5dd12381-3e24-40ad-813a-a550ae136882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301159588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3301159588
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2462771625
Short name T389
Test name
Test status
Simulation time 237243735 ps
CPU time 3.05 seconds
Started Mar 14 12:49:22 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 216440 kb
Host smart-9085ce33-ef9c-4eed-b234-5041a6e25ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462771625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2462771625
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2451981656
Short name T198
Test name
Test status
Simulation time 71290165457 ps
CPU time 547.01 seconds
Started Mar 14 12:49:20 PM PDT 24
Finished Mar 14 12:58:27 PM PDT 24
Peak memory 217564 kb
Host smart-18ba53e3-1d1c-4332-90e8-7875a19753b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451981656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2451981656
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert_test.2570312619
Short name T575
Test name
Test status
Simulation time 73014566 ps
CPU time 0.93 seconds
Started Mar 14 12:48:21 PM PDT 24
Finished Mar 14 12:48:22 PM PDT 24
Peak memory 206556 kb
Host smart-94b23d7e-5d89-4134-a828-680bb11b2bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570312619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2570312619
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1389319481
Short name T782
Test name
Test status
Simulation time 16470935 ps
CPU time 0.88 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215532 kb
Host smart-666dd7a0-921c-4383-b31d-ab52ee9f3ac5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389319481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1389319481
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.2372009191
Short name T85
Test name
Test status
Simulation time 28125223 ps
CPU time 1.18 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 219620 kb
Host smart-a2f030a6-3ff4-40fb-83f8-2f57e73d8d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372009191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2372009191
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_intr.940258525
Short name T365
Test name
Test status
Simulation time 30447084 ps
CPU time 0.97 seconds
Started Mar 14 12:48:20 PM PDT 24
Finished Mar 14 12:48:21 PM PDT 24
Peak memory 232256 kb
Host smart-b1e6a13a-09bc-4aab-9915-bab7f95066fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940258525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.940258525
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2780371306
Short name T265
Test name
Test status
Simulation time 86678143 ps
CPU time 0.86 seconds
Started Mar 14 12:48:21 PM PDT 24
Finished Mar 14 12:48:22 PM PDT 24
Peak memory 206784 kb
Host smart-53f13d1d-fb55-45d9-9d02-c0b0509df854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780371306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2780371306
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2434244874
Short name T46
Test name
Test status
Simulation time 323001269 ps
CPU time 5.49 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 235200 kb
Host smart-d2a3edc1-fc24-4f2d-a8f4-bbae1cb2a390
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434244874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2434244874
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.915058750
Short name T811
Test name
Test status
Simulation time 62288403 ps
CPU time 0.9 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 214776 kb
Host smart-b1796bf8-0793-42e7-a294-2882f7db0335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915058750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.915058750
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2438393847
Short name T584
Test name
Test status
Simulation time 92447680 ps
CPU time 2.4 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 214936 kb
Host smart-a3ac2270-5a68-4319-8c31-2bd49c4d97eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438393847 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2438393847
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3097320808
Short name T603
Test name
Test status
Simulation time 17649748783 ps
CPU time 406.03 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:55:09 PM PDT 24
Peak memory 223372 kb
Host smart-93665041-b4d5-4df6-9e48-a4e12d6baf01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097320808 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3097320808
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1749987414
Short name T105
Test name
Test status
Simulation time 201435931 ps
CPU time 1.22 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 215220 kb
Host smart-0c86af33-f0dc-42c4-96ac-e0505c48a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749987414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1749987414
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2708544616
Short name T493
Test name
Test status
Simulation time 24581597 ps
CPU time 0.81 seconds
Started Mar 14 12:49:23 PM PDT 24
Finished Mar 14 12:49:24 PM PDT 24
Peak memory 205308 kb
Host smart-8ebef1b0-6325-4b42-9caf-34f60cb2645f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708544616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2708544616
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1847765723
Short name T652
Test name
Test status
Simulation time 38374826 ps
CPU time 0.89 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 215144 kb
Host smart-0ed14419-a307-4fe0-be0b-98a0cfc6c7cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847765723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1847765723
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.891659196
Short name T464
Test name
Test status
Simulation time 24355910 ps
CPU time 1.12 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 219872 kb
Host smart-ca2a48b8-f921-40d8-b9ed-45fde9710e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891659196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.891659196
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.952340815
Short name T555
Test name
Test status
Simulation time 229351669 ps
CPU time 1.28 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 216412 kb
Host smart-63adc49a-1686-4c3a-bf6d-937ae51a12a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952340815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.952340815
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.784798739
Short name T136
Test name
Test status
Simulation time 20942236 ps
CPU time 1.07 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 215360 kb
Host smart-743fea15-0276-4461-816a-b9f7635547ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784798739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.784798739
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3561465850
Short name T206
Test name
Test status
Simulation time 20773229 ps
CPU time 0.88 seconds
Started Mar 14 12:49:17 PM PDT 24
Finished Mar 14 12:49:18 PM PDT 24
Peak memory 215004 kb
Host smart-efc6211d-83ce-481f-8137-0ad5c0c03878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561465850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3561465850
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1906705513
Short name T736
Test name
Test status
Simulation time 134365463 ps
CPU time 2.32 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 216000 kb
Host smart-30a088d5-2486-4335-a5f3-87dc5705af08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906705513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1906705513
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2518909627
Short name T508
Test name
Test status
Simulation time 245957384470 ps
CPU time 1624.63 seconds
Started Mar 14 12:49:21 PM PDT 24
Finished Mar 14 01:16:26 PM PDT 24
Peak memory 223736 kb
Host smart-9e44732e-8b4f-44fb-a47d-7db665e0d10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518909627 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2518909627
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2388673299
Short name T174
Test name
Test status
Simulation time 136720864 ps
CPU time 1.12 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 215220 kb
Host smart-365ade89-1b4c-47b3-ba72-a0e4832f420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388673299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2388673299
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1736668554
Short name T500
Test name
Test status
Simulation time 27475578 ps
CPU time 0.92 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 206504 kb
Host smart-5ef3cef6-3208-4788-9b27-71a31d274981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736668554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1736668554
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4271692399
Short name T658
Test name
Test status
Simulation time 108327173 ps
CPU time 1.07 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 217188 kb
Host smart-c56a00ee-0a00-40d1-812c-d57942abb47a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271692399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4271692399
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.742608860
Short name T111
Test name
Test status
Simulation time 90315845 ps
CPU time 0.88 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 230800 kb
Host smart-f45997d0-c0df-45ca-8ec4-8d7f36f77998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742608860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.742608860
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_intr.4032996832
Short name T318
Test name
Test status
Simulation time 30696923 ps
CPU time 1.08 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 223756 kb
Host smart-446c307c-2451-4c2c-b784-2c7418f6a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032996832 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4032996832
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2836589412
Short name T458
Test name
Test status
Simulation time 133938491 ps
CPU time 0.94 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 215000 kb
Host smart-068e2f74-112d-4055-9541-7a2d237c011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836589412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2836589412
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.832847884
Short name T628
Test name
Test status
Simulation time 25288773 ps
CPU time 1.08 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 205760 kb
Host smart-6ef48519-64a5-47a2-91c3-1fcaace22374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832847884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.832847884
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.76402217
Short name T534
Test name
Test status
Simulation time 77050180925 ps
CPU time 1837.75 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 01:20:06 PM PDT 24
Peak memory 224804 kb
Host smart-f26863b5-d69c-4baf-8391-6e280b071a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76402217 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.76402217
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.517913777
Short name T812
Test name
Test status
Simulation time 24800924 ps
CPU time 1.23 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 215180 kb
Host smart-88e36479-7689-46bd-b0ee-bf5faa6fd3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517913777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.517913777
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.406515445
Short name T832
Test name
Test status
Simulation time 18392937 ps
CPU time 0.93 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 206532 kb
Host smart-ac446269-b2d2-4c04-a6ab-31dd96f713f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406515445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.406515445
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.717402024
Short name T112
Test name
Test status
Simulation time 22833681 ps
CPU time 0.87 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 215476 kb
Host smart-3d9e09ac-5884-4956-8bb6-7f59fe91e929
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717402024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.717402024
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1234298800
Short name T756
Test name
Test status
Simulation time 41293924 ps
CPU time 1.16 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 217308 kb
Host smart-d4bc839b-9c9b-40a8-a009-6bc4e00165eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234298800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1234298800
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3187306451
Short name T107
Test name
Test status
Simulation time 18711367 ps
CPU time 1 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 217668 kb
Host smart-a570988d-a504-438d-acf9-01f9fe11f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187306451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3187306451
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1414202454
Short name T737
Test name
Test status
Simulation time 180707088 ps
CPU time 1.45 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 218368 kb
Host smart-55409819-9626-4e2e-92e7-87526141b34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414202454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1414202454
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2995420606
Short name T641
Test name
Test status
Simulation time 63286660 ps
CPU time 0.84 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 214972 kb
Host smart-8679c962-1dac-4e82-a588-701c2789bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995420606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2995420606
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2619434660
Short name T420
Test name
Test status
Simulation time 36021505 ps
CPU time 0.87 seconds
Started Mar 14 12:49:31 PM PDT 24
Finished Mar 14 12:49:32 PM PDT 24
Peak memory 214960 kb
Host smart-a3656d80-3c0a-40c8-a3ad-7b75d5db7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619434660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2619434660
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.63792359
Short name T551
Test name
Test status
Simulation time 330542098 ps
CPU time 2.34 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 214996 kb
Host smart-bc2e86f8-157d-40fc-b062-927385c7df3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63792359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.63792359
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.573043874
Short name T728
Test name
Test status
Simulation time 26494602485 ps
CPU time 695.73 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 01:01:16 PM PDT 24
Peak memory 217388 kb
Host smart-2872f8f7-623b-4b6a-b165-786bdf428844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573043874 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.573043874
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2753574751
Short name T109
Test name
Test status
Simulation time 143936247 ps
CPU time 1.07 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 215220 kb
Host smart-8b73506e-21a9-4e2d-8291-d1122306ed63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753574751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2753574751
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1581400335
Short name T328
Test name
Test status
Simulation time 26586637 ps
CPU time 0.84 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 206512 kb
Host smart-fcc5ddee-7686-481d-8cab-a06f3f6f78d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581400335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1581400335
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2439861797
Short name T170
Test name
Test status
Simulation time 21954130 ps
CPU time 0.89 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 215140 kb
Host smart-e70a53f6-0322-4517-bc3f-1968394a15f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439861797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2439861797
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.649193187
Short name T70
Test name
Test status
Simulation time 35212670 ps
CPU time 1.3 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 216104 kb
Host smart-2d06adf5-c075-44b4-8634-140ade8c5b4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649193187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.649193187
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2620807335
Short name T100
Test name
Test status
Simulation time 38644700 ps
CPU time 0.89 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 217320 kb
Host smart-9fd7fcf7-1ce1-4ab5-bea4-3a438aa6ab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620807335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2620807335
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1665192962
Short name T675
Test name
Test status
Simulation time 47177045 ps
CPU time 1.22 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 216428 kb
Host smart-675b09b7-6e85-47f8-a993-950a7e846fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665192962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1665192962
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1718793996
Short name T490
Test name
Test status
Simulation time 33014697 ps
CPU time 0.97 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 223488 kb
Host smart-2d49bf38-e1f4-48f7-8669-fc1fc369d70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718793996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1718793996
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2820940635
Short name T667
Test name
Test status
Simulation time 28584116 ps
CPU time 0.93 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 214852 kb
Host smart-aeb988e9-9c45-4010-95ac-ce0203310902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820940635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2820940635
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.215992797
Short name T566
Test name
Test status
Simulation time 306684372 ps
CPU time 4.43 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:35 PM PDT 24
Peak memory 219196 kb
Host smart-afdc0d18-8e67-482d-b288-dfff7646eb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215992797 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.215992797
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.628117636
Short name T200
Test name
Test status
Simulation time 52036899448 ps
CPU time 1078.54 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 01:07:25 PM PDT 24
Peak memory 219340 kb
Host smart-ff078e65-d6d7-41e8-8d8a-5f3356f74670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628117636 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.628117636
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.510377070
Short name T263
Test name
Test status
Simulation time 27740008 ps
CPU time 1.21 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 215108 kb
Host smart-2a8a113a-b510-45af-80ba-c82a8415a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510377070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.510377070
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3465226499
Short name T354
Test name
Test status
Simulation time 31824216 ps
CPU time 1 seconds
Started Mar 14 12:49:39 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 206080 kb
Host smart-b463eaa6-f7d4-4cd4-b733-ddd22090920f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465226499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3465226499
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2954447784
Short name T104
Test name
Test status
Simulation time 12303701 ps
CPU time 0.9 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 215564 kb
Host smart-e110037d-b602-4888-9979-791a93b17982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954447784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2954447784
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2283717905
Short name T745
Test name
Test status
Simulation time 22984598 ps
CPU time 1.12 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 216032 kb
Host smart-fe9236b3-8baa-46c4-a511-f12ead0c68cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283717905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2283717905
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.940304951
Short name T487
Test name
Test status
Simulation time 19158762 ps
CPU time 1.19 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 222772 kb
Host smart-7263934a-d24a-411c-bc60-ee8c08a426f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940304951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.940304951
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.531977097
Short name T336
Test name
Test status
Simulation time 93367877 ps
CPU time 1.17 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:32 PM PDT 24
Peak memory 217272 kb
Host smart-f369c05c-b5be-4785-af2a-c853077ddb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531977097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.531977097
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.752987622
Short name T669
Test name
Test status
Simulation time 36225889 ps
CPU time 0.86 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 214936 kb
Host smart-cb4151ee-298d-4fe1-835d-ff6b7c473d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752987622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.752987622
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1664354613
Short name T676
Test name
Test status
Simulation time 20534931 ps
CPU time 0.95 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 215008 kb
Host smart-5d72c675-92b9-404c-9ac3-d8f00e6a4c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664354613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1664354613
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3028999242
Short name T613
Test name
Test status
Simulation time 271054659 ps
CPU time 5.44 seconds
Started Mar 14 12:49:34 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 217744 kb
Host smart-aa114693-c656-4fb4-ac09-de39c39d45a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028999242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3028999242
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3528712495
Short name T190
Test name
Test status
Simulation time 59381863183 ps
CPU time 1454.01 seconds
Started Mar 14 12:49:24 PM PDT 24
Finished Mar 14 01:13:39 PM PDT 24
Peak memory 223840 kb
Host smart-0cab619c-3860-47fd-a546-6de30ccaeaef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528712495 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3528712495
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2613612826
Short name T270
Test name
Test status
Simulation time 27896804 ps
CPU time 1.21 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 215200 kb
Host smart-6b6d8384-d143-42a6-9a01-e68c451db69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613612826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2613612826
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1828142736
Short name T808
Test name
Test status
Simulation time 12739306 ps
CPU time 0.92 seconds
Started Mar 14 12:49:33 PM PDT 24
Finished Mar 14 12:49:34 PM PDT 24
Peak memory 205608 kb
Host smart-f1dd4743-106b-4728-b371-f22384bf7d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828142736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1828142736
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.95342440
Short name T180
Test name
Test status
Simulation time 12323886 ps
CPU time 0.84 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 215184 kb
Host smart-066a0b19-5d70-40ac-9fc7-238c38e2989a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95342440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.95342440
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2608392879
Short name T58
Test name
Test status
Simulation time 24911627 ps
CPU time 1.1 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 217536 kb
Host smart-33071c82-04c5-457f-9943-bf8d4d23cb56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608392879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2608392879
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1238268962
Short name T108
Test name
Test status
Simulation time 19419231 ps
CPU time 1.08 seconds
Started Mar 14 12:49:34 PM PDT 24
Finished Mar 14 12:49:36 PM PDT 24
Peak memory 217508 kb
Host smart-4e10d7fd-2878-4c3b-a57d-0348f239b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238268962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1238268962
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3499161591
Short name T625
Test name
Test status
Simulation time 25785398 ps
CPU time 1.11 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 216164 kb
Host smart-b34cd456-61f3-4c43-8310-916cc2128de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499161591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3499161591
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.774216800
Short name T611
Test name
Test status
Simulation time 29545318 ps
CPU time 0.87 seconds
Started Mar 14 12:49:34 PM PDT 24
Finished Mar 14 12:49:35 PM PDT 24
Peak memory 215224 kb
Host smart-0b4acaea-8a93-4418-8f17-0746e56e5636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774216800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.774216800
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3013014156
Short name T672
Test name
Test status
Simulation time 15165182 ps
CPU time 1 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 215048 kb
Host smart-e0da042f-0856-463f-a185-e0379d2a9c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013014156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3013014156
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.14401045
Short name T579
Test name
Test status
Simulation time 442042049 ps
CPU time 6.53 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 216232 kb
Host smart-ee3af814-a2ff-47c1-bce7-40f959ac8b05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401045 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.14401045
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.790355991
Short name T594
Test name
Test status
Simulation time 25044964 ps
CPU time 1.23 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 215104 kb
Host smart-57bfb52f-f067-45eb-bc81-722aed54f8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790355991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.790355991
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.633903163
Short name T541
Test name
Test status
Simulation time 84663554 ps
CPU time 0.76 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 205296 kb
Host smart-a4112abd-7645-4389-81a4-52908a91055c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633903163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.633903163
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_err.1774656966
Short name T158
Test name
Test status
Simulation time 28130875 ps
CPU time 0.84 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 217288 kb
Host smart-f59d602a-3069-4117-a221-58fb4a123718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774656966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1774656966
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.240394027
Short name T820
Test name
Test status
Simulation time 52654659 ps
CPU time 1.9 seconds
Started Mar 14 12:49:27 PM PDT 24
Finished Mar 14 12:49:29 PM PDT 24
Peak memory 217416 kb
Host smart-2ee62408-2b76-4849-825d-4f5341f8c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240394027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.240394027
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3614935033
Short name T321
Test name
Test status
Simulation time 58523326 ps
CPU time 1.01 seconds
Started Mar 14 12:49:34 PM PDT 24
Finished Mar 14 12:49:36 PM PDT 24
Peak memory 223540 kb
Host smart-e735d3c5-750d-4542-9812-69764dfcb31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614935033 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3614935033
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.81936338
Short name T710
Test name
Test status
Simulation time 30415499 ps
CPU time 0.92 seconds
Started Mar 14 12:49:31 PM PDT 24
Finished Mar 14 12:49:32 PM PDT 24
Peak memory 214944 kb
Host smart-07203f6f-543f-4255-b327-78eb1410f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81936338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.81936338
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2393518658
Short name T758
Test name
Test status
Simulation time 180195493 ps
CPU time 1.52 seconds
Started Mar 14 12:49:34 PM PDT 24
Finished Mar 14 12:49:36 PM PDT 24
Peak memory 216208 kb
Host smart-de245bfe-cf19-4f31-a08e-c1a58933c652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393518658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2393518658
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.862584028
Short name T201
Test name
Test status
Simulation time 9034960460 ps
CPU time 199.86 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:52:50 PM PDT 24
Peak memory 216528 kb
Host smart-32114235-8755-4574-9027-ef85f8a40520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862584028 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.862584028
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3611355159
Short name T604
Test name
Test status
Simulation time 25972531 ps
CPU time 1.28 seconds
Started Mar 14 12:49:26 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 215232 kb
Host smart-578c1e35-3b57-476c-b8e4-ada275ad8edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611355159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3611355159
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1471064143
Short name T304
Test name
Test status
Simulation time 19860728 ps
CPU time 0.98 seconds
Started Mar 14 12:49:25 PM PDT 24
Finished Mar 14 12:49:26 PM PDT 24
Peak memory 206616 kb
Host smart-ee4a35bc-94d1-4a21-bba1-cda860b13019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471064143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1471064143
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1623734582
Short name T183
Test name
Test status
Simulation time 63100887 ps
CPU time 0.78 seconds
Started Mar 14 12:49:29 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 215000 kb
Host smart-22a20a05-d5c1-4a11-be4f-5f52d55f1e4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623734582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1623734582
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1666547652
Short name T608
Test name
Test status
Simulation time 50881291 ps
CPU time 1 seconds
Started Mar 14 12:49:28 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 217300 kb
Host smart-01bcf613-d425-47fd-b300-8eeb810cb229
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666547652 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1666547652
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3553855653
Short name T99
Test name
Test status
Simulation time 20010650 ps
CPU time 1.15 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 232164 kb
Host smart-32fb6eab-27b9-474c-bcac-a3a487d2b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553855653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3553855653
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1562161082
Short name T742
Test name
Test status
Simulation time 80905280 ps
CPU time 1.22 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 216460 kb
Host smart-ac75708b-38fe-4b64-b354-c1c620c2a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562161082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1562161082
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1528807594
Short name T609
Test name
Test status
Simulation time 38235669 ps
CPU time 1 seconds
Started Mar 14 12:49:31 PM PDT 24
Finished Mar 14 12:49:32 PM PDT 24
Peak memory 223860 kb
Host smart-4c860e9e-4856-4466-af68-58aa33b70ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528807594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1528807594
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3516695671
Short name T349
Test name
Test status
Simulation time 18370698 ps
CPU time 0.96 seconds
Started Mar 14 12:49:30 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 215000 kb
Host smart-9ab95834-888a-4f51-89c7-4fa4aabeb207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516695671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3516695671
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2447668706
Short name T644
Test name
Test status
Simulation time 1560727173 ps
CPU time 3.99 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:44 PM PDT 24
Peak memory 214848 kb
Host smart-488bb2fd-2fab-4221-ae31-6987edf46cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447668706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2447668706
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2149313248
Short name T440
Test name
Test status
Simulation time 74614350614 ps
CPU time 1804.37 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 01:19:43 PM PDT 24
Peak memory 226832 kb
Host smart-970de869-20c0-436d-ad55-3bbab3ab584d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149313248 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2149313248
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1588246109
Short name T597
Test name
Test status
Simulation time 73783571 ps
CPU time 1.29 seconds
Started Mar 14 12:49:39 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 215228 kb
Host smart-4e14bc19-f97d-43ec-995a-296a6bc3170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588246109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1588246109
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.340512905
Short name T678
Test name
Test status
Simulation time 25300838 ps
CPU time 0.96 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 206216 kb
Host smart-9dad1e4a-3f61-4780-8a90-3b0c83b804f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340512905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.340512905
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3991136177
Short name T114
Test name
Test status
Simulation time 36739869 ps
CPU time 0.86 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 215440 kb
Host smart-d959a217-def0-439c-8c2e-73c72d58caed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991136177 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3991136177
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.3564185144
Short name T117
Test name
Test status
Simulation time 36347358 ps
CPU time 0.94 seconds
Started Mar 14 12:49:39 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 222660 kb
Host smart-f7359b4d-419c-42c1-8c78-2b4a1fff740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564185144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3564185144
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1541456136
Short name T316
Test name
Test status
Simulation time 108384880 ps
CPU time 1.11 seconds
Started Mar 14 12:49:29 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 216440 kb
Host smart-e63d3282-55c3-4435-ba14-5a3d989f2c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541456136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1541456136
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2416724397
Short name T42
Test name
Test status
Simulation time 39605707 ps
CPU time 0.95 seconds
Started Mar 14 12:49:42 PM PDT 24
Finished Mar 14 12:49:43 PM PDT 24
Peak memory 223736 kb
Host smart-ae508172-4ce8-43e4-bb7b-0fcbf0ed29d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416724397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2416724397
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1250884538
Short name T479
Test name
Test status
Simulation time 18249822 ps
CPU time 1.03 seconds
Started Mar 14 12:49:29 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 214960 kb
Host smart-5c67911a-b1e4-4fa1-a8b6-3619ad27e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250884538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1250884538
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1336609787
Short name T809
Test name
Test status
Simulation time 317378400 ps
CPU time 2.07 seconds
Started Mar 14 12:49:35 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 218724 kb
Host smart-487433db-a848-418b-a9ce-784f6e938048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336609787 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1336609787
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1590982043
Short name T721
Test name
Test status
Simulation time 149953040803 ps
CPU time 993.43 seconds
Started Mar 14 12:49:29 PM PDT 24
Finished Mar 14 01:06:03 PM PDT 24
Peak memory 222696 kb
Host smart-9bd3831c-9cf1-497d-8cfd-45df5af7d970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590982043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1590982043
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.177054347
Short name T241
Test name
Test status
Simulation time 72301946 ps
CPU time 1.17 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 215212 kb
Host smart-7be0cd09-66fc-42e2-ae16-5b0d01a6b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177054347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.177054347
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2335535017
Short name T367
Test name
Test status
Simulation time 41460854 ps
CPU time 0.84 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 206344 kb
Host smart-e76a188f-20b3-4c65-887e-a498c9750eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335535017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2335535017
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.485391544
Short name T794
Test name
Test status
Simulation time 67686016 ps
CPU time 1.27 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 215976 kb
Host smart-79a0298b-226d-4e95-808c-06e72b252287
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485391544 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.485391544
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4231591774
Short name T73
Test name
Test status
Simulation time 24717311 ps
CPU time 1.26 seconds
Started Mar 14 12:49:42 PM PDT 24
Finished Mar 14 12:49:44 PM PDT 24
Peak memory 229456 kb
Host smart-3ed7fb30-21fe-4ebf-a79b-4348944df650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231591774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4231591774
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3031395368
Short name T141
Test name
Test status
Simulation time 37902373 ps
CPU time 1.12 seconds
Started Mar 14 12:49:42 PM PDT 24
Finished Mar 14 12:49:43 PM PDT 24
Peak memory 216408 kb
Host smart-69386532-7d0c-4053-9306-56e0eaa8a097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031395368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3031395368
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2807524407
Short name T577
Test name
Test status
Simulation time 28176116 ps
CPU time 1.03 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 215132 kb
Host smart-6ae94066-f815-4715-a82d-9da93b388233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807524407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2807524407
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1533153020
Short name T799
Test name
Test status
Simulation time 27537699 ps
CPU time 0.91 seconds
Started Mar 14 12:49:39 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 214956 kb
Host smart-e523465b-4d44-4a9d-8cbb-df84541a5a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533153020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1533153020
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3348223984
Short name T51
Test name
Test status
Simulation time 106467991 ps
CPU time 1.83 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 216160 kb
Host smart-17d2331e-068b-43b6-87fd-7d093ab24022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348223984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3348223984
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1113385387
Short name T795
Test name
Test status
Simulation time 85203310839 ps
CPU time 1337.94 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 01:11:58 PM PDT 24
Peak memory 223416 kb
Host smart-226a3dce-7137-4149-be0b-7c2fcb6e57cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113385387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1113385387
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1068083073
Short name T106
Test name
Test status
Simulation time 35826104 ps
CPU time 1.04 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215164 kb
Host smart-6cd3c113-cae1-46f7-9927-5b1217b337ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068083073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1068083073
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1917143826
Short name T544
Test name
Test status
Simulation time 30263819 ps
CPU time 0.92 seconds
Started Mar 14 12:48:34 PM PDT 24
Finished Mar 14 12:48:35 PM PDT 24
Peak memory 206124 kb
Host smart-6b4fc80f-1fc1-44fc-aad0-8b2a4c31314f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917143826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1917143826
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1976485162
Short name T145
Test name
Test status
Simulation time 12982666 ps
CPU time 0.9 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:27 PM PDT 24
Peak memory 215532 kb
Host smart-35ab20cf-3e67-476e-884d-af639d95fcc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976485162 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1976485162
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1084906406
Short name T160
Test name
Test status
Simulation time 74534755 ps
CPU time 1.15 seconds
Started Mar 14 12:48:26 PM PDT 24
Finished Mar 14 12:48:28 PM PDT 24
Peak memory 216036 kb
Host smart-751ada8e-8b1e-4b34-b877-53354b5cd8bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084906406 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1084906406
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1260678575
Short name T449
Test name
Test status
Simulation time 32776289 ps
CPU time 0.91 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 230792 kb
Host smart-c2030673-e7c9-40b1-9e41-9465843378eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260678575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1260678575
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1270028818
Short name T247
Test name
Test status
Simulation time 33451102 ps
CPU time 1.33 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 217384 kb
Host smart-b699a0d0-b38e-4913-abea-3eccef1de5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270028818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1270028818
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2641439118
Short name T131
Test name
Test status
Simulation time 29444258 ps
CPU time 0.84 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215192 kb
Host smart-b664c1d4-4841-4bcf-94d2-24d2eafa3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641439118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2641439118
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3655065254
Short name T788
Test name
Test status
Simulation time 28929621 ps
CPU time 0.93 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 206780 kb
Host smart-79077ccc-ddec-4706-90eb-e8ad65129fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655065254 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3655065254
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.390064128
Short name T501
Test name
Test status
Simulation time 44174420 ps
CPU time 0.89 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 214760 kb
Host smart-89a0486b-58ce-4a42-9870-26db55d93182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390064128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.390064128
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.480015982
Short name T212
Test name
Test status
Simulation time 420994593 ps
CPU time 2.52 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 216192 kb
Host smart-42479b3a-f19d-4a67-b506-34e6d480a917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480015982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.480015982
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2000461942
Short name T591
Test name
Test status
Simulation time 35504169951 ps
CPU time 640.1 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:59:06 PM PDT 24
Peak memory 219888 kb
Host smart-e3638e1a-30aa-4a9d-879a-f37f360f11a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000461942 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2000461942
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.881550316
Short name T562
Test name
Test status
Simulation time 28169473 ps
CPU time 1.25 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 216592 kb
Host smart-70c0eae3-242e-4932-9ff4-cffb16ce5fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881550316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.881550316
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.234201881
Short name T801
Test name
Test status
Simulation time 49457597 ps
CPU time 1.4 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 217464 kb
Host smart-5315f7db-cf8c-4a36-98d2-95c42d60c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234201881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.234201881
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1549133932
Short name T498
Test name
Test status
Simulation time 74597351 ps
CPU time 1.1 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 218768 kb
Host smart-52f5b7c7-1009-4e1f-ab76-6ee7f32b8f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549133932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1549133932
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2077984156
Short name T514
Test name
Test status
Simulation time 223349532 ps
CPU time 1.24 seconds
Started Mar 14 12:49:39 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 218352 kb
Host smart-dce4d18f-5a67-4064-970f-00fa8341c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077984156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2077984156
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1899248498
Short name T147
Test name
Test status
Simulation time 123791937 ps
CPU time 1.03 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 218896 kb
Host smart-970dcba0-6608-4177-80c6-16f1b750d762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899248498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1899248498
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.2819756737
Short name T476
Test name
Test status
Simulation time 22666094 ps
CPU time 0.98 seconds
Started Mar 14 12:49:41 PM PDT 24
Finished Mar 14 12:49:42 PM PDT 24
Peak memory 217776 kb
Host smart-bb6be29e-ea6c-4a58-96b2-072667fa1a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819756737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2819756737
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4222647768
Short name T499
Test name
Test status
Simulation time 34013209 ps
CPU time 1.05 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 216148 kb
Host smart-ad176c6b-ec35-4ec1-a412-35fdc4af017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222647768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4222647768
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1104382843
Short name T149
Test name
Test status
Simulation time 184274220 ps
CPU time 1.26 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 233104 kb
Host smart-13b583ba-5654-4721-b586-b9731a5cf552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104382843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1104382843
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1049678115
Short name T576
Test name
Test status
Simulation time 272161600 ps
CPU time 1.14 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:42 PM PDT 24
Peak memory 216308 kb
Host smart-b0cde5fe-38a6-4585-a8bf-76ff07712faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049678115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1049678115
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.4169598384
Short name T581
Test name
Test status
Simulation time 20169007 ps
CPU time 0.99 seconds
Started Mar 14 12:49:39 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 217444 kb
Host smart-fb2e3e0d-2a66-4003-80fd-88664afd16dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169598384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4169598384
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2495547211
Short name T525
Test name
Test status
Simulation time 35221177 ps
CPU time 1.34 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:42 PM PDT 24
Peak memory 218780 kb
Host smart-ee33d5d8-d0cb-42b9-a736-d6ab95a67bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495547211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2495547211
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1885622395
Short name T635
Test name
Test status
Simulation time 28343987 ps
CPU time 0.86 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 217352 kb
Host smart-37fe6f53-efe0-41b2-94d1-57e1a42aa3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885622395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1885622395
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2332793809
Short name T681
Test name
Test status
Simulation time 51520499 ps
CPU time 1.72 seconds
Started Mar 14 12:49:41 PM PDT 24
Finished Mar 14 12:49:43 PM PDT 24
Peak memory 217496 kb
Host smart-91681f52-0e5e-4bbf-a70e-1acb7651fef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332793809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2332793809
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.758045441
Short name T472
Test name
Test status
Simulation time 19619445 ps
CPU time 1.24 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:42 PM PDT 24
Peak memory 230956 kb
Host smart-c7e44945-3d79-4689-aa2d-4e3a72dcdd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758045441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.758045441
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.911438358
Short name T315
Test name
Test status
Simulation time 36348302 ps
CPU time 1.37 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 217412 kb
Host smart-ce9baf07-ac5c-4f77-87ea-85a52c5441f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911438358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.911438358
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3974172148
Short name T97
Test name
Test status
Simulation time 26288067 ps
CPU time 1.22 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 217688 kb
Host smart-2ba37401-ece1-4be2-b86a-6fe50aa0f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974172148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3974172148
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1764352033
Short name T659
Test name
Test status
Simulation time 96194694 ps
CPU time 1.2 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:42 PM PDT 24
Peak memory 216300 kb
Host smart-832f2b4e-4e11-4528-99eb-b83a3cebd27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764352033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1764352033
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.189107355
Short name T82
Test name
Test status
Simulation time 32566661 ps
CPU time 1.04 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 231996 kb
Host smart-3236bd00-b3ec-4e6e-9ead-f6203f99977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189107355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.189107355
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3909171484
Short name T773
Test name
Test status
Simulation time 67246649 ps
CPU time 1.05 seconds
Started Mar 14 12:49:36 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 217704 kb
Host smart-a51ceede-1867-4c9e-a11f-b4b2fd31e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909171484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3909171484
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2136895124
Short name T403
Test name
Test status
Simulation time 39307625 ps
CPU time 1.23 seconds
Started Mar 14 12:48:34 PM PDT 24
Finished Mar 14 12:48:36 PM PDT 24
Peak memory 215192 kb
Host smart-a9d3aa33-a035-49c9-980c-77bd5bf9d8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136895124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2136895124
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3357423691
Short name T627
Test name
Test status
Simulation time 25126598 ps
CPU time 0.89 seconds
Started Mar 14 12:48:25 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 205616 kb
Host smart-62fa280a-ed39-4340-bb9f-38592bbfb813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357423691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3357423691
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1378400235
Short name T473
Test name
Test status
Simulation time 12530719 ps
CPU time 0.88 seconds
Started Mar 14 12:48:34 PM PDT 24
Finished Mar 14 12:48:35 PM PDT 24
Peak memory 215344 kb
Host smart-07dd42e6-37ee-4c93-a0b5-40008f533eb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378400235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1378400235
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3505176845
Short name T75
Test name
Test status
Simulation time 55411281 ps
CPU time 1.1 seconds
Started Mar 14 12:48:33 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 216076 kb
Host smart-b46e6873-b3ae-41cc-b1e9-2d00071c1ec6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505176845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3505176845
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1361390690
Short name T44
Test name
Test status
Simulation time 49726264 ps
CPU time 1.51 seconds
Started Mar 14 12:48:34 PM PDT 24
Finished Mar 14 12:48:36 PM PDT 24
Peak memory 231928 kb
Host smart-ec17dbe7-935a-47b0-a6ce-47102710fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361390690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1361390690
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.4105482874
Short name T530
Test name
Test status
Simulation time 50168484 ps
CPU time 1.15 seconds
Started Mar 14 12:48:22 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 216332 kb
Host smart-af0233d2-ecf5-4a13-a32b-d5311b1011b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105482874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4105482874
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3017466689
Short name T135
Test name
Test status
Simulation time 32787415 ps
CPU time 0.91 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 215208 kb
Host smart-d3b8172a-3ffb-4230-b7fe-b639eecd4f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017466689 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3017466689
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2676942833
Short name T257
Test name
Test status
Simulation time 18470806 ps
CPU time 0.95 seconds
Started Mar 14 12:48:34 PM PDT 24
Finished Mar 14 12:48:35 PM PDT 24
Peak memory 206672 kb
Host smart-cc3f6ca4-bb72-4cf7-ae9f-24219d1bff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676942833 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2676942833
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.4178324978
Short name T806
Test name
Test status
Simulation time 55334781 ps
CPU time 0.92 seconds
Started Mar 14 12:48:21 PM PDT 24
Finished Mar 14 12:48:22 PM PDT 24
Peak memory 214944 kb
Host smart-181871fd-22f7-4340-aa2b-854e8e5126f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178324978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4178324978
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3031308217
Short name T637
Test name
Test status
Simulation time 746911453 ps
CPU time 4.47 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 216320 kb
Host smart-2b0e57de-73c9-4483-ad32-5d0a4086bf0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031308217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3031308217
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1557143057
Short name T300
Test name
Test status
Simulation time 135594865614 ps
CPU time 1229.12 seconds
Started Mar 14 12:48:34 PM PDT 24
Finished Mar 14 01:09:03 PM PDT 24
Peak memory 222640 kb
Host smart-d4104ac8-cdde-44fa-98ab-e5ce48161c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557143057 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1557143057
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.449391794
Short name T738
Test name
Test status
Simulation time 24772115 ps
CPU time 1.04 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 216348 kb
Host smart-d92f2814-d32f-482a-a83d-509bebdb0fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449391794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.449391794
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3137169995
Short name T595
Test name
Test status
Simulation time 89812391 ps
CPU time 1.15 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 217516 kb
Host smart-73f5e8e2-697d-4ee9-8ba2-7e02ddba681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137169995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3137169995
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3688973199
Short name T77
Test name
Test status
Simulation time 32836366 ps
CPU time 0.97 seconds
Started Mar 14 12:49:37 PM PDT 24
Finished Mar 14 12:49:38 PM PDT 24
Peak memory 218804 kb
Host smart-a18670c2-e857-4e1b-bb62-dc5e935bd624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688973199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3688973199
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3950661180
Short name T528
Test name
Test status
Simulation time 81564611 ps
CPU time 1.2 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 216068 kb
Host smart-f798e168-cd30-4b8e-b563-238465d52903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950661180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3950661180
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2252817919
Short name T399
Test name
Test status
Simulation time 37678728 ps
CPU time 1.11 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 216696 kb
Host smart-26380aee-6aff-47f9-9fc9-6148ad7d6426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252817919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2252817919
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.3777876982
Short name T3
Test name
Test status
Simulation time 23136477 ps
CPU time 1 seconds
Started Mar 14 12:49:40 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 217284 kb
Host smart-5805a0ec-a0d4-4087-b47b-52c27507b995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777876982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3777876982
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1183252830
Short name T427
Test name
Test status
Simulation time 83774198 ps
CPU time 1.19 seconds
Started Mar 14 12:49:38 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 216324 kb
Host smart-ca0dab94-dc27-4708-b107-1446b82c5549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183252830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1183252830
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1939082063
Short name T393
Test name
Test status
Simulation time 21266765 ps
CPU time 0.9 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 217412 kb
Host smart-fb8c6411-18dd-4cc9-ba02-46bec661e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939082063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1939082063
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3976121387
Short name T470
Test name
Test status
Simulation time 59899077 ps
CPU time 1.3 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 217924 kb
Host smart-980af3f9-3598-49e2-a01c-deb176e55a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976121387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3976121387
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.109519660
Short name T444
Test name
Test status
Simulation time 22209892 ps
CPU time 0.9 seconds
Started Mar 14 12:49:56 PM PDT 24
Finished Mar 14 12:49:57 PM PDT 24
Peak memory 217644 kb
Host smart-ecce3224-98a2-4254-8428-91c3495d800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109519660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.109519660
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1318663045
Short name T426
Test name
Test status
Simulation time 37411620 ps
CPU time 1.48 seconds
Started Mar 14 12:49:54 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 219104 kb
Host smart-c92b7cf5-3c4c-495d-8e89-b07c6cbd54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318663045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1318663045
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3490553056
Short name T93
Test name
Test status
Simulation time 25833193 ps
CPU time 1.35 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 229524 kb
Host smart-9016fa24-2a9a-411c-81f6-6f2561df9f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490553056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3490553056
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2648096787
Short name T35
Test name
Test status
Simulation time 44932147 ps
CPU time 1.46 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 214924 kb
Host smart-02bf3da1-bcd5-426d-a865-7682a72caef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648096787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2648096787
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.66162961
Short name T703
Test name
Test status
Simulation time 18200694 ps
CPU time 1.01 seconds
Started Mar 14 12:49:49 PM PDT 24
Finished Mar 14 12:49:51 PM PDT 24
Peak memory 217444 kb
Host smart-5a4bf102-6215-4eab-ac00-5cf93dda39d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66162961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.66162961
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1336828403
Short name T400
Test name
Test status
Simulation time 38494164 ps
CPU time 1.61 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 216256 kb
Host smart-52935334-9971-4519-aa5d-3b84076eca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336828403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1336828403
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1767316297
Short name T648
Test name
Test status
Simulation time 27983144 ps
CPU time 1.29 seconds
Started Mar 14 12:49:49 PM PDT 24
Finished Mar 14 12:49:51 PM PDT 24
Peak memory 219232 kb
Host smart-a8156191-e1ac-4ae4-b760-2bcb0a234352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767316297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1767316297
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2253358935
Short name T633
Test name
Test status
Simulation time 37336244 ps
CPU time 1.43 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 217476 kb
Host smart-adf1512e-6c07-45d0-bdfc-87a75e4e73e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253358935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2253358935
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3784708809
Short name T91
Test name
Test status
Simulation time 24803286 ps
CPU time 1.09 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 218836 kb
Host smart-2ec35942-c956-478b-a496-1973d77f7b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784708809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3784708809
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1368930795
Short name T282
Test name
Test status
Simulation time 189841185 ps
CPU time 3.19 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:56 PM PDT 24
Peak memory 216568 kb
Host smart-3aae1bc3-142c-42d8-bab8-1e9f1a754e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368930795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1368930795
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1632487185
Short name T124
Test name
Test status
Simulation time 97021021 ps
CPU time 1.2 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215160 kb
Host smart-19417a26-c0a7-4211-8f4e-ecd67320bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632487185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1632487185
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1467603714
Short name T815
Test name
Test status
Simulation time 23168235 ps
CPU time 0.87 seconds
Started Mar 14 12:48:28 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 206592 kb
Host smart-e2a6c934-de2d-4c11-84a9-cb5841894125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467603714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1467603714
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2306270517
Short name T559
Test name
Test status
Simulation time 131834931 ps
CPU time 0.89 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 215172 kb
Host smart-45ae35a3-fcf4-4813-b0b1-5dfa52ef39f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306270517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2306270517
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.237555902
Short name T654
Test name
Test status
Simulation time 79116678 ps
CPU time 1.01 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 216316 kb
Host smart-cdb48de3-bcbd-4b23-b482-e67968c9fc93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237555902 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.237555902
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1625933413
Short name T371
Test name
Test status
Simulation time 20592549 ps
CPU time 1.1 seconds
Started Mar 14 12:48:27 PM PDT 24
Finished Mar 14 12:48:28 PM PDT 24
Peak memory 219068 kb
Host smart-3d308bd1-c0d4-4733-be1a-2ffec44e9f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625933413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1625933413
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3539025374
Short name T138
Test name
Test status
Simulation time 60667541 ps
CPU time 2.03 seconds
Started Mar 14 12:48:33 PM PDT 24
Finished Mar 14 12:48:35 PM PDT 24
Peak memory 217736 kb
Host smart-d4f07b3b-234f-418b-b279-5dfc1e8f6660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539025374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3539025374
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2170270007
Short name T494
Test name
Test status
Simulation time 29135411 ps
CPU time 0.91 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 215068 kb
Host smart-29ae049a-132e-4345-af4f-e97d306a68a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170270007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2170270007
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.2646566779
Short name T491
Test name
Test status
Simulation time 24507514 ps
CPU time 0.86 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 214960 kb
Host smart-382c13ce-2cb0-41dc-9dd2-501977594c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646566779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2646566779
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.541827637
Short name T771
Test name
Test status
Simulation time 118331860 ps
CPU time 1.77 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 214960 kb
Host smart-c103423b-c725-4ba8-91aa-5d7f4682070f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541827637 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.541827637
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3597010724
Short name T759
Test name
Test status
Simulation time 39558186106 ps
CPU time 738.32 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 01:00:43 PM PDT 24
Peak memory 217808 kb
Host smart-3c75f13d-efad-4796-aba9-af49b2e69a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597010724 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3597010724
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.551102155
Short name T68
Test name
Test status
Simulation time 26744750 ps
CPU time 1.26 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 219852 kb
Host smart-47724df7-d853-4489-8736-c3abaea59ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551102155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.551102155
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3603904634
Short name T452
Test name
Test status
Simulation time 107479441 ps
CPU time 1.16 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 217348 kb
Host smart-16880ce1-7e7c-45a1-adf9-310769fea8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603904634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3603904634
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2205032196
Short name T406
Test name
Test status
Simulation time 18590753 ps
CPU time 1.09 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217624 kb
Host smart-db774513-95d1-4757-ae22-3a757c608a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205032196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2205032196
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3529382433
Short name T792
Test name
Test status
Simulation time 40699007 ps
CPU time 1.39 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 216096 kb
Host smart-21ac4e21-56a0-4a1e-9aab-087868954c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529382433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3529382433
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1629967786
Short name T153
Test name
Test status
Simulation time 43032553 ps
CPU time 1.11 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 218640 kb
Host smart-7014b94c-4b8e-4bb5-98b4-5a466b6f7ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629967786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1629967786
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2380753472
Short name T380
Test name
Test status
Simulation time 58023124 ps
CPU time 1.19 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217444 kb
Host smart-9ee17582-575b-412d-ae0c-24bd18683627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380753472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2380753472
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3386004903
Short name T513
Test name
Test status
Simulation time 34334020 ps
CPU time 0.8 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217252 kb
Host smart-9cace617-d34b-4f12-83b4-6e1074400795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386004903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3386004903
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1186047314
Short name T359
Test name
Test status
Simulation time 47453323 ps
CPU time 1.69 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 217616 kb
Host smart-b0782890-0323-4469-968b-6674ce884dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186047314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1186047314
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3758065825
Short name T512
Test name
Test status
Simulation time 65068319 ps
CPU time 0.99 seconds
Started Mar 14 12:49:49 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 219768 kb
Host smart-979ecf54-ede7-412e-bd3a-ce99fb8410e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758065825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3758065825
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.106489909
Short name T621
Test name
Test status
Simulation time 41647726 ps
CPU time 1.39 seconds
Started Mar 14 12:49:48 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 216464 kb
Host smart-dc747e56-0dcb-4406-b85b-631d8ebab7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106489909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.106489909
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3228317725
Short name T92
Test name
Test status
Simulation time 62580534 ps
CPU time 1.01 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 218964 kb
Host smart-ee69e219-aa8f-4959-805f-dc5c70697a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228317725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3228317725
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1410402229
Short name T507
Test name
Test status
Simulation time 83256859 ps
CPU time 2.71 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 219172 kb
Host smart-9ece475f-bc93-4211-a99f-d1c35a7bd01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410402229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1410402229
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.1179154912
Short name T163
Test name
Test status
Simulation time 28224331 ps
CPU time 1.27 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 218708 kb
Host smart-f437b49b-7400-4fc4-9a6a-0f399ef20b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179154912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1179154912
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.958010950
Short name T636
Test name
Test status
Simulation time 46729989 ps
CPU time 1.82 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 217616 kb
Host smart-5e7d0d70-2973-417c-bc77-862593cde356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958010950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.958010950
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3546165845
Short name T673
Test name
Test status
Simulation time 19139992 ps
CPU time 1.12 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 222740 kb
Host smart-e03b5032-d5a0-408f-9c23-03c9b300e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546165845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3546165845
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2074119973
Short name T416
Test name
Test status
Simulation time 59861575 ps
CPU time 2 seconds
Started Mar 14 12:49:54 PM PDT 24
Finished Mar 14 12:49:57 PM PDT 24
Peak memory 219008 kb
Host smart-8449dc9b-9fbe-42ef-b5b5-7dd5c3a0de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074119973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2074119973
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2116964386
Short name T578
Test name
Test status
Simulation time 69467846 ps
CPU time 0.96 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217884 kb
Host smart-1a66334a-9d01-47c5-9c64-75f8b6a4f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116964386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2116964386
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.3753993831
Short name T60
Test name
Test status
Simulation time 26906572 ps
CPU time 1.31 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 229524 kb
Host smart-b3c377bb-70d4-42dc-b544-3e4ca7c4fbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753993831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3753993831
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1392485327
Short name T714
Test name
Test status
Simulation time 60168096 ps
CPU time 2.01 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217504 kb
Host smart-8c0b2d38-7e1e-4280-960c-d54bdc14934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392485327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1392485327
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.66238
Short name T259
Test name
Test status
Simulation time 68182521 ps
CPU time 1.21 seconds
Started Mar 14 12:48:28 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 215296 kb
Host smart-f2af10e6-98ea-43cb-af27-a5fdcf2d45e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.66238
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1246582547
Short name T475
Test name
Test status
Simulation time 38196387 ps
CPU time 0.79 seconds
Started Mar 14 12:48:31 PM PDT 24
Finished Mar 14 12:48:32 PM PDT 24
Peak memory 205320 kb
Host smart-c7a43f17-a9b8-4b50-b72f-f577eac2ce1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246582547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1246582547
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3800762399
Short name T622
Test name
Test status
Simulation time 12797311 ps
CPU time 0.88 seconds
Started Mar 14 12:48:33 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 215348 kb
Host smart-b1f6a1b1-b05f-464b-b814-bca76f82673e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800762399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3800762399
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4125088853
Short name T90
Test name
Test status
Simulation time 67973359 ps
CPU time 1.16 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 216104 kb
Host smart-5e29ed88-55f6-4807-9969-e6141f5815a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125088853 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4125088853
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1661106173
Short name T67
Test name
Test status
Simulation time 28731994 ps
CPU time 1.07 seconds
Started Mar 14 12:48:30 PM PDT 24
Finished Mar 14 12:48:31 PM PDT 24
Peak memory 219740 kb
Host smart-85379ea5-f830-4983-aefb-680a74ea30b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661106173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1661106173
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1903178833
Short name T511
Test name
Test status
Simulation time 126473462 ps
CPU time 1.64 seconds
Started Mar 14 12:48:29 PM PDT 24
Finished Mar 14 12:48:30 PM PDT 24
Peak memory 217724 kb
Host smart-27c7dcfc-0cf3-4c2d-8174-aff74a390a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903178833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1903178833
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.288187402
Short name T45
Test name
Test status
Simulation time 40857946 ps
CPU time 0.98 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 223732 kb
Host smart-28affe80-abcb-4bcf-ae64-43c02fd0f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288187402 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.288187402
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.969848772
Short name T53
Test name
Test status
Simulation time 15908523 ps
CPU time 0.91 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:25 PM PDT 24
Peak memory 206632 kb
Host smart-2167e801-a654-43e7-9de3-f74517cdf949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969848772 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.969848772
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3644551966
Short name T379
Test name
Test status
Simulation time 27418204 ps
CPU time 0.91 seconds
Started Mar 14 12:48:26 PM PDT 24
Finished Mar 14 12:48:28 PM PDT 24
Peak memory 214952 kb
Host smart-76043b50-4fdc-4ede-80db-f7eb1c5b9c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644551966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3644551966
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.808398552
Short name T450
Test name
Test status
Simulation time 568221564 ps
CPU time 4.55 seconds
Started Mar 14 12:48:24 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 215052 kb
Host smart-9dfc40c0-5178-41ab-92ef-5465e58ccb7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808398552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.808398552
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.483925647
Short name T700
Test name
Test status
Simulation time 31096694662 ps
CPU time 674.67 seconds
Started Mar 14 12:48:23 PM PDT 24
Finished Mar 14 12:59:38 PM PDT 24
Peak memory 223224 kb
Host smart-5c7cac6c-11f8-4973-813b-39763e310884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483925647 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.483925647
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.265337809
Short name T363
Test name
Test status
Simulation time 19315676 ps
CPU time 1.05 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 217548 kb
Host smart-d0691844-7a1e-4201-adbc-765a01fa32a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265337809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.265337809
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2998356539
Short name T351
Test name
Test status
Simulation time 94380513 ps
CPU time 1.52 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217768 kb
Host smart-da0689e9-968f-4ba1-85e9-f2881818ae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998356539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2998356539
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2324753539
Short name T717
Test name
Test status
Simulation time 23727831 ps
CPU time 0.94 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217520 kb
Host smart-e27d4c4e-1f2d-411d-863b-974797c7e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324753539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2324753539
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2428333423
Short name T768
Test name
Test status
Simulation time 71227943 ps
CPU time 1.36 seconds
Started Mar 14 12:49:48 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 219256 kb
Host smart-10509c40-5c18-40ec-b228-5fad1c3d9ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428333423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2428333423
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2196636153
Short name T59
Test name
Test status
Simulation time 22914903 ps
CPU time 1 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 216292 kb
Host smart-866d8995-06d3-4e2f-bc9c-8e75a1e60553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196636153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2196636153
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.254778085
Short name T398
Test name
Test status
Simulation time 72491934 ps
CPU time 1.17 seconds
Started Mar 14 12:49:49 PM PDT 24
Finished Mar 14 12:49:51 PM PDT 24
Peak memory 216168 kb
Host smart-d290395e-fbf6-4791-9d54-f60dae1e746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254778085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.254778085
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1900288515
Short name T15
Test name
Test status
Simulation time 27733141 ps
CPU time 0.96 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 222672 kb
Host smart-a46379ef-58c5-4b29-bd30-ae57be183f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900288515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1900288515
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1237498552
Short name T301
Test name
Test status
Simulation time 81182525 ps
CPU time 1.98 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 218192 kb
Host smart-69b49565-0606-4e8c-b000-839fb8681abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237498552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1237498552
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.608329571
Short name T72
Test name
Test status
Simulation time 25816467 ps
CPU time 1.03 seconds
Started Mar 14 12:49:49 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 218900 kb
Host smart-f562d4be-6266-437b-97af-f4e8932cffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608329571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.608329571
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2716418101
Short name T435
Test name
Test status
Simulation time 31123984 ps
CPU time 1.23 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 218504 kb
Host smart-75bce923-21f7-45b0-8d94-09e02123016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716418101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2716418101
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.402236907
Short name T55
Test name
Test status
Simulation time 34019449 ps
CPU time 0.83 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217572 kb
Host smart-067219f3-ec5f-4209-ab08-b8d8390f445b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402236907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.402236907
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1178700007
Short name T481
Test name
Test status
Simulation time 51244735 ps
CPU time 1.31 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 217748 kb
Host smart-37f59238-d89a-4d1f-b06f-56f9f27551a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178700007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1178700007
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1123450455
Short name T115
Test name
Test status
Simulation time 27937792 ps
CPU time 1.03 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 232008 kb
Host smart-eff795b3-7907-42a5-b871-820886a14701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123450455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1123450455
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2916030233
Short name T459
Test name
Test status
Simulation time 33092877 ps
CPU time 1.2 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:52 PM PDT 24
Peak memory 216372 kb
Host smart-e95caa67-d8ef-4e97-8461-290dddc9f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916030233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2916030233
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.317613104
Short name T83
Test name
Test status
Simulation time 23587115 ps
CPU time 1.02 seconds
Started Mar 14 12:49:55 PM PDT 24
Finished Mar 14 12:49:56 PM PDT 24
Peak memory 230844 kb
Host smart-2d587c65-ece5-48fe-bd50-da08fae15273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317613104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.317613104
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1274809548
Short name T298
Test name
Test status
Simulation time 54090115 ps
CPU time 2.24 seconds
Started Mar 14 12:49:55 PM PDT 24
Finished Mar 14 12:49:57 PM PDT 24
Peak memory 217836 kb
Host smart-326b1ec7-4a53-4681-b311-5d63c1ac3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274809548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1274809548
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2295548870
Short name T79
Test name
Test status
Simulation time 90057763 ps
CPU time 1.18 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 229360 kb
Host smart-b49a0bbd-2daf-401d-8889-c0764b8b56b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295548870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2295548870
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1835470024
Short name T347
Test name
Test status
Simulation time 44245696 ps
CPU time 1.21 seconds
Started Mar 14 12:49:55 PM PDT 24
Finished Mar 14 12:49:57 PM PDT 24
Peak memory 217520 kb
Host smart-93aefc2a-eb7d-43b5-8884-5571fc4cdfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835470024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1835470024
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3032167236
Short name T634
Test name
Test status
Simulation time 49351133 ps
CPU time 0.88 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 217384 kb
Host smart-a88fcc4c-49b4-4f31-80e4-5221911944c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032167236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3032167236
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4176715962
Short name T308
Test name
Test status
Simulation time 88463558 ps
CPU time 1.43 seconds
Started Mar 14 12:49:52 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 217764 kb
Host smart-cba9124b-edb9-486e-b036-1d7afd94cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176715962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4176715962
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2133459517
Short name T187
Test name
Test status
Simulation time 36188595 ps
CPU time 1.37 seconds
Started Mar 14 12:48:30 PM PDT 24
Finished Mar 14 12:48:31 PM PDT 24
Peak memory 215100 kb
Host smart-1cabdaa1-4217-478c-a43b-9aa099bae5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133459517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2133459517
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3794050269
Short name T176
Test name
Test status
Simulation time 24641354 ps
CPU time 0.89 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 206484 kb
Host smart-bd121b08-ede9-4e7b-b764-2316300d3a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794050269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3794050269
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3049466577
Short name T57
Test name
Test status
Simulation time 10934297 ps
CPU time 0.88 seconds
Started Mar 14 12:48:44 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 215036 kb
Host smart-48b6a3ba-10f1-4bf5-8430-818075659444
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049466577 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3049466577
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2405351347
Short name T602
Test name
Test status
Simulation time 70778831 ps
CPU time 1.08 seconds
Started Mar 14 12:48:43 PM PDT 24
Finished Mar 14 12:48:44 PM PDT 24
Peak memory 216100 kb
Host smart-ecc655f6-6379-402e-be9c-fb6d0553486a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405351347 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2405351347
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.406493072
Short name T765
Test name
Test status
Simulation time 155572721 ps
CPU time 1.17 seconds
Started Mar 14 12:48:43 PM PDT 24
Finished Mar 14 12:48:44 PM PDT 24
Peak memory 218764 kb
Host smart-4a18fa60-7782-409b-9096-ebfe765bd5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406493072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.406493072
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.887160539
Short name T280
Test name
Test status
Simulation time 42335936 ps
CPU time 1.77 seconds
Started Mar 14 12:48:37 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 217608 kb
Host smart-3c57bd91-cc6d-430e-9feb-2b27332b2fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887160539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.887160539
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2898819826
Short name T125
Test name
Test status
Simulation time 38949074 ps
CPU time 0.87 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 214984 kb
Host smart-3f2420c0-7a44-40c3-b7da-0e322c805f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898819826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2898819826
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.2524104486
Short name T428
Test name
Test status
Simulation time 67791249 ps
CPU time 0.98 seconds
Started Mar 14 12:48:35 PM PDT 24
Finished Mar 14 12:48:36 PM PDT 24
Peak memory 215048 kb
Host smart-22131719-16a1-471b-ad28-e0073dc62109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524104486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2524104486
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2886199521
Short name T411
Test name
Test status
Simulation time 296134239 ps
CPU time 5.72 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 12:48:38 PM PDT 24
Peak memory 214816 kb
Host smart-78f5f395-0f2d-4ad3-8ad0-e54ef231ac86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886199521 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2886199521
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1479107969
Short name T166
Test name
Test status
Simulation time 122029258950 ps
CPU time 1462.85 seconds
Started Mar 14 12:48:32 PM PDT 24
Finished Mar 14 01:12:56 PM PDT 24
Peak memory 221388 kb
Host smart-d22f0009-d42a-424b-81cb-ca3e426011ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479107969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1479107969
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2524239699
Short name T162
Test name
Test status
Simulation time 124105114 ps
CPU time 1.13 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 218696 kb
Host smart-2f2e79dc-9537-4f83-aa4d-2995d715155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524239699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2524239699
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3688165218
Short name T353
Test name
Test status
Simulation time 28902412 ps
CPU time 1.26 seconds
Started Mar 14 12:49:56 PM PDT 24
Finished Mar 14 12:49:57 PM PDT 24
Peak memory 216264 kb
Host smart-cdcafaf7-dacb-4f56-9517-0bf17d930ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688165218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3688165218
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.7721125
Short name T798
Test name
Test status
Simulation time 32205361 ps
CPU time 1.04 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 219056 kb
Host smart-d2819b76-65e6-49e0-a6ce-5bc504d9f2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7721125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.7721125
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.400910694
Short name T483
Test name
Test status
Simulation time 60105366 ps
CPU time 2.18 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 219316 kb
Host smart-a6d63b8e-3aa5-455d-9bca-6aa5b41d2681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400910694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.400910694
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3171396776
Short name T760
Test name
Test status
Simulation time 45710384 ps
CPU time 1.12 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 218856 kb
Host smart-6300ecf6-d706-4d91-8893-7cffec5b1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171396776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3171396776
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2240658760
Short name T404
Test name
Test status
Simulation time 40461826 ps
CPU time 1.4 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 217564 kb
Host smart-28b0dbc4-03ae-40f9-93cd-a3eb6c87e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240658760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2240658760
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.4040122710
Short name T517
Test name
Test status
Simulation time 22540142 ps
CPU time 1.11 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 232432 kb
Host smart-8e18a02a-64bf-4c86-acbf-7bb1891bdca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040122710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4040122710
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.546613278
Short name T744
Test name
Test status
Simulation time 130384754 ps
CPU time 2.76 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 214948 kb
Host smart-9d37731a-8f3c-451f-8014-476c964d1c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546613278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.546613278
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_genbits.1396610823
Short name T337
Test name
Test status
Simulation time 49688889 ps
CPU time 1.39 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 218976 kb
Host smart-71258af4-ab96-4abe-a870-c70bbf8d17ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396610823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1396610823
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2715355870
Short name T401
Test name
Test status
Simulation time 19585929 ps
CPU time 1.09 seconds
Started Mar 14 12:49:51 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 217404 kb
Host smart-ab1d2c12-8aba-4f24-a646-28b6be41b76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715355870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2715355870
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.277523199
Short name T326
Test name
Test status
Simulation time 182596898 ps
CPU time 1.83 seconds
Started Mar 14 12:49:53 PM PDT 24
Finished Mar 14 12:49:55 PM PDT 24
Peak memory 217768 kb
Host smart-eca0a827-7721-432d-a2fd-0e7b23d4b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277523199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.277523199
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3772102960
Short name T520
Test name
Test status
Simulation time 24256099 ps
CPU time 1.16 seconds
Started Mar 14 12:49:55 PM PDT 24
Finished Mar 14 12:49:56 PM PDT 24
Peak memory 217668 kb
Host smart-3a84a028-2665-44ce-bab8-d6704c75c014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772102960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3772102960
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1372983677
Short name T705
Test name
Test status
Simulation time 58298722 ps
CPU time 1.49 seconds
Started Mar 14 12:49:54 PM PDT 24
Finished Mar 14 12:49:56 PM PDT 24
Peak memory 217488 kb
Host smart-07702375-4ef8-44cf-b367-6afe86aaab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372983677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1372983677
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1609158186
Short name T78
Test name
Test status
Simulation time 50016523 ps
CPU time 0.95 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 218764 kb
Host smart-676d1843-5b11-4f96-a32a-4034d1f190c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609158186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1609158186
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.314449693
Short name T535
Test name
Test status
Simulation time 69695561 ps
CPU time 1.3 seconds
Started Mar 14 12:49:50 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 217848 kb
Host smart-7b0afee8-4d68-4f08-8004-c226b4a4073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314449693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.314449693
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1668538831
Short name T734
Test name
Test status
Simulation time 18713278 ps
CPU time 1.03 seconds
Started Mar 14 12:50:02 PM PDT 24
Finished Mar 14 12:50:04 PM PDT 24
Peak memory 217620 kb
Host smart-461a7abe-0b0a-4e67-a2ad-c742e7fca8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668538831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1668538831
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1913287486
Short name T573
Test name
Test status
Simulation time 50660911 ps
CPU time 1.11 seconds
Started Mar 14 12:50:06 PM PDT 24
Finished Mar 14 12:50:08 PM PDT 24
Peak memory 218916 kb
Host smart-f8b7c043-9a52-48ef-9c2e-1396aedf8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913287486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1913287486
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3842506426
Short name T154
Test name
Test status
Simulation time 35704887 ps
CPU time 1.27 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 218712 kb
Host smart-cb7a70e6-8d03-42f4-95f6-40a82a958f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842506426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3842506426
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1590906351
Short name T327
Test name
Test status
Simulation time 64243079 ps
CPU time 1.53 seconds
Started Mar 14 12:50:03 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 217704 kb
Host smart-087af9a6-6554-409f-b7b5-d762f7af1309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590906351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1590906351
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%