Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.91 98.27 93.63 96.79 82.08 96.87 96.58 93.15


Total test records in report: 964
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T785 /workspace/coverage/default/170.edn_genbits.2258406928 Mar 17 12:44:00 PM PDT 24 Mar 17 12:44:02 PM PDT 24 32876032 ps
T786 /workspace/coverage/default/9.edn_alert_test.2921329600 Mar 17 12:42:47 PM PDT 24 Mar 17 12:42:48 PM PDT 24 75945444 ps
T126 /workspace/coverage/default/38.edn_err.4267348488 Mar 17 12:43:46 PM PDT 24 Mar 17 12:43:47 PM PDT 24 19074863 ps
T787 /workspace/coverage/default/47.edn_alert.3368944870 Mar 17 12:43:53 PM PDT 24 Mar 17 12:43:54 PM PDT 24 80737531 ps
T788 /workspace/coverage/default/282.edn_genbits.2433615472 Mar 17 12:44:35 PM PDT 24 Mar 17 12:44:38 PM PDT 24 158283858 ps
T789 /workspace/coverage/default/152.edn_genbits.187323314 Mar 17 12:44:00 PM PDT 24 Mar 17 12:44:02 PM PDT 24 44692532 ps
T790 /workspace/coverage/default/203.edn_genbits.4130709579 Mar 17 12:44:31 PM PDT 24 Mar 17 12:44:33 PM PDT 24 27981310 ps
T791 /workspace/coverage/default/31.edn_genbits.274580273 Mar 17 12:43:15 PM PDT 24 Mar 17 12:43:16 PM PDT 24 56828621 ps
T792 /workspace/coverage/default/7.edn_alert.1773794508 Mar 17 12:42:39 PM PDT 24 Mar 17 12:42:41 PM PDT 24 44858254 ps
T793 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1273562052 Mar 17 12:42:34 PM PDT 24 Mar 17 12:54:46 PM PDT 24 65400121433 ps
T794 /workspace/coverage/default/99.edn_err.1750986800 Mar 17 12:44:00 PM PDT 24 Mar 17 12:44:02 PM PDT 24 24518244 ps
T795 /workspace/coverage/default/82.edn_err.37572291 Mar 17 12:43:55 PM PDT 24 Mar 17 12:43:57 PM PDT 24 21506677 ps
T796 /workspace/coverage/default/75.edn_err.1662088741 Mar 17 12:43:58 PM PDT 24 Mar 17 12:44:00 PM PDT 24 45801307 ps
T797 /workspace/coverage/default/1.edn_alert_test.391397132 Mar 17 12:42:28 PM PDT 24 Mar 17 12:42:29 PM PDT 24 15266113 ps
T798 /workspace/coverage/default/15.edn_genbits.730821774 Mar 17 12:42:52 PM PDT 24 Mar 17 12:42:54 PM PDT 24 47892036 ps
T799 /workspace/coverage/default/21.edn_smoke.588146995 Mar 17 12:43:10 PM PDT 24 Mar 17 12:43:11 PM PDT 24 19262223 ps
T800 /workspace/coverage/default/6.edn_disable_auto_req_mode.2465473094 Mar 17 12:42:41 PM PDT 24 Mar 17 12:42:43 PM PDT 24 50658469 ps
T801 /workspace/coverage/default/23.edn_err.633818535 Mar 17 12:43:06 PM PDT 24 Mar 17 12:43:07 PM PDT 24 31736093 ps
T802 /workspace/coverage/default/25.edn_smoke.1311159537 Mar 17 12:43:07 PM PDT 24 Mar 17 12:43:08 PM PDT 24 90243790 ps
T803 /workspace/coverage/default/241.edn_genbits.2590763637 Mar 17 12:44:31 PM PDT 24 Mar 17 12:44:33 PM PDT 24 100091378 ps
T804 /workspace/coverage/default/209.edn_genbits.2129018566 Mar 17 12:44:05 PM PDT 24 Mar 17 12:44:07 PM PDT 24 44249294 ps
T805 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2120149496 Mar 17 12:43:51 PM PDT 24 Mar 17 12:48:20 PM PDT 24 21548305353 ps
T806 /workspace/coverage/default/23.edn_intr.2067746870 Mar 17 12:43:08 PM PDT 24 Mar 17 12:43:09 PM PDT 24 23663186 ps
T807 /workspace/coverage/default/85.edn_err.4229476706 Mar 17 12:44:01 PM PDT 24 Mar 17 12:44:03 PM PDT 24 21273449 ps
T808 /workspace/coverage/default/24.edn_intr.4197085550 Mar 17 12:43:05 PM PDT 24 Mar 17 12:43:07 PM PDT 24 26936875 ps
T809 /workspace/coverage/default/298.edn_genbits.4028614897 Mar 17 12:44:35 PM PDT 24 Mar 17 12:44:37 PM PDT 24 82264413 ps
T810 /workspace/coverage/default/20.edn_stress_all.3303790252 Mar 17 12:43:02 PM PDT 24 Mar 17 12:43:07 PM PDT 24 351020040 ps
T811 /workspace/coverage/default/4.edn_disable_auto_req_mode.3944683667 Mar 17 12:42:37 PM PDT 24 Mar 17 12:42:39 PM PDT 24 66587418 ps
T812 /workspace/coverage/default/228.edn_genbits.1729907340 Mar 17 12:44:07 PM PDT 24 Mar 17 12:44:09 PM PDT 24 113342310 ps
T813 /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1677098591 Mar 17 12:42:35 PM PDT 24 Mar 17 01:26:36 PM PDT 24 425797380433 ps
T814 /workspace/coverage/default/76.edn_err.1955729647 Mar 17 12:44:04 PM PDT 24 Mar 17 12:44:06 PM PDT 24 18817186 ps
T119 /workspace/coverage/default/53.edn_err.3483688985 Mar 17 12:43:52 PM PDT 24 Mar 17 12:43:53 PM PDT 24 53140656 ps
T815 /workspace/coverage/default/96.edn_err.1880318117 Mar 17 12:44:02 PM PDT 24 Mar 17 12:44:04 PM PDT 24 32340280 ps
T816 /workspace/coverage/default/248.edn_genbits.2852572989 Mar 17 12:44:30 PM PDT 24 Mar 17 12:44:33 PM PDT 24 49785669 ps
T817 /workspace/coverage/default/41.edn_stress_all.1589342313 Mar 17 12:43:25 PM PDT 24 Mar 17 12:43:30 PM PDT 24 905771410 ps
T818 /workspace/coverage/default/164.edn_genbits.2757756031 Mar 17 12:44:01 PM PDT 24 Mar 17 12:44:03 PM PDT 24 27900299 ps
T819 /workspace/coverage/default/259.edn_genbits.2651511368 Mar 17 12:44:27 PM PDT 24 Mar 17 12:44:31 PM PDT 24 41257008 ps
T78 /workspace/coverage/default/11.edn_disable_auto_req_mode.275036629 Mar 17 12:42:46 PM PDT 24 Mar 17 12:42:47 PM PDT 24 42682704 ps
T820 /workspace/coverage/default/15.edn_err.97533866 Mar 17 12:42:55 PM PDT 24 Mar 17 12:42:57 PM PDT 24 145293088 ps
T120 /workspace/coverage/default/43.edn_err.2133675360 Mar 17 12:43:38 PM PDT 24 Mar 17 12:43:39 PM PDT 24 28218805 ps
T821 /workspace/coverage/default/59.edn_genbits.3595208634 Mar 17 12:43:55 PM PDT 24 Mar 17 12:43:57 PM PDT 24 171255962 ps
T822 /workspace/coverage/default/47.edn_intr.1476789677 Mar 17 12:43:43 PM PDT 24 Mar 17 12:43:44 PM PDT 24 25866909 ps
T823 /workspace/coverage/default/278.edn_genbits.781809812 Mar 17 12:44:39 PM PDT 24 Mar 17 12:44:41 PM PDT 24 120182104 ps
T824 /workspace/coverage/default/34.edn_err.3502496472 Mar 17 12:43:17 PM PDT 24 Mar 17 12:43:18 PM PDT 24 20247244 ps
T825 /workspace/coverage/default/81.edn_err.500660597 Mar 17 12:43:56 PM PDT 24 Mar 17 12:43:58 PM PDT 24 48722818 ps
T826 /workspace/coverage/default/33.edn_intr.2512290723 Mar 17 12:43:23 PM PDT 24 Mar 17 12:43:24 PM PDT 24 20627513 ps
T827 /workspace/coverage/default/46.edn_disable_auto_req_mode.2997782041 Mar 17 12:43:52 PM PDT 24 Mar 17 12:43:54 PM PDT 24 23052130 ps
T828 /workspace/coverage/default/182.edn_genbits.2334327707 Mar 17 12:44:00 PM PDT 24 Mar 17 12:44:02 PM PDT 24 48336793 ps
T829 /workspace/coverage/default/20.edn_alert_test.362124957 Mar 17 12:43:06 PM PDT 24 Mar 17 12:43:07 PM PDT 24 190769846 ps
T221 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2624587387 Mar 17 12:25:05 PM PDT 24 Mar 17 12:25:06 PM PDT 24 107785331 ps
T830 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2753836648 Mar 17 12:26:28 PM PDT 24 Mar 17 12:26:29 PM PDT 24 34832892 ps
T831 /workspace/coverage/cover_reg_top/35.edn_intr_test.4023581818 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 35638355 ps
T236 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2556689918 Mar 17 12:25:44 PM PDT 24 Mar 17 12:25:45 PM PDT 24 79712916 ps
T832 /workspace/coverage/cover_reg_top/11.edn_intr_test.1613646114 Mar 17 12:27:54 PM PDT 24 Mar 17 12:27:56 PM PDT 24 47025266 ps
T237 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1819399922 Mar 17 12:24:43 PM PDT 24 Mar 17 12:24:44 PM PDT 24 29001307 ps
T833 /workspace/coverage/cover_reg_top/8.edn_intr_test.549240512 Mar 17 12:26:54 PM PDT 24 Mar 17 12:26:55 PM PDT 24 17096160 ps
T834 /workspace/coverage/cover_reg_top/10.edn_intr_test.2309353373 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:20 PM PDT 24 22202815 ps
T835 /workspace/coverage/cover_reg_top/34.edn_intr_test.3633358898 Mar 17 12:25:14 PM PDT 24 Mar 17 12:25:16 PM PDT 24 19988085 ps
T836 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1531057926 Mar 17 12:26:16 PM PDT 24 Mar 17 12:26:17 PM PDT 24 28359191 ps
T837 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1944977417 Mar 17 12:26:10 PM PDT 24 Mar 17 12:26:13 PM PDT 24 42105214 ps
T222 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2221618503 Mar 17 12:26:04 PM PDT 24 Mar 17 12:26:05 PM PDT 24 14203877 ps
T838 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3939179927 Mar 17 12:25:05 PM PDT 24 Mar 17 12:25:07 PM PDT 24 42449777 ps
T839 /workspace/coverage/cover_reg_top/25.edn_intr_test.300042287 Mar 17 12:28:17 PM PDT 24 Mar 17 12:28:18 PM PDT 24 96508876 ps
T840 /workspace/coverage/cover_reg_top/7.edn_intr_test.459512060 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:07 PM PDT 24 49263474 ps
T841 /workspace/coverage/cover_reg_top/49.edn_intr_test.41361319 Mar 17 12:27:55 PM PDT 24 Mar 17 12:27:57 PM PDT 24 15991713 ps
T223 /workspace/coverage/cover_reg_top/19.edn_csr_rw.262783862 Mar 17 12:25:55 PM PDT 24 Mar 17 12:25:56 PM PDT 24 49547767 ps
T242 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3399774708 Mar 17 12:25:15 PM PDT 24 Mar 17 12:25:16 PM PDT 24 35823984 ps
T238 /workspace/coverage/cover_reg_top/6.edn_csr_rw.263542313 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 21189469 ps
T245 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3519422782 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 209943737 ps
T246 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.307109730 Mar 17 12:27:39 PM PDT 24 Mar 17 12:27:41 PM PDT 24 61066743 ps
T842 /workspace/coverage/cover_reg_top/4.edn_tl_errors.494413678 Mar 17 12:28:14 PM PDT 24 Mar 17 12:28:16 PM PDT 24 26924218 ps
T843 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2736274204 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:36 PM PDT 24 299639587 ps
T243 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1262160613 Mar 17 12:26:23 PM PDT 24 Mar 17 12:26:24 PM PDT 24 42006166 ps
T844 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2705805222 Mar 17 12:25:25 PM PDT 24 Mar 17 12:25:27 PM PDT 24 55551343 ps
T845 /workspace/coverage/cover_reg_top/30.edn_intr_test.1613441279 Mar 17 12:28:16 PM PDT 24 Mar 17 12:28:17 PM PDT 24 12950768 ps
T244 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2099947411 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 24379970 ps
T239 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.189634289 Mar 17 12:25:12 PM PDT 24 Mar 17 12:25:14 PM PDT 24 15546327 ps
T846 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1042973436 Mar 17 12:25:04 PM PDT 24 Mar 17 12:25:05 PM PDT 24 31462443 ps
T847 /workspace/coverage/cover_reg_top/14.edn_intr_test.461458930 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:41 PM PDT 24 56653862 ps
T224 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3856108731 Mar 17 12:28:14 PM PDT 24 Mar 17 12:28:16 PM PDT 24 135470921 ps
T848 /workspace/coverage/cover_reg_top/43.edn_intr_test.3197324816 Mar 17 12:27:49 PM PDT 24 Mar 17 12:27:50 PM PDT 24 31201009 ps
T247 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1498489817 Mar 17 12:23:13 PM PDT 24 Mar 17 12:23:15 PM PDT 24 275531488 ps
T849 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2858445123 Mar 17 12:27:30 PM PDT 24 Mar 17 12:27:31 PM PDT 24 24115099 ps
T850 /workspace/coverage/cover_reg_top/0.edn_intr_test.2823542496 Mar 17 12:24:27 PM PDT 24 Mar 17 12:24:29 PM PDT 24 117157024 ps
T851 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1287137308 Mar 17 12:26:11 PM PDT 24 Mar 17 12:26:13 PM PDT 24 29552743 ps
T852 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1278207079 Mar 17 12:28:15 PM PDT 24 Mar 17 12:28:17 PM PDT 24 54322960 ps
T853 /workspace/coverage/cover_reg_top/12.edn_intr_test.3156373241 Mar 17 12:25:16 PM PDT 24 Mar 17 12:25:17 PM PDT 24 20896306 ps
T225 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3225197388 Mar 17 12:26:35 PM PDT 24 Mar 17 12:26:37 PM PDT 24 19762345 ps
T854 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1742468094 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:41 PM PDT 24 37562889 ps
T855 /workspace/coverage/cover_reg_top/40.edn_intr_test.389602492 Mar 17 12:25:11 PM PDT 24 Mar 17 12:25:12 PM PDT 24 19508655 ps
T856 /workspace/coverage/cover_reg_top/42.edn_intr_test.2395641507 Mar 17 12:28:34 PM PDT 24 Mar 17 12:28:35 PM PDT 24 45326852 ps
T226 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2893462005 Mar 17 12:22:50 PM PDT 24 Mar 17 12:22:52 PM PDT 24 27143022 ps
T255 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1473170218 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:34 PM PDT 24 271960538 ps
T857 /workspace/coverage/cover_reg_top/36.edn_intr_test.3218544933 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 15389699 ps
T227 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2087986405 Mar 17 12:24:53 PM PDT 24 Mar 17 12:24:54 PM PDT 24 42333990 ps
T240 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.255860552 Mar 17 12:26:50 PM PDT 24 Mar 17 12:26:51 PM PDT 24 25222806 ps
T858 /workspace/coverage/cover_reg_top/1.edn_intr_test.1428423888 Mar 17 12:23:24 PM PDT 24 Mar 17 12:23:25 PM PDT 24 42358973 ps
T859 /workspace/coverage/cover_reg_top/33.edn_intr_test.1224753353 Mar 17 12:27:14 PM PDT 24 Mar 17 12:27:15 PM PDT 24 47495146 ps
T860 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2845099441 Mar 17 12:25:57 PM PDT 24 Mar 17 12:26:01 PM PDT 24 985481925 ps
T241 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2661986392 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:09 PM PDT 24 93368318 ps
T228 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3415069717 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:34 PM PDT 24 129693531 ps
T861 /workspace/coverage/cover_reg_top/39.edn_intr_test.1146350609 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 13401971 ps
T229 /workspace/coverage/cover_reg_top/17.edn_csr_rw.638327656 Mar 17 12:27:13 PM PDT 24 Mar 17 12:27:13 PM PDT 24 24718846 ps
T862 /workspace/coverage/cover_reg_top/27.edn_intr_test.2395392441 Mar 17 12:25:10 PM PDT 24 Mar 17 12:25:11 PM PDT 24 26933230 ps
T863 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3434202041 Mar 17 12:27:31 PM PDT 24 Mar 17 12:27:32 PM PDT 24 25885872 ps
T253 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2449787345 Mar 17 12:27:17 PM PDT 24 Mar 17 12:27:19 PM PDT 24 167832387 ps
T864 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3272642116 Mar 17 12:25:23 PM PDT 24 Mar 17 12:25:25 PM PDT 24 38837876 ps
T865 /workspace/coverage/cover_reg_top/20.edn_intr_test.1178857931 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:32 PM PDT 24 21822518 ps
T866 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.192214067 Mar 17 12:26:36 PM PDT 24 Mar 17 12:26:37 PM PDT 24 23441074 ps
T867 /workspace/coverage/cover_reg_top/32.edn_intr_test.1861593209 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:32 PM PDT 24 33816878 ps
T868 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1466397459 Mar 17 12:26:14 PM PDT 24 Mar 17 12:26:15 PM PDT 24 42876218 ps
T869 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3771643308 Mar 17 12:28:13 PM PDT 24 Mar 17 12:28:15 PM PDT 24 46098524 ps
T870 /workspace/coverage/cover_reg_top/38.edn_intr_test.3047150803 Mar 17 12:27:48 PM PDT 24 Mar 17 12:27:49 PM PDT 24 49417662 ps
T871 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3061930171 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:13 PM PDT 24 234806665 ps
T872 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1333991845 Mar 17 12:25:23 PM PDT 24 Mar 17 12:25:25 PM PDT 24 86490650 ps
T873 /workspace/coverage/cover_reg_top/26.edn_intr_test.2175564166 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 12741752 ps
T874 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3044823717 Mar 17 12:28:14 PM PDT 24 Mar 17 12:28:16 PM PDT 24 93147980 ps
T875 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4013977470 Mar 17 12:28:15 PM PDT 24 Mar 17 12:28:17 PM PDT 24 46744512 ps
T876 /workspace/coverage/cover_reg_top/13.edn_intr_test.1667059833 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:41 PM PDT 24 18767154 ps
T877 /workspace/coverage/cover_reg_top/46.edn_intr_test.553325258 Mar 17 12:28:17 PM PDT 24 Mar 17 12:28:18 PM PDT 24 19461444 ps
T878 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1975197342 Mar 17 12:26:23 PM PDT 24 Mar 17 12:26:26 PM PDT 24 228435956 ps
T879 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3089721676 Mar 17 12:25:15 PM PDT 24 Mar 17 12:25:16 PM PDT 24 24855615 ps
T880 /workspace/coverage/cover_reg_top/5.edn_intr_test.2906477719 Mar 17 12:26:07 PM PDT 24 Mar 17 12:26:08 PM PDT 24 23758300 ps
T881 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.412567285 Mar 17 12:23:12 PM PDT 24 Mar 17 12:23:14 PM PDT 24 20512396 ps
T882 /workspace/coverage/cover_reg_top/37.edn_intr_test.909461034 Mar 17 12:28:05 PM PDT 24 Mar 17 12:28:06 PM PDT 24 180198341 ps
T883 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1469360879 Mar 17 12:25:12 PM PDT 24 Mar 17 12:25:14 PM PDT 24 51890711 ps
T884 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3081455881 Mar 17 12:25:16 PM PDT 24 Mar 17 12:25:17 PM PDT 24 18173710 ps
T885 /workspace/coverage/cover_reg_top/24.edn_intr_test.3589269494 Mar 17 12:25:15 PM PDT 24 Mar 17 12:25:16 PM PDT 24 13114158 ps
T886 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2051418205 Mar 17 12:27:18 PM PDT 24 Mar 17 12:27:20 PM PDT 24 31515789 ps
T887 /workspace/coverage/cover_reg_top/22.edn_intr_test.2681979540 Mar 17 12:28:17 PM PDT 24 Mar 17 12:28:18 PM PDT 24 26261423 ps
T888 /workspace/coverage/cover_reg_top/4.edn_intr_test.1287764737 Mar 17 12:26:35 PM PDT 24 Mar 17 12:26:37 PM PDT 24 15109403 ps
T889 /workspace/coverage/cover_reg_top/31.edn_intr_test.3092419314 Mar 17 12:26:10 PM PDT 24 Mar 17 12:26:11 PM PDT 24 14166185 ps
T890 /workspace/coverage/cover_reg_top/11.edn_tl_errors.294235232 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:35 PM PDT 24 33460822 ps
T891 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4018040452 Mar 17 12:24:41 PM PDT 24 Mar 17 12:24:43 PM PDT 24 65875899 ps
T892 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3519541588 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:12 PM PDT 24 19548846 ps
T893 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2628316534 Mar 17 12:26:59 PM PDT 24 Mar 17 12:27:02 PM PDT 24 127144636 ps
T894 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3503631607 Mar 17 12:25:25 PM PDT 24 Mar 17 12:25:26 PM PDT 24 111428806 ps
T895 /workspace/coverage/cover_reg_top/21.edn_intr_test.523579515 Mar 17 12:28:33 PM PDT 24 Mar 17 12:28:34 PM PDT 24 43513047 ps
T896 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.445345618 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:45 PM PDT 24 55475969 ps
T897 /workspace/coverage/cover_reg_top/12.edn_csr_rw.658377298 Mar 17 12:26:35 PM PDT 24 Mar 17 12:26:36 PM PDT 24 20137884 ps
T230 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3569971186 Mar 17 12:28:14 PM PDT 24 Mar 17 12:28:16 PM PDT 24 39998844 ps
T898 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3539963083 Mar 17 12:26:54 PM PDT 24 Mar 17 12:26:56 PM PDT 24 42989895 ps
T899 /workspace/coverage/cover_reg_top/19.edn_intr_test.2253951521 Mar 17 12:25:11 PM PDT 24 Mar 17 12:25:12 PM PDT 24 23176521 ps
T900 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.270723456 Mar 17 12:27:22 PM PDT 24 Mar 17 12:27:23 PM PDT 24 34558034 ps
T231 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3026594923 Mar 17 12:26:04 PM PDT 24 Mar 17 12:26:05 PM PDT 24 81938436 ps
T901 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3772025385 Mar 17 12:25:57 PM PDT 24 Mar 17 12:25:59 PM PDT 24 69423292 ps
T902 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2133131212 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 59083967 ps
T903 /workspace/coverage/cover_reg_top/17.edn_intr_test.1937499293 Mar 17 12:28:08 PM PDT 24 Mar 17 12:28:10 PM PDT 24 61884783 ps
T904 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3309694518 Mar 17 12:25:12 PM PDT 24 Mar 17 12:25:14 PM PDT 24 17906697 ps
T232 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3957189896 Mar 17 12:24:27 PM PDT 24 Mar 17 12:24:29 PM PDT 24 14052416 ps
T905 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3356496967 Mar 17 12:26:07 PM PDT 24 Mar 17 12:26:08 PM PDT 24 78324064 ps
T906 /workspace/coverage/cover_reg_top/6.edn_intr_test.2696852579 Mar 17 12:26:53 PM PDT 24 Mar 17 12:26:54 PM PDT 24 33719019 ps
T907 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2283822866 Mar 17 12:25:20 PM PDT 24 Mar 17 12:25:22 PM PDT 24 59837162 ps
T908 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3387296031 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:39 PM PDT 24 126460834 ps
T909 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3655045773 Mar 17 12:23:17 PM PDT 24 Mar 17 12:23:18 PM PDT 24 57249364 ps
T910 /workspace/coverage/cover_reg_top/48.edn_intr_test.973126980 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:07 PM PDT 24 34334453 ps
T911 /workspace/coverage/cover_reg_top/28.edn_intr_test.3845741502 Mar 17 12:25:20 PM PDT 24 Mar 17 12:25:22 PM PDT 24 29970999 ps
T912 /workspace/coverage/cover_reg_top/15.edn_intr_test.3012932212 Mar 17 12:28:08 PM PDT 24 Mar 17 12:28:10 PM PDT 24 28960946 ps
T913 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1285629334 Mar 17 12:26:16 PM PDT 24 Mar 17 12:26:17 PM PDT 24 15226361 ps
T914 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3662035046 Mar 17 12:25:21 PM PDT 24 Mar 17 12:25:25 PM PDT 24 238671079 ps
T915 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2411717926 Mar 17 12:25:14 PM PDT 24 Mar 17 12:25:17 PM PDT 24 126811215 ps
T916 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4014885879 Mar 17 12:25:12 PM PDT 24 Mar 17 12:25:14 PM PDT 24 138201902 ps
T917 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2275777404 Mar 17 12:27:31 PM PDT 24 Mar 17 12:27:32 PM PDT 24 19127761 ps
T918 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1226417794 Mar 17 12:23:13 PM PDT 24 Mar 17 12:23:16 PM PDT 24 159127807 ps
T919 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2898019795 Mar 17 12:25:26 PM PDT 24 Mar 17 12:25:28 PM PDT 24 164313782 ps
T920 /workspace/coverage/cover_reg_top/23.edn_intr_test.4085409529 Mar 17 12:27:18 PM PDT 24 Mar 17 12:27:20 PM PDT 24 35212683 ps
T921 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3051303700 Mar 17 12:28:08 PM PDT 24 Mar 17 12:28:10 PM PDT 24 119779369 ps
T922 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.68878797 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:35 PM PDT 24 185065110 ps
T923 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1964785776 Mar 17 12:27:07 PM PDT 24 Mar 17 12:27:08 PM PDT 24 23275907 ps
T924 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2864919954 Mar 17 12:28:49 PM PDT 24 Mar 17 12:28:51 PM PDT 24 164876849 ps
T925 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2403661430 Mar 17 12:25:10 PM PDT 24 Mar 17 12:25:11 PM PDT 24 15589896 ps
T926 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1499370761 Mar 17 12:25:11 PM PDT 24 Mar 17 12:25:14 PM PDT 24 147919306 ps
T927 /workspace/coverage/cover_reg_top/47.edn_intr_test.4054554408 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:01 PM PDT 24 12728769 ps
T233 /workspace/coverage/cover_reg_top/10.edn_csr_rw.4227335351 Mar 17 12:24:44 PM PDT 24 Mar 17 12:24:45 PM PDT 24 18463203 ps
T928 /workspace/coverage/cover_reg_top/2.edn_intr_test.3567887446 Mar 17 12:25:05 PM PDT 24 Mar 17 12:25:06 PM PDT 24 22197619 ps
T929 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2511384856 Mar 17 12:27:17 PM PDT 24 Mar 17 12:27:20 PM PDT 24 35224129 ps
T930 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2162268398 Mar 17 12:23:38 PM PDT 24 Mar 17 12:23:41 PM PDT 24 227816225 ps
T931 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2087634514 Mar 17 12:27:34 PM PDT 24 Mar 17 12:27:36 PM PDT 24 37977616 ps
T932 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2961326802 Mar 17 12:24:49 PM PDT 24 Mar 17 12:24:53 PM PDT 24 596770451 ps
T933 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2847971110 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:20 PM PDT 24 20951150 ps
T934 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3643056367 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:02 PM PDT 24 180049800 ps
T935 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3681930522 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:08 PM PDT 24 181843553 ps
T936 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2500989692 Mar 17 12:27:17 PM PDT 24 Mar 17 12:27:19 PM PDT 24 19972626 ps
T937 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1526327264 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:08 PM PDT 24 42048986 ps
T938 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2214723301 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:22 PM PDT 24 153673526 ps
T939 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2520064944 Mar 17 12:26:06 PM PDT 24 Mar 17 12:26:09 PM PDT 24 350957826 ps
T940 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3711504461 Mar 17 12:28:15 PM PDT 24 Mar 17 12:28:17 PM PDT 24 35300415 ps
T941 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1362457057 Mar 17 12:25:16 PM PDT 24 Mar 17 12:25:18 PM PDT 24 137832167 ps
T942 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1245376594 Mar 17 12:25:11 PM PDT 24 Mar 17 12:25:15 PM PDT 24 170905217 ps
T943 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1836098834 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:34 PM PDT 24 87340557 ps
T944 /workspace/coverage/cover_reg_top/18.edn_intr_test.2382933711 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:44 PM PDT 24 27295896 ps
T945 /workspace/coverage/cover_reg_top/29.edn_intr_test.1854677094 Mar 17 12:27:31 PM PDT 24 Mar 17 12:27:32 PM PDT 24 15997092 ps
T946 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1442748047 Mar 17 12:23:13 PM PDT 24 Mar 17 12:23:13 PM PDT 24 199563529 ps
T947 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1206652871 Mar 17 12:27:18 PM PDT 24 Mar 17 12:27:21 PM PDT 24 91704684 ps
T948 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4242962884 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 39479747 ps
T949 /workspace/coverage/cover_reg_top/44.edn_intr_test.2086764245 Mar 17 12:27:24 PM PDT 24 Mar 17 12:27:26 PM PDT 24 59787090 ps
T950 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2693231350 Mar 17 12:24:59 PM PDT 24 Mar 17 12:25:01 PM PDT 24 53738357 ps
T951 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3556916869 Mar 17 12:23:37 PM PDT 24 Mar 17 12:23:40 PM PDT 24 82950027 ps
T952 /workspace/coverage/cover_reg_top/16.edn_intr_test.2510915739 Mar 17 12:28:30 PM PDT 24 Mar 17 12:28:36 PM PDT 24 24850176 ps
T953 /workspace/coverage/cover_reg_top/3.edn_intr_test.3055393863 Mar 17 12:23:20 PM PDT 24 Mar 17 12:23:21 PM PDT 24 25494606 ps
T254 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1754187730 Mar 17 12:25:05 PM PDT 24 Mar 17 12:25:08 PM PDT 24 290842762 ps
T954 /workspace/coverage/cover_reg_top/1.edn_tl_errors.513662699 Mar 17 12:25:53 PM PDT 24 Mar 17 12:25:56 PM PDT 24 165445808 ps
T955 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3879661664 Mar 17 12:25:58 PM PDT 24 Mar 17 12:26:00 PM PDT 24 27457236 ps
T234 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.656967336 Mar 17 12:24:53 PM PDT 24 Mar 17 12:24:54 PM PDT 24 28198578 ps
T956 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2130384475 Mar 17 12:24:35 PM PDT 24 Mar 17 12:24:36 PM PDT 24 23444838 ps
T957 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3095501126 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:15 PM PDT 24 116495196 ps
T958 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3739094023 Mar 17 12:26:12 PM PDT 24 Mar 17 12:26:16 PM PDT 24 911786529 ps
T235 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1546015785 Mar 17 12:25:30 PM PDT 24 Mar 17 12:25:31 PM PDT 24 25019325 ps
T959 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1993516822 Mar 17 12:26:11 PM PDT 24 Mar 17 12:26:15 PM PDT 24 212183241 ps
T960 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3988114804 Mar 17 12:26:04 PM PDT 24 Mar 17 12:26:05 PM PDT 24 30608113 ps
T961 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1100812419 Mar 17 12:27:40 PM PDT 24 Mar 17 12:27:41 PM PDT 24 128328935 ps
T962 /workspace/coverage/cover_reg_top/9.edn_intr_test.233871939 Mar 17 12:24:38 PM PDT 24 Mar 17 12:24:39 PM PDT 24 12507917 ps
T963 /workspace/coverage/cover_reg_top/45.edn_intr_test.141273806 Mar 17 12:28:32 PM PDT 24 Mar 17 12:28:33 PM PDT 24 36945225 ps
T964 /workspace/coverage/cover_reg_top/41.edn_intr_test.300045771 Mar 17 12:28:28 PM PDT 24 Mar 17 12:28:29 PM PDT 24 46659617 ps

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2548895203
Short name T2
Test name
Test status
Simulation time 27846519940 ps
CPU time 731.21 seconds
Started Mar 17 12:42:52 PM PDT 24
Finished Mar 17 12:55:03 PM PDT 24
Peak memory 218240 kb
Host smart-82db89ab-8b31-4daa-a6df-122112a898f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548895203 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2548895203
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/299.edn_genbits.3111389009
Short name T31
Test name
Test status
Simulation time 69911323 ps
CPU time 2.45 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:41 PM PDT 24
Peak memory 219520 kb
Host smart-0f19d682-aa16-44a8-bebc-4c00e8b918c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111389009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3111389009
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.809389135
Short name T18
Test name
Test status
Simulation time 47738652 ps
CPU time 1.14 seconds
Started Mar 17 12:43:20 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 215716 kb
Host smart-9ff3934b-6e80-44af-a5e5-df95110d9255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809389135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.809389135
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.2608327512
Short name T6
Test name
Test status
Simulation time 31321700 ps
CPU time 0.91 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218176 kb
Host smart-5b1aa52c-6141-4d3c-8a02-66b8255f8916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608327512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2608327512
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/4.edn_sec_cm.276955246
Short name T23
Test name
Test status
Simulation time 2856109212 ps
CPU time 4.11 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 236148 kb
Host smart-41f31037-2a67-4d8f-8529-d7bd6d8c5cad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276955246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.276955246
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/8.edn_err.3798312220
Short name T16
Test name
Test status
Simulation time 23368290 ps
CPU time 0.99 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 231160 kb
Host smart-81774925-900f-4a3d-8536-bb3256218beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798312220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3798312220
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2479147691
Short name T9
Test name
Test status
Simulation time 28421370 ps
CPU time 1.09 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 216588 kb
Host smart-8692cddc-28e7-4a42-b70d-ea11ddc6c77f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479147691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2479147691
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable.1562799769
Short name T122
Test name
Test status
Simulation time 32485100 ps
CPU time 0.87 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 215832 kb
Host smart-ec34406b-cf78-42e5-94f5-66d7e618cfd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562799769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1562799769
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/44.edn_alert.3279763481
Short name T19
Test name
Test status
Simulation time 28797712 ps
CPU time 1.27 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 215644 kb
Host smart-7418a16a-5043-426a-92d3-850397fb6897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279763481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3279763481
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/25.edn_intr.2617620883
Short name T136
Test name
Test status
Simulation time 37151602 ps
CPU time 0.89 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215716 kb
Host smart-2790a4dd-f58f-44dd-b394-562ec1f29ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617620883 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2617620883
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.547796276
Short name T133
Test name
Test status
Simulation time 30307286 ps
CPU time 0.91 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:34 PM PDT 24
Peak memory 207112 kb
Host smart-78789e61-9b36-4bda-ac2c-95f4d193819e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547796276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.547796276
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/39.edn_alert.3510075993
Short name T72
Test name
Test status
Simulation time 104392775 ps
CPU time 1.29 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 215624 kb
Host smart-771b6c6c-c34e-4c13-9de8-ddf6f433690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510075993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3510075993
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.3124433498
Short name T27
Test name
Test status
Simulation time 17333633 ps
CPU time 0.83 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 215908 kb
Host smart-71841c90-d385-4c1e-80a9-7b92fb757c9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124433498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3124433498
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2449787345
Short name T253
Test name
Test status
Simulation time 167832387 ps
CPU time 2.2 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:27:19 PM PDT 24
Peak memory 205956 kb
Host smart-29af6eaf-e6f5-4234-b500-3a1e77222a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449787345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2449787345
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/161.edn_genbits.1043201402
Short name T12
Test name
Test status
Simulation time 61026532 ps
CPU time 1.41 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 219228 kb
Host smart-98f809e3-2186-465c-bfa5-9ee4ce307e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043201402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1043201402
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.262783862
Short name T223
Test name
Test status
Simulation time 49547767 ps
CPU time 0.88 seconds
Started Mar 17 12:25:55 PM PDT 24
Finished Mar 17 12:25:56 PM PDT 24
Peak memory 205672 kb
Host smart-86cbab30-5568-42ad-910e-689807a51c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262783862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.262783862
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.620792954
Short name T26
Test name
Test status
Simulation time 27337857 ps
CPU time 1.03 seconds
Started Mar 17 12:43:41 PM PDT 24
Finished Mar 17 12:43:42 PM PDT 24
Peak memory 216508 kb
Host smart-876d091e-f6d0-4e41-be1a-17c172a55504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620792954 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.620792954
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_alert.2133427665
Short name T110
Test name
Test status
Simulation time 64524862 ps
CPU time 1.13 seconds
Started Mar 17 12:43:45 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 215648 kb
Host smart-a3bed772-389a-403e-9c84-a6a0f594af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133427665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2133427665
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3890775915
Short name T178
Test name
Test status
Simulation time 58628598 ps
CPU time 1.5 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218148 kb
Host smart-a033f5a3-b4d4-4bf9-b0f2-29d8a03ea3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890775915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3890775915
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2993848727
Short name T194
Test name
Test status
Simulation time 21829318502 ps
CPU time 150.62 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:45:47 PM PDT 24
Peak memory 217764 kb
Host smart-fcb2b7f4-6970-49e5-964d-de69a9ac231c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993848727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2993848727
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_disable.4003983529
Short name T158
Test name
Test status
Simulation time 30381792 ps
CPU time 0.82 seconds
Started Mar 17 12:42:48 PM PDT 24
Finished Mar 17 12:42:49 PM PDT 24
Peak memory 215896 kb
Host smart-60b59f60-a6ce-4792-ae7b-aa03f6396de6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003983529 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4003983529
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable.486217124
Short name T163
Test name
Test status
Simulation time 12681251 ps
CPU time 0.88 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 216016 kb
Host smart-9347e81e-be34-4099-89a4-35bd3432270a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486217124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.486217124
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.82685644
Short name T172
Test name
Test status
Simulation time 64432487 ps
CPU time 0.9 seconds
Started Mar 17 12:43:42 PM PDT 24
Finished Mar 17 12:43:43 PM PDT 24
Peak memory 215916 kb
Host smart-96dcb2d1-ab8b-4628-bc19-1ddf584443f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82685644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.82685644
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.1727153178
Short name T555
Test name
Test status
Simulation time 24937812 ps
CPU time 0.92 seconds
Started Mar 17 12:42:46 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 215704 kb
Host smart-115912da-a78a-41ac-ac23-b09fc2c7f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727153178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1727153178
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2112360516
Short name T686
Test name
Test status
Simulation time 86670552 ps
CPU time 1.01 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 216692 kb
Host smart-35701d50-3089-43eb-9031-f59550d8685d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112360516 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2112360516
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/120.edn_genbits.232486622
Short name T573
Test name
Test status
Simulation time 46468092 ps
CPU time 1.51 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216736 kb
Host smart-5ee0873d-2d64-45ec-9598-3b9050d2a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232486622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.232486622
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_genbits.3521854381
Short name T264
Test name
Test status
Simulation time 43105845 ps
CPU time 1.71 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:56 PM PDT 24
Peak memory 219340 kb
Host smart-894c2d2d-89f1-432a-89ed-8cab1d910797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521854381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3521854381
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_disable.4237454949
Short name T179
Test name
Test status
Simulation time 13624791 ps
CPU time 0.89 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215656 kb
Host smart-175e2d29-17e1-4a17-b6aa-8aa52df3c6ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237454949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4237454949
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3958201797
Short name T85
Test name
Test status
Simulation time 28903146 ps
CPU time 1.13 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 216552 kb
Host smart-d644fd9d-51e4-425d-af48-2d3fa604afcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958201797 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3958201797
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_disable.2507775522
Short name T128
Test name
Test status
Simulation time 30491742 ps
CPU time 0.86 seconds
Started Mar 17 12:43:11 PM PDT 24
Finished Mar 17 12:43:12 PM PDT 24
Peak memory 215824 kb
Host smart-b885c7d6-ea4c-4266-8d96-00051cb0461c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507775522 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2507775522
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.275036629
Short name T78
Test name
Test status
Simulation time 42682704 ps
CPU time 1.3 seconds
Started Mar 17 12:42:46 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 216608 kb
Host smart-14e951cc-d763-4466-ac9a-6da82ad60f22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275036629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.275036629
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable.2845699026
Short name T165
Test name
Test status
Simulation time 19328841 ps
CPU time 0.82 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 216008 kb
Host smart-0c05f3b7-4303-48d7-bef8-2f94fdf43f49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845699026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2845699026
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2122618251
Short name T91
Test name
Test status
Simulation time 106224553 ps
CPU time 1.14 seconds
Started Mar 17 12:43:45 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 216496 kb
Host smart-5c08bbf5-8fb9-42ad-b416-3ce397a47574
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122618251 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2122618251
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_alert_test.2208453043
Short name T331
Test name
Test status
Simulation time 17948449 ps
CPU time 0.97 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 206516 kb
Host smart-ffcfec18-f234-4da1-8681-9f97072f15b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208453043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2208453043
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/176.edn_genbits.414228227
Short name T281
Test name
Test status
Simulation time 53411357 ps
CPU time 1.66 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 218220 kb
Host smart-8fc1af8a-6b6a-4b36-bfe6-540cd1c4feaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414228227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.414228227
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.1779607361
Short name T135
Test name
Test status
Simulation time 19177259 ps
CPU time 0.96 seconds
Started Mar 17 12:42:27 PM PDT 24
Finished Mar 17 12:42:29 PM PDT 24
Peak memory 207060 kb
Host smart-7c558176-cece-4f16-8648-63ac110fbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779607361 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1779607361
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_regwen.13772957
Short name T298
Test name
Test status
Simulation time 25013581 ps
CPU time 0.9 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:34 PM PDT 24
Peak memory 207112 kb
Host smart-c89627ae-02fe-41b4-99af-b2c9e82df3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13772957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.13772957
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_alert.807894162
Short name T214
Test name
Test status
Simulation time 225736497 ps
CPU time 1.31 seconds
Started Mar 17 12:42:44 PM PDT 24
Finished Mar 17 12:42:46 PM PDT 24
Peak memory 215640 kb
Host smart-c1ff16c1-a9e9-4d97-b638-49404c7e2cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807894162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.807894162
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.995526504
Short name T57
Test name
Test status
Simulation time 97602390 ps
CPU time 1.38 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217876 kb
Host smart-5d4e9c44-1ba9-48e4-9744-f7816f6f503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995526504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.995526504
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_alert.300408777
Short name T248
Test name
Test status
Simulation time 73516219 ps
CPU time 1.14 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 215792 kb
Host smart-0a00d1d8-406c-489f-8968-3b6ca52c4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300408777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.300408777
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/98.edn_genbits.902445726
Short name T202
Test name
Test status
Simulation time 144596048 ps
CPU time 1.28 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 218096 kb
Host smart-49232840-bad6-4dda-91a5-9c9f8cb5d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902445726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.902445726
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.144402310
Short name T143
Test name
Test status
Simulation time 25790912 ps
CPU time 0.87 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:34 PM PDT 24
Peak memory 215776 kb
Host smart-0077c4ed-f8fc-4388-8d95-780c02e47971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144402310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.144402310
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3957189896
Short name T232
Test name
Test status
Simulation time 14052416 ps
CPU time 1.08 seconds
Started Mar 17 12:24:27 PM PDT 24
Finished Mar 17 12:24:29 PM PDT 24
Peak memory 205904 kb
Host smart-be57f6b4-ff65-4300-882d-d3d19557b9d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957189896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3957189896
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/0.edn_stress_all.4250136546
Short name T209
Test name
Test status
Simulation time 273230337 ps
CPU time 3.01 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 216696 kb
Host smart-87d41169-0591-4633-b817-b3e0db4b602c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250136546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4250136546
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all.416968367
Short name T279
Test name
Test status
Simulation time 199092517 ps
CPU time 4.21 seconds
Started Mar 17 12:42:31 PM PDT 24
Finished Mar 17 12:42:35 PM PDT 24
Peak memory 215308 kb
Host smart-d47bb802-c31a-48e2-9fe8-c3c0dd7b3c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416968367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.416968367
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/109.edn_genbits.3257249330
Short name T274
Test name
Test status
Simulation time 72821605 ps
CPU time 2.67 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:58 PM PDT 24
Peak memory 218032 kb
Host smart-3a2800a0-2f58-41cf-8e4e-69881752d04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257249330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3257249330
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable.3358357966
Short name T288
Test name
Test status
Simulation time 18460915 ps
CPU time 0.87 seconds
Started Mar 17 12:42:46 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 215500 kb
Host smart-cb038959-1895-466f-84a0-35b21a53ed9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358357966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3358357966
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3816192645
Short name T619
Test name
Test status
Simulation time 382939037210 ps
CPU time 1571.46 seconds
Started Mar 17 12:42:48 PM PDT 24
Finished Mar 17 01:09:00 PM PDT 24
Peak memory 224420 kb
Host smart-6c898111-1404-4610-b584-dfe62e98fe7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816192645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3816192645
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.1547341800
Short name T302
Test name
Test status
Simulation time 29064317 ps
CPU time 1.36 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 215572 kb
Host smart-083b5408-e14e-4b24-b870-3d75e718f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547341800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1547341800
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.670631839
Short name T32
Test name
Test status
Simulation time 24836454 ps
CPU time 1.08 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 216764 kb
Host smart-6c5fcf91-ab02-43f3-adc4-1fcb2289f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670631839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.670631839
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1285899086
Short name T280
Test name
Test status
Simulation time 40752738 ps
CPU time 1.26 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217820 kb
Host smart-0bf0d5dd-cac5-497c-9116-fc77fbd06c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285899086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1285899086
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.747958813
Short name T152
Test name
Test status
Simulation time 29427588 ps
CPU time 1.25 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 215696 kb
Host smart-dd6de9f5-a993-48a9-91fb-e216cc3e7711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747958813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.747958813
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3358373328
Short name T271
Test name
Test status
Simulation time 202811286 ps
CPU time 1.89 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 218468 kb
Host smart-0abeb9d9-3495-429a-a962-1624df9a5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358373328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3358373328
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.268494139
Short name T269
Test name
Test status
Simulation time 231722828 ps
CPU time 3.21 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:10 PM PDT 24
Peak memory 217860 kb
Host smart-aa3edf6a-734d-455a-b97b-6324e4e7e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268494139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.268494139
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.757808453
Short name T141
Test name
Test status
Simulation time 30077113 ps
CPU time 0.84 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 215576 kb
Host smart-1710bf56-c079-4124-b2cb-49d49ea6c65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757808453 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.757808453
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.1054512817
Short name T153
Test name
Test status
Simulation time 41981264 ps
CPU time 1.23 seconds
Started Mar 17 12:42:27 PM PDT 24
Finished Mar 17 12:42:29 PM PDT 24
Peak memory 215608 kb
Host smart-a59eb5ab-1f85-4199-ae13-1a8da1b0457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054512817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1054512817
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1409827455
Short name T38
Test name
Test status
Simulation time 203951646 ps
CPU time 1.25 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 219212 kb
Host smart-23772a30-ccbd-448a-aaf0-432bb7526dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409827455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1409827455
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3707955697
Short name T180
Test name
Test status
Simulation time 63412878 ps
CPU time 2.22 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 218016 kb
Host smart-e92a9223-916d-4b30-b330-4653e92da022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707955697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3707955697
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3739094023
Short name T958
Test name
Test status
Simulation time 911786529 ps
CPU time 3.27 seconds
Started Mar 17 12:26:12 PM PDT 24
Finished Mar 17 12:26:16 PM PDT 24
Peak memory 206024 kb
Host smart-fcfaa3dc-4dac-4538-8a6b-06fe9730c030
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739094023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3739094023
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1442748047
Short name T946
Test name
Test status
Simulation time 199563529 ps
CPU time 0.84 seconds
Started Mar 17 12:23:13 PM PDT 24
Finished Mar 17 12:23:13 PM PDT 24
Peak memory 205672 kb
Host smart-661637e4-2fb8-4e8d-b89b-d63b569beb65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442748047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1442748047
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3061930171
Short name T871
Test name
Test status
Simulation time 234806665 ps
CPU time 1.6 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:13 PM PDT 24
Peak memory 222372 kb
Host smart-d030703d-9137-44fe-aac1-7ecfb90215af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061930171 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3061930171
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2130384475
Short name T956
Test name
Test status
Simulation time 23444838 ps
CPU time 0.9 seconds
Started Mar 17 12:24:35 PM PDT 24
Finished Mar 17 12:24:36 PM PDT 24
Peak memory 205840 kb
Host smart-ce64eb6f-b709-4c99-90b8-e29a2e0bc93e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130384475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2130384475
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2823542496
Short name T850
Test name
Test status
Simulation time 117157024 ps
CPU time 1.06 seconds
Started Mar 17 12:24:27 PM PDT 24
Finished Mar 17 12:24:29 PM PDT 24
Peak memory 205900 kb
Host smart-55511cc4-a944-4120-a07d-13ef3deca00d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823542496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2823542496
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.189634289
Short name T239
Test name
Test status
Simulation time 15546327 ps
CPU time 1 seconds
Started Mar 17 12:25:12 PM PDT 24
Finished Mar 17 12:25:14 PM PDT 24
Peak memory 206016 kb
Host smart-829c70d7-3b25-4ca7-9b03-ee231657e530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189634289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.189634289
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1226417794
Short name T918
Test name
Test status
Simulation time 159127807 ps
CPU time 3.06 seconds
Started Mar 17 12:23:13 PM PDT 24
Finished Mar 17 12:23:16 PM PDT 24
Peak memory 214308 kb
Host smart-757a4ea5-0f84-43e8-bb31-a9f999c2c6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226417794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1226417794
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2864919954
Short name T924
Test name
Test status
Simulation time 164876849 ps
CPU time 1.53 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:28:51 PM PDT 24
Peak memory 205956 kb
Host smart-d99692f9-b97a-48d7-8c0d-c5b2c00b1129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864919954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2864919954
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.412567285
Short name T881
Test name
Test status
Simulation time 20512396 ps
CPU time 1.31 seconds
Started Mar 17 12:23:12 PM PDT 24
Finished Mar 17 12:23:14 PM PDT 24
Peak memory 205908 kb
Host smart-aa838659-3e74-4ca5-9e75-b08be5b9edd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412567285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.412567285
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.68878797
Short name T922
Test name
Test status
Simulation time 185065110 ps
CPU time 2.7 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:35 PM PDT 24
Peak memory 205812 kb
Host smart-12dd5813-6a58-4a0d-99ac-e3cf76223a85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68878797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.68878797
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3309694518
Short name T904
Test name
Test status
Simulation time 17906697 ps
CPU time 1.04 seconds
Started Mar 17 12:25:12 PM PDT 24
Finished Mar 17 12:25:14 PM PDT 24
Peak memory 205860 kb
Host smart-c984f6cb-a910-4290-a06b-660ee7acb3cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309694518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3309694518
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3988114804
Short name T960
Test name
Test status
Simulation time 30608113 ps
CPU time 0.96 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:05 PM PDT 24
Peak memory 206112 kb
Host smart-8ab71f58-2216-4a05-a809-13e2cb23b746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988114804 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3988114804
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2403661430
Short name T925
Test name
Test status
Simulation time 15589896 ps
CPU time 0.9 seconds
Started Mar 17 12:25:10 PM PDT 24
Finished Mar 17 12:25:11 PM PDT 24
Peak memory 206220 kb
Host smart-a5cd0aa9-1544-40bb-8f22-68a4e6ee4891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403661430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2403661430
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1428423888
Short name T858
Test name
Test status
Simulation time 42358973 ps
CPU time 0.92 seconds
Started Mar 17 12:23:24 PM PDT 24
Finished Mar 17 12:23:25 PM PDT 24
Peak memory 205892 kb
Host smart-2bdbe304-d18f-44a0-b6b0-dd2de169179e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428423888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1428423888
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2275777404
Short name T917
Test name
Test status
Simulation time 19127761 ps
CPU time 1.15 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 205916 kb
Host smart-96222801-b43f-4615-81c9-9c183087265a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275777404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2275777404
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.513662699
Short name T954
Test name
Test status
Simulation time 165445808 ps
CPU time 2.89 seconds
Started Mar 17 12:25:53 PM PDT 24
Finished Mar 17 12:25:56 PM PDT 24
Peak memory 214360 kb
Host smart-6f723fc3-1910-455f-ab67-424bb822aa33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513662699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.513662699
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3655045773
Short name T909
Test name
Test status
Simulation time 57249364 ps
CPU time 1.71 seconds
Started Mar 17 12:23:17 PM PDT 24
Finished Mar 17 12:23:18 PM PDT 24
Peak memory 205872 kb
Host smart-eb999561-1da6-4d37-81d3-f35330980a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655045773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3655045773
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2051418205
Short name T886
Test name
Test status
Simulation time 31515789 ps
CPU time 1.33 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 214820 kb
Host smart-2aa4367e-ffd1-4b25-8f92-b3ebc764120b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051418205 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2051418205
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4227335351
Short name T233
Test name
Test status
Simulation time 18463203 ps
CPU time 0.96 seconds
Started Mar 17 12:24:44 PM PDT 24
Finished Mar 17 12:24:45 PM PDT 24
Peak memory 205904 kb
Host smart-80b1189f-dd3b-4a80-b450-057af95af369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227335351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4227335351
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2309353373
Short name T834
Test name
Test status
Simulation time 22202815 ps
CPU time 0.82 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 205580 kb
Host smart-c369587e-1347-437d-8139-603643382f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309353373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2309353373
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2283822866
Short name T907
Test name
Test status
Simulation time 59837162 ps
CPU time 1.12 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:25:22 PM PDT 24
Peak memory 205940 kb
Host smart-4e0a3b07-73ac-471a-becc-07c97ded43d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283822866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2283822866
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2411717926
Short name T915
Test name
Test status
Simulation time 126811215 ps
CPU time 2.29 seconds
Started Mar 17 12:25:14 PM PDT 24
Finished Mar 17 12:25:17 PM PDT 24
Peak memory 214264 kb
Host smart-e31ab522-54ea-410b-801e-1d5c87615372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411717926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2411717926
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1836098834
Short name T943
Test name
Test status
Simulation time 87340557 ps
CPU time 1.5 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:34 PM PDT 24
Peak memory 206048 kb
Host smart-4f9bacae-d4a1-4076-bba3-daebecc78621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836098834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1836098834
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3434202041
Short name T863
Test name
Test status
Simulation time 25885872 ps
CPU time 1.12 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 214204 kb
Host smart-42d608e6-cfc3-4305-8363-b59c5349e29e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434202041 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3434202041
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3415069717
Short name T228
Test name
Test status
Simulation time 129693531 ps
CPU time 0.89 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:34 PM PDT 24
Peak memory 205728 kb
Host smart-b20ec75f-1b68-4c90-bace-9cb07d6eb290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415069717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3415069717
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1613646114
Short name T832
Test name
Test status
Simulation time 47025266 ps
CPU time 0.82 seconds
Started Mar 17 12:27:54 PM PDT 24
Finished Mar 17 12:27:56 PM PDT 24
Peak memory 205660 kb
Host smart-4c2c294c-de61-48ef-a597-a2cb9b8c0b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613646114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1613646114
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3081455881
Short name T884
Test name
Test status
Simulation time 18173710 ps
CPU time 1.01 seconds
Started Mar 17 12:25:16 PM PDT 24
Finished Mar 17 12:25:17 PM PDT 24
Peak memory 206072 kb
Host smart-082be9e2-bb24-4fa3-a3cb-d76f9cfb7d3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081455881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3081455881
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.294235232
Short name T890
Test name
Test status
Simulation time 33460822 ps
CPU time 2.33 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:35 PM PDT 24
Peak memory 214176 kb
Host smart-250ebb89-2799-4168-8833-6e5d2a6d04b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294235232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.294235232
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1206652871
Short name T947
Test name
Test status
Simulation time 91704684 ps
CPU time 2.41 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:27:21 PM PDT 24
Peak memory 204304 kb
Host smart-da6ac78b-b124-40ee-bc26-c000bae36e51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206652871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1206652871
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1742468094
Short name T854
Test name
Test status
Simulation time 37562889 ps
CPU time 1.25 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 214300 kb
Host smart-6dd701b6-d885-41fc-8ee9-b40b9c7c1692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742468094 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1742468094
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.658377298
Short name T897
Test name
Test status
Simulation time 20137884 ps
CPU time 0.85 seconds
Started Mar 17 12:26:35 PM PDT 24
Finished Mar 17 12:26:36 PM PDT 24
Peak memory 205716 kb
Host smart-9643fcec-8d0c-46cb-8328-7a1b32fb6ed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658377298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.658377298
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3156373241
Short name T853
Test name
Test status
Simulation time 20896306 ps
CPU time 0.85 seconds
Started Mar 17 12:25:16 PM PDT 24
Finished Mar 17 12:25:17 PM PDT 24
Peak memory 205912 kb
Host smart-d0c2462d-6d83-4769-868b-226a1f8b84f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156373241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3156373241
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3879661664
Short name T955
Test name
Test status
Simulation time 27457236 ps
CPU time 1.32 seconds
Started Mar 17 12:25:58 PM PDT 24
Finished Mar 17 12:26:00 PM PDT 24
Peak memory 205060 kb
Host smart-1379eb5f-0b75-4e0c-8a43-3f1270da1f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879661664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3879661664
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2214723301
Short name T938
Test name
Test status
Simulation time 153673526 ps
CPU time 1.65 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:22 PM PDT 24
Peak memory 214072 kb
Host smart-57836f97-93f6-4ac8-b446-e28ee61fc2e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214723301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2214723301
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1499370761
Short name T926
Test name
Test status
Simulation time 147919306 ps
CPU time 2.96 seconds
Started Mar 17 12:25:11 PM PDT 24
Finished Mar 17 12:25:14 PM PDT 24
Peak memory 205996 kb
Host smart-671c7f17-64f1-42dc-adb6-cd1ce1142528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499370761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1499370761
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1287137308
Short name T851
Test name
Test status
Simulation time 29552743 ps
CPU time 1.37 seconds
Started Mar 17 12:26:11 PM PDT 24
Finished Mar 17 12:26:13 PM PDT 24
Peak memory 215092 kb
Host smart-99cde64e-c559-4732-83b1-bf613feceb7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287137308 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1287137308
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2087986405
Short name T227
Test name
Test status
Simulation time 42333990 ps
CPU time 0.93 seconds
Started Mar 17 12:24:53 PM PDT 24
Finished Mar 17 12:24:54 PM PDT 24
Peak memory 205776 kb
Host smart-82a9fb41-fc77-4645-aab2-074dd0cb1012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087986405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2087986405
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1667059833
Short name T876
Test name
Test status
Simulation time 18767154 ps
CPU time 0.87 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 205904 kb
Host smart-60323772-d3c7-4569-af22-3e9bb4199f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667059833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1667059833
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.270723456
Short name T900
Test name
Test status
Simulation time 34558034 ps
CPU time 1.38 seconds
Started Mar 17 12:27:22 PM PDT 24
Finished Mar 17 12:27:23 PM PDT 24
Peak memory 205100 kb
Host smart-960fd96b-caa8-40f3-b1d3-80023745e61c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270723456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.270723456
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2961326802
Short name T932
Test name
Test status
Simulation time 596770451 ps
CPU time 3.73 seconds
Started Mar 17 12:24:49 PM PDT 24
Finished Mar 17 12:24:53 PM PDT 24
Peak memory 214296 kb
Host smart-06f51ada-1f04-44ee-87e0-a2c70f4c2e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961326802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2961326802
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1100812419
Short name T961
Test name
Test status
Simulation time 128328935 ps
CPU time 1.76 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 205984 kb
Host smart-0f0ea6f2-2e77-4f47-a0b9-8500ea4a1919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100812419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1100812419
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3051303700
Short name T921
Test name
Test status
Simulation time 119779369 ps
CPU time 1.13 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 214272 kb
Host smart-e52a4f8f-f0dc-40a0-b8a3-a446ee9cba13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051303700 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3051303700
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1285629334
Short name T913
Test name
Test status
Simulation time 15226361 ps
CPU time 0.91 seconds
Started Mar 17 12:26:16 PM PDT 24
Finished Mar 17 12:26:17 PM PDT 24
Peak memory 205812 kb
Host smart-0da0daa4-90a7-463e-9aab-98c7cd952ca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285629334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1285629334
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.461458930
Short name T847
Test name
Test status
Simulation time 56653862 ps
CPU time 0.77 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 205640 kb
Host smart-65a638d1-1e17-4ee7-9b14-818588868da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461458930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.461458930
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3272642116
Short name T864
Test name
Test status
Simulation time 38837876 ps
CPU time 1.53 seconds
Started Mar 17 12:25:23 PM PDT 24
Finished Mar 17 12:25:25 PM PDT 24
Peak memory 205964 kb
Host smart-e886e4ac-5878-4b03-ad93-45970b334249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272642116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3272642116
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1993516822
Short name T959
Test name
Test status
Simulation time 212183241 ps
CPU time 3.68 seconds
Started Mar 17 12:26:11 PM PDT 24
Finished Mar 17 12:26:15 PM PDT 24
Peak memory 213016 kb
Host smart-233faf16-7db3-4899-8d65-218a4ecf3b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993516822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1993516822
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1362457057
Short name T941
Test name
Test status
Simulation time 137832167 ps
CPU time 2.14 seconds
Started Mar 17 12:25:16 PM PDT 24
Finished Mar 17 12:25:18 PM PDT 24
Peak memory 206040 kb
Host smart-7f5f622a-2566-458d-9568-19744f90abb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362457057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1362457057
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4013977470
Short name T875
Test name
Test status
Simulation time 46744512 ps
CPU time 0.98 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 212880 kb
Host smart-b1e7b2a4-7096-4f2b-9170-77d81ca85e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013977470 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4013977470
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3711504461
Short name T940
Test name
Test status
Simulation time 35300415 ps
CPU time 0.92 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 204936 kb
Host smart-059c14cf-f290-4d23-850d-fd3d4761c90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711504461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3711504461
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3012932212
Short name T912
Test name
Test status
Simulation time 28960946 ps
CPU time 0.83 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 205772 kb
Host smart-b98ccd9a-b69d-4a66-9195-68abfa59b45c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012932212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3012932212
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3519541588
Short name T892
Test name
Test status
Simulation time 19548846 ps
CPU time 1.1 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 205964 kb
Host smart-3bda79a8-eee9-44ac-89cf-1b5cbff41435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519541588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3519541588
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3939179927
Short name T838
Test name
Test status
Simulation time 42449777 ps
CPU time 2.64 seconds
Started Mar 17 12:25:05 PM PDT 24
Finished Mar 17 12:25:07 PM PDT 24
Peak memory 214460 kb
Host smart-b138d0c4-2aa6-40bc-98f5-a4eac21a8e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939179927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3939179927
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1333991845
Short name T872
Test name
Test status
Simulation time 86490650 ps
CPU time 1.73 seconds
Started Mar 17 12:25:23 PM PDT 24
Finished Mar 17 12:25:25 PM PDT 24
Peak memory 205960 kb
Host smart-e5c05dab-2cbd-43dd-a152-5d0405f7f8b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333991845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1333991845
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1278207079
Short name T852
Test name
Test status
Simulation time 54322960 ps
CPU time 1.41 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 213032 kb
Host smart-4160d8b2-d7d7-425e-956b-9dfd340c1b31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278207079 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1278207079
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1964785776
Short name T923
Test name
Test status
Simulation time 23275907 ps
CPU time 0.85 seconds
Started Mar 17 12:27:07 PM PDT 24
Finished Mar 17 12:27:08 PM PDT 24
Peak memory 205824 kb
Host smart-2d772d88-5c29-4301-ab7d-085dfa7eb839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964785776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1964785776
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2510915739
Short name T952
Test name
Test status
Simulation time 24850176 ps
CPU time 0.85 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:28:36 PM PDT 24
Peak memory 205840 kb
Host smart-26131688-50ef-4c5c-9555-acda94671bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510915739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2510915739
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2693231350
Short name T950
Test name
Test status
Simulation time 53738357 ps
CPU time 1.53 seconds
Started Mar 17 12:24:59 PM PDT 24
Finished Mar 17 12:25:01 PM PDT 24
Peak memory 206048 kb
Host smart-1bc54738-9779-4214-b880-8f64bbad7ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693231350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2693231350
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3095501126
Short name T957
Test name
Test status
Simulation time 116495196 ps
CPU time 3.85 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:15 PM PDT 24
Peak memory 214204 kb
Host smart-b2158eca-41ad-4b47-9232-ddd4f78797c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095501126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3095501126
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1042973436
Short name T846
Test name
Test status
Simulation time 31462443 ps
CPU time 1.03 seconds
Started Mar 17 12:25:04 PM PDT 24
Finished Mar 17 12:25:05 PM PDT 24
Peak memory 214268 kb
Host smart-7ce00d53-d19a-467c-9c63-e1edc349c01d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042973436 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1042973436
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.638327656
Short name T229
Test name
Test status
Simulation time 24718846 ps
CPU time 0.8 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:13 PM PDT 24
Peak memory 205612 kb
Host smart-b9466fb1-3960-46c2-a200-1c52696bba21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638327656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.638327656
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1937499293
Short name T903
Test name
Test status
Simulation time 61884783 ps
CPU time 0.89 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 205588 kb
Host smart-94e076e5-9d3c-4635-b4e9-94e507900b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937499293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1937499293
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2624587387
Short name T221
Test name
Test status
Simulation time 107785331 ps
CPU time 1.06 seconds
Started Mar 17 12:25:05 PM PDT 24
Finished Mar 17 12:25:06 PM PDT 24
Peak memory 205992 kb
Host smart-56941a05-4447-402e-8cff-474f379cb446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624587387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2624587387
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1944977417
Short name T837
Test name
Test status
Simulation time 42105214 ps
CPU time 2.87 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:26:13 PM PDT 24
Peak memory 214268 kb
Host smart-ad79bc9a-a542-4e56-97f3-4460c040b015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944977417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1944977417
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2628316534
Short name T893
Test name
Test status
Simulation time 127144636 ps
CPU time 2.64 seconds
Started Mar 17 12:26:59 PM PDT 24
Finished Mar 17 12:27:02 PM PDT 24
Peak memory 205996 kb
Host smart-e3294065-d109-49cf-95f5-670cdf4533f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628316534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2628316534
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3089721676
Short name T879
Test name
Test status
Simulation time 24855615 ps
CPU time 1.02 seconds
Started Mar 17 12:25:15 PM PDT 24
Finished Mar 17 12:25:16 PM PDT 24
Peak memory 206168 kb
Host smart-af9386ce-a867-4a9d-8125-d0c064c4a569
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089721676 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3089721676
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3026594923
Short name T231
Test name
Test status
Simulation time 81938436 ps
CPU time 0.85 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:05 PM PDT 24
Peak memory 205724 kb
Host smart-55b358a2-43bd-4e2a-bd33-1825d5b38f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026594923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3026594923
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2382933711
Short name T944
Test name
Test status
Simulation time 27295896 ps
CPU time 0.86 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:44 PM PDT 24
Peak memory 205792 kb
Host smart-a3b3b7e9-71dd-4800-8eae-4cc99bda9fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382933711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2382933711
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3772025385
Short name T901
Test name
Test status
Simulation time 69423292 ps
CPU time 1.2 seconds
Started Mar 17 12:25:57 PM PDT 24
Finished Mar 17 12:25:59 PM PDT 24
Peak memory 206096 kb
Host smart-f6a04f1c-c57f-4a4d-8c44-e9d26d60788b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772025385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3772025385
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1245376594
Short name T942
Test name
Test status
Simulation time 170905217 ps
CPU time 3.32 seconds
Started Mar 17 12:25:11 PM PDT 24
Finished Mar 17 12:25:15 PM PDT 24
Peak memory 214264 kb
Host smart-4783ec0e-aaec-4098-ab48-acfeaa86ffe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245376594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1245376594
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1473170218
Short name T255
Test name
Test status
Simulation time 271960538 ps
CPU time 1.39 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:34 PM PDT 24
Peak memory 205988 kb
Host smart-7979a5cf-e01c-4331-a28b-9ebf19b730fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473170218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1473170218
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1469360879
Short name T883
Test name
Test status
Simulation time 51890711 ps
CPU time 1.36 seconds
Started Mar 17 12:25:12 PM PDT 24
Finished Mar 17 12:25:14 PM PDT 24
Peak memory 214264 kb
Host smart-838b655d-2d05-4f7a-a580-8cb4e5332169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469360879 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1469360879
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2253951521
Short name T899
Test name
Test status
Simulation time 23176521 ps
CPU time 0.88 seconds
Started Mar 17 12:25:11 PM PDT 24
Finished Mar 17 12:25:12 PM PDT 24
Peak memory 205872 kb
Host smart-fcc29acf-7fd6-4280-aa8d-e878622b08ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253951521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2253951521
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3643056367
Short name T934
Test name
Test status
Simulation time 180049800 ps
CPU time 0.96 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 205252 kb
Host smart-5015ceff-0d45-4275-bdba-a010c07a1b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643056367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3643056367
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2845099441
Short name T860
Test name
Test status
Simulation time 985481925 ps
CPU time 3.1 seconds
Started Mar 17 12:25:57 PM PDT 24
Finished Mar 17 12:26:01 PM PDT 24
Peak memory 214396 kb
Host smart-1065fbdf-5ec9-4664-be45-095bff41181d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845099441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2845099441
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3662035046
Short name T914
Test name
Test status
Simulation time 238671079 ps
CPU time 2.6 seconds
Started Mar 17 12:25:21 PM PDT 24
Finished Mar 17 12:25:25 PM PDT 24
Peak memory 205972 kb
Host smart-08a6488f-ca77-40a6-b989-73839c1120eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662035046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3662035046
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1262160613
Short name T243
Test name
Test status
Simulation time 42006166 ps
CPU time 0.97 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:24 PM PDT 24
Peak memory 205812 kb
Host smart-168d62e2-3b8c-4ba6-a1c2-066411fa405e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262160613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1262160613
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1975197342
Short name T878
Test name
Test status
Simulation time 228435956 ps
CPU time 3.1 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:26 PM PDT 24
Peak memory 205732 kb
Host smart-fb8b6168-7a91-49d5-939d-e4c1ae35fab4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975197342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1975197342
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.656967336
Short name T234
Test name
Test status
Simulation time 28198578 ps
CPU time 1.01 seconds
Started Mar 17 12:24:53 PM PDT 24
Finished Mar 17 12:24:54 PM PDT 24
Peak memory 205772 kb
Host smart-23e4c2ba-fa27-4e68-bd7b-c683a27e89fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656967336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.656967336
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4242962884
Short name T948
Test name
Test status
Simulation time 39479747 ps
CPU time 0.87 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 205936 kb
Host smart-dd877812-a914-4cb9-ba47-96960256caf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242962884 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4242962884
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2221618503
Short name T222
Test name
Test status
Simulation time 14203877 ps
CPU time 0.91 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:05 PM PDT 24
Peak memory 205908 kb
Host smart-fb95acb0-3237-44dc-85d3-533205f22f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221618503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2221618503
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3567887446
Short name T928
Test name
Test status
Simulation time 22197619 ps
CPU time 0.9 seconds
Started Mar 17 12:25:05 PM PDT 24
Finished Mar 17 12:25:06 PM PDT 24
Peak memory 205824 kb
Host smart-30d05bc7-7a3e-4c33-9c77-e14acc1b5af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567887446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3567887446
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2500989692
Short name T936
Test name
Test status
Simulation time 19972626 ps
CPU time 0.94 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:27:19 PM PDT 24
Peak memory 204600 kb
Host smart-7f69f93b-8209-44a2-8f32-7cfe20949775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500989692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2500989692
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3556916869
Short name T951
Test name
Test status
Simulation time 82950027 ps
CPU time 2.83 seconds
Started Mar 17 12:23:37 PM PDT 24
Finished Mar 17 12:23:40 PM PDT 24
Peak memory 214548 kb
Host smart-101be889-0029-4586-b67e-ba709f7dbf03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556916869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3556916869
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1754187730
Short name T254
Test name
Test status
Simulation time 290842762 ps
CPU time 2.25 seconds
Started Mar 17 12:25:05 PM PDT 24
Finished Mar 17 12:25:08 PM PDT 24
Peak memory 205996 kb
Host smart-5c420a1d-82d7-4ad5-a1d4-146049983ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754187730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1754187730
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1178857931
Short name T865
Test name
Test status
Simulation time 21822518 ps
CPU time 0.84 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 205764 kb
Host smart-780c586b-dd15-4d92-9911-d18082e62b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178857931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1178857931
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.523579515
Short name T895
Test name
Test status
Simulation time 43513047 ps
CPU time 0.79 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 205812 kb
Host smart-7c109d38-7d78-4ec9-ac0a-1659175f5ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523579515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.523579515
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2681979540
Short name T887
Test name
Test status
Simulation time 26261423 ps
CPU time 0.83 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 205744 kb
Host smart-0e4f759c-7cd6-4552-a7fb-d4836ef2ea1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681979540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2681979540
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4085409529
Short name T920
Test name
Test status
Simulation time 35212683 ps
CPU time 0.82 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 204256 kb
Host smart-ceecc48b-17e1-4de4-a353-2c0b4aea8cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085409529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4085409529
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3589269494
Short name T885
Test name
Test status
Simulation time 13114158 ps
CPU time 0.85 seconds
Started Mar 17 12:25:15 PM PDT 24
Finished Mar 17 12:25:16 PM PDT 24
Peak memory 205912 kb
Host smart-6eb1417b-8c2f-40cb-90a0-6df23771c35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589269494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3589269494
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.300042287
Short name T839
Test name
Test status
Simulation time 96508876 ps
CPU time 0.78 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 205744 kb
Host smart-9abe9a73-0c49-4298-98bd-077564eb63a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300042287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.300042287
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2175564166
Short name T873
Test name
Test status
Simulation time 12741752 ps
CPU time 0.88 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 205296 kb
Host smart-4e8ae35b-f070-4743-bf43-db5d2303c6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175564166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2175564166
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2395392441
Short name T862
Test name
Test status
Simulation time 26933230 ps
CPU time 0.85 seconds
Started Mar 17 12:25:10 PM PDT 24
Finished Mar 17 12:25:11 PM PDT 24
Peak memory 205900 kb
Host smart-6255eefb-93b9-42b4-96c8-a3bbc3863532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395392441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2395392441
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3845741502
Short name T911
Test name
Test status
Simulation time 29970999 ps
CPU time 0.86 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:25:22 PM PDT 24
Peak memory 205836 kb
Host smart-1a8d1ffb-d2c0-4ffa-812e-64516fc92469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845741502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3845741502
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1854677094
Short name T945
Test name
Test status
Simulation time 15997092 ps
CPU time 0.87 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 205760 kb
Host smart-51748d1f-f1f9-4cc8-8451-03e1b048f32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854677094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1854677094
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3569971186
Short name T230
Test name
Test status
Simulation time 39998844 ps
CPU time 1.49 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 205636 kb
Host smart-757fb6fb-e79d-4f03-b537-c113305faf5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569971186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3569971186
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3856108731
Short name T224
Test name
Test status
Simulation time 135470921 ps
CPU time 1.89 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 205568 kb
Host smart-70efe263-297d-4a28-a45f-e5c1f9d1c4a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856108731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3856108731
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2893462005
Short name T226
Test name
Test status
Simulation time 27143022 ps
CPU time 1.11 seconds
Started Mar 17 12:22:50 PM PDT 24
Finished Mar 17 12:22:52 PM PDT 24
Peak memory 205752 kb
Host smart-22d1c60a-f5ff-4ff6-bed7-ff555db10d8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893462005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2893462005
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3771643308
Short name T869
Test name
Test status
Simulation time 46098524 ps
CPU time 1.11 seconds
Started Mar 17 12:28:13 PM PDT 24
Finished Mar 17 12:28:15 PM PDT 24
Peak memory 214172 kb
Host smart-3eda637f-ff4d-4472-bffd-3f4e8017e803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771643308 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3771643308
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3356496967
Short name T905
Test name
Test status
Simulation time 78324064 ps
CPU time 0.87 seconds
Started Mar 17 12:26:07 PM PDT 24
Finished Mar 17 12:26:08 PM PDT 24
Peak memory 205716 kb
Host smart-dae51b28-4383-4fe7-8624-343c06259d20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356496967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3356496967
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3055393863
Short name T953
Test name
Test status
Simulation time 25494606 ps
CPU time 0.86 seconds
Started Mar 17 12:23:20 PM PDT 24
Finished Mar 17 12:23:21 PM PDT 24
Peak memory 206032 kb
Host smart-ccf96d26-b064-47b3-be81-5d6745f0f06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055393863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3055393863
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2556689918
Short name T236
Test name
Test status
Simulation time 79712916 ps
CPU time 1.06 seconds
Started Mar 17 12:25:44 PM PDT 24
Finished Mar 17 12:25:45 PM PDT 24
Peak memory 206356 kb
Host smart-784ef920-130e-4523-8b9a-9d2f8eec126f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556689918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2556689918
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2898019795
Short name T919
Test name
Test status
Simulation time 164313782 ps
CPU time 2.21 seconds
Started Mar 17 12:25:26 PM PDT 24
Finished Mar 17 12:25:28 PM PDT 24
Peak memory 214320 kb
Host smart-c2d40d18-b680-41ca-bffb-7be3e0a4a60a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898019795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2898019795
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3387296031
Short name T908
Test name
Test status
Simulation time 126460834 ps
CPU time 1.69 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:39 PM PDT 24
Peak memory 206060 kb
Host smart-688d02c1-868a-433d-828e-f803dd641462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387296031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3387296031
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1613441279
Short name T845
Test name
Test status
Simulation time 12950768 ps
CPU time 0.83 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 205608 kb
Host smart-58f4a1b7-e0b0-4f17-a8f9-876a3362edd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613441279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1613441279
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3092419314
Short name T889
Test name
Test status
Simulation time 14166185 ps
CPU time 0.89 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:26:11 PM PDT 24
Peak memory 205936 kb
Host smart-a9555e7e-8d2a-4b32-bed7-e6c2a2a36753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092419314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3092419314
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1861593209
Short name T867
Test name
Test status
Simulation time 33816878 ps
CPU time 0.79 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 205768 kb
Host smart-7859e13f-8dbc-4cdf-8ef6-be6afbd7303f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861593209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1861593209
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1224753353
Short name T859
Test name
Test status
Simulation time 47495146 ps
CPU time 0.87 seconds
Started Mar 17 12:27:14 PM PDT 24
Finished Mar 17 12:27:15 PM PDT 24
Peak memory 204704 kb
Host smart-52126568-8214-4e8c-bb18-ec5e0cb02656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224753353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1224753353
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3633358898
Short name T835
Test name
Test status
Simulation time 19988085 ps
CPU time 0.9 seconds
Started Mar 17 12:25:14 PM PDT 24
Finished Mar 17 12:25:16 PM PDT 24
Peak memory 205896 kb
Host smart-e76fc43a-e755-4c9c-af26-67c2bcfb79b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633358898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3633358898
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.4023581818
Short name T831
Test name
Test status
Simulation time 35638355 ps
CPU time 0.84 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 205444 kb
Host smart-b5ce7a8b-e539-4315-807c-7e5bcd873f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023581818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.4023581818
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3218544933
Short name T857
Test name
Test status
Simulation time 15389699 ps
CPU time 0.9 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 205128 kb
Host smart-fca8522a-0806-4c5f-af3b-666396241fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218544933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3218544933
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.909461034
Short name T882
Test name
Test status
Simulation time 180198341 ps
CPU time 0.94 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:28:06 PM PDT 24
Peak memory 205768 kb
Host smart-9a268646-27d4-45c2-a330-6794589a22b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909461034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.909461034
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3047150803
Short name T870
Test name
Test status
Simulation time 49417662 ps
CPU time 0.86 seconds
Started Mar 17 12:27:48 PM PDT 24
Finished Mar 17 12:27:49 PM PDT 24
Peak memory 205708 kb
Host smart-49b6f8a5-e301-49d2-b9eb-15c269e4e15d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047150803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3047150803
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1146350609
Short name T861
Test name
Test status
Simulation time 13401971 ps
CPU time 0.83 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 205240 kb
Host smart-47bc4ef4-0d5b-40f7-b0e1-a9eddac599dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146350609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1146350609
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2133131212
Short name T902
Test name
Test status
Simulation time 59083967 ps
CPU time 1.04 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 206008 kb
Host smart-2a83cdd8-8043-444b-930f-5d9383d63b21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133131212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2133131212
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2511384856
Short name T929
Test name
Test status
Simulation time 35224129 ps
CPU time 2 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 204368 kb
Host smart-01219834-324e-4b4f-845d-23235e9d2689
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511384856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2511384856
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.192214067
Short name T866
Test name
Test status
Simulation time 23441074 ps
CPU time 0.88 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:26:37 PM PDT 24
Peak memory 204572 kb
Host smart-087e7288-4961-4f45-98e1-7704fb884dc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192214067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.192214067
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1531057926
Short name T836
Test name
Test status
Simulation time 28359191 ps
CPU time 0.94 seconds
Started Mar 17 12:26:16 PM PDT 24
Finished Mar 17 12:26:17 PM PDT 24
Peak memory 206012 kb
Host smart-0f14d7b4-f07a-4b34-92c1-9340f6d811fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531057926 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1531057926
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3399774708
Short name T242
Test name
Test status
Simulation time 35823984 ps
CPU time 0.85 seconds
Started Mar 17 12:25:15 PM PDT 24
Finished Mar 17 12:25:16 PM PDT 24
Peak memory 205900 kb
Host smart-00391295-d4a9-4a3a-a4d2-de50fc58dd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399774708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3399774708
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1287764737
Short name T888
Test name
Test status
Simulation time 15109403 ps
CPU time 0.99 seconds
Started Mar 17 12:26:35 PM PDT 24
Finished Mar 17 12:26:37 PM PDT 24
Peak memory 204444 kb
Host smart-bc71704f-2e35-4e8c-96cf-31a1f8ae93f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287764737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1287764737
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.255860552
Short name T240
Test name
Test status
Simulation time 25222806 ps
CPU time 1.08 seconds
Started Mar 17 12:26:50 PM PDT 24
Finished Mar 17 12:26:51 PM PDT 24
Peak memory 205944 kb
Host smart-ead6a4aa-19be-48b1-881e-8b77d85dc41a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255860552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.255860552
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.494413678
Short name T842
Test name
Test status
Simulation time 26924218 ps
CPU time 1.75 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 214216 kb
Host smart-3b7828d4-08c7-47d6-b34f-870d3865be32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494413678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.494413678
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1498489817
Short name T247
Test name
Test status
Simulation time 275531488 ps
CPU time 2.26 seconds
Started Mar 17 12:23:13 PM PDT 24
Finished Mar 17 12:23:15 PM PDT 24
Peak memory 206108 kb
Host smart-e0cc3951-ff4b-4bf1-a8b0-fecaf8ab0129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498489817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1498489817
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.389602492
Short name T855
Test name
Test status
Simulation time 19508655 ps
CPU time 0.88 seconds
Started Mar 17 12:25:11 PM PDT 24
Finished Mar 17 12:25:12 PM PDT 24
Peak memory 205712 kb
Host smart-e544d46d-8e75-4e71-828e-2d8984a466ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389602492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.389602492
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.300045771
Short name T964
Test name
Test status
Simulation time 46659617 ps
CPU time 0.83 seconds
Started Mar 17 12:28:28 PM PDT 24
Finished Mar 17 12:28:29 PM PDT 24
Peak memory 205752 kb
Host smart-0f3a9807-6495-4cce-a01e-cb1dbf09e21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300045771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.300045771
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2395641507
Short name T856
Test name
Test status
Simulation time 45326852 ps
CPU time 0.81 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:28:35 PM PDT 24
Peak memory 205632 kb
Host smart-a48b06b2-cd01-429c-9b40-d0d61b927e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395641507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2395641507
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3197324816
Short name T848
Test name
Test status
Simulation time 31201009 ps
CPU time 0.89 seconds
Started Mar 17 12:27:49 PM PDT 24
Finished Mar 17 12:27:50 PM PDT 24
Peak memory 205728 kb
Host smart-9f964650-8c26-4a62-95f5-424848af1ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197324816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3197324816
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2086764245
Short name T949
Test name
Test status
Simulation time 59787090 ps
CPU time 0.91 seconds
Started Mar 17 12:27:24 PM PDT 24
Finished Mar 17 12:27:26 PM PDT 24
Peak memory 204644 kb
Host smart-d6d444ab-0f83-455e-821c-9d633310dd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086764245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2086764245
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.141273806
Short name T963
Test name
Test status
Simulation time 36945225 ps
CPU time 0.87 seconds
Started Mar 17 12:28:32 PM PDT 24
Finished Mar 17 12:28:33 PM PDT 24
Peak memory 205856 kb
Host smart-8d85aee7-f2a1-45fb-8a5f-a8ba7ef4480f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141273806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.141273806
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.553325258
Short name T877
Test name
Test status
Simulation time 19461444 ps
CPU time 0.95 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 205744 kb
Host smart-9d0046fe-e5a4-4fa8-ba93-b8dea8035b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553325258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.553325258
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4054554408
Short name T927
Test name
Test status
Simulation time 12728769 ps
CPU time 0.82 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 205772 kb
Host smart-eccc9993-8db2-488e-a804-fb5f5bbf8c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054554408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4054554408
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.973126980
Short name T910
Test name
Test status
Simulation time 34334453 ps
CPU time 0.76 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 205616 kb
Host smart-3df566a7-eb35-4e38-875c-ce5d0987770f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973126980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.973126980
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.41361319
Short name T841
Test name
Test status
Simulation time 15991713 ps
CPU time 0.79 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:27:57 PM PDT 24
Peak memory 205524 kb
Host smart-6ba8f54f-4cfd-4ad1-9c98-4df86746a94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41361319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.41361319
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2753836648
Short name T830
Test name
Test status
Simulation time 34832892 ps
CPU time 0.87 seconds
Started Mar 17 12:26:28 PM PDT 24
Finished Mar 17 12:26:29 PM PDT 24
Peak memory 205988 kb
Host smart-95432b6a-b9ad-4737-a67c-d9b6fe6910d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753836648 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2753836648
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3225197388
Short name T225
Test name
Test status
Simulation time 19762345 ps
CPU time 0.9 seconds
Started Mar 17 12:26:35 PM PDT 24
Finished Mar 17 12:26:37 PM PDT 24
Peak memory 204336 kb
Host smart-8efcfdda-28f5-434d-a16b-da7b520cfc39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225197388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3225197388
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2906477719
Short name T880
Test name
Test status
Simulation time 23758300 ps
CPU time 0.9 seconds
Started Mar 17 12:26:07 PM PDT 24
Finished Mar 17 12:26:08 PM PDT 24
Peak memory 205904 kb
Host smart-8c9b93da-e6d2-415c-9cc6-2abdefba29ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906477719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2906477719
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1819399922
Short name T237
Test name
Test status
Simulation time 29001307 ps
CPU time 1.12 seconds
Started Mar 17 12:24:43 PM PDT 24
Finished Mar 17 12:24:44 PM PDT 24
Peak memory 206020 kb
Host smart-9bde0572-11c1-41fa-b45b-8438aa8c2d8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819399922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1819399922
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2087634514
Short name T931
Test name
Test status
Simulation time 37977616 ps
CPU time 1.69 seconds
Started Mar 17 12:27:34 PM PDT 24
Finished Mar 17 12:27:36 PM PDT 24
Peak memory 214156 kb
Host smart-655d7f7b-d041-4527-a06e-718d8bbeb23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087634514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2087634514
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3519422782
Short name T245
Test name
Test status
Simulation time 209943737 ps
CPU time 1.46 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 206060 kb
Host smart-e6b4840d-236e-47f8-8f00-ff415a65f520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519422782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3519422782
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3503631607
Short name T894
Test name
Test status
Simulation time 111428806 ps
CPU time 1.26 seconds
Started Mar 17 12:25:25 PM PDT 24
Finished Mar 17 12:25:26 PM PDT 24
Peak memory 214364 kb
Host smart-25f7c364-9f5b-4daf-8fb1-c9a0cc740477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503631607 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3503631607
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.263542313
Short name T238
Test name
Test status
Simulation time 21189469 ps
CPU time 0.86 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 205796 kb
Host smart-5601f500-9e19-42a0-aef6-31d2d49b89ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263542313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.263542313
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2696852579
Short name T906
Test name
Test status
Simulation time 33719019 ps
CPU time 0.9 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:26:54 PM PDT 24
Peak memory 204516 kb
Host smart-2b8fbe6a-1798-4f43-bfeb-143c50e0c2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696852579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2696852579
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3539963083
Short name T898
Test name
Test status
Simulation time 42989895 ps
CPU time 1.18 seconds
Started Mar 17 12:26:54 PM PDT 24
Finished Mar 17 12:26:56 PM PDT 24
Peak memory 205892 kb
Host smart-1a0b4efe-06fe-49f8-9d42-ac9c1ce7d1d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539963083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3539963083
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2162268398
Short name T930
Test name
Test status
Simulation time 227816225 ps
CPU time 3.71 seconds
Started Mar 17 12:23:38 PM PDT 24
Finished Mar 17 12:23:41 PM PDT 24
Peak memory 214268 kb
Host smart-8d19d4b4-579c-41e7-8e18-c9dd6d8082d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162268398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2162268398
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3044823717
Short name T874
Test name
Test status
Simulation time 93147980 ps
CPU time 1.53 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 205936 kb
Host smart-d72049eb-cc75-4b1f-a3e5-0c5ffa064a32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044823717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3044823717
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1526327264
Short name T937
Test name
Test status
Simulation time 42048986 ps
CPU time 1.37 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 214056 kb
Host smart-74161282-53af-4053-92c4-2927681a4787
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526327264 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1526327264
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2099947411
Short name T244
Test name
Test status
Simulation time 24379970 ps
CPU time 0.84 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 205800 kb
Host smart-8fb31a40-a5ed-43e2-982c-c28671e714db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099947411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2099947411
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.459512060
Short name T840
Test name
Test status
Simulation time 49263474 ps
CPU time 0.83 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 205516 kb
Host smart-f0862282-54b2-4435-9796-57cc006d3c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459512060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.459512060
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1466397459
Short name T868
Test name
Test status
Simulation time 42876218 ps
CPU time 1.13 seconds
Started Mar 17 12:26:14 PM PDT 24
Finished Mar 17 12:26:15 PM PDT 24
Peak memory 206152 kb
Host smart-9bdc2a67-705a-486b-8b91-4a993d470af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466397459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1466397459
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2520064944
Short name T939
Test name
Test status
Simulation time 350957826 ps
CPU time 3.49 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:26:09 PM PDT 24
Peak memory 214196 kb
Host smart-09432502-7222-49be-9b4d-34d2200950ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520064944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2520064944
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.445345618
Short name T896
Test name
Test status
Simulation time 55475969 ps
CPU time 1.64 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:45 PM PDT 24
Peak memory 205984 kb
Host smart-079264db-fcad-40d2-81f8-bcdfec1686ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445345618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.445345618
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2705805222
Short name T844
Test name
Test status
Simulation time 55551343 ps
CPU time 1.3 seconds
Started Mar 17 12:25:25 PM PDT 24
Finished Mar 17 12:25:27 PM PDT 24
Peak memory 214368 kb
Host smart-53f89118-f689-454d-8c19-11e95543a0d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705805222 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2705805222
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1546015785
Short name T235
Test name
Test status
Simulation time 25019325 ps
CPU time 0.91 seconds
Started Mar 17 12:25:30 PM PDT 24
Finished Mar 17 12:25:31 PM PDT 24
Peak memory 206020 kb
Host smart-79cd742b-ed23-4ee1-b26f-13d6e9f88034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546015785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1546015785
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.549240512
Short name T833
Test name
Test status
Simulation time 17096160 ps
CPU time 1.01 seconds
Started Mar 17 12:26:54 PM PDT 24
Finished Mar 17 12:26:55 PM PDT 24
Peak memory 205812 kb
Host smart-e54dd782-e2fb-4a86-bc33-d42065aa9d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549240512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.549240512
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2661986392
Short name T241
Test name
Test status
Simulation time 93368318 ps
CPU time 1.42 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:09 PM PDT 24
Peak memory 205948 kb
Host smart-6911e0ca-6051-409c-b16d-1019cacdf4f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661986392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2661986392
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3681930522
Short name T935
Test name
Test status
Simulation time 181843553 ps
CPU time 1.83 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 214004 kb
Host smart-d2901673-1dc4-41d8-a490-3a522a2515aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681930522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3681930522
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.307109730
Short name T246
Test name
Test status
Simulation time 61066743 ps
CPU time 1.82 seconds
Started Mar 17 12:27:39 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 205980 kb
Host smart-396b874d-439d-4273-861a-624c4a01f1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307109730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.307109730
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4014885879
Short name T916
Test name
Test status
Simulation time 138201902 ps
CPU time 1.49 seconds
Started Mar 17 12:25:12 PM PDT 24
Finished Mar 17 12:25:14 PM PDT 24
Peak memory 214304 kb
Host smart-6fff7c7a-8559-4887-9e51-a05b90656381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014885879 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4014885879
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2858445123
Short name T849
Test name
Test status
Simulation time 24115099 ps
CPU time 0.86 seconds
Started Mar 17 12:27:30 PM PDT 24
Finished Mar 17 12:27:31 PM PDT 24
Peak memory 205500 kb
Host smart-090e695c-4d8b-424c-8ba1-f27b6bf145d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858445123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2858445123
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.233871939
Short name T962
Test name
Test status
Simulation time 12507917 ps
CPU time 0.88 seconds
Started Mar 17 12:24:38 PM PDT 24
Finished Mar 17 12:24:39 PM PDT 24
Peak memory 205788 kb
Host smart-a9c5d830-ebfd-45c6-871c-d940909e3714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233871939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.233871939
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2847971110
Short name T933
Test name
Test status
Simulation time 20951150 ps
CPU time 1.13 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 205700 kb
Host smart-d762f071-489f-40c3-b19d-00b15e9fa225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847971110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2847971110
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2736274204
Short name T843
Test name
Test status
Simulation time 299639587 ps
CPU time 3.43 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:36 PM PDT 24
Peak memory 214204 kb
Host smart-51cc93db-2af5-40df-b4bd-560a94a089fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736274204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2736274204
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4018040452
Short name T891
Test name
Test status
Simulation time 65875899 ps
CPU time 2.01 seconds
Started Mar 17 12:24:41 PM PDT 24
Finished Mar 17 12:24:43 PM PDT 24
Peak memory 205988 kb
Host smart-07c72225-7058-4ebd-88cf-069e98a38166
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018040452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4018040452
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2303030897
Short name T479
Test name
Test status
Simulation time 24433249 ps
CPU time 0.95 seconds
Started Mar 17 12:42:31 PM PDT 24
Finished Mar 17 12:42:32 PM PDT 24
Peak memory 206868 kb
Host smart-eac6d616-4e81-49b9-a31d-e46cbd396143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303030897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2303030897
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2617997899
Short name T115
Test name
Test status
Simulation time 44469577 ps
CPU time 0.84 seconds
Started Mar 17 12:42:27 PM PDT 24
Finished Mar 17 12:42:29 PM PDT 24
Peak memory 215928 kb
Host smart-f81dfe76-9253-4262-9361-92a8f50e2f62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617997899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2617997899
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.2959559354
Short name T69
Test name
Test status
Simulation time 105290000 ps
CPU time 0.9 seconds
Started Mar 17 12:42:31 PM PDT 24
Finished Mar 17 12:42:32 PM PDT 24
Peak memory 216524 kb
Host smart-64c02c4d-fbd2-40d6-81a2-11731eca7d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959559354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2959559354
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4135154800
Short name T663
Test name
Test status
Simulation time 69206498 ps
CPU time 1.43 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:39 PM PDT 24
Peak memory 218076 kb
Host smart-22c98ac6-c7f9-4f09-9317-43d234337823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135154800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4135154800
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3603506078
Short name T735
Test name
Test status
Simulation time 28811380 ps
CPU time 0.91 seconds
Started Mar 17 12:42:31 PM PDT 24
Finished Mar 17 12:42:33 PM PDT 24
Peak memory 215628 kb
Host smart-1b4ca4b0-e0a8-4f61-b960-603f53f2f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603506078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3603506078
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3242751745
Short name T52
Test name
Test status
Simulation time 486971868 ps
CPU time 7.63 seconds
Started Mar 17 12:42:28 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 233248 kb
Host smart-bd80c615-8afc-4935-97b8-0d5cada3142e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242751745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3242751745
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.171244489
Short name T629
Test name
Test status
Simulation time 27814856 ps
CPU time 0.91 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 215240 kb
Host smart-359001e4-bcef-4bc9-9def-b190a5d5ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171244489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.171244489
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1187350951
Short name T358
Test name
Test status
Simulation time 136907460856 ps
CPU time 1630.6 seconds
Started Mar 17 12:42:27 PM PDT 24
Finished Mar 17 01:09:39 PM PDT 24
Peak memory 224620 kb
Host smart-c9dbade6-d160-453f-9280-0aa8fad53eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187350951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1187350951
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.899145753
Short name T578
Test name
Test status
Simulation time 48541843 ps
CPU time 1.23 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 215524 kb
Host smart-687f022f-afb8-4992-9557-ff851a861b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899145753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.899145753
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.391397132
Short name T797
Test name
Test status
Simulation time 15266113 ps
CPU time 0.79 seconds
Started Mar 17 12:42:28 PM PDT 24
Finished Mar 17 12:42:29 PM PDT 24
Peak memory 205692 kb
Host smart-9f8b1514-93dc-4799-ae05-5d10cf186b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391397132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.391397132
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.818385275
Short name T74
Test name
Test status
Simulation time 55348375 ps
CPU time 0.98 seconds
Started Mar 17 12:42:31 PM PDT 24
Finished Mar 17 12:42:32 PM PDT 24
Peak memory 220000 kb
Host smart-7bc74499-2c07-4e8c-b6b3-6a80765319a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818385275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.818385275
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2923986754
Short name T516
Test name
Test status
Simulation time 193840081 ps
CPU time 2.83 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 219452 kb
Host smart-8f2e5a98-b7df-4e7a-883e-81c75c790c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923986754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2923986754
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1043692887
Short name T53
Test name
Test status
Simulation time 1010591211 ps
CPU time 3.3 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 236508 kb
Host smart-04dd646f-2c68-4ae6-b956-54a108479e5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043692887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1043692887
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1698536801
Short name T467
Test name
Test status
Simulation time 52033556 ps
CPU time 0.88 seconds
Started Mar 17 12:42:30 PM PDT 24
Finished Mar 17 12:42:31 PM PDT 24
Peak memory 215348 kb
Host smart-0b2e432e-de7f-483c-adcd-bd21c21796b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698536801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1698536801
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2577949062
Short name T646
Test name
Test status
Simulation time 97135338868 ps
CPU time 1083.1 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 01:00:38 PM PDT 24
Peak memory 222128 kb
Host smart-9504d6d7-961b-489c-84e3-8dfac2547101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577949062 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2577949062
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2844988109
Short name T380
Test name
Test status
Simulation time 15075716 ps
CPU time 0.9 seconds
Started Mar 17 12:42:44 PM PDT 24
Finished Mar 17 12:42:45 PM PDT 24
Peak memory 206660 kb
Host smart-c9e1882e-6d02-43f7-bb35-76c07e24e524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844988109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2844988109
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.3103053267
Short name T90
Test name
Test status
Simulation time 26057586 ps
CPU time 1.37 seconds
Started Mar 17 12:42:45 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 229952 kb
Host smart-fe8c6e8c-3f97-4a42-b2d4-f6a25867171b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103053267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3103053267
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4260660569
Short name T466
Test name
Test status
Simulation time 62659032 ps
CPU time 1.22 seconds
Started Mar 17 12:42:48 PM PDT 24
Finished Mar 17 12:42:49 PM PDT 24
Peak memory 216640 kb
Host smart-aa9be4f0-b10f-431b-9453-13894c45e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260660569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4260660569
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.4202541623
Short name T220
Test name
Test status
Simulation time 16809277 ps
CPU time 0.96 seconds
Started Mar 17 12:42:46 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 215288 kb
Host smart-93517bc2-85c1-4322-aafd-6db56e74f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202541623 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.4202541623
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1399132073
Short name T501
Test name
Test status
Simulation time 80667817 ps
CPU time 1.44 seconds
Started Mar 17 12:42:48 PM PDT 24
Finished Mar 17 12:42:49 PM PDT 24
Peak memory 218696 kb
Host smart-65c772ee-e619-456b-9bf7-df7aad94e086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399132073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1399132073
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.725463485
Short name T638
Test name
Test status
Simulation time 93368603924 ps
CPU time 1016.28 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:59:43 PM PDT 24
Peak memory 220996 kb
Host smart-042a860c-0c40-4f46-b8a6-ca089ce06508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725463485 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.725463485
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.233997543
Short name T460
Test name
Test status
Simulation time 110167333 ps
CPU time 1.3 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 218364 kb
Host smart-bf80f055-81df-48d4-9606-45df7d807def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233997543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.233997543
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.500272879
Short name T482
Test name
Test status
Simulation time 31324070 ps
CPU time 1.45 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 217764 kb
Host smart-e3ba6ff2-7d71-4f1f-a4a0-0db5f2cb430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500272879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.500272879
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2144697496
Short name T598
Test name
Test status
Simulation time 239203817 ps
CPU time 1.06 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216764 kb
Host smart-b11f8643-5b8c-48f1-8893-ef7740554caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144697496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2144697496
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3139133010
Short name T185
Test name
Test status
Simulation time 163054891 ps
CPU time 3.63 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 219648 kb
Host smart-53ab57b1-757b-4488-8bf8-975e249c23bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139133010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3139133010
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1530323965
Short name T673
Test name
Test status
Simulation time 67982969 ps
CPU time 2.37 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217876 kb
Host smart-57de0541-be40-4d64-b7e8-e1ea47e34620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530323965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1530323965
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.748910369
Short name T340
Test name
Test status
Simulation time 266341812 ps
CPU time 2.96 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:59 PM PDT 24
Peak memory 219536 kb
Host smart-ac5a40db-6121-41fb-8845-6f3844eab025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748910369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.748910369
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1402938776
Short name T515
Test name
Test status
Simulation time 48111186 ps
CPU time 1.65 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 219684 kb
Host smart-0b1b36cb-e433-4eeb-9ff2-3650f7eda2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402938776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1402938776
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.4122997984
Short name T200
Test name
Test status
Simulation time 38585475 ps
CPU time 1.41 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 217952 kb
Host smart-9f5a0650-3b78-46c3-9cdc-c0f294ba05b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122997984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.4122997984
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3190938560
Short name T722
Test name
Test status
Simulation time 45487033 ps
CPU time 1.23 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217900 kb
Host smart-4ae771b3-29f0-45bc-992f-0a67bab33923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190938560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3190938560
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3815604709
Short name T297
Test name
Test status
Simulation time 23750550 ps
CPU time 1.13 seconds
Started Mar 17 12:42:46 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 215680 kb
Host smart-17da15af-792c-4a8f-899b-cf03541fe0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815604709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3815604709
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1450174147
Short name T620
Test name
Test status
Simulation time 55679178 ps
CPU time 0.97 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 206880 kb
Host smart-ef39007d-a48d-48a7-97ea-cf18f829fcad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450174147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1450174147
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.1372402876
Short name T7
Test name
Test status
Simulation time 120492001 ps
CPU time 1.18 seconds
Started Mar 17 12:42:44 PM PDT 24
Finished Mar 17 12:42:45 PM PDT 24
Peak memory 219288 kb
Host smart-d91999e2-f1b5-4f53-a2d5-8a4d8e9fbe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372402876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1372402876
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3233259756
Short name T498
Test name
Test status
Simulation time 38930460 ps
CPU time 1.06 seconds
Started Mar 17 12:42:45 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 218508 kb
Host smart-f2a46ac7-9b6c-43f2-bb33-15659cb4a7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233259756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3233259756
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1928556060
Short name T66
Test name
Test status
Simulation time 84645028 ps
CPU time 0.82 seconds
Started Mar 17 12:42:48 PM PDT 24
Finished Mar 17 12:42:49 PM PDT 24
Peak memory 215424 kb
Host smart-97c83f48-6f5e-4ccc-91b8-0e0106126dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928556060 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1928556060
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1025150430
Short name T529
Test name
Test status
Simulation time 16605605 ps
CPU time 0.95 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 215228 kb
Host smart-a1b9ebc3-e110-469e-adb5-5ee483545cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025150430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1025150430
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2661453859
Short name T451
Test name
Test status
Simulation time 906601427 ps
CPU time 4.29 seconds
Started Mar 17 12:42:44 PM PDT 24
Finished Mar 17 12:42:49 PM PDT 24
Peak memory 216572 kb
Host smart-18ed0fd9-bcdb-47f1-83dc-12a803651612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661453859 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2661453859
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.7658620
Short name T410
Test name
Test status
Simulation time 89565968 ps
CPU time 1.5 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 218172 kb
Host smart-67bc9984-a080-4558-b6de-7600a9149c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7658620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.7658620
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.326779611
Short name T409
Test name
Test status
Simulation time 55224618 ps
CPU time 1.21 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 216760 kb
Host smart-458d6030-c6e9-4456-8551-285c9c829a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326779611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.326779611
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.341622749
Short name T677
Test name
Test status
Simulation time 42608724 ps
CPU time 1.53 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217656 kb
Host smart-4ff98f3f-cd13-4d8a-9d7c-7eabec01da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341622749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.341622749
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1762865417
Short name T330
Test name
Test status
Simulation time 24174182 ps
CPU time 1.14 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 216996 kb
Host smart-5cb9fbbd-eb4e-4685-b6b8-de9cf322b53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762865417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1762865417
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.876595143
Short name T765
Test name
Test status
Simulation time 29740379 ps
CPU time 1.22 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216688 kb
Host smart-16efd0fa-fae3-4763-8b19-da035acb869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876595143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.876595143
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1528736292
Short name T388
Test name
Test status
Simulation time 76158092 ps
CPU time 1.25 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 219468 kb
Host smart-d0912554-77fc-4d04-b429-602cdf0dfea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528736292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1528736292
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1292569243
Short name T561
Test name
Test status
Simulation time 71237299 ps
CPU time 1.13 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216816 kb
Host smart-0bee624e-a6be-4651-87d6-7c43798ff7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292569243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1292569243
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.329388475
Short name T305
Test name
Test status
Simulation time 51604048 ps
CPU time 1.07 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 215288 kb
Host smart-138f889e-1454-4c3d-a895-dc991eebe7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329388475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.329388475
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2891735012
Short name T660
Test name
Test status
Simulation time 35548906 ps
CPU time 0.81 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 205688 kb
Host smart-080947cd-d8ab-408a-86a2-29b74b2c0543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891735012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2891735012
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.3271713716
Short name T398
Test name
Test status
Simulation time 23091071 ps
CPU time 0.89 seconds
Started Mar 17 12:42:51 PM PDT 24
Finished Mar 17 12:42:52 PM PDT 24
Peak memory 217468 kb
Host smart-3210c426-e678-4460-9dd6-269575c80dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271713716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3271713716
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.4201199987
Short name T570
Test name
Test status
Simulation time 467631379 ps
CPU time 3.97 seconds
Started Mar 17 12:42:48 PM PDT 24
Finished Mar 17 12:42:52 PM PDT 24
Peak memory 216856 kb
Host smart-f43e6063-a617-4376-a218-4dbad8ea98e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201199987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4201199987
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1360131845
Short name T147
Test name
Test status
Simulation time 29154962 ps
CPU time 0.9 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 215524 kb
Host smart-5775c138-a5ee-4b93-afe7-02ba3a8699e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360131845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1360131845
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2068316230
Short name T416
Test name
Test status
Simulation time 49723286 ps
CPU time 0.89 seconds
Started Mar 17 12:42:46 PM PDT 24
Finished Mar 17 12:42:47 PM PDT 24
Peak memory 215260 kb
Host smart-991441eb-8594-4585-ab6a-a0d11b0152df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068316230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2068316230
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3717916968
Short name T522
Test name
Test status
Simulation time 135747126 ps
CPU time 1.34 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:49 PM PDT 24
Peak memory 216844 kb
Host smart-9df37b21-d3b0-4c81-894e-35365ee3dbd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717916968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3717916968
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3647014170
Short name T197
Test name
Test status
Simulation time 72382024240 ps
CPU time 415.13 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:49:42 PM PDT 24
Peak memory 217452 kb
Host smart-2108c618-8e77-40ac-979c-f39baa023446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647014170 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3647014170
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.edn_genbits.1901741817
Short name T723
Test name
Test status
Simulation time 114600463 ps
CPU time 1.22 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217752 kb
Host smart-4954733c-f82a-419f-8987-e05a1aca3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901741817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1901741817
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1350955042
Short name T750
Test name
Test status
Simulation time 87457163 ps
CPU time 1.42 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 218268 kb
Host smart-af49534f-df19-4928-b5d3-fb61bf372935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350955042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1350955042
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.345269230
Short name T497
Test name
Test status
Simulation time 65488292 ps
CPU time 1.29 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217712 kb
Host smart-2e0ee8a9-943a-4cc4-8e0e-764055dedc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345269230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.345269230
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.4138500652
Short name T454
Test name
Test status
Simulation time 160315419 ps
CPU time 0.91 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 216568 kb
Host smart-0019e12d-1bee-4831-8208-a8f7f12d3a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138500652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4138500652
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3278159863
Short name T626
Test name
Test status
Simulation time 90066409 ps
CPU time 1.7 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 217872 kb
Host smart-a133516a-f19c-4204-a2f9-d06325b63dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278159863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3278159863
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2900041028
Short name T411
Test name
Test status
Simulation time 74117522 ps
CPU time 1.17 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 216648 kb
Host smart-0878b3d1-ab85-4b68-9599-dd7eafed8fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900041028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2900041028
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2943160654
Short name T487
Test name
Test status
Simulation time 30063185 ps
CPU time 1.22 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217892 kb
Host smart-1c795400-e091-49d0-a146-078a3bdaabfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943160654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2943160654
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3569791647
Short name T597
Test name
Test status
Simulation time 40047426 ps
CPU time 1.68 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218148 kb
Host smart-297c5af1-a983-4d7a-a8d5-b2edcb8da315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569791647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3569791647
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.283849924
Short name T71
Test name
Test status
Simulation time 139261372 ps
CPU time 1.3 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 215652 kb
Host smart-31b71914-52b1-4863-845d-c934660b4ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283849924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.283849924
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1929502295
Short name T458
Test name
Test status
Simulation time 19395982 ps
CPU time 1.02 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 206112 kb
Host smart-baf4a783-fe24-4435-acfc-116c72f11915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929502295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1929502295
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3056210639
Short name T129
Test name
Test status
Simulation time 30452455 ps
CPU time 0.88 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 215840 kb
Host smart-579ac181-685a-4449-bfc8-737cf40d350a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056210639 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3056210639
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2638452278
Short name T442
Test name
Test status
Simulation time 77247199 ps
CPU time 1.1 seconds
Started Mar 17 12:42:56 PM PDT 24
Finished Mar 17 12:42:58 PM PDT 24
Peak memory 216300 kb
Host smart-13ead5f6-1501-4c91-b8a1-6f8fa115d014
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638452278 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2638452278
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2009047629
Short name T73
Test name
Test status
Simulation time 74366079 ps
CPU time 1.1 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 229588 kb
Host smart-1872d110-03f9-4455-83ec-8b4cf6ed6212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009047629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2009047629
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3078487620
Short name T462
Test name
Test status
Simulation time 36155301 ps
CPU time 1.07 seconds
Started Mar 17 12:42:55 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 216496 kb
Host smart-3706d71f-c105-433a-b3ac-fd874e55fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078487620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3078487620
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.973696373
Short name T590
Test name
Test status
Simulation time 22196432 ps
CPU time 1.23 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 223988 kb
Host smart-69c4e57f-701d-4fd1-8e46-7fa8bd65aeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973696373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.973696373
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2909847600
Short name T175
Test name
Test status
Simulation time 51752380 ps
CPU time 0.97 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 215364 kb
Host smart-fbcec7aa-0132-42fd-83ac-649dbfe35194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909847600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2909847600
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2159496596
Short name T602
Test name
Test status
Simulation time 82678873 ps
CPU time 1.11 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 216652 kb
Host smart-6e2147ea-015a-4670-bb51-7bc219f8ade6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159496596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2159496596
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_genbits.2989187405
Short name T360
Test name
Test status
Simulation time 40804471 ps
CPU time 1.14 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 216680 kb
Host smart-dd8934fd-78c7-456c-8085-42ac90d4accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989187405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2989187405
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.240206040
Short name T452
Test name
Test status
Simulation time 52348103 ps
CPU time 1.11 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 216600 kb
Host smart-4a4614ae-1238-490c-8d3f-0c12099c69b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240206040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.240206040
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2236455924
Short name T672
Test name
Test status
Simulation time 116173508 ps
CPU time 1.08 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:43:59 PM PDT 24
Peak memory 216484 kb
Host smart-b365bc14-9697-4b65-abda-bf28d187efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236455924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2236455924
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2719056132
Short name T265
Test name
Test status
Simulation time 107099742 ps
CPU time 2.64 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 216960 kb
Host smart-7c63295b-195f-4a18-ad2f-104756441993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719056132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2719056132
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.806117469
Short name T595
Test name
Test status
Simulation time 56402423 ps
CPU time 1.29 seconds
Started Mar 17 12:44:25 PM PDT 24
Finished Mar 17 12:44:27 PM PDT 24
Peak memory 217992 kb
Host smart-c35ba71a-18ef-48b3-ac66-2ca241174c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806117469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.806117469
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.804425227
Short name T34
Test name
Test status
Simulation time 94957756 ps
CPU time 1.28 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:59 PM PDT 24
Peak memory 216640 kb
Host smart-4e54da31-be6e-491a-b937-160df3877b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804425227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.804425227
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1731647241
Short name T418
Test name
Test status
Simulation time 41908318 ps
CPU time 1.32 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217612 kb
Host smart-b15488b7-8c9a-4424-a5fa-c7c0aeec8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731647241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1731647241
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2438408029
Short name T51
Test name
Test status
Simulation time 45838290 ps
CPU time 1.67 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 217932 kb
Host smart-cb8a3912-9989-4048-969f-29bd9b17fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438408029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2438408029
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3497607757
Short name T364
Test name
Test status
Simulation time 102490279 ps
CPU time 1.47 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218416 kb
Host smart-bf06a836-81d2-4c0b-b871-33e178a5e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497607757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3497607757
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.141035570
Short name T130
Test name
Test status
Simulation time 23997839 ps
CPU time 1.1 seconds
Started Mar 17 12:42:58 PM PDT 24
Finished Mar 17 12:43:00 PM PDT 24
Peak memory 215688 kb
Host smart-e2523a64-6e21-4f1d-b946-4f2196bca9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141035570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.141035570
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2609903035
Short name T734
Test name
Test status
Simulation time 22673279 ps
CPU time 0.89 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 206056 kb
Host smart-e8e3dc1d-d7bd-4186-be80-091b551f5557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609903035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2609903035
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1140034178
Short name T219
Test name
Test status
Simulation time 17793437 ps
CPU time 0.91 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 215888 kb
Host smart-c89112b0-c85d-42ac-9536-962595dc2c04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140034178 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1140034178
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.829184708
Short name T77
Test name
Test status
Simulation time 77011643 ps
CPU time 1.07 seconds
Started Mar 17 12:42:56 PM PDT 24
Finished Mar 17 12:42:57 PM PDT 24
Peak memory 216424 kb
Host smart-400168fd-3ba0-476e-9fa5-078dc0290447
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829184708 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.829184708
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2724340781
Short name T481
Test name
Test status
Simulation time 156856876 ps
CPU time 0.95 seconds
Started Mar 17 12:42:58 PM PDT 24
Finished Mar 17 12:42:59 PM PDT 24
Peak memory 220244 kb
Host smart-d1d55c26-897f-4867-8f5a-3c5c1d44058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724340781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2724340781
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.63045953
Short name T552
Test name
Test status
Simulation time 67794327 ps
CPU time 2.57 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 219448 kb
Host smart-6819fa95-c859-401e-918e-ddf99d38f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63045953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.63045953
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.673177616
Short name T378
Test name
Test status
Simulation time 49325310 ps
CPU time 0.93 seconds
Started Mar 17 12:42:55 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 215276 kb
Host smart-38d4aa42-8b0c-4626-9b45-95ada2bd2b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673177616 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.673177616
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2051977643
Short name T568
Test name
Test status
Simulation time 1108130847 ps
CPU time 4.7 seconds
Started Mar 17 12:42:51 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 216808 kb
Host smart-c590aeaa-1c16-4c6a-bc0d-89515ef858bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051977643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2051977643
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3031073985
Short name T759
Test name
Test status
Simulation time 20519547015 ps
CPU time 388.49 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:49:22 PM PDT 24
Peak memory 223796 kb
Host smart-214b6c8e-e091-4e1b-931d-229a0b040303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031073985 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3031073985
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2211484714
Short name T3
Test name
Test status
Simulation time 39157595 ps
CPU time 1.46 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217980 kb
Host smart-65cc37c6-8ef0-4491-9eb1-ea77ed932e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211484714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2211484714
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1537846848
Short name T250
Test name
Test status
Simulation time 65473844 ps
CPU time 1.03 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216672 kb
Host smart-8b8f8810-4e3d-41b6-8529-9a0cbdeef71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537846848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1537846848
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2835245596
Short name T612
Test name
Test status
Simulation time 39488747 ps
CPU time 1.02 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 216744 kb
Host smart-6a04fdfb-3516-494a-b81f-2375eefc43c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835245596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2835245596
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2653870918
Short name T530
Test name
Test status
Simulation time 95902618 ps
CPU time 1.21 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 216672 kb
Host smart-053111ee-9f1d-4599-b410-42651a59dfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653870918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2653870918
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2792062733
Short name T491
Test name
Test status
Simulation time 129771816 ps
CPU time 1.15 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 218404 kb
Host smart-85d17b1c-ef83-41c9-94b9-1386dceee6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792062733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2792062733
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3836432751
Short name T494
Test name
Test status
Simulation time 59196193 ps
CPU time 1.21 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:14 PM PDT 24
Peak memory 216652 kb
Host smart-0afd12fb-fe5e-416b-948e-a695f95f29e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836432751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3836432751
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3672742364
Short name T203
Test name
Test status
Simulation time 35834453 ps
CPU time 1.25 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 215316 kb
Host smart-d016dcce-4170-4c15-854b-06db3076b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672742364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3672742364
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1063378065
Short name T315
Test name
Test status
Simulation time 52642521 ps
CPU time 1.2 seconds
Started Mar 17 12:44:25 PM PDT 24
Finished Mar 17 12:44:26 PM PDT 24
Peak memory 216632 kb
Host smart-b74255c4-b20e-4565-9c05-ae79557540c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063378065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1063378065
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2515207481
Short name T353
Test name
Test status
Simulation time 86633539 ps
CPU time 1.42 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 219256 kb
Host smart-2d5f23b7-e339-464d-a418-9e5146dd9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515207481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2515207481
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.913184637
Short name T678
Test name
Test status
Simulation time 25786922 ps
CPU time 1.24 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 215736 kb
Host smart-bbdacc05-c750-4118-b4e9-80d85a280755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913184637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.913184637
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3596315591
Short name T351
Test name
Test status
Simulation time 135395577 ps
CPU time 0.9 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 206516 kb
Host smart-a7c26864-6c7b-4060-880e-03f535fff163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596315591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3596315591
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4216656118
Short name T775
Test name
Test status
Simulation time 29513531 ps
CPU time 0.89 seconds
Started Mar 17 12:42:52 PM PDT 24
Finished Mar 17 12:42:53 PM PDT 24
Peak memory 215864 kb
Host smart-0ada1f07-e693-4937-85e3-d3c3d404c8c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216656118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4216656118
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2812383571
Short name T169
Test name
Test status
Simulation time 56984167 ps
CPU time 1.38 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 217176 kb
Host smart-85af806c-bf99-45c7-a508-9ece4876b5e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812383571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2812383571
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.97533866
Short name T820
Test name
Test status
Simulation time 145293088 ps
CPU time 0.93 seconds
Started Mar 17 12:42:55 PM PDT 24
Finished Mar 17 12:42:57 PM PDT 24
Peak memory 216864 kb
Host smart-79254056-f79c-47b9-a026-28f48fe84414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97533866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.97533866
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.730821774
Short name T798
Test name
Test status
Simulation time 47892036 ps
CPU time 1.5 seconds
Started Mar 17 12:42:52 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 219304 kb
Host smart-f41fb040-2e14-4b77-af65-279c389bda22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730821774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.730821774
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.4116217396
Short name T434
Test name
Test status
Simulation time 30473064 ps
CPU time 0.85 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 215496 kb
Host smart-a33a1516-8bd8-4330-abbc-a5e53670b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116217396 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.4116217396
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3302467089
Short name T585
Test name
Test status
Simulation time 33872614 ps
CPU time 0.88 seconds
Started Mar 17 12:42:55 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 215308 kb
Host smart-c172f1a5-bf0e-4079-ad03-65da5692cb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302467089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3302467089
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1115797783
Short name T210
Test name
Test status
Simulation time 141118876 ps
CPU time 2.55 seconds
Started Mar 17 12:42:51 PM PDT 24
Finished Mar 17 12:42:54 PM PDT 24
Peak memory 215292 kb
Host smart-4e80c8c8-31f2-431f-8d8a-425f97b1f743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115797783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1115797783
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1397422515
Short name T4
Test name
Test status
Simulation time 318587462444 ps
CPU time 1314.99 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 01:04:50 PM PDT 24
Peak memory 224700 kb
Host smart-b3e3d394-8d70-4dd1-b1dd-65d4dad6615a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397422515 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1397422515
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.712053858
Short name T542
Test name
Test status
Simulation time 77872604 ps
CPU time 1.07 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 215384 kb
Host smart-34e02fc3-748d-430a-b3bc-d144d74802ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712053858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.712053858
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3399779379
Short name T366
Test name
Test status
Simulation time 56273017 ps
CPU time 1.43 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 218084 kb
Host smart-35bc7dff-bcc4-4f89-9885-2e32ca85393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399779379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3399779379
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.187323314
Short name T789
Test name
Test status
Simulation time 44692532 ps
CPU time 1.29 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217660 kb
Host smart-fd16747d-e479-454a-9fa7-273a9717e6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187323314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.187323314
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2227253820
Short name T571
Test name
Test status
Simulation time 33412465 ps
CPU time 1.22 seconds
Started Mar 17 12:44:33 PM PDT 24
Finished Mar 17 12:44:35 PM PDT 24
Peak memory 216548 kb
Host smart-a14c5019-25d6-4d72-a996-3641b07f2767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227253820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2227253820
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3811465635
Short name T520
Test name
Test status
Simulation time 75887629 ps
CPU time 1.59 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217980 kb
Host smart-af9c3ad6-bfe4-4696-a9b8-9278dd8bc668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811465635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3811465635
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2260791896
Short name T465
Test name
Test status
Simulation time 124012927 ps
CPU time 1.2 seconds
Started Mar 17 12:44:13 PM PDT 24
Finished Mar 17 12:44:15 PM PDT 24
Peak memory 219120 kb
Host smart-e5373706-8149-484c-8eba-823563b4d141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260791896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2260791896
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.952415333
Short name T503
Test name
Test status
Simulation time 41763466 ps
CPU time 1.11 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 219236 kb
Host smart-230b08ba-de3e-4e93-af34-1805e8f8284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952415333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.952415333
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.146926812
Short name T689
Test name
Test status
Simulation time 45540703 ps
CPU time 1.15 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:14 PM PDT 24
Peak memory 216736 kb
Host smart-b64ffab3-9d58-4c45-be3d-61ce763c4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146926812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.146926812
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1135732881
Short name T333
Test name
Test status
Simulation time 70266896 ps
CPU time 1.51 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:10 PM PDT 24
Peak memory 217996 kb
Host smart-9d0a712c-21a1-4c4e-8a1a-f5224dcfe72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135732881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1135732881
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1832115771
Short name T550
Test name
Test status
Simulation time 34311422 ps
CPU time 1.3 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217796 kb
Host smart-210daf70-d53c-480e-8dbd-f8406432553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832115771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1832115771
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3792024686
Short name T303
Test name
Test status
Simulation time 40413332 ps
CPU time 1.14 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 215632 kb
Host smart-08cc5c6c-59b7-4cb4-83df-dc1284e86112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792024686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3792024686
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3009273103
Short name T614
Test name
Test status
Simulation time 55021832 ps
CPU time 0.8 seconds
Started Mar 17 12:42:59 PM PDT 24
Finished Mar 17 12:43:01 PM PDT 24
Peak memory 205824 kb
Host smart-83e339ff-1437-4763-96be-e5f7b0942c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009273103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3009273103
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3656338683
Short name T171
Test name
Test status
Simulation time 27309594 ps
CPU time 0.84 seconds
Started Mar 17 12:42:52 PM PDT 24
Finished Mar 17 12:42:53 PM PDT 24
Peak memory 215848 kb
Host smart-40ede240-5915-47c1-9c6a-5fcf243291e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656338683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3656338683
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.87629456
Short name T321
Test name
Test status
Simulation time 35243143 ps
CPU time 1.21 seconds
Started Mar 17 12:42:57 PM PDT 24
Finished Mar 17 12:42:59 PM PDT 24
Peak memory 217720 kb
Host smart-fb8b56c8-1074-42f6-8222-e4d4efdbbebd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87629456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_dis
able_auto_req_mode.87629456
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3453674478
Short name T107
Test name
Test status
Simulation time 35429127 ps
CPU time 0.8 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:55 PM PDT 24
Peak memory 217848 kb
Host smart-080c8a9d-52b8-420c-a359-8a02175ed4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453674478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3453674478
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.847733851
Short name T654
Test name
Test status
Simulation time 89873876 ps
CPU time 2.24 seconds
Started Mar 17 12:42:54 PM PDT 24
Finished Mar 17 12:42:56 PM PDT 24
Peak memory 217972 kb
Host smart-369e3ea4-12ef-4e37-906b-47b3d4d8e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847733851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.847733851
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3656626200
Short name T144
Test name
Test status
Simulation time 20419078 ps
CPU time 1.07 seconds
Started Mar 17 12:42:50 PM PDT 24
Finished Mar 17 12:42:51 PM PDT 24
Peak memory 215816 kb
Host smart-6f74949d-ebfb-498a-80ea-9b4ff88d089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656626200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3656626200
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3370576472
Short name T519
Test name
Test status
Simulation time 20665700 ps
CPU time 0.95 seconds
Started Mar 17 12:42:58 PM PDT 24
Finished Mar 17 12:43:00 PM PDT 24
Peak memory 215300 kb
Host smart-f34e85d7-c18a-43e1-8421-1a7f802e568f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370576472 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3370576472
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2323037534
Short name T206
Test name
Test status
Simulation time 399632241 ps
CPU time 7.33 seconds
Started Mar 17 12:42:52 PM PDT 24
Finished Mar 17 12:43:00 PM PDT 24
Peak memory 216476 kb
Host smart-95425de3-35e1-48a6-8e43-60e7862666ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323037534 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2323037534
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.4143106485
Short name T644
Test name
Test status
Simulation time 49896746677 ps
CPU time 633.68 seconds
Started Mar 17 12:42:53 PM PDT 24
Finished Mar 17 12:53:27 PM PDT 24
Peak memory 218772 kb
Host smart-81478ab2-671c-4790-8684-3845dc13828b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143106485 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.4143106485
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.627474258
Short name T307
Test name
Test status
Simulation time 26276078 ps
CPU time 1.24 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 217960 kb
Host smart-6b684de8-5596-4ff4-bb8f-fe710f384f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627474258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.627474258
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2861061387
Short name T28
Test name
Test status
Simulation time 68552323 ps
CPU time 1.05 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216828 kb
Host smart-8b71e6b5-d77c-452a-97d6-bc84ede22f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861061387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2861061387
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.306660476
Short name T600
Test name
Test status
Simulation time 38591583 ps
CPU time 1.43 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 216652 kb
Host smart-07006bc4-a362-47a3-b882-01544d12e3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306660476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.306660476
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2757756031
Short name T818
Test name
Test status
Simulation time 27900299 ps
CPU time 1.28 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 216716 kb
Host smart-9cdbb609-696f-4a93-b452-96e4b38834db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757756031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2757756031
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.935770990
Short name T577
Test name
Test status
Simulation time 48097203 ps
CPU time 1.27 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218152 kb
Host smart-c78bf63a-4baa-459b-b6e4-a164b14ebba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935770990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.935770990
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2950689349
Short name T563
Test name
Test status
Simulation time 36267355 ps
CPU time 1.27 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 218024 kb
Host smart-59a77f8f-15b4-4b5d-8218-6560d1f8c9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950689349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2950689349
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2173284116
Short name T328
Test name
Test status
Simulation time 58752880 ps
CPU time 1.22 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 216696 kb
Host smart-7395c23e-f942-4444-8dd9-1e58479cb9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173284116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2173284116
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1745439289
Short name T463
Test name
Test status
Simulation time 153179660 ps
CPU time 1.33 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 216860 kb
Host smart-eef91f00-2784-4d35-ab6e-0e3dbb7eb326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745439289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1745439289
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.75783349
Short name T420
Test name
Test status
Simulation time 61697818 ps
CPU time 1.28 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217908 kb
Host smart-ecf9e84c-bbfe-45c3-94ab-a0c1dec075d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75783349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.75783349
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3811066368
Short name T628
Test name
Test status
Simulation time 36496339 ps
CPU time 1.01 seconds
Started Mar 17 12:42:59 PM PDT 24
Finished Mar 17 12:43:02 PM PDT 24
Peak memory 206092 kb
Host smart-2410ccc5-84d8-4690-b0f4-6f61225ede34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811066368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3811066368
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.680724733
Short name T161
Test name
Test status
Simulation time 40975416 ps
CPU time 0.89 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215840 kb
Host smart-66ee6058-e83e-4ae3-a2dc-18585108924b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680724733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.680724733
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4221626699
Short name T323
Test name
Test status
Simulation time 135830928 ps
CPU time 1.09 seconds
Started Mar 17 12:43:03 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 216332 kb
Host smart-24a2a795-7478-474b-a4d8-54d0a3358ccc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221626699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4221626699
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1963640317
Short name T81
Test name
Test status
Simulation time 89443843 ps
CPU time 1.01 seconds
Started Mar 17 12:43:00 PM PDT 24
Finished Mar 17 12:43:02 PM PDT 24
Peak memory 219220 kb
Host smart-73bd1414-12ea-4fdb-bd6e-e493f32f70b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963640317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1963640317
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.229962248
Short name T658
Test name
Test status
Simulation time 94108437 ps
CPU time 1.19 seconds
Started Mar 17 12:43:00 PM PDT 24
Finished Mar 17 12:43:02 PM PDT 24
Peak memory 217816 kb
Host smart-e7e43b44-bb35-4a40-a1d3-980f668e42b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229962248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.229962248
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4129916821
Short name T773
Test name
Test status
Simulation time 33805810 ps
CPU time 1.01 seconds
Started Mar 17 12:43:01 PM PDT 24
Finished Mar 17 12:43:03 PM PDT 24
Peak memory 223856 kb
Host smart-1f562ba5-4044-4901-a8e2-e6a00f17a1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129916821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4129916821
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.236337123
Short name T593
Test name
Test status
Simulation time 36376487 ps
CPU time 0.93 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215252 kb
Host smart-244404c7-6231-4faa-8a1f-71fcbd3f1a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236337123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.236337123
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.400680341
Short name T397
Test name
Test status
Simulation time 272804033 ps
CPU time 5.42 seconds
Started Mar 17 12:43:01 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215256 kb
Host smart-9ddc13f7-4dc0-4088-a431-37e34e3aed52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400680341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.400680341
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4239651454
Short name T648
Test name
Test status
Simulation time 44627066052 ps
CPU time 491.3 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:51:15 PM PDT 24
Peak memory 217636 kb
Host smart-a6f481ea-8a9f-447f-87da-4aa5af008672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239651454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4239651454
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2258406928
Short name T785
Test name
Test status
Simulation time 32876032 ps
CPU time 1.34 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218096 kb
Host smart-ac8c132b-63b3-4647-a4ba-77cc91ed1895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258406928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2258406928
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1856514773
Short name T29
Test name
Test status
Simulation time 50180725 ps
CPU time 1.17 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217860 kb
Host smart-3fd73507-a26d-42fe-b63c-efe3ca5326f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856514773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1856514773
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2548222667
Short name T502
Test name
Test status
Simulation time 103916098 ps
CPU time 1.05 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 216724 kb
Host smart-fa51131e-3dd2-4d99-93be-0e6d26706d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548222667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2548222667
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.4072812387
Short name T447
Test name
Test status
Simulation time 94803121 ps
CPU time 1.18 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:58 PM PDT 24
Peak memory 217984 kb
Host smart-f93b613b-517c-4d91-814d-4de14b2d644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072812387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4072812387
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3585573394
Short name T433
Test name
Test status
Simulation time 36250261 ps
CPU time 1.65 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217928 kb
Host smart-035ffef8-dbf5-49eb-b19b-3813a0928ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585573394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3585573394
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1774030920
Short name T426
Test name
Test status
Simulation time 34875382 ps
CPU time 1.34 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 219200 kb
Host smart-89d60a84-3229-4352-b2e3-6e141a0be06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774030920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1774030920
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1846668617
Short name T710
Test name
Test status
Simulation time 74358137 ps
CPU time 1.3 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 216804 kb
Host smart-d23c1c16-8acf-4bee-a2f1-3125a992fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846668617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1846668617
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3663128326
Short name T766
Test name
Test status
Simulation time 22466760 ps
CPU time 1.2 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 216972 kb
Host smart-73a45fb1-44b6-47e1-ae99-f79a1480ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663128326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3663128326
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.612551226
Short name T470
Test name
Test status
Simulation time 61924458 ps
CPU time 1.26 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216604 kb
Host smart-ea2d9708-e137-4cab-b02e-e1011dcff9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612551226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.612551226
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1169048130
Short name T687
Test name
Test status
Simulation time 34979387 ps
CPU time 1.26 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 215744 kb
Host smart-78479fea-57e2-4a93-b762-dea486eaad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169048130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1169048130
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.335191680
Short name T387
Test name
Test status
Simulation time 45272350 ps
CPU time 1.09 seconds
Started Mar 17 12:42:59 PM PDT 24
Finished Mar 17 12:43:00 PM PDT 24
Peak memory 218812 kb
Host smart-ab05cb51-4e1a-4062-b53e-6e23ef8373fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335191680 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.335191680
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3230095531
Short name T215
Test name
Test status
Simulation time 24517934 ps
CPU time 1.22 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 220340 kb
Host smart-ae04871b-e28c-4f9d-bfef-fead39d48835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230095531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3230095531
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1247182683
Short name T774
Test name
Test status
Simulation time 99586049 ps
CPU time 1.27 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 218452 kb
Host smart-fc69a512-1dd6-414e-b517-3d059406067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247182683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1247182683
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.865150150
Short name T783
Test name
Test status
Simulation time 80047943 ps
CPU time 0.84 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:04 PM PDT 24
Peak memory 215420 kb
Host smart-5e2da8f8-b467-46ab-afef-27818a7d86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865150150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.865150150
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.154136305
Short name T696
Test name
Test status
Simulation time 16108195 ps
CPU time 0.9 seconds
Started Mar 17 12:42:58 PM PDT 24
Finished Mar 17 12:43:00 PM PDT 24
Peak memory 215292 kb
Host smart-b21014e0-52b9-4ed6-881e-8ad2a142b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154136305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.154136305
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.223561490
Short name T694
Test name
Test status
Simulation time 44378943 ps
CPU time 1.04 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215264 kb
Host smart-678b155c-bbe7-46c3-ad1d-d752e86fc60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223561490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.223561490
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1854317586
Short name T55
Test name
Test status
Simulation time 20980684165 ps
CPU time 373.23 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:49:18 PM PDT 24
Peak memory 218680 kb
Host smart-9c18101e-4503-40fe-afa5-d1aeb6532c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854317586 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1854317586
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.edn_genbits.2334327707
Short name T828
Test name
Test status
Simulation time 48336793 ps
CPU time 1.24 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217892 kb
Host smart-59d700c8-bc99-4abc-ba0f-2a99f2f85ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334327707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2334327707
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.877497011
Short name T275
Test name
Test status
Simulation time 283599911 ps
CPU time 3.52 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 218092 kb
Host smart-6a9ed481-70ce-46e8-9dd2-8e7c55daef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877497011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.877497011
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3962663558
Short name T607
Test name
Test status
Simulation time 43696556 ps
CPU time 1.32 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217772 kb
Host smart-38acae0c-b784-4cee-b974-41949ab62d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962663558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3962663558
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1887839735
Short name T273
Test name
Test status
Simulation time 74800431 ps
CPU time 1.21 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218148 kb
Host smart-eab3b52f-9106-468e-bf9f-05244dc3a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887839735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1887839735
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2413821788
Short name T477
Test name
Test status
Simulation time 46387244 ps
CPU time 1.08 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 218320 kb
Host smart-c5ee1a70-af70-4da6-ae19-af15c79f0a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413821788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2413821788
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2045302366
Short name T36
Test name
Test status
Simulation time 74923502 ps
CPU time 1.3 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 218308 kb
Host smart-fcaf9715-0f0b-43f8-aca5-cb2dd374ae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045302366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2045302366
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2268597383
Short name T422
Test name
Test status
Simulation time 132525773 ps
CPU time 2.81 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 218896 kb
Host smart-6e0c34f2-eef3-4ae1-9d06-95a93f501aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268597383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2268597383
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2597695544
Short name T685
Test name
Test status
Simulation time 170286164 ps
CPU time 1.35 seconds
Started Mar 17 12:44:14 PM PDT 24
Finished Mar 17 12:44:16 PM PDT 24
Peak memory 218184 kb
Host smart-04155b80-9406-4d99-84a0-6c2d9b2f1828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597695544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2597695544
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2323365652
Short name T217
Test name
Test status
Simulation time 53730879 ps
CPU time 1.27 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:03 PM PDT 24
Peak memory 215644 kb
Host smart-ddb6d859-aba1-4959-ae04-0bc495b0d6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323365652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2323365652
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4225685320
Short name T643
Test name
Test status
Simulation time 65807985 ps
CPU time 0.95 seconds
Started Mar 17 12:43:01 PM PDT 24
Finished Mar 17 12:43:03 PM PDT 24
Peak memory 206532 kb
Host smart-fbb2ad19-a555-4950-bde5-e186a14232e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225685320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4225685320
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1770017889
Short name T121
Test name
Test status
Simulation time 38076892 ps
CPU time 0.84 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:03 PM PDT 24
Peak memory 215908 kb
Host smart-22f336af-7c37-48fa-bb1b-739a2b48a8a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770017889 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1770017889
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3421100609
Short name T62
Test name
Test status
Simulation time 25152091 ps
CPU time 1.09 seconds
Started Mar 17 12:43:03 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 216476 kb
Host smart-38dc7be9-b36f-4179-8585-7e855e33b9d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421100609 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3421100609
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1213032372
Short name T753
Test name
Test status
Simulation time 23553694 ps
CPU time 1.17 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 215340 kb
Host smart-76bf7411-405d-437f-94d7-e274805b8724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213032372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1213032372
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1304319690
Short name T13
Test name
Test status
Simulation time 55181601 ps
CPU time 1.22 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 218504 kb
Host smart-deab4a06-26b6-4259-90f6-4c02044e028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304319690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1304319690
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1807354313
Short name T332
Test name
Test status
Simulation time 25548824 ps
CPU time 1.02 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 223944 kb
Host smart-3bd62a90-2693-4299-b4a6-4fffaeff06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807354313 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1807354313
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2940243214
Short name T381
Test name
Test status
Simulation time 46795949 ps
CPU time 0.91 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 215240 kb
Host smart-de367fb8-0405-4724-8541-2cec159255d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940243214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2940243214
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.860341237
Short name T449
Test name
Test status
Simulation time 88457568 ps
CPU time 2.17 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:05 PM PDT 24
Peak memory 215324 kb
Host smart-aaa3f16c-b340-4e2e-813b-54ca27bf9ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860341237 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.860341237
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1821189159
Short name T716
Test name
Test status
Simulation time 25331657235 ps
CPU time 563.71 seconds
Started Mar 17 12:43:01 PM PDT 24
Finished Mar 17 12:52:26 PM PDT 24
Peak memory 223752 kb
Host smart-a2190f57-9a76-414f-9844-a631b21ceb7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821189159 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1821189159
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2214264405
Short name T642
Test name
Test status
Simulation time 267370882 ps
CPU time 3.36 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 218016 kb
Host smart-19980a32-25ae-4580-bac4-a27e3e6158f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214264405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2214264405
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.162000818
Short name T684
Test name
Test status
Simulation time 165353038 ps
CPU time 1.19 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 216628 kb
Host smart-031d8648-9906-4528-a52b-7bd40528db21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162000818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.162000818
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4202259644
Short name T33
Test name
Test status
Simulation time 62510390 ps
CPU time 2.09 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 218136 kb
Host smart-346124c9-ca89-42e3-953c-3585782cd13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202259644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4202259644
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2469593488
Short name T372
Test name
Test status
Simulation time 55211587 ps
CPU time 1.12 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:10 PM PDT 24
Peak memory 217904 kb
Host smart-4373ad43-e648-472c-82da-f968bff6119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469593488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2469593488
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.991021426
Short name T517
Test name
Test status
Simulation time 109650819 ps
CPU time 1.38 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 219664 kb
Host smart-ff546fbb-b503-4b8b-9af9-32ecd019f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991021426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.991021426
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.932425825
Short name T382
Test name
Test status
Simulation time 67506731 ps
CPU time 1.8 seconds
Started Mar 17 12:44:37 PM PDT 24
Finished Mar 17 12:44:38 PM PDT 24
Peak memory 217848 kb
Host smart-9b243c37-c5ae-4821-b906-22cc8818ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932425825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.932425825
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3359689524
Short name T547
Test name
Test status
Simulation time 25374326 ps
CPU time 1.18 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 219100 kb
Host smart-7b1b796c-5d54-4d32-b295-262ad364ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359689524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3359689524
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3161536795
Short name T659
Test name
Test status
Simulation time 28579642 ps
CPU time 1.31 seconds
Started Mar 17 12:44:10 PM PDT 24
Finished Mar 17 12:44:12 PM PDT 24
Peak memory 216864 kb
Host smart-9450b935-ec18-4a7c-b2ac-f974fa513abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161536795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3161536795
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1983392887
Short name T359
Test name
Test status
Simulation time 33624104 ps
CPU time 1.33 seconds
Started Mar 17 12:44:17 PM PDT 24
Finished Mar 17 12:44:18 PM PDT 24
Peak memory 216724 kb
Host smart-6c3222ac-ed40-449d-8f4f-498bc94ddbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983392887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1983392887
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3875706536
Short name T719
Test name
Test status
Simulation time 39766234 ps
CPU time 1.33 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 217808 kb
Host smart-bcbc71dd-c5b9-4e07-8d60-b282f39d5d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875706536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3875706536
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1128151352
Short name T300
Test name
Test status
Simulation time 78031599 ps
CPU time 1.17 seconds
Started Mar 17 12:42:29 PM PDT 24
Finished Mar 17 12:42:31 PM PDT 24
Peak memory 215712 kb
Host smart-8ff9c05f-ab1f-47ea-9157-6bd7ac829992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128151352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1128151352
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1385367326
Short name T509
Test name
Test status
Simulation time 54371473 ps
CPU time 0.88 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 206464 kb
Host smart-3b8a6a5c-d068-4205-8763-03d78e9ae1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385367326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1385367326
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1633521649
Short name T740
Test name
Test status
Simulation time 94799345 ps
CPU time 0.81 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 215472 kb
Host smart-8f16b3b4-c072-46ac-9e3f-c9bcb7aec8fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633521649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1633521649
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.957593106
Short name T489
Test name
Test status
Simulation time 78747370 ps
CPU time 1.02 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 217824 kb
Host smart-30300938-0c60-471f-aedd-70783810a3b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957593106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.957593106
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.870041295
Short name T17
Test name
Test status
Simulation time 18396805 ps
CPU time 1.13 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 222944 kb
Host smart-3fdba7d3-0729-4397-9716-cc507831cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870041295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.870041295
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1872163323
Short name T39
Test name
Test status
Simulation time 64473898 ps
CPU time 1.48 seconds
Started Mar 17 12:42:26 PM PDT 24
Finished Mar 17 12:42:28 PM PDT 24
Peak memory 218268 kb
Host smart-3a48e714-4769-4690-814f-6799be44e656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872163323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1872163323
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3308805831
Short name T357
Test name
Test status
Simulation time 23458466 ps
CPU time 1.14 seconds
Started Mar 17 12:42:29 PM PDT 24
Finished Mar 17 12:42:30 PM PDT 24
Peak memory 224060 kb
Host smart-c2cf68d3-33f0-4711-ae9c-2bcb414caea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308805831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3308805831
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2483420856
Short name T301
Test name
Test status
Simulation time 44600964 ps
CPU time 0.89 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 207112 kb
Host smart-50ea5657-c9db-4462-865a-87afe5a14b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483420856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2483420856
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2816809879
Short name T21
Test name
Test status
Simulation time 351649994 ps
CPU time 5.88 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 236384 kb
Host smart-f33f31f1-dfbf-4da8-a724-b8c00a1c9db5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816809879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2816809879
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.266875342
Short name T337
Test name
Test status
Simulation time 21629142 ps
CPU time 0.94 seconds
Started Mar 17 12:42:30 PM PDT 24
Finished Mar 17 12:42:31 PM PDT 24
Peak memory 215300 kb
Host smart-8a75a310-5c8c-4ef2-ba42-69e15142d79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266875342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.266875342
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2614663263
Short name T428
Test name
Test status
Simulation time 192382288 ps
CPU time 3.86 seconds
Started Mar 17 12:42:25 PM PDT 24
Finished Mar 17 12:42:30 PM PDT 24
Peak memory 215280 kb
Host smart-4cf3d799-0122-43d9-a253-e00dd60abeee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614663263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2614663263
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4099062544
Short name T195
Test name
Test status
Simulation time 203609705085 ps
CPU time 1060.66 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 01:00:14 PM PDT 24
Peak memory 222208 kb
Host smart-1e178092-5104-4e4d-be9a-11ead1dcc586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099062544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4099062544
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.487361167
Short name T20
Test name
Test status
Simulation time 34845985 ps
CPU time 1.17 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:04 PM PDT 24
Peak memory 215668 kb
Host smart-18e1e8f0-0ffb-4599-af86-1e0ed4a3a05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487361167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.487361167
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.362124957
Short name T829
Test name
Test status
Simulation time 190769846 ps
CPU time 0.9 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 206860 kb
Host smart-6123a43a-3bff-4875-9dac-19e45ff06e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362124957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.362124957
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_err.3469316876
Short name T86
Test name
Test status
Simulation time 31893417 ps
CPU time 0.87 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 218092 kb
Host smart-f5aa04a9-1f70-40a0-84e0-3b8f516e73e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469316876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3469316876
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2166974573
Short name T480
Test name
Test status
Simulation time 87728084 ps
CPU time 1.1 seconds
Started Mar 17 12:43:00 PM PDT 24
Finished Mar 17 12:43:03 PM PDT 24
Peak memory 219016 kb
Host smart-3fddb982-94b8-474f-8817-b27f91c2525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166974573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2166974573
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1959963179
Short name T754
Test name
Test status
Simulation time 19803918 ps
CPU time 1.06 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215764 kb
Host smart-96f09ff0-8c45-46a9-bab4-1e0422843af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959963179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1959963179
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3784379083
Short name T752
Test name
Test status
Simulation time 14648750 ps
CPU time 0.95 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:04 PM PDT 24
Peak memory 215268 kb
Host smart-71c110f2-f4a1-43ed-b5fe-59b28039f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784379083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3784379083
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3303790252
Short name T810
Test name
Test status
Simulation time 351020040 ps
CPU time 3.96 seconds
Started Mar 17 12:43:02 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 216704 kb
Host smart-1ad25a83-a232-433f-87c5-494c6a00a87f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303790252 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3303790252
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2086117769
Short name T150
Test name
Test status
Simulation time 35677576892 ps
CPU time 755.28 seconds
Started Mar 17 12:43:01 PM PDT 24
Finished Mar 17 12:55:37 PM PDT 24
Peak memory 218892 kb
Host smart-295aaafa-2d50-4bad-8ef7-e1a4cb55e03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086117769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2086117769
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2940064490
Short name T525
Test name
Test status
Simulation time 50956296 ps
CPU time 1.28 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 218816 kb
Host smart-2432a4d7-eb9f-488b-83e8-99fe28efc8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940064490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2940064490
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1128941008
Short name T635
Test name
Test status
Simulation time 36487795 ps
CPU time 1.37 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 216720 kb
Host smart-cd5fba22-cb77-4f0f-8462-caaede15f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128941008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1128941008
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4130709579
Short name T790
Test name
Test status
Simulation time 27981310 ps
CPU time 1.22 seconds
Started Mar 17 12:44:31 PM PDT 24
Finished Mar 17 12:44:33 PM PDT 24
Peak memory 217812 kb
Host smart-df64f4bc-6d21-4fc3-94a8-6fa1779b475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130709579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4130709579
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1179799942
Short name T567
Test name
Test status
Simulation time 64822447 ps
CPU time 1.35 seconds
Started Mar 17 12:44:11 PM PDT 24
Finished Mar 17 12:44:13 PM PDT 24
Peak memory 217676 kb
Host smart-befcd006-cfb1-465c-8b39-a0a4b7947f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179799942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1179799942
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1820508313
Short name T554
Test name
Test status
Simulation time 49954119 ps
CPU time 1.24 seconds
Started Mar 17 12:44:11 PM PDT 24
Finished Mar 17 12:44:13 PM PDT 24
Peak memory 218208 kb
Host smart-9fc03c16-8e08-48d2-ad9a-c88ce32084e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820508313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1820508313
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3380387000
Short name T721
Test name
Test status
Simulation time 250278907 ps
CPU time 2.97 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 218092 kb
Host smart-b70b9452-a58c-4c0d-b94b-46123d3e2a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380387000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3380387000
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3008470159
Short name T562
Test name
Test status
Simulation time 158653030 ps
CPU time 1.02 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 216712 kb
Host smart-da2e458e-b94a-41aa-b4cb-40a8ccfc6a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008470159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3008470159
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2551752958
Short name T698
Test name
Test status
Simulation time 76893606 ps
CPU time 1.2 seconds
Started Mar 17 12:44:29 PM PDT 24
Finished Mar 17 12:44:31 PM PDT 24
Peak memory 217844 kb
Host smart-7b9820ef-271e-440c-8b8f-bf86b2c61375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551752958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2551752958
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2129018566
Short name T804
Test name
Test status
Simulation time 44249294 ps
CPU time 1.5 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 218188 kb
Host smart-1c67a2e2-3878-45a8-9121-31c4b747e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129018566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2129018566
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4120575021
Short name T154
Test name
Test status
Simulation time 312763192 ps
CPU time 1.48 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:13 PM PDT 24
Peak memory 215688 kb
Host smart-2c800cb6-24b8-4b66-9db1-f17784d1c4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120575021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4120575021
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3809381232
Short name T566
Test name
Test status
Simulation time 36635427 ps
CPU time 0.96 seconds
Started Mar 17 12:43:12 PM PDT 24
Finished Mar 17 12:43:13 PM PDT 24
Peak memory 206492 kb
Host smart-347d1ebb-60fe-4c14-bd71-34b0a8ed0ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809381232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3809381232
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.719695459
Short name T701
Test name
Test status
Simulation time 74085103 ps
CPU time 1 seconds
Started Mar 17 12:43:10 PM PDT 24
Finished Mar 17 12:43:11 PM PDT 24
Peak memory 217504 kb
Host smart-29555717-812f-4706-986f-83b598d95575
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719695459 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.719695459
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2057814611
Short name T114
Test name
Test status
Simulation time 24679204 ps
CPU time 0.91 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 218004 kb
Host smart-67edafa9-86f1-40f7-b06d-8dcbec7968b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057814611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2057814611
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1385466839
Short name T732
Test name
Test status
Simulation time 32792076 ps
CPU time 1.24 seconds
Started Mar 17 12:43:08 PM PDT 24
Finished Mar 17 12:43:12 PM PDT 24
Peak memory 219336 kb
Host smart-4c911b1e-8719-43c7-9b13-f23341499c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385466839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1385466839
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3117401451
Short name T347
Test name
Test status
Simulation time 79321431 ps
CPU time 0.84 seconds
Started Mar 17 12:43:08 PM PDT 24
Finished Mar 17 12:43:09 PM PDT 24
Peak memory 215372 kb
Host smart-6ba69d28-a4bd-4c4d-8838-bf53f6324702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117401451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3117401451
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.588146995
Short name T799
Test name
Test status
Simulation time 19262223 ps
CPU time 1.06 seconds
Started Mar 17 12:43:10 PM PDT 24
Finished Mar 17 12:43:11 PM PDT 24
Peak memory 215328 kb
Host smart-07d7a06d-3dfa-4ffc-af6e-bc093890cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588146995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.588146995
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1010014946
Short name T528
Test name
Test status
Simulation time 1147257480 ps
CPU time 4.62 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:12 PM PDT 24
Peak memory 216504 kb
Host smart-3f72cfb0-576e-403c-8f8a-3c0832be054c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010014946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1010014946
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3403902078
Short name T537
Test name
Test status
Simulation time 465720756947 ps
CPU time 736.3 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:55:24 PM PDT 24
Peak memory 219608 kb
Host smart-d3f049b3-5be1-4cc9-882b-4c9826911800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403902078 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3403902078
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.905222011
Short name T304
Test name
Test status
Simulation time 42477875 ps
CPU time 1.17 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 216744 kb
Host smart-bce8b2ff-6474-4ae8-9867-33fb95cc63bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905222011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.905222011
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1053504876
Short name T741
Test name
Test status
Simulation time 51232077 ps
CPU time 1.23 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 218560 kb
Host smart-9176c11a-07df-4ad8-b753-452761613da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053504876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1053504876
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.242281423
Short name T733
Test name
Test status
Simulation time 159793463 ps
CPU time 1 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 216620 kb
Host smart-1ccd5c79-c871-44d7-9c64-52bd487abd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242281423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.242281423
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3860759200
Short name T524
Test name
Test status
Simulation time 44096011 ps
CPU time 1.6 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 218672 kb
Host smart-3b527fe8-f83e-4a28-8a9c-a5c914d8e828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860759200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3860759200
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3778480957
Short name T377
Test name
Test status
Simulation time 87994107 ps
CPU time 1.28 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 216872 kb
Host smart-7a46bc7d-689e-49c1-af40-8877613dea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778480957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3778480957
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2055086347
Short name T403
Test name
Test status
Simulation time 74122298 ps
CPU time 1.01 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 216544 kb
Host smart-6854ee6c-036b-4d8f-9084-51407fd7de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055086347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2055086347
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1314038307
Short name T683
Test name
Test status
Simulation time 57365137 ps
CPU time 2.04 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 216808 kb
Host smart-f2a87508-0fbc-4cab-a788-a75d4eefb362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314038307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1314038307
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2505861700
Short name T287
Test name
Test status
Simulation time 65624369 ps
CPU time 1.84 seconds
Started Mar 17 12:44:17 PM PDT 24
Finished Mar 17 12:44:19 PM PDT 24
Peak memory 218136 kb
Host smart-af58a39d-945b-4600-b519-3185f0b51a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505861700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2505861700
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3467142306
Short name T744
Test name
Test status
Simulation time 92634634 ps
CPU time 2.98 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 218172 kb
Host smart-737e35e5-9677-48eb-8084-6efb85391a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467142306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3467142306
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1255289570
Short name T56
Test name
Test status
Simulation time 92360472 ps
CPU time 2.19 seconds
Started Mar 17 12:44:11 PM PDT 24
Finished Mar 17 12:44:14 PM PDT 24
Peak memory 217900 kb
Host smart-171abf99-803a-4b30-9830-a3fe69dd56fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255289570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1255289570
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1401033655
Short name T459
Test name
Test status
Simulation time 94193017 ps
CPU time 1.24 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215696 kb
Host smart-25c10b83-9797-428b-a0e8-367180a16d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401033655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1401033655
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3265593481
Short name T782
Test name
Test status
Simulation time 16525563 ps
CPU time 0.88 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 206004 kb
Host smart-32432013-8dd0-4779-a2bd-c027724d43d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265593481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3265593481
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2682175219
Short name T102
Test name
Test status
Simulation time 14912874 ps
CPU time 0.9 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 216072 kb
Host smart-4c3214af-97de-41f9-9208-fab27f75b75c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682175219 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2682175219
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.297305574
Short name T170
Test name
Test status
Simulation time 100851736 ps
CPU time 0.97 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 216816 kb
Host smart-638cda71-0fac-4ca6-8f8e-85b25b93c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297305574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.297305574
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.447696596
Short name T334
Test name
Test status
Simulation time 52335794 ps
CPU time 1.58 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 218148 kb
Host smart-d824c4d4-e9af-47e2-9831-bc6c3175185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447696596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.447696596
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3571143821
Short name T137
Test name
Test status
Simulation time 22092048 ps
CPU time 1 seconds
Started Mar 17 12:43:04 PM PDT 24
Finished Mar 17 12:43:06 PM PDT 24
Peak memory 215756 kb
Host smart-fc6d03c4-44e3-47e4-9dbc-60205525a4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571143821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3571143821
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4131710935
Short name T1
Test name
Test status
Simulation time 27732137 ps
CPU time 0.94 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215356 kb
Host smart-841cae89-f50f-46da-91ae-ffb2d9885146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131710935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4131710935
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4256682347
Short name T667
Test name
Test status
Simulation time 324166682 ps
CPU time 5.89 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:13 PM PDT 24
Peak memory 216764 kb
Host smart-afdd85e5-ed02-4740-ae64-1944166f8278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256682347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4256682347
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.177031802
Short name T61
Test name
Test status
Simulation time 86495894136 ps
CPU time 1242.43 seconds
Started Mar 17 12:43:10 PM PDT 24
Finished Mar 17 01:03:53 PM PDT 24
Peak memory 224524 kb
Host smart-29be77ed-a5d8-4c58-b94f-938b15b4eea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177031802 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.177031802
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2947940650
Short name T424
Test name
Test status
Simulation time 38799605 ps
CPU time 1.03 seconds
Started Mar 17 12:44:12 PM PDT 24
Finished Mar 17 12:44:13 PM PDT 24
Peak memory 216508 kb
Host smart-4eccc139-f76b-4bf3-ae09-2d5ad92f5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947940650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2947940650
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4023470448
Short name T603
Test name
Test status
Simulation time 194159230 ps
CPU time 2.8 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:10 PM PDT 24
Peak memory 216880 kb
Host smart-499ac7e8-0807-4fca-8c29-a01a75b309e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023470448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4023470448
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3616423421
Short name T437
Test name
Test status
Simulation time 83727890 ps
CPU time 1.1 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 216772 kb
Host smart-7f460008-8f51-4405-9a00-f3cce81eed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616423421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3616423421
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3667479159
Short name T259
Test name
Test status
Simulation time 58338816 ps
CPU time 1.34 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 219444 kb
Host smart-baa4e776-f218-4a60-bc87-d5e4ec95c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667479159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3667479159
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.78795748
Short name T249
Test name
Test status
Simulation time 105713154 ps
CPU time 1.14 seconds
Started Mar 17 12:44:22 PM PDT 24
Finished Mar 17 12:44:23 PM PDT 24
Peak memory 216816 kb
Host smart-92fbf7ac-34fe-4110-9c26-49d9b6f15a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78795748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.78795748
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3372063256
Short name T35
Test name
Test status
Simulation time 79073477 ps
CPU time 1.28 seconds
Started Mar 17 12:44:34 PM PDT 24
Finished Mar 17 12:44:36 PM PDT 24
Peak memory 217908 kb
Host smart-7df0749e-05f9-41c1-adfd-0048269e4510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372063256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3372063256
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3842897178
Short name T252
Test name
Test status
Simulation time 55613465 ps
CPU time 1.17 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 217892 kb
Host smart-e6afc1a7-6cc6-4313-ab82-b748eb3ad60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842897178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3842897178
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.4055143509
Short name T363
Test name
Test status
Simulation time 119806618 ps
CPU time 1.12 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 218448 kb
Host smart-dcc3d451-6bb1-4427-b26a-0bbe3b092329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055143509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.4055143509
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1729907340
Short name T812
Test name
Test status
Simulation time 113342310 ps
CPU time 1.32 seconds
Started Mar 17 12:44:07 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 219560 kb
Host smart-e03d41b9-61ff-4f17-b937-6847afd61d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729907340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1729907340
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3315258276
Short name T729
Test name
Test status
Simulation time 171343636 ps
CPU time 1.02 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:10 PM PDT 24
Peak memory 216800 kb
Host smart-b947ca45-f30b-484b-85ff-00b2e2bf1ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315258276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3315258276
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.146090944
Short name T623
Test name
Test status
Simulation time 82602649 ps
CPU time 1.16 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215608 kb
Host smart-ded15711-6226-4774-82c7-9dfad838ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146090944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.146090944
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3931337576
Short name T365
Test name
Test status
Simulation time 16883410 ps
CPU time 0.93 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 206580 kb
Host smart-a58964f3-5863-4c3d-9a5e-9739067847c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931337576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3931337576
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1311390450
Short name T743
Test name
Test status
Simulation time 77868051 ps
CPU time 0.92 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 216556 kb
Host smart-25d3adb0-6f0d-44de-919b-213fa76cc99f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311390450 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1311390450
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.633818535
Short name T801
Test name
Test status
Simulation time 31736093 ps
CPU time 0.99 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 219260 kb
Host smart-ca83540b-4836-49f3-9b1f-9b6dede81f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633818535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.633818535
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1830196752
Short name T666
Test name
Test status
Simulation time 92668461 ps
CPU time 1.16 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 216676 kb
Host smart-4e6a4dac-53d1-4250-bcac-fcd5f0b4071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830196752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1830196752
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2067746870
Short name T806
Test name
Test status
Simulation time 23663186 ps
CPU time 0.93 seconds
Started Mar 17 12:43:08 PM PDT 24
Finished Mar 17 12:43:09 PM PDT 24
Peak memory 215768 kb
Host smart-0d2cd69c-60cf-40b2-8eaf-70dbe66d29ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067746870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2067746870
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.581947779
Short name T440
Test name
Test status
Simulation time 33340501 ps
CPU time 0.91 seconds
Started Mar 17 12:43:11 PM PDT 24
Finished Mar 17 12:43:12 PM PDT 24
Peak memory 215264 kb
Host smart-c4fe57a5-2b4f-4164-aa59-87a6fa8024f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581947779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.581947779
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2605113961
Short name T343
Test name
Test status
Simulation time 26752401 ps
CPU time 1.1 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 215348 kb
Host smart-695e06a7-034d-4072-a655-fc18eca4cec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605113961 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2605113961
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.194887346
Short name T132
Test name
Test status
Simulation time 279418399470 ps
CPU time 1613.85 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 225792 kb
Host smart-98bd608a-5168-45b8-8a81-ac944be419a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194887346 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.194887346
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.596442170
Short name T469
Test name
Test status
Simulation time 57009975 ps
CPU time 1.93 seconds
Started Mar 17 12:44:11 PM PDT 24
Finished Mar 17 12:44:14 PM PDT 24
Peak memory 217556 kb
Host smart-fa82e5ca-a8a9-4440-a829-e07914d21b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596442170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.596442170
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.754654711
Short name T308
Test name
Test status
Simulation time 78834562 ps
CPU time 2.37 seconds
Started Mar 17 12:44:11 PM PDT 24
Finished Mar 17 12:44:14 PM PDT 24
Peak memory 218140 kb
Host smart-2709a83a-7d82-4cb7-9665-2538f3eb427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754654711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.754654711
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3643678453
Short name T345
Test name
Test status
Simulation time 77892464 ps
CPU time 1.24 seconds
Started Mar 17 12:44:16 PM PDT 24
Finished Mar 17 12:44:18 PM PDT 24
Peak memory 218328 kb
Host smart-0c71ad63-e816-4faa-a830-d9ffe83593f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643678453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3643678453
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1526123488
Short name T40
Test name
Test status
Simulation time 82864528 ps
CPU time 1.12 seconds
Started Mar 17 12:44:12 PM PDT 24
Finished Mar 17 12:44:14 PM PDT 24
Peak memory 216612 kb
Host smart-370ed68f-606e-4547-9170-563cf3df6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526123488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1526123488
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.213122778
Short name T540
Test name
Test status
Simulation time 45210920 ps
CPU time 1.48 seconds
Started Mar 17 12:44:47 PM PDT 24
Finished Mar 17 12:44:49 PM PDT 24
Peak memory 217896 kb
Host smart-72603da2-fb26-460c-bfbd-3ee910163ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213122778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.213122778
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1434917837
Short name T521
Test name
Test status
Simulation time 108190022 ps
CPU time 1.35 seconds
Started Mar 17 12:44:30 PM PDT 24
Finished Mar 17 12:44:33 PM PDT 24
Peak memory 216768 kb
Host smart-b1cea172-2cec-47b1-965a-5606579af05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434917837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1434917837
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1703601279
Short name T263
Test name
Test status
Simulation time 74936001 ps
CPU time 1.55 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 218220 kb
Host smart-cb770952-45d3-4590-8320-7ae12257dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703601279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1703601279
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3041666574
Short name T679
Test name
Test status
Simulation time 54729331 ps
CPU time 1.23 seconds
Started Mar 17 12:44:29 PM PDT 24
Finished Mar 17 12:44:31 PM PDT 24
Peak memory 218580 kb
Host smart-3fccb55f-3ad4-4dac-9ee7-94dfa07bcc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041666574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3041666574
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1523964573
Short name T448
Test name
Test status
Simulation time 41015868 ps
CPU time 1.42 seconds
Started Mar 17 12:44:29 PM PDT 24
Finished Mar 17 12:44:31 PM PDT 24
Peak memory 216600 kb
Host smart-21a6e1f4-a7af-4db1-a12b-383c74fcecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523964573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1523964573
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3643812244
Short name T767
Test name
Test status
Simulation time 85652973 ps
CPU time 1.75 seconds
Started Mar 17 12:44:09 PM PDT 24
Finished Mar 17 12:44:11 PM PDT 24
Peak memory 218940 kb
Host smart-bbf2842b-0f58-470b-a101-b3148a3d4e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643812244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3643812244
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2991819060
Short name T569
Test name
Test status
Simulation time 166449689 ps
CPU time 1.12 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:43:06 PM PDT 24
Peak memory 215680 kb
Host smart-10c65421-5b04-458e-9763-16e071957f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991819060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2991819060
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4225802120
Short name T649
Test name
Test status
Simulation time 26301240 ps
CPU time 1.04 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 206088 kb
Host smart-66fb2dea-2a82-46ee-9e37-02eb24d542e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225802120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4225802120
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3147903863
Short name T565
Test name
Test status
Simulation time 24294275 ps
CPU time 0.9 seconds
Started Mar 17 12:43:06 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 215788 kb
Host smart-db141967-a6c6-44b4-8148-fac74ae9ee17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147903863 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3147903863
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3372903752
Short name T748
Test name
Test status
Simulation time 99570594 ps
CPU time 1.03 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:09 PM PDT 24
Peak memory 216692 kb
Host smart-f7934947-dca7-4d4f-92d7-76bb2633a319
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372903752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3372903752
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.939744706
Short name T641
Test name
Test status
Simulation time 32144238 ps
CPU time 0.97 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 230992 kb
Host smart-c9640b17-a74e-469a-8a59-63ec1dffa7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939744706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.939744706
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2748947710
Short name T14
Test name
Test status
Simulation time 113875484 ps
CPU time 1.32 seconds
Started Mar 17 12:43:08 PM PDT 24
Finished Mar 17 12:43:09 PM PDT 24
Peak memory 219608 kb
Host smart-1362dc37-1977-4f44-bf55-657c3d5af1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748947710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2748947710
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4197085550
Short name T808
Test name
Test status
Simulation time 26936875 ps
CPU time 1.04 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 223952 kb
Host smart-d5904cbc-7adb-42fd-b980-7f2681216bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197085550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4197085550
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2072719243
Short name T352
Test name
Test status
Simulation time 37461132 ps
CPU time 0.9 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215312 kb
Host smart-801fd82a-27ee-4d3c-b876-3c8799daca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072719243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2072719243
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.269338012
Short name T207
Test name
Test status
Simulation time 183975327 ps
CPU time 3.57 seconds
Started Mar 17 12:43:10 PM PDT 24
Finished Mar 17 12:43:13 PM PDT 24
Peak memory 218452 kb
Host smart-c5f1b2f9-7eee-4372-a959-f4224400736f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269338012 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.269338012
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2379613946
Short name T662
Test name
Test status
Simulation time 14832618614 ps
CPU time 316.7 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:48:25 PM PDT 24
Peak memory 219288 kb
Host smart-b83aeb05-c5c1-4a19-a133-e1b81bfced3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379613946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2379613946
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3338406903
Short name T747
Test name
Test status
Simulation time 91466851 ps
CPU time 0.96 seconds
Started Mar 17 12:44:32 PM PDT 24
Finished Mar 17 12:44:34 PM PDT 24
Peak memory 216580 kb
Host smart-e92d5840-8553-41f0-baf8-7ccf90c1e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338406903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3338406903
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2590763637
Short name T803
Test name
Test status
Simulation time 100091378 ps
CPU time 1.58 seconds
Started Mar 17 12:44:31 PM PDT 24
Finished Mar 17 12:44:33 PM PDT 24
Peak memory 218208 kb
Host smart-13b3a798-a275-4c80-9bd9-3e1c06e30d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590763637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2590763637
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.885864928
Short name T647
Test name
Test status
Simulation time 93423272 ps
CPU time 1.44 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 216572 kb
Host smart-f931bfc5-de3c-45a0-a4aa-c3c6ef056c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885864928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.885864928
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2216131466
Short name T588
Test name
Test status
Simulation time 31130916 ps
CPU time 1.28 seconds
Started Mar 17 12:44:33 PM PDT 24
Finished Mar 17 12:44:35 PM PDT 24
Peak memory 216656 kb
Host smart-b8d159ea-7ebb-4444-92d7-3b964c314065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216131466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2216131466
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.964432584
Short name T726
Test name
Test status
Simulation time 49450446 ps
CPU time 1.2 seconds
Started Mar 17 12:44:19 PM PDT 24
Finished Mar 17 12:44:20 PM PDT 24
Peak memory 217976 kb
Host smart-e9a35192-1e11-483c-b5ae-68beda4901c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964432584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.964432584
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2255410090
Short name T615
Test name
Test status
Simulation time 93699004 ps
CPU time 1.43 seconds
Started Mar 17 12:44:42 PM PDT 24
Finished Mar 17 12:44:43 PM PDT 24
Peak memory 218000 kb
Host smart-9651a151-c5dd-4a50-8a96-041e913d5ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255410090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2255410090
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4229453618
Short name T261
Test name
Test status
Simulation time 79654159 ps
CPU time 1.52 seconds
Started Mar 17 12:44:17 PM PDT 24
Finished Mar 17 12:44:18 PM PDT 24
Peak memory 218268 kb
Host smart-0cc634b8-d991-4946-ad16-39df0c6f72b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229453618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4229453618
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2326372519
Short name T174
Test name
Test status
Simulation time 189259217 ps
CPU time 1.14 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:10 PM PDT 24
Peak memory 216548 kb
Host smart-a976e55a-3699-4381-b212-c243ad3ed041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326372519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2326372519
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2852572989
Short name T816
Test name
Test status
Simulation time 49785669 ps
CPU time 1.96 seconds
Started Mar 17 12:44:30 PM PDT 24
Finished Mar 17 12:44:33 PM PDT 24
Peak memory 217016 kb
Host smart-0f239568-4d83-4141-a39d-7f8b615b5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852572989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2852572989
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3109707112
Short name T510
Test name
Test status
Simulation time 61453538 ps
CPU time 1.1 seconds
Started Mar 17 12:44:40 PM PDT 24
Finished Mar 17 12:44:41 PM PDT 24
Peak memory 216716 kb
Host smart-4ae3964a-8d19-4bd0-b236-e977954c078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109707112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3109707112
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1796206842
Short name T533
Test name
Test status
Simulation time 84306937 ps
CPU time 1.19 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:10 PM PDT 24
Peak memory 215704 kb
Host smart-724084ac-c28e-4f7d-876d-31a3adfeb3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796206842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1796206842
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3594141127
Short name T653
Test name
Test status
Simulation time 15337600 ps
CPU time 0.92 seconds
Started Mar 17 12:43:05 PM PDT 24
Finished Mar 17 12:43:07 PM PDT 24
Peak memory 206536 kb
Host smart-0a9606ae-c471-45fd-b79e-adf4319ad79f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594141127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3594141127
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2620679215
Short name T650
Test name
Test status
Simulation time 40710385 ps
CPU time 0.9 seconds
Started Mar 17 12:43:10 PM PDT 24
Finished Mar 17 12:43:11 PM PDT 24
Peak memory 215888 kb
Host smart-ed4943bc-dd3d-42e0-8fbb-39953e7cdba7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620679215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2620679215
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.4241351841
Short name T109
Test name
Test status
Simulation time 138066201 ps
CPU time 1.08 seconds
Started Mar 17 12:43:08 PM PDT 24
Finished Mar 17 12:43:09 PM PDT 24
Peak memory 219248 kb
Host smart-b61e22c7-f0b6-4685-97f4-16003694cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241351841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4241351841
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2765520312
Short name T444
Test name
Test status
Simulation time 49967153 ps
CPU time 1.91 seconds
Started Mar 17 12:43:12 PM PDT 24
Finished Mar 17 12:43:14 PM PDT 24
Peak memory 218816 kb
Host smart-49781433-73eb-438c-ba5c-4cb222b8a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765520312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2765520312
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.1311159537
Short name T802
Test name
Test status
Simulation time 90243790 ps
CPU time 0.92 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215288 kb
Host smart-5d7b002e-e6aa-47d4-913b-4b8920a0c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311159537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1311159537
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2648603015
Short name T543
Test name
Test status
Simulation time 330859910 ps
CPU time 4.94 seconds
Started Mar 17 12:43:09 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 216316 kb
Host smart-4d9d7ba1-ac61-4da2-8fbb-50454b8b9b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648603015 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2648603015
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.995350792
Short name T691
Test name
Test status
Simulation time 254629800802 ps
CPU time 914.76 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:58:22 PM PDT 24
Peak memory 221304 kb
Host smart-2f68fd42-d667-4468-9010-44b78081dde8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995350792 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.995350792
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2631263615
Short name T506
Test name
Test status
Simulation time 78262761 ps
CPU time 1.06 seconds
Started Mar 17 12:44:32 PM PDT 24
Finished Mar 17 12:44:34 PM PDT 24
Peak memory 217736 kb
Host smart-cde8096c-9403-4543-8eed-d6e35574f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631263615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2631263615
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2152960033
Short name T262
Test name
Test status
Simulation time 202388527 ps
CPU time 1.13 seconds
Started Mar 17 12:44:23 PM PDT 24
Finished Mar 17 12:44:25 PM PDT 24
Peak memory 216704 kb
Host smart-5bff66cb-d748-464d-ad15-4b99b6ebf9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152960033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2152960033
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3689414997
Short name T278
Test name
Test status
Simulation time 132645493 ps
CPU time 1.29 seconds
Started Mar 17 12:44:09 PM PDT 24
Finished Mar 17 12:44:11 PM PDT 24
Peak memory 217876 kb
Host smart-409f4811-f6ee-496e-ba26-3b50cd89c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689414997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3689414997
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1280263268
Short name T728
Test name
Test status
Simulation time 121279114 ps
CPU time 1.23 seconds
Started Mar 17 12:44:44 PM PDT 24
Finished Mar 17 12:44:45 PM PDT 24
Peak memory 216888 kb
Host smart-6e1e7808-3f6a-4ef3-badb-c887aac499e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280263268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1280263268
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4102498321
Short name T344
Test name
Test status
Simulation time 101940980 ps
CPU time 1.92 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:41 PM PDT 24
Peak memory 219292 kb
Host smart-d9df0aa4-23b5-466e-b22a-c3464fa907a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102498321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4102498321
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1392316498
Short name T282
Test name
Test status
Simulation time 110521439 ps
CPU time 1.2 seconds
Started Mar 17 12:44:31 PM PDT 24
Finished Mar 17 12:44:33 PM PDT 24
Peak memory 219476 kb
Host smart-00d5ef58-ea3d-4115-a970-1009b461ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392316498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1392316498
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2679888968
Short name T682
Test name
Test status
Simulation time 113165104 ps
CPU time 2.39 seconds
Started Mar 17 12:44:37 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 218428 kb
Host smart-fcfc5c86-638a-47bc-8856-88cae71ebc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679888968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2679888968
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.741363998
Short name T715
Test name
Test status
Simulation time 78135815 ps
CPU time 1.13 seconds
Started Mar 17 12:44:33 PM PDT 24
Finished Mar 17 12:44:35 PM PDT 24
Peak memory 216716 kb
Host smart-c5f19179-5005-45fd-a8dc-29d2d2f9ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741363998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.741363998
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2271221964
Short name T708
Test name
Test status
Simulation time 39060904 ps
CPU time 1.54 seconds
Started Mar 17 12:44:31 PM PDT 24
Finished Mar 17 12:44:33 PM PDT 24
Peak memory 219212 kb
Host smart-3985f7a7-6c15-46ff-ac42-9b8533ba4bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271221964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2271221964
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2651511368
Short name T819
Test name
Test status
Simulation time 41257008 ps
CPU time 1.77 seconds
Started Mar 17 12:44:27 PM PDT 24
Finished Mar 17 12:44:31 PM PDT 24
Peak memory 218052 kb
Host smart-eafd0231-a92d-4a4c-afbb-e3e33d2b1c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651511368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2651511368
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.308549219
Short name T293
Test name
Test status
Simulation time 203092760 ps
CPU time 1.23 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 215604 kb
Host smart-f4fe7d6b-95a9-48f6-b649-8ad847c78294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308549219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.308549219
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1022857523
Short name T680
Test name
Test status
Simulation time 49111413 ps
CPU time 0.86 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 206028 kb
Host smart-25967087-67b9-45d6-b25f-fcd7b9b4947e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022857523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1022857523
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2150422574
Short name T777
Test name
Test status
Simulation time 12438685 ps
CPU time 0.86 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215700 kb
Host smart-b4a1d4ce-ee4f-40d4-ac31-e6898c98592b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150422574 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2150422574
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1666562041
Short name T560
Test name
Test status
Simulation time 97186496 ps
CPU time 1.11 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 216528 kb
Host smart-ad8d916a-daca-4d86-93ca-5d34aa88cbe4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666562041 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1666562041
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.619121540
Short name T124
Test name
Test status
Simulation time 25588516 ps
CPU time 0.9 seconds
Started Mar 17 12:43:14 PM PDT 24
Finished Mar 17 12:43:15 PM PDT 24
Peak memory 217968 kb
Host smart-fb91a94e-c87c-4278-a6f3-47cac87551cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619121540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.619121540
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3625362865
Short name T430
Test name
Test status
Simulation time 51974132 ps
CPU time 1.8 seconds
Started Mar 17 12:43:13 PM PDT 24
Finished Mar 17 12:43:15 PM PDT 24
Peak memory 218116 kb
Host smart-06193dcb-0685-4820-8db8-eeb3e004dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625362865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3625362865
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2659845041
Short name T142
Test name
Test status
Simulation time 29311855 ps
CPU time 0.89 seconds
Started Mar 17 12:43:13 PM PDT 24
Finished Mar 17 12:43:14 PM PDT 24
Peak memory 215888 kb
Host smart-76b2b62b-3069-4367-864c-1ee5e4fdbaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659845041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2659845041
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1870891546
Short name T421
Test name
Test status
Simulation time 28229331 ps
CPU time 0.93 seconds
Started Mar 17 12:43:07 PM PDT 24
Finished Mar 17 12:43:08 PM PDT 24
Peak memory 215340 kb
Host smart-07131a6f-3be1-4f95-a37f-2698234be595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870891546 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1870891546
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3194030431
Short name T339
Test name
Test status
Simulation time 691441155 ps
CPU time 4.18 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:20 PM PDT 24
Peak memory 219056 kb
Host smart-e5ea7ab4-af85-43f7-a483-0af65cb4045b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194030431 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3194030431
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.1385509059
Short name T186
Test name
Test status
Simulation time 57880615 ps
CPU time 1.27 seconds
Started Mar 17 12:44:37 PM PDT 24
Finished Mar 17 12:44:38 PM PDT 24
Peak memory 218900 kb
Host smart-81b128c8-3fba-4d96-b2de-78904d5a9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385509059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1385509059
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.714394084
Short name T532
Test name
Test status
Simulation time 92299734 ps
CPU time 1.98 seconds
Started Mar 17 12:44:28 PM PDT 24
Finished Mar 17 12:44:31 PM PDT 24
Peak memory 219372 kb
Host smart-5fa5985e-df09-4f20-b31b-30b66981026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714394084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.714394084
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2400976403
Short name T476
Test name
Test status
Simulation time 54503208 ps
CPU time 1.5 seconds
Started Mar 17 12:44:33 PM PDT 24
Finished Mar 17 12:44:36 PM PDT 24
Peak memory 218132 kb
Host smart-395d7d24-ab90-49a8-81b9-017340387d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400976403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2400976403
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4115596491
Short name T355
Test name
Test status
Simulation time 51211698 ps
CPU time 1.36 seconds
Started Mar 17 12:44:27 PM PDT 24
Finished Mar 17 12:44:28 PM PDT 24
Peak memory 218000 kb
Host smart-e6b128ca-cdfc-4148-912d-cafc9f199f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115596491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4115596491
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3498205324
Short name T260
Test name
Test status
Simulation time 83107847 ps
CPU time 1.13 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:36 PM PDT 24
Peak memory 218988 kb
Host smart-cacdceb1-8dff-4fd5-94a6-7f36d7bf2e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498205324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3498205324
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.65961435
Short name T342
Test name
Test status
Simulation time 66983724 ps
CPU time 1.05 seconds
Started Mar 17 12:44:44 PM PDT 24
Finished Mar 17 12:44:45 PM PDT 24
Peak memory 216508 kb
Host smart-fb7747a1-4b01-4505-bba7-05282a515ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65961435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.65961435
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1305137657
Short name T258
Test name
Test status
Simulation time 81548214 ps
CPU time 1.17 seconds
Started Mar 17 12:44:26 PM PDT 24
Finished Mar 17 12:44:28 PM PDT 24
Peak memory 216640 kb
Host smart-b1ba68e9-dd2a-4250-8221-abb10854ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305137657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1305137657
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4099293638
Short name T453
Test name
Test status
Simulation time 84867633 ps
CPU time 1.45 seconds
Started Mar 17 12:44:24 PM PDT 24
Finished Mar 17 12:44:26 PM PDT 24
Peak memory 218136 kb
Host smart-8aca05c9-8209-4648-8d47-06429b660596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099293638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4099293638
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3580873561
Short name T432
Test name
Test status
Simulation time 139149677 ps
CPU time 2.93 seconds
Started Mar 17 12:44:29 PM PDT 24
Finished Mar 17 12:44:32 PM PDT 24
Peak memory 216876 kb
Host smart-0ebc12e3-eca1-4bee-ae72-9affa253e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580873561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3580873561
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1021754945
Short name T335
Test name
Test status
Simulation time 88334350 ps
CPU time 1.12 seconds
Started Mar 17 12:44:36 PM PDT 24
Finished Mar 17 12:44:38 PM PDT 24
Peak memory 216616 kb
Host smart-43bf7b8f-5862-4d7d-888a-3d6eb164e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021754945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1021754945
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3737832699
Short name T627
Test name
Test status
Simulation time 143322583 ps
CPU time 1.2 seconds
Started Mar 17 12:43:13 PM PDT 24
Finished Mar 17 12:43:15 PM PDT 24
Peak memory 215676 kb
Host smart-15c8ac40-869a-444c-9ae9-17c9ecd039d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737832699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3737832699
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3143021381
Short name T541
Test name
Test status
Simulation time 55547096 ps
CPU time 0.94 seconds
Started Mar 17 12:43:14 PM PDT 24
Finished Mar 17 12:43:15 PM PDT 24
Peak memory 206048 kb
Host smart-cdc132e8-12d0-4a4a-b732-257baff45b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143021381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3143021381
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4294125397
Short name T636
Test name
Test status
Simulation time 73686558 ps
CPU time 0.79 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215908 kb
Host smart-04b588f8-aecd-462e-bc63-bc054d8363bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294125397 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4294125397
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1454692037
Short name T11
Test name
Test status
Simulation time 26921865 ps
CPU time 1.02 seconds
Started Mar 17 12:43:14 PM PDT 24
Finished Mar 17 12:43:15 PM PDT 24
Peak memory 216352 kb
Host smart-84b2c80c-a42b-42ef-8b81-ef28ff9abff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454692037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1454692037
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3528500305
Short name T610
Test name
Test status
Simulation time 22019320 ps
CPU time 1.06 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 231300 kb
Host smart-cb05b54f-7388-420b-8fcd-167b9e19095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528500305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3528500305
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2581786340
Short name T634
Test name
Test status
Simulation time 68403558 ps
CPU time 1.53 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 218128 kb
Host smart-a1bc8a9e-991e-403d-ac0b-470294e3a993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581786340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2581786340
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.724810031
Short name T139
Test name
Test status
Simulation time 23885128 ps
CPU time 0.99 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 215716 kb
Host smart-0ec46be1-eff4-466b-a7be-906ed6bffe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724810031 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.724810031
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2557588704
Short name T474
Test name
Test status
Simulation time 19390054 ps
CPU time 0.87 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 215244 kb
Host smart-5b24a54e-e528-49e8-b1d2-3e7a71fb619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557588704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2557588704
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1194666803
Short name T284
Test name
Test status
Simulation time 219293948 ps
CPU time 1.24 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 215292 kb
Host smart-9473f08b-e832-4dd8-930b-0d4bb491270c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194666803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1194666803
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1262638554
Short name T189
Test name
Test status
Simulation time 166854856717 ps
CPU time 678.82 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:54:36 PM PDT 24
Peak memory 223716 kb
Host smart-66764b68-8491-4058-bd70-b83bd87cdf29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262638554 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1262638554
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1042007357
Short name T362
Test name
Test status
Simulation time 41899273 ps
CPU time 1.07 seconds
Started Mar 17 12:44:32 PM PDT 24
Finished Mar 17 12:44:34 PM PDT 24
Peak memory 216656 kb
Host smart-d10ea580-f50c-4d3a-bb5a-57561b3ce3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042007357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1042007357
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1989782262
Short name T488
Test name
Test status
Simulation time 100993818 ps
CPU time 1.23 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:39 PM PDT 24
Peak memory 216664 kb
Host smart-995e4308-08cf-49bd-934a-7f70ef35127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989782262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1989782262
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.895672375
Short name T473
Test name
Test status
Simulation time 48172357 ps
CPU time 1.09 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 216524 kb
Host smart-28a7da27-5d0e-4daa-b3a2-d045bb2b4f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895672375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.895672375
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.125974017
Short name T204
Test name
Test status
Simulation time 233127892 ps
CPU time 1.1 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 215324 kb
Host smart-c2e7f935-9fdd-4175-87da-4af99c8bc765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125974017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.125974017
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3855019613
Short name T538
Test name
Test status
Simulation time 78078451 ps
CPU time 0.94 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 216520 kb
Host smart-cafe73ee-4533-4554-b7ea-a1ab3cc6397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855019613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3855019613
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3247012133
Short name T737
Test name
Test status
Simulation time 55351829 ps
CPU time 1.87 seconds
Started Mar 17 12:44:46 PM PDT 24
Finished Mar 17 12:44:48 PM PDT 24
Peak memory 219456 kb
Host smart-8e7b4ec8-1288-4481-8001-852416b51d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247012133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3247012133
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2588492486
Short name T613
Test name
Test status
Simulation time 44851108 ps
CPU time 1.4 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 218508 kb
Host smart-b62acdd9-1cbd-4c54-97d5-4c15ccb4d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588492486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2588492486
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.800272209
Short name T268
Test name
Test status
Simulation time 45903495 ps
CPU time 1.6 seconds
Started Mar 17 12:44:42 PM PDT 24
Finished Mar 17 12:44:43 PM PDT 24
Peak memory 217896 kb
Host smart-826778f3-bfae-4a49-bed3-4916988500fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800272209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.800272209
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.781809812
Short name T823
Test name
Test status
Simulation time 120182104 ps
CPU time 1.17 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:41 PM PDT 24
Peak memory 218224 kb
Host smart-3e51bd40-cdb5-48cd-b48c-80773987277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781809812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.781809812
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1508610937
Short name T37
Test name
Test status
Simulation time 106600197 ps
CPU time 1.57 seconds
Started Mar 17 12:44:42 PM PDT 24
Finished Mar 17 12:44:44 PM PDT 24
Peak memory 219644 kb
Host smart-c684a382-fe38-4657-a288-7cf194a68859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508610937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1508610937
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2285805086
Short name T579
Test name
Test status
Simulation time 23654830 ps
CPU time 1.18 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215648 kb
Host smart-c723cf48-9de3-4c19-bec9-13074dc709ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285805086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2285805086
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.201089682
Short name T630
Test name
Test status
Simulation time 64749368 ps
CPU time 1.32 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 206232 kb
Host smart-46c4d435-a1c5-43a0-a482-1fec1b426e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201089682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.201089682
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2760718881
Short name T127
Test name
Test status
Simulation time 105397735 ps
CPU time 0.82 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215852 kb
Host smart-4a3a5cbb-33f4-420e-b4fc-bb251e588055
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760718881 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2760718881
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.1531545210
Short name T113
Test name
Test status
Simulation time 23844711 ps
CPU time 0.92 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 218120 kb
Host smart-03145817-1891-42c5-a4a0-ec13bd9b3d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531545210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1531545210
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2677120410
Short name T758
Test name
Test status
Simulation time 150634896 ps
CPU time 1.95 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 218004 kb
Host smart-15c03d13-4236-4660-9e64-56bbd1cff4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677120410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2677120410
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.590734939
Short name T427
Test name
Test status
Simulation time 60461304 ps
CPU time 0.85 seconds
Started Mar 17 12:43:13 PM PDT 24
Finished Mar 17 12:43:14 PM PDT 24
Peak memory 215180 kb
Host smart-66366cae-c362-4c76-8ad1-2400f95eb3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590734939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.590734939
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3986500389
Short name T675
Test name
Test status
Simulation time 18365670 ps
CPU time 0.97 seconds
Started Mar 17 12:43:22 PM PDT 24
Finished Mar 17 12:43:23 PM PDT 24
Peak memory 215252 kb
Host smart-cf62b8d1-4d32-4f10-b6dc-8d3c97452466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986500389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3986500389
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4232968908
Short name T350
Test name
Test status
Simulation time 352667821 ps
CPU time 4.87 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 216576 kb
Host smart-1317eb2c-320e-4a31-aa55-267446e597e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232968908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4232968908
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1401672205
Short name T727
Test name
Test status
Simulation time 79091008242 ps
CPU time 452.68 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:50:51 PM PDT 24
Peak memory 218372 kb
Host smart-a05ea8f3-ff9d-438a-9cfe-db7d644a674a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401672205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1401672205
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2896419227
Short name T218
Test name
Test status
Simulation time 70567168 ps
CPU time 1.09 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 216836 kb
Host smart-0194d9be-f042-4b9b-8b85-5d8d90750fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896419227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2896419227
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4293332927
Short name T676
Test name
Test status
Simulation time 104851256 ps
CPU time 1.51 seconds
Started Mar 17 12:44:44 PM PDT 24
Finished Mar 17 12:44:46 PM PDT 24
Peak memory 218492 kb
Host smart-de36c41a-a81b-40c7-9a7c-87fb0be45399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293332927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4293332927
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2433615472
Short name T788
Test name
Test status
Simulation time 158283858 ps
CPU time 3.21 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:38 PM PDT 24
Peak memory 218000 kb
Host smart-ac78afd3-18b9-4de8-b288-53757d01b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433615472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2433615472
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1797647384
Short name T369
Test name
Test status
Simulation time 102402705 ps
CPU time 2.03 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:42 PM PDT 24
Peak memory 217956 kb
Host smart-d11903e3-2650-4413-9f37-7b651c91a279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797647384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1797647384
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.839709069
Short name T436
Test name
Test status
Simulation time 83460925 ps
CPU time 1.4 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:39 PM PDT 24
Peak memory 218140 kb
Host smart-2f65c281-273e-471f-aeac-ba2009b79d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839709069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.839709069
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1131838779
Short name T184
Test name
Test status
Simulation time 140466036 ps
CPU time 1.02 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 216748 kb
Host smart-489a0446-da57-469c-85ec-b00f1ead57de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131838779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1131838779
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.566021777
Short name T640
Test name
Test status
Simulation time 43514063 ps
CPU time 1.48 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 217788 kb
Host smart-f23349a2-932a-43ae-94cb-fb47e3a59f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566021777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.566021777
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2646908
Short name T30
Test name
Test status
Simulation time 42818508 ps
CPU time 1.13 seconds
Started Mar 17 12:44:36 PM PDT 24
Finished Mar 17 12:44:38 PM PDT 24
Peak memory 216764 kb
Host smart-f7363ab8-2415-4968-8fda-b76421891af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2646908
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.583584760
Short name T326
Test name
Test status
Simulation time 48645432 ps
CPU time 1.45 seconds
Started Mar 17 12:44:46 PM PDT 24
Finished Mar 17 12:44:47 PM PDT 24
Peak memory 217032 kb
Host smart-54b91335-353a-4bae-a0f8-77ce89521a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583584760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.583584760
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1716404326
Short name T370
Test name
Test status
Simulation time 79635013 ps
CPU time 1.04 seconds
Started Mar 17 12:44:41 PM PDT 24
Finished Mar 17 12:44:42 PM PDT 24
Peak memory 216768 kb
Host smart-68beeb06-36c4-4e9e-8f10-e89caef908ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716404326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1716404326
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3710537154
Short name T559
Test name
Test status
Simulation time 24838528 ps
CPU time 1.27 seconds
Started Mar 17 12:43:14 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 215716 kb
Host smart-551e907e-4690-4474-8bbd-3b3044eac7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710537154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3710537154
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3395569783
Short name T495
Test name
Test status
Simulation time 54536092 ps
CPU time 0.88 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 206872 kb
Host smart-e8c4abd7-f4c7-4601-858d-9e52c3ba1ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395569783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3395569783
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2084202516
Short name T59
Test name
Test status
Simulation time 11864120 ps
CPU time 0.85 seconds
Started Mar 17 12:43:20 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 215968 kb
Host smart-2e6cd932-17af-4b81-bc89-4f1600871d7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084202516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2084202516
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3777242867
Short name T216
Test name
Test status
Simulation time 91359460 ps
CPU time 1.06 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 216532 kb
Host smart-1afb0d9f-2bcd-4ede-b49a-5b2c6dce8396
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777242867 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3777242867
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2172395032
Short name T80
Test name
Test status
Simulation time 24042928 ps
CPU time 1.26 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 229852 kb
Host smart-839e7c6f-2a06-491d-9078-ec99869a811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172395032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2172395032
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3125876550
Short name T455
Test name
Test status
Simulation time 61698331 ps
CPU time 1.34 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 216728 kb
Host smart-e6e5dd9b-a8f9-4551-913f-1f6b6cab7b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125876550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3125876550
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.166177440
Short name T348
Test name
Test status
Simulation time 21885499 ps
CPU time 1.09 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 215620 kb
Host smart-c676643c-6849-443c-8fa4-04a6132b9b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166177440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.166177440
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1790047796
Short name T367
Test name
Test status
Simulation time 18632822 ps
CPU time 0.98 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215192 kb
Host smart-fc1f8d26-f885-46c1-b6f8-db38dfe8a9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790047796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1790047796
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2008636136
Short name T208
Test name
Test status
Simulation time 232924520 ps
CPU time 1.39 seconds
Started Mar 17 12:43:22 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 215272 kb
Host smart-f9194eab-b871-4b5c-9cbf-6ef506f8ad5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008636136 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2008636136
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.13114183
Short name T760
Test name
Test status
Simulation time 127352017580 ps
CPU time 759.61 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:55:55 PM PDT 24
Peak memory 223744 kb
Host smart-bb6e195a-6af1-433c-92fd-2504a1a389b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13114183 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.13114183
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.785418751
Short name T618
Test name
Test status
Simulation time 45708884 ps
CPU time 1.44 seconds
Started Mar 17 12:44:39 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 217700 kb
Host smart-edb79cbb-84ab-4d93-90e3-7672cc0e13d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785418751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.785418751
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3172597330
Short name T671
Test name
Test status
Simulation time 308436679 ps
CPU time 1.01 seconds
Started Mar 17 12:44:42 PM PDT 24
Finished Mar 17 12:44:44 PM PDT 24
Peak memory 216500 kb
Host smart-4abb04a1-aac7-49bb-876d-49ff5637ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172597330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3172597330
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.439535907
Short name T599
Test name
Test status
Simulation time 59877377 ps
CPU time 1.13 seconds
Started Mar 17 12:44:44 PM PDT 24
Finished Mar 17 12:44:46 PM PDT 24
Peak memory 217944 kb
Host smart-9f7f63aa-b407-4aff-b24d-a62e040ad1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439535907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.439535907
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1060880933
Short name T429
Test name
Test status
Simulation time 66060367 ps
CPU time 2.41 seconds
Started Mar 17 12:44:44 PM PDT 24
Finished Mar 17 12:44:47 PM PDT 24
Peak memory 219496 kb
Host smart-2868e1c9-a29e-466e-8076-55c03b86d012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060880933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1060880933
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3692059880
Short name T386
Test name
Test status
Simulation time 51512140 ps
CPU time 1.28 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:39 PM PDT 24
Peak memory 216508 kb
Host smart-a97a29cf-5da8-4ef8-9c39-6291f32fedbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692059880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3692059880
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4204941388
Short name T390
Test name
Test status
Simulation time 112032753 ps
CPU time 1.17 seconds
Started Mar 17 12:44:32 PM PDT 24
Finished Mar 17 12:44:34 PM PDT 24
Peak memory 216636 kb
Host smart-db6aa084-1793-4305-9d7e-c3c088d189f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204941388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4204941388
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.451315418
Short name T594
Test name
Test status
Simulation time 90301017 ps
CPU time 1.42 seconds
Started Mar 17 12:44:36 PM PDT 24
Finished Mar 17 12:44:38 PM PDT 24
Peak memory 217960 kb
Host smart-97b3df18-bc93-4763-a628-6584d09ada58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451315418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.451315418
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1147713220
Short name T584
Test name
Test status
Simulation time 149993295 ps
CPU time 0.98 seconds
Started Mar 17 12:44:38 PM PDT 24
Finished Mar 17 12:44:40 PM PDT 24
Peak memory 216572 kb
Host smart-8bfe25d1-7523-4500-8988-e966c3a97522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147713220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1147713220
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4028614897
Short name T809
Test name
Test status
Simulation time 82264413 ps
CPU time 1.2 seconds
Started Mar 17 12:44:35 PM PDT 24
Finished Mar 17 12:44:37 PM PDT 24
Peak memory 216716 kb
Host smart-271cb513-7eff-4c3e-910e-4ad1e5e0e880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028614897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4028614897
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2969907484
Short name T155
Test name
Test status
Simulation time 126804686 ps
CPU time 1.13 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 215636 kb
Host smart-b05583f1-169b-4458-92b2-94e4d63af35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969907484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2969907484
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.109171283
Short name T461
Test name
Test status
Simulation time 289352712 ps
CPU time 0.97 seconds
Started Mar 17 12:42:32 PM PDT 24
Finished Mar 17 12:42:34 PM PDT 24
Peak memory 206044 kb
Host smart-a816da96-309a-468a-927d-2aef09f41242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109171283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.109171283
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3545101237
Short name T100
Test name
Test status
Simulation time 30381221 ps
CPU time 0.85 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:35 PM PDT 24
Peak memory 215532 kb
Host smart-2c14df6f-5ca8-49b7-924e-3edbe0d98c4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545101237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3545101237
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.638652384
Short name T605
Test name
Test status
Simulation time 48266848 ps
CPU time 1.19 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 223944 kb
Host smart-e1f63899-e5d1-41a7-84cf-8e18c41efdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638652384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.638652384
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2390483769
Short name T601
Test name
Test status
Simulation time 45644813 ps
CPU time 1.09 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 216648 kb
Host smart-17d45042-fa91-44fd-b962-0dd02064fa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390483769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2390483769
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.169645813
Short name T583
Test name
Test status
Simulation time 25030106 ps
CPU time 1.19 seconds
Started Mar 17 12:42:36 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 223912 kb
Host smart-e55a8250-0c8b-4a19-a206-9a455e5816f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169645813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.169645813
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4012195735
Short name T22
Test name
Test status
Simulation time 760925658 ps
CPU time 3.54 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 234396 kb
Host smart-6c2e795d-e0b9-4327-8891-8b751b834cec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012195735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4012195735
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3996186695
Short name T419
Test name
Test status
Simulation time 16850170 ps
CPU time 0.98 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 215276 kb
Host smart-e2f2452f-3499-4d73-a6ee-e5db1f67d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996186695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3996186695
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2918428772
Short name T375
Test name
Test status
Simulation time 20083994 ps
CPU time 0.94 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 206040 kb
Host smart-c69c6496-f870-441b-a4e7-b19445bec2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918428772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2918428772
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1677098591
Short name T813
Test name
Test status
Simulation time 425797380433 ps
CPU time 2639.97 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 01:26:36 PM PDT 24
Peak memory 233072 kb
Host smart-cbe9ffa3-2f14-4269-bfa6-c2e9647f1558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677098591 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1677098591
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1631395688
Short name T111
Test name
Test status
Simulation time 29083742 ps
CPU time 1.16 seconds
Started Mar 17 12:43:13 PM PDT 24
Finished Mar 17 12:43:14 PM PDT 24
Peak memory 215844 kb
Host smart-8596b11a-4382-4299-8fb9-7faa2e2b07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631395688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1631395688
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2945043365
Short name T531
Test name
Test status
Simulation time 29557329 ps
CPU time 0.86 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 206076 kb
Host smart-6fcdb4c0-ab06-4880-a773-c9d48c9e6cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945043365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2945043365
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2888380806
Short name T756
Test name
Test status
Simulation time 48798916 ps
CPU time 0.84 seconds
Started Mar 17 12:43:22 PM PDT 24
Finished Mar 17 12:43:23 PM PDT 24
Peak memory 215832 kb
Host smart-e8412582-0a6d-4afb-b8dc-d8b8549dca6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888380806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2888380806
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.692926998
Short name T415
Test name
Test status
Simulation time 38818061 ps
CPU time 0.91 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 217540 kb
Host smart-e242c774-e0c6-43df-945a-1d9aa90c1185
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692926998 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.692926998
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.208646655
Short name T423
Test name
Test status
Simulation time 29334737 ps
CPU time 0.84 seconds
Started Mar 17 12:43:14 PM PDT 24
Finished Mar 17 12:43:20 PM PDT 24
Peak memory 217556 kb
Host smart-5ac77720-a3b9-40f2-b87d-ba39a590ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208646655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.208646655
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2832071255
Short name T692
Test name
Test status
Simulation time 40581725 ps
CPU time 1.33 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 216512 kb
Host smart-c066b0f8-d12d-4400-a7fa-5674d84bc9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832071255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2832071255
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3192786004
Short name T725
Test name
Test status
Simulation time 22696543 ps
CPU time 1.17 seconds
Started Mar 17 12:43:22 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 223928 kb
Host smart-ad159d45-4186-44e3-8ae1-6d607f7414d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192786004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3192786004
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4040109852
Short name T564
Test name
Test status
Simulation time 19971959 ps
CPU time 0.93 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 215316 kb
Host smart-d60e641a-f175-4c76-98e0-5e8e69833918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040109852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4040109852
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1298256656
Short name T338
Test name
Test status
Simulation time 598506966 ps
CPU time 3.69 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 216484 kb
Host smart-0efcd98a-8015-44fd-84dc-6a8debec1bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298256656 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1298256656
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1918438494
Short name T191
Test name
Test status
Simulation time 91401145993 ps
CPU time 731.79 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:55:28 PM PDT 24
Peak memory 219744 kb
Host smart-d079070b-f488-40d4-b8d6-e8da6a1b1805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918438494 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1918438494
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1783064303
Short name T54
Test name
Test status
Simulation time 81165553 ps
CPU time 1.27 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 215592 kb
Host smart-a93652a9-07c2-41a9-842c-ae1913b5847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783064303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1783064303
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1435565937
Short name T402
Test name
Test status
Simulation time 36363582 ps
CPU time 0.94 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 206596 kb
Host smart-c234b6a1-3117-41f9-8bf7-848be0aeebf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435565937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1435565937
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1141032324
Short name T591
Test name
Test status
Simulation time 27200879 ps
CPU time 0.82 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215892 kb
Host smart-534fe536-0088-4fa6-b1d0-5c7b531a62a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141032324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1141032324
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.2625283798
Short name T101
Test name
Test status
Simulation time 29430418 ps
CPU time 0.91 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 218052 kb
Host smart-23878ff6-e4a9-49e4-8c4d-9c103134ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625283798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2625283798
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.274580273
Short name T791
Test name
Test status
Simulation time 56828621 ps
CPU time 1.19 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 216540 kb
Host smart-6a51d6f9-8417-49c9-9647-7e053b50c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274580273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.274580273
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1144119744
Short name T138
Test name
Test status
Simulation time 28203099 ps
CPU time 0.82 seconds
Started Mar 17 12:43:13 PM PDT 24
Finished Mar 17 12:43:14 PM PDT 24
Peak memory 215644 kb
Host smart-faa7fef1-3177-4d50-9f7a-8b5bc5f66db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144119744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1144119744
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3723636984
Short name T320
Test name
Test status
Simulation time 31376637 ps
CPU time 0.88 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 215348 kb
Host smart-d0022e2f-29e9-4e92-ac61-15226ae720d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723636984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3723636984
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1215828622
Short name T505
Test name
Test status
Simulation time 46579090 ps
CPU time 1.41 seconds
Started Mar 17 12:43:15 PM PDT 24
Finished Mar 17 12:43:16 PM PDT 24
Peak memory 215332 kb
Host smart-a97102a3-f65e-4a1f-bcfa-64481038d1c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215828622 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1215828622
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2395961322
Short name T688
Test name
Test status
Simulation time 372070183217 ps
CPU time 2385.93 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 01:23:04 PM PDT 24
Peak memory 230680 kb
Host smart-5c413b4a-e9ef-47e2-83a0-14f38377c0c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395961322 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2395961322
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2862552584
Short name T112
Test name
Test status
Simulation time 36228738 ps
CPU time 1.09 seconds
Started Mar 17 12:43:21 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 215748 kb
Host smart-37028f2d-0f1e-4bd3-972a-d2a0d10fd2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862552584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2862552584
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.749963082
Short name T445
Test name
Test status
Simulation time 17961609 ps
CPU time 0.88 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 206112 kb
Host smart-af4a2b0d-b061-4291-9c66-de42bb134c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749963082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.749963082
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1920669235
Short name T166
Test name
Test status
Simulation time 21818689 ps
CPU time 0.89 seconds
Started Mar 17 12:43:32 PM PDT 24
Finished Mar 17 12:43:33 PM PDT 24
Peak memory 215532 kb
Host smart-26dadc6c-0cec-4234-8ea7-8decd2e8fc33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920669235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1920669235
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1687405556
Short name T396
Test name
Test status
Simulation time 71053287 ps
CPU time 1.07 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 217664 kb
Host smart-162aabae-9dc3-446d-87af-8edc3f885f20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687405556 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1687405556
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.200790509
Short name T412
Test name
Test status
Simulation time 24432589 ps
CPU time 1.18 seconds
Started Mar 17 12:43:42 PM PDT 24
Finished Mar 17 12:43:43 PM PDT 24
Peak memory 217912 kb
Host smart-2cfcbc1a-ccaa-4f3c-8398-980846a3658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200790509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.200790509
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3694602598
Short name T270
Test name
Test status
Simulation time 87413580 ps
CPU time 1.2 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 216792 kb
Host smart-26fd2316-0d05-4bd5-816d-da29f918c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694602598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3694602598
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3253449417
Short name T639
Test name
Test status
Simulation time 22637783 ps
CPU time 1.01 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 215704 kb
Host smart-7e1454cf-32fe-47ff-9855-d962119ef7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253449417 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3253449417
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2344799390
Short name T551
Test name
Test status
Simulation time 18502535 ps
CPU time 1.02 seconds
Started Mar 17 12:43:16 PM PDT 24
Finished Mar 17 12:43:17 PM PDT 24
Peak memory 215244 kb
Host smart-a58e5bba-f028-439f-82f3-abd8bc0a8046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344799390 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2344799390
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1605002458
Short name T724
Test name
Test status
Simulation time 249515569 ps
CPU time 3.18 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 219408 kb
Host smart-f83b7c88-cfbc-409b-8b85-fb4d91047007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605002458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1605002458
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2010264754
Short name T511
Test name
Test status
Simulation time 187780977317 ps
CPU time 1172.75 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 01:02:51 PM PDT 24
Peak memory 224340 kb
Host smart-0430fe1f-c7b5-4e9a-80fe-86331248242c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010264754 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2010264754
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2486989290
Short name T779
Test name
Test status
Simulation time 78567739 ps
CPU time 1.23 seconds
Started Mar 17 12:43:36 PM PDT 24
Finished Mar 17 12:43:37 PM PDT 24
Peak memory 215752 kb
Host smart-bac41c31-5e27-45ae-9f08-5998b0cb6832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486989290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2486989290
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3147473890
Short name T401
Test name
Test status
Simulation time 12487160 ps
CPU time 0.79 seconds
Started Mar 17 12:43:30 PM PDT 24
Finished Mar 17 12:43:31 PM PDT 24
Peak memory 206008 kb
Host smart-14986fa5-287a-49a6-bbdd-a5174a270460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147473890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3147473890
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1461780613
Short name T176
Test name
Test status
Simulation time 13202624 ps
CPU time 0.84 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:20 PM PDT 24
Peak memory 215644 kb
Host smart-f7d526cf-cc81-4361-a200-2b7d9af7ca58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461780613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1461780613
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2096257200
Short name T164
Test name
Test status
Simulation time 35719905 ps
CPU time 1.21 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:20 PM PDT 24
Peak memory 216488 kb
Host smart-b6c787ed-27cd-4f8d-9fb0-6ecb1e4793fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096257200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2096257200
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2553049680
Short name T83
Test name
Test status
Simulation time 31958288 ps
CPU time 0.91 seconds
Started Mar 17 12:43:30 PM PDT 24
Finished Mar 17 12:43:31 PM PDT 24
Peak memory 219084 kb
Host smart-a5d6f29b-b18b-4441-9caf-76a035b104e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553049680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2553049680
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3179013340
Short name T314
Test name
Test status
Simulation time 86018842 ps
CPU time 1.19 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 219564 kb
Host smart-6613bc28-3481-4e28-92bf-57c164498443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179013340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3179013340
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2512290723
Short name T826
Test name
Test status
Simulation time 20627513 ps
CPU time 1 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 215760 kb
Host smart-011f54ea-4dbb-42ce-a04c-8624069fe483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512290723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2512290723
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.908667305
Short name T404
Test name
Test status
Simulation time 46424339 ps
CPU time 0.91 seconds
Started Mar 17 12:43:42 PM PDT 24
Finished Mar 17 12:43:43 PM PDT 24
Peak memory 215256 kb
Host smart-614c8c73-65c6-4ee8-b244-bc3769219005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908667305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.908667305
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1743193101
Short name T312
Test name
Test status
Simulation time 127592994 ps
CPU time 2.9 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 216620 kb
Host smart-da1e8b24-8631-466a-b0c5-33b6799c340e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743193101 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1743193101
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.404727583
Short name T549
Test name
Test status
Simulation time 44645032450 ps
CPU time 1114.73 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 01:01:52 PM PDT 24
Peak memory 220292 kb
Host smart-7f0109f4-0e6f-4477-a89f-a462dfeb6ace
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404727583 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.404727583
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3843745499
Short name T177
Test name
Test status
Simulation time 81573605 ps
CPU time 1.19 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 215636 kb
Host smart-7cc5b6d9-03ab-4644-8bc0-12dd31c73427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843745499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3843745499
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1604643164
Short name T702
Test name
Test status
Simulation time 50635466 ps
CPU time 0.82 seconds
Started Mar 17 12:43:32 PM PDT 24
Finished Mar 17 12:43:33 PM PDT 24
Peak memory 206440 kb
Host smart-93ee7a76-72c9-4c49-8cb2-eb9be807b280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604643164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1604643164
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.401164319
Short name T181
Test name
Test status
Simulation time 16702540 ps
CPU time 0.81 seconds
Started Mar 17 12:43:20 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 215424 kb
Host smart-bdfd7bcc-3912-43c2-874a-659b5305f470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401164319 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.401164319
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2746768834
Short name T84
Test name
Test status
Simulation time 24069321 ps
CPU time 1.06 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 216376 kb
Host smart-dda497b1-3b52-4e71-83c5-f2e87de82b7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746768834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2746768834
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3502496472
Short name T824
Test name
Test status
Simulation time 20247244 ps
CPU time 0.97 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 218044 kb
Host smart-0b491861-37c5-4615-b005-8f96dbf1796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502496472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3502496472
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3743008926
Short name T60
Test name
Test status
Simulation time 40188981 ps
CPU time 1.21 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 217872 kb
Host smart-4cb2a3e9-f129-4831-a623-1c7c7ab70bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743008926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3743008926
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2246651945
Short name T472
Test name
Test status
Simulation time 32043825 ps
CPU time 0.83 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 215668 kb
Host smart-92cdd320-e263-46c9-a7dc-b018650ef4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246651945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2246651945
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.494157082
Short name T717
Test name
Test status
Simulation time 19026280 ps
CPU time 0.94 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:43:29 PM PDT 24
Peak memory 215388 kb
Host smart-96e362fb-4cf6-4a8b-9ebf-a336377b2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494157082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.494157082
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1635924337
Short name T664
Test name
Test status
Simulation time 76079470 ps
CPU time 1.37 seconds
Started Mar 17 12:43:44 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 207176 kb
Host smart-33fba4d7-b42f-482d-978f-e34ee42a2736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635924337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1635924337
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3444193135
Short name T187
Test name
Test status
Simulation time 167401410699 ps
CPU time 1543.21 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 01:09:01 PM PDT 24
Peak memory 226244 kb
Host smart-3d45da7f-f345-4839-8b1d-7d5d5f94e4c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444193135 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3444193135
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.330642808
Short name T325
Test name
Test status
Simulation time 63984340 ps
CPU time 0.87 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 206628 kb
Host smart-24452e85-27d7-4428-973f-aa85999df85e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330642808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.330642808
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2286903874
Short name T94
Test name
Test status
Simulation time 123598928 ps
CPU time 1.13 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:20 PM PDT 24
Peak memory 216596 kb
Host smart-9fb1d05b-8afb-4872-88e1-bab4612a3f97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286903874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2286903874
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2792122930
Short name T167
Test name
Test status
Simulation time 100562060 ps
CPU time 1.09 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:29 PM PDT 24
Peak memory 219328 kb
Host smart-bee9f534-3ff1-4cbf-8006-9ed33e36e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792122930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2792122930
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1127968105
Short name T780
Test name
Test status
Simulation time 88419761 ps
CPU time 1.45 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:43:30 PM PDT 24
Peak memory 218448 kb
Host smart-1e519697-7698-4054-9853-cd8a087d2991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127968105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1127968105
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1509934334
Short name T718
Test name
Test status
Simulation time 30332722 ps
CPU time 0.89 seconds
Started Mar 17 12:43:30 PM PDT 24
Finished Mar 17 12:43:31 PM PDT 24
Peak memory 215784 kb
Host smart-28a0ea46-5e31-4e9c-b349-8b40de517bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509934334 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1509934334
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2129706419
Short name T652
Test name
Test status
Simulation time 42645418 ps
CPU time 0.88 seconds
Started Mar 17 12:43:17 PM PDT 24
Finished Mar 17 12:43:18 PM PDT 24
Peak memory 215276 kb
Host smart-4c2b6c22-d179-4d21-9c79-8bf2fb3c460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129706419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2129706419
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2492724310
Short name T493
Test name
Test status
Simulation time 389228039 ps
CPU time 4.09 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:23 PM PDT 24
Peak memory 216716 kb
Host smart-f193893c-c75f-417b-84d8-8bb4ca918ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492724310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2492724310
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2844323867
Short name T693
Test name
Test status
Simulation time 286480659564 ps
CPU time 1663.03 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 01:11:09 PM PDT 24
Peak memory 224324 kb
Host smart-f203e249-8cf7-4583-84cc-036c337095fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844323867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2844323867
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1399732371
Short name T290
Test name
Test status
Simulation time 23669531 ps
CPU time 1.16 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:43:30 PM PDT 24
Peak memory 215592 kb
Host smart-dd0538b3-34aa-4104-99bd-7bd6b1e5fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399732371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1399732371
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3961389661
Short name T41
Test name
Test status
Simulation time 36738790 ps
CPU time 0.87 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:44 PM PDT 24
Peak memory 205968 kb
Host smart-a47b7a38-02c7-4925-95b8-72deeaa2d9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961389661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3961389661
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1220435616
Short name T116
Test name
Test status
Simulation time 20517993 ps
CPU time 0.84 seconds
Started Mar 17 12:43:20 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 215992 kb
Host smart-b53c1abc-0da0-4efe-a285-618238e1ae17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220435616 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1220435616
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.81737149
Short name T450
Test name
Test status
Simulation time 60469062 ps
CPU time 1.02 seconds
Started Mar 17 12:43:33 PM PDT 24
Finished Mar 17 12:43:34 PM PDT 24
Peak memory 216544 kb
Host smart-c2e0273a-a24e-4cf1-be1a-75def493ac3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81737149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_dis
able_auto_req_mode.81737149
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1549072090
Short name T88
Test name
Test status
Simulation time 103168203 ps
CPU time 1.24 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 232224 kb
Host smart-14a8fd9d-1416-4839-a5d7-37b4dc19b42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549072090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1549072090
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4253162081
Short name T283
Test name
Test status
Simulation time 131283971 ps
CPU time 2.82 seconds
Started Mar 17 12:43:36 PM PDT 24
Finished Mar 17 12:43:39 PM PDT 24
Peak memory 216788 kb
Host smart-80f9b9f7-becc-4234-8b74-a5a40d907295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253162081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4253162081
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.271352770
Short name T145
Test name
Test status
Simulation time 21378322 ps
CPU time 1.06 seconds
Started Mar 17 12:43:37 PM PDT 24
Finished Mar 17 12:43:38 PM PDT 24
Peak memory 215528 kb
Host smart-83907cb5-3c2d-4d20-95f5-22bea8e89b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271352770 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.271352770
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3011194568
Short name T739
Test name
Test status
Simulation time 33963950 ps
CPU time 0.94 seconds
Started Mar 17 12:43:18 PM PDT 24
Finished Mar 17 12:43:19 PM PDT 24
Peak memory 215324 kb
Host smart-23bed127-c3f8-4277-b267-b27e724e060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011194568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3011194568
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.839752104
Short name T514
Test name
Test status
Simulation time 672217768 ps
CPU time 3.06 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 216776 kb
Host smart-1570beca-ef8f-4c53-b91f-1484fe091675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839752104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.839752104
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1323328690
Short name T192
Test name
Test status
Simulation time 149452713557 ps
CPU time 1595.64 seconds
Started Mar 17 12:43:21 PM PDT 24
Finished Mar 17 01:09:57 PM PDT 24
Peak memory 224364 kb
Host smart-8d8c4e84-6530-41c0-8dc6-2d7d43e03fb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323328690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1323328690
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.549854131
Short name T104
Test name
Test status
Simulation time 48062696 ps
CPU time 1.19 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:29 PM PDT 24
Peak memory 215716 kb
Host smart-fa3b606f-48a0-45a9-aefa-0fdaf44c4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549854131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.549854131
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3374709646
Short name T346
Test name
Test status
Simulation time 42570965 ps
CPU time 0.87 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 206000 kb
Host smart-e7e4b885-a732-4eda-81e6-56322fbf188c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374709646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3374709646
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1740010692
Short name T393
Test name
Test status
Simulation time 84113629 ps
CPU time 0.85 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:48 PM PDT 24
Peak memory 215420 kb
Host smart-133ecd02-01f0-4ca6-a23f-af76a284c1b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740010692 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1740010692
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.1668521934
Short name T341
Test name
Test status
Simulation time 21823343 ps
CPU time 0.9 seconds
Started Mar 17 12:43:20 PM PDT 24
Finished Mar 17 12:43:21 PM PDT 24
Peak memory 217808 kb
Host smart-46668845-a6d8-418b-be11-ae34050dab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668521934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1668521934
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1897280058
Short name T324
Test name
Test status
Simulation time 109000230 ps
CPU time 1.47 seconds
Started Mar 17 12:43:22 PM PDT 24
Finished Mar 17 12:43:23 PM PDT 24
Peak memory 218236 kb
Host smart-16ff78dc-5167-4259-86d3-d179bf09b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897280058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1897280058
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.509410700
Short name T368
Test name
Test status
Simulation time 29208261 ps
CPU time 1.03 seconds
Started Mar 17 12:43:36 PM PDT 24
Finished Mar 17 12:43:37 PM PDT 24
Peak memory 223912 kb
Host smart-d3f8ec00-1831-4db7-a6cb-e5d6dc06fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509410700 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.509410700
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3054841825
Short name T140
Test name
Test status
Simulation time 27492335 ps
CPU time 0.95 seconds
Started Mar 17 12:43:30 PM PDT 24
Finished Mar 17 12:43:31 PM PDT 24
Peak memory 215296 kb
Host smart-b777456a-3b47-4347-89f4-30d644984fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054841825 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3054841825
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2039730349
Short name T757
Test name
Test status
Simulation time 315787974 ps
CPU time 6.14 seconds
Started Mar 17 12:43:20 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 216568 kb
Host smart-f5f8b66c-afa5-4798-8076-4105a36919ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039730349 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2039730349
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2406957975
Short name T651
Test name
Test status
Simulation time 62267127849 ps
CPU time 1309.89 seconds
Started Mar 17 12:43:41 PM PDT 24
Finished Mar 17 01:05:31 PM PDT 24
Peak memory 221380 kb
Host smart-c56fe7cb-b706-4b96-8a67-93980d214901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406957975 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2406957975
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.1732137557
Short name T379
Test name
Test status
Simulation time 21691691 ps
CPU time 0.84 seconds
Started Mar 17 12:43:33 PM PDT 24
Finished Mar 17 12:43:33 PM PDT 24
Peak memory 206616 kb
Host smart-6ce9870a-b707-4e3c-a300-0263fc894736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732137557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1732137557
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3898987673
Short name T25
Test name
Test status
Simulation time 32558403 ps
CPU time 0.81 seconds
Started Mar 17 12:43:44 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 215496 kb
Host smart-7aee2bfd-cdc4-4247-a5f6-352e91c5305c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898987673 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3898987673
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1650299993
Short name T492
Test name
Test status
Simulation time 77462545 ps
CPU time 1.28 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 12:43:20 PM PDT 24
Peak memory 216400 kb
Host smart-52493bfb-0e9f-415d-b9f3-b29d15c4efe4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650299993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1650299993
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4267348488
Short name T126
Test name
Test status
Simulation time 19074863 ps
CPU time 1.06 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 218072 kb
Host smart-801ad078-d825-4ae8-a2b3-84a0c6487c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267348488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4267348488
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1620464615
Short name T399
Test name
Test status
Simulation time 36843727 ps
CPU time 1.39 seconds
Started Mar 17 12:43:39 PM PDT 24
Finished Mar 17 12:43:40 PM PDT 24
Peak memory 218016 kb
Host smart-ef6ead35-0a15-4c10-b13f-a5ad43bd0163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620464615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1620464615
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1275720818
Short name T657
Test name
Test status
Simulation time 24642029 ps
CPU time 0.88 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:43:29 PM PDT 24
Peak memory 215500 kb
Host smart-a7cbe666-3ae5-4351-aebc-4b98cbb61bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275720818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1275720818
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1543498204
Short name T311
Test name
Test status
Simulation time 15830876 ps
CPU time 0.94 seconds
Started Mar 17 12:43:21 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 215372 kb
Host smart-0b7a528c-03d7-4ebc-86b3-36d60e139cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543498204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1543498204
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.855126407
Short name T457
Test name
Test status
Simulation time 1353191876 ps
CPU time 2.69 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:31 PM PDT 24
Peak memory 216860 kb
Host smart-5adc9acc-64d0-499b-8bc6-0899f9420f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855126407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.855126407
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1627884713
Short name T485
Test name
Test status
Simulation time 210804511976 ps
CPU time 2704.88 seconds
Started Mar 17 12:43:19 PM PDT 24
Finished Mar 17 01:28:24 PM PDT 24
Peak memory 233100 kb
Host smart-8e77f3a2-1391-40ae-bc7b-ca4cc414ef20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627884713 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1627884713
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert_test.3672453724
Short name T373
Test name
Test status
Simulation time 21681344 ps
CPU time 0.96 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:27 PM PDT 24
Peak memory 206020 kb
Host smart-3972179b-d687-44da-9423-abcd4e557af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672453724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3672453724
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3032533291
Short name T441
Test name
Test status
Simulation time 82329746 ps
CPU time 0.78 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:27 PM PDT 24
Peak memory 215492 kb
Host smart-cf3b7ddb-ae7e-4b78-8b57-a204b1af9367
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032533291 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3032533291
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.2719335714
Short name T576
Test name
Test status
Simulation time 29824870 ps
CPU time 0.84 seconds
Started Mar 17 12:43:23 PM PDT 24
Finished Mar 17 12:43:24 PM PDT 24
Peak memory 218420 kb
Host smart-93a4e3f4-0e49-4a57-8845-97db252679c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719335714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2719335714
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1290252372
Short name T574
Test name
Test status
Simulation time 37244478 ps
CPU time 1.14 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:43:29 PM PDT 24
Peak memory 216864 kb
Host smart-93907b11-ff5c-4e62-8e3d-411a792fb77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290252372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1290252372
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1001201907
Short name T58
Test name
Test status
Simulation time 49188034 ps
CPU time 0.83 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:27 PM PDT 24
Peak memory 215288 kb
Host smart-9e0d663f-7d41-45e3-aa92-6b139cec51a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001201907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1001201907
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.42577567
Short name T633
Test name
Test status
Simulation time 24741427 ps
CPU time 0.88 seconds
Started Mar 17 12:43:27 PM PDT 24
Finished Mar 17 12:43:28 PM PDT 24
Peak memory 215232 kb
Host smart-fac2fa31-3d52-4cc5-b1fc-642e6c021edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42577567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.42577567
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4243286775
Short name T478
Test name
Test status
Simulation time 518622871 ps
CPU time 5.14 seconds
Started Mar 17 12:43:41 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 220112 kb
Host smart-bd3c2084-2bee-401d-80e5-68b6e89a7086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243286775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4243286775
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1669229406
Short name T771
Test name
Test status
Simulation time 103651505518 ps
CPU time 527.29 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:52:16 PM PDT 24
Peak memory 219948 kb
Host smart-68e988d1-878b-466a-af34-3a13ed973da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669229406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1669229406
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2918584554
Short name T707
Test name
Test status
Simulation time 56233234 ps
CPU time 1.34 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 215748 kb
Host smart-d71671eb-81ff-43ee-a719-477b48f4d57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918584554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2918584554
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.410127932
Short name T670
Test name
Test status
Simulation time 37154012 ps
CPU time 0.84 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:35 PM PDT 24
Peak memory 205656 kb
Host smart-966849f1-ebce-498d-835e-713c4da6d5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410127932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.410127932
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1280034966
Short name T162
Test name
Test status
Simulation time 36471249 ps
CPU time 0.8 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:35 PM PDT 24
Peak memory 215876 kb
Host smart-88f85f99-e303-454e-bb1f-8621fac4d235
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280034966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1280034966
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3944683667
Short name T811
Test name
Test status
Simulation time 66587418 ps
CPU time 1.14 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:39 PM PDT 24
Peak memory 216360 kb
Host smart-859560ba-d920-445e-ab24-cfa1f2e027b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944683667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3944683667
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1671861852
Short name T697
Test name
Test status
Simulation time 35628918 ps
CPU time 1.06 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 231124 kb
Host smart-405aeda4-32f8-4c8e-89c6-cbf4a74daefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671861852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1671861852
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1877930803
Short name T609
Test name
Test status
Simulation time 97296693 ps
CPU time 2.15 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 219560 kb
Host smart-e67834dd-fc41-47ad-829b-169d865d4a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877930803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1877930803
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3983977221
Short name T146
Test name
Test status
Simulation time 39629040 ps
CPU time 0.85 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 215564 kb
Host smart-e6b65d43-b432-41f6-b245-5a2e3448f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983977221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3983977221
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1134135899
Short name T292
Test name
Test status
Simulation time 16240445 ps
CPU time 0.94 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 207004 kb
Host smart-40f22672-88ec-4aec-adad-1938552d15f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134135899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1134135899
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3997449824
Short name T608
Test name
Test status
Simulation time 238593814 ps
CPU time 0.89 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 215064 kb
Host smart-1f7ede43-d89b-49ca-850c-796ee2a8e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997449824 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3997449824
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3430553100
Short name T413
Test name
Test status
Simulation time 88124788 ps
CPU time 2.17 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 216564 kb
Host smart-e12a67f6-bb91-485b-a10e-1bada13a5eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430553100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3430553100
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1273562052
Short name T793
Test name
Test status
Simulation time 65400121433 ps
CPU time 730.67 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:54:46 PM PDT 24
Peak memory 218008 kb
Host smart-d050589a-1ff0-4660-8d79-df8a2e868353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273562052 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1273562052
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.293633765
Short name T299
Test name
Test status
Simulation time 75150315 ps
CPU time 1.22 seconds
Started Mar 17 12:43:38 PM PDT 24
Finished Mar 17 12:43:39 PM PDT 24
Peak memory 215720 kb
Host smart-0897af35-65b9-411f-aada-80b155304119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293633765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.293633765
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1471766532
Short name T383
Test name
Test status
Simulation time 26049357 ps
CPU time 1.07 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:28 PM PDT 24
Peak memory 206140 kb
Host smart-eac423e9-db32-4b1a-89a3-503d8f7efcf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471766532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1471766532
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1585707280
Short name T99
Test name
Test status
Simulation time 19567856 ps
CPU time 0.87 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 215488 kb
Host smart-bb286b3c-578c-467b-b13a-57fa3a32b0b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585707280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1585707280
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1034982642
Short name T76
Test name
Test status
Simulation time 230628841 ps
CPU time 1.15 seconds
Started Mar 17 12:43:44 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 216508 kb
Host smart-c0f7424a-73c7-4759-873a-c66fa53ce2c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034982642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1034982642
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1830796246
Short name T389
Test name
Test status
Simulation time 26987495 ps
CPU time 0.8 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 217512 kb
Host smart-d95d74b2-08b0-4429-b97a-6289c27fb226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830796246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1830796246
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2355737581
Short name T592
Test name
Test status
Simulation time 112660963 ps
CPU time 1.89 seconds
Started Mar 17 12:43:35 PM PDT 24
Finished Mar 17 12:43:37 PM PDT 24
Peak memory 216804 kb
Host smart-2bfac480-c26c-4911-8998-36b25932ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355737581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2355737581
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3704404687
Short name T400
Test name
Test status
Simulation time 42103896 ps
CPU time 0.88 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 215624 kb
Host smart-a0ce5448-3f99-4739-9b51-df1c89b36f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704404687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3704404687
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2580297692
Short name T712
Test name
Test status
Simulation time 16445961 ps
CPU time 0.95 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:27 PM PDT 24
Peak memory 215232 kb
Host smart-639067b9-f98e-43a7-ac24-ba3477617b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580297692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2580297692
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.766937261
Short name T50
Test name
Test status
Simulation time 65867810 ps
CPU time 1.21 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 215372 kb
Host smart-5d363e1a-10ae-46aa-a08d-4d360ce15f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766937261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.766937261
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3456717306
Short name T5
Test name
Test status
Simulation time 96767041955 ps
CPU time 2098.72 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 01:18:24 PM PDT 24
Peak memory 227092 kb
Host smart-966d7fa1-ded4-41ba-b283-29f9ff016324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456717306 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3456717306
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3282150466
Short name T151
Test name
Test status
Simulation time 68633646 ps
CPU time 1.08 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:51 PM PDT 24
Peak memory 215596 kb
Host smart-67ed5afa-e21c-4ef8-ae3c-a68f0c59b42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282150466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3282150466
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3457257702
Short name T705
Test name
Test status
Simulation time 56317424 ps
CPU time 0.96 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:29 PM PDT 24
Peak memory 206128 kb
Host smart-1571b07c-a559-4e26-acc5-17d595cde8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457257702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3457257702
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3633258637
Short name T526
Test name
Test status
Simulation time 18083791 ps
CPU time 0.9 seconds
Started Mar 17 12:43:44 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 216028 kb
Host smart-5757249e-9546-4a65-9f3e-5813aa065d7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633258637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3633258637
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.2293936291
Short name T778
Test name
Test status
Simulation time 20234370 ps
CPU time 0.91 seconds
Started Mar 17 12:43:39 PM PDT 24
Finished Mar 17 12:43:40 PM PDT 24
Peak memory 218252 kb
Host smart-5597c2e9-b1ed-49c2-8da7-97e2dcd549bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293936291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2293936291
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.999207750
Short name T484
Test name
Test status
Simulation time 353316872 ps
CPU time 3.52 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 218008 kb
Host smart-b1321ae5-3a4a-46b0-9416-ed84bf788900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999207750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.999207750
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1267853199
Short name T148
Test name
Test status
Simulation time 29156113 ps
CPU time 0.86 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:26 PM PDT 24
Peak memory 215800 kb
Host smart-b1ec1a73-0aad-42b8-b6a4-31acc9f25102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267853199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1267853199
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3674903239
Short name T468
Test name
Test status
Simulation time 48396918 ps
CPU time 0.9 seconds
Started Mar 17 12:43:45 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 215292 kb
Host smart-d145efe5-8c51-4af1-a907-50be9a967ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674903239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3674903239
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1589342313
Short name T817
Test name
Test status
Simulation time 905771410 ps
CPU time 4.98 seconds
Started Mar 17 12:43:25 PM PDT 24
Finished Mar 17 12:43:30 PM PDT 24
Peak memory 219356 kb
Host smart-b7c62e4d-41a4-438d-b18e-045ee84e469b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589342313 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1589342313
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.275142602
Short name T764
Test name
Test status
Simulation time 48980973180 ps
CPU time 1232.97 seconds
Started Mar 17 12:43:40 PM PDT 24
Finished Mar 17 01:04:13 PM PDT 24
Peak memory 222492 kb
Host smart-b807005f-354d-4ed4-ba26-60279191d323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275142602 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.275142602
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3713319
Short name T624
Test name
Test status
Simulation time 34364193 ps
CPU time 1.26 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:28 PM PDT 24
Peak memory 215672 kb
Host smart-ed7c07e8-b5fc-405f-a267-14465a58ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3713319
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.619801258
Short name T354
Test name
Test status
Simulation time 37347972 ps
CPU time 0.81 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 205920 kb
Host smart-9f2cdc39-8b70-4b62-93ce-b91b165bc213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619801258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.619801258
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3353742097
Short name T123
Test name
Test status
Simulation time 34158721 ps
CPU time 0.82 seconds
Started Mar 17 12:43:27 PM PDT 24
Finished Mar 17 12:43:28 PM PDT 24
Peak memory 215952 kb
Host smart-7d654ce5-70ab-4397-97d7-acf80691b998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353742097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3353742097
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.914786982
Short name T131
Test name
Test status
Simulation time 22685668 ps
CPU time 0.95 seconds
Started Mar 17 12:43:41 PM PDT 24
Finished Mar 17 12:43:43 PM PDT 24
Peak memory 217872 kb
Host smart-84709d9e-1811-4560-aa3a-c99e8270b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914786982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.914786982
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2199962912
Short name T762
Test name
Test status
Simulation time 286829256 ps
CPU time 3.52 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 218372 kb
Host smart-83dfad95-a0b7-4e77-9322-10242cf474ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199962912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2199962912
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1059655483
Short name T556
Test name
Test status
Simulation time 22433394 ps
CPU time 1.12 seconds
Started Mar 17 12:43:36 PM PDT 24
Finished Mar 17 12:43:37 PM PDT 24
Peak memory 215668 kb
Host smart-a0ea0744-e2de-4049-b668-55405a0724a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059655483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1059655483
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1351764541
Short name T438
Test name
Test status
Simulation time 26869650 ps
CPU time 0.92 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 215292 kb
Host smart-c2743f6d-fda8-45d9-91de-3d00df1f3b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351764541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1351764541
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2802149613
Short name T309
Test name
Test status
Simulation time 85395997 ps
CPU time 2.05 seconds
Started Mar 17 12:43:26 PM PDT 24
Finished Mar 17 12:43:28 PM PDT 24
Peak memory 216444 kb
Host smart-6195277a-984c-4ab0-92d4-24bac1b45dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802149613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2802149613
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.640147887
Short name T285
Test name
Test status
Simulation time 25422445427 ps
CPU time 646.69 seconds
Started Mar 17 12:43:28 PM PDT 24
Finished Mar 17 12:54:15 PM PDT 24
Peak memory 220200 kb
Host smart-7fa27bf5-ea7b-42b0-845f-a6bbef49d5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640147887 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.640147887
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1514527302
Short name T295
Test name
Test status
Simulation time 44142637 ps
CPU time 1.19 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:44 PM PDT 24
Peak memory 215652 kb
Host smart-fb529388-f325-4d38-8c24-b3b6d2f9f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514527302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1514527302
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2231358274
Short name T43
Test name
Test status
Simulation time 25921242 ps
CPU time 0.84 seconds
Started Mar 17 12:43:44 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 206832 kb
Host smart-22cf3897-22a8-4935-8d04-e37b20265ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231358274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2231358274
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.921025239
Short name T546
Test name
Test status
Simulation time 29173518 ps
CPU time 0.84 seconds
Started Mar 17 12:43:38 PM PDT 24
Finished Mar 17 12:43:39 PM PDT 24
Peak memory 215900 kb
Host smart-7925e340-7749-41a2-9f84-fe893bb203af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921025239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.921025239
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1557609039
Short name T695
Test name
Test status
Simulation time 34073851 ps
CPU time 1.22 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:56 PM PDT 24
Peak memory 216548 kb
Host smart-ad6fe47c-b7c9-43bb-a69a-f8a02f5088b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557609039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1557609039
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2133675360
Short name T120
Test name
Test status
Simulation time 28218805 ps
CPU time 0.97 seconds
Started Mar 17 12:43:38 PM PDT 24
Finished Mar 17 12:43:39 PM PDT 24
Peak memory 231076 kb
Host smart-fbab3e4b-c04a-4557-a147-15d789c9bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133675360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2133675360
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.637293974
Short name T632
Test name
Test status
Simulation time 121494792 ps
CPU time 2.68 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 217868 kb
Host smart-a76f6bf5-90fd-4beb-9bbe-32916fc493df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637293974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.637293974
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.778357897
Short name T24
Test name
Test status
Simulation time 28272798 ps
CPU time 0.96 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 215828 kb
Host smart-04a78b3f-b6b5-4400-9397-dcfd80ce0243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778357897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.778357897
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3353194909
Short name T512
Test name
Test status
Simulation time 20798818 ps
CPU time 0.88 seconds
Started Mar 17 12:43:29 PM PDT 24
Finished Mar 17 12:43:30 PM PDT 24
Peak memory 215284 kb
Host smart-4b96a93e-9b17-4278-9333-4a8488ebd7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353194909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3353194909
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3844162043
Short name T486
Test name
Test status
Simulation time 114755845 ps
CPU time 2.54 seconds
Started Mar 17 12:43:32 PM PDT 24
Finished Mar 17 12:43:35 PM PDT 24
Peak memory 218984 kb
Host smart-67c1bb3c-90a0-41b9-bf09-ca4f20ba9b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844162043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3844162043
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4216664758
Short name T606
Test name
Test status
Simulation time 180129998605 ps
CPU time 2137.28 seconds
Started Mar 17 12:43:36 PM PDT 24
Finished Mar 17 01:19:14 PM PDT 24
Peak memory 226396 kb
Host smart-bc7cb5c1-8d72-4678-9f67-c89e697eb525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216664758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4216664758
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert_test.106896580
Short name T425
Test name
Test status
Simulation time 15827823 ps
CPU time 0.88 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:44 PM PDT 24
Peak memory 206896 kb
Host smart-4f9b40c9-1b83-49db-b7b3-705f45b182f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106896580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.106896580
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1429144084
Short name T168
Test name
Test status
Simulation time 16326103 ps
CPU time 0.91 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 215932 kb
Host smart-56b6a42c-5e94-414f-b609-1e10e1222197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429144084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1429144084
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.929394480
Short name T108
Test name
Test status
Simulation time 45634802 ps
CPU time 1.19 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 233412 kb
Host smart-14718339-bbbe-48bf-8160-5e5eb84561cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929394480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.929394480
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2544584525
Short name T435
Test name
Test status
Simulation time 54604004 ps
CPU time 1.64 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 217940 kb
Host smart-8ca5c0aa-475c-4e58-9aae-d0d3efc1cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544584525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2544584525
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.17257826
Short name T65
Test name
Test status
Simulation time 25023723 ps
CPU time 0.91 seconds
Started Mar 17 12:43:45 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 215572 kb
Host smart-64ffdaaf-087d-45f8-ae70-e4ca88a3f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17257826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.17257826
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.810343420
Short name T317
Test name
Test status
Simulation time 38519799 ps
CPU time 0.85 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 215236 kb
Host smart-e195e51a-e205-412c-b274-4e32162e49c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810343420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.810343420
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.324417580
Short name T631
Test name
Test status
Simulation time 2249475977 ps
CPU time 4.02 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 216628 kb
Host smart-ed8637aa-01fd-41f9-b394-2a6afefa6a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324417580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.324417580
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1102161257
Short name T198
Test name
Test status
Simulation time 136762819586 ps
CPU time 1469.91 seconds
Started Mar 17 12:43:40 PM PDT 24
Finished Mar 17 01:08:10 PM PDT 24
Peak memory 223784 kb
Host smart-e1f4bffe-e5bd-425b-af00-583d16f5234b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102161257 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1102161257
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.298167453
Short name T42
Test name
Test status
Simulation time 29928504 ps
CPU time 0.87 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 206852 kb
Host smart-f380019d-464d-4517-8a97-ecf2fe45b93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298167453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.298167453
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3640311778
Short name T700
Test name
Test status
Simulation time 13963840 ps
CPU time 0.89 seconds
Started Mar 17 12:43:41 PM PDT 24
Finished Mar 17 12:43:42 PM PDT 24
Peak memory 215724 kb
Host smart-67c51642-a183-4e9e-a346-13e8907d938e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640311778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3640311778
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.443410478
Short name T617
Test name
Test status
Simulation time 27152289 ps
CPU time 0.86 seconds
Started Mar 17 12:43:44 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 217520 kb
Host smart-add60f10-f9da-4915-afa6-2dc77bf65c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443410478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.443410478
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3608141404
Short name T371
Test name
Test status
Simulation time 52731335 ps
CPU time 1.13 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:48 PM PDT 24
Peak memory 217600 kb
Host smart-8c705941-91e0-4840-bdbd-ba3400b043b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608141404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3608141404
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2128994996
Short name T48
Test name
Test status
Simulation time 23650548 ps
CPU time 1.17 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 223956 kb
Host smart-2bec184e-804a-4410-80f1-42f2d0a34d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128994996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2128994996
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1151566593
Short name T149
Test name
Test status
Simulation time 51691321 ps
CPU time 0.92 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 215276 kb
Host smart-fe57d42c-0fdf-4dff-ab8a-058915c1b4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151566593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1151566593
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1306179407
Short name T349
Test name
Test status
Simulation time 49578126 ps
CPU time 1.44 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:51 PM PDT 24
Peak memory 215264 kb
Host smart-1646d54a-ae75-4c9b-b1c2-aa0cc4b689bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306179407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1306179407
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2818864127
Short name T193
Test name
Test status
Simulation time 20946885339 ps
CPU time 228.48 seconds
Started Mar 17 12:43:35 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 221184 kb
Host smart-f2f21c2d-3242-4530-a041-3d10544b7597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818864127 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2818864127
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2177147966
Short name T211
Test name
Test status
Simulation time 53968954 ps
CPU time 1.29 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 215696 kb
Host smart-0aa3e4b6-e057-43f7-9f42-39ffca9389ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177147966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2177147966
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1106945865
Short name T572
Test name
Test status
Simulation time 45909146 ps
CPU time 0.85 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 205988 kb
Host smart-7a3da74f-6165-43fc-901f-1e857f6ef05e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106945865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1106945865
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.918346695
Short name T720
Test name
Test status
Simulation time 33014449 ps
CPU time 0.86 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:56 PM PDT 24
Peak memory 216008 kb
Host smart-c906c9a4-c078-4a25-9b48-50f8ab7c96cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918346695 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.918346695
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2997782041
Short name T827
Test name
Test status
Simulation time 23052130 ps
CPU time 1.09 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 217944 kb
Host smart-98e43af8-265c-4c53-bcf2-6080b60d0ac9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997782041 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2997782041
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2261405459
Short name T681
Test name
Test status
Simulation time 66627898 ps
CPU time 0.83 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 217724 kb
Host smart-43838852-322a-4f0f-8936-147a58926603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261405459 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2261405459
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2935202442
Short name T322
Test name
Test status
Simulation time 145990461 ps
CPU time 2.78 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 218512 kb
Host smart-673f8cdb-dd50-48dc-b929-c7f10142ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935202442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2935202442
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3763963187
Short name T536
Test name
Test status
Simulation time 35583059 ps
CPU time 0.83 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 215408 kb
Host smart-acee35f3-c59a-43d1-99c9-21d7b3620118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763963187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3763963187
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3201659655
Short name T392
Test name
Test status
Simulation time 14371336 ps
CPU time 0.96 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 215248 kb
Host smart-ec57bf0f-a558-41cb-a635-873e37bf741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201659655 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3201659655
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4186856664
Short name T159
Test name
Test status
Simulation time 1922890885 ps
CPU time 4.91 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:48 PM PDT 24
Peak memory 216416 kb
Host smart-3f3e5c29-abd2-4d72-816e-c4979493c8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186856664 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4186856664
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1766841839
Short name T417
Test name
Test status
Simulation time 135497114168 ps
CPU time 1559.41 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 01:09:50 PM PDT 24
Peak memory 225016 kb
Host smart-c12cb173-28d6-4891-83ce-85a042d7bdbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766841839 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1766841839
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3368944870
Short name T787
Test name
Test status
Simulation time 80737531 ps
CPU time 1.15 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 215708 kb
Host smart-3ea4e8af-db4f-4eec-be69-7bcea4ac2cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368944870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3368944870
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2944084268
Short name T668
Test name
Test status
Simulation time 18143530 ps
CPU time 0.96 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 206196 kb
Host smart-2fb9dff0-d9e6-434f-bc89-d2b018390a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944084268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2944084268
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2864503928
Short name T507
Test name
Test status
Simulation time 27931708 ps
CPU time 0.82 seconds
Started Mar 17 12:43:45 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 216004 kb
Host smart-4c8aac56-6d7a-4b82-9482-ef2a0ce61706
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864503928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2864503928
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.180164017
Short name T736
Test name
Test status
Simulation time 31159236 ps
CPU time 1.11 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:48 PM PDT 24
Peak memory 220108 kb
Host smart-bdc93401-14ce-47c1-b881-ae77b2f86577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180164017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.180164017
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3969637585
Short name T742
Test name
Test status
Simulation time 98638488 ps
CPU time 1.52 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:45 PM PDT 24
Peak memory 218116 kb
Host smart-89c39d8c-00e4-4542-9047-f2d6383bd16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969637585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3969637585
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1476789677
Short name T822
Test name
Test status
Simulation time 25866909 ps
CPU time 0.96 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:44 PM PDT 24
Peak memory 215816 kb
Host smart-9d008b6e-d17a-4767-9395-588fcc490039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476789677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1476789677
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1293664239
Short name T539
Test name
Test status
Simulation time 29726181 ps
CPU time 0.95 seconds
Started Mar 17 12:43:43 PM PDT 24
Finished Mar 17 12:43:44 PM PDT 24
Peak memory 215344 kb
Host smart-e7b64cdb-6bbe-4476-9611-fe5d7b1a1a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293664239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1293664239
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3315389864
Short name T730
Test name
Test status
Simulation time 253828326 ps
CPU time 4.97 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 216480 kb
Host smart-67715c2c-9a33-4041-9e35-6f580bd0c57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315389864 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3315389864
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2120149496
Short name T805
Test name
Test status
Simulation time 21548305353 ps
CPU time 269.25 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:48:20 PM PDT 24
Peak memory 218000 kb
Host smart-2f7edacf-6076-498b-b2fd-3767738e9f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120149496 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2120149496
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1890592461
Short name T544
Test name
Test status
Simulation time 79524639 ps
CPU time 1.03 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 215672 kb
Host smart-db6a9f8a-6d09-47e0-a5a0-ec3b408960f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890592461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1890592461
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1458526962
Short name T414
Test name
Test status
Simulation time 36091999 ps
CPU time 1 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 206112 kb
Host smart-fadb1839-d8bf-4dc3-a889-90ecc682db47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458526962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1458526962
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.80973924
Short name T98
Test name
Test status
Simulation time 33843863 ps
CPU time 0.83 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:51 PM PDT 24
Peak memory 215528 kb
Host smart-9c3d22f1-fc52-4c88-8253-f91b1978c895
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80973924 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.80973924
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.3660254779
Short name T738
Test name
Test status
Simulation time 26474094 ps
CPU time 1 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 219524 kb
Host smart-454aff0a-114a-489c-b853-e1a300aca427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660254779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3660254779
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2687850879
Short name T272
Test name
Test status
Simulation time 30595488 ps
CPU time 1.34 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:51 PM PDT 24
Peak memory 216876 kb
Host smart-74372f7c-b569-4513-854b-89451fa20edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687850879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2687850879
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3387341021
Short name T63
Test name
Test status
Simulation time 71531898 ps
CPU time 0.82 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 215544 kb
Host smart-8235947f-9205-4806-bfe9-39feb32f14e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387341021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3387341021
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1733490489
Short name T406
Test name
Test status
Simulation time 21625932 ps
CPU time 0.95 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 215340 kb
Host smart-d4657d24-e4fb-4c40-917c-defb403094b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733490489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1733490489
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2411957388
Short name T731
Test name
Test status
Simulation time 526146697 ps
CPU time 2.51 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 216504 kb
Host smart-5d49115a-5ac7-4385-85ba-ee3cbadfeb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411957388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2411957388
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4173696318
Short name T196
Test name
Test status
Simulation time 80701766359 ps
CPU time 1761.74 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 01:13:23 PM PDT 24
Peak memory 224628 kb
Host smart-b19c1df8-93e3-4f66-935c-c7a708e119e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173696318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4173696318
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2581816617
Short name T661
Test name
Test status
Simulation time 124865057 ps
CPU time 1.27 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 215760 kb
Host smart-c0855ee2-97bf-4130-b0dd-d8019030b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581816617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2581816617
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1980180342
Short name T711
Test name
Test status
Simulation time 48922776 ps
CPU time 0.88 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 206896 kb
Host smart-fb024ac0-c01e-4117-8469-f59de41bcdcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980180342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1980180342
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2259500916
Short name T329
Test name
Test status
Simulation time 16910503 ps
CPU time 0.81 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 215932 kb
Host smart-86f25017-4c3b-49d3-aeed-7954ba28da90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259500916 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2259500916
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.695458191
Short name T117
Test name
Test status
Simulation time 31407524 ps
CPU time 0.85 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 218008 kb
Host smart-7d27cf41-1aa7-4e7c-bb03-844275bf8bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695458191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.695458191
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1365093334
Short name T665
Test name
Test status
Simulation time 82416057 ps
CPU time 1.47 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 218020 kb
Host smart-80a10a56-56a3-43c2-8e0e-ea8dba42e768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365093334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1365093334
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2288140094
Short name T407
Test name
Test status
Simulation time 25623709 ps
CPU time 0.94 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:48 PM PDT 24
Peak memory 215712 kb
Host smart-8d6d18e3-960f-4297-8f02-8c99854ad5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288140094 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2288140094
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3524090877
Short name T475
Test name
Test status
Simulation time 51724686 ps
CPU time 0.93 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:56 PM PDT 24
Peak memory 215272 kb
Host smart-0f7e4cfb-a3e6-4430-8aad-c474313b7cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524090877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3524090877
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1113819690
Short name T160
Test name
Test status
Simulation time 796416433 ps
CPU time 4.3 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 216312 kb
Host smart-0685fafb-212c-4913-bc46-1995e085a33f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113819690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1113819690
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1956181386
Short name T190
Test name
Test status
Simulation time 26613274383 ps
CPU time 508.2 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:52:24 PM PDT 24
Peak memory 218076 kb
Host smart-1158ac71-01ba-4e79-9291-584b06debe51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956181386 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1956181386
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.301679000
Short name T776
Test name
Test status
Simulation time 49484902 ps
CPU time 1.2 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:39 PM PDT 24
Peak memory 215584 kb
Host smart-ef68ba9e-517e-4106-9be2-dff4a02654ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301679000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.301679000
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.629383219
Short name T199
Test name
Test status
Simulation time 50358364 ps
CPU time 0.85 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 206900 kb
Host smart-f49e10cb-5ad1-44d2-a56b-c804493dbfd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629383219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.629383219
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1945581251
Short name T183
Test name
Test status
Simulation time 23467261 ps
CPU time 0.9 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 215836 kb
Host smart-9e3d6c78-5b7d-4586-8a91-2a612c509e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945581251 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1945581251
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3621348276
Short name T95
Test name
Test status
Simulation time 27505153 ps
CPU time 1.02 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:35 PM PDT 24
Peak memory 216764 kb
Host smart-aa0cc41b-32e0-4d4c-bfac-b66e1e90b007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621348276 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3621348276
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1977175298
Short name T622
Test name
Test status
Simulation time 45967873 ps
CPU time 1.19 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 233468 kb
Host smart-96025060-1ffa-4d5e-a7e0-06fda8dc7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977175298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1977175298
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4049545248
Short name T586
Test name
Test status
Simulation time 39791124 ps
CPU time 1.36 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 217676 kb
Host smart-48fb1a7d-f292-402c-b61e-827864fd9f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049545248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4049545248
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1948637429
Short name T327
Test name
Test status
Simulation time 37624298 ps
CPU time 0.88 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215672 kb
Host smart-c43fe229-3ff0-44be-92b8-0bfbfdc348b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948637429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1948637429
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2585502289
Short name T296
Test name
Test status
Simulation time 25812832 ps
CPU time 0.91 seconds
Started Mar 17 12:42:36 PM PDT 24
Finished Mar 17 12:42:37 PM PDT 24
Peak memory 207016 kb
Host smart-b8d12614-fdd6-4709-8c14-809dfbcf9247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585502289 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2585502289
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.723438697
Short name T201
Test name
Test status
Simulation time 63311979 ps
CPU time 0.83 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:41 PM PDT 24
Peak memory 215388 kb
Host smart-3ff78402-e629-4d56-b50d-8ea4e82cfe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723438697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.723438697
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3881404647
Short name T761
Test name
Test status
Simulation time 490835997 ps
CPU time 5.04 seconds
Started Mar 17 12:42:35 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 215292 kb
Host smart-6189b2fe-41ef-4efd-b30c-da689b73aa3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881404647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3881404647
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.281664693
Short name T625
Test name
Test status
Simulation time 120695309046 ps
CPU time 1558.48 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 01:08:33 PM PDT 24
Peak memory 226384 kb
Host smart-b1041bfc-b298-4a55-abb7-e1c54b41d89a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281664693 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.281664693
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1794892940
Short name T500
Test name
Test status
Simulation time 19221477 ps
CPU time 1.16 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 231104 kb
Host smart-e7a109fe-5543-431f-a197-e20b3ecba7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794892940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1794892940
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.438368361
Short name T431
Test name
Test status
Simulation time 36911002 ps
CPU time 1.3 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 218724 kb
Host smart-ce62ec36-3534-4d7a-822c-93d3a04eef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438368361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.438368361
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1955473750
Short name T93
Test name
Test status
Simulation time 37190523 ps
CPU time 1.09 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 216924 kb
Host smart-c5cc343d-c7c2-4251-bb21-4865d3585bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955473750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1955473750
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2208777229
Short name T527
Test name
Test status
Simulation time 47417998 ps
CPU time 1.44 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 217900 kb
Host smart-b796198c-5ddd-4ae0-8c33-8062094005f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208777229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2208777229
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1811853334
Short name T45
Test name
Test status
Simulation time 25440513 ps
CPU time 1.06 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 231168 kb
Host smart-5c961d27-dbdb-406f-8b9b-b36f43fa49c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811853334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1811853334
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2853722906
Short name T751
Test name
Test status
Simulation time 27630718 ps
CPU time 1.18 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 217852 kb
Host smart-be6bdee9-4f2f-4a85-a0d8-5b373f01724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853722906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2853722906
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3483688985
Short name T119
Test name
Test status
Simulation time 53140656 ps
CPU time 0.82 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 217864 kb
Host smart-3ef9c8c1-5a6a-4315-a850-5feb120c7bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483688985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3483688985
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3932768291
Short name T504
Test name
Test status
Simulation time 44351516 ps
CPU time 0.91 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 216920 kb
Host smart-650995fe-2163-4dab-a43d-2d2c98448b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932768291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3932768291
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.489407960
Short name T645
Test name
Test status
Simulation time 33376296 ps
CPU time 1.28 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 219120 kb
Host smart-cbe83e00-1691-4666-a3af-5e149798c6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489407960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.489407960
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4039993319
Short name T496
Test name
Test status
Simulation time 56532577 ps
CPU time 1.19 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 215220 kb
Host smart-52af76dc-8ce6-4f59-a6fe-e5d0c104044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039993319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4039993319
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3109184232
Short name T446
Test name
Test status
Simulation time 48444739 ps
CPU time 0.84 seconds
Started Mar 17 12:43:48 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 219596 kb
Host smart-795f8056-e6f0-48ef-a024-1429f74896ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109184232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3109184232
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.233496312
Short name T10
Test name
Test status
Simulation time 43910460 ps
CPU time 1.57 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:59 PM PDT 24
Peak memory 217776 kb
Host smart-75abb2e1-6ad0-4198-885f-447c868c017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233496312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.233496312
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.4178814003
Short name T64
Test name
Test status
Simulation time 42838235 ps
CPU time 1.07 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 219260 kb
Host smart-66c369ef-ecaf-484e-9868-7e9fb16106a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178814003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4178814003
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2346508198
Short name T581
Test name
Test status
Simulation time 36623219 ps
CPU time 1.43 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217896 kb
Host smart-bf215b72-5e58-43c3-b431-43d444c62143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346508198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2346508198
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3603692028
Short name T70
Test name
Test status
Simulation time 20186747 ps
CPU time 1.08 seconds
Started Mar 17 12:43:50 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 219440 kb
Host smart-deba2de9-28fa-404a-ad79-93259faf7fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603692028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3603692028
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1507079636
Short name T257
Test name
Test status
Simulation time 85541378 ps
CPU time 1.11 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 216500 kb
Host smart-47e43b7f-6e26-42be-9e1d-853a663b3d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507079636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1507079636
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3254978874
Short name T534
Test name
Test status
Simulation time 20810540 ps
CPU time 0.89 seconds
Started Mar 17 12:43:46 PM PDT 24
Finished Mar 17 12:43:47 PM PDT 24
Peak memory 218276 kb
Host smart-2d517e7e-7e47-4f0e-a69c-5cbe055a47a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254978874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3254978874
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2492168614
Short name T361
Test name
Test status
Simulation time 33296527 ps
CPU time 1.03 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 219204 kb
Host smart-26cedf7c-6c95-48fa-9dbd-8992dc9c49f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492168614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2492168614
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.104607523
Short name T67
Test name
Test status
Simulation time 23570306 ps
CPU time 0.9 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 218316 kb
Host smart-5924b8a1-30c1-40a1-a86c-5eebf2fa5b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104607523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.104607523
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3595208634
Short name T821
Test name
Test status
Simulation time 171255962 ps
CPU time 0.98 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 216760 kb
Host smart-907cf6f6-2359-4d18-ad96-309b9ff138a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595208634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3595208634
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.158343905
Short name T156
Test name
Test status
Simulation time 46275093 ps
CPU time 1.18 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215596 kb
Host smart-abe0f194-d12d-49ec-91cf-b7e9bae48531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158343905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.158343905
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3707323879
Short name T499
Test name
Test status
Simulation time 38289382 ps
CPU time 0.97 seconds
Started Mar 17 12:42:42 PM PDT 24
Finished Mar 17 12:42:44 PM PDT 24
Peak memory 206184 kb
Host smart-e81eba28-81a9-40b5-80f7-198b9bedaae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707323879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3707323879
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3681359891
Short name T394
Test name
Test status
Simulation time 27651369 ps
CPU time 0.8 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215452 kb
Host smart-9da48df8-aea7-4a2d-9a40-4d2676e8db63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681359891 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3681359891
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2465473094
Short name T800
Test name
Test status
Simulation time 50658469 ps
CPU time 0.96 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 216552 kb
Host smart-9731fb84-3d33-432b-abd1-25a2e4b64a8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465473094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2465473094
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.890959496
Short name T92
Test name
Test status
Simulation time 61169003 ps
CPU time 1.13 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 229536 kb
Host smart-bebe915c-26f5-4894-a247-2709b76c18cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890959496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.890959496
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3902585185
Short name T772
Test name
Test status
Simulation time 101623025 ps
CPU time 1.13 seconds
Started Mar 17 12:42:34 PM PDT 24
Finished Mar 17 12:42:36 PM PDT 24
Peak memory 216516 kb
Host smart-4a192bcd-9975-4bef-b517-7b3484a5b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902585185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3902585185
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3115033394
Short name T46
Test name
Test status
Simulation time 21201573 ps
CPU time 1.21 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 223924 kb
Host smart-40c73dcb-a27d-4ae8-8684-830a90c74986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115033394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3115033394
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1581509208
Short name T749
Test name
Test status
Simulation time 46945323 ps
CPU time 0.9 seconds
Started Mar 17 12:42:33 PM PDT 24
Finished Mar 17 12:42:34 PM PDT 24
Peak memory 207092 kb
Host smart-2e92966f-4ec4-47e9-b955-fb47a29102df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581509208 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1581509208
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2433940747
Short name T709
Test name
Test status
Simulation time 35496151 ps
CPU time 0.88 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:38 PM PDT 24
Peak memory 215316 kb
Host smart-1785825a-95fb-4d54-b4c0-afb455b9f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433940747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2433940747
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3284063933
Short name T376
Test name
Test status
Simulation time 346523083 ps
CPU time 6.7 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:42:45 PM PDT 24
Peak memory 215364 kb
Host smart-16916782-7beb-4420-8b9b-bf2658543b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284063933 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3284063933
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1162105562
Short name T188
Test name
Test status
Simulation time 18842379316 ps
CPU time 420.81 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:49:39 PM PDT 24
Peak memory 217480 kb
Host smart-c60421ca-9b61-4e88-8d2b-42855f5f9d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162105562 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1162105562
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1253287875
Short name T770
Test name
Test status
Simulation time 34277179 ps
CPU time 1.07 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 218168 kb
Host smart-7589e754-4e3b-45e4-bfaf-8d1d6bbd022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253287875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1253287875
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1817398599
Short name T251
Test name
Test status
Simulation time 43121540 ps
CPU time 1.58 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 219300 kb
Host smart-6a3689c8-eb65-4498-bc4f-6f817e09c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817398599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1817398599
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.643787789
Short name T118
Test name
Test status
Simulation time 28315424 ps
CPU time 0.95 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 231024 kb
Host smart-3a2c1e70-37a1-47f2-a3b3-619103067655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643787789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.643787789
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.880110098
Short name T611
Test name
Test status
Simulation time 65722371 ps
CPU time 1.67 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 217892 kb
Host smart-0c63aedc-9a06-4197-aaec-d2fdb87776ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880110098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.880110098
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2318376269
Short name T173
Test name
Test status
Simulation time 28957591 ps
CPU time 1.27 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 224240 kb
Host smart-18decbbb-4c95-4b32-a903-b39f09332242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318376269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2318376269
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4025185548
Short name T558
Test name
Test status
Simulation time 58148882 ps
CPU time 1.23 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:53 PM PDT 24
Peak memory 216544 kb
Host smart-bd7d5941-b72d-424e-9a41-40cb94a8621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025185548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4025185548
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2102548738
Short name T79
Test name
Test status
Simulation time 25692927 ps
CPU time 1.05 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 229608 kb
Host smart-8866cc1a-380b-4e83-b874-3fc22474803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102548738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2102548738
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.251147214
Short name T746
Test name
Test status
Simulation time 57531057 ps
CPU time 1.39 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 216864 kb
Host smart-4e216766-adce-4627-bdbe-5c9c6ecbef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251147214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.251147214
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1265430989
Short name T755
Test name
Test status
Simulation time 19474286 ps
CPU time 1.01 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 218120 kb
Host smart-23446498-ad31-4b3d-9791-ec33ba618fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265430989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1265430989
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1162356415
Short name T490
Test name
Test status
Simulation time 43593632 ps
CPU time 1.21 seconds
Started Mar 17 12:44:05 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 216544 kb
Host smart-0b180e9e-40e3-4fa3-b5b4-6dc58e539ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162356415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1162356415
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1812819696
Short name T49
Test name
Test status
Simulation time 47683748 ps
CPU time 1.08 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 229800 kb
Host smart-e35f47e1-a05e-40c2-abf3-a60fa2a25cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812819696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1812819696
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4027777981
Short name T456
Test name
Test status
Simulation time 108596424 ps
CPU time 1.15 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216544 kb
Host smart-f3f9d154-6301-4976-a4ee-9698088c8a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027777981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4027777981
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3729367755
Short name T336
Test name
Test status
Simulation time 19413435 ps
CPU time 1.03 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:51 PM PDT 24
Peak memory 218204 kb
Host smart-295b404a-ad07-43fd-8398-9718da0064b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729367755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3729367755
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1004643535
Short name T604
Test name
Test status
Simulation time 95750600 ps
CPU time 1.48 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 217880 kb
Host smart-317ecb23-ff43-49e6-828e-4d0f68634b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004643535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1004643535
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3505481103
Short name T125
Test name
Test status
Simulation time 40397808 ps
CPU time 0.96 seconds
Started Mar 17 12:43:45 PM PDT 24
Finished Mar 17 12:43:46 PM PDT 24
Peak memory 232336 kb
Host smart-096cd450-67cc-4302-b451-3233bf280ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505481103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3505481103
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.458581349
Short name T483
Test name
Test status
Simulation time 90780608 ps
CPU time 1.01 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:58 PM PDT 24
Peak memory 219508 kb
Host smart-5febb69f-5013-47d1-a4a3-7eb7a3d43260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458581349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.458581349
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2656892003
Short name T106
Test name
Test status
Simulation time 32139862 ps
CPU time 1.01 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 222884 kb
Host smart-2aea80c7-fcdc-4647-a410-f9ba9001543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656892003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2656892003
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3649445453
Short name T276
Test name
Test status
Simulation time 40197259 ps
CPU time 1.41 seconds
Started Mar 17 12:43:47 PM PDT 24
Finished Mar 17 12:43:49 PM PDT 24
Peak memory 217728 kb
Host smart-fbc30d83-4980-4494-96cd-c1b6123bb07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649445453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3649445453
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3591897819
Short name T205
Test name
Test status
Simulation time 19900874 ps
CPU time 1.03 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:56 PM PDT 24
Peak memory 217920 kb
Host smart-26172d5d-8880-4285-ae47-732069006c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591897819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3591897819
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.1773794508
Short name T792
Test name
Test status
Simulation time 44858254 ps
CPU time 1.1 seconds
Started Mar 17 12:42:39 PM PDT 24
Finished Mar 17 12:42:41 PM PDT 24
Peak memory 215748 kb
Host smart-990fa6af-f247-436e-9407-be8f16e8238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773794508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1773794508
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1460078259
Short name T157
Test name
Test status
Simulation time 117735906 ps
CPU time 1.13 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 206220 kb
Host smart-dce39675-5d81-447c-ad44-c453a1549c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460078259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1460078259
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4251539556
Short name T690
Test name
Test status
Simulation time 58232596 ps
CPU time 0.87 seconds
Started Mar 17 12:42:42 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 215904 kb
Host smart-ef3a0a7b-74b9-4780-a853-56e18d92640c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251539556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4251539556
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.4054993035
Short name T714
Test name
Test status
Simulation time 65826376 ps
CPU time 1.03 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 231176 kb
Host smart-82d26c57-c69d-49dc-9fb7-578e867d299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054993035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4054993035
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.889319889
Short name T212
Test name
Test status
Simulation time 105442536 ps
CPU time 0.95 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 216736 kb
Host smart-b30c04ca-3855-429d-9350-044dd3933cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889319889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.889319889
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3630945679
Short name T781
Test name
Test status
Simulation time 37844337 ps
CPU time 0.85 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215632 kb
Host smart-7700a751-ba9c-4d70-ae76-1a8b23dee9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630945679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3630945679
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1042752909
Short name T294
Test name
Test status
Simulation time 34633604 ps
CPU time 0.87 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 207008 kb
Host smart-ba4f0458-5fca-424b-8704-b4778b0d511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042752909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1042752909
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.345642010
Short name T356
Test name
Test status
Simulation time 94330348 ps
CPU time 0.83 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 215028 kb
Host smart-3f5d388d-bb7c-46d0-b250-8bd9c09031b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345642010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.345642010
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1277098550
Short name T464
Test name
Test status
Simulation time 366526672 ps
CPU time 2.36 seconds
Started Mar 17 12:42:42 PM PDT 24
Finished Mar 17 12:42:45 PM PDT 24
Peak memory 219244 kb
Host smart-21e0a9ed-775e-4e00-8d3a-6db192385332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277098550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1277098550
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1219129808
Short name T553
Test name
Test status
Simulation time 9426701667 ps
CPU time 236.3 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:46:35 PM PDT 24
Peak memory 223784 kb
Host smart-edb92cd0-1c3e-492b-999a-a6bee6690b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219129808 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1219129808
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2949994319
Short name T15
Test name
Test status
Simulation time 19712461 ps
CPU time 1.05 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 223080 kb
Host smart-626ff194-9512-4217-b859-88f520559e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949994319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2949994319
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3386587854
Short name T745
Test name
Test status
Simulation time 43478294 ps
CPU time 1.46 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 217756 kb
Host smart-d592b16f-84f9-48df-8b3e-9e16fb937169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386587854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3386587854
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.727992777
Short name T213
Test name
Test status
Simulation time 32764373 ps
CPU time 1.44 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 233484 kb
Host smart-44a23261-1163-4a55-908d-6506d9a24f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727992777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.727992777
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.311429705
Short name T616
Test name
Test status
Simulation time 114154325 ps
CPU time 1.68 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 216876 kb
Host smart-b2c2b6a3-be77-4dd1-a3dc-f0b90b8fddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311429705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.311429705
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1284888850
Short name T763
Test name
Test status
Simulation time 28615198 ps
CPU time 1.16 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 231224 kb
Host smart-da3a079e-45c7-4f48-8071-65865d8c43f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284888850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1284888850
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.670649155
Short name T674
Test name
Test status
Simulation time 146093362 ps
CPU time 1.85 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 218048 kb
Host smart-979b264c-d0db-4407-8c15-c4a645a5f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670649155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.670649155
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3683814883
Short name T621
Test name
Test status
Simulation time 19794868 ps
CPU time 0.99 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 217972 kb
Host smart-98f86c76-fd8e-45f5-b2c6-01f2bcce2679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683814883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3683814883
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1996690439
Short name T306
Test name
Test status
Simulation time 41426259 ps
CPU time 1.15 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 218920 kb
Host smart-2951f540-7c24-4371-842a-e6004819bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996690439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1996690439
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4149873449
Short name T68
Test name
Test status
Simulation time 141393830 ps
CPU time 1.04 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 216768 kb
Host smart-1d42d3e3-0474-48fd-bdef-a565f8495e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149873449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4149873449
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2569422753
Short name T706
Test name
Test status
Simulation time 365618769 ps
CPU time 1.23 seconds
Started Mar 17 12:44:08 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 216488 kb
Host smart-b786e165-7835-48d1-bfc0-6c3c35b38d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569422753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2569422753
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1662088741
Short name T796
Test name
Test status
Simulation time 45801307 ps
CPU time 0.97 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 218104 kb
Host smart-5b63dbe9-f537-497d-8bf1-18e812c42297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662088741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1662088741
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3533947174
Short name T182
Test name
Test status
Simulation time 45627511 ps
CPU time 1.39 seconds
Started Mar 17 12:43:58 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217844 kb
Host smart-6084a50d-5d47-40ee-b4e6-da87e90c98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533947174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3533947174
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.1955729647
Short name T814
Test name
Test status
Simulation time 18817186 ps
CPU time 1.04 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 218128 kb
Host smart-d315dbd2-01d7-4b21-96f5-2bf7c21ff3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955729647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1955729647
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3827790154
Short name T443
Test name
Test status
Simulation time 161201433 ps
CPU time 1.27 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 218072 kb
Host smart-cdbaa73f-59ae-4996-9557-240b4ab6f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827790154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3827790154
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.611553775
Short name T75
Test name
Test status
Simulation time 21061164 ps
CPU time 1.07 seconds
Started Mar 17 12:43:49 PM PDT 24
Finished Mar 17 12:43:50 PM PDT 24
Peak memory 219232 kb
Host smart-be666ffc-a757-4169-9e62-b844293869dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611553775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.611553775
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4181738109
Short name T523
Test name
Test status
Simulation time 98481578 ps
CPU time 1.32 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216772 kb
Host smart-af0b4096-edf7-45e6-863f-791053e06035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181738109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4181738109
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_genbits.852628128
Short name T266
Test name
Test status
Simulation time 2999961884 ps
CPU time 75.66 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:45:07 PM PDT 24
Peak memory 217128 kb
Host smart-e1e69080-83fc-4133-bd67-4fd336e8460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852628128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.852628128
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.139244726
Short name T587
Test name
Test status
Simulation time 36823187 ps
CPU time 0.92 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 219580 kb
Host smart-193f33fd-c0e9-4502-97d7-0a37f7dd58f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139244726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.139244726
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.512652227
Short name T318
Test name
Test status
Simulation time 149298068 ps
CPU time 3.14 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 217000 kb
Host smart-762c9a92-064e-405f-9d24-f8acb5cd51db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512652227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.512652227
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2416327683
Short name T105
Test name
Test status
Simulation time 131503185 ps
CPU time 1.28 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215632 kb
Host smart-fa8127be-1e1c-4593-b327-20fb91802fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416327683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2416327683
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.4023878895
Short name T319
Test name
Test status
Simulation time 105256432 ps
CPU time 0.91 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 206160 kb
Host smart-33cf8fc2-ecd0-489f-a608-6e9833668b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023878895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.4023878895
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4244122906
Short name T471
Test name
Test status
Simulation time 20830729 ps
CPU time 0.85 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:41 PM PDT 24
Peak memory 215364 kb
Host smart-eb5f3d19-b448-4e89-973e-894148a2a6ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244122906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4244122906
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_genbits.339722107
Short name T286
Test name
Test status
Simulation time 37572113 ps
CPU time 1.42 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 215292 kb
Host smart-972a710a-a567-443f-8c6c-9820caa458d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339722107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.339722107
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1038412177
Short name T545
Test name
Test status
Simulation time 21023900 ps
CPU time 1.07 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215780 kb
Host smart-452b674a-ade1-46c7-a663-4a2db761752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038412177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1038412177
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1442936090
Short name T134
Test name
Test status
Simulation time 47883046 ps
CPU time 0.9 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:41 PM PDT 24
Peak memory 207080 kb
Host smart-1ca65497-1631-4fda-9ca6-d1f3fdfb71f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442936090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1442936090
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2927224971
Short name T313
Test name
Test status
Simulation time 24907980 ps
CPU time 0.92 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 215392 kb
Host smart-33cc2867-bfb9-4a59-a338-854273640f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927224971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2927224971
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3564948350
Short name T310
Test name
Test status
Simulation time 831030610 ps
CPU time 4.81 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:46 PM PDT 24
Peak memory 216576 kb
Host smart-70867c77-dcb1-4b12-aff2-31bfd8f2a687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564948350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3564948350
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1055851523
Short name T374
Test name
Test status
Simulation time 195276340872 ps
CPU time 845.38 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:56:46 PM PDT 24
Peak memory 219888 kb
Host smart-267057ff-07d0-4f33-ac8d-bfa15b4c858d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055851523 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1055851523
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3441531107
Short name T405
Test name
Test status
Simulation time 23210402 ps
CPU time 1.03 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 231288 kb
Host smart-8157e7d3-d5f3-400d-b368-0850efe7726c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441531107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3441531107
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4175740209
Short name T768
Test name
Test status
Simulation time 49649797 ps
CPU time 1.19 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 216636 kb
Host smart-33848538-18f5-4278-952b-3b449a3f0d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175740209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4175740209
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.500660597
Short name T825
Test name
Test status
Simulation time 48722818 ps
CPU time 0.93 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:58 PM PDT 24
Peak memory 218104 kb
Host smart-3f98354c-966d-45e6-b131-1ca0ff4e8fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500660597 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.500660597
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3846341219
Short name T256
Test name
Test status
Simulation time 130373924 ps
CPU time 1.12 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 216828 kb
Host smart-f4519ae0-9e2b-43fb-97d6-0400a1b14066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846341219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3846341219
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.37572291
Short name T795
Test name
Test status
Simulation time 21506677 ps
CPU time 0.87 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 218084 kb
Host smart-939988a4-d201-4883-9c4b-0c85cd0b640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37572291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.37572291
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3400417856
Short name T713
Test name
Test status
Simulation time 147350821 ps
CPU time 2.84 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 219464 kb
Host smart-4b70e425-6387-40a4-84e1-99abbf215441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400417856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3400417856
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1714683065
Short name T47
Test name
Test status
Simulation time 19226958 ps
CPU time 1.11 seconds
Started Mar 17 12:43:51 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 232488 kb
Host smart-83fe465d-93ab-41ff-bb75-d3fc1635fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714683065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1714683065
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1342003922
Short name T508
Test name
Test status
Simulation time 94571045 ps
CPU time 1.08 seconds
Started Mar 17 12:44:06 PM PDT 24
Finished Mar 17 12:44:07 PM PDT 24
Peak memory 216736 kb
Host smart-5280fd41-ef6d-4a76-9e73-98bbd6560d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342003922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1342003922
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1225967333
Short name T82
Test name
Test status
Simulation time 24255000 ps
CPU time 1.25 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 229680 kb
Host smart-da6e2dbb-cf59-4ca9-a465-7aae8a3dc22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225967333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1225967333
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2730245888
Short name T535
Test name
Test status
Simulation time 32395205 ps
CPU time 1.22 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 217704 kb
Host smart-72dcc24e-4e44-4e13-bf21-8ab2316b6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730245888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2730245888
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.4229476706
Short name T807
Test name
Test status
Simulation time 21273449 ps
CPU time 0.96 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 218128 kb
Host smart-df619076-3978-4721-9449-3bbfd3148dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229476706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4229476706
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2201222624
Short name T384
Test name
Test status
Simulation time 27664053 ps
CPU time 1.09 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 216412 kb
Host smart-7ed75694-2b79-46c0-9828-d569e7d0af6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201222624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2201222624
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.620583315
Short name T395
Test name
Test status
Simulation time 48142870 ps
CPU time 0.92 seconds
Started Mar 17 12:43:55 PM PDT 24
Finished Mar 17 12:43:57 PM PDT 24
Peak memory 218008 kb
Host smart-f95974f3-e70a-4f9a-9592-aa9bbb703a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620583315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.620583315
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1932751171
Short name T277
Test name
Test status
Simulation time 55549348 ps
CPU time 1.76 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218140 kb
Host smart-7f9234d9-d8b3-4ca1-89dd-ea6c15d93970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932751171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1932751171
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3950556796
Short name T97
Test name
Test status
Simulation time 36204741 ps
CPU time 0.99 seconds
Started Mar 17 12:43:56 PM PDT 24
Finished Mar 17 12:43:59 PM PDT 24
Peak memory 231024 kb
Host smart-c3774d0a-8fc1-4c21-81d3-c0e7b5d5b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950556796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3950556796
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.496694413
Short name T575
Test name
Test status
Simulation time 40642231 ps
CPU time 1.36 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 215280 kb
Host smart-1e1142d6-d74c-4260-907f-743a588f3cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496694413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.496694413
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.611586796
Short name T8
Test name
Test status
Simulation time 35545590 ps
CPU time 1.16 seconds
Started Mar 17 12:43:53 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 229568 kb
Host smart-58fb5f5e-41d4-4b7c-bcb4-9c062ad92cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611586796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.611586796
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2178121207
Short name T513
Test name
Test status
Simulation time 37799849 ps
CPU time 1.39 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 217896 kb
Host smart-58e012ad-34af-493e-a73b-f739e678efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178121207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2178121207
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.4056164732
Short name T89
Test name
Test status
Simulation time 33494510 ps
CPU time 0.96 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 229616 kb
Host smart-632474e5-0d1d-4c2d-99f7-4e6aadc7192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056164732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4056164732
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3211044404
Short name T439
Test name
Test status
Simulation time 27752507 ps
CPU time 1.16 seconds
Started Mar 17 12:43:54 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 217904 kb
Host smart-1c9ba36b-1514-48f3-90a8-8e7711d5e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211044404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3211044404
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2678568767
Short name T291
Test name
Test status
Simulation time 122519920 ps
CPU time 1.15 seconds
Started Mar 17 12:42:37 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 215672 kb
Host smart-1a6c6956-2c17-4e30-8754-88a69fefa3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678568767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2678568767
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2921329600
Short name T786
Test name
Test status
Simulation time 75945444 ps
CPU time 0.92 seconds
Started Mar 17 12:42:47 PM PDT 24
Finished Mar 17 12:42:48 PM PDT 24
Peak memory 206000 kb
Host smart-6b0901f9-79d4-476e-b759-cbb06005d9bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921329600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2921329600
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2301807423
Short name T103
Test name
Test status
Simulation time 33936265 ps
CPU time 0.81 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:41 PM PDT 24
Peak memory 215852 kb
Host smart-25e6feb1-59f9-497d-a45a-78d0ad5b010c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301807423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2301807423
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.456881018
Short name T582
Test name
Test status
Simulation time 143057265 ps
CPU time 0.95 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 217480 kb
Host smart-3c635978-1059-4c20-892f-cbf1c615b76c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456881018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.456881018
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2014154279
Short name T699
Test name
Test status
Simulation time 32701406 ps
CPU time 0.85 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 217780 kb
Host smart-60d11a36-cc0b-44f6-a27e-14f2d80faa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014154279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2014154279
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4261029208
Short name T704
Test name
Test status
Simulation time 43233362 ps
CPU time 1.57 seconds
Started Mar 17 12:42:38 PM PDT 24
Finished Mar 17 12:42:40 PM PDT 24
Peak memory 217680 kb
Host smart-82f42b81-9e1d-4f47-adb9-b136539f2e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261029208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4261029208
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2244740734
Short name T44
Test name
Test status
Simulation time 22203226 ps
CPU time 1.26 seconds
Started Mar 17 12:42:41 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 224136 kb
Host smart-63dcf19a-3f71-4a50-8a74-297050ec015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244740734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2244740734
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1793287175
Short name T289
Test name
Test status
Simulation time 39876593 ps
CPU time 0.89 seconds
Started Mar 17 12:42:40 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 207148 kb
Host smart-a81eb19a-2386-48cd-b967-00be8845acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793287175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1793287175
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3623506107
Short name T548
Test name
Test status
Simulation time 20589199 ps
CPU time 1.01 seconds
Started Mar 17 12:42:42 PM PDT 24
Finished Mar 17 12:42:43 PM PDT 24
Peak memory 215376 kb
Host smart-467cce87-09e3-4677-8776-1685eec1cfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623506107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3623506107
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1486153579
Short name T518
Test name
Test status
Simulation time 385516985 ps
CPU time 5.26 seconds
Started Mar 17 12:42:39 PM PDT 24
Finished Mar 17 12:42:46 PM PDT 24
Peak memory 215304 kb
Host smart-6e9bb375-988b-4671-bc20-b9c00dfc3229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486153579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1486153579
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3272102445
Short name T596
Test name
Test status
Simulation time 18973545399 ps
CPU time 209.58 seconds
Started Mar 17 12:42:42 PM PDT 24
Finished Mar 17 12:46:12 PM PDT 24
Peak memory 221004 kb
Host smart-3d4ecd78-8dc1-4163-87ce-dd9dbfbe17be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272102445 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3272102445
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1469062289
Short name T391
Test name
Test status
Simulation time 28090322 ps
CPU time 0.83 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:06 PM PDT 24
Peak memory 218048 kb
Host smart-c775aa5e-1a88-4c79-9c02-09d96e242330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469062289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1469062289
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3120511034
Short name T784
Test name
Test status
Simulation time 52620242 ps
CPU time 1.37 seconds
Started Mar 17 12:44:03 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 218328 kb
Host smart-d01f6ba6-b86b-4129-aade-ac6699e27d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120511034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3120511034
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.389358274
Short name T656
Test name
Test status
Simulation time 53042586 ps
CPU time 1.16 seconds
Started Mar 17 12:44:04 PM PDT 24
Finished Mar 17 12:44:05 PM PDT 24
Peak memory 219236 kb
Host smart-fff9df9b-8791-454b-832a-3e300475c1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389358274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.389358274
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3830894657
Short name T669
Test name
Test status
Simulation time 76522514 ps
CPU time 1.43 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218188 kb
Host smart-77a667ea-20b7-4593-9006-16274c10a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830894657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3830894657
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.782826221
Short name T408
Test name
Test status
Simulation time 22672051 ps
CPU time 0.92 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 217984 kb
Host smart-888da075-2b59-4092-b336-a1005d198d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782826221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.782826221
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3935830198
Short name T703
Test name
Test status
Simulation time 68500930 ps
CPU time 1.77 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218188 kb
Host smart-b6f35600-576d-4119-9e77-0ed173213f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935830198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3935830198
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3311849928
Short name T769
Test name
Test status
Simulation time 18751641 ps
CPU time 1.1 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:03 PM PDT 24
Peak memory 222984 kb
Host smart-7f5534c2-d4f1-4175-94ed-e9914c7b68d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311849928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3311849928
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.52470750
Short name T385
Test name
Test status
Simulation time 38235521 ps
CPU time 1.47 seconds
Started Mar 17 12:43:57 PM PDT 24
Finished Mar 17 12:43:59 PM PDT 24
Peak memory 219156 kb
Host smart-c049706a-0590-49c4-a0ed-7428aed15daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52470750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.52470750
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2624689462
Short name T96
Test name
Test status
Simulation time 23770094 ps
CPU time 0.92 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:00 PM PDT 24
Peak memory 218160 kb
Host smart-f5b87f00-bc3d-4880-b92e-112325321dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624689462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2624689462
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2878249571
Short name T655
Test name
Test status
Simulation time 86029021 ps
CPU time 1.25 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 216772 kb
Host smart-43d78d5c-9ab0-425f-9f2d-cd55b46521a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878249571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2878249571
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4229187788
Short name T580
Test name
Test status
Simulation time 21281252 ps
CPU time 1.18 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218100 kb
Host smart-f6b1914e-c706-4db4-b12f-b9e39d23ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229187788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4229187788
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3579669727
Short name T316
Test name
Test status
Simulation time 57641813 ps
CPU time 1.2 seconds
Started Mar 17 12:44:01 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217856 kb
Host smart-fe1ed3cc-98bd-4d95-a78c-ca61cea89e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579669727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3579669727
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1880318117
Short name T815
Test name
Test status
Simulation time 32340280 ps
CPU time 0.82 seconds
Started Mar 17 12:44:02 PM PDT 24
Finished Mar 17 12:44:04 PM PDT 24
Peak memory 217604 kb
Host smart-8c7dc562-2f8c-4d89-bd3e-2cbf22a280ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880318117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1880318117
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.525360329
Short name T637
Test name
Test status
Simulation time 36542426 ps
CPU time 1.1 seconds
Started Mar 17 12:43:52 PM PDT 24
Finished Mar 17 12:43:54 PM PDT 24
Peak memory 219300 kb
Host smart-17b685ed-6e9c-4039-a882-0473502cdc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525360329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.525360329
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2860282229
Short name T87
Test name
Test status
Simulation time 26473275 ps
CPU time 1.29 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 232508 kb
Host smart-3b4a79e9-3ba5-4618-9d1e-8ac5ad515bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860282229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2860282229
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.943835500
Short name T589
Test name
Test status
Simulation time 67168748 ps
CPU time 1.51 seconds
Started Mar 17 12:43:59 PM PDT 24
Finished Mar 17 12:44:01 PM PDT 24
Peak memory 218152 kb
Host smart-f7654ca8-9369-44b8-a3a9-14fdf2fbf4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943835500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.943835500
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2851622064
Short name T557
Test name
Test status
Simulation time 76078966 ps
CPU time 1.08 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 219432 kb
Host smart-3248cad8-0627-4eaa-94c8-f12710a32ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851622064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2851622064
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.1750986800
Short name T794
Test name
Test status
Simulation time 24518244 ps
CPU time 0.95 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 218280 kb
Host smart-e8499e33-0a33-4a5f-80f4-c31499b8bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750986800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1750986800
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3153698245
Short name T267
Test name
Test status
Simulation time 44114317 ps
CPU time 1.34 seconds
Started Mar 17 12:44:00 PM PDT 24
Finished Mar 17 12:44:02 PM PDT 24
Peak memory 217900 kb
Host smart-4a1654da-b2d8-4c13-b0e0-1fc20d395687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153698245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3153698245
Directory /workspace/99.edn_genbits/latest
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