Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.21 98.27 93.63 96.79 84.39 96.87 96.58 92.95


Total test records in report: 974
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T790 /workspace/coverage/default/107.edn_genbits.3944621172 Mar 19 02:57:20 PM PDT 24 Mar 19 02:57:21 PM PDT 24 27069378 ps
T791 /workspace/coverage/default/27.edn_alert_test.4064886613 Mar 19 02:56:35 PM PDT 24 Mar 19 02:56:36 PM PDT 24 26286778 ps
T792 /workspace/coverage/default/143.edn_genbits.740258260 Mar 19 02:57:20 PM PDT 24 Mar 19 02:57:21 PM PDT 24 61571307 ps
T793 /workspace/coverage/default/289.edn_genbits.2983696792 Mar 19 02:57:50 PM PDT 24 Mar 19 02:57:52 PM PDT 24 30344285 ps
T188 /workspace/coverage/default/7.edn_err.1017019091 Mar 19 02:55:55 PM PDT 24 Mar 19 02:55:56 PM PDT 24 35471620 ps
T794 /workspace/coverage/default/13.edn_smoke.4254962676 Mar 19 02:56:07 PM PDT 24 Mar 19 02:56:08 PM PDT 24 47947766 ps
T795 /workspace/coverage/default/233.edn_genbits.1226911753 Mar 19 02:57:51 PM PDT 24 Mar 19 02:57:52 PM PDT 24 70897589 ps
T796 /workspace/coverage/default/31.edn_alert.3704240453 Mar 19 02:56:35 PM PDT 24 Mar 19 02:56:36 PM PDT 24 84590990 ps
T797 /workspace/coverage/default/37.edn_genbits.1865028297 Mar 19 02:56:43 PM PDT 24 Mar 19 02:56:47 PM PDT 24 273394866 ps
T798 /workspace/coverage/default/28.edn_alert_test.1092095392 Mar 19 02:56:34 PM PDT 24 Mar 19 02:56:36 PM PDT 24 15620675 ps
T56 /workspace/coverage/default/1.edn_sec_cm.1491551515 Mar 19 02:55:47 PM PDT 24 Mar 19 02:55:55 PM PDT 24 1516604947 ps
T799 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1722751682 Mar 19 02:56:07 PM PDT 24 Mar 19 03:31:17 PM PDT 24 758895349668 ps
T800 /workspace/coverage/default/30.edn_disable_auto_req_mode.2345327830 Mar 19 02:56:40 PM PDT 24 Mar 19 02:56:42 PM PDT 24 38143279 ps
T801 /workspace/coverage/default/252.edn_genbits.3411500559 Mar 19 02:57:52 PM PDT 24 Mar 19 02:57:53 PM PDT 24 52271753 ps
T802 /workspace/coverage/default/164.edn_genbits.3204508330 Mar 19 02:57:23 PM PDT 24 Mar 19 02:57:25 PM PDT 24 142474144 ps
T803 /workspace/coverage/default/38.edn_genbits.2689607662 Mar 19 02:56:38 PM PDT 24 Mar 19 02:56:40 PM PDT 24 32278025 ps
T804 /workspace/coverage/default/32.edn_genbits.3300702036 Mar 19 02:56:34 PM PDT 24 Mar 19 02:56:36 PM PDT 24 35057092 ps
T805 /workspace/coverage/default/44.edn_genbits.2282620598 Mar 19 02:56:52 PM PDT 24 Mar 19 02:56:54 PM PDT 24 39498587 ps
T806 /workspace/coverage/default/171.edn_genbits.3705722950 Mar 19 02:57:47 PM PDT 24 Mar 19 02:58:59 PM PDT 24 2288799924 ps
T807 /workspace/coverage/default/1.edn_genbits.3989786697 Mar 19 02:55:43 PM PDT 24 Mar 19 02:55:47 PM PDT 24 167864194 ps
T808 /workspace/coverage/default/219.edn_genbits.1580146654 Mar 19 02:57:31 PM PDT 24 Mar 19 02:57:33 PM PDT 24 50325894 ps
T809 /workspace/coverage/default/7.edn_stress_all.972369932 Mar 19 02:55:52 PM PDT 24 Mar 19 02:55:54 PM PDT 24 132270929 ps
T810 /workspace/coverage/default/32.edn_stress_all.2079345377 Mar 19 02:56:31 PM PDT 24 Mar 19 02:56:33 PM PDT 24 85721518 ps
T811 /workspace/coverage/default/44.edn_alert.249191391 Mar 19 02:56:49 PM PDT 24 Mar 19 02:56:50 PM PDT 24 41305107 ps
T812 /workspace/coverage/default/167.edn_genbits.2400841539 Mar 19 02:57:33 PM PDT 24 Mar 19 02:57:35 PM PDT 24 37919748 ps
T813 /workspace/coverage/default/279.edn_genbits.2618576559 Mar 19 02:57:41 PM PDT 24 Mar 19 02:57:42 PM PDT 24 23579184 ps
T814 /workspace/coverage/default/154.edn_genbits.4097440805 Mar 19 02:57:27 PM PDT 24 Mar 19 02:57:29 PM PDT 24 31879096 ps
T815 /workspace/coverage/default/50.edn_genbits.3056609171 Mar 19 02:57:05 PM PDT 24 Mar 19 02:57:06 PM PDT 24 88148649 ps
T816 /workspace/coverage/default/4.edn_genbits.4284049217 Mar 19 02:55:47 PM PDT 24 Mar 19 02:55:50 PM PDT 24 45115291 ps
T817 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1034737985 Mar 19 02:56:35 PM PDT 24 Mar 19 03:11:11 PM PDT 24 128461228638 ps
T818 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.40117013 Mar 19 02:56:35 PM PDT 24 Mar 19 03:39:46 PM PDT 24 111319196255 ps
T819 /workspace/coverage/default/228.edn_genbits.3314782035 Mar 19 02:57:50 PM PDT 24 Mar 19 02:57:51 PM PDT 24 85241808 ps
T820 /workspace/coverage/default/43.edn_err.3920365016 Mar 19 02:56:47 PM PDT 24 Mar 19 02:56:48 PM PDT 24 29753648 ps
T821 /workspace/coverage/default/217.edn_genbits.974791704 Mar 19 02:57:49 PM PDT 24 Mar 19 02:57:52 PM PDT 24 103201715 ps
T822 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.60853513 Mar 19 02:56:51 PM PDT 24 Mar 19 03:06:35 PM PDT 24 103752288168 ps
T823 /workspace/coverage/default/5.edn_regwen.2411055374 Mar 19 02:55:50 PM PDT 24 Mar 19 02:55:52 PM PDT 24 18343188 ps
T193 /workspace/coverage/default/36.edn_err.1042466439 Mar 19 02:56:43 PM PDT 24 Mar 19 02:56:45 PM PDT 24 78244536 ps
T824 /workspace/coverage/default/35.edn_err.2052484621 Mar 19 02:56:37 PM PDT 24 Mar 19 02:56:38 PM PDT 24 27619833 ps
T825 /workspace/coverage/default/15.edn_alert.473627553 Mar 19 02:56:11 PM PDT 24 Mar 19 02:56:12 PM PDT 24 86918455 ps
T826 /workspace/coverage/default/35.edn_disable_auto_req_mode.2137501042 Mar 19 02:56:41 PM PDT 24 Mar 19 02:56:43 PM PDT 24 47051674 ps
T827 /workspace/coverage/default/16.edn_stress_all.1198368022 Mar 19 02:56:11 PM PDT 24 Mar 19 02:56:16 PM PDT 24 706047212 ps
T828 /workspace/coverage/default/256.edn_genbits.3060788577 Mar 19 02:57:40 PM PDT 24 Mar 19 02:57:41 PM PDT 24 76857939 ps
T829 /workspace/coverage/default/19.edn_smoke.608137934 Mar 19 02:56:14 PM PDT 24 Mar 19 02:56:15 PM PDT 24 37039135 ps
T830 /workspace/coverage/default/176.edn_genbits.1487615416 Mar 19 02:57:22 PM PDT 24 Mar 19 02:57:24 PM PDT 24 78550866 ps
T831 /workspace/coverage/default/42.edn_alert_test.101977648 Mar 19 02:56:59 PM PDT 24 Mar 19 02:57:01 PM PDT 24 51833398 ps
T832 /workspace/coverage/default/68.edn_genbits.3655548845 Mar 19 02:57:07 PM PDT 24 Mar 19 02:57:10 PM PDT 24 238386291 ps
T833 /workspace/coverage/default/13.edn_disable.947135093 Mar 19 02:56:15 PM PDT 24 Mar 19 02:56:15 PM PDT 24 17266539 ps
T834 /workspace/coverage/default/57.edn_err.2941511645 Mar 19 02:57:10 PM PDT 24 Mar 19 02:57:11 PM PDT 24 34232684 ps
T835 /workspace/coverage/default/169.edn_genbits.4202556292 Mar 19 02:57:28 PM PDT 24 Mar 19 02:57:30 PM PDT 24 70588969 ps
T836 /workspace/coverage/default/49.edn_smoke.2424970383 Mar 19 02:57:13 PM PDT 24 Mar 19 02:57:14 PM PDT 24 57898796 ps
T837 /workspace/coverage/default/82.edn_err.2094845409 Mar 19 02:57:09 PM PDT 24 Mar 19 02:57:11 PM PDT 24 27510613 ps
T190 /workspace/coverage/default/16.edn_disable_auto_req_mode.3653675738 Mar 19 02:56:12 PM PDT 24 Mar 19 02:56:13 PM PDT 24 66796279 ps
T838 /workspace/coverage/default/35.edn_alert.1538911158 Mar 19 02:56:44 PM PDT 24 Mar 19 02:56:45 PM PDT 24 77244784 ps
T839 /workspace/coverage/default/25.edn_smoke.2681229996 Mar 19 02:56:35 PM PDT 24 Mar 19 02:56:36 PM PDT 24 28350498 ps
T840 /workspace/coverage/default/239.edn_genbits.2924598492 Mar 19 02:57:31 PM PDT 24 Mar 19 02:57:32 PM PDT 24 37271452 ps
T841 /workspace/coverage/default/26.edn_disable_auto_req_mode.2772277925 Mar 19 02:56:33 PM PDT 24 Mar 19 02:56:34 PM PDT 24 38040653 ps
T842 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2890219654 Mar 19 02:56:23 PM PDT 24 Mar 19 03:08:25 PM PDT 24 66489744102 ps
T843 /workspace/coverage/default/86.edn_genbits.2066357137 Mar 19 02:57:12 PM PDT 24 Mar 19 02:57:14 PM PDT 24 128103115 ps
T302 /workspace/coverage/default/247.edn_genbits.4005572490 Mar 19 02:57:39 PM PDT 24 Mar 19 02:57:41 PM PDT 24 101189600 ps
T253 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2697415036 Mar 19 02:57:48 PM PDT 24 Mar 19 02:57:50 PM PDT 24 39829594 ps
T254 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.953918744 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:58 PM PDT 24 269250716 ps
T844 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1409293805 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:05 PM PDT 24 105845780 ps
T845 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.238002134 Mar 19 02:58:17 PM PDT 24 Mar 19 02:58:18 PM PDT 24 28375497 ps
T846 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1308722428 Mar 19 02:58:02 PM PDT 24 Mar 19 02:58:04 PM PDT 24 242322508 ps
T251 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1942042655 Mar 19 02:57:44 PM PDT 24 Mar 19 02:57:45 PM PDT 24 86643939 ps
T847 /workspace/coverage/cover_reg_top/33.edn_intr_test.4069887994 Mar 19 02:58:30 PM PDT 24 Mar 19 02:58:31 PM PDT 24 108904257 ps
T848 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1361559826 Mar 19 02:58:06 PM PDT 24 Mar 19 02:58:08 PM PDT 24 52627069 ps
T225 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3322455168 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:09 PM PDT 24 37856144 ps
T244 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.407205771 Mar 19 02:57:57 PM PDT 24 Mar 19 02:57:58 PM PDT 24 16201448 ps
T252 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2983122683 Mar 19 02:57:48 PM PDT 24 Mar 19 02:57:49 PM PDT 24 26938883 ps
T255 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.758519251 Mar 19 02:57:58 PM PDT 24 Mar 19 02:58:00 PM PDT 24 139855438 ps
T849 /workspace/coverage/cover_reg_top/39.edn_intr_test.928489557 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:10 PM PDT 24 30005388 ps
T850 /workspace/coverage/cover_reg_top/34.edn_intr_test.1372569190 Mar 19 02:58:17 PM PDT 24 Mar 19 02:58:18 PM PDT 24 32077407 ps
T851 /workspace/coverage/cover_reg_top/5.edn_intr_test.4140768298 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:57 PM PDT 24 13064235 ps
T852 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.317117451 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:14 PM PDT 24 90056555 ps
T853 /workspace/coverage/cover_reg_top/41.edn_intr_test.2739797316 Mar 19 02:58:16 PM PDT 24 Mar 19 02:58:17 PM PDT 24 14944203 ps
T854 /workspace/coverage/cover_reg_top/2.edn_intr_test.933062367 Mar 19 02:57:48 PM PDT 24 Mar 19 02:57:49 PM PDT 24 17524622 ps
T226 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3072997212 Mar 19 02:57:44 PM PDT 24 Mar 19 02:57:45 PM PDT 24 20640628 ps
T264 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3041913551 Mar 19 02:58:14 PM PDT 24 Mar 19 02:58:16 PM PDT 24 50268744 ps
T855 /workspace/coverage/cover_reg_top/22.edn_intr_test.2824159323 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 15240141 ps
T856 /workspace/coverage/cover_reg_top/30.edn_intr_test.4090086107 Mar 19 02:58:32 PM PDT 24 Mar 19 02:58:34 PM PDT 24 18552252 ps
T857 /workspace/coverage/cover_reg_top/26.edn_intr_test.4065882895 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:09 PM PDT 24 37750045 ps
T858 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3723757632 Mar 19 02:57:55 PM PDT 24 Mar 19 02:57:57 PM PDT 24 39539659 ps
T245 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3085267085 Mar 19 02:57:47 PM PDT 24 Mar 19 02:57:48 PM PDT 24 29044924 ps
T246 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3071674611 Mar 19 02:58:04 PM PDT 24 Mar 19 02:58:05 PM PDT 24 18573205 ps
T859 /workspace/coverage/cover_reg_top/11.edn_intr_test.792179734 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 25205070 ps
T860 /workspace/coverage/cover_reg_top/14.edn_tl_errors.38850453 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:15 PM PDT 24 45072598 ps
T227 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1101612589 Mar 19 02:58:02 PM PDT 24 Mar 19 02:58:03 PM PDT 24 24579893 ps
T861 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2660756881 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:09 PM PDT 24 28814861 ps
T862 /workspace/coverage/cover_reg_top/19.edn_intr_test.2150958351 Mar 19 02:58:17 PM PDT 24 Mar 19 02:58:18 PM PDT 24 92788012 ps
T247 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3708088758 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 20356395 ps
T863 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2027581525 Mar 19 02:58:06 PM PDT 24 Mar 19 02:58:07 PM PDT 24 56763133 ps
T864 /workspace/coverage/cover_reg_top/11.edn_tl_errors.331594555 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:12 PM PDT 24 276046042 ps
T865 /workspace/coverage/cover_reg_top/10.edn_intr_test.2725941063 Mar 19 02:57:55 PM PDT 24 Mar 19 02:57:56 PM PDT 24 13414265 ps
T866 /workspace/coverage/cover_reg_top/17.edn_intr_test.2816357214 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:10 PM PDT 24 31827584 ps
T867 /workspace/coverage/cover_reg_top/46.edn_intr_test.1424953313 Mar 19 02:58:24 PM PDT 24 Mar 19 02:58:25 PM PDT 24 19401917 ps
T868 /workspace/coverage/cover_reg_top/47.edn_intr_test.1938911878 Mar 19 02:58:14 PM PDT 24 Mar 19 02:58:15 PM PDT 24 49283734 ps
T248 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.578900748 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:57 PM PDT 24 28463229 ps
T249 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3461957494 Mar 19 02:58:04 PM PDT 24 Mar 19 02:58:05 PM PDT 24 38001203 ps
T869 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2408546499 Mar 19 02:58:03 PM PDT 24 Mar 19 02:58:04 PM PDT 24 31424580 ps
T870 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4147372912 Mar 19 02:57:55 PM PDT 24 Mar 19 02:57:58 PM PDT 24 227385743 ps
T250 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.717643314 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:13 PM PDT 24 19731880 ps
T871 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.270537909 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 124331627 ps
T228 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1296021528 Mar 19 02:57:52 PM PDT 24 Mar 19 02:57:53 PM PDT 24 45991400 ps
T872 /workspace/coverage/cover_reg_top/14.edn_intr_test.3080978162 Mar 19 02:58:06 PM PDT 24 Mar 19 02:58:07 PM PDT 24 18151073 ps
T873 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3193358930 Mar 19 02:58:02 PM PDT 24 Mar 19 02:58:05 PM PDT 24 94851461 ps
T874 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3187722110 Mar 19 02:58:04 PM PDT 24 Mar 19 02:58:07 PM PDT 24 42815520 ps
T229 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2577937143 Mar 19 02:57:53 PM PDT 24 Mar 19 02:57:54 PM PDT 24 19587648 ps
T875 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1222208791 Mar 19 02:57:54 PM PDT 24 Mar 19 02:57:55 PM PDT 24 33750847 ps
T876 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2559948273 Mar 19 02:58:29 PM PDT 24 Mar 19 02:58:31 PM PDT 24 27530194 ps
T230 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3486764169 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:12 PM PDT 24 28733820 ps
T231 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1461111384 Mar 19 02:57:54 PM PDT 24 Mar 19 02:57:55 PM PDT 24 49930359 ps
T877 /workspace/coverage/cover_reg_top/36.edn_intr_test.3762268165 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:10 PM PDT 24 41241800 ps
T878 /workspace/coverage/cover_reg_top/16.edn_intr_test.4074279039 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 35750620 ps
T879 /workspace/coverage/cover_reg_top/2.edn_tl_errors.917456698 Mar 19 02:57:47 PM PDT 24 Mar 19 02:57:50 PM PDT 24 208518142 ps
T880 /workspace/coverage/cover_reg_top/37.edn_intr_test.1858495989 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:12 PM PDT 24 47794103 ps
T881 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4138500754 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 15610649 ps
T882 /workspace/coverage/cover_reg_top/15.edn_tl_errors.678933128 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:13 PM PDT 24 299434117 ps
T883 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1858071407 Mar 19 02:57:53 PM PDT 24 Mar 19 02:57:55 PM PDT 24 310184740 ps
T884 /workspace/coverage/cover_reg_top/31.edn_intr_test.1198483590 Mar 19 02:58:23 PM PDT 24 Mar 19 02:58:24 PM PDT 24 34061193 ps
T265 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3419488177 Mar 19 02:57:58 PM PDT 24 Mar 19 02:57:59 PM PDT 24 46418759 ps
T885 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.235448695 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:14 PM PDT 24 67978070 ps
T886 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.77043919 Mar 19 02:57:57 PM PDT 24 Mar 19 02:57:58 PM PDT 24 47401437 ps
T887 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3275820945 Mar 19 02:58:13 PM PDT 24 Mar 19 02:58:15 PM PDT 24 18338237 ps
T888 /workspace/coverage/cover_reg_top/43.edn_intr_test.1690455559 Mar 19 02:58:20 PM PDT 24 Mar 19 02:58:21 PM PDT 24 135531893 ps
T232 /workspace/coverage/cover_reg_top/3.edn_csr_rw.907975181 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:10 PM PDT 24 71597793 ps
T889 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.52633808 Mar 19 02:58:18 PM PDT 24 Mar 19 02:58:22 PM PDT 24 500308230 ps
T890 /workspace/coverage/cover_reg_top/9.edn_intr_test.3644510288 Mar 19 02:57:55 PM PDT 24 Mar 19 02:57:56 PM PDT 24 22317609 ps
T233 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3347125660 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:59 PM PDT 24 57744698 ps
T891 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3098030889 Mar 19 02:58:29 PM PDT 24 Mar 19 02:58:34 PM PDT 24 218203813 ps
T892 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1812779526 Mar 19 02:57:52 PM PDT 24 Mar 19 02:57:53 PM PDT 24 64996590 ps
T893 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.684364916 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:10 PM PDT 24 85068045 ps
T894 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1822785716 Mar 19 02:58:10 PM PDT 24 Mar 19 02:58:12 PM PDT 24 267785971 ps
T234 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1031766450 Mar 19 02:57:51 PM PDT 24 Mar 19 02:57:52 PM PDT 24 32736295 ps
T895 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2128812171 Mar 19 02:58:05 PM PDT 24 Mar 19 02:58:08 PM PDT 24 360355709 ps
T896 /workspace/coverage/cover_reg_top/42.edn_intr_test.357188272 Mar 19 02:58:27 PM PDT 24 Mar 19 02:58:28 PM PDT 24 11945752 ps
T897 /workspace/coverage/cover_reg_top/25.edn_intr_test.2419811014 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 16940857 ps
T898 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4258958478 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 38098319 ps
T899 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1664272159 Mar 19 02:58:03 PM PDT 24 Mar 19 02:58:04 PM PDT 24 15988566 ps
T900 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.344569887 Mar 19 02:57:48 PM PDT 24 Mar 19 02:57:49 PM PDT 24 21366437 ps
T901 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1751337228 Mar 19 02:58:17 PM PDT 24 Mar 19 02:58:18 PM PDT 24 27430856 ps
T902 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3465105699 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:10 PM PDT 24 140029413 ps
T903 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3640116553 Mar 19 02:58:06 PM PDT 24 Mar 19 02:58:07 PM PDT 24 31888101 ps
T904 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1334820686 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:09 PM PDT 24 28109301 ps
T263 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2003298470 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:03 PM PDT 24 157853603 ps
T905 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1093338056 Mar 19 02:58:03 PM PDT 24 Mar 19 02:58:06 PM PDT 24 281063607 ps
T906 /workspace/coverage/cover_reg_top/8.edn_intr_test.3130072372 Mar 19 02:57:57 PM PDT 24 Mar 19 02:57:58 PM PDT 24 79987174 ps
T907 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4193146907 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 101421867 ps
T908 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.692231616 Mar 19 02:57:57 PM PDT 24 Mar 19 02:58:03 PM PDT 24 228914566 ps
T909 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.537062937 Mar 19 02:58:10 PM PDT 24 Mar 19 02:58:12 PM PDT 24 56310844 ps
T910 /workspace/coverage/cover_reg_top/48.edn_intr_test.323189802 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:13 PM PDT 24 21413767 ps
T911 /workspace/coverage/cover_reg_top/13.edn_intr_test.404549694 Mar 19 02:58:00 PM PDT 24 Mar 19 02:58:01 PM PDT 24 11382232 ps
T912 /workspace/coverage/cover_reg_top/40.edn_intr_test.1690033363 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:13 PM PDT 24 13655542 ps
T913 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3819006247 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 121415941 ps
T914 /workspace/coverage/cover_reg_top/3.edn_intr_test.1136233493 Mar 19 02:57:47 PM PDT 24 Mar 19 02:57:48 PM PDT 24 35861691 ps
T915 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.140132740 Mar 19 02:57:59 PM PDT 24 Mar 19 02:58:01 PM PDT 24 51297129 ps
T916 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2757742100 Mar 19 02:58:06 PM PDT 24 Mar 19 02:58:08 PM PDT 24 27387891 ps
T235 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2648486392 Mar 19 02:57:57 PM PDT 24 Mar 19 02:58:03 PM PDT 24 453203433 ps
T917 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1315748344 Mar 19 02:57:59 PM PDT 24 Mar 19 02:58:00 PM PDT 24 35506163 ps
T918 /workspace/coverage/cover_reg_top/44.edn_intr_test.1256866275 Mar 19 02:58:10 PM PDT 24 Mar 19 02:58:11 PM PDT 24 13173270 ps
T919 /workspace/coverage/cover_reg_top/23.edn_intr_test.2068001606 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:12 PM PDT 24 117157099 ps
T920 /workspace/coverage/cover_reg_top/27.edn_intr_test.2150529586 Mar 19 02:58:22 PM PDT 24 Mar 19 02:58:23 PM PDT 24 121333395 ps
T921 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.285978649 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:57 PM PDT 24 102319706 ps
T922 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1792361143 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 62813600 ps
T923 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3129965297 Mar 19 02:58:10 PM PDT 24 Mar 19 02:58:15 PM PDT 24 570424386 ps
T924 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2494864285 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:10 PM PDT 24 290941574 ps
T925 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3560427292 Mar 19 02:58:06 PM PDT 24 Mar 19 02:58:11 PM PDT 24 262478619 ps
T236 /workspace/coverage/cover_reg_top/17.edn_csr_rw.775955666 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:12 PM PDT 24 14723234 ps
T926 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3148463126 Mar 19 02:57:56 PM PDT 24 Mar 19 02:58:01 PM PDT 24 205474615 ps
T927 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3217022898 Mar 19 02:57:45 PM PDT 24 Mar 19 02:57:46 PM PDT 24 14820699 ps
T928 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3675680166 Mar 19 02:57:59 PM PDT 24 Mar 19 02:58:00 PM PDT 24 62984636 ps
T929 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1818221404 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:57 PM PDT 24 30772291 ps
T930 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2954578098 Mar 19 02:57:51 PM PDT 24 Mar 19 02:57:53 PM PDT 24 35951216 ps
T931 /workspace/coverage/cover_reg_top/32.edn_intr_test.2254847278 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:13 PM PDT 24 51348709 ps
T237 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3077143081 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:57 PM PDT 24 17646362 ps
T932 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4137783126 Mar 19 02:57:45 PM PDT 24 Mar 19 02:57:47 PM PDT 24 84902162 ps
T238 /workspace/coverage/cover_reg_top/14.edn_csr_rw.710386397 Mar 19 02:58:13 PM PDT 24 Mar 19 02:58:14 PM PDT 24 10917194 ps
T933 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.240285854 Mar 19 02:58:12 PM PDT 24 Mar 19 02:58:14 PM PDT 24 296285561 ps
T934 /workspace/coverage/cover_reg_top/9.edn_csr_rw.157805264 Mar 19 02:57:58 PM PDT 24 Mar 19 02:57:59 PM PDT 24 15500731 ps
T935 /workspace/coverage/cover_reg_top/6.edn_intr_test.3218814431 Mar 19 02:57:58 PM PDT 24 Mar 19 02:57:59 PM PDT 24 18208262 ps
T936 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4135885007 Mar 19 02:58:03 PM PDT 24 Mar 19 02:58:04 PM PDT 24 108320362 ps
T937 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2910900491 Mar 19 02:57:48 PM PDT 24 Mar 19 02:57:50 PM PDT 24 32744848 ps
T938 /workspace/coverage/cover_reg_top/12.edn_intr_test.2055100148 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 14764256 ps
T939 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2601409593 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:10 PM PDT 24 41985103 ps
T940 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2171282575 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:09 PM PDT 24 25688119 ps
T941 /workspace/coverage/cover_reg_top/21.edn_intr_test.3699614048 Mar 19 02:58:15 PM PDT 24 Mar 19 02:58:17 PM PDT 24 18530709 ps
T942 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1695347728 Mar 19 02:57:58 PM PDT 24 Mar 19 02:58:01 PM PDT 24 43513769 ps
T943 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2994254995 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:10 PM PDT 24 32389055 ps
T239 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1107490650 Mar 19 02:57:47 PM PDT 24 Mar 19 02:57:48 PM PDT 24 151702174 ps
T944 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3539181180 Mar 19 02:57:51 PM PDT 24 Mar 19 02:57:52 PM PDT 24 39117996 ps
T945 /workspace/coverage/cover_reg_top/49.edn_intr_test.2550260576 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:12 PM PDT 24 19664954 ps
T946 /workspace/coverage/cover_reg_top/9.edn_tl_errors.208848924 Mar 19 02:57:58 PM PDT 24 Mar 19 02:58:01 PM PDT 24 65726263 ps
T947 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1643165687 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:09 PM PDT 24 131232141 ps
T948 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.525586686 Mar 19 02:57:55 PM PDT 24 Mar 19 02:57:56 PM PDT 24 25013484 ps
T949 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.588471049 Mar 19 02:58:09 PM PDT 24 Mar 19 02:58:11 PM PDT 24 170096511 ps
T950 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3651260726 Mar 19 02:58:00 PM PDT 24 Mar 19 02:58:02 PM PDT 24 147962547 ps
T240 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.57667473 Mar 19 02:57:58 PM PDT 24 Mar 19 02:57:59 PM PDT 24 24556955 ps
T951 /workspace/coverage/cover_reg_top/0.edn_intr_test.589662677 Mar 19 02:57:48 PM PDT 24 Mar 19 02:57:49 PM PDT 24 25630689 ps
T243 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3575229935 Mar 19 02:57:55 PM PDT 24 Mar 19 02:57:56 PM PDT 24 27347495 ps
T952 /workspace/coverage/cover_reg_top/28.edn_intr_test.2250422432 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:09 PM PDT 24 22329689 ps
T241 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.355649081 Mar 19 02:57:45 PM PDT 24 Mar 19 02:57:49 PM PDT 24 536526036 ps
T953 /workspace/coverage/cover_reg_top/4.edn_intr_test.1186761138 Mar 19 02:57:58 PM PDT 24 Mar 19 02:57:59 PM PDT 24 37713654 ps
T954 /workspace/coverage/cover_reg_top/1.edn_intr_test.3173939647 Mar 19 02:57:50 PM PDT 24 Mar 19 02:57:51 PM PDT 24 30129962 ps
T955 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3137453388 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:03 PM PDT 24 55059281 ps
T956 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4180882004 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 19709606 ps
T957 /workspace/coverage/cover_reg_top/15.edn_intr_test.2996432980 Mar 19 02:57:56 PM PDT 24 Mar 19 02:57:57 PM PDT 24 25010904 ps
T958 /workspace/coverage/cover_reg_top/38.edn_intr_test.3119278493 Mar 19 02:58:17 PM PDT 24 Mar 19 02:58:18 PM PDT 24 10325328 ps
T959 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1543838115 Mar 19 02:57:58 PM PDT 24 Mar 19 02:58:00 PM PDT 24 65725180 ps
T242 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3940248984 Mar 19 02:57:57 PM PDT 24 Mar 19 02:57:58 PM PDT 24 26819817 ps
T960 /workspace/coverage/cover_reg_top/7.edn_intr_test.3106578717 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 15911292 ps
T961 /workspace/coverage/cover_reg_top/45.edn_intr_test.1141325561 Mar 19 02:58:13 PM PDT 24 Mar 19 02:58:14 PM PDT 24 62354070 ps
T962 /workspace/coverage/cover_reg_top/18.edn_intr_test.560431134 Mar 19 02:58:11 PM PDT 24 Mar 19 02:58:12 PM PDT 24 43968632 ps
T963 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3526334572 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 42352058 ps
T964 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2968070383 Mar 19 02:57:54 PM PDT 24 Mar 19 02:57:56 PM PDT 24 282575093 ps
T965 /workspace/coverage/cover_reg_top/35.edn_intr_test.1604563282 Mar 19 02:58:20 PM PDT 24 Mar 19 02:58:22 PM PDT 24 15045038 ps
T966 /workspace/coverage/cover_reg_top/20.edn_intr_test.3891159241 Mar 19 02:58:08 PM PDT 24 Mar 19 02:58:09 PM PDT 24 31517883 ps
T967 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1282614357 Mar 19 02:57:58 PM PDT 24 Mar 19 02:57:59 PM PDT 24 24457260 ps
T968 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3427093068 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:08 PM PDT 24 24167761 ps
T969 /workspace/coverage/cover_reg_top/29.edn_intr_test.1807392827 Mar 19 02:58:04 PM PDT 24 Mar 19 02:58:05 PM PDT 24 45829339 ps
T970 /workspace/coverage/cover_reg_top/24.edn_intr_test.314414805 Mar 19 02:58:02 PM PDT 24 Mar 19 02:58:03 PM PDT 24 70333621 ps
T971 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.544798799 Mar 19 02:58:01 PM PDT 24 Mar 19 02:58:02 PM PDT 24 27933301 ps
T972 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2190212415 Mar 19 02:58:07 PM PDT 24 Mar 19 02:58:09 PM PDT 24 180080418 ps
T973 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2973459046 Mar 19 02:57:54 PM PDT 24 Mar 19 02:57:57 PM PDT 24 132734557 ps
T974 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1484772938 Mar 19 02:57:59 PM PDT 24 Mar 19 02:58:00 PM PDT 24 15036012 ps

Test location /workspace/coverage/default/33.edn_genbits.2456574790
Short name T2
Test name
Test status
Simulation time 400887150 ps
CPU time 4.49 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 216936 kb
Host smart-e2215f19-c722-4214-aa62-b8c052664aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456574790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2456574790
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1892455789
Short name T24
Test name
Test status
Simulation time 39088048535 ps
CPU time 845.54 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 03:09:54 PM PDT 24
Peak memory 223936 kb
Host smart-69b5ced6-7261-4462-adc1-817d1a56ba4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892455789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1892455789
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.380217302
Short name T12
Test name
Test status
Simulation time 85260624 ps
CPU time 1.13 seconds
Started Mar 19 02:56:00 PM PDT 24
Finished Mar 19 02:56:01 PM PDT 24
Peak memory 215800 kb
Host smart-c1b21e7a-1e3e-4140-97e9-e37b74341cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380217302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.380217302
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1704821875
Short name T55
Test name
Test status
Simulation time 758893543 ps
CPU time 6.37 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 235712 kb
Host smart-33f6fffb-cd84-4944-8221-bb5d767198a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704821875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1704821875
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_err.1318533136
Short name T5
Test name
Test status
Simulation time 34502226 ps
CPU time 1.09 seconds
Started Mar 19 02:55:56 PM PDT 24
Finished Mar 19 02:55:57 PM PDT 24
Peak memory 218236 kb
Host smart-d3605276-0a3f-4d85-9f6b-55a9eddd00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318533136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1318533136
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3845474546
Short name T140
Test name
Test status
Simulation time 37907203 ps
CPU time 0.97 seconds
Started Mar 19 02:56:42 PM PDT 24
Finished Mar 19 02:56:44 PM PDT 24
Peak memory 217708 kb
Host smart-72fb3c2f-4a5b-4dfb-817c-9eaa5d0ec2ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845474546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3845474546
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.1463995857
Short name T37
Test name
Test status
Simulation time 144759657 ps
CPU time 1.39 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:55:48 PM PDT 24
Peak memory 218100 kb
Host smart-30cccc70-545a-44e4-81f2-a48454bda81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463995857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1463995857
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.385437410
Short name T16
Test name
Test status
Simulation time 39590733 ps
CPU time 1.08 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 02:56:35 PM PDT 24
Peak memory 215836 kb
Host smart-3fac6cb1-c2f9-4fc7-90a4-74b4c2d5ff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385437410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.385437410
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3231261867
Short name T206
Test name
Test status
Simulation time 57217909858 ps
CPU time 1272.56 seconds
Started Mar 19 02:56:21 PM PDT 24
Finished Mar 19 03:17:34 PM PDT 24
Peak memory 221204 kb
Host smart-3313bc4a-af28-40ea-9b15-ba330cc20b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231261867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3231261867
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_disable.3148207780
Short name T27
Test name
Test status
Simulation time 11799664 ps
CPU time 0.94 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 216156 kb
Host smart-fe0560d1-abf9-422d-938e-4a305da335e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148207780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3148207780
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/1.edn_regwen.92175110
Short name T272
Test name
Test status
Simulation time 215440572 ps
CPU time 0.97 seconds
Started Mar 19 02:55:43 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 207216 kb
Host smart-6270466c-76ba-4951-9f2f-1b2812afa2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92175110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.92175110
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_intr.1025561793
Short name T66
Test name
Test status
Simulation time 26097417 ps
CPU time 0.91 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 216032 kb
Host smart-005e80ac-2317-4710-bb1c-347f8b43e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025561793 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1025561793
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/22.edn_alert.819145792
Short name T473
Test name
Test status
Simulation time 28040362 ps
CPU time 1.29 seconds
Started Mar 19 02:56:25 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 215792 kb
Host smart-3cba1572-571e-4b67-91f7-36f2e64611ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819145792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.819145792
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.758519251
Short name T255
Test name
Test status
Simulation time 139855438 ps
CPU time 2.14 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:58:00 PM PDT 24
Peak memory 206216 kb
Host smart-b456c7fd-8a24-4020-bdbe-d43f21121540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758519251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.758519251
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3322455168
Short name T225
Test name
Test status
Simulation time 37856144 ps
CPU time 0.86 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 205812 kb
Host smart-f3f3d4f7-cbcb-4b07-aa9f-796fe25f3bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322455168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3322455168
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2497076748
Short name T75
Test name
Test status
Simulation time 41003677 ps
CPU time 1.31 seconds
Started Mar 19 02:56:40 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 216568 kb
Host smart-d10daa6b-9876-4a95-81fe-f445b20c5bb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497076748 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2497076748
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_sec_cm.311424200
Short name T18
Test name
Test status
Simulation time 5757126126 ps
CPU time 6.28 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:56:05 PM PDT 24
Peak memory 236244 kb
Host smart-ae9efdf8-961f-4b78-862d-2b85a63c3c99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311424200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.311424200
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/21.edn_alert.3801655796
Short name T111
Test name
Test status
Simulation time 30322691 ps
CPU time 1.28 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:24 PM PDT 24
Peak memory 215812 kb
Host smart-d7627ede-0700-4e20-9a67-384211da9ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801655796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3801655796
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2631145677
Short name T76
Test name
Test status
Simulation time 41448589 ps
CPU time 1.36 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 216636 kb
Host smart-0fe8f8e8-329f-459c-b691-a6bf2f8063e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631145677 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2631145677
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_disable.801584763
Short name T109
Test name
Test status
Simulation time 50089760 ps
CPU time 0.91 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 216056 kb
Host smart-0dbd6855-ef35-411c-a635-cf5276050a44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801584763 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.801584763
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.3842259283
Short name T119
Test name
Test status
Simulation time 17739824 ps
CPU time 0.82 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 215988 kb
Host smart-9dd13bec-8cdc-4cd4-9968-346249055e2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842259283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3842259283
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/16.edn_intr.205376405
Short name T135
Test name
Test status
Simulation time 20371254 ps
CPU time 1.08 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 216020 kb
Host smart-8c5d3976-df0e-4cfe-9db9-14547d644f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205376405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.205376405
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/66.edn_genbits.2368587011
Short name T29
Test name
Test status
Simulation time 83253872 ps
CPU time 1.83 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 218208 kb
Host smart-b661a675-3d51-47e0-ade4-f3ae20441000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368587011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2368587011
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3552563702
Short name T32
Test name
Test status
Simulation time 37838406 ps
CPU time 1.36 seconds
Started Mar 19 02:56:08 PM PDT 24
Finished Mar 19 02:56:09 PM PDT 24
Peak memory 216628 kb
Host smart-0ac0be0b-1fe9-468b-a54c-4ade54524248
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552563702 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3552563702
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2728150059
Short name T44
Test name
Test status
Simulation time 23470784 ps
CPU time 0.99 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 232556 kb
Host smart-16d7c3c0-8d60-4f9c-8c7f-e8a09a8738a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728150059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2728150059
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/223.edn_genbits.1656857608
Short name T154
Test name
Test status
Simulation time 34067588 ps
CPU time 1.3 seconds
Started Mar 19 02:57:44 PM PDT 24
Finished Mar 19 02:57:46 PM PDT 24
Peak memory 218096 kb
Host smart-516c10de-d329-46dd-beb9-25ffca55a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656857608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1656857608
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/240.edn_genbits.596348527
Short name T283
Test name
Test status
Simulation time 46410697 ps
CPU time 1.18 seconds
Started Mar 19 02:57:42 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 217920 kb
Host smart-67fca7eb-ac90-4763-8f7b-c698d1ae355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596348527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.596348527
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_alert.3414571021
Short name T256
Test name
Test status
Simulation time 33565407 ps
CPU time 1.36 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215760 kb
Host smart-9ffb9080-1bf4-477d-85cb-e7f26ee33fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414571021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3414571021
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.116337735
Short name T167
Test name
Test status
Simulation time 21688605 ps
CPU time 0.88 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 215996 kb
Host smart-0b5f617e-d65d-4b5f-b76d-977ebdbc8003
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116337735 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.116337735
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3354912146
Short name T98
Test name
Test status
Simulation time 70732052 ps
CPU time 1.27 seconds
Started Mar 19 02:56:01 PM PDT 24
Finished Mar 19 02:56:03 PM PDT 24
Peak memory 216636 kb
Host smart-e17e263b-02da-4876-aa17-f959c3f5d586
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354912146 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3354912146
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.4150366731
Short name T598
Test name
Test status
Simulation time 11659421 ps
CPU time 0.89 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 215752 kb
Host smart-4f90c0bf-d1b6-4e08-a074-f3276a515ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150366731 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4150366731
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.2288221862
Short name T177
Test name
Test status
Simulation time 43426967 ps
CPU time 0.9 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 216016 kb
Host smart-a91edc7e-d4d1-4069-98d5-7c582e93ca8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288221862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2288221862
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable.1822045937
Short name T184
Test name
Test status
Simulation time 28120556 ps
CPU time 0.79 seconds
Started Mar 19 02:56:42 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 215980 kb
Host smart-33d2e04b-39c0-44e8-a787-1db7ca894e5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822045937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1822045937
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1883307932
Short name T89
Test name
Test status
Simulation time 22084887 ps
CPU time 1.05 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:48 PM PDT 24
Peak memory 218068 kb
Host smart-ef2629e3-62ac-402d-ad79-0196f441f093
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883307932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1883307932
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1347344654
Short name T101
Test name
Test status
Simulation time 265488495 ps
CPU time 1.07 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 216696 kb
Host smart-6817e343-9d62-451a-a131-17563b88e79e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347344654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1347344654
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.3992960147
Short name T174
Test name
Test status
Simulation time 14759598 ps
CPU time 0.94 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 216252 kb
Host smart-2adb3112-26e8-48dd-8ef2-7d6f714aeb0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992960147 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3992960147
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.2068346627
Short name T123
Test name
Test status
Simulation time 34375866 ps
CPU time 0.89 seconds
Started Mar 19 02:56:21 PM PDT 24
Finished Mar 19 02:56:22 PM PDT 24
Peak memory 215988 kb
Host smart-b5a049ac-2a7e-4bde-a0b9-cb920546a102
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068346627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2068346627
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.3399191955
Short name T189
Test name
Test status
Simulation time 17820941 ps
CPU time 0.86 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 216020 kb
Host smart-6cfcce62-b323-40ce-9390-aba6ed8b5e6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399191955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3399191955
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3684753496
Short name T185
Test name
Test status
Simulation time 111706331 ps
CPU time 1.09 seconds
Started Mar 19 02:56:44 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 216544 kb
Host smart-6475ed90-e74f-4115-afd1-7e47fbd50c3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684753496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3684753496
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_disable.3588296224
Short name T168
Test name
Test status
Simulation time 11875062 ps
CPU time 0.91 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 216284 kb
Host smart-cef3bda3-a641-482d-a434-5288df975fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588296224 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3588296224
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2808911663
Short name T84
Test name
Test status
Simulation time 46376181 ps
CPU time 1.23 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 02:56:56 PM PDT 24
Peak memory 216492 kb
Host smart-a8eb8d39-d54d-4ac8-b82c-151dfd4470d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808911663 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2808911663
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_disable.720320354
Short name T173
Test name
Test status
Simulation time 12851386 ps
CPU time 0.91 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 216192 kb
Host smart-768b0134-86b8-4b6c-b4f7-f72b6fdbb183
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720320354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.720320354
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/16.edn_alert_test.2821429469
Short name T321
Test name
Test status
Simulation time 53659807 ps
CPU time 0.97 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 02:56:16 PM PDT 24
Peak memory 206660 kb
Host smart-c7ac28d3-e5d3-4c8a-8ad1-6a1a76f3ba72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821429469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2821429469
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_genbits.2930072817
Short name T281
Test name
Test status
Simulation time 104816534 ps
CPU time 1.13 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:54 PM PDT 24
Peak memory 219760 kb
Host smart-fc06f830-ebc3-4d87-ad04-32c18ecece2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930072817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2930072817
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.225946907
Short name T268
Test name
Test status
Simulation time 35452643 ps
CPU time 0.96 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 207224 kb
Host smart-14600909-3cfb-42af-8c7f-6190fad48848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225946907 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.225946907
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/166.edn_genbits.2860335878
Short name T71
Test name
Test status
Simulation time 90541347 ps
CPU time 2.47 seconds
Started Mar 19 02:57:28 PM PDT 24
Finished Mar 19 02:57:31 PM PDT 24
Peak memory 219476 kb
Host smart-c23fc52b-399a-4e99-bfd0-c8958962e53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860335878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2860335878
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.40519538
Short name T132
Test name
Test status
Simulation time 211127310 ps
CPU time 0.93 seconds
Started Mar 19 02:56:00 PM PDT 24
Finished Mar 19 02:56:01 PM PDT 24
Peak memory 207232 kb
Host smart-3378deda-9268-4eb8-b9c9-ccc2a48b069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40519538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.40519538
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/22.edn_intr.1120042331
Short name T134
Test name
Test status
Simulation time 23826107 ps
CPU time 0.93 seconds
Started Mar 19 02:56:20 PM PDT 24
Finished Mar 19 02:56:21 PM PDT 24
Peak memory 215812 kb
Host smart-d466ed42-296b-4481-9ae9-bc098f00ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120042331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1120042331
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.355649081
Short name T241
Test name
Test status
Simulation time 536526036 ps
CPU time 3.58 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 206008 kb
Host smart-1f6a7746-a21c-4ad5-b913-8333f49bcf51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355649081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.355649081
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/105.edn_genbits.3631069013
Short name T223
Test name
Test status
Simulation time 23826743 ps
CPU time 1.11 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:23 PM PDT 24
Peak memory 216740 kb
Host smart-9f0e718f-cdbf-454b-bd14-09fcd188b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631069013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3631069013
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3580047799
Short name T289
Test name
Test status
Simulation time 65977454 ps
CPU time 2.57 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 219708 kb
Host smart-00a7b25d-c45e-442c-a885-d079c191467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580047799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3580047799
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1837121154
Short name T618
Test name
Test status
Simulation time 36312368 ps
CPU time 1.15 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216584 kb
Host smart-cf20a1fc-7bbf-43f2-b468-fc9889686628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837121154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1837121154
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.969187977
Short name T260
Test name
Test status
Simulation time 47552762 ps
CPU time 1.63 seconds
Started Mar 19 02:57:43 PM PDT 24
Finished Mar 19 02:57:44 PM PDT 24
Peak memory 217992 kb
Host smart-536bc8e1-e4a1-42c3-aabc-c4a70d7a30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969187977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.969187977
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.34155647
Short name T303
Test name
Test status
Simulation time 153386385 ps
CPU time 3.15 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:23 PM PDT 24
Peak memory 218080 kb
Host smart-3fa87e99-5d24-42be-befa-d187ef0e5f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34155647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.34155647
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3667773180
Short name T196
Test name
Test status
Simulation time 119873459 ps
CPU time 1.07 seconds
Started Mar 19 02:57:28 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 216820 kb
Host smart-9dce1be3-54ae-4982-a855-c9229343ea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667773180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3667773180
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_genbits.131444443
Short name T280
Test name
Test status
Simulation time 31371664 ps
CPU time 1.37 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 217904 kb
Host smart-3fea9d9d-c6ce-4356-afa7-89021a6720ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131444443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.131444443
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3739531606
Short name T677
Test name
Test status
Simulation time 41755858 ps
CPU time 1.31 seconds
Started Mar 19 02:57:41 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 217952 kb
Host smart-0d08cfbb-a579-4477-9d32-9b5e0575f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739531606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3739531606
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2690975580
Short name T299
Test name
Test status
Simulation time 84604480 ps
CPU time 1.18 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 216604 kb
Host smart-844b1b8a-3516-4519-8fb1-0ddc58078bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690975580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2690975580
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4005572490
Short name T302
Test name
Test status
Simulation time 101189600 ps
CPU time 1.37 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 218336 kb
Host smart-393959dc-3b38-44a6-9d50-c2481d513e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005572490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4005572490
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_genbits.2697831682
Short name T292
Test name
Test status
Simulation time 81898005 ps
CPU time 1.04 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 219472 kb
Host smart-f142ec2a-daf0-45d2-ab8f-efcd54111d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697831682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2697831682
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.993592993
Short name T53
Test name
Test status
Simulation time 94437273 ps
CPU time 1.48 seconds
Started Mar 19 02:57:46 PM PDT 24
Finished Mar 19 02:57:47 PM PDT 24
Peak memory 218268 kb
Host smart-37419fc6-67ef-4aee-be18-1d7a42f4a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993592993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.993592993
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_alert.466018116
Short name T202
Test name
Test status
Simulation time 47426046 ps
CPU time 1.24 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 215696 kb
Host smart-d19e24cb-36a0-4ef8-a7e3-6af83772e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466018116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.466018116
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/34.edn_intr.1204196665
Short name T4
Test name
Test status
Simulation time 21803670 ps
CPU time 0.97 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215844 kb
Host smart-efbec0ab-44cf-461d-8742-2e6a427ba0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204196665 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1204196665
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/1.edn_intr.4138983818
Short name T138
Test name
Test status
Simulation time 21280108 ps
CPU time 1 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 215888 kb
Host smart-d5081365-eb31-458a-a2ce-3cbd81aa348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138983818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4138983818
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/127.edn_genbits.216514212
Short name T356
Test name
Test status
Simulation time 32225326 ps
CPU time 1.31 seconds
Started Mar 19 02:57:37 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 216992 kb
Host smart-a6e8e087-cce4-40b3-b70b-1a3a61d420cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216514212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.216514212
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1942042655
Short name T251
Test name
Test status
Simulation time 86643939 ps
CPU time 1.22 seconds
Started Mar 19 02:57:44 PM PDT 24
Finished Mar 19 02:57:45 PM PDT 24
Peak memory 206064 kb
Host smart-021d5cbf-b1cc-419e-9682-c2b323d0b899
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942042655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1942042655
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.344569887
Short name T900
Test name
Test status
Simulation time 21366437 ps
CPU time 0.88 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 205828 kb
Host smart-8ce10b7b-9bd2-4833-8018-511cf42ce701
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344569887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.344569887
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.525586686
Short name T948
Test name
Test status
Simulation time 25013484 ps
CPU time 1.3 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 214388 kb
Host smart-1179bb7a-081a-43de-9435-74dbc8c4b0d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525586686 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.525586686
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3217022898
Short name T927
Test name
Test status
Simulation time 14820699 ps
CPU time 0.92 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:46 PM PDT 24
Peak memory 206012 kb
Host smart-a2ccc13d-febe-449a-b8ba-35561c60095f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217022898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3217022898
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.589662677
Short name T951
Test name
Test status
Simulation time 25630689 ps
CPU time 0.86 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 205996 kb
Host smart-0b1a2b34-8931-4c89-b150-0dd60a6dd934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589662677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.589662677
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3072997212
Short name T226
Test name
Test status
Simulation time 20640628 ps
CPU time 1.21 seconds
Started Mar 19 02:57:44 PM PDT 24
Finished Mar 19 02:57:45 PM PDT 24
Peak memory 206152 kb
Host smart-35d4b636-3bac-4eea-806d-9c8e9b56a548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072997212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3072997212
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2968070383
Short name T964
Test name
Test status
Simulation time 282575093 ps
CPU time 2.19 seconds
Started Mar 19 02:57:54 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 214840 kb
Host smart-7eb0cdea-cfc1-4ee9-9ff6-3ce8691f9932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968070383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2968070383
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4137783126
Short name T932
Test name
Test status
Simulation time 84902162 ps
CPU time 1.84 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:47 PM PDT 24
Peak memory 206108 kb
Host smart-864b77a6-c2d1-480c-a314-50bb8fb7b7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137783126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4137783126
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1107490650
Short name T239
Test name
Test status
Simulation time 151702174 ps
CPU time 1.48 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:48 PM PDT 24
Peak memory 206024 kb
Host smart-006ab0c8-dd7d-4393-941f-7778e584ffca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107490650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1107490650
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.692231616
Short name T908
Test name
Test status
Simulation time 228914566 ps
CPU time 6.3 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 205992 kb
Host smart-28a17565-22a6-4855-adee-c36b52e54805
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692231616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.692231616
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1461111384
Short name T231
Test name
Test status
Simulation time 49930359 ps
CPU time 0.93 seconds
Started Mar 19 02:57:54 PM PDT 24
Finished Mar 19 02:57:55 PM PDT 24
Peak memory 205996 kb
Host smart-11a2a5aa-e81c-4d52-9eee-ff825ac2d077
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461111384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1461111384
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2171282575
Short name T940
Test name
Test status
Simulation time 25688119 ps
CPU time 1.57 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 214420 kb
Host smart-4b2b6384-578f-40f6-9201-27929bb92881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171282575 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2171282575
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3085267085
Short name T245
Test name
Test status
Simulation time 29044924 ps
CPU time 0.93 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:48 PM PDT 24
Peak memory 205992 kb
Host smart-ae70330a-5c10-4a47-8d05-b39026ebbe73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085267085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3085267085
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3173939647
Short name T954
Test name
Test status
Simulation time 30129962 ps
CPU time 0.93 seconds
Started Mar 19 02:57:50 PM PDT 24
Finished Mar 19 02:57:51 PM PDT 24
Peak memory 205992 kb
Host smart-760099c8-4114-48bc-a249-4f37d96debdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173939647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3173939647
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2910900491
Short name T937
Test name
Test status
Simulation time 32744848 ps
CPU time 1.4 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:50 PM PDT 24
Peak memory 206160 kb
Host smart-7ac86129-c79c-4b2d-a2ee-158a146a55d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910900491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2910900491
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1409293805
Short name T844
Test name
Test status
Simulation time 105845780 ps
CPU time 4.28 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:05 PM PDT 24
Peak memory 214368 kb
Host smart-15127b48-935c-4c54-aa74-9bc68078b2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409293805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1409293805
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1858071407
Short name T883
Test name
Test status
Simulation time 310184740 ps
CPU time 2.32 seconds
Started Mar 19 02:57:53 PM PDT 24
Finished Mar 19 02:57:55 PM PDT 24
Peak memory 206224 kb
Host smart-f71b40b1-e7a3-4592-9474-e2338677ce78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858071407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1858071407
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1222208791
Short name T875
Test name
Test status
Simulation time 33750847 ps
CPU time 1.27 seconds
Started Mar 19 02:57:54 PM PDT 24
Finished Mar 19 02:57:55 PM PDT 24
Peak memory 214472 kb
Host smart-082ff3f6-97aa-4491-9b46-f21ecd23abc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222208791 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1222208791
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2577937143
Short name T229
Test name
Test status
Simulation time 19587648 ps
CPU time 0.86 seconds
Started Mar 19 02:57:53 PM PDT 24
Finished Mar 19 02:57:54 PM PDT 24
Peak memory 206048 kb
Host smart-49275e6d-4890-481d-a6d7-2e84126dc0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577937143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2577937143
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2725941063
Short name T865
Test name
Test status
Simulation time 13414265 ps
CPU time 0.89 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 206016 kb
Host smart-0a876aa1-ae0c-4ec7-9202-1178c9c26968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725941063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2725941063
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1101612589
Short name T227
Test name
Test status
Simulation time 24579893 ps
CPU time 1 seconds
Started Mar 19 02:58:02 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 206172 kb
Host smart-cef4b3e3-62cc-448b-88a7-0ee05124092b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101612589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1101612589
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3427093068
Short name T968
Test name
Test status
Simulation time 24167761 ps
CPU time 1.29 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 214396 kb
Host smart-fdad7b7e-9afd-446b-ae14-2120e2bc7ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427093068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3427093068
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.140132740
Short name T915
Test name
Test status
Simulation time 51297129 ps
CPU time 1.79 seconds
Started Mar 19 02:57:59 PM PDT 24
Finished Mar 19 02:58:01 PM PDT 24
Peak memory 206136 kb
Host smart-66631c8e-3c2c-4e0e-97ef-86419b9d8923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140132740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.140132740
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1543838115
Short name T959
Test name
Test status
Simulation time 65725180 ps
CPU time 1.45 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:58:00 PM PDT 24
Peak memory 214516 kb
Host smart-034c0fca-66db-4a90-966d-d7f8a6b98703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543838115 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1543838115
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3940248984
Short name T242
Test name
Test status
Simulation time 26819817 ps
CPU time 0.87 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 205828 kb
Host smart-7258ec6e-012c-4829-85a6-205104f9440d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940248984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3940248984
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.792179734
Short name T859
Test name
Test status
Simulation time 25205070 ps
CPU time 0.8 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 205808 kb
Host smart-d50756ec-e7e7-4b5c-bc1c-b9a8bc51b29d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792179734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.792179734
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2994254995
Short name T943
Test name
Test status
Simulation time 32389055 ps
CPU time 1.24 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 206116 kb
Host smart-628b00f5-d961-4589-bbb7-843cb1e361c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994254995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2994254995
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.331594555
Short name T864
Test name
Test status
Simulation time 276046042 ps
CPU time 4.56 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 217836 kb
Host smart-473d44b5-df12-4f3e-aca1-1d03cc1b3e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331594555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.331594555
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.317117451
Short name T852
Test name
Test status
Simulation time 90056555 ps
CPU time 1.59 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:14 PM PDT 24
Peak memory 206180 kb
Host smart-848e735e-bcd2-4be6-a8ff-45f42ab69bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317117451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.317117451
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.52633808
Short name T889
Test name
Test status
Simulation time 500308230 ps
CPU time 2.48 seconds
Started Mar 19 02:58:18 PM PDT 24
Finished Mar 19 02:58:22 PM PDT 24
Peak memory 214488 kb
Host smart-090723e0-3c4d-4731-b2e8-d22182629953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52633808 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.52633808
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3486764169
Short name T230
Test name
Test status
Simulation time 28733820 ps
CPU time 0.8 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 205792 kb
Host smart-bfbb3f8f-d233-46d3-9492-003b87c6013b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486764169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3486764169
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2055100148
Short name T938
Test name
Test status
Simulation time 14764256 ps
CPU time 0.92 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 206020 kb
Host smart-f9ae1900-ec0d-495c-b910-0acd30605f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055100148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2055100148
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4135885007
Short name T936
Test name
Test status
Simulation time 108320362 ps
CPU time 1.41 seconds
Started Mar 19 02:58:03 PM PDT 24
Finished Mar 19 02:58:04 PM PDT 24
Peak memory 206188 kb
Host smart-e342e305-187e-4c5a-b9d7-84252a8c40d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135885007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4135885007
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1695347728
Short name T942
Test name
Test status
Simulation time 43513769 ps
CPU time 2.91 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:58:01 PM PDT 24
Peak memory 214412 kb
Host smart-6a663984-b7b8-4c98-a793-e023a3230f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695347728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1695347728
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3098030889
Short name T891
Test name
Test status
Simulation time 218203813 ps
CPU time 4.32 seconds
Started Mar 19 02:58:29 PM PDT 24
Finished Mar 19 02:58:34 PM PDT 24
Peak memory 206184 kb
Host smart-07955240-e2af-4900-83cd-8e58a3974722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098030889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3098030889
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.238002134
Short name T845
Test name
Test status
Simulation time 28375497 ps
CPU time 1.01 seconds
Started Mar 19 02:58:17 PM PDT 24
Finished Mar 19 02:58:18 PM PDT 24
Peak memory 206168 kb
Host smart-1dc2384f-f31b-4f5e-95e3-b78bb34d4fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238002134 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.238002134
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1751337228
Short name T901
Test name
Test status
Simulation time 27430856 ps
CPU time 0.87 seconds
Started Mar 19 02:58:17 PM PDT 24
Finished Mar 19 02:58:18 PM PDT 24
Peak memory 205964 kb
Host smart-73e89c19-2663-40f3-a5c4-02611d64184a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751337228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1751337228
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.404549694
Short name T911
Test name
Test status
Simulation time 11382232 ps
CPU time 0.87 seconds
Started Mar 19 02:58:00 PM PDT 24
Finished Mar 19 02:58:01 PM PDT 24
Peak memory 206016 kb
Host smart-ca16d070-45ea-4345-8377-772c979654ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404549694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.404549694
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.240285854
Short name T933
Test name
Test status
Simulation time 296285561 ps
CPU time 1.38 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:14 PM PDT 24
Peak memory 205984 kb
Host smart-e35a348f-fc24-4c85-9a1a-595b71aab0a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240285854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.240285854
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2128812171
Short name T895
Test name
Test status
Simulation time 360355709 ps
CPU time 2.82 seconds
Started Mar 19 02:58:05 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 214460 kb
Host smart-c1a198ad-c946-4443-ad1b-e8f7cd830f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128812171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2128812171
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3137453388
Short name T955
Test name
Test status
Simulation time 55059281 ps
CPU time 1.79 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 206208 kb
Host smart-025bcc5a-da59-431a-9927-30942037b47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137453388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3137453388
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2027581525
Short name T863
Test name
Test status
Simulation time 56763133 ps
CPU time 1.47 seconds
Started Mar 19 02:58:06 PM PDT 24
Finished Mar 19 02:58:07 PM PDT 24
Peak memory 214396 kb
Host smart-2a985f98-b066-4ed4-a4e7-4daa0450f5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027581525 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2027581525
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.710386397
Short name T238
Test name
Test status
Simulation time 10917194 ps
CPU time 0.92 seconds
Started Mar 19 02:58:13 PM PDT 24
Finished Mar 19 02:58:14 PM PDT 24
Peak memory 205984 kb
Host smart-62d35f7a-7796-4582-a327-43a2a451eb0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710386397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.710386397
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3080978162
Short name T872
Test name
Test status
Simulation time 18151073 ps
CPU time 0.8 seconds
Started Mar 19 02:58:06 PM PDT 24
Finished Mar 19 02:58:07 PM PDT 24
Peak memory 205984 kb
Host smart-f8c4294e-221c-47bc-aa73-65a0bbe6407e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080978162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3080978162
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.717643314
Short name T250
Test name
Test status
Simulation time 19731880 ps
CPU time 1.04 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:13 PM PDT 24
Peak memory 206132 kb
Host smart-3d4b446d-9197-4aad-93ce-205ccaabd6e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717643314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.717643314
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.38850453
Short name T860
Test name
Test status
Simulation time 45072598 ps
CPU time 3.19 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:15 PM PDT 24
Peak memory 214428 kb
Host smart-88e286e5-9e60-4244-82ac-67ba671f36de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38850453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.38850453
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.588471049
Short name T949
Test name
Test status
Simulation time 170096511 ps
CPU time 1.67 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:11 PM PDT 24
Peak memory 206236 kb
Host smart-d41fc8aa-b2f0-44b9-a3a0-ad4dc406b0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588471049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.588471049
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1361559826
Short name T848
Test name
Test status
Simulation time 52627069 ps
CPU time 1.46 seconds
Started Mar 19 02:58:06 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 214416 kb
Host smart-9153c33e-3033-417f-92e0-ff85069eacc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361559826 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1361559826
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4258958478
Short name T898
Test name
Test status
Simulation time 38098319 ps
CPU time 0.87 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 205832 kb
Host smart-820c04ab-f666-4195-8726-28bddf9ec7fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258958478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4258958478
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2996432980
Short name T957
Test name
Test status
Simulation time 25010904 ps
CPU time 0.86 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 206008 kb
Host smart-57960910-1f75-4da3-bab8-f4660cbbc3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996432980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2996432980
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4180882004
Short name T956
Test name
Test status
Simulation time 19709606 ps
CPU time 1.19 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 206188 kb
Host smart-7bd35442-e456-46fc-b2e2-7cc66b6b7deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180882004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4180882004
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.678933128
Short name T882
Test name
Test status
Simulation time 299434117 ps
CPU time 1.61 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:13 PM PDT 24
Peak memory 214392 kb
Host smart-f499decc-7423-4667-af91-07fa9bfac282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678933128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.678933128
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3041913551
Short name T264
Test name
Test status
Simulation time 50268744 ps
CPU time 1.7 seconds
Started Mar 19 02:58:14 PM PDT 24
Finished Mar 19 02:58:16 PM PDT 24
Peak memory 206100 kb
Host smart-d1afa303-cbd3-4619-b5fe-e7f5fb417d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041913551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3041913551
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.537062937
Short name T909
Test name
Test status
Simulation time 56310844 ps
CPU time 0.98 seconds
Started Mar 19 02:58:10 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 206152 kb
Host smart-ba71e024-cc8d-40ea-8dc3-37c9ea2b4420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537062937 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.537062937
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2408546499
Short name T869
Test name
Test status
Simulation time 31424580 ps
CPU time 0.87 seconds
Started Mar 19 02:58:03 PM PDT 24
Finished Mar 19 02:58:04 PM PDT 24
Peak memory 206000 kb
Host smart-118ff37e-635f-4143-b65d-1b73a32d3547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408546499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2408546499
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4074279039
Short name T878
Test name
Test status
Simulation time 35750620 ps
CPU time 0.84 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 205816 kb
Host smart-ea5710cd-6fc6-4ba2-8330-4421146d8115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074279039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4074279039
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3708088758
Short name T247
Test name
Test status
Simulation time 20356395 ps
CPU time 1.09 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 206096 kb
Host smart-dac25921-0d84-436b-80d1-5205c492f9c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708088758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3708088758
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1822785716
Short name T894
Test name
Test status
Simulation time 267785971 ps
CPU time 2.41 seconds
Started Mar 19 02:58:10 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 214416 kb
Host smart-f87a71de-f51e-4527-afba-a19587e28c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822785716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1822785716
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3465105699
Short name T902
Test name
Test status
Simulation time 140029413 ps
CPU time 1.48 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 206120 kb
Host smart-ab775abc-17b2-476f-a863-4d1e885b50fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465105699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3465105699
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3275820945
Short name T887
Test name
Test status
Simulation time 18338237 ps
CPU time 1.1 seconds
Started Mar 19 02:58:13 PM PDT 24
Finished Mar 19 02:58:15 PM PDT 24
Peak memory 206176 kb
Host smart-04372140-5caa-4ea6-9169-0e21e2f23209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275820945 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3275820945
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.775955666
Short name T236
Test name
Test status
Simulation time 14723234 ps
CPU time 0.97 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 206008 kb
Host smart-b72d9792-67be-46ff-9446-0f8b36f27c54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775955666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.775955666
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2816357214
Short name T866
Test name
Test status
Simulation time 31827584 ps
CPU time 0.89 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 205812 kb
Host smart-6ff56ce0-800a-4bb4-ae3e-155dd1a14422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816357214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2816357214
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2601409593
Short name T939
Test name
Test status
Simulation time 41985103 ps
CPU time 1.47 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 206056 kb
Host smart-9970c95e-e7e8-4f76-bfbf-7aa1ff175f1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601409593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2601409593
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2190212415
Short name T972
Test name
Test status
Simulation time 180080418 ps
CPU time 2.11 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 216792 kb
Host smart-40989168-daff-40ab-a104-08b9a5bab530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190212415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2190212415
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2494864285
Short name T924
Test name
Test status
Simulation time 290941574 ps
CPU time 2.28 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 206188 kb
Host smart-c0dc2864-d6f8-4174-8d21-26681ca45585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494864285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2494864285
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.235448695
Short name T885
Test name
Test status
Simulation time 67978070 ps
CPU time 1.26 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:14 PM PDT 24
Peak memory 214520 kb
Host smart-690511bb-477d-454b-ad03-3478ad122a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235448695 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.235448695
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.560431134
Short name T962
Test name
Test status
Simulation time 43968632 ps
CPU time 0.85 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 206000 kb
Host smart-b10944a6-fd40-43b3-ba35-1d8b603a7858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560431134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.560431134
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1664272159
Short name T899
Test name
Test status
Simulation time 15988566 ps
CPU time 1.01 seconds
Started Mar 19 02:58:03 PM PDT 24
Finished Mar 19 02:58:04 PM PDT 24
Peak memory 206148 kb
Host smart-02d65eb7-8218-4f1a-b4f3-29184b96fb29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664272159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1664272159
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3129965297
Short name T923
Test name
Test status
Simulation time 570424386 ps
CPU time 4.49 seconds
Started Mar 19 02:58:10 PM PDT 24
Finished Mar 19 02:58:15 PM PDT 24
Peak memory 214428 kb
Host smart-39759986-d89f-43b7-8359-5d3af62141bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129965297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3129965297
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3819006247
Short name T913
Test name
Test status
Simulation time 121415941 ps
CPU time 1.61 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 206124 kb
Host smart-47c474cf-daa7-447f-ba9c-010b3bd069a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819006247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3819006247
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2660756881
Short name T861
Test name
Test status
Simulation time 28814861 ps
CPU time 1.41 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 214492 kb
Host smart-81dfeaa5-6335-4517-9421-de21919d67ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660756881 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2660756881
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3071674611
Short name T246
Test name
Test status
Simulation time 18573205 ps
CPU time 0.79 seconds
Started Mar 19 02:58:04 PM PDT 24
Finished Mar 19 02:58:05 PM PDT 24
Peak memory 205812 kb
Host smart-1333583a-fa34-478a-97fc-df33dd7a17fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071674611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3071674611
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2150958351
Short name T862
Test name
Test status
Simulation time 92788012 ps
CPU time 0.88 seconds
Started Mar 19 02:58:17 PM PDT 24
Finished Mar 19 02:58:18 PM PDT 24
Peak memory 205776 kb
Host smart-bbaccf44-4021-4616-b30e-ae6b60cf101c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150958351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2150958351
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.544798799
Short name T971
Test name
Test status
Simulation time 27933301 ps
CPU time 0.95 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 206124 kb
Host smart-3cb55db0-8e9d-4a40-8c0c-d230b9de1a31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544798799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.544798799
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2559948273
Short name T876
Test name
Test status
Simulation time 27530194 ps
CPU time 1.89 seconds
Started Mar 19 02:58:29 PM PDT 24
Finished Mar 19 02:58:31 PM PDT 24
Peak memory 214360 kb
Host smart-447fb28a-a6cf-4565-b328-2b6eaff12670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559948273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2559948273
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.684364916
Short name T893
Test name
Test status
Simulation time 85068045 ps
CPU time 1.66 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 214360 kb
Host smart-c8f0450d-6f55-4967-9d61-8c49839961f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684364916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.684364916
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.57667473
Short name T240
Test name
Test status
Simulation time 24556955 ps
CPU time 1.19 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 206024 kb
Host smart-36976fec-cc10-4c4a-9dd2-b8e9e1790abe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57667473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.57667473
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3193358930
Short name T873
Test name
Test status
Simulation time 94851461 ps
CPU time 3.24 seconds
Started Mar 19 02:58:02 PM PDT 24
Finished Mar 19 02:58:05 PM PDT 24
Peak memory 205980 kb
Host smart-1f5ef0d8-697f-456b-951f-f996aedea590
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193358930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3193358930
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3539181180
Short name T944
Test name
Test status
Simulation time 39117996 ps
CPU time 0.82 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 205796 kb
Host smart-c6d71db7-0ed1-49a9-adef-c34e1ed8e4d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539181180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3539181180
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2757742100
Short name T916
Test name
Test status
Simulation time 27387891 ps
CPU time 1.14 seconds
Started Mar 19 02:58:06 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 214448 kb
Host smart-f7c6153f-056d-44cf-89fa-3bc67f67fbe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757742100 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2757742100
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2983122683
Short name T252
Test name
Test status
Simulation time 26938883 ps
CPU time 0.92 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 205968 kb
Host smart-0e1d63c9-530c-4afe-a279-9d34370a24fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983122683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2983122683
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.933062367
Short name T854
Test name
Test status
Simulation time 17524622 ps
CPU time 0.91 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 205964 kb
Host smart-4fa320ac-30db-4ed9-a506-dcfe03df1f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933062367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.933062367
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1031766450
Short name T234
Test name
Test status
Simulation time 32736295 ps
CPU time 1.39 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 206076 kb
Host smart-fdd670ec-4937-4f2f-878e-299c155ed605
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031766450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1031766450
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.917456698
Short name T879
Test name
Test status
Simulation time 208518142 ps
CPU time 3.02 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:50 PM PDT 24
Peak memory 214476 kb
Host smart-77a6dedf-a653-44ca-9b29-9077cc6cbb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917456698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.917456698
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3419488177
Short name T265
Test name
Test status
Simulation time 46418759 ps
CPU time 1.64 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 206128 kb
Host smart-12f73d57-40d4-4b03-8de4-624362f65ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419488177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3419488177
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3891159241
Short name T966
Test name
Test status
Simulation time 31517883 ps
CPU time 0.81 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 205800 kb
Host smart-cbe81f5d-a3ed-40b7-899f-9e1298d72780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891159241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3891159241
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3699614048
Short name T941
Test name
Test status
Simulation time 18530709 ps
CPU time 0.87 seconds
Started Mar 19 02:58:15 PM PDT 24
Finished Mar 19 02:58:17 PM PDT 24
Peak memory 205976 kb
Host smart-687c29de-bd29-4af4-b2e6-cbccf62160e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699614048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3699614048
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2824159323
Short name T855
Test name
Test status
Simulation time 15240141 ps
CPU time 0.87 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 205988 kb
Host smart-b92c3b23-b25a-4bd1-94a7-df82c4ad5907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824159323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2824159323
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2068001606
Short name T919
Test name
Test status
Simulation time 117157099 ps
CPU time 0.84 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 205824 kb
Host smart-84ba37e9-c96e-4b00-b25c-de78496d387f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068001606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2068001606
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.314414805
Short name T970
Test name
Test status
Simulation time 70333621 ps
CPU time 0.8 seconds
Started Mar 19 02:58:02 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 205800 kb
Host smart-677192a6-8425-48bc-96bd-bc57bd0a4ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314414805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.314414805
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2419811014
Short name T897
Test name
Test status
Simulation time 16940857 ps
CPU time 0.84 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 205776 kb
Host smart-0e6c95f2-6d2b-47de-83ab-87a604e11beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419811014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2419811014
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4065882895
Short name T857
Test name
Test status
Simulation time 37750045 ps
CPU time 0.84 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 205860 kb
Host smart-6d3f2bf6-b97e-4b38-9770-bdbc3b29bbff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065882895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4065882895
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2150529586
Short name T920
Test name
Test status
Simulation time 121333395 ps
CPU time 0.82 seconds
Started Mar 19 02:58:22 PM PDT 24
Finished Mar 19 02:58:23 PM PDT 24
Peak memory 206016 kb
Host smart-0182808d-abd1-4e26-9794-6a9fe1b4d3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150529586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2150529586
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2250422432
Short name T952
Test name
Test status
Simulation time 22329689 ps
CPU time 0.86 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 206020 kb
Host smart-ace60e55-6d9d-4569-9f9c-a6201d72453d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250422432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2250422432
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1807392827
Short name T969
Test name
Test status
Simulation time 45829339 ps
CPU time 0.89 seconds
Started Mar 19 02:58:04 PM PDT 24
Finished Mar 19 02:58:05 PM PDT 24
Peak memory 206016 kb
Host smart-780b4184-6e8c-4a0a-b090-b21d426d4a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807392827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1807392827
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3675680166
Short name T928
Test name
Test status
Simulation time 62984636 ps
CPU time 1.32 seconds
Started Mar 19 02:57:59 PM PDT 24
Finished Mar 19 02:58:00 PM PDT 24
Peak memory 206108 kb
Host smart-508daffe-0115-4c05-9bfc-b9e1f6a10fd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675680166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3675680166
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3347125660
Short name T233
Test name
Test status
Simulation time 57744698 ps
CPU time 3.19 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 206068 kb
Host smart-e3eb8b7d-fce2-4032-9e85-75f268132a30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347125660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3347125660
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3526334572
Short name T963
Test name
Test status
Simulation time 42352058 ps
CPU time 0.81 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 205704 kb
Host smart-2bc93813-196a-416a-ba75-64da9e8306a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526334572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3526334572
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1315748344
Short name T917
Test name
Test status
Simulation time 35506163 ps
CPU time 1.52 seconds
Started Mar 19 02:57:59 PM PDT 24
Finished Mar 19 02:58:00 PM PDT 24
Peak memory 216752 kb
Host smart-d1fe33b6-e6c7-4f77-a72b-41a8a7d23620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315748344 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1315748344
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.907975181
Short name T232
Test name
Test status
Simulation time 71597793 ps
CPU time 0.9 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 205852 kb
Host smart-32c933ab-79c7-49d4-9c50-3fb53b38499c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907975181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.907975181
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1136233493
Short name T914
Test name
Test status
Simulation time 35861691 ps
CPU time 0.86 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:48 PM PDT 24
Peak memory 205800 kb
Host smart-7bb2976c-8455-4395-b52c-e615f04c7dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136233493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1136233493
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2954578098
Short name T930
Test name
Test status
Simulation time 35951216 ps
CPU time 1.46 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 206128 kb
Host smart-c9ba9934-7ba9-4312-b255-3f196b038a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954578098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2954578098
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4147372912
Short name T870
Test name
Test status
Simulation time 227385743 ps
CPU time 2.33 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 214476 kb
Host smart-200c93d1-91ee-47ac-911a-669662b2499e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147372912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4147372912
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2697415036
Short name T253
Test name
Test status
Simulation time 39829594 ps
CPU time 1.62 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:50 PM PDT 24
Peak memory 206212 kb
Host smart-00256af9-36c8-4658-9bf1-2ab532e8dc97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697415036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2697415036
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.4090086107
Short name T856
Test name
Test status
Simulation time 18552252 ps
CPU time 0.97 seconds
Started Mar 19 02:58:32 PM PDT 24
Finished Mar 19 02:58:34 PM PDT 24
Peak memory 205984 kb
Host smart-ce3bd19b-0368-45fe-b39d-ff35f0d2fb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090086107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4090086107
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1198483590
Short name T884
Test name
Test status
Simulation time 34061193 ps
CPU time 0.9 seconds
Started Mar 19 02:58:23 PM PDT 24
Finished Mar 19 02:58:24 PM PDT 24
Peak memory 205968 kb
Host smart-8a9cb170-3907-47e2-9304-68da9a58c5b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198483590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1198483590
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2254847278
Short name T931
Test name
Test status
Simulation time 51348709 ps
CPU time 0.85 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:13 PM PDT 24
Peak memory 206000 kb
Host smart-00df6c64-1f37-4001-bce9-a62bb9436e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254847278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2254847278
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4069887994
Short name T847
Test name
Test status
Simulation time 108904257 ps
CPU time 0.9 seconds
Started Mar 19 02:58:30 PM PDT 24
Finished Mar 19 02:58:31 PM PDT 24
Peak memory 205928 kb
Host smart-76045a78-53ac-4461-93ab-7bdbdf01196b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069887994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4069887994
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1372569190
Short name T850
Test name
Test status
Simulation time 32077407 ps
CPU time 0.79 seconds
Started Mar 19 02:58:17 PM PDT 24
Finished Mar 19 02:58:18 PM PDT 24
Peak memory 205776 kb
Host smart-9db9a7a0-9e34-4f74-a424-0660ddde4ea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372569190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1372569190
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1604563282
Short name T965
Test name
Test status
Simulation time 15045038 ps
CPU time 0.91 seconds
Started Mar 19 02:58:20 PM PDT 24
Finished Mar 19 02:58:22 PM PDT 24
Peak memory 205968 kb
Host smart-ddb8c899-31e6-44fb-b89c-3fb14a7580f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604563282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1604563282
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3762268165
Short name T877
Test name
Test status
Simulation time 41241800 ps
CPU time 0.79 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 205812 kb
Host smart-749def1e-2840-48cb-a7e3-9ccc6d5abd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762268165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3762268165
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1858495989
Short name T880
Test name
Test status
Simulation time 47794103 ps
CPU time 0.91 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 205988 kb
Host smart-086e96b3-0ed4-4353-aa63-57c2fdcd0cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858495989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1858495989
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3119278493
Short name T958
Test name
Test status
Simulation time 10325328 ps
CPU time 0.81 seconds
Started Mar 19 02:58:17 PM PDT 24
Finished Mar 19 02:58:18 PM PDT 24
Peak memory 205840 kb
Host smart-bac31ddb-8c31-442f-a02c-95e1c3469bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119278493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3119278493
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.928489557
Short name T849
Test name
Test status
Simulation time 30005388 ps
CPU time 0.93 seconds
Started Mar 19 02:58:09 PM PDT 24
Finished Mar 19 02:58:10 PM PDT 24
Peak memory 205988 kb
Host smart-28375ea0-ffa0-4a30-b092-62b2cf2b17e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928489557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.928489557
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1643165687
Short name T947
Test name
Test status
Simulation time 131232141 ps
CPU time 1.52 seconds
Started Mar 19 02:58:08 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 206008 kb
Host smart-5e231155-8194-4e32-aa44-27d38093dd3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643165687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1643165687
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2648486392
Short name T235
Test name
Test status
Simulation time 453203433 ps
CPU time 5.94 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 206012 kb
Host smart-c427f894-4701-498e-b7f6-78157c376120
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648486392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2648486392
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.77043919
Short name T886
Test name
Test status
Simulation time 47401437 ps
CPU time 0.89 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 205796 kb
Host smart-ff4e2c2e-5f40-4a2a-bdbc-bdb3002135f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77043919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.77043919
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.270537909
Short name T871
Test name
Test status
Simulation time 124331627 ps
CPU time 1.18 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 214440 kb
Host smart-cc389f40-7dad-4fc4-8f5c-e0aea1f41b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270537909 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.270537909
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1484772938
Short name T974
Test name
Test status
Simulation time 15036012 ps
CPU time 0.97 seconds
Started Mar 19 02:57:59 PM PDT 24
Finished Mar 19 02:58:00 PM PDT 24
Peak memory 205988 kb
Host smart-b710638d-5780-48d0-81d6-3737bae9d05c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484772938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1484772938
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1186761138
Short name T953
Test name
Test status
Simulation time 37713654 ps
CPU time 0.81 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 205804 kb
Host smart-a268390b-74fe-4b51-a08e-b50e33cde684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186761138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1186761138
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.407205771
Short name T244
Test name
Test status
Simulation time 16201448 ps
CPU time 0.98 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 206104 kb
Host smart-e86cf38c-01a9-453d-82da-120c283cae67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407205771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.407205771
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1308722428
Short name T846
Test name
Test status
Simulation time 242322508 ps
CPU time 2.06 seconds
Started Mar 19 02:58:02 PM PDT 24
Finished Mar 19 02:58:04 PM PDT 24
Peak memory 214512 kb
Host smart-b8676841-b508-4b0c-a302-1ff8891f3f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308722428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1308722428
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3148463126
Short name T926
Test name
Test status
Simulation time 205474615 ps
CPU time 4.18 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:58:01 PM PDT 24
Peak memory 206104 kb
Host smart-f6d57684-d188-4e41-8bb7-4d0961e83047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148463126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3148463126
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1690033363
Short name T912
Test name
Test status
Simulation time 13655542 ps
CPU time 0.91 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:13 PM PDT 24
Peak memory 206020 kb
Host smart-b91b9860-8713-44b5-86ca-d0c381597bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690033363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1690033363
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2739797316
Short name T853
Test name
Test status
Simulation time 14944203 ps
CPU time 0.89 seconds
Started Mar 19 02:58:16 PM PDT 24
Finished Mar 19 02:58:17 PM PDT 24
Peak memory 205976 kb
Host smart-ec6a4c86-167b-4dfd-89a8-0801fc519789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739797316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2739797316
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.357188272
Short name T896
Test name
Test status
Simulation time 11945752 ps
CPU time 0.83 seconds
Started Mar 19 02:58:27 PM PDT 24
Finished Mar 19 02:58:28 PM PDT 24
Peak memory 205996 kb
Host smart-4108850a-f996-4e70-986c-1c6f7dd13406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357188272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.357188272
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1690455559
Short name T888
Test name
Test status
Simulation time 135531893 ps
CPU time 0.9 seconds
Started Mar 19 02:58:20 PM PDT 24
Finished Mar 19 02:58:21 PM PDT 24
Peak memory 205968 kb
Host smart-449c1b49-9bcc-4f73-84e8-23cc47db8641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690455559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1690455559
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1256866275
Short name T918
Test name
Test status
Simulation time 13173270 ps
CPU time 0.89 seconds
Started Mar 19 02:58:10 PM PDT 24
Finished Mar 19 02:58:11 PM PDT 24
Peak memory 206000 kb
Host smart-35c85ab7-3e3c-4583-9618-a751b0da2cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256866275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1256866275
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1141325561
Short name T961
Test name
Test status
Simulation time 62354070 ps
CPU time 0.89 seconds
Started Mar 19 02:58:13 PM PDT 24
Finished Mar 19 02:58:14 PM PDT 24
Peak memory 205964 kb
Host smart-1bbd804d-bb37-4b38-bd97-01ccf5940caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141325561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1141325561
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1424953313
Short name T867
Test name
Test status
Simulation time 19401917 ps
CPU time 0.84 seconds
Started Mar 19 02:58:24 PM PDT 24
Finished Mar 19 02:58:25 PM PDT 24
Peak memory 205984 kb
Host smart-835a7b9c-6deb-4e9f-9dbf-35872a5cce23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424953313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1424953313
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1938911878
Short name T868
Test name
Test status
Simulation time 49283734 ps
CPU time 0.83 seconds
Started Mar 19 02:58:14 PM PDT 24
Finished Mar 19 02:58:15 PM PDT 24
Peak memory 205860 kb
Host smart-d9b747b7-63c6-4496-bbc7-3d41fdbdb6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938911878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1938911878
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.323189802
Short name T910
Test name
Test status
Simulation time 21413767 ps
CPU time 0.79 seconds
Started Mar 19 02:58:12 PM PDT 24
Finished Mar 19 02:58:13 PM PDT 24
Peak memory 206000 kb
Host smart-81a8dc24-debe-4553-af6d-a52b09a8ce6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323189802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.323189802
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2550260576
Short name T945
Test name
Test status
Simulation time 19664954 ps
CPU time 0.89 seconds
Started Mar 19 02:58:11 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 206032 kb
Host smart-e7b05f65-3f69-494f-aad3-35c22edb521f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550260576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2550260576
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1812779526
Short name T892
Test name
Test status
Simulation time 64996590 ps
CPU time 1.52 seconds
Started Mar 19 02:57:52 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 214492 kb
Host smart-6d40d197-065a-470a-b057-b58531a39efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812779526 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1812779526
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3575229935
Short name T243
Test name
Test status
Simulation time 27347495 ps
CPU time 0.92 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 206020 kb
Host smart-fbee7a2c-0d6e-4411-9a93-51458b2d31b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575229935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3575229935
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4140768298
Short name T851
Test name
Test status
Simulation time 13064235 ps
CPU time 0.84 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 205996 kb
Host smart-3727f8d0-d10c-4d80-bede-e03c48f9d5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140768298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4140768298
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.578900748
Short name T248
Test name
Test status
Simulation time 28463229 ps
CPU time 1.17 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 206204 kb
Host smart-c2f99cd0-bcfa-466a-b654-5dfaf0710a9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578900748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.578900748
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1334820686
Short name T904
Test name
Test status
Simulation time 28109301 ps
CPU time 1.8 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 214448 kb
Host smart-8be8431e-a945-43ed-a84a-1b1daeb3103c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334820686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1334820686
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3651260726
Short name T950
Test name
Test status
Simulation time 147962547 ps
CPU time 1.56 seconds
Started Mar 19 02:58:00 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 206092 kb
Host smart-00b9b5f1-d2fd-466f-9925-5fba8ed9f180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651260726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3651260726
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1818221404
Short name T929
Test name
Test status
Simulation time 30772291 ps
CPU time 1.16 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 214476 kb
Host smart-d9e1109c-7cea-4c6d-bb11-bdef90973d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818221404 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1818221404
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1282614357
Short name T967
Test name
Test status
Simulation time 24457260 ps
CPU time 1.04 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 205924 kb
Host smart-52a708e4-debe-4829-a891-deefa44e2ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282614357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1282614357
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3218814431
Short name T935
Test name
Test status
Simulation time 18208262 ps
CPU time 0.94 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 206000 kb
Host smart-7db23746-aeb7-4839-be4c-7222a1527e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218814431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3218814431
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4193146907
Short name T907
Test name
Test status
Simulation time 101421867 ps
CPU time 1.43 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 206140 kb
Host smart-a0ab1267-c3e9-47da-8932-f0521f823139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193146907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4193146907
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2973459046
Short name T973
Test name
Test status
Simulation time 132734557 ps
CPU time 2.93 seconds
Started Mar 19 02:57:54 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 214568 kb
Host smart-8052cb22-d7b5-4056-8a6d-c2a54eae913c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973459046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2973459046
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1792361143
Short name T922
Test name
Test status
Simulation time 62813600 ps
CPU time 1.23 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 214428 kb
Host smart-a01f5cc0-7ffe-47c6-ae90-dc6774aae0c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792361143 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1792361143
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1296021528
Short name T228
Test name
Test status
Simulation time 45991400 ps
CPU time 0.88 seconds
Started Mar 19 02:57:52 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 206020 kb
Host smart-b5efa580-3891-4995-aa1d-2611e403ca3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296021528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1296021528
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3106578717
Short name T960
Test name
Test status
Simulation time 15911292 ps
CPU time 0.92 seconds
Started Mar 19 02:58:07 PM PDT 24
Finished Mar 19 02:58:08 PM PDT 24
Peak memory 206004 kb
Host smart-6e516161-1fda-4762-83e4-e267efe05647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106578717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3106578717
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.285978649
Short name T921
Test name
Test status
Simulation time 102319706 ps
CPU time 1.3 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 206228 kb
Host smart-f562fae6-1a82-426c-b8c2-33da6907ca1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285978649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.285978649
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3187722110
Short name T874
Test name
Test status
Simulation time 42815520 ps
CPU time 2.95 seconds
Started Mar 19 02:58:04 PM PDT 24
Finished Mar 19 02:58:07 PM PDT 24
Peak memory 214472 kb
Host smart-c20f5993-1fea-4a06-bbaf-999ad4a873be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187722110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3187722110
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.953918744
Short name T254
Test name
Test status
Simulation time 269250716 ps
CPU time 2.24 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 206108 kb
Host smart-e8e28ac8-22c1-4229-868d-e47294dca8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953918744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.953918744
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3723757632
Short name T858
Test name
Test status
Simulation time 39539659 ps
CPU time 1.16 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 214508 kb
Host smart-6fd95bea-45c0-41fe-8138-0054bbfe6841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723757632 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3723757632
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3077143081
Short name T237
Test name
Test status
Simulation time 17646362 ps
CPU time 0.93 seconds
Started Mar 19 02:57:56 PM PDT 24
Finished Mar 19 02:57:57 PM PDT 24
Peak memory 205996 kb
Host smart-18994096-1b27-4080-91f3-76a24fb0aa82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077143081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3077143081
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3130072372
Short name T906
Test name
Test status
Simulation time 79987174 ps
CPU time 0.89 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 206016 kb
Host smart-d72841cd-e4bf-418d-b507-78a12426064c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130072372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3130072372
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3640116553
Short name T903
Test name
Test status
Simulation time 31888101 ps
CPU time 1.14 seconds
Started Mar 19 02:58:06 PM PDT 24
Finished Mar 19 02:58:07 PM PDT 24
Peak memory 206208 kb
Host smart-762d8f6a-9cee-4809-83a3-bc94e5f97f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640116553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3640116553
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3560427292
Short name T925
Test name
Test status
Simulation time 262478619 ps
CPU time 4.52 seconds
Started Mar 19 02:58:06 PM PDT 24
Finished Mar 19 02:58:11 PM PDT 24
Peak memory 214384 kb
Host smart-48a5a1a6-87b3-46ab-bf70-f1e1b5f55812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560427292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3560427292
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2003298470
Short name T263
Test name
Test status
Simulation time 157853603 ps
CPU time 2.49 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 206168 kb
Host smart-37bdc5e6-2d15-4ab6-9f4e-430b341c5fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003298470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2003298470
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4138500754
Short name T881
Test name
Test status
Simulation time 15610649 ps
CPU time 1.05 seconds
Started Mar 19 02:58:01 PM PDT 24
Finished Mar 19 02:58:02 PM PDT 24
Peak memory 206192 kb
Host smart-220cdd1d-5546-4b83-bf22-8c968b0e4287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138500754 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4138500754
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.157805264
Short name T934
Test name
Test status
Simulation time 15500731 ps
CPU time 0.94 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:57:59 PM PDT 24
Peak memory 206116 kb
Host smart-31ce9995-7230-4a88-9669-e78ff3355731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157805264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.157805264
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3644510288
Short name T890
Test name
Test status
Simulation time 22317609 ps
CPU time 0.82 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 205912 kb
Host smart-a0c3cba4-c8a7-43a2-8e5a-7506a1b3d05c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644510288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3644510288
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3461957494
Short name T249
Test name
Test status
Simulation time 38001203 ps
CPU time 1.09 seconds
Started Mar 19 02:58:04 PM PDT 24
Finished Mar 19 02:58:05 PM PDT 24
Peak memory 206092 kb
Host smart-b0f0c9c3-2f4b-4a2b-b508-fe8edf59b88b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461957494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3461957494
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.208848924
Short name T946
Test name
Test status
Simulation time 65726263 ps
CPU time 2.34 seconds
Started Mar 19 02:57:58 PM PDT 24
Finished Mar 19 02:58:01 PM PDT 24
Peak memory 214368 kb
Host smart-0fa39407-b15a-4b72-b383-38e792abd0d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208848924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.208848924
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1093338056
Short name T905
Test name
Test status
Simulation time 281063607 ps
CPU time 2.3 seconds
Started Mar 19 02:58:03 PM PDT 24
Finished Mar 19 02:58:06 PM PDT 24
Peak memory 206116 kb
Host smart-ec9f74eb-fe0a-49a8-88a7-5a5074b6100e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093338056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1093338056
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.478587541
Short name T763
Test name
Test status
Simulation time 77786380 ps
CPU time 1.24 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215808 kb
Host smart-43dd3cf4-cb33-4710-8ebf-d594eb40ab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478587541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.478587541
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2604192290
Short name T700
Test name
Test status
Simulation time 23314511 ps
CPU time 0.84 seconds
Started Mar 19 02:55:51 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 206780 kb
Host smart-ec891095-b839-4f06-8d98-6b73d348e001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604192290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2604192290
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.210635257
Short name T169
Test name
Test status
Simulation time 23978315 ps
CPU time 0.97 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 218244 kb
Host smart-7f06f558-474d-46e0-a96d-85b43af9c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210635257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.210635257
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2516773956
Short name T374
Test name
Test status
Simulation time 57814540 ps
CPU time 1.67 seconds
Started Mar 19 02:55:40 PM PDT 24
Finished Mar 19 02:55:42 PM PDT 24
Peak memory 219464 kb
Host smart-6b6b3cab-a4d9-4039-baa8-6952a61b4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516773956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2516773956
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1577152072
Short name T456
Test name
Test status
Simulation time 22700189 ps
CPU time 1.17 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 224124 kb
Host smart-6dfd88f0-ac8f-40b9-86a2-48b6d01b8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577152072 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1577152072
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3392665464
Short name T266
Test name
Test status
Simulation time 26669978 ps
CPU time 0.99 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 207200 kb
Host smart-0809f7fd-a066-4e99-9ace-ff8dc372735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392665464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3392665464
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1477037851
Short name T20
Test name
Test status
Simulation time 192238874 ps
CPU time 3.67 seconds
Started Mar 19 02:55:51 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 236668 kb
Host smart-48b7bdbd-205d-4544-8728-0dabf92cbb13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477037851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1477037851
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3113299014
Short name T526
Test name
Test status
Simulation time 51611709 ps
CPU time 0.94 seconds
Started Mar 19 02:55:42 PM PDT 24
Finished Mar 19 02:55:43 PM PDT 24
Peak memory 215436 kb
Host smart-2e1d7764-833c-433b-9f8a-5de2c34d72c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113299014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3113299014
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2211322047
Short name T533
Test name
Test status
Simulation time 868147347 ps
CPU time 5.29 seconds
Started Mar 19 02:55:43 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 216784 kb
Host smart-6450a860-3ad3-4f0e-857c-07f8dc3b8948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211322047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2211322047
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2814671672
Short name T591
Test name
Test status
Simulation time 142515879483 ps
CPU time 1792.93 seconds
Started Mar 19 02:55:49 PM PDT 24
Finished Mar 19 03:25:43 PM PDT 24
Peak memory 227964 kb
Host smart-93ae6d9d-8be8-4112-8c08-93a79286ed82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814671672 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2814671672
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.121662850
Short name T257
Test name
Test status
Simulation time 30424963 ps
CPU time 1.33 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215656 kb
Host smart-377f80ff-6375-4143-810b-1d0fb2087f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121662850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.121662850
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.2566740382
Short name T516
Test name
Test status
Simulation time 27116191 ps
CPU time 0.92 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 206148 kb
Host smart-a013463a-bfba-410d-acc3-f47f40916a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566740382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2566740382
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3705918339
Short name T750
Test name
Test status
Simulation time 24265425 ps
CPU time 1.01 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 217984 kb
Host smart-d5530b76-1653-492d-ba60-4bb9bd9af17e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705918339 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3705918339
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1392518319
Short name T419
Test name
Test status
Simulation time 28745632 ps
CPU time 0.87 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:48 PM PDT 24
Peak memory 217972 kb
Host smart-c7078d92-de2b-4e8e-b7b7-3d818d79f107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392518319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1392518319
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3989786697
Short name T807
Test name
Test status
Simulation time 167864194 ps
CPU time 1.26 seconds
Started Mar 19 02:55:43 PM PDT 24
Finished Mar 19 02:55:47 PM PDT 24
Peak memory 216776 kb
Host smart-442c2395-ce12-4c3c-976c-7d34697746de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989786697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3989786697
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1491551515
Short name T56
Test name
Test status
Simulation time 1516604947 ps
CPU time 6.14 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 234464 kb
Host smart-35e1e128-9eab-4ecd-9fee-bb3b367e5fab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491551515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1491551515
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1423853916
Short name T358
Test name
Test status
Simulation time 29517662 ps
CPU time 0.98 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 215400 kb
Host smart-2bf8eb6d-2ed6-41fc-b906-691d660e1608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423853916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1423853916
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.249917651
Short name T561
Test name
Test status
Simulation time 235238481 ps
CPU time 1.36 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:55:48 PM PDT 24
Peak memory 216988 kb
Host smart-4ee00c4c-03ec-4025-aaab-6c84cfc9b5f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249917651 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.249917651
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2828652895
Short name T499
Test name
Test status
Simulation time 72834926118 ps
CPU time 1847.32 seconds
Started Mar 19 02:55:42 PM PDT 24
Finished Mar 19 03:26:30 PM PDT 24
Peak memory 227428 kb
Host smart-adec1da9-e755-446a-90a2-c0a20eab95b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828652895 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2828652895
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3736508717
Short name T77
Test name
Test status
Simulation time 33851640 ps
CPU time 1.35 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 215772 kb
Host smart-d88d7491-4724-4216-b409-bb82928451a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736508717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3736508717
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3929061659
Short name T393
Test name
Test status
Simulation time 158531194 ps
CPU time 0.97 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:01 PM PDT 24
Peak memory 206000 kb
Host smart-d003db3c-821b-4605-a75d-65df9dfbe7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929061659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3929061659
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1646530012
Short name T637
Test name
Test status
Simulation time 13935698 ps
CPU time 0.91 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 216472 kb
Host smart-07c0d13e-edcb-4e23-95bf-632b0c8e44eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646530012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1646530012
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.688065275
Short name T651
Test name
Test status
Simulation time 195444181 ps
CPU time 1.11 seconds
Started Mar 19 02:56:02 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 216792 kb
Host smart-9b114223-2ac4-485e-b711-cd47d3e92c7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688065275 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.688065275
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2741806217
Short name T495
Test name
Test status
Simulation time 26553779 ps
CPU time 0.84 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 217868 kb
Host smart-85c70a20-fe43-4586-9b76-a8077dca33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741806217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2741806217
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2999515197
Short name T369
Test name
Test status
Simulation time 168892960 ps
CPU time 1.66 seconds
Started Mar 19 02:56:02 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 219664 kb
Host smart-62153574-829a-419e-8ead-25d020eef647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999515197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2999515197
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.838050519
Short name T631
Test name
Test status
Simulation time 32710479 ps
CPU time 0.83 seconds
Started Mar 19 02:56:09 PM PDT 24
Finished Mar 19 02:56:10 PM PDT 24
Peak memory 215672 kb
Host smart-e14e5268-2482-4b38-bb11-7e1509fc6d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838050519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.838050519
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1696499010
Short name T359
Test name
Test status
Simulation time 17774273 ps
CPU time 1.07 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 215432 kb
Host smart-6d4a0f3a-4489-4745-8d33-b0aa51a3b590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696499010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1696499010
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2152601164
Short name T155
Test name
Test status
Simulation time 1045813424 ps
CPU time 4.78 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:56:03 PM PDT 24
Peak memory 219656 kb
Host smart-1c4a986d-e9f5-4b36-9006-a65d48e610ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152601164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2152601164
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1898362663
Short name T205
Test name
Test status
Simulation time 43074077708 ps
CPU time 569.26 seconds
Started Mar 19 02:56:04 PM PDT 24
Finished Mar 19 03:05:34 PM PDT 24
Peak memory 219140 kb
Host smart-bedfc8c9-034e-4a12-bbe6-b8a5683f52ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898362663 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1898362663
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2015579241
Short name T377
Test name
Test status
Simulation time 48349760 ps
CPU time 1.12 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 216052 kb
Host smart-84827d26-6ef5-46b5-a461-c6a7079f5c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015579241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2015579241
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.18809531
Short name T771
Test name
Test status
Simulation time 85600678 ps
CPU time 1.04 seconds
Started Mar 19 02:57:18 PM PDT 24
Finished Mar 19 02:57:19 PM PDT 24
Peak memory 216796 kb
Host smart-3da48a79-5af4-4598-b7cc-c697133c7a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18809531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.18809531
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.72877639
Short name T423
Test name
Test status
Simulation time 82680696 ps
CPU time 1.22 seconds
Started Mar 19 02:57:29 PM PDT 24
Finished Mar 19 02:57:30 PM PDT 24
Peak memory 219796 kb
Host smart-5ff9cc84-b0b9-41e2-8678-9483d9b05a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72877639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.72877639
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3787255365
Short name T471
Test name
Test status
Simulation time 41573576 ps
CPU time 1.81 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 217880 kb
Host smart-17acbb8a-eb6a-4595-bf64-4cfe02263a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787255365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3787255365
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2437656900
Short name T575
Test name
Test status
Simulation time 56766173 ps
CPU time 1.21 seconds
Started Mar 19 02:57:19 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 216836 kb
Host smart-111687e9-5b3b-48e9-a5e4-5ba3069f093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437656900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2437656900
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2339075874
Short name T465
Test name
Test status
Simulation time 31619535 ps
CPU time 1.25 seconds
Started Mar 19 02:57:32 PM PDT 24
Finished Mar 19 02:57:33 PM PDT 24
Peak memory 217964 kb
Host smart-5ff8bd15-03ff-4dd5-844c-e0c6764f94a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339075874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2339075874
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3944621172
Short name T790
Test name
Test status
Simulation time 27069378 ps
CPU time 1.24 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 216836 kb
Host smart-67517e13-e0e6-4559-8fb4-1088f244ac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944621172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3944621172
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2243504695
Short name T313
Test name
Test status
Simulation time 81336130 ps
CPU time 2.84 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:31 PM PDT 24
Peak memory 219456 kb
Host smart-e2afbee3-cb23-4684-9df9-036b0c5df2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243504695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2243504695
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.393194030
Short name T596
Test name
Test status
Simulation time 149327926 ps
CPU time 1.47 seconds
Started Mar 19 02:57:23 PM PDT 24
Finished Mar 19 02:57:25 PM PDT 24
Peak memory 218540 kb
Host smart-cbc10461-f4cf-4476-9f92-16a7f3685771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393194030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.393194030
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1588868232
Short name T60
Test name
Test status
Simulation time 54585828 ps
CPU time 1.24 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:01 PM PDT 24
Peak memory 216068 kb
Host smart-6d40fafb-1fb5-414f-8438-91427d1198c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588868232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1588868232
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.4020658084
Short name T761
Test name
Test status
Simulation time 18744526 ps
CPU time 0.94 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 206176 kb
Host smart-f19d432e-bc3a-42b8-af04-48a31c7c93c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020658084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4020658084
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3910760489
Short name T170
Test name
Test status
Simulation time 23076573 ps
CPU time 0.92 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 216004 kb
Host smart-d125fb60-734a-4855-8943-42ebd81a45b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910760489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3910760489
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.4253984057
Short name T726
Test name
Test status
Simulation time 41547742 ps
CPU time 0.84 seconds
Started Mar 19 02:56:04 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 217628 kb
Host smart-d772aa6c-2747-4fd3-9809-a7d813b393d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253984057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4253984057
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3965050053
Short name T451
Test name
Test status
Simulation time 53207915 ps
CPU time 1.51 seconds
Started Mar 19 02:55:57 PM PDT 24
Finished Mar 19 02:55:58 PM PDT 24
Peak memory 217920 kb
Host smart-de89faa4-20e2-4958-9989-364d28617960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965050053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3965050053
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.92658004
Short name T694
Test name
Test status
Simulation time 63969916 ps
CPU time 0.94 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 215428 kb
Host smart-34f76f4b-61b0-4f5e-aea9-1df775f2c2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92658004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.92658004
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2426379296
Short name T442
Test name
Test status
Simulation time 1227376846 ps
CPU time 2.93 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:03 PM PDT 24
Peak memory 219768 kb
Host smart-0d869d0f-6d57-415d-ac56-28045cf1cd8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426379296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2426379296
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3297702483
Short name T515
Test name
Test status
Simulation time 329004135311 ps
CPU time 1099.47 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 03:14:24 PM PDT 24
Peak memory 221928 kb
Host smart-04ab9cd3-7d5c-49d5-8d3e-f471f821e11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297702483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3297702483
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1103450082
Short name T620
Test name
Test status
Simulation time 40512939 ps
CPU time 1.65 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 218180 kb
Host smart-76aa8ad4-851e-4898-9e99-ff8a21faa9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103450082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1103450082
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3763185256
Short name T627
Test name
Test status
Simulation time 74404065 ps
CPU time 1.31 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 218268 kb
Host smart-ef1d61e0-e05e-4d3a-a994-ff4f0e22dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763185256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3763185256
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4079136418
Short name T385
Test name
Test status
Simulation time 41692634 ps
CPU time 1.31 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 217848 kb
Host smart-d309140c-2f95-469d-9b61-dfd36dff52f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079136418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4079136418
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.769051735
Short name T650
Test name
Test status
Simulation time 83573798 ps
CPU time 1.61 seconds
Started Mar 19 02:57:34 PM PDT 24
Finished Mar 19 02:57:36 PM PDT 24
Peak memory 218024 kb
Host smart-e5767840-a659-4afe-a746-6f5ff5e57072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769051735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.769051735
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1872171661
Short name T216
Test name
Test status
Simulation time 74541377 ps
CPU time 1.11 seconds
Started Mar 19 02:57:42 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 216596 kb
Host smart-8900bc9b-aba0-4d16-94fa-4c68d8e1f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872171661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1872171661
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.764294523
Short name T691
Test name
Test status
Simulation time 96401933 ps
CPU time 2.09 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:47 PM PDT 24
Peak memory 217008 kb
Host smart-12edcab7-1b31-4bb0-84b1-8d03f01ac1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764294523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.764294523
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2451208504
Short name T695
Test name
Test status
Simulation time 82325202 ps
CPU time 1.11 seconds
Started Mar 19 02:57:34 PM PDT 24
Finished Mar 19 02:57:35 PM PDT 24
Peak memory 215408 kb
Host smart-2ec62351-2b11-4040-ba51-942b51c8fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451208504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2451208504
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1110064303
Short name T710
Test name
Test status
Simulation time 47528915 ps
CPU time 1.41 seconds
Started Mar 19 02:57:37 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 215388 kb
Host smart-26e4ef6d-e37c-4e63-a1c3-c38376054232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110064303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1110064303
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3807541749
Short name T582
Test name
Test status
Simulation time 36638118 ps
CPU time 1.28 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 216784 kb
Host smart-a724f4e7-418e-48ca-a05b-4c1a86b4de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807541749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3807541749
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.3019208337
Short name T523
Test name
Test status
Simulation time 25322194 ps
CPU time 0.98 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 206688 kb
Host smart-bb217e9f-ac3d-4a7a-9286-bec08ebe2911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019208337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3019208337
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2024734411
Short name T553
Test name
Test status
Simulation time 14879547 ps
CPU time 0.89 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 215608 kb
Host smart-f5b67536-58d6-4fee-a770-268535f8d2ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024734411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2024734411
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.542840071
Short name T46
Test name
Test status
Simulation time 61581003 ps
CPU time 1.08 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 229752 kb
Host smart-cdeb8c36-1495-4444-aa8e-8456362fea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542840071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.542840071
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2881502991
Short name T433
Test name
Test status
Simulation time 128818075 ps
CPU time 0.98 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 216692 kb
Host smart-e3ee02cc-2c15-4e5b-ba80-3e2d8f31016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881502991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2881502991
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.926329954
Short name T400
Test name
Test status
Simulation time 34546052 ps
CPU time 0.88 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 215360 kb
Host smart-eaf95365-2194-421c-9b50-71baa4db073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926329954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.926329954
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2827872531
Short name T342
Test name
Test status
Simulation time 24794296 ps
CPU time 1 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 215404 kb
Host smart-bc001df3-c66b-4e3e-b1b9-17361ed3ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827872531 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2827872531
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.177918411
Short name T687
Test name
Test status
Simulation time 418074027 ps
CPU time 4.95 seconds
Started Mar 19 02:56:04 PM PDT 24
Finished Mar 19 02:56:10 PM PDT 24
Peak memory 216660 kb
Host smart-9c00ef77-f64d-4ad4-a2de-3383465400c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177918411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.177918411
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3329128597
Short name T215
Test name
Test status
Simulation time 108546915502 ps
CPU time 616.52 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 03:06:16 PM PDT 24
Peak memory 220060 kb
Host smart-44470a9a-330f-468e-a7e5-a58e9a9eb04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329128597 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3329128597
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2763095340
Short name T262
Test name
Test status
Simulation time 55064201 ps
CPU time 1.3 seconds
Started Mar 19 02:57:19 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 218156 kb
Host smart-350fe22c-c361-4b54-97d0-4b324cf01808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763095340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2763095340
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1517192461
Short name T599
Test name
Test status
Simulation time 73841497 ps
CPU time 1.62 seconds
Started Mar 19 02:57:16 PM PDT 24
Finished Mar 19 02:57:18 PM PDT 24
Peak memory 216736 kb
Host smart-2bf1116a-2744-44fe-9f9c-cad67e1dc4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517192461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1517192461
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.477181028
Short name T10
Test name
Test status
Simulation time 35920551 ps
CPU time 1.09 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 219360 kb
Host smart-e0274988-8483-4a20-a13a-2f5466742fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477181028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.477181028
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1819195745
Short name T8
Test name
Test status
Simulation time 751605229 ps
CPU time 4.8 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 219808 kb
Host smart-03afdab1-1f1c-432f-bacd-56b4ae2756aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819195745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1819195745
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3607921220
Short name T408
Test name
Test status
Simulation time 127016397 ps
CPU time 1.22 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 216696 kb
Host smart-aae4d4d7-2106-4bbd-8ff4-4ce07b42c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607921220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3607921220
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3504742609
Short name T781
Test name
Test status
Simulation time 431192340 ps
CPU time 4.42 seconds
Started Mar 19 02:57:19 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 219512 kb
Host smart-384214df-8045-4dda-b689-90056e8e8e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504742609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3504742609
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1323583658
Short name T258
Test name
Test status
Simulation time 20969420 ps
CPU time 1.1 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216884 kb
Host smart-2881202a-322c-47e5-aaa1-9e582690a587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323583658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1323583658
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2258004359
Short name T588
Test name
Test status
Simulation time 37845370 ps
CPU time 1.63 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 218000 kb
Host smart-b173b8da-90c2-4c31-8a15-d6f807e246a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258004359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2258004359
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.173689527
Short name T611
Test name
Test status
Simulation time 26525743 ps
CPU time 1.32 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 215880 kb
Host smart-01e289e9-3348-46ab-b19f-6dac7b21665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173689527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.173689527
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2777472572
Short name T645
Test name
Test status
Simulation time 24377750 ps
CPU time 1.01 seconds
Started Mar 19 02:56:10 PM PDT 24
Finished Mar 19 02:56:11 PM PDT 24
Peak memory 206164 kb
Host smart-14cede1d-6801-4816-9344-381d21dce8e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777472572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2777472572
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.947135093
Short name T833
Test name
Test status
Simulation time 17266539 ps
CPU time 0.88 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 215552 kb
Host smart-40939394-8ca8-4163-a465-904db66a57b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947135093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.947135093
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.4053944504
Short name T604
Test name
Test status
Simulation time 22698306 ps
CPU time 0.99 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 218216 kb
Host smart-ddb38266-0986-411f-a817-d331b2ace48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053944504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.4053944504
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3024682046
Short name T284
Test name
Test status
Simulation time 104485005 ps
CPU time 1.11 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 216796 kb
Host smart-b7bd7fcb-11b1-4599-bb80-5750b83c8c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024682046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3024682046
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.98849298
Short name T69
Test name
Test status
Simulation time 70531762 ps
CPU time 0.8 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 215544 kb
Host smart-fbb0795f-c9d4-44d7-83e5-b162571bd5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98849298 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.98849298
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4254962676
Short name T794
Test name
Test status
Simulation time 47947766 ps
CPU time 0.86 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 215456 kb
Host smart-3b972082-4c3e-4d34-92de-01dc4821b5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254962676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4254962676
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4192515576
Short name T405
Test name
Test status
Simulation time 168658626 ps
CPU time 2.37 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 216628 kb
Host smart-98c79888-0d23-4007-9c69-e17c28268731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192515576 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4192515576
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2682585340
Short name T210
Test name
Test status
Simulation time 179525185564 ps
CPU time 1803.1 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 03:26:18 PM PDT 24
Peak memory 225612 kb
Host smart-e89b2f1a-ac25-41f7-90c3-5daa4deba21c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682585340 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2682585340
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3631480701
Short name T640
Test name
Test status
Simulation time 165484924 ps
CPU time 1.2 seconds
Started Mar 19 02:57:44 PM PDT 24
Finished Mar 19 02:57:45 PM PDT 24
Peak memory 216876 kb
Host smart-68d87916-0d4d-4222-bc0a-eef50d6ad0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631480701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3631480701
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3966881318
Short name T769
Test name
Test status
Simulation time 32483912 ps
CPU time 1.47 seconds
Started Mar 19 02:57:21 PM PDT 24
Finished Mar 19 02:57:22 PM PDT 24
Peak memory 219496 kb
Host smart-699e2f90-fb70-4c97-a467-ce94a1bbaa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966881318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3966881318
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1882476744
Short name T578
Test name
Test status
Simulation time 400094506 ps
CPU time 1.42 seconds
Started Mar 19 02:57:38 PM PDT 24
Finished Mar 19 02:57:39 PM PDT 24
Peak memory 219512 kb
Host smart-a896b74c-abd3-4fc6-90cb-677ecb4c39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882476744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1882476744
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1640426445
Short name T689
Test name
Test status
Simulation time 29870270 ps
CPU time 1.35 seconds
Started Mar 19 02:57:24 PM PDT 24
Finished Mar 19 02:57:25 PM PDT 24
Peak memory 218208 kb
Host smart-f57d6d6d-b1b6-4445-b377-db60dddd9365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640426445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1640426445
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1575658574
Short name T502
Test name
Test status
Simulation time 56369499 ps
CPU time 1.03 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 216940 kb
Host smart-27124840-e5bb-4a5a-b46c-520f83769f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575658574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1575658574
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.735791018
Short name T788
Test name
Test status
Simulation time 48797979 ps
CPU time 1.42 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 217812 kb
Host smart-7aa11543-2c05-4a4a-848d-2047767dfd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735791018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.735791018
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.180778460
Short name T307
Test name
Test status
Simulation time 47267778 ps
CPU time 1.2 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 217884 kb
Host smart-a3084770-6e95-4614-b9c3-1fbb3e036665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180778460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.180778460
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2847383230
Short name T128
Test name
Test status
Simulation time 26573584 ps
CPU time 1.21 seconds
Started Mar 19 02:56:04 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 215780 kb
Host smart-f6a4feae-85a3-4cc5-9b81-f69bd282d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847383230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2847383230
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2374393482
Short name T550
Test name
Test status
Simulation time 44739242 ps
CPU time 0.93 seconds
Started Mar 19 02:56:06 PM PDT 24
Finished Mar 19 02:56:07 PM PDT 24
Peak memory 206980 kb
Host smart-b8b21cbd-a983-4ca7-9b11-36243a4f3da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374393482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2374393482
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2528681750
Short name T535
Test name
Test status
Simulation time 19660825 ps
CPU time 0.85 seconds
Started Mar 19 02:56:10 PM PDT 24
Finished Mar 19 02:56:11 PM PDT 24
Peak memory 215548 kb
Host smart-1f236b2a-9a47-4ffb-9e66-f46743aab5e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528681750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2528681750
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.830717352
Short name T775
Test name
Test status
Simulation time 29198930 ps
CPU time 1.18 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 216504 kb
Host smart-77917c6e-e79e-42d2-bd65-1c5138dc5019
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830717352 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.830717352
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1412145933
Short name T187
Test name
Test status
Simulation time 18293055 ps
CPU time 1.05 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 218184 kb
Host smart-05b89d61-49ef-46f8-8874-712f8ad2bc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412145933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1412145933
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.3509289105
Short name T42
Test name
Test status
Simulation time 24661480 ps
CPU time 1.07 seconds
Started Mar 19 02:56:10 PM PDT 24
Finished Mar 19 02:56:11 PM PDT 24
Peak memory 232564 kb
Host smart-3caa5f2b-a682-4525-9535-6823e4805899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509289105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3509289105
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2000050804
Short name T690
Test name
Test status
Simulation time 23069545 ps
CPU time 0.96 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 215444 kb
Host smart-a9b3c608-e7ed-476f-a29d-adf327fa94cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000050804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2000050804
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3907945468
Short name T479
Test name
Test status
Simulation time 356612878 ps
CPU time 2.31 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:09 PM PDT 24
Peak memory 216888 kb
Host smart-4ea37e91-200f-4c5c-90c7-a32cd6932dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907945468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3907945468
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2922456226
Short name T619
Test name
Test status
Simulation time 140130965299 ps
CPU time 3076.9 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 03:47:20 PM PDT 24
Peak memory 230504 kb
Host smart-85346109-d6d8-421e-886f-2bf8b015a821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922456226 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2922456226
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2322772546
Short name T486
Test name
Test status
Simulation time 174274390 ps
CPU time 1.47 seconds
Started Mar 19 02:57:21 PM PDT 24
Finished Mar 19 02:57:23 PM PDT 24
Peak memory 218300 kb
Host smart-aed9f45b-cc7f-46c3-8e21-4e9cadd4e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322772546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2322772546
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3414267942
Short name T304
Test name
Test status
Simulation time 73764115 ps
CPU time 1.44 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 218000 kb
Host smart-5d60b9c9-ea2b-461c-9ff7-b623f0de1011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414267942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3414267942
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.788276227
Short name T282
Test name
Test status
Simulation time 43285230 ps
CPU time 1.44 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 216708 kb
Host smart-9aef649f-3373-4313-80d0-be2ad041076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788276227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.788276227
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.740258260
Short name T792
Test name
Test status
Simulation time 61571307 ps
CPU time 1.25 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 216832 kb
Host smart-b84f1f92-5223-4ab0-8719-3a7a9028d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740258260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.740258260
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.4020119401
Short name T278
Test name
Test status
Simulation time 110415587 ps
CPU time 1.36 seconds
Started Mar 19 02:57:17 PM PDT 24
Finished Mar 19 02:57:19 PM PDT 24
Peak memory 218360 kb
Host smart-fb5df882-f1ce-4f97-8153-110211d33e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020119401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4020119401
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1310781644
Short name T410
Test name
Test status
Simulation time 43974345 ps
CPU time 1.49 seconds
Started Mar 19 02:57:23 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 216884 kb
Host smart-3c5edc71-db0e-450b-9eb2-e257c9ad3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310781644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1310781644
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.921583965
Short name T468
Test name
Test status
Simulation time 89329073 ps
CPU time 1.16 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:46 PM PDT 24
Peak memory 216876 kb
Host smart-6659244a-8823-4315-9601-7b99090e117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921583965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.921583965
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.99188519
Short name T370
Test name
Test status
Simulation time 63848561 ps
CPU time 1.02 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:23 PM PDT 24
Peak memory 216696 kb
Host smart-9e72df50-72c7-4bf3-8cea-1784ee6a3636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99188519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.99188519
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.4057201394
Short name T38
Test name
Test status
Simulation time 59301094 ps
CPU time 1.99 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 215500 kb
Host smart-4758724e-fd38-42e7-a3cc-f8f805cad6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057201394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4057201394
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.473627553
Short name T825
Test name
Test status
Simulation time 86918455 ps
CPU time 1.23 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 215792 kb
Host smart-f4850227-52d3-458e-83f8-7ab8b578a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473627553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.473627553
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.675374709
Short name T766
Test name
Test status
Simulation time 121869162 ps
CPU time 0.86 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 206788 kb
Host smart-1d91e94c-6b67-4975-9d26-af423e7e8a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675374709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.675374709
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3217710081
Short name T48
Test name
Test status
Simulation time 21654550 ps
CPU time 0.9 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 216012 kb
Host smart-4e86d2ed-9761-4eba-b087-e89fa07a5132
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217710081 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3217710081
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1163923396
Short name T103
Test name
Test status
Simulation time 19218024 ps
CPU time 1.01 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 218100 kb
Host smart-f90229d9-3547-44a2-bab2-50c110ca1a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163923396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1163923396
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3376830396
Short name T745
Test name
Test status
Simulation time 75835903 ps
CPU time 1.08 seconds
Started Mar 19 02:56:04 PM PDT 24
Finished Mar 19 02:56:05 PM PDT 24
Peak memory 216880 kb
Host smart-adb96e64-058b-4056-819b-742cb1b58f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376830396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3376830396
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2672312832
Short name T703
Test name
Test status
Simulation time 21908829 ps
CPU time 1.22 seconds
Started Mar 19 02:56:04 PM PDT 24
Finished Mar 19 02:56:05 PM PDT 24
Peak memory 224116 kb
Host smart-fd7729ce-e307-48ae-9e6f-3677684bfc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672312832 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2672312832
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.442828482
Short name T787
Test name
Test status
Simulation time 16589835 ps
CPU time 0.98 seconds
Started Mar 19 02:56:05 PM PDT 24
Finished Mar 19 02:56:06 PM PDT 24
Peak memory 215440 kb
Host smart-8a18b471-9f43-490d-9347-d3b7ef203424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442828482 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.442828482
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.583890285
Short name T150
Test name
Test status
Simulation time 722704926 ps
CPU time 4.16 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 02:56:11 PM PDT 24
Peak memory 215448 kb
Host smart-5308f1ae-6f7d-4420-ace8-dfedc0d573ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583890285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.583890285
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1722751682
Short name T799
Test name
Test status
Simulation time 758895349668 ps
CPU time 2109.74 seconds
Started Mar 19 02:56:07 PM PDT 24
Finished Mar 19 03:31:17 PM PDT 24
Peak memory 226160 kb
Host smart-f4296d5d-28fc-4963-8589-56dbeb693690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722751682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1722751682
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1929508123
Short name T391
Test name
Test status
Simulation time 101725252 ps
CPU time 1.26 seconds
Started Mar 19 02:57:18 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 216956 kb
Host smart-7c7add1e-d39b-4d08-8d83-2901ef6ccc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929508123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1929508123
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1743416246
Short name T623
Test name
Test status
Simulation time 57032834 ps
CPU time 1.48 seconds
Started Mar 19 02:57:18 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 216896 kb
Host smart-efb862c1-d6cf-4486-9870-95da0c0a9e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743416246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1743416246
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.4289786391
Short name T420
Test name
Test status
Simulation time 38979027 ps
CPU time 1.48 seconds
Started Mar 19 02:57:18 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 218088 kb
Host smart-9d8d7a20-a526-4461-a1a7-cee3915641f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289786391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4289786391
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1486641010
Short name T715
Test name
Test status
Simulation time 81201376 ps
CPU time 1.17 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:23 PM PDT 24
Peak memory 218236 kb
Host smart-aedd059e-1b7c-4be2-8797-fded8409c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486641010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1486641010
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.4097440805
Short name T814
Test name
Test status
Simulation time 31879096 ps
CPU time 1.29 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 217988 kb
Host smart-82eae50d-3ad8-4bea-84ef-2217c49afa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097440805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4097440805
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2856386853
Short name T764
Test name
Test status
Simulation time 70668021 ps
CPU time 2.32 seconds
Started Mar 19 02:57:21 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 219464 kb
Host smart-0db51b4c-caca-44b0-9ab8-0acd98524e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856386853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2856386853
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3659514024
Short name T474
Test name
Test status
Simulation time 73719141 ps
CPU time 2.91 seconds
Started Mar 19 02:57:18 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 219576 kb
Host smart-fe0ee504-863a-4a91-8ced-7ce6e2f35bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659514024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3659514024
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.869442873
Short name T587
Test name
Test status
Simulation time 42709133 ps
CPU time 1.38 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 216616 kb
Host smart-6fda9906-e480-4dd9-a1fd-52552f8efab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869442873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.869442873
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1255111920
Short name T382
Test name
Test status
Simulation time 38769209 ps
CPU time 1.68 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 217948 kb
Host smart-a91e1ddf-47be-409e-b6f0-06f9fe67e87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255111920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1255111920
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1267530181
Short name T390
Test name
Test status
Simulation time 45311013 ps
CPU time 1.57 seconds
Started Mar 19 02:57:37 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 218232 kb
Host smart-885b0edf-8f51-4e07-b9f4-97e846660c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267530181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1267530181
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2062852184
Short name T198
Test name
Test status
Simulation time 43960447 ps
CPU time 1.3 seconds
Started Mar 19 02:56:16 PM PDT 24
Finished Mar 19 02:56:17 PM PDT 24
Peak memory 215784 kb
Host smart-871cc579-acc2-4af9-905b-a3e0f88007eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062852184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2062852184
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3653675738
Short name T190
Test name
Test status
Simulation time 66796279 ps
CPU time 1.04 seconds
Started Mar 19 02:56:12 PM PDT 24
Finished Mar 19 02:56:13 PM PDT 24
Peak memory 216712 kb
Host smart-5379946e-dcb6-4a49-b7b9-df0acc55a085
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653675738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3653675738
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1963411788
Short name T503
Test name
Test status
Simulation time 48314326 ps
CPU time 1.27 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 224316 kb
Host smart-cfb739c0-fb8b-45b1-a360-f2b8db2df297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963411788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1963411788
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2985371658
Short name T666
Test name
Test status
Simulation time 50299908 ps
CPU time 1.93 seconds
Started Mar 19 02:56:13 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 217848 kb
Host smart-5ffed30a-e89b-4102-8c48-16887016d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985371658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2985371658
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.546327015
Short name T317
Test name
Test status
Simulation time 22441225 ps
CPU time 0.92 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 215404 kb
Host smart-d87edef3-2ac9-40f2-b2ab-6efd6bc1e054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546327015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.546327015
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1198368022
Short name T827
Test name
Test status
Simulation time 706047212 ps
CPU time 4.1 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:16 PM PDT 24
Peak memory 216676 kb
Host smart-34435870-fc57-4520-93fa-28cccf933ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198368022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1198368022
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.142637789
Short name T148
Test name
Test status
Simulation time 22352081869 ps
CPU time 560.21 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 03:05:35 PM PDT 24
Peak memory 216824 kb
Host smart-34e6d848-450e-4bac-982a-3313417f2af3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142637789 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.142637789
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.896620755
Short name T454
Test name
Test status
Simulation time 71654611 ps
CPU time 1.13 seconds
Started Mar 19 02:57:21 PM PDT 24
Finished Mar 19 02:57:23 PM PDT 24
Peak memory 216848 kb
Host smart-111aef6e-9bff-4d7b-86f7-277bc3d38a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896620755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.896620755
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.733807505
Short name T497
Test name
Test status
Simulation time 60522564 ps
CPU time 1.35 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 218860 kb
Host smart-a226e3c0-649c-4a08-83b2-9032c8f1a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733807505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.733807505
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2661217145
Short name T475
Test name
Test status
Simulation time 55021094 ps
CPU time 2.07 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 219456 kb
Host smart-ec277c4d-46ed-4dfc-a61f-9e8605ab8c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661217145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2661217145
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.787730782
Short name T335
Test name
Test status
Simulation time 49883870 ps
CPU time 1.28 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216804 kb
Host smart-10090bc4-5a7f-4b9c-8473-edac91a1b86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787730782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.787730782
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3204508330
Short name T802
Test name
Test status
Simulation time 142474144 ps
CPU time 1.58 seconds
Started Mar 19 02:57:23 PM PDT 24
Finished Mar 19 02:57:25 PM PDT 24
Peak memory 218660 kb
Host smart-dc605964-6c5f-4443-88eb-c7e30cc6840d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204508330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3204508330
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.517913193
Short name T592
Test name
Test status
Simulation time 232073362 ps
CPU time 1.6 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 218364 kb
Host smart-4590b47e-6c59-4354-b996-13e80c3eb879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517913193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.517913193
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2400841539
Short name T812
Test name
Test status
Simulation time 37919748 ps
CPU time 1.4 seconds
Started Mar 19 02:57:33 PM PDT 24
Finished Mar 19 02:57:35 PM PDT 24
Peak memory 218012 kb
Host smart-f50f0477-31e3-4df0-a419-3c0aa4cb5bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400841539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2400841539
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2631711620
Short name T507
Test name
Test status
Simulation time 36715127 ps
CPU time 1.55 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 217964 kb
Host smart-b15cbf7b-8c35-4fdb-b2d5-d7acb6fdf158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631711620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2631711620
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.4202556292
Short name T835
Test name
Test status
Simulation time 70588969 ps
CPU time 1.45 seconds
Started Mar 19 02:57:28 PM PDT 24
Finished Mar 19 02:57:30 PM PDT 24
Peak memory 219040 kb
Host smart-640204f1-8d5a-4baf-a0fa-9e281fed7ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202556292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4202556292
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1415211858
Short name T94
Test name
Test status
Simulation time 27422298 ps
CPU time 1.28 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 215784 kb
Host smart-f06c3608-1d35-41a1-b1bc-ddd4c0baa155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415211858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1415211858
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3417124830
Short name T336
Test name
Test status
Simulation time 222265469 ps
CPU time 3.74 seconds
Started Mar 19 02:56:13 PM PDT 24
Finished Mar 19 02:56:17 PM PDT 24
Peak memory 207048 kb
Host smart-3a509d5a-93cd-46d6-9de8-3301fa50111b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417124830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3417124830
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2196907989
Short name T324
Test name
Test status
Simulation time 114531487 ps
CPU time 1.18 seconds
Started Mar 19 02:56:12 PM PDT 24
Finished Mar 19 02:56:13 PM PDT 24
Peak memory 216496 kb
Host smart-4cd92751-c76f-4533-93bc-0a673556204b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196907989 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2196907989
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.615837591
Short name T120
Test name
Test status
Simulation time 24681374 ps
CPU time 0.92 seconds
Started Mar 19 02:56:13 PM PDT 24
Finished Mar 19 02:56:14 PM PDT 24
Peak memory 217784 kb
Host smart-7acd4cb0-b3e5-4895-8ef4-40381f0d4bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615837591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.615837591
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.4221069781
Short name T642
Test name
Test status
Simulation time 70281752 ps
CPU time 1.73 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:13 PM PDT 24
Peak memory 218012 kb
Host smart-70bee04e-96e5-4336-b1b7-864bd22b40ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221069781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4221069781
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1232854706
Short name T364
Test name
Test status
Simulation time 61313013 ps
CPU time 0.87 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:13 PM PDT 24
Peak memory 215524 kb
Host smart-d3cba7e4-c907-4885-b477-be423992c58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232854706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1232854706
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.352817503
Short name T165
Test name
Test status
Simulation time 46091450 ps
CPU time 0.91 seconds
Started Mar 19 02:56:17 PM PDT 24
Finished Mar 19 02:56:18 PM PDT 24
Peak memory 215412 kb
Host smart-2692776e-ebb4-4259-9946-5bdfc7239c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352817503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.352817503
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1511865873
Short name T655
Test name
Test status
Simulation time 32607804 ps
CPU time 1.2 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 206132 kb
Host smart-4c22fc3c-d0d8-4663-a58d-73723189f4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511865873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1511865873
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1056883239
Short name T209
Test name
Test status
Simulation time 71361821360 ps
CPU time 881.79 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 03:11:06 PM PDT 24
Peak memory 220200 kb
Host smart-d0695ea3-d4a0-4083-93f3-467071654678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056883239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1056883239
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.733621506
Short name T785
Test name
Test status
Simulation time 56975693 ps
CPU time 1.26 seconds
Started Mar 19 02:57:36 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 216656 kb
Host smart-bcbb3728-f934-4f9e-a64f-605dbadca24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733621506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.733621506
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3705722950
Short name T806
Test name
Test status
Simulation time 2288799924 ps
CPU time 72.66 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:58:59 PM PDT 24
Peak memory 218196 kb
Host smart-bfa9f8c9-081a-4982-ac6b-ffee1bb50d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705722950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3705722950
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2735453490
Short name T64
Test name
Test status
Simulation time 112173101 ps
CPU time 1.33 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 218172 kb
Host smart-5888926c-0ef3-438a-9758-4bfeb68d79c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735453490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2735453490
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.140286503
Short name T407
Test name
Test status
Simulation time 87281032 ps
CPU time 1.3 seconds
Started Mar 19 02:57:31 PM PDT 24
Finished Mar 19 02:57:33 PM PDT 24
Peak memory 218136 kb
Host smart-b8376398-0e3f-4949-b355-f4b7bcf367fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140286503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.140286503
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4198430165
Short name T668
Test name
Test status
Simulation time 31970766 ps
CPU time 1.35 seconds
Started Mar 19 02:57:23 PM PDT 24
Finished Mar 19 02:57:25 PM PDT 24
Peak memory 216796 kb
Host smart-3f4e8d53-d686-473a-9d5d-bf9b5cf5771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198430165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4198430165
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2338961622
Short name T529
Test name
Test status
Simulation time 37691565 ps
CPU time 1.45 seconds
Started Mar 19 02:57:42 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 217944 kb
Host smart-c8f1a4c2-e758-47f2-acad-d5518c1dcebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338961622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2338961622
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1487615416
Short name T830
Test name
Test status
Simulation time 78550866 ps
CPU time 1.48 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 218368 kb
Host smart-8ef165a0-2aee-45f7-8b1c-a357efc7b075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487615416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1487615416
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1154402014
Short name T590
Test name
Test status
Simulation time 59285542 ps
CPU time 1.4 seconds
Started Mar 19 02:57:33 PM PDT 24
Finished Mar 19 02:57:34 PM PDT 24
Peak memory 218232 kb
Host smart-7832efbc-2cf8-43fb-85c3-0db76cc45fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154402014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1154402014
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3668653979
Short name T542
Test name
Test status
Simulation time 47600713 ps
CPU time 1.28 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 216860 kb
Host smart-cf574065-60eb-4450-a64f-d368d6d6aa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668653979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3668653979
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.723262169
Short name T664
Test name
Test status
Simulation time 60763783 ps
CPU time 1.21 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 216956 kb
Host smart-fd0c59b0-a4f9-432d-9c1a-64ea2034e56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723262169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.723262169
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.639713404
Short name T127
Test name
Test status
Simulation time 52737664 ps
CPU time 1.19 seconds
Started Mar 19 02:56:12 PM PDT 24
Finished Mar 19 02:56:14 PM PDT 24
Peak memory 215772 kb
Host smart-ab6a1777-fc09-4b84-8ad1-06984dd5438c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639713404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.639713404
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1496694355
Short name T580
Test name
Test status
Simulation time 48628173 ps
CPU time 0.89 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 206732 kb
Host smart-78d62605-2dbb-4991-82ac-94bb479109c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496694355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1496694355
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1214857518
Short name T200
Test name
Test status
Simulation time 12295401 ps
CPU time 0.9 seconds
Started Mar 19 02:56:16 PM PDT 24
Finished Mar 19 02:56:17 PM PDT 24
Peak memory 215732 kb
Host smart-2aa8d644-5138-4f2f-b1b6-5adfb50f1925
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214857518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1214857518
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2807474044
Short name T539
Test name
Test status
Simulation time 43945236 ps
CPU time 1.25 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:16 PM PDT 24
Peak memory 216712 kb
Host smart-0ac45270-4935-4b35-bd88-65b293a3bcca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807474044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2807474044
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1832015061
Short name T182
Test name
Test status
Simulation time 39644490 ps
CPU time 1.04 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 02:56:17 PM PDT 24
Peak memory 219572 kb
Host smart-87d0949c-fc4f-4721-a19a-0652ffdd69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832015061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1832015061
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.272604951
Short name T139
Test name
Test status
Simulation time 430781247 ps
CPU time 4.23 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 02:56:20 PM PDT 24
Peak memory 217172 kb
Host smart-108ea772-6dd0-4ad8-98cb-157654d431ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272604951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.272604951
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3918437883
Short name T136
Test name
Test status
Simulation time 53957644 ps
CPU time 0.83 seconds
Started Mar 19 02:56:13 PM PDT 24
Finished Mar 19 02:56:14 PM PDT 24
Peak memory 215680 kb
Host smart-ec3debad-7fe0-4ded-9791-a27e2faaa0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918437883 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3918437883
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2877648699
Short name T709
Test name
Test status
Simulation time 123337324 ps
CPU time 0.87 seconds
Started Mar 19 02:56:13 PM PDT 24
Finished Mar 19 02:56:14 PM PDT 24
Peak memory 215432 kb
Host smart-1a63ec5b-5dd9-48ae-878d-8c36867e288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877648699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2877648699
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3891184189
Short name T277
Test name
Test status
Simulation time 130755200 ps
CPU time 2.98 seconds
Started Mar 19 02:56:17 PM PDT 24
Finished Mar 19 02:56:20 PM PDT 24
Peak memory 216580 kb
Host smart-97caa214-1f2f-46a8-bb3c-0143e227a73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891184189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3891184189
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2293170858
Short name T149
Test name
Test status
Simulation time 48776066397 ps
CPU time 769.48 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 03:09:00 PM PDT 24
Peak memory 218724 kb
Host smart-b39924fb-a9c6-4bc8-8f90-010d17f3a324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293170858 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2293170858
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4001351203
Short name T746
Test name
Test status
Simulation time 52774408 ps
CPU time 1.42 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 218004 kb
Host smart-d78f02d5-ee01-4040-801d-5053b2548199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001351203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4001351203
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2056749209
Short name T348
Test name
Test status
Simulation time 241150364 ps
CPU time 2.55 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 219732 kb
Host smart-6b94f124-f179-4d50-a514-5180cc095855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056749209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2056749209
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.211428892
Short name T504
Test name
Test status
Simulation time 53255904 ps
CPU time 1.24 seconds
Started Mar 19 02:57:23 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 216704 kb
Host smart-4462783d-25c1-4320-9c89-514e424ca89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211428892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.211428892
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2656360583
Short name T484
Test name
Test status
Simulation time 166185531 ps
CPU time 1.2 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 218040 kb
Host smart-9f155bd0-1d19-4f48-9fa8-1ba19bb43418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656360583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2656360583
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2222778074
Short name T567
Test name
Test status
Simulation time 74620584 ps
CPU time 1.69 seconds
Started Mar 19 02:57:36 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 217912 kb
Host smart-b491ba61-0f99-4188-987f-41cd92432be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222778074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2222778074
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3153820935
Short name T481
Test name
Test status
Simulation time 62187113 ps
CPU time 1.35 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216872 kb
Host smart-ef9e8ec2-e262-45d8-afb5-a3912db01fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153820935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3153820935
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.244744318
Short name T680
Test name
Test status
Simulation time 30748824 ps
CPU time 1.28 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 219392 kb
Host smart-bd11573e-5a4f-452d-a519-8aa274cf6c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244744318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.244744318
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.673609714
Short name T725
Test name
Test status
Simulation time 85757717 ps
CPU time 1.53 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 216768 kb
Host smart-003361dc-13f4-443a-a728-2a75b08b0543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673609714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.673609714
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.239658151
Short name T754
Test name
Test status
Simulation time 91725432 ps
CPU time 1.15 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216840 kb
Host smart-715b18f3-40cf-44df-8857-e906edfe98ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239658151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.239658151
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3009822164
Short name T259
Test name
Test status
Simulation time 38220074 ps
CPU time 1.39 seconds
Started Mar 19 02:57:35 PM PDT 24
Finished Mar 19 02:57:37 PM PDT 24
Peak memory 217860 kb
Host smart-00b47c21-2d5c-4f3f-9340-4c52174f4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009822164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3009822164
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4269587474
Short name T672
Test name
Test status
Simulation time 71957966 ps
CPU time 1.2 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 02:56:17 PM PDT 24
Peak memory 215748 kb
Host smart-1336762a-52d6-4706-8fd0-0ef45040df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269587474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4269587474
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3391662033
Short name T730
Test name
Test status
Simulation time 26682643 ps
CPU time 0.84 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:24 PM PDT 24
Peak memory 206604 kb
Host smart-b0354f29-36dc-45b8-b0d9-a0ab9506482c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391662033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3391662033
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1804174453
Short name T597
Test name
Test status
Simulation time 29597911 ps
CPU time 0.86 seconds
Started Mar 19 02:56:13 PM PDT 24
Finished Mar 19 02:56:14 PM PDT 24
Peak memory 215668 kb
Host smart-31266f82-322c-40c1-96d4-96e47a8cf53e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804174453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1804174453
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2164990480
Short name T175
Test name
Test status
Simulation time 43863829 ps
CPU time 1.14 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 216824 kb
Host smart-bb509bbf-36a0-40e8-9b44-a061a2c64f91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164990480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2164990480
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1636257584
Short name T125
Test name
Test status
Simulation time 36519981 ps
CPU time 0.92 seconds
Started Mar 19 02:56:15 PM PDT 24
Finished Mar 19 02:56:16 PM PDT 24
Peak memory 218016 kb
Host smart-c17393b6-9eea-4424-83a7-5c6420fb2c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636257584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1636257584
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2038284169
Short name T635
Test name
Test status
Simulation time 74989236 ps
CPU time 1.24 seconds
Started Mar 19 02:56:16 PM PDT 24
Finished Mar 19 02:56:18 PM PDT 24
Peak memory 216660 kb
Host smart-b7daedcb-aed4-40db-a18c-9c41eede1a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038284169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2038284169
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2117604651
Short name T416
Test name
Test status
Simulation time 26182140 ps
CPU time 1.08 seconds
Started Mar 19 02:56:11 PM PDT 24
Finished Mar 19 02:56:12 PM PDT 24
Peak memory 232540 kb
Host smart-d99f7825-88fc-4bac-8250-69a8db043223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117604651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2117604651
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.608137934
Short name T829
Test name
Test status
Simulation time 37039135 ps
CPU time 0.88 seconds
Started Mar 19 02:56:14 PM PDT 24
Finished Mar 19 02:56:15 PM PDT 24
Peak memory 207252 kb
Host smart-62e7b104-47cb-417e-ad44-605e76115720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608137934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.608137934
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3803716152
Short name T153
Test name
Test status
Simulation time 166727768 ps
CPU time 2.02 seconds
Started Mar 19 02:56:21 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 215216 kb
Host smart-1d7ff7c9-f5f9-4dc0-9e4b-c3ed04bf3e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803716152 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3803716152
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2757527999
Short name T743
Test name
Test status
Simulation time 19458179654 ps
CPU time 448.64 seconds
Started Mar 19 02:56:21 PM PDT 24
Finished Mar 19 03:03:50 PM PDT 24
Peak memory 216916 kb
Host smart-3f2851dc-e01f-4c0c-90c8-c0d6ed4a79df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757527999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2757527999
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3083132213
Short name T371
Test name
Test status
Simulation time 115154358 ps
CPU time 2.81 seconds
Started Mar 19 02:57:38 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 217952 kb
Host smart-ed788455-ae3d-4f69-b7c4-b92bb9fd4f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083132213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3083132213
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1872762571
Short name T285
Test name
Test status
Simulation time 46230097 ps
CPU time 1.52 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:48 PM PDT 24
Peak memory 216792 kb
Host smart-c1e34829-7dc6-4275-9930-ed83d38806b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872762571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1872762571
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3396573596
Short name T449
Test name
Test status
Simulation time 124544145 ps
CPU time 1.19 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 216816 kb
Host smart-abd66b32-3427-41c4-8e23-71ea58d07b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396573596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3396573596
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3759564165
Short name T447
Test name
Test status
Simulation time 29417200 ps
CPU time 1.21 seconds
Started Mar 19 02:57:36 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 218064 kb
Host smart-2c614ffb-422a-48cf-851b-b4ba168cae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759564165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3759564165
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1131658291
Short name T11
Test name
Test status
Simulation time 42182487 ps
CPU time 1.26 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 218884 kb
Host smart-175a1b95-8f9e-4f8b-b65f-4a4c4f373556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131658291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1131658291
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1751402957
Short name T290
Test name
Test status
Simulation time 79475429 ps
CPU time 1.11 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 216916 kb
Host smart-3b77dd13-a5a2-4b98-8a0e-7b982d77eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751402957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1751402957
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2214104609
Short name T39
Test name
Test status
Simulation time 59301208 ps
CPU time 1.61 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216860 kb
Host smart-bc37a934-3a85-4f98-9c9a-a5fb4849a2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214104609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2214104609
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3323690993
Short name T287
Test name
Test status
Simulation time 41308638 ps
CPU time 1.53 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 218004 kb
Host smart-25c1e7ba-102e-4e75-8bc1-eb121962920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323690993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3323690993
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2648356744
Short name T330
Test name
Test status
Simulation time 45572237 ps
CPU time 1.24 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216968 kb
Host smart-51e75e07-0212-402c-bb1c-64d0cd57f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648356744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2648356744
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.870407380
Short name T508
Test name
Test status
Simulation time 46865205 ps
CPU time 1.28 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:26 PM PDT 24
Peak memory 216816 kb
Host smart-bf6e2df6-14d1-4726-9745-d3cf830f8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870407380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.870407380
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1690446149
Short name T458
Test name
Test status
Simulation time 43233093 ps
CPU time 1.17 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 215816 kb
Host smart-a7792d3d-b095-408e-b26c-987dd298d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690446149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1690446149
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2026317508
Short name T446
Test name
Test status
Simulation time 21510289 ps
CPU time 0.98 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:48 PM PDT 24
Peak memory 206992 kb
Host smart-931c5a95-6353-4565-a85c-a1d1267a273a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026317508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2026317508
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.69091835
Short name T707
Test name
Test status
Simulation time 42024618 ps
CPU time 0.87 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 216012 kb
Host smart-bd88d73d-0377-4da5-bf01-48db1d08cb55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69091835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.69091835
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.2958549289
Short name T789
Test name
Test status
Simulation time 29692374 ps
CPU time 1.01 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 218384 kb
Host smart-6798f4a5-8f0a-44b3-82d1-f140f1588f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958549289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2958549289
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.258006366
Short name T422
Test name
Test status
Simulation time 45111360 ps
CPU time 1.87 seconds
Started Mar 19 02:55:49 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 216960 kb
Host smart-e7d8299b-7944-45b7-828a-01ba4e6f12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258006366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.258006366
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3269049304
Short name T143
Test name
Test status
Simulation time 27001325 ps
CPU time 0.94 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215976 kb
Host smart-dcf8fc80-265b-4c2d-9b1b-ba4436ffc1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269049304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3269049304
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.4075071214
Short name T131
Test name
Test status
Simulation time 14840721 ps
CPU time 1.02 seconds
Started Mar 19 02:55:43 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 207256 kb
Host smart-3d122c69-5b01-4b39-a0d8-16f6100f5e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075071214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.4075071214
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1666465875
Short name T19
Test name
Test status
Simulation time 1040496989 ps
CPU time 6.05 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 235708 kb
Host smart-a4097381-717c-4aa8-8ade-2c22bd1be6e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666465875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1666465875
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2974790558
Short name T443
Test name
Test status
Simulation time 15894469 ps
CPU time 0.98 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:55:47 PM PDT 24
Peak memory 215428 kb
Host smart-80fc30be-6850-4852-b20b-72e1cdfa0542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974790558 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2974790558
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3427304279
Short name T572
Test name
Test status
Simulation time 244249165 ps
CPU time 5 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:54 PM PDT 24
Peak memory 216768 kb
Host smart-a856f167-82b7-4457-9c93-e5cc229d2ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427304279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3427304279
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1111402088
Short name T744
Test name
Test status
Simulation time 442384539087 ps
CPU time 575.52 seconds
Started Mar 19 02:55:49 PM PDT 24
Finished Mar 19 03:05:26 PM PDT 24
Peak memory 218140 kb
Host smart-f8c2863a-b2c4-4c1a-bd55-84bcaac490c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111402088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1111402088
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1726358844
Short name T424
Test name
Test status
Simulation time 49241615 ps
CPU time 1.28 seconds
Started Mar 19 02:56:25 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 215768 kb
Host smart-da07abca-ccdb-4b5d-aa33-75f96d8e33a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726358844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1726358844
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1262327054
Short name T388
Test name
Test status
Simulation time 35740664 ps
CPU time 1.05 seconds
Started Mar 19 02:56:25 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 206208 kb
Host smart-89abec49-6966-435d-92f0-4c71ca759b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262327054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1262327054
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.918827168
Short name T773
Test name
Test status
Simulation time 89042839 ps
CPU time 1.13 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:24 PM PDT 24
Peak memory 216680 kb
Host smart-03cef015-5b56-45db-baf6-bae44f0e4142
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918827168 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.918827168
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2251078736
Short name T485
Test name
Test status
Simulation time 39919997 ps
CPU time 0.88 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 217720 kb
Host smart-38fdc448-f870-4348-a70f-04e0925b2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251078736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2251078736
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.268947132
Short name T461
Test name
Test status
Simulation time 173318065 ps
CPU time 3.38 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:27 PM PDT 24
Peak memory 219696 kb
Host smart-c295f989-aa02-45dc-99ac-ae36fc7a3eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268947132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.268947132
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1538326960
Short name T372
Test name
Test status
Simulation time 22526278 ps
CPU time 1.15 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 215696 kb
Host smart-a9fb923b-13e7-4125-9222-0f69a3dac15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538326960 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1538326960
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1564932460
Short name T22
Test name
Test status
Simulation time 17915277 ps
CPU time 1 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 215424 kb
Host smart-bc07f034-b9d3-472d-b636-b338819a6a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564932460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1564932460
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.496049952
Short name T721
Test name
Test status
Simulation time 486942462 ps
CPU time 3 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 215436 kb
Host smart-2543e420-b0e9-47fb-9af1-011bd5cce20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496049952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.496049952
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.3982275221
Short name T551
Test name
Test status
Simulation time 50614755 ps
CPU time 1.58 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:33 PM PDT 24
Peak memory 218244 kb
Host smart-a52face8-23a2-44d5-ad30-e11db71bc738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982275221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3982275221
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4262322580
Short name T663
Test name
Test status
Simulation time 34290553 ps
CPU time 1.73 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 217912 kb
Host smart-fb5e7e32-922c-4e15-adff-84dbdd0eb061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262322580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4262322580
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2583733149
Short name T573
Test name
Test status
Simulation time 124000206 ps
CPU time 1.49 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216932 kb
Host smart-150cd39f-c069-4c9c-b323-c31477fb89f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583733149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2583733149
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2649270836
Short name T579
Test name
Test status
Simulation time 82941687 ps
CPU time 1.07 seconds
Started Mar 19 02:57:33 PM PDT 24
Finished Mar 19 02:57:34 PM PDT 24
Peak memory 216860 kb
Host smart-f90b3747-a5f6-4f56-bdc8-80bf63e2b82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649270836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2649270836
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4140338958
Short name T323
Test name
Test status
Simulation time 38792734 ps
CPU time 1.15 seconds
Started Mar 19 02:57:30 PM PDT 24
Finished Mar 19 02:57:31 PM PDT 24
Peak memory 216600 kb
Host smart-f3e62045-0e29-418d-9cb4-1f2e5e9bcd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140338958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4140338958
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.730982782
Short name T329
Test name
Test status
Simulation time 224670967 ps
CPU time 2.92 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 219700 kb
Host smart-5c6ddb28-2c60-4d22-a6e6-7b51798ba658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730982782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.730982782
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2511506592
Short name T35
Test name
Test status
Simulation time 75526860 ps
CPU time 1.26 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216696 kb
Host smart-657e7c64-8d50-4f2a-95d7-53e645c8c173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511506592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2511506592
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4100807283
Short name T641
Test name
Test status
Simulation time 54859572 ps
CPU time 1.04 seconds
Started Mar 19 02:57:31 PM PDT 24
Finished Mar 19 02:57:32 PM PDT 24
Peak memory 216492 kb
Host smart-9b602678-5020-40af-90bc-912aa0a4b973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100807283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4100807283
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1123530976
Short name T733
Test name
Test status
Simulation time 36307060 ps
CPU time 1.29 seconds
Started Mar 19 02:57:49 PM PDT 24
Finished Mar 19 02:57:51 PM PDT 24
Peak memory 218032 kb
Host smart-77ce5dd1-43c6-4dc7-82ec-a55bac214144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123530976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1123530976
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.3216871831
Short name T755
Test name
Test status
Simulation time 173543577 ps
CPU time 1.03 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:24 PM PDT 24
Peak memory 206196 kb
Host smart-90b8127f-1512-43ff-8631-7f75c8d57c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216871831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3216871831
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1812552635
Short name T171
Test name
Test status
Simulation time 20409404 ps
CPU time 0.88 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 215892 kb
Host smart-9c10be7a-6fba-4b37-ad11-2d40a754d4aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812552635 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1812552635
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1619525926
Short name T605
Test name
Test status
Simulation time 84719029 ps
CPU time 1.11 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 216488 kb
Host smart-cf781eb6-038a-4409-a39d-58fcf91e3550
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619525926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1619525926
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3737990720
Short name T113
Test name
Test status
Simulation time 27598631 ps
CPU time 0.84 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:22 PM PDT 24
Peak memory 217988 kb
Host smart-bb03e76a-a1cb-4048-82a0-a2d4e70d10f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737990720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3737990720
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2912484843
Short name T521
Test name
Test status
Simulation time 104363961 ps
CPU time 1.18 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 216644 kb
Host smart-211a4846-ab60-415c-9faf-2ea8475b5b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912484843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2912484843
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3939186807
Short name T398
Test name
Test status
Simulation time 25716583 ps
CPU time 0.95 seconds
Started Mar 19 02:56:21 PM PDT 24
Finished Mar 19 02:56:22 PM PDT 24
Peak memory 215724 kb
Host smart-bedc6fb9-af0b-4951-8b11-479a84672646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939186807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3939186807
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3102569374
Short name T319
Test name
Test status
Simulation time 179881506 ps
CPU time 0.94 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 215404 kb
Host smart-840ddcd1-1184-4a97-9ef1-0d4f5d7f6edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102569374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3102569374
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3504571910
Short name T310
Test name
Test status
Simulation time 1876971458 ps
CPU time 4.49 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:27 PM PDT 24
Peak memory 215412 kb
Host smart-0b31e3bf-7d17-4c21-9e4c-72f515175c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504571910 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3504571910
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3859727617
Short name T208
Test name
Test status
Simulation time 74618463871 ps
CPU time 1967.28 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 03:29:11 PM PDT 24
Peak memory 227800 kb
Host smart-7c26d2d4-afb4-4d70-a98f-be583c03f610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859727617 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3859727617
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.262634410
Short name T767
Test name
Test status
Simulation time 38202531 ps
CPU time 1.37 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 216808 kb
Host smart-f3c9e82a-3b79-46f3-8a01-c941f007d0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262634410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.262634410
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2191471498
Short name T397
Test name
Test status
Simulation time 76056704 ps
CPU time 1.66 seconds
Started Mar 19 02:57:33 PM PDT 24
Finished Mar 19 02:57:35 PM PDT 24
Peak memory 217964 kb
Host smart-89c9eac2-2a02-4214-b03d-29faf3c8cfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191471498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2191471498
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2158994556
Short name T674
Test name
Test status
Simulation time 27926959 ps
CPU time 1.28 seconds
Started Mar 19 02:57:41 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 216924 kb
Host smart-5be60e10-32a2-45da-83bc-9940cae5e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158994556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2158994556
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.5511623
Short name T344
Test name
Test status
Simulation time 42582008 ps
CPU time 1.42 seconds
Started Mar 19 02:57:28 PM PDT 24
Finished Mar 19 02:57:30 PM PDT 24
Peak memory 217764 kb
Host smart-231587d2-7da4-4741-8aca-575a22ba942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5511623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.5511623
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2001258664
Short name T531
Test name
Test status
Simulation time 76383408 ps
CPU time 1.55 seconds
Started Mar 19 02:57:30 PM PDT 24
Finished Mar 19 02:57:32 PM PDT 24
Peak memory 218228 kb
Host smart-76b7c39a-2fd6-4992-ad8a-e9bf2971d0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001258664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2001258664
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.689210219
Short name T373
Test name
Test status
Simulation time 58324433 ps
CPU time 1.32 seconds
Started Mar 19 02:57:29 PM PDT 24
Finished Mar 19 02:57:30 PM PDT 24
Peak memory 218708 kb
Host smart-6711d4dc-c0d2-443f-811a-a9aaf1adcded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689210219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.689210219
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.789958003
Short name T648
Test name
Test status
Simulation time 93199148 ps
CPU time 1.39 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 218256 kb
Host smart-00212608-61bc-4652-a602-62447689e20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789958003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.789958003
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.974791704
Short name T821
Test name
Test status
Simulation time 103201715 ps
CPU time 1.88 seconds
Started Mar 19 02:57:49 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 219760 kb
Host smart-561d1196-ebf6-4a2f-8667-23b4065888c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974791704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.974791704
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2954415516
Short name T357
Test name
Test status
Simulation time 67137007 ps
CPU time 1.63 seconds
Started Mar 19 02:57:32 PM PDT 24
Finished Mar 19 02:57:33 PM PDT 24
Peak memory 218304 kb
Host smart-736577f9-311c-4bdd-b7bb-396c83436ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954415516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2954415516
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1580146654
Short name T808
Test name
Test status
Simulation time 50325894 ps
CPU time 1.37 seconds
Started Mar 19 02:57:31 PM PDT 24
Finished Mar 19 02:57:33 PM PDT 24
Peak memory 217668 kb
Host smart-8d7e08fe-a7d6-4166-a51d-8d9a73f20369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580146654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1580146654
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.945864845
Short name T469
Test name
Test status
Simulation time 190379766 ps
CPU time 0.93 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 207072 kb
Host smart-2e84d232-33fd-4d83-b415-93d35c536aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945864845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.945864845
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1485007929
Short name T625
Test name
Test status
Simulation time 48170633 ps
CPU time 1.13 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 216804 kb
Host smart-45ee5aa2-35d6-4f73-bf9f-b0b456152208
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485007929 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1485007929
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1996665508
Short name T107
Test name
Test status
Simulation time 24184722 ps
CPU time 1 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 218120 kb
Host smart-80551074-c805-46bf-be5d-3a89f97cf2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996665508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1996665508
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2181856224
Short name T467
Test name
Test status
Simulation time 114483490 ps
CPU time 1.24 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 216836 kb
Host smart-aa86bdd5-6674-4135-a1d6-576b13512c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181856224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2181856224
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.339299940
Short name T638
Test name
Test status
Simulation time 16871110 ps
CPU time 1.07 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 02:56:24 PM PDT 24
Peak memory 215420 kb
Host smart-d6a822d4-be24-4f19-9d82-fb50875436a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339299940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.339299940
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2853910919
Short name T387
Test name
Test status
Simulation time 314551542 ps
CPU time 3.36 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 216864 kb
Host smart-a6ab62a4-acef-49f4-9e24-78f5caca3fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853910919 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2853910919
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2890219654
Short name T842
Test name
Test status
Simulation time 66489744102 ps
CPU time 721.97 seconds
Started Mar 19 02:56:23 PM PDT 24
Finished Mar 19 03:08:25 PM PDT 24
Peak memory 220232 kb
Host smart-fa04cc10-041f-47bc-8964-9f63cc6ae0e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890219654 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2890219654
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1275682758
Short name T351
Test name
Test status
Simulation time 52941407 ps
CPU time 1.9 seconds
Started Mar 19 02:57:35 PM PDT 24
Finished Mar 19 02:57:37 PM PDT 24
Peak memory 216932 kb
Host smart-76965ea1-4ca6-49fa-b8f2-cabdd3268e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275682758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1275682758
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1646127096
Short name T312
Test name
Test status
Simulation time 77340822 ps
CPU time 1.2 seconds
Started Mar 19 02:57:43 PM PDT 24
Finished Mar 19 02:57:45 PM PDT 24
Peak memory 218192 kb
Host smart-090b069a-fea7-4f7e-bb6d-db1861ea67ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646127096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1646127096
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.761027590
Short name T577
Test name
Test status
Simulation time 51460130 ps
CPU time 1.41 seconds
Started Mar 19 02:57:30 PM PDT 24
Finished Mar 19 02:57:32 PM PDT 24
Peak memory 217840 kb
Host smart-ab727fac-9718-4837-ab22-b23bae15246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761027590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.761027590
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3445381617
Short name T490
Test name
Test status
Simulation time 101416373 ps
CPU time 1.76 seconds
Started Mar 19 02:57:50 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 217864 kb
Host smart-eee43086-8493-4994-9c4b-7b10725568b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445381617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3445381617
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3149614476
Short name T363
Test name
Test status
Simulation time 43992201 ps
CPU time 1.58 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 216972 kb
Host smart-369c5ba0-1f14-4f1d-a3f5-20cacdc8db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149614476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3149614476
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.912847349
Short name T559
Test name
Test status
Simulation time 39112416 ps
CPU time 1.36 seconds
Started Mar 19 02:57:36 PM PDT 24
Finished Mar 19 02:57:37 PM PDT 24
Peak memory 219492 kb
Host smart-0d7fb047-fd19-4adf-bf53-1739459f5ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912847349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.912847349
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.4267925983
Short name T496
Test name
Test status
Simulation time 229362754 ps
CPU time 1.49 seconds
Started Mar 19 02:57:52 PM PDT 24
Finished Mar 19 02:57:54 PM PDT 24
Peak memory 218028 kb
Host smart-d9742135-9ba9-4182-bea2-62508e35897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267925983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.4267925983
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3314782035
Short name T819
Test name
Test status
Simulation time 85241808 ps
CPU time 1.16 seconds
Started Mar 19 02:57:50 PM PDT 24
Finished Mar 19 02:57:51 PM PDT 24
Peak memory 217012 kb
Host smart-83a0fd0c-d6a1-4e1a-a33b-594ade13fb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314782035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3314782035
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4265121524
Short name T418
Test name
Test status
Simulation time 95027284 ps
CPU time 1.21 seconds
Started Mar 19 02:57:38 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 218224 kb
Host smart-b4db8a31-aca4-43f4-a615-de0c5df7ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265121524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4265121524
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4052985496
Short name T270
Test name
Test status
Simulation time 43938328 ps
CPU time 1.17 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215768 kb
Host smart-cb1805be-e6e7-421f-8040-1c69f8401218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052985496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4052985496
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3527891068
Short name T712
Test name
Test status
Simulation time 15368783 ps
CPU time 0.91 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 206124 kb
Host smart-5821a986-fc4c-491c-a592-9546e002827b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527891068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3527891068
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2744369621
Short name T47
Test name
Test status
Simulation time 21598376 ps
CPU time 0.88 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 215608 kb
Host smart-1e544e97-06a9-4dd2-b491-8f387af7eb6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744369621 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2744369621
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3185609478
Short name T662
Test name
Test status
Simulation time 190057366 ps
CPU time 1.17 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 216644 kb
Host smart-1ef2e1cb-d717-45ed-95b8-7a3179918e0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185609478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3185609478
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.4126042856
Short name T739
Test name
Test status
Simulation time 24927932 ps
CPU time 0.93 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:32 PM PDT 24
Peak memory 218048 kb
Host smart-42c25e9b-fed1-4f1e-9151-0d6753d8f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126042856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4126042856
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2620387355
Short name T332
Test name
Test status
Simulation time 59003495 ps
CPU time 1.19 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 02:56:25 PM PDT 24
Peak memory 216992 kb
Host smart-dd9eebac-da73-4e07-b963-93c468b13b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620387355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2620387355
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3068485151
Short name T734
Test name
Test status
Simulation time 21319619 ps
CPU time 1 seconds
Started Mar 19 02:56:26 PM PDT 24
Finished Mar 19 02:56:27 PM PDT 24
Peak memory 215848 kb
Host smart-7f60e936-0625-4173-b474-d027307c2f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068485151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3068485151
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2445845976
Short name T686
Test name
Test status
Simulation time 43441377 ps
CPU time 0.93 seconds
Started Mar 19 02:56:22 PM PDT 24
Finished Mar 19 02:56:23 PM PDT 24
Peak memory 215416 kb
Host smart-7f312ac6-ee36-4f19-a495-7f40d1972aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445845976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2445845976
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3703037563
Short name T378
Test name
Test status
Simulation time 453107267 ps
CPU time 4.89 seconds
Started Mar 19 02:56:21 PM PDT 24
Finished Mar 19 02:56:26 PM PDT 24
Peak memory 215404 kb
Host smart-1adb9adf-8c63-4492-a7f6-f6a0b6bb50f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703037563 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3703037563
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3281247701
Short name T207
Test name
Test status
Simulation time 39497940235 ps
CPU time 983.9 seconds
Started Mar 19 02:56:24 PM PDT 24
Finished Mar 19 03:12:48 PM PDT 24
Peak memory 217824 kb
Host smart-e46eb071-e0be-4bde-b828-e2ef0e403a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281247701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3281247701
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3590131419
Short name T524
Test name
Test status
Simulation time 131294821 ps
CPU time 1.64 seconds
Started Mar 19 02:57:35 PM PDT 24
Finished Mar 19 02:57:37 PM PDT 24
Peak memory 218264 kb
Host smart-88044147-b150-4b5b-a137-ad6273da0d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590131419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3590131419
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.791854746
Short name T427
Test name
Test status
Simulation time 95284032 ps
CPU time 1.13 seconds
Started Mar 19 02:57:35 PM PDT 24
Finished Mar 19 02:57:36 PM PDT 24
Peak memory 216856 kb
Host smart-5fb60104-92df-49fd-bbf2-56b811792629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791854746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.791854746
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.665651188
Short name T315
Test name
Test status
Simulation time 227558668 ps
CPU time 1.43 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 217060 kb
Host smart-874c8fc9-fe03-4467-9af7-e91cfbf714fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665651188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.665651188
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1226911753
Short name T795
Test name
Test status
Simulation time 70897589 ps
CPU time 1.32 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 218124 kb
Host smart-ddfb46a4-1f71-411d-91c8-c2fcab74972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226911753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1226911753
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2056201092
Short name T36
Test name
Test status
Simulation time 50933564 ps
CPU time 1.46 seconds
Started Mar 19 02:57:38 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 217848 kb
Host smart-79051c69-e9b3-4c67-a4cf-79094b93a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056201092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2056201092
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.22464667
Short name T595
Test name
Test status
Simulation time 44777971 ps
CPU time 1.71 seconds
Started Mar 19 02:57:32 PM PDT 24
Finished Mar 19 02:57:34 PM PDT 24
Peak memory 217924 kb
Host smart-318e2854-7a7f-4154-ba87-f54b7c1e7dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22464667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.22464667
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2470112046
Short name T311
Test name
Test status
Simulation time 223891551 ps
CPU time 1.16 seconds
Started Mar 19 02:57:37 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 216772 kb
Host smart-f2f6c2ab-8056-4be2-826b-838ddf943fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470112046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2470112046
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1585648995
Short name T399
Test name
Test status
Simulation time 469946236 ps
CPU time 3.72 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:51 PM PDT 24
Peak memory 215492 kb
Host smart-836a33c7-9af3-489d-a78d-e5b6e8b54eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585648995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1585648995
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.20353111
Short name T732
Test name
Test status
Simulation time 76284296 ps
CPU time 1.13 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:46 PM PDT 24
Peak memory 216684 kb
Host smart-8a2424e9-aaff-4f4d-87ed-1d9b50e32413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20353111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.20353111
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2924598492
Short name T840
Test name
Test status
Simulation time 37271452 ps
CPU time 1.47 seconds
Started Mar 19 02:57:31 PM PDT 24
Finished Mar 19 02:57:32 PM PDT 24
Peak memory 216952 kb
Host smart-a2361261-8c9b-4304-b67e-924d31a80080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924598492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2924598492
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3974435346
Short name T720
Test name
Test status
Simulation time 25128111 ps
CPU time 1.22 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 215804 kb
Host smart-f6ecf1ef-341e-4582-b20c-75725913dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974435346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3974435346
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4191361796
Short name T322
Test name
Test status
Simulation time 28458259 ps
CPU time 0.85 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 205804 kb
Host smart-831a70d7-8dc4-4d2c-8a31-726281c31112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191361796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4191361796
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1624013062
Short name T124
Test name
Test status
Simulation time 16679010 ps
CPU time 0.84 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:32 PM PDT 24
Peak memory 215996 kb
Host smart-20ec19ce-7683-438c-8e60-209fa8ceada5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624013062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1624013062
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2354790104
Short name T102
Test name
Test status
Simulation time 101604207 ps
CPU time 1.15 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 216636 kb
Host smart-fac0adeb-e0f7-49e8-a8cf-07dc2104a8fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354790104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2354790104
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1697056382
Short name T366
Test name
Test status
Simulation time 49046321 ps
CPU time 0.99 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 216996 kb
Host smart-bf132cee-4f5f-4a86-8667-d006e9b901eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697056382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1697056382
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2505620769
Short name T354
Test name
Test status
Simulation time 164405224 ps
CPU time 1.75 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:35 PM PDT 24
Peak memory 219532 kb
Host smart-7f7d24fc-500d-46da-a4bf-ebb6d5a706fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505620769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2505620769
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4008696879
Short name T68
Test name
Test status
Simulation time 20829655 ps
CPU time 1.1 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215600 kb
Host smart-0ef022e0-fcdd-4f24-b9ef-71037bce323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008696879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4008696879
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3778971953
Short name T482
Test name
Test status
Simulation time 18782331 ps
CPU time 0.98 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:32 PM PDT 24
Peak memory 207232 kb
Host smart-5b27d0f1-5431-4855-a860-7aa51fb569f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778971953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3778971953
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3488555757
Short name T697
Test name
Test status
Simulation time 119544894 ps
CPU time 1.72 seconds
Started Mar 19 02:56:29 PM PDT 24
Finished Mar 19 02:56:31 PM PDT 24
Peak memory 215440 kb
Host smart-fd0052a5-34c8-4f71-a716-dae5f843f2ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488555757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3488555757
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4200051245
Short name T213
Test name
Test status
Simulation time 41592229778 ps
CPU time 924.63 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 03:11:58 PM PDT 24
Peak memory 223872 kb
Host smart-9e614904-9fdd-4edc-b20d-97e2d9713690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200051245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4200051245
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/241.edn_genbits.1465460250
Short name T276
Test name
Test status
Simulation time 63650478 ps
CPU time 1.26 seconds
Started Mar 19 02:58:02 PM PDT 24
Finished Mar 19 02:58:03 PM PDT 24
Peak memory 216624 kb
Host smart-caa2215b-765a-4b57-b4c0-c0321c7e4944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465460250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1465460250
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1059715562
Short name T738
Test name
Test status
Simulation time 171517680 ps
CPU time 1.48 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 219488 kb
Host smart-85bacac2-fecc-4ea0-9b38-3afecc59906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059715562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1059715562
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3969515905
Short name T643
Test name
Test status
Simulation time 64976667 ps
CPU time 2.22 seconds
Started Mar 19 02:57:35 PM PDT 24
Finished Mar 19 02:57:37 PM PDT 24
Peak memory 218160 kb
Host smart-8723d59c-ef4d-456a-9c43-8b513398abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969515905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3969515905
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1639668836
Short name T658
Test name
Test status
Simulation time 43615863 ps
CPU time 1.62 seconds
Started Mar 19 02:57:31 PM PDT 24
Finished Mar 19 02:57:32 PM PDT 24
Peak memory 216708 kb
Host smart-e5bd9f31-2597-452a-a8d9-e0c262c0b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639668836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1639668836
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3471464114
Short name T305
Test name
Test status
Simulation time 117379411 ps
CPU time 1.87 seconds
Started Mar 19 02:57:41 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 218200 kb
Host smart-f828d6bc-f8a8-434e-b348-4fb218b6bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471464114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3471464114
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.336896970
Short name T546
Test name
Test status
Simulation time 76925353 ps
CPU time 1.32 seconds
Started Mar 19 02:57:38 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 218244 kb
Host smart-85cad543-2e16-4011-87bd-b1c0831219df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336896970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.336896970
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.798601013
Short name T603
Test name
Test status
Simulation time 166983350 ps
CPU time 3.35 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 218788 kb
Host smart-53743e12-fb99-4219-b149-9073a1f1499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798601013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.798601013
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2591729702
Short name T291
Test name
Test status
Simulation time 64002251 ps
CPU time 1.54 seconds
Started Mar 19 02:57:37 PM PDT 24
Finished Mar 19 02:57:39 PM PDT 24
Peak memory 218136 kb
Host smart-b0c96a19-1929-4ba7-acfe-4517ce75a19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591729702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2591729702
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3112396112
Short name T525
Test name
Test status
Simulation time 32995844 ps
CPU time 1.32 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215800 kb
Host smart-c955ee4d-ee84-48e0-b039-ce8f7758f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112396112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3112396112
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3638205691
Short name T325
Test name
Test status
Simulation time 28199812 ps
CPU time 0.93 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:32 PM PDT 24
Peak memory 206160 kb
Host smart-ff728270-5188-43eb-a3d1-707c81217d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638205691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3638205691
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.4005348474
Short name T28
Test name
Test status
Simulation time 29835747 ps
CPU time 0.81 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 216040 kb
Host smart-7df47fce-567c-48fd-80f1-385fa92532d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005348474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4005348474
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3107814015
Short name T406
Test name
Test status
Simulation time 18673897 ps
CPU time 0.98 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 217716 kb
Host smart-eafafff1-78a7-430b-9214-bd82d0f9d0fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107814015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3107814015
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3938633442
Short name T15
Test name
Test status
Simulation time 70378274 ps
CPU time 1.28 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 224212 kb
Host smart-eb96752f-f60d-4c31-a527-ce83152799a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938633442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3938633442
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1700815903
Short name T705
Test name
Test status
Simulation time 41259260 ps
CPU time 1.1 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 216636 kb
Host smart-ea6021b3-ccd1-498d-82d8-ce72cfda6be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700815903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1700815903
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2506064355
Short name T392
Test name
Test status
Simulation time 39481022 ps
CPU time 0.84 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 215384 kb
Host smart-79d51f80-6b9b-4109-bcd2-ce9677e72e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506064355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2506064355
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2681229996
Short name T839
Test name
Test status
Simulation time 28350498 ps
CPU time 1.02 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215428 kb
Host smart-ea6f9aae-07b5-486d-8fa9-fb240700fce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681229996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2681229996
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.398677095
Short name T222
Test name
Test status
Simulation time 254375446 ps
CPU time 3 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 217900 kb
Host smart-9ca6842c-3b2d-4ce3-9eae-743a05980cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398677095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.398677095
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.40117013
Short name T818
Test name
Test status
Simulation time 111319196255 ps
CPU time 2590.03 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 03:39:46 PM PDT 24
Peak memory 227960 kb
Host smart-15fed9cc-3fcc-4860-bdb8-19e611a281cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40117013 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.40117013
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2657804466
Short name T338
Test name
Test status
Simulation time 54924049 ps
CPU time 1.61 seconds
Started Mar 19 02:57:54 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 217844 kb
Host smart-718588ca-769c-4941-8004-6435affcd46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657804466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2657804466
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2877179560
Short name T151
Test name
Test status
Simulation time 49765427 ps
CPU time 1.21 seconds
Started Mar 19 02:57:50 PM PDT 24
Finished Mar 19 02:57:51 PM PDT 24
Peak memory 216896 kb
Host smart-a8ec3b53-e5c8-4817-8eae-a3e23f6ad66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877179560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2877179560
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3411500559
Short name T801
Test name
Test status
Simulation time 52271753 ps
CPU time 1.03 seconds
Started Mar 19 02:57:52 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 217024 kb
Host smart-74ed8882-bdaa-45a8-9ea2-98a505acbcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411500559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3411500559
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1889793986
Short name T716
Test name
Test status
Simulation time 45001846 ps
CPU time 1.01 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216620 kb
Host smart-875c4245-cf75-498a-ac3b-9ca41faa415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889793986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1889793986
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1778248738
Short name T753
Test name
Test status
Simulation time 73129221 ps
CPU time 1.34 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 215432 kb
Host smart-59c39b4c-0ccc-4d80-837c-9962b8d22264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778248738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1778248738
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.999925452
Short name T706
Test name
Test status
Simulation time 49090795 ps
CPU time 1.17 seconds
Started Mar 19 02:57:43 PM PDT 24
Finished Mar 19 02:57:45 PM PDT 24
Peak memory 217756 kb
Host smart-e73e9313-994e-4007-9fcd-8988c5029f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999925452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.999925452
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3060788577
Short name T828
Test name
Test status
Simulation time 76857939 ps
CPU time 1.15 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216664 kb
Host smart-16e69be0-3a38-440c-b76c-643ef28cfd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060788577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3060788577
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.579588437
Short name T657
Test name
Test status
Simulation time 61262624 ps
CPU time 1.2 seconds
Started Mar 19 02:57:50 PM PDT 24
Finished Mar 19 02:57:51 PM PDT 24
Peak memory 216636 kb
Host smart-39f0ad0c-2b14-433e-82ed-a1824419b072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579588437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.579588437
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.815498355
Short name T339
Test name
Test status
Simulation time 68182377 ps
CPU time 1.01 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 215432 kb
Host smart-bf496827-0d69-4df6-9d32-d0bfd726e99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815498355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.815498355
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.595629908
Short name T517
Test name
Test status
Simulation time 42906926 ps
CPU time 1.32 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 216704 kb
Host smart-6f47cefd-ebf1-4c7d-9ab3-e59aa1c6e92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595629908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.595629908
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3632562641
Short name T114
Test name
Test status
Simulation time 95283290 ps
CPU time 1.17 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 215792 kb
Host smart-f93cf400-35f8-43a6-bfa9-c342fd9160fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632562641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3632562641
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3566177577
Short name T345
Test name
Test status
Simulation time 16169023 ps
CPU time 0.94 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:32 PM PDT 24
Peak memory 206688 kb
Host smart-575099da-763e-4e32-b67a-832de6d0be89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566177577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3566177577
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4134277069
Short name T646
Test name
Test status
Simulation time 21416810 ps
CPU time 0.87 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215996 kb
Host smart-8dfb7974-a4d7-452f-850f-58ead78dbe2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134277069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4134277069
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2772277925
Short name T841
Test name
Test status
Simulation time 38040653 ps
CPU time 1.09 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 218136 kb
Host smart-402a53c5-4a09-4191-931a-7be3f179390e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772277925 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2772277925
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.720513790
Short name T104
Test name
Test status
Simulation time 23574091 ps
CPU time 1.09 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 231332 kb
Host smart-adf4442a-963c-4039-bba0-ff2449d92bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720513790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.720513790
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.504972847
Short name T350
Test name
Test status
Simulation time 77366766 ps
CPU time 1.11 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 216808 kb
Host smart-0c4e5512-5b2d-4ad6-beed-af5766a6b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504972847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.504972847
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3450420870
Short name T693
Test name
Test status
Simulation time 21650243 ps
CPU time 1.06 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 215708 kb
Host smart-5e3c75f8-bd98-4761-943d-776f0aab97a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450420870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3450420870
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2381546452
Short name T429
Test name
Test status
Simulation time 44106584 ps
CPU time 0.88 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215420 kb
Host smart-0cc27a6b-2401-45c6-bb40-05414d8a14c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381546452 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2381546452
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1912711188
Short name T565
Test name
Test status
Simulation time 22577664 ps
CPU time 1.03 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 206096 kb
Host smart-9f3f8f4f-a53b-4ea3-83de-80afc1ffef11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912711188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1912711188
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1665237384
Short name T415
Test name
Test status
Simulation time 88739834086 ps
CPU time 428.09 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 03:03:42 PM PDT 24
Peak memory 219640 kb
Host smart-dbc44bfa-2974-42c3-b019-807a56d637c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665237384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1665237384
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3918935446
Short name T450
Test name
Test status
Simulation time 63609759 ps
CPU time 2.42 seconds
Started Mar 19 02:57:52 PM PDT 24
Finished Mar 19 02:57:54 PM PDT 24
Peak memory 218032 kb
Host smart-4cf26eca-23e9-4a72-9722-c2d2a8213310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918935446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3918935446
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3533442085
Short name T380
Test name
Test status
Simulation time 56488085 ps
CPU time 1.36 seconds
Started Mar 19 02:57:46 PM PDT 24
Finished Mar 19 02:57:48 PM PDT 24
Peak memory 218068 kb
Host smart-f7435933-9d68-49db-ac75-4a421c4c59de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533442085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3533442085
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3064306331
Short name T9
Test name
Test status
Simulation time 32707237 ps
CPU time 1.32 seconds
Started Mar 19 02:57:41 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 218952 kb
Host smart-48fde67d-29a7-4bde-8ba5-675dd775ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064306331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3064306331
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3762010690
Short name T426
Test name
Test status
Simulation time 129545569 ps
CPU time 1.18 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 218088 kb
Host smart-a5529dcf-e8ec-490e-a236-aff6629d4aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762010690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3762010690
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.434237177
Short name T543
Test name
Test status
Simulation time 46225971 ps
CPU time 1.46 seconds
Started Mar 19 02:57:48 PM PDT 24
Finished Mar 19 02:57:50 PM PDT 24
Peak memory 217928 kb
Host smart-d29b7397-7588-447f-81dd-e30a8ea94f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434237177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.434237177
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2393058261
Short name T52
Test name
Test status
Simulation time 28258671 ps
CPU time 1.25 seconds
Started Mar 19 02:57:55 PM PDT 24
Finished Mar 19 02:57:56 PM PDT 24
Peak memory 218032 kb
Host smart-c7b3f736-b040-44bd-ba6a-1ac97b2c6f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393058261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2393058261
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1667243137
Short name T439
Test name
Test status
Simulation time 66947673 ps
CPU time 0.97 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216944 kb
Host smart-2d2da862-8a68-4315-9090-1ae9d39e60a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667243137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1667243137
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4214663599
Short name T476
Test name
Test status
Simulation time 50222979 ps
CPU time 1.23 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216904 kb
Host smart-b2a20429-7dcf-431b-a04e-b1675368b14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214663599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4214663599
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1581495982
Short name T748
Test name
Test status
Simulation time 94905362 ps
CPU time 1.26 seconds
Started Mar 19 02:57:49 PM PDT 24
Finished Mar 19 02:57:50 PM PDT 24
Peak memory 217120 kb
Host smart-176b157a-763d-476f-b703-fd21173f83f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581495982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1581495982
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2788332761
Short name T306
Test name
Test status
Simulation time 65736411 ps
CPU time 1.43 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 217868 kb
Host smart-08749052-1d0d-43e8-acf1-25b937b10f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788332761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2788332761
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1042007023
Short name T164
Test name
Test status
Simulation time 101405240 ps
CPU time 1.37 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215780 kb
Host smart-df937512-8856-4f90-8c1e-e82c1322abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042007023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1042007023
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4064886613
Short name T791
Test name
Test status
Simulation time 26286778 ps
CPU time 0.92 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 206984 kb
Host smart-1db6d323-df90-4ff6-b300-fb8e01dabaec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064886613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4064886613
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.311796618
Short name T624
Test name
Test status
Simulation time 34120186 ps
CPU time 0.9 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215624 kb
Host smart-16e0d1c9-4e6a-4d96-aa7c-e265fd112c3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311796618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.311796618
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1855306721
Short name T487
Test name
Test status
Simulation time 80314302 ps
CPU time 1.08 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 217804 kb
Host smart-c812aa8c-0536-4864-afb1-bec18503d2eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855306721 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1855306721
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.349453210
Short name T783
Test name
Test status
Simulation time 17980235 ps
CPU time 1.05 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 218256 kb
Host smart-51f078c6-c412-455f-a245-0e6b6adecccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349453210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.349453210
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1576487273
Short name T601
Test name
Test status
Simulation time 119175142 ps
CPU time 1.4 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:35 PM PDT 24
Peak memory 218312 kb
Host smart-89f2cade-ea55-4d92-b8c6-5ac1ee727d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576487273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1576487273
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2249082007
Short name T756
Test name
Test status
Simulation time 32714887 ps
CPU time 0.98 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 224108 kb
Host smart-690c175f-cec3-429d-ac9d-5e826d434546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249082007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2249082007
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3478169193
Short name T609
Test name
Test status
Simulation time 27761325 ps
CPU time 0.98 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 215428 kb
Host smart-dbaed9d5-56ad-4259-ae87-8674cf81ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478169193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3478169193
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2749792056
Short name T435
Test name
Test status
Simulation time 45764301 ps
CPU time 1.34 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 216824 kb
Host smart-d18b7065-3493-4f49-a4f0-102d025fcd6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749792056 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2749792056
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1774257814
Short name T779
Test name
Test status
Simulation time 139425343815 ps
CPU time 451.62 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 03:04:05 PM PDT 24
Peak memory 219000 kb
Host smart-5091824b-5375-4050-9886-8dfdea63fc84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774257814 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1774257814
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2021879637
Short name T279
Test name
Test status
Simulation time 57740832 ps
CPU time 1.43 seconds
Started Mar 19 02:57:57 PM PDT 24
Finished Mar 19 02:57:58 PM PDT 24
Peak memory 218120 kb
Host smart-f2ae014c-e17f-437b-b7fc-bfb87ad08edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021879637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2021879637
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1517436874
Short name T480
Test name
Test status
Simulation time 50428988 ps
CPU time 1.15 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 216912 kb
Host smart-88b0109f-8789-4aef-9cc6-7c67f97ede4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517436874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1517436874
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1407572812
Short name T673
Test name
Test status
Simulation time 116624089 ps
CPU time 1.62 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:53 PM PDT 24
Peak memory 218020 kb
Host smart-c35dc207-ea85-4a3d-aa73-3f4099ff11b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407572812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1407572812
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3551688222
Short name T34
Test name
Test status
Simulation time 58506461 ps
CPU time 1.56 seconds
Started Mar 19 02:57:42 PM PDT 24
Finished Mar 19 02:57:44 PM PDT 24
Peak memory 217980 kb
Host smart-dafab6ef-7ea7-45e8-841d-f859a934c6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551688222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3551688222
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1142938277
Short name T341
Test name
Test status
Simulation time 53912185 ps
CPU time 1.67 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 217824 kb
Host smart-8c695a13-58e4-4dc5-906c-59e50c2eb046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142938277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1142938277
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3897752537
Short name T326
Test name
Test status
Simulation time 31422857 ps
CPU time 1.22 seconds
Started Mar 19 02:57:51 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 219144 kb
Host smart-cf0be5d2-d551-4483-b197-043f35c3e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897752537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3897752537
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.812379830
Short name T492
Test name
Test status
Simulation time 79613123 ps
CPU time 1.55 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 217908 kb
Host smart-f55622db-7fff-482d-86f1-450db052c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812379830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.812379830
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1177523845
Short name T747
Test name
Test status
Simulation time 57896996 ps
CPU time 2 seconds
Started Mar 19 02:57:53 PM PDT 24
Finished Mar 19 02:57:55 PM PDT 24
Peak memory 217968 kb
Host smart-30a2ec40-1486-405d-b121-735cc217f1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177523845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1177523845
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3489000523
Short name T413
Test name
Test status
Simulation time 48805777 ps
CPU time 0.93 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216724 kb
Host smart-5181cd9d-5d04-4534-af0f-5c55ea5206bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489000523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3489000523
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2618576559
Short name T813
Test name
Test status
Simulation time 23579184 ps
CPU time 1.11 seconds
Started Mar 19 02:57:41 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 217004 kb
Host smart-fbeafc8c-b176-4ddc-8232-dc8469feed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618576559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2618576559
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1138226120
Short name T195
Test name
Test status
Simulation time 93016664 ps
CPU time 1.19 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215800 kb
Host smart-a5f0b17f-2796-4370-8dff-1e633beb6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138226120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1138226120
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1092095392
Short name T798
Test name
Test status
Simulation time 15620675 ps
CPU time 0.91 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 206024 kb
Host smart-3b1b3c8f-1e0f-4989-bcb0-3061b8089b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092095392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1092095392
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2331911468
Short name T194
Test name
Test status
Simulation time 10419642 ps
CPU time 0.89 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215564 kb
Host smart-5cb09778-29e2-4804-90a9-11cb2003b2c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331911468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2331911468
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3123632930
Short name T100
Test name
Test status
Simulation time 24886405 ps
CPU time 1.25 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 216848 kb
Host smart-a2d7e765-7f57-4c40-a85f-ff92afd33544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123632930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3123632930
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2885138769
Short name T395
Test name
Test status
Simulation time 32443594 ps
CPU time 1.38 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 217944 kb
Host smart-383e1425-09a9-4080-aa22-92e52b4c53f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885138769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2885138769
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3707916685
Short name T676
Test name
Test status
Simulation time 20243862 ps
CPU time 1.07 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215840 kb
Host smart-ce192a1b-0887-49b6-8f49-ce5207f4fe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707916685 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3707916685
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2300800011
Short name T3
Test name
Test status
Simulation time 38998051 ps
CPU time 0.9 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215420 kb
Host smart-0b290d2b-6167-43cf-95b5-d16c1434613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300800011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2300800011
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1704543653
Short name T404
Test name
Test status
Simulation time 403195945 ps
CPU time 4.44 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:48 PM PDT 24
Peak memory 216540 kb
Host smart-7921c08c-77e1-4fdc-b75e-7551f2957ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704543653 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1704543653
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1034737985
Short name T817
Test name
Test status
Simulation time 128461228638 ps
CPU time 875.89 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 03:11:11 PM PDT 24
Peak memory 221280 kb
Host smart-6535a8fa-9d7f-4322-842f-8c7c56b1da43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034737985 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1034737985
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3408581409
Short name T355
Test name
Test status
Simulation time 80365317 ps
CPU time 1.87 seconds
Started Mar 19 02:57:36 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 217980 kb
Host smart-daba3df5-8496-4401-9466-77df7041a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408581409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3408581409
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4072880748
Short name T428
Test name
Test status
Simulation time 38564567 ps
CPU time 1.17 seconds
Started Mar 19 02:57:36 PM PDT 24
Finished Mar 19 02:57:37 PM PDT 24
Peak memory 216664 kb
Host smart-b19c0da7-1cb5-4d8b-bd30-0c63d0e7d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072880748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4072880748
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3294070625
Short name T558
Test name
Test status
Simulation time 87247993 ps
CPU time 1.16 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 217660 kb
Host smart-3351af43-71d3-4472-8814-202b18f42bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294070625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3294070625
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.797612637
Short name T593
Test name
Test status
Simulation time 33319815 ps
CPU time 1.26 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216904 kb
Host smart-a20cf453-d319-45a0-ac85-7929a4ea49ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797612637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.797612637
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3016636889
Short name T724
Test name
Test status
Simulation time 41733224 ps
CPU time 1.12 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 218148 kb
Host smart-e6cce655-0e8c-444b-8178-941d4103569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016636889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3016636889
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3532196172
Short name T774
Test name
Test status
Simulation time 95991165 ps
CPU time 1.66 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 217860 kb
Host smart-a4fa5e46-8c76-45a9-8694-073e0e87a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532196172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3532196172
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3490198098
Short name T584
Test name
Test status
Simulation time 48804409 ps
CPU time 1.27 seconds
Started Mar 19 02:57:46 PM PDT 24
Finished Mar 19 02:57:47 PM PDT 24
Peak memory 216924 kb
Host smart-8b0f571b-a649-4f06-a5fc-1c6319d229a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490198098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3490198098
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2592298313
Short name T494
Test name
Test status
Simulation time 75621685 ps
CPU time 1.39 seconds
Started Mar 19 02:57:42 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 218112 kb
Host smart-3d28f9e3-3d62-4680-929d-2824ede4b1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592298313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2592298313
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.976341523
Short name T347
Test name
Test status
Simulation time 29599969 ps
CPU time 1.24 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 218060 kb
Host smart-c3f46eb2-f62a-47be-b410-987a39a85cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976341523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.976341523
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2983696792
Short name T793
Test name
Test status
Simulation time 30344285 ps
CPU time 1.29 seconds
Started Mar 19 02:57:50 PM PDT 24
Finished Mar 19 02:57:52 PM PDT 24
Peak memory 217884 kb
Host smart-4a0b038c-d1a8-435f-8fbc-e7ffb2ac5225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983696792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2983696792
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3099586453
Short name T489
Test name
Test status
Simulation time 11726484 ps
CPU time 0.86 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 205936 kb
Host smart-7cdbd416-0bea-4a38-9987-a440886c0e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099586453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3099586453
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1543620216
Short name T478
Test name
Test status
Simulation time 11369111 ps
CPU time 0.89 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:35 PM PDT 24
Peak memory 215664 kb
Host smart-ed2820a4-adb6-439e-9653-0c0023c66b3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543620216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1543620216
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.258218333
Short name T110
Test name
Test status
Simulation time 32509987 ps
CPU time 0.92 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215316 kb
Host smart-8d5dc7cd-0f9c-49c9-bdc8-fbb7f0842779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258218333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.258218333
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.2849867069
Short name T727
Test name
Test status
Simulation time 21873019 ps
CPU time 1.15 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:32 PM PDT 24
Peak memory 215780 kb
Host smart-127315a9-69db-4790-9c01-b055e5206dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849867069 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2849867069
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4291213225
Short name T436
Test name
Test status
Simulation time 45555164 ps
CPU time 0.9 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 215436 kb
Host smart-3def98ad-730c-4a97-b04c-2e912de370ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291213225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4291213225
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2782697843
Short name T49
Test name
Test status
Simulation time 252664239 ps
CPU time 5.04 seconds
Started Mar 19 02:56:41 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 216588 kb
Host smart-e1dec5be-e1e4-42ef-86fd-ca950077c69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782697843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2782697843
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2835010522
Short name T540
Test name
Test status
Simulation time 310749735798 ps
CPU time 1904.5 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 03:28:24 PM PDT 24
Peak memory 229004 kb
Host smart-0b1a0ae5-2fc9-4bed-aa57-8d24e1353389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835010522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2835010522
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1169058275
Short name T653
Test name
Test status
Simulation time 131322157 ps
CPU time 2.41 seconds
Started Mar 19 02:57:41 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 218116 kb
Host smart-658c1137-a057-4a3a-bc66-5bb37af8b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169058275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1169058275
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3703042188
Short name T218
Test name
Test status
Simulation time 82487310 ps
CPU time 1.03 seconds
Started Mar 19 02:57:42 PM PDT 24
Finished Mar 19 02:57:43 PM PDT 24
Peak memory 215392 kb
Host smart-de9596a7-4460-4353-89bf-9059d70756e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703042188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3703042188
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1352652409
Short name T613
Test name
Test status
Simulation time 31068620 ps
CPU time 1.28 seconds
Started Mar 19 02:57:37 PM PDT 24
Finished Mar 19 02:57:38 PM PDT 24
Peak memory 217112 kb
Host smart-6c3a9a88-f9ef-4db7-a714-99a13fd90d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352652409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1352652409
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3873156217
Short name T665
Test name
Test status
Simulation time 40371839 ps
CPU time 1.47 seconds
Started Mar 19 02:58:13 PM PDT 24
Finished Mar 19 02:58:14 PM PDT 24
Peak memory 217868 kb
Host smart-18d85fef-c33c-41f6-842a-eec641ca5509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873156217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3873156217
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.448190432
Short name T294
Test name
Test status
Simulation time 68197509 ps
CPU time 1.04 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 216756 kb
Host smart-d1bbc5ba-a96b-4d74-8164-18d54b32eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448190432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.448190432
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.902753137
Short name T519
Test name
Test status
Simulation time 38288872 ps
CPU time 1.5 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:41 PM PDT 24
Peak memory 215420 kb
Host smart-c29f6e82-604b-4678-a244-a03eef105c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902753137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.902753137
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1150656934
Short name T614
Test name
Test status
Simulation time 60103352 ps
CPU time 1.61 seconds
Started Mar 19 02:57:45 PM PDT 24
Finished Mar 19 02:57:47 PM PDT 24
Peak memory 217936 kb
Host smart-ea0da7f0-64e6-45fc-a4e7-319a2860d6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150656934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1150656934
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1161365468
Short name T660
Test name
Test status
Simulation time 25255317 ps
CPU time 1.14 seconds
Started Mar 19 02:57:47 PM PDT 24
Finished Mar 19 02:57:48 PM PDT 24
Peak memory 216812 kb
Host smart-432325f6-5542-4ad6-a189-32b6a31ff122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161365468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1161365468
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.402487306
Short name T26
Test name
Test status
Simulation time 112202257 ps
CPU time 1.35 seconds
Started Mar 19 02:58:03 PM PDT 24
Finished Mar 19 02:58:05 PM PDT 24
Peak memory 219084 kb
Host smart-40347b1c-2b40-40cd-bcd5-9c8c7eee5223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402487306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.402487306
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1757865247
Short name T158
Test name
Test status
Simulation time 95584433 ps
CPU time 1.2 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 215792 kb
Host smart-3fe4337a-d52e-4e7d-8661-6ad254f5447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757865247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1757865247
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3487771507
Short name T768
Test name
Test status
Simulation time 34712521 ps
CPU time 0.8 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 205772 kb
Host smart-a6be1a8d-5704-435f-b095-53c0d53ff6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487771507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3487771507
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1667168199
Short name T566
Test name
Test status
Simulation time 93747235 ps
CPU time 1.15 seconds
Started Mar 19 02:55:51 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 218928 kb
Host smart-5b850e64-9e1d-4437-9002-8d348d6996ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667168199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1667168199
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3652899331
Short name T191
Test name
Test status
Simulation time 30274220 ps
CPU time 0.83 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 217960 kb
Host smart-3aabfb3f-e5a3-4660-8c9c-a3964ff420b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652899331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3652899331
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_intr.467329512
Short name T133
Test name
Test status
Simulation time 22147389 ps
CPU time 1.07 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215888 kb
Host smart-bf13b49d-40e7-4f1d-ac87-cc99876fca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467329512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.467329512
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3764857566
Short name T731
Test name
Test status
Simulation time 29793457 ps
CPU time 1 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 207212 kb
Host smart-920c5941-f8ff-46b7-a1b8-d9673f0401b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764857566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3764857566
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3861846727
Short name T152
Test name
Test status
Simulation time 37075660 ps
CPU time 0.88 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215372 kb
Host smart-c796928f-731d-4048-8bb0-667249951624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861846727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3861846727
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1329581607
Short name T50
Test name
Test status
Simulation time 88197434 ps
CPU time 2.22 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 216856 kb
Host smart-522839ec-0b6d-4f29-8ecc-09eeceab30b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329581607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1329581607
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.1786392894
Short name T612
Test name
Test status
Simulation time 113053157 ps
CPU time 1.26 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 215792 kb
Host smart-15d3b172-0abf-4f0d-9639-3f378fff3d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786392894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1786392894
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1644654034
Short name T606
Test name
Test status
Simulation time 122268733 ps
CPU time 0.93 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 206732 kb
Host smart-c091e17b-6d0c-4297-8359-babb7bb2e4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644654034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1644654034
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3128836226
Short name T203
Test name
Test status
Simulation time 37597175 ps
CPU time 0.87 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215576 kb
Host smart-cf07bc20-bbb2-4415-9c78-d4a309e710d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128836226 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3128836226
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2345327830
Short name T800
Test name
Test status
Simulation time 38143279 ps
CPU time 1.31 seconds
Started Mar 19 02:56:40 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 216652 kb
Host smart-9b6ce1b4-9f82-4681-8f2e-aa0c0e2b7bb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345327830 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2345327830
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.451587041
Short name T684
Test name
Test status
Simulation time 24862795 ps
CPU time 1.13 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 229660 kb
Host smart-3bec9ac1-c02c-467b-84c6-2c2b9f9a6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451587041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.451587041
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2216244185
Short name T683
Test name
Test status
Simulation time 45768868 ps
CPU time 1.33 seconds
Started Mar 19 02:56:40 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 216768 kb
Host smart-a6939e8c-bd0a-4aaa-8f71-6cebc4ba1e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216244185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2216244185
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2908818643
Short name T379
Test name
Test status
Simulation time 40505215 ps
CPU time 0.88 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 215360 kb
Host smart-526e50d1-a9b4-4be6-b6b5-9bd22a9a8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908818643 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2908818643
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2882556250
Short name T384
Test name
Test status
Simulation time 83345588 ps
CPU time 0.95 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:35 PM PDT 24
Peak memory 215444 kb
Host smart-be2941ca-3bb6-4295-bb7b-a2d9cb8078f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882556250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2882556250
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4032644302
Short name T368
Test name
Test status
Simulation time 173644583 ps
CPU time 1.09 seconds
Started Mar 19 02:56:40 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 215404 kb
Host smart-88b51a47-d1ad-4158-8864-92b8db2ea909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032644302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4032644302
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2501385100
Short name T714
Test name
Test status
Simulation time 242876317578 ps
CPU time 1372.9 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 03:19:30 PM PDT 24
Peak memory 224060 kb
Host smart-029eb07d-5d48-4a12-9fd3-8eddfc2ff6cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501385100 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2501385100
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3704240453
Short name T796
Test name
Test status
Simulation time 84590990 ps
CPU time 1.2 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 215776 kb
Host smart-85561d30-8d16-4124-8946-5cc86449dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704240453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3704240453
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2320918892
Short name T681
Test name
Test status
Simulation time 47194205 ps
CPU time 0.92 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 206980 kb
Host smart-81851f4f-b11e-496d-b540-2b3843f30469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320918892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2320918892
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.914294709
Short name T105
Test name
Test status
Simulation time 21382080 ps
CPU time 0.88 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 215544 kb
Host smart-6b0b485c-2916-4b1a-b952-5e02c7038c37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914294709 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.914294709
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2974273994
Short name T90
Test name
Test status
Simulation time 50697789 ps
CPU time 1.14 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 216448 kb
Host smart-abfa5fd8-0ddc-40e8-8000-70f8f8017f2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974273994 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2974273994
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2760676421
Short name T112
Test name
Test status
Simulation time 19416795 ps
CPU time 1.11 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 218124 kb
Host smart-97e65860-f67d-49d0-82f6-dc3ecf621577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760676421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2760676421
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.230915386
Short name T782
Test name
Test status
Simulation time 46107604 ps
CPU time 1.32 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 217740 kb
Host smart-2309b9fe-8828-48ea-ac28-9d7bddc7cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230915386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.230915386
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2144633071
Short name T441
Test name
Test status
Simulation time 26016772 ps
CPU time 0.97 seconds
Started Mar 19 02:56:41 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 215524 kb
Host smart-b39dc35e-5260-4d17-b375-4af000099818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144633071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2144633071
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.279744718
Short name T421
Test name
Test status
Simulation time 22278374 ps
CPU time 0.94 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 215420 kb
Host smart-1e08ed87-e038-4cf5-ac31-2e54b3473461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279744718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.279744718
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.876949457
Short name T547
Test name
Test status
Simulation time 48060123 ps
CPU time 1.5 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 206008 kb
Host smart-cb82b67f-3f47-44ba-8b97-59b7d4768d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876949457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.876949457
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1501825071
Short name T25
Test name
Test status
Simulation time 230418864460 ps
CPU time 1326.52 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 03:18:47 PM PDT 24
Peak memory 223824 kb
Host smart-8f244e7b-5ab3-42dc-ba8f-817f5071bfd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501825071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1501825071
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4049657879
Short name T157
Test name
Test status
Simulation time 36970639 ps
CPU time 1.05 seconds
Started Mar 19 02:56:33 PM PDT 24
Finished Mar 19 02:56:35 PM PDT 24
Peak memory 215772 kb
Host smart-739e45c7-8f57-4ac2-8c9a-92d5ffdcae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049657879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4049657879
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3029564651
Short name T445
Test name
Test status
Simulation time 16482826 ps
CPU time 0.93 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 206972 kb
Host smart-7e6b048c-869e-4e53-86c3-a4de894d0a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029564651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3029564651
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3225295111
Short name T621
Test name
Test status
Simulation time 51574843 ps
CPU time 1.03 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 217992 kb
Host smart-2f03cce5-4d40-405a-be7d-6b285605098b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225295111 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3225295111
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3169915713
Short name T192
Test name
Test status
Simulation time 41127453 ps
CPU time 1.25 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 233480 kb
Host smart-5efff3ed-2621-4f6d-8659-27dd000404de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169915713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3169915713
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3300702036
Short name T804
Test name
Test status
Simulation time 35057092 ps
CPU time 1.3 seconds
Started Mar 19 02:56:34 PM PDT 24
Finished Mar 19 02:56:36 PM PDT 24
Peak memory 216932 kb
Host smart-c01c5239-47a3-4ef9-9cde-6d3d518b112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300702036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3300702036
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.872908516
Short name T602
Test name
Test status
Simulation time 35826289 ps
CPU time 0.94 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 215532 kb
Host smart-38858639-4036-4f67-b6a0-4b05a2ee0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872908516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.872908516
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2727729174
Short name T571
Test name
Test status
Simulation time 15579325 ps
CPU time 0.99 seconds
Started Mar 19 02:56:32 PM PDT 24
Finished Mar 19 02:56:34 PM PDT 24
Peak memory 215432 kb
Host smart-14ddb978-37c9-4064-a662-bc9bbfed1106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727729174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2727729174
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2079345377
Short name T810
Test name
Test status
Simulation time 85721518 ps
CPU time 1.49 seconds
Started Mar 19 02:56:31 PM PDT 24
Finished Mar 19 02:56:33 PM PDT 24
Peak memory 217864 kb
Host smart-ce1e0a73-40bd-4af3-8b8e-fae8878f080f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079345377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2079345377
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1424813560
Short name T212
Test name
Test status
Simulation time 40100330921 ps
CPU time 922.96 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 03:11:59 PM PDT 24
Peak memory 223844 kb
Host smart-1c410939-06f2-4585-a331-916bb8a23f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424813560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1424813560
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1193458020
Short name T360
Test name
Test status
Simulation time 205347601 ps
CPU time 1.27 seconds
Started Mar 19 02:56:42 PM PDT 24
Finished Mar 19 02:56:44 PM PDT 24
Peak memory 215768 kb
Host smart-5fc1351f-0219-46ba-8ba1-1d2445573966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193458020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1193458020
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2609635784
Short name T770
Test name
Test status
Simulation time 56249082 ps
CPU time 0.82 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 206016 kb
Host smart-b244de66-959c-440a-af36-49b362926c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609635784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2609635784
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1073069217
Short name T512
Test name
Test status
Simulation time 11170715 ps
CPU time 0.93 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 216056 kb
Host smart-b0f758f1-5e37-481d-acd1-924bd2743cf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073069217 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1073069217
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3086572303
Short name T636
Test name
Test status
Simulation time 70144108 ps
CPU time 1.04 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 216932 kb
Host smart-a4565d52-8f8c-4c9f-bf00-4461af670ad5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086572303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3086572303
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.67466473
Short name T122
Test name
Test status
Simulation time 26244629 ps
CPU time 1.04 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 231352 kb
Host smart-d53cdd29-53ce-4094-bd65-456095f3796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67466473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.67466473
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_intr.4184273554
Short name T772
Test name
Test status
Simulation time 35910716 ps
CPU time 0.8 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 215624 kb
Host smart-c29c89cf-b7a6-45ed-b191-30abf6a58215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184273554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4184273554
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.539580839
Short name T675
Test name
Test status
Simulation time 93304364 ps
CPU time 1.03 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 215456 kb
Host smart-943794b2-bd87-4c02-81c9-b90b5bd69f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539580839 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.539580839
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.466723240
Short name T760
Test name
Test status
Simulation time 423998888 ps
CPU time 2.89 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 216536 kb
Host smart-7adb89fb-610d-4723-8449-c22c6dc706da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466723240 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.466723240
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2854152172
Short name T737
Test name
Test status
Simulation time 14789677776 ps
CPU time 391.24 seconds
Started Mar 19 02:56:41 PM PDT 24
Finished Mar 19 03:03:13 PM PDT 24
Peak memory 218304 kb
Host smart-21da0ec5-746f-4359-bc9c-a7fd1a5398a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854152172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2854152172
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.3418152243
Short name T639
Test name
Test status
Simulation time 26423160 ps
CPU time 0.93 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 206136 kb
Host smart-6e7b4d1b-2012-4f9c-9bf4-beffaf0b4cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418152243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3418152243
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3617272114
Short name T219
Test name
Test status
Simulation time 14514838 ps
CPU time 0.86 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 215648 kb
Host smart-1912d24f-ab7e-4b5e-8853-f68d51787e4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617272114 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3617272114
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.130561923
Short name T86
Test name
Test status
Simulation time 89360719 ps
CPU time 1.06 seconds
Started Mar 19 02:56:54 PM PDT 24
Finished Mar 19 02:56:56 PM PDT 24
Peak memory 229652 kb
Host smart-15251dc2-de94-481a-87c9-6e21df508c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130561923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.130561923
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2867387866
Short name T396
Test name
Test status
Simulation time 87839448 ps
CPU time 1.17 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 216640 kb
Host smart-96e5e0d3-e415-4b47-8e1a-a913669d39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867387866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2867387866
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.484426290
Short name T574
Test name
Test status
Simulation time 20688242 ps
CPU time 0.99 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215432 kb
Host smart-d43b9e9c-6469-4828-89c4-489a1b17bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484426290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.484426290
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3600029551
Short name T434
Test name
Test status
Simulation time 484521616 ps
CPU time 4.74 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 216612 kb
Host smart-80b3fab4-1bc2-4f07-9fcd-87639793c964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600029551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3600029551
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4201476225
Short name T555
Test name
Test status
Simulation time 50527180637 ps
CPU time 1086.53 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 03:14:45 PM PDT 24
Peak memory 220632 kb
Host smart-2453411f-5fbb-40e1-a491-30efbfe0e7e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201476225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4201476225
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1538911158
Short name T838
Test name
Test status
Simulation time 77244784 ps
CPU time 1.19 seconds
Started Mar 19 02:56:44 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215464 kb
Host smart-42a7abcb-5900-4b51-9884-3b8a40ced1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538911158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1538911158
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.983760419
Short name T159
Test name
Test status
Simulation time 89069970 ps
CPU time 0.98 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:44 PM PDT 24
Peak memory 206200 kb
Host smart-7fac4d3b-de0e-4304-823c-4aca37e3b19a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983760419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.983760419
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.346314543
Short name T178
Test name
Test status
Simulation time 28625972 ps
CPU time 0.89 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 216040 kb
Host smart-d30433e3-28ac-4498-a2f5-19026be06b65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346314543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.346314543
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2137501042
Short name T826
Test name
Test status
Simulation time 47051674 ps
CPU time 1.09 seconds
Started Mar 19 02:56:41 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 216480 kb
Host smart-0a466264-15a3-4f83-b245-5a3f91682788
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137501042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2137501042
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2052484621
Short name T824
Test name
Test status
Simulation time 27619833 ps
CPU time 1.23 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 219724 kb
Host smart-90ecfa06-63b7-4424-a591-165dffbd3c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052484621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2052484621
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1155300763
Short name T615
Test name
Test status
Simulation time 47375242 ps
CPU time 1.45 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 217944 kb
Host smart-93ece0c4-55fd-48de-b691-535f8cdc1389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155300763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1155300763
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2674825541
Short name T440
Test name
Test status
Simulation time 29740060 ps
CPU time 1.06 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 232528 kb
Host smart-a5f13070-906b-477e-b647-3162a8a7c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674825541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2674825541
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3040879687
Short name T318
Test name
Test status
Simulation time 47240816 ps
CPU time 0.94 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 207224 kb
Host smart-05aee212-0c4b-43c3-a176-61a09a3d871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040879687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3040879687
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.299906100
Short name T453
Test name
Test status
Simulation time 108435718 ps
CPU time 2.58 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 215440 kb
Host smart-8624e976-e6c1-4f27-ba45-84a0557068e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299906100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.299906100
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2973152779
Short name T740
Test name
Test status
Simulation time 29262871204 ps
CPU time 622.21 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 03:07:02 PM PDT 24
Peak memory 218248 kb
Host smart-61c691f4-c86d-4413-8baf-ff3a20fdf85a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973152779 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2973152779
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.4157622391
Short name T129
Test name
Test status
Simulation time 77406892 ps
CPU time 1.18 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 215788 kb
Host smart-c74bfe45-d4a0-48ec-864b-4dfeff7a259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157622391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4157622391
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1337638011
Short name T162
Test name
Test status
Simulation time 76528454 ps
CPU time 0.86 seconds
Started Mar 19 02:56:54 PM PDT 24
Finished Mar 19 02:56:55 PM PDT 24
Peak memory 206136 kb
Host smart-579cd0c1-4044-4991-9885-c760d95fca6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337638011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1337638011
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4012007489
Short name T534
Test name
Test status
Simulation time 85470697 ps
CPU time 1.09 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 216608 kb
Host smart-269427e3-094e-4c8c-aa21-0ca28cd06192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012007489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4012007489
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1042466439
Short name T193
Test name
Test status
Simulation time 78244536 ps
CPU time 1.04 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 219272 kb
Host smart-65e388f1-92a8-4ac1-8764-9b35da568f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042466439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1042466439
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4176432702
Short name T33
Test name
Test status
Simulation time 32058521 ps
CPU time 1.67 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 217960 kb
Host smart-8ade2aa7-2edb-465a-8d53-14be9b19c488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176432702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4176432702
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4065740703
Short name T331
Test name
Test status
Simulation time 20999807 ps
CPU time 1.07 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 215768 kb
Host smart-e28e8d21-f8b8-4cb0-8ebd-2ca029970bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065740703 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4065740703
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1404883184
Short name T349
Test name
Test status
Simulation time 20459587 ps
CPU time 0.91 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 215420 kb
Host smart-d4189922-6372-488b-ab17-682038556a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404883184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1404883184
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1756952910
Short name T669
Test name
Test status
Simulation time 96634743 ps
CPU time 2.59 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:49 PM PDT 24
Peak memory 216740 kb
Host smart-d0185587-0882-45c3-bd05-312336b7e220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756952910 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1756952910
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.669830037
Short name T204
Test name
Test status
Simulation time 112394881394 ps
CPU time 1624.8 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 03:24:01 PM PDT 24
Peak memory 224744 kb
Host smart-1976a3c6-6bf5-47fc-a6e5-5c422fd8dd10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669830037 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.669830037
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3347639904
Short name T470
Test name
Test status
Simulation time 42638635 ps
CPU time 1.12 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:38 PM PDT 24
Peak memory 215808 kb
Host smart-58a8adf8-9230-4756-b6f3-ca95cb714ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347639904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3347639904
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2937104812
Short name T160
Test name
Test status
Simulation time 18037907 ps
CPU time 0.77 seconds
Started Mar 19 02:56:44 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 205832 kb
Host smart-a6dda7c7-0796-4319-aebc-fe52c54a580b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937104812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2937104812
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2255758178
Short name T97
Test name
Test status
Simulation time 28133405 ps
CPU time 1.19 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 216776 kb
Host smart-45f63acb-56d1-4ee7-a83c-017fad1c515d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255758178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2255758178
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_genbits.1865028297
Short name T797
Test name
Test status
Simulation time 273394866 ps
CPU time 3.93 seconds
Started Mar 19 02:56:43 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 216856 kb
Host smart-e49a3e25-9719-4b96-a8d8-eddaf1f7ce39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865028297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1865028297
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2873905642
Short name T742
Test name
Test status
Simulation time 62412461 ps
CPU time 0.82 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 02:56:46 PM PDT 24
Peak memory 215724 kb
Host smart-51438a0a-80cb-4c99-a0dc-43cde2938768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873905642 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2873905642
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.564115972
Short name T334
Test name
Test status
Simulation time 21046505 ps
CPU time 0.91 seconds
Started Mar 19 02:56:36 PM PDT 24
Finished Mar 19 02:56:37 PM PDT 24
Peak memory 215424 kb
Host smart-8368fea4-41b3-4a74-a347-c92058f88914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564115972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.564115972
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3060086850
Short name T617
Test name
Test status
Simulation time 470037758 ps
CPU time 2.54 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 02:56:58 PM PDT 24
Peak memory 215480 kb
Host smart-aff25d61-0c13-4a18-b1c0-94d88209c0f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060086850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3060086850
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1477967753
Short name T23
Test name
Test status
Simulation time 44755149826 ps
CPU time 602.91 seconds
Started Mar 19 02:56:35 PM PDT 24
Finished Mar 19 03:06:38 PM PDT 24
Peak memory 219164 kb
Host smart-4f5f37de-057c-48b8-ad2d-65500511026e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477967753 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1477967753
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1504482896
Short name T762
Test name
Test status
Simulation time 49726351 ps
CPU time 1.2 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 02:56:56 PM PDT 24
Peak memory 215808 kb
Host smart-1e1a2faf-749b-4316-a899-5741fdc71c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504482896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1504482896
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3550339073
Short name T320
Test name
Test status
Simulation time 38679543 ps
CPU time 0.86 seconds
Started Mar 19 02:56:37 PM PDT 24
Finished Mar 19 02:56:39 PM PDT 24
Peak memory 206644 kb
Host smart-220ea676-04d7-4fb7-b5b3-74c308f1dcb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550339073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3550339073
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2457005523
Short name T549
Test name
Test status
Simulation time 30853654 ps
CPU time 0.89 seconds
Started Mar 19 02:56:40 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 215620 kb
Host smart-ea77ee08-3201-4310-8848-017ce3ab140d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457005523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2457005523
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.322057677
Short name T93
Test name
Test status
Simulation time 32717900 ps
CPU time 1.19 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 231392 kb
Host smart-c33a2ef3-ad6e-4979-8299-d73326a0fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322057677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.322057677
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2689607662
Short name T803
Test name
Test status
Simulation time 32278025 ps
CPU time 1.07 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 218412 kb
Host smart-c1db936f-11b7-482f-a5f0-62a1acb96574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689607662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2689607662
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3067268104
Short name T144
Test name
Test status
Simulation time 42310661 ps
CPU time 0.84 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:40 PM PDT 24
Peak memory 215688 kb
Host smart-9fe88a0b-6c2b-4978-aae4-182c4ca6c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067268104 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3067268104
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.221042572
Short name T466
Test name
Test status
Simulation time 35858870 ps
CPU time 0.88 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 215356 kb
Host smart-d6d9f49d-8549-4a0b-9e9d-59f2a28864ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221042572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.221042572
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3974872790
Short name T220
Test name
Test status
Simulation time 354502753 ps
CPU time 2.85 seconds
Started Mar 19 02:56:38 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 216828 kb
Host smart-93db29ea-c72b-4cdd-9578-d72376a9a794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974872790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3974872790
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.234068094
Short name T532
Test name
Test status
Simulation time 79390757972 ps
CPU time 1997.07 seconds
Started Mar 19 02:56:59 PM PDT 24
Finished Mar 19 03:30:16 PM PDT 24
Peak memory 228768 kb
Host smart-9a7b447e-86bc-403b-a66f-524f93a90f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234068094 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.234068094
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.355995914
Short name T115
Test name
Test status
Simulation time 26446646 ps
CPU time 1.19 seconds
Started Mar 19 02:56:40 PM PDT 24
Finished Mar 19 02:56:42 PM PDT 24
Peak memory 215816 kb
Host smart-593be416-d1b5-49b3-8067-0d012e1ce307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355995914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.355995914
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.704506966
Short name T353
Test name
Test status
Simulation time 90759537 ps
CPU time 1.94 seconds
Started Mar 19 02:56:47 PM PDT 24
Finished Mar 19 02:56:49 PM PDT 24
Peak memory 206236 kb
Host smart-3a16fa04-818e-407f-a5cc-e29c9075ee28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704506966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.704506966
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1961705706
Short name T414
Test name
Test status
Simulation time 10765626 ps
CPU time 0.87 seconds
Started Mar 19 02:56:39 PM PDT 24
Finished Mar 19 02:56:41 PM PDT 24
Peak memory 215616 kb
Host smart-f6da182f-36bb-4336-aab4-1ace89f98cbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961705706 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1961705706
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.61652845
Short name T718
Test name
Test status
Simulation time 89554882 ps
CPU time 1.01 seconds
Started Mar 19 02:56:59 PM PDT 24
Finished Mar 19 02:57:01 PM PDT 24
Peak memory 217732 kb
Host smart-13cf8e02-04ec-488d-87d5-1ee8281954a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61652845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_dis
able_auto_req_mode.61652845
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3357752283
Short name T172
Test name
Test status
Simulation time 32115138 ps
CPU time 0.9 seconds
Started Mar 19 02:56:42 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 218364 kb
Host smart-440be5d1-b0e5-44ce-8614-feb9488a7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357752283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3357752283
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.616612239
Short name T417
Test name
Test status
Simulation time 38000051 ps
CPU time 1.39 seconds
Started Mar 19 02:56:41 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 218056 kb
Host smart-3c3c67a2-72df-4ce9-ac6f-1556bf54d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616612239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.616612239
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.929896787
Short name T735
Test name
Test status
Simulation time 22016963 ps
CPU time 0.93 seconds
Started Mar 19 02:56:42 PM PDT 24
Finished Mar 19 02:56:43 PM PDT 24
Peak memory 215860 kb
Host smart-b44468d6-5509-4db2-9a52-91eb8f9023b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929896787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.929896787
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1285968935
Short name T786
Test name
Test status
Simulation time 50202838 ps
CPU time 0.91 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 215392 kb
Host smart-198e1b41-e1d6-4000-8c05-69715f82ae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285968935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1285968935
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3339603683
Short name T63
Test name
Test status
Simulation time 291700963 ps
CPU time 3.44 seconds
Started Mar 19 02:56:41 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215440 kb
Host smart-211e3b3f-a66a-4350-99ca-f498745073e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339603683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3339603683
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2156007848
Short name T728
Test name
Test status
Simulation time 31385452200 ps
CPU time 689.98 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 03:08:23 PM PDT 24
Peak memory 218276 kb
Host smart-525f2b7b-03ae-469d-97dd-84f86f56be9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156007848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2156007848
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3065170570
Short name T78
Test name
Test status
Simulation time 77778904 ps
CPU time 1.18 seconds
Started Mar 19 02:55:53 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 215808 kb
Host smart-2bce2c7d-8fa5-4ab3-a5d2-6bbf4c914bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065170570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3065170570
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3437939661
Short name T570
Test name
Test status
Simulation time 19123627 ps
CPU time 1.02 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 206240 kb
Host smart-a73f64ab-7c1b-4807-94af-f137fde14dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437939661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3437939661
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.4234986508
Short name T337
Test name
Test status
Simulation time 36138249 ps
CPU time 0.81 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 215640 kb
Host smart-4b5e58dc-d437-4ed4-bb7a-0479029ce44f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234986508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4234986508
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2610258071
Short name T659
Test name
Test status
Simulation time 257430420 ps
CPU time 1.14 seconds
Started Mar 19 02:55:54 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 217852 kb
Host smart-16f29f08-32bc-4fa7-88cc-31552ac628c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610258071 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2610258071
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.4284049217
Short name T816
Test name
Test status
Simulation time 45115291 ps
CPU time 1.12 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 216732 kb
Host smart-bf768e4f-1558-4182-be13-e56db837ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284049217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4284049217
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2717426862
Short name T137
Test name
Test status
Simulation time 29179469 ps
CPU time 0.87 seconds
Started Mar 19 02:55:43 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 215668 kb
Host smart-2f503553-8497-4e55-acb1-8751bb2d6b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717426862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2717426862
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2268310339
Short name T130
Test name
Test status
Simulation time 100498665 ps
CPU time 0.9 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 207208 kb
Host smart-4adf3730-58d2-4565-ad1a-df73973fe486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268310339 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2268310339
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.212946275
Short name T381
Test name
Test status
Simulation time 17596414 ps
CPU time 0.97 seconds
Started Mar 19 02:55:48 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215404 kb
Host smart-ba1dc664-1237-4d51-8621-4dfea35c86f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212946275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.212946275
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3550528399
Short name T538
Test name
Test status
Simulation time 281515431 ps
CPU time 1.84 seconds
Started Mar 19 02:55:46 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 216848 kb
Host smart-42bf499a-cb28-481f-a35a-e0030b6e85bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550528399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3550528399
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3189639845
Short name T569
Test name
Test status
Simulation time 42062220464 ps
CPU time 718.44 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 217916 kb
Host smart-447a28d0-2382-4292-a16f-96c4aaa37135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189639845 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3189639845
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.3217175299
Short name T488
Test name
Test status
Simulation time 17229779 ps
CPU time 0.95 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:53 PM PDT 24
Peak memory 206760 kb
Host smart-633a5af1-4dd9-416b-9b3a-c56f4ad7dd78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217175299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3217175299
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3518928359
Short name T118
Test name
Test status
Simulation time 33551336 ps
CPU time 0.83 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 215904 kb
Host smart-98001538-5ecb-405d-9544-e57fe7e61645
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518928359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3518928359
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3611494063
Short name T409
Test name
Test status
Simulation time 22280368 ps
CPU time 1 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 217800 kb
Host smart-0d0af32b-f84a-45b5-8023-3ca891d6818c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611494063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3611494063
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1581697506
Short name T80
Test name
Test status
Simulation time 91311457 ps
CPU time 1.07 seconds
Started Mar 19 02:56:44 PM PDT 24
Finished Mar 19 02:56:46 PM PDT 24
Peak memory 220376 kb
Host smart-b57e95a5-dac4-4e8f-bcac-9f15dc26a826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581697506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1581697506
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1601145312
Short name T563
Test name
Test status
Simulation time 84337703 ps
CPU time 2.09 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:48 PM PDT 24
Peak memory 219792 kb
Host smart-4b7a38ee-0205-47b0-83ba-386080ef8b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601145312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1601145312
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3827574129
Short name T141
Test name
Test status
Simulation time 22312364 ps
CPU time 0.91 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:57:00 PM PDT 24
Peak memory 215840 kb
Host smart-21eb3faa-f3dd-427b-89f9-ed669430352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827574129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3827574129
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3266275252
Short name T463
Test name
Test status
Simulation time 55326847 ps
CPU time 0.92 seconds
Started Mar 19 02:56:44 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215396 kb
Host smart-279bc216-f48c-49dd-bce9-6ddde112f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266275252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3266275252
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2764384170
Short name T749
Test name
Test status
Simulation time 214686988 ps
CPU time 4.37 seconds
Started Mar 19 02:56:50 PM PDT 24
Finished Mar 19 02:56:55 PM PDT 24
Peak memory 216496 kb
Host smart-0d6cdb02-78c0-4e86-976c-d9b93dbaa223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764384170 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2764384170
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.4061042327
Short name T514
Test name
Test status
Simulation time 64275302396 ps
CPU time 844.56 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 03:11:10 PM PDT 24
Peak memory 223788 kb
Host smart-03d4fce3-f2ba-41ae-818f-11aef1bae5b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061042327 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4061042327
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1565862913
Short name T576
Test name
Test status
Simulation time 98747438 ps
CPU time 1.29 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:48 PM PDT 24
Peak memory 215780 kb
Host smart-6c92fcda-2587-40f2-958f-b1a56d4acec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565862913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1565862913
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2227977556
Short name T701
Test name
Test status
Simulation time 21003922 ps
CPU time 1 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 206620 kb
Host smart-b60372e0-f75f-49eb-9633-dfedf2e60899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227977556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2227977556
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4242440331
Short name T784
Test name
Test status
Simulation time 89273533 ps
CPU time 1.09 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 216484 kb
Host smart-43ec5038-4a97-4250-910c-60bf73d0c5d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242440331 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4242440331
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3712318612
Short name T67
Test name
Test status
Simulation time 18545064 ps
CPU time 1.05 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 218280 kb
Host smart-d10c3e54-dda5-4b72-b246-d5c1c90d6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712318612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3712318612
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.553759108
Short name T296
Test name
Test status
Simulation time 69560951 ps
CPU time 1.2 seconds
Started Mar 19 02:56:47 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 218328 kb
Host smart-52131ace-83b7-4313-9b40-6981fceabf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553759108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.553759108
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1873951331
Short name T1
Test name
Test status
Simulation time 21375958 ps
CPU time 1.03 seconds
Started Mar 19 02:57:07 PM PDT 24
Finished Mar 19 02:57:08 PM PDT 24
Peak memory 215672 kb
Host smart-2de16937-df1b-4c74-9aba-24c3da6efbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873951331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1873951331
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.547344847
Short name T430
Test name
Test status
Simulation time 113234732 ps
CPU time 0.93 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 215444 kb
Host smart-0be60883-e758-4166-af4f-38439db0b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547344847 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.547344847
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2603089698
Short name T62
Test name
Test status
Simulation time 199347316 ps
CPU time 1.7 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 215316 kb
Host smart-6b15eb94-abe2-452c-bc7e-9b31110e955c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603089698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2603089698
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2769988222
Short name T295
Test name
Test status
Simulation time 165542150688 ps
CPU time 470.1 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 03:04:36 PM PDT 24
Peak memory 219068 kb
Host smart-f20b674a-ea4d-4e55-bbe3-ce66627a9aa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769988222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2769988222
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3179089481
Short name T717
Test name
Test status
Simulation time 26286718 ps
CPU time 1.27 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 215796 kb
Host smart-095da498-07f8-41e4-9cd3-af1d98b52187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179089481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3179089481
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.101977648
Short name T831
Test name
Test status
Simulation time 51833398 ps
CPU time 0.92 seconds
Started Mar 19 02:56:59 PM PDT 24
Finished Mar 19 02:57:01 PM PDT 24
Peak memory 206216 kb
Host smart-39755655-3b13-47e8-a801-09e0f188de74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101977648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.101977648
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2078317397
Short name T31
Test name
Test status
Simulation time 44275778 ps
CPU time 0.88 seconds
Started Mar 19 02:56:46 PM PDT 24
Finished Mar 19 02:56:47 PM PDT 24
Peak memory 215596 kb
Host smart-ff0b5882-3925-4177-8a82-5216253dec4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078317397 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2078317397
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1894057019
Short name T541
Test name
Test status
Simulation time 58882852 ps
CPU time 1.07 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:13 PM PDT 24
Peak memory 217944 kb
Host smart-95471a0a-5233-48b4-b6c1-2e6fbffd8062
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894057019 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1894057019
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2044285368
Short name T633
Test name
Test status
Simulation time 18660418 ps
CPU time 0.96 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 218040 kb
Host smart-7c418334-4fe1-4b97-acd1-ff59dbabbddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044285368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2044285368
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3692357597
Short name T309
Test name
Test status
Simulation time 99463634 ps
CPU time 1.33 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 219000 kb
Host smart-fdab143f-2acc-43f4-82ce-793c0fb41d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692357597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3692357597
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2165861153
Short name T583
Test name
Test status
Simulation time 26868461 ps
CPU time 1.05 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 224048 kb
Host smart-6c7311b3-72a1-4a24-b73b-a01591ccbc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165861153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2165861153
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3609593764
Short name T425
Test name
Test status
Simulation time 20502735 ps
CPU time 0.98 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 215392 kb
Host smart-cfe0ff83-a923-4062-9c57-d094b44f5301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609593764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3609593764
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1466791085
Short name T491
Test name
Test status
Simulation time 281758137 ps
CPU time 1.7 seconds
Started Mar 19 02:56:42 PM PDT 24
Finished Mar 19 02:56:45 PM PDT 24
Peak memory 215364 kb
Host smart-eba02d6c-2f17-4d29-909f-31779a481316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466791085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1466791085
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.60853513
Short name T822
Test name
Test status
Simulation time 103752288168 ps
CPU time 583.55 seconds
Started Mar 19 02:56:51 PM PDT 24
Finished Mar 19 03:06:35 PM PDT 24
Peak memory 219148 kb
Host smart-d0fb164a-3f4e-4f3b-a890-b2599eabd3b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60853513 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.60853513
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.543236388
Short name T552
Test name
Test status
Simulation time 145437703 ps
CPU time 1.3 seconds
Started Mar 19 02:56:47 PM PDT 24
Finished Mar 19 02:56:48 PM PDT 24
Peak memory 215784 kb
Host smart-61163c62-c00f-40cd-8759-5ea9a56f40c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543236388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.543236388
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3231522691
Short name T778
Test name
Test status
Simulation time 17698951 ps
CPU time 1.03 seconds
Started Mar 19 02:57:00 PM PDT 24
Finished Mar 19 02:57:02 PM PDT 24
Peak memory 206156 kb
Host smart-92da37b8-35e0-4800-b38c-455002b4f8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231522691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3231522691
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2627679969
Short name T197
Test name
Test status
Simulation time 14485075 ps
CPU time 0.89 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 216052 kb
Host smart-9aea0091-91c9-4b34-8865-989f2493a715
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627679969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2627679969
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2467061175
Short name T81
Test name
Test status
Simulation time 279821225 ps
CPU time 1.25 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 02:56:46 PM PDT 24
Peak memory 216708 kb
Host smart-7e75e16f-0c45-41e2-b186-c98a5d69b89f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467061175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2467061175
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3920365016
Short name T820
Test name
Test status
Simulation time 29753648 ps
CPU time 0.89 seconds
Started Mar 19 02:56:47 PM PDT 24
Finished Mar 19 02:56:48 PM PDT 24
Peak memory 218024 kb
Host smart-f97b347b-f3b7-418e-943d-5894d3f18a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920365016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3920365016
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3639520845
Short name T505
Test name
Test status
Simulation time 55382812 ps
CPU time 0.97 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 216816 kb
Host smart-cd5a5089-4234-4c0d-ba11-e9ec02d6be4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639520845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3639520845
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1475845084
Short name T142
Test name
Test status
Simulation time 20108616 ps
CPU time 1.05 seconds
Started Mar 19 02:56:59 PM PDT 24
Finished Mar 19 02:57:01 PM PDT 24
Peak memory 215780 kb
Host smart-4c1952fe-41e8-44dd-9b41-caca8e2cd3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475845084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1475845084
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.785380794
Short name T57
Test name
Test status
Simulation time 53709595 ps
CPU time 1.07 seconds
Started Mar 19 02:56:51 PM PDT 24
Finished Mar 19 02:56:52 PM PDT 24
Peak memory 215432 kb
Host smart-01f20a01-0e36-42d3-a945-d814aa96a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785380794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.785380794
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1464900319
Short name T557
Test name
Test status
Simulation time 53100545 ps
CPU time 1.12 seconds
Started Mar 19 02:56:48 PM PDT 24
Finished Mar 19 02:56:50 PM PDT 24
Peak memory 206312 kb
Host smart-108c18da-0703-4997-a628-ee1604d44233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464900319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1464900319
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2906564827
Short name T214
Test name
Test status
Simulation time 596092792292 ps
CPU time 834.5 seconds
Started Mar 19 02:56:45 PM PDT 24
Finished Mar 19 03:10:40 PM PDT 24
Peak memory 223888 kb
Host smart-83cb92c9-73df-4030-8a07-d30f82a71c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906564827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2906564827
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.249191391
Short name T811
Test name
Test status
Simulation time 41305107 ps
CPU time 1.19 seconds
Started Mar 19 02:56:49 PM PDT 24
Finished Mar 19 02:56:50 PM PDT 24
Peak memory 215804 kb
Host smart-64d7dfec-2f5d-4aa0-9c44-9eff8b838756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249191391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.249191391
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3023533954
Short name T327
Test name
Test status
Simulation time 12917570 ps
CPU time 0.95 seconds
Started Mar 19 02:56:57 PM PDT 24
Finished Mar 19 02:56:58 PM PDT 24
Peak memory 205976 kb
Host smart-d2a2ed36-e699-4bcc-8431-768b07e218a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023533954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3023533954
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4239030124
Short name T452
Test name
Test status
Simulation time 14710671 ps
CPU time 0.95 seconds
Started Mar 19 02:56:51 PM PDT 24
Finished Mar 19 02:56:52 PM PDT 24
Peak memory 216196 kb
Host smart-cf9f88e9-3707-4770-92bf-94bda811163e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239030124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4239030124
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.3907648636
Short name T376
Test name
Test status
Simulation time 20346638 ps
CPU time 1.05 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 217960 kb
Host smart-afa1affa-ae01-4614-8944-540241058626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907648636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3907648636
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2282620598
Short name T805
Test name
Test status
Simulation time 39498587 ps
CPU time 1.48 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 216892 kb
Host smart-621e8c54-2cc7-437f-8889-ced355181612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282620598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2282620598
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1679195491
Short name T464
Test name
Test status
Simulation time 60572866 ps
CPU time 0.86 seconds
Started Mar 19 02:56:49 PM PDT 24
Finished Mar 19 02:56:50 PM PDT 24
Peak memory 215376 kb
Host smart-3ad5cd65-793e-4148-9518-d10ba314392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679195491 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1679195491
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1977696365
Short name T585
Test name
Test status
Simulation time 45519331 ps
CPU time 0.91 seconds
Started Mar 19 02:56:49 PM PDT 24
Finished Mar 19 02:56:50 PM PDT 24
Peak memory 207216 kb
Host smart-12fc092d-3cac-4800-ba6f-172042a174ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977696365 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1977696365
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1565748052
Short name T40
Test name
Test status
Simulation time 347186631 ps
CPU time 2.44 seconds
Started Mar 19 02:56:48 PM PDT 24
Finished Mar 19 02:56:51 PM PDT 24
Peak memory 216888 kb
Host smart-f22299ee-0d24-4f43-8009-6d5a2facff40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565748052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1565748052
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1960647898
Short name T610
Test name
Test status
Simulation time 29364409998 ps
CPU time 760.05 seconds
Started Mar 19 02:56:49 PM PDT 24
Finished Mar 19 03:09:29 PM PDT 24
Peak memory 218148 kb
Host smart-5b775336-8333-4cf8-97df-28e825c4982b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960647898 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1960647898
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.4186387698
Short name T699
Test name
Test status
Simulation time 28669309 ps
CPU time 1.2 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 02:56:57 PM PDT 24
Peak memory 215772 kb
Host smart-949bcff6-a0e6-48c3-983e-02e597d31b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186387698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4186387698
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.4214412670
Short name T656
Test name
Test status
Simulation time 54015951 ps
CPU time 0.83 seconds
Started Mar 19 02:56:50 PM PDT 24
Finished Mar 19 02:56:51 PM PDT 24
Peak memory 205820 kb
Host smart-619c9b08-2e91-4bc0-92b2-0a4b37043448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214412670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.4214412670
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4216473181
Short name T704
Test name
Test status
Simulation time 12044949 ps
CPU time 0.84 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:53 PM PDT 24
Peak memory 215972 kb
Host smart-8dc0e748-b057-4cd6-98c5-e4589e13d069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216473181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4216473181
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.1687485822
Short name T460
Test name
Test status
Simulation time 26226101 ps
CPU time 1.08 seconds
Started Mar 19 02:57:11 PM PDT 24
Finished Mar 19 02:57:13 PM PDT 24
Peak memory 231424 kb
Host smart-7ad6391d-4f3f-43cc-b541-4fecd81013f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687485822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1687485822
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2393590430
Short name T581
Test name
Test status
Simulation time 28676499 ps
CPU time 1.41 seconds
Started Mar 19 02:56:53 PM PDT 24
Finished Mar 19 02:56:55 PM PDT 24
Peak memory 219624 kb
Host smart-d7c1ef65-200c-444f-b8bc-3f9793ab62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393590430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2393590430
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.82816831
Short name T432
Test name
Test status
Simulation time 31272446 ps
CPU time 0.86 seconds
Started Mar 19 02:56:50 PM PDT 24
Finished Mar 19 02:56:51 PM PDT 24
Peak memory 215728 kb
Host smart-8e3b1f0b-d005-4989-ad13-7decf89a02b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82816831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.82816831
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2528758092
Short name T498
Test name
Test status
Simulation time 28627073 ps
CPU time 0.96 seconds
Started Mar 19 02:56:48 PM PDT 24
Finished Mar 19 02:56:49 PM PDT 24
Peak memory 215448 kb
Host smart-4913cc6b-a9a1-4186-ae75-56695bca8c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528758092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2528758092
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2783408942
Short name T459
Test name
Test status
Simulation time 59818244 ps
CPU time 1.6 seconds
Started Mar 19 02:57:00 PM PDT 24
Finished Mar 19 02:57:02 PM PDT 24
Peak memory 207200 kb
Host smart-1ae3bf5f-fcd6-4970-ad3a-3494c2b6f02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783408942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2783408942
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.520097850
Short name T301
Test name
Test status
Simulation time 31634339526 ps
CPU time 365.5 seconds
Started Mar 19 02:56:57 PM PDT 24
Finished Mar 19 03:03:03 PM PDT 24
Peak memory 219460 kb
Host smart-11e7e7b8-2599-4215-9d8c-13fc4a7b414d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520097850 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.520097850
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.4125441760
Short name T199
Test name
Test status
Simulation time 27995147 ps
CPU time 1.34 seconds
Started Mar 19 02:56:56 PM PDT 24
Finished Mar 19 02:56:57 PM PDT 24
Peak memory 215764 kb
Host smart-13faadd4-25bb-4b32-8910-e5119846d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125441760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4125441760
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.258233582
Short name T386
Test name
Test status
Simulation time 36789993 ps
CPU time 0.83 seconds
Started Mar 19 02:56:57 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 205784 kb
Host smart-b45f44cf-5e37-4bd6-855a-637b88e38d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258233582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.258233582
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.63005535
Short name T70
Test name
Test status
Simulation time 13492901 ps
CPU time 0.92 seconds
Started Mar 19 02:56:48 PM PDT 24
Finished Mar 19 02:56:49 PM PDT 24
Peak memory 216272 kb
Host smart-4f65d144-c95d-438f-be9f-2f83b5609b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63005535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.63005535
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3542691585
Short name T437
Test name
Test status
Simulation time 62063410 ps
CPU time 1.16 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 217872 kb
Host smart-55b04af1-8419-4ca1-a2d8-82793520b8ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542691585 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3542691585
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.966954806
Short name T91
Test name
Test status
Simulation time 30028281 ps
CPU time 1.02 seconds
Started Mar 19 02:56:54 PM PDT 24
Finished Mar 19 02:56:56 PM PDT 24
Peak memory 218280 kb
Host smart-98cd589e-4804-475b-ba1e-b845d1fdbe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966954806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.966954806
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3214195229
Short name T607
Test name
Test status
Simulation time 83077246 ps
CPU time 1.28 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:54 PM PDT 24
Peak memory 216964 kb
Host smart-43a25770-339b-4812-8334-5acf17a2e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214195229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3214195229
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.153587985
Short name T536
Test name
Test status
Simulation time 35293007 ps
CPU time 0.91 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 215536 kb
Host smart-488fbaee-dd79-4f6a-9ce6-d7391cec4faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153587985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.153587985
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1693459632
Short name T340
Test name
Test status
Simulation time 18159959 ps
CPU time 1 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 02:56:56 PM PDT 24
Peak memory 215404 kb
Host smart-ae8740e0-0305-4c60-898a-a6b29bb804d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693459632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1693459632
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3828438987
Short name T628
Test name
Test status
Simulation time 432979205 ps
CPU time 5.01 seconds
Started Mar 19 02:56:52 PM PDT 24
Finished Mar 19 02:56:58 PM PDT 24
Peak memory 215492 kb
Host smart-3d4445c4-7dc7-477b-b2e6-6e36c0f4497d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828438987 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3828438987
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1605064293
Short name T751
Test name
Test status
Simulation time 146531603774 ps
CPU time 983.33 seconds
Started Mar 19 02:56:53 PM PDT 24
Finished Mar 19 03:13:16 PM PDT 24
Peak memory 222228 kb
Host smart-61e1ba39-465f-47bc-80b4-aab60bb8c951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605064293 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1605064293
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2760705957
Short name T562
Test name
Test status
Simulation time 42142961 ps
CPU time 1.21 seconds
Started Mar 19 02:56:57 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 215856 kb
Host smart-b612e89b-9a02-433b-8634-972051b96ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760705957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2760705957
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3657353701
Short name T161
Test name
Test status
Simulation time 18751394 ps
CPU time 1 seconds
Started Mar 19 02:57:02 PM PDT 24
Finished Mar 19 02:57:03 PM PDT 24
Peak memory 206756 kb
Host smart-bea1ae8d-712e-4047-bb93-99999baf9173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657353701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3657353701
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4124422665
Short name T186
Test name
Test status
Simulation time 15369337 ps
CPU time 0.95 seconds
Started Mar 19 02:57:07 PM PDT 24
Finished Mar 19 02:57:08 PM PDT 24
Peak memory 216188 kb
Host smart-666ef85d-6ff5-477e-aa60-a169ae8134ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124422665 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4124422665
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3050417588
Short name T88
Test name
Test status
Simulation time 53771726 ps
CPU time 1.12 seconds
Started Mar 19 02:56:54 PM PDT 24
Finished Mar 19 02:56:56 PM PDT 24
Peak memory 217952 kb
Host smart-74954a68-feb7-43a0-bffb-44fe805c696d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050417588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3050417588
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.333405605
Short name T13
Test name
Test status
Simulation time 24495299 ps
CPU time 1.28 seconds
Started Mar 19 02:56:55 PM PDT 24
Finished Mar 19 02:56:57 PM PDT 24
Peak memory 230032 kb
Host smart-6393abe0-d621-4f3e-be1c-443fbb4bc2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333405605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.333405605
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2864258186
Short name T300
Test name
Test status
Simulation time 86839764 ps
CPU time 1.21 seconds
Started Mar 19 02:56:56 PM PDT 24
Finished Mar 19 02:56:57 PM PDT 24
Peak memory 216856 kb
Host smart-6cdc53ac-cd68-48c0-ae33-61244688b5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864258186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2864258186
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2402938080
Short name T145
Test name
Test status
Simulation time 24706506 ps
CPU time 0.96 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:57:00 PM PDT 24
Peak memory 215920 kb
Host smart-eba66d8a-6fde-4dd0-9e84-6aee999ab712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402938080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2402938080
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3853074259
Short name T501
Test name
Test status
Simulation time 41205077 ps
CPU time 0.87 seconds
Started Mar 19 02:56:56 PM PDT 24
Finished Mar 19 02:56:57 PM PDT 24
Peak memory 207240 kb
Host smart-439628cb-c5c9-445d-a5a1-9851f8141b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853074259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3853074259
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2375120057
Short name T723
Test name
Test status
Simulation time 100550091 ps
CPU time 2.43 seconds
Started Mar 19 02:56:56 PM PDT 24
Finished Mar 19 02:56:58 PM PDT 24
Peak memory 216668 kb
Host smart-c99ee3d8-f708-406a-8994-a9044574f4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375120057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2375120057
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1514782540
Short name T483
Test name
Test status
Simulation time 30488189789 ps
CPU time 803.56 seconds
Started Mar 19 02:56:57 PM PDT 24
Finished Mar 19 03:10:21 PM PDT 24
Peak memory 218568 kb
Host smart-18979f80-1fac-4a63-9934-543de6c4b1ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514782540 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1514782540
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2278336076
Short name T273
Test name
Test status
Simulation time 98939735 ps
CPU time 1.33 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 215860 kb
Host smart-54a5b58d-40f1-4558-9221-c66a97914df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278336076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2278336076
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.262314019
Short name T383
Test name
Test status
Simulation time 15096893 ps
CPU time 1 seconds
Started Mar 19 02:57:00 PM PDT 24
Finished Mar 19 02:57:01 PM PDT 24
Peak memory 206184 kb
Host smart-eb76a66f-b205-4600-9d27-4b72a8f983e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262314019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.262314019
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.351975313
Short name T201
Test name
Test status
Simulation time 24403721 ps
CPU time 0.94 seconds
Started Mar 19 02:57:02 PM PDT 24
Finished Mar 19 02:57:03 PM PDT 24
Peak memory 215960 kb
Host smart-e7e5fc6d-4255-49ae-bab4-71461d695e3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351975313 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.351975313
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1822934038
Short name T736
Test name
Test status
Simulation time 128813229 ps
CPU time 1.23 seconds
Started Mar 19 02:57:07 PM PDT 24
Finished Mar 19 02:57:09 PM PDT 24
Peak memory 219000 kb
Host smart-f3997683-3e31-455d-9174-019393eceba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822934038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1822934038
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3667855330
Short name T455
Test name
Test status
Simulation time 34798932 ps
CPU time 1 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:57:00 PM PDT 24
Peak memory 219296 kb
Host smart-5b52182a-76b0-4b6b-80b2-43bbeb85f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667855330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3667855330
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.455557900
Short name T147
Test name
Test status
Simulation time 36464720 ps
CPU time 1.35 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:09 PM PDT 24
Peak memory 218072 kb
Host smart-910b306f-ca64-420b-8511-c05745da3785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455557900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.455557900
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1226793404
Short name T708
Test name
Test status
Simulation time 23700964 ps
CPU time 1.08 seconds
Started Mar 19 02:56:59 PM PDT 24
Finished Mar 19 02:57:00 PM PDT 24
Peak memory 224104 kb
Host smart-70587f55-8625-4b2c-8d36-78b4a6b77c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226793404 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1226793404
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1436292625
Short name T412
Test name
Test status
Simulation time 27068842 ps
CPU time 0.94 seconds
Started Mar 19 02:56:58 PM PDT 24
Finished Mar 19 02:56:59 PM PDT 24
Peak memory 215468 kb
Host smart-4442f22f-9d55-472f-8ab3-069d9f82f6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436292625 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1436292625
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1899154992
Short name T146
Test name
Test status
Simulation time 230882075 ps
CPU time 2.84 seconds
Started Mar 19 02:57:02 PM PDT 24
Finished Mar 19 02:57:05 PM PDT 24
Peak memory 219188 kb
Host smart-5e67b054-c1e1-4814-a9b1-582bd80802bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899154992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1899154992
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.3196276881
Short name T17
Test name
Test status
Simulation time 149489307 ps
CPU time 1.2 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 215780 kb
Host smart-a8b61713-6b5c-44e4-86e1-b4395d4e8ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196276881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3196276881
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.362223532
Short name T692
Test name
Test status
Simulation time 33116784 ps
CPU time 0.84 seconds
Started Mar 19 02:57:11 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 206768 kb
Host smart-dcc28f2c-9444-4736-94f7-31544227ca9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362223532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.362223532
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3749115533
Short name T181
Test name
Test status
Simulation time 18286448 ps
CPU time 0.85 seconds
Started Mar 19 02:56:59 PM PDT 24
Finished Mar 19 02:57:00 PM PDT 24
Peak memory 215960 kb
Host smart-69dd3dac-a654-497e-98ad-df6fb7e9e74b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749115533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3749115533
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.942821394
Short name T6
Test name
Test status
Simulation time 40384598 ps
CPU time 0.9 seconds
Started Mar 19 02:57:04 PM PDT 24
Finished Mar 19 02:57:05 PM PDT 24
Peak memory 219588 kb
Host smart-7aa370fa-498b-45a2-9260-494f8d7d0da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942821394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.942821394
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3253998918
Short name T261
Test name
Test status
Simulation time 49399733 ps
CPU time 1.28 seconds
Started Mar 19 02:57:00 PM PDT 24
Finished Mar 19 02:57:02 PM PDT 24
Peak memory 216668 kb
Host smart-6e6a0857-4924-4672-af66-bf5292e57966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253998918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3253998918
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1905918606
Short name T688
Test name
Test status
Simulation time 49447771 ps
CPU time 0.94 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:09 PM PDT 24
Peak memory 223880 kb
Host smart-3308e858-7061-4b6e-b482-56e488e24cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905918606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1905918606
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2424970383
Short name T836
Test name
Test status
Simulation time 57898796 ps
CPU time 0.86 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 215388 kb
Host smart-d84241c4-e9d6-403f-a501-de3cb94f7661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424970383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2424970383
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1567925251
Short name T221
Test name
Test status
Simulation time 97551897 ps
CPU time 1.13 seconds
Started Mar 19 02:57:00 PM PDT 24
Finished Mar 19 02:57:02 PM PDT 24
Peak memory 215380 kb
Host smart-b5daa5af-6516-41cd-a4e1-b3cd67585a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567925251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1567925251
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3872792961
Short name T513
Test name
Test status
Simulation time 58843690953 ps
CPU time 640.92 seconds
Started Mar 19 02:57:11 PM PDT 24
Finished Mar 19 03:07:52 PM PDT 24
Peak memory 218576 kb
Host smart-12035aad-d481-4c82-a02a-df9c2f97f5be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872792961 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3872792961
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2583315484
Short name T275
Test name
Test status
Simulation time 27247515 ps
CPU time 1.28 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 215804 kb
Host smart-1e721b6b-f201-4d34-9f7a-ee3610244568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583315484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2583315484
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2447912811
Short name T667
Test name
Test status
Simulation time 23976283 ps
CPU time 0.96 seconds
Started Mar 19 02:55:55 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 206664 kb
Host smart-9e1a50e9-bfd2-487a-a360-d2c0afa047e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447912811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2447912811
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2149678049
Short name T126
Test name
Test status
Simulation time 113637073 ps
CPU time 0.82 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 215992 kb
Host smart-49d1dba6-c7b3-4f5a-bfaf-2fabbf6329ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149678049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2149678049
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1967853013
Short name T548
Test name
Test status
Simulation time 96920122 ps
CPU time 1.19 seconds
Started Mar 19 02:55:56 PM PDT 24
Finished Mar 19 02:55:57 PM PDT 24
Peak memory 219052 kb
Host smart-f095c3f2-b735-4790-99ed-a256c5bb3ae4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967853013 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1967853013
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.62944078
Short name T65
Test name
Test status
Simulation time 23313447 ps
CPU time 0.88 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 218064 kb
Host smart-fda8cd90-56f1-48f4-a8a0-b3f51a293fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62944078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.62944078
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3845255323
Short name T346
Test name
Test status
Simulation time 56161241 ps
CPU time 1.65 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:54 PM PDT 24
Peak memory 217752 kb
Host smart-64419f90-1624-4488-97c6-030c5bc328d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845255323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3845255323
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.962329703
Short name T626
Test name
Test status
Simulation time 35249187 ps
CPU time 0.9 seconds
Started Mar 19 02:55:56 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 215724 kb
Host smart-620a298d-cf02-42ab-84df-db14ae16adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962329703 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.962329703
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2411055374
Short name T823
Test name
Test status
Simulation time 18343188 ps
CPU time 1.01 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 207240 kb
Host smart-adfcc380-1d5d-4af5-aaad-a90eaca19e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411055374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2411055374
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.512545086
Short name T527
Test name
Test status
Simulation time 38270122 ps
CPU time 0.86 seconds
Started Mar 19 02:55:54 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 215232 kb
Host smart-71604585-7679-4742-9fe9-8839f82bf719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512545086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.512545086
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3472293427
Short name T722
Test name
Test status
Simulation time 1115412701 ps
CPU time 2.42 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:54 PM PDT 24
Peak memory 215400 kb
Host smart-d99f1e35-3988-4126-a859-7b0ccb7992be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472293427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3472293427
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2706132575
Short name T556
Test name
Test status
Simulation time 97349464776 ps
CPU time 589.71 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 03:05:42 PM PDT 24
Peak memory 220176 kb
Host smart-ab2dcb61-2f7d-436f-bbe9-5c7a4a59cb58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706132575 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2706132575
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1760000336
Short name T45
Test name
Test status
Simulation time 19713451 ps
CPU time 1.17 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:09 PM PDT 24
Peak memory 223208 kb
Host smart-a2dc7c0c-6ecd-4cfb-8688-3d89da74d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760000336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1760000336
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3056609171
Short name T815
Test name
Test status
Simulation time 88148649 ps
CPU time 1.31 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 218580 kb
Host smart-bf61c04e-ffc3-492c-839c-ce6683642514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056609171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3056609171
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3225835223
Short name T678
Test name
Test status
Simulation time 34651335 ps
CPU time 1.2 seconds
Started Mar 19 02:56:56 PM PDT 24
Finished Mar 19 02:56:58 PM PDT 24
Peak memory 219388 kb
Host smart-4f64b175-cf25-49c6-bf71-083ddce19382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225835223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3225835223
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2939646249
Short name T780
Test name
Test status
Simulation time 92883778 ps
CPU time 1.47 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:15 PM PDT 24
Peak memory 218124 kb
Host smart-1124d461-0327-475b-a86d-7e188009f59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939646249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2939646249
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2883347207
Short name T43
Test name
Test status
Simulation time 23346887 ps
CPU time 1.25 seconds
Started Mar 19 02:57:06 PM PDT 24
Finished Mar 19 02:57:07 PM PDT 24
Peak memory 229740 kb
Host smart-38e9b862-24d9-4421-9923-a3de84035939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883347207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2883347207
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3576051756
Short name T510
Test name
Test status
Simulation time 51104211 ps
CPU time 2.02 seconds
Started Mar 19 02:57:06 PM PDT 24
Finished Mar 19 02:57:08 PM PDT 24
Peak memory 219612 kb
Host smart-861ffd63-14be-48c0-a1ec-7e19ac930091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576051756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3576051756
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3589578132
Short name T679
Test name
Test status
Simulation time 27900597 ps
CPU time 1.26 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 220060 kb
Host smart-9deb3a73-0681-4f49-9a9a-c1815c0b644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589578132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3589578132
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2006999502
Short name T545
Test name
Test status
Simulation time 44127833 ps
CPU time 1.4 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 216368 kb
Host smart-f9a8d94f-05b7-4a33-b2a6-22b5f869db1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006999502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2006999502
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.357770237
Short name T554
Test name
Test status
Simulation time 24774838 ps
CPU time 0.94 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 218144 kb
Host smart-a8421706-ee84-4032-8b85-6ce7878d0f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357770237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.357770237
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2652153899
Short name T51
Test name
Test status
Simulation time 31516595 ps
CPU time 1.25 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 217696 kb
Host smart-cf28491c-e728-4f34-a075-3965ab3ee973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652153899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2652153899
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1586815727
Short name T92
Test name
Test status
Simulation time 73853383 ps
CPU time 1.18 seconds
Started Mar 19 02:57:03 PM PDT 24
Finished Mar 19 02:57:05 PM PDT 24
Peak memory 231380 kb
Host smart-70bbf27a-01e4-42a3-ac17-0bc485309a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586815727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1586815727
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2362843122
Short name T293
Test name
Test status
Simulation time 4363684436 ps
CPU time 87.13 seconds
Started Mar 19 02:57:01 PM PDT 24
Finished Mar 19 02:58:28 PM PDT 24
Peak memory 220288 kb
Host smart-8be4a02d-b263-4b08-8755-88391a8c2a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362843122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2362843122
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.664356795
Short name T719
Test name
Test status
Simulation time 18052196 ps
CPU time 1.05 seconds
Started Mar 19 02:57:06 PM PDT 24
Finished Mar 19 02:57:07 PM PDT 24
Peak memory 218096 kb
Host smart-61b22416-fbd2-447e-b42c-8cd5b12a4b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664356795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.664356795
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1099364951
Short name T333
Test name
Test status
Simulation time 218220493 ps
CPU time 1.83 seconds
Started Mar 19 02:57:10 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 218264 kb
Host smart-510243db-3012-4a4d-9698-46a9f4013f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099364951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1099364951
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2941511645
Short name T834
Test name
Test status
Simulation time 34232684 ps
CPU time 0.85 seconds
Started Mar 19 02:57:10 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 218136 kb
Host smart-b1410c81-235f-4558-b87f-e6c5b8bc42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941511645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2941511645
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3464921598
Short name T522
Test name
Test status
Simulation time 30965004 ps
CPU time 1.35 seconds
Started Mar 19 02:57:18 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 218084 kb
Host smart-5984ebda-b104-430e-8b73-1859fed6e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464921598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3464921598
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.4178641103
Short name T87
Test name
Test status
Simulation time 20394331 ps
CPU time 1.11 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 219524 kb
Host smart-32bc1947-b724-44b8-ab45-49f671b31010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178641103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4178641103
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4075474491
Short name T401
Test name
Test status
Simulation time 62937466 ps
CPU time 1.13 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 219680 kb
Host smart-8ad2f7bb-77ac-499f-be6a-3723c49af291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075474491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4075474491
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1070394315
Short name T121
Test name
Test status
Simulation time 23745258 ps
CPU time 0.97 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 218348 kb
Host smart-0e043242-52d2-4222-b2d0-6158e5638868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070394315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1070394315
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2271673659
Short name T528
Test name
Test status
Simulation time 45863933 ps
CPU time 1.61 seconds
Started Mar 19 02:57:03 PM PDT 24
Finished Mar 19 02:57:05 PM PDT 24
Peak memory 218180 kb
Host smart-339a464c-ea94-4ccb-8cf0-97e354d0af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271673659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2271673659
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.747063737
Short name T163
Test name
Test status
Simulation time 45403068 ps
CPU time 1.18 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:54 PM PDT 24
Peak memory 215780 kb
Host smart-205d840b-63be-49ac-a770-305a97edb1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747063737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.747063737
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1454740507
Short name T568
Test name
Test status
Simulation time 23624020 ps
CPU time 0.92 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 206980 kb
Host smart-538036a9-e75f-4d4c-88be-7518ce555dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454740507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1454740507
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4225542894
Short name T166
Test name
Test status
Simulation time 16103470 ps
CPU time 0.84 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 216052 kb
Host smart-2a4c5f66-ad0d-43d6-97e1-ab985d3ce1aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225542894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4225542894
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.4028292745
Short name T106
Test name
Test status
Simulation time 23571515 ps
CPU time 0.9 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 217932 kb
Host smart-569d68f4-7099-419f-9167-3e46125fded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028292745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4028292745
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3554201884
Short name T711
Test name
Test status
Simulation time 57483576 ps
CPU time 1.58 seconds
Started Mar 19 02:55:49 PM PDT 24
Finished Mar 19 02:55:51 PM PDT 24
Peak memory 219192 kb
Host smart-8d273313-c629-478a-8c44-b76e8ea09b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554201884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3554201884
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1865747066
Short name T629
Test name
Test status
Simulation time 48912016 ps
CPU time 0.94 seconds
Started Mar 19 02:55:51 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 223872 kb
Host smart-7c2da0bc-bc5b-4ada-b9e2-e7e572af2b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865747066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1865747066
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.509891305
Short name T269
Test name
Test status
Simulation time 16674587 ps
CPU time 0.97 seconds
Started Mar 19 02:55:55 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 207224 kb
Host smart-72d48807-26b6-45ee-9709-63be767b0d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509891305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.509891305
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2808443944
Short name T217
Test name
Test status
Simulation time 15028992 ps
CPU time 0.97 seconds
Started Mar 19 02:55:51 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 215404 kb
Host smart-412173c9-69f3-4f30-ae64-bfd4271c22f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808443944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2808443944
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2124661748
Short name T729
Test name
Test status
Simulation time 297382773 ps
CPU time 2.1 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 216568 kb
Host smart-6f5c14fe-e9f0-4aab-b936-79a23b40c415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124661748 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2124661748
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1561491634
Short name T632
Test name
Test status
Simulation time 117088190543 ps
CPU time 651.92 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 223944 kb
Host smart-6e8b2551-ba60-4658-b515-6b7308774144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561491634 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1561491634
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1723172084
Short name T343
Test name
Test status
Simulation time 19830722 ps
CPU time 1.07 seconds
Started Mar 19 02:57:10 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 218248 kb
Host smart-ff55b779-4af3-4178-8058-1d07b0b84c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723172084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1723172084
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1993644600
Short name T560
Test name
Test status
Simulation time 58870078 ps
CPU time 1.25 seconds
Started Mar 19 02:57:11 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 218108 kb
Host smart-71477621-3ec9-46bb-a83e-bbb49112ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993644600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1993644600
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2553788777
Short name T752
Test name
Test status
Simulation time 35063479 ps
CPU time 0.92 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 217984 kb
Host smart-22bb55af-23df-4266-a627-9d8e8b62731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553788777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2553788777
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.432418575
Short name T444
Test name
Test status
Simulation time 76622585 ps
CPU time 1.24 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 216948 kb
Host smart-c29072e6-ee2f-443e-810f-7f91fbbe86da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432418575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.432418575
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.397497005
Short name T530
Test name
Test status
Simulation time 100721255 ps
CPU time 1.09 seconds
Started Mar 19 02:57:17 PM PDT 24
Finished Mar 19 02:57:19 PM PDT 24
Peak memory 232608 kb
Host smart-70fad0cc-904c-4a0b-927b-3df0cef6b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397497005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.397497005
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1025594451
Short name T654
Test name
Test status
Simulation time 122266818 ps
CPU time 2.7 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 219156 kb
Host smart-f3f2a333-e98d-4f80-b0dc-3412c36267d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025594451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1025594451
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.72491081
Short name T74
Test name
Test status
Simulation time 179647563 ps
CPU time 1.09 seconds
Started Mar 19 02:57:01 PM PDT 24
Finished Mar 19 02:57:03 PM PDT 24
Peak memory 229920 kb
Host smart-23a85ccf-7f9b-42dd-845b-0c26d665daa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72491081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.72491081
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.118725821
Short name T297
Test name
Test status
Simulation time 61431688 ps
CPU time 1.1 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 218096 kb
Host smart-e069ba4e-e3a9-4448-a537-ae7d28d200aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118725821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.118725821
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2538895533
Short name T267
Test name
Test status
Simulation time 25357875 ps
CPU time 0.97 seconds
Started Mar 19 02:57:04 PM PDT 24
Finished Mar 19 02:57:05 PM PDT 24
Peak memory 218364 kb
Host smart-487ad114-0330-4f2c-98a2-4783e5bed301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538895533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2538895533
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3746794849
Short name T21
Test name
Test status
Simulation time 46554712 ps
CPU time 1.2 seconds
Started Mar 19 02:57:01 PM PDT 24
Finished Mar 19 02:57:03 PM PDT 24
Peak memory 218280 kb
Host smart-7e39acd3-fc15-43f0-b00e-cf08c99fed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746794849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3746794849
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1410147428
Short name T7
Test name
Test status
Simulation time 39961289 ps
CPU time 1.18 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 219988 kb
Host smart-6e4330ee-c576-42f1-9700-fea467713f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410147428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1410147428
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3707394341
Short name T375
Test name
Test status
Simulation time 42687669 ps
CPU time 1.55 seconds
Started Mar 19 02:57:04 PM PDT 24
Finished Mar 19 02:57:06 PM PDT 24
Peak memory 218088 kb
Host smart-86b33b1b-e538-47d8-a741-fc25be39aba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707394341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3707394341
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.296312226
Short name T95
Test name
Test status
Simulation time 33069997 ps
CPU time 1.05 seconds
Started Mar 19 02:57:01 PM PDT 24
Finished Mar 19 02:57:02 PM PDT 24
Peak memory 216808 kb
Host smart-c094e1c2-0a9d-4061-9ef6-206da1c1abfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296312226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.296312226
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.2962878748
Short name T83
Test name
Test status
Simulation time 37963270 ps
CPU time 1.24 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 229808 kb
Host smart-0ed62b83-d3e2-4550-a316-fd508d1085fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962878748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2962878748
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4177740347
Short name T41
Test name
Test status
Simulation time 174785672 ps
CPU time 1.17 seconds
Started Mar 19 02:57:06 PM PDT 24
Finished Mar 19 02:57:07 PM PDT 24
Peak memory 216784 kb
Host smart-afdd13ae-511d-439e-aec0-62931dbd5bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177740347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4177740347
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1207515000
Short name T176
Test name
Test status
Simulation time 18879484 ps
CPU time 1.1 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:16 PM PDT 24
Peak memory 218252 kb
Host smart-9b17a1b6-8ff6-4fa0-a8ec-4719f33df6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207515000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1207515000
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3655548845
Short name T832
Test name
Test status
Simulation time 238386291 ps
CPU time 3.24 seconds
Started Mar 19 02:57:07 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 218512 kb
Host smart-b531b774-7032-4059-8c42-8573a1e810ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655548845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3655548845
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2927915485
Short name T520
Test name
Test status
Simulation time 42301469 ps
CPU time 0.84 seconds
Started Mar 19 02:57:07 PM PDT 24
Finished Mar 19 02:57:08 PM PDT 24
Peak memory 217880 kb
Host smart-77585436-5e9c-4c48-9ff6-a47e396a8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927915485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2927915485
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2928101959
Short name T286
Test name
Test status
Simulation time 52149152 ps
CPU time 1.42 seconds
Started Mar 19 02:57:02 PM PDT 24
Finished Mar 19 02:57:04 PM PDT 24
Peak memory 218112 kb
Host smart-bad9f074-b350-43c8-b4ef-5d049deb9ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928101959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2928101959
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1738410322
Short name T156
Test name
Test status
Simulation time 46403540 ps
CPU time 1.15 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 215792 kb
Host smart-1b2150a8-006e-4461-8521-db4a51972174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738410322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1738410322
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2793384709
Short name T462
Test name
Test status
Simulation time 57239822 ps
CPU time 0.85 seconds
Started Mar 19 02:55:57 PM PDT 24
Finished Mar 19 02:55:58 PM PDT 24
Peak memory 206720 kb
Host smart-34e022ab-8674-4708-bcbb-2828ea0d5759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793384709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2793384709
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.892029701
Short name T179
Test name
Test status
Simulation time 17471847 ps
CPU time 0.86 seconds
Started Mar 19 02:55:55 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 216048 kb
Host smart-cdc30483-00a8-4d0b-a5ac-d526b91ca073
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892029701 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.892029701
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1874005790
Short name T493
Test name
Test status
Simulation time 99235678 ps
CPU time 0.99 seconds
Started Mar 19 02:55:51 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 216492 kb
Host smart-91554507-eb99-4f37-a8aa-ec557d28f8bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874005790 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1874005790
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1017019091
Short name T188
Test name
Test status
Simulation time 35471620 ps
CPU time 0.94 seconds
Started Mar 19 02:55:55 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 218056 kb
Host smart-30c4f282-bbe7-4402-9607-04a6ac2dc361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017019091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1017019091
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.4245583333
Short name T713
Test name
Test status
Simulation time 25411634 ps
CPU time 1.08 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 224084 kb
Host smart-e51f73f8-2c58-47fa-9d3d-5bf0f1491a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245583333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4245583333
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2007874088
Short name T271
Test name
Test status
Simulation time 41305658 ps
CPU time 0.9 seconds
Started Mar 19 02:55:55 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 207212 kb
Host smart-71290efd-1caa-407e-b45f-c04a2c15b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007874088 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2007874088
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.748525460
Short name T600
Test name
Test status
Simulation time 43709371 ps
CPU time 0.91 seconds
Started Mar 19 02:55:50 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 215476 kb
Host smart-9a17da70-6e26-435c-a56d-91efa9656be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748525460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.748525460
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.972369932
Short name T809
Test name
Test status
Simulation time 132270929 ps
CPU time 2.03 seconds
Started Mar 19 02:55:52 PM PDT 24
Finished Mar 19 02:55:54 PM PDT 24
Peak memory 215464 kb
Host smart-c5096a4c-beae-4a84-aece-21af890cff9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972369932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.972369932
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3895764568
Short name T511
Test name
Test status
Simulation time 54574773113 ps
CPU time 1237.91 seconds
Started Mar 19 02:55:54 PM PDT 24
Finished Mar 19 03:16:32 PM PDT 24
Peak memory 221128 kb
Host smart-8953696d-24a6-4bfc-b6cb-fbf8256408fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895764568 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3895764568
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1300656855
Short name T183
Test name
Test status
Simulation time 24948071 ps
CPU time 1.1 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 232600 kb
Host smart-eed3f421-3e70-4d82-a637-9ab98ec14000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300656855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1300656855
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3823050184
Short name T314
Test name
Test status
Simulation time 4844581348 ps
CPU time 90.77 seconds
Started Mar 19 02:57:19 PM PDT 24
Finished Mar 19 02:58:50 PM PDT 24
Peak memory 220332 kb
Host smart-e155a887-dcf9-4981-a11e-603700f66587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823050184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3823050184
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3919191703
Short name T438
Test name
Test status
Simulation time 34790335 ps
CPU time 1.11 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 220240 kb
Host smart-f741c89b-c919-4836-8473-256a80353b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919191703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3919191703
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1167546624
Short name T328
Test name
Test status
Simulation time 88053241 ps
CPU time 1.99 seconds
Started Mar 19 02:57:05 PM PDT 24
Finished Mar 19 02:57:07 PM PDT 24
Peak memory 218092 kb
Host smart-4d42c121-5a06-43ab-99b1-d5ce4624040d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167546624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1167546624
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1945363708
Short name T367
Test name
Test status
Simulation time 24740985 ps
CPU time 0.88 seconds
Started Mar 19 02:57:19 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 217672 kb
Host smart-c32a2ae0-d523-430a-959c-6797e894b38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945363708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1945363708
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.140311561
Short name T403
Test name
Test status
Simulation time 56528153 ps
CPU time 1.37 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 218200 kb
Host smart-8e6d23a3-8408-4555-8a2e-afeac51c5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140311561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.140311561
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3332790230
Short name T647
Test name
Test status
Simulation time 44986472 ps
CPU time 0.88 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:15 PM PDT 24
Peak memory 217832 kb
Host smart-6f43686c-64fd-4be0-a67e-ce8369fe2f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332790230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3332790230
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3809091694
Short name T298
Test name
Test status
Simulation time 138154711 ps
CPU time 1.93 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:18 PM PDT 24
Peak memory 216932 kb
Host smart-ffd7d228-9286-4a34-a128-2a365d110098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809091694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3809091694
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.719478086
Short name T696
Test name
Test status
Simulation time 55362455 ps
CPU time 0.86 seconds
Started Mar 19 02:57:11 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 215252 kb
Host smart-79ff9324-20e2-46db-82e9-51ac8aabfe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719478086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.719478086
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2078541792
Short name T352
Test name
Test status
Simulation time 86998080 ps
CPU time 1.22 seconds
Started Mar 19 02:57:06 PM PDT 24
Finished Mar 19 02:57:08 PM PDT 24
Peak memory 217000 kb
Host smart-611069af-1fe9-48b1-b26d-7c9cee66304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078541792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2078541792
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1893113951
Short name T73
Test name
Test status
Simulation time 24038797 ps
CPU time 1.3 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:09 PM PDT 24
Peak memory 220284 kb
Host smart-71852fdc-fe21-4b65-a7c1-38e7d6eac554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893113951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1893113951
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3478821093
Short name T622
Test name
Test status
Simulation time 63658538 ps
CPU time 1.09 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 218936 kb
Host smart-19876a36-6ab6-4162-aeaf-79d8b33df08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478821093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3478821093
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.312886983
Short name T509
Test name
Test status
Simulation time 99110998 ps
CPU time 1.05 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 231428 kb
Host smart-7bf22e8b-45ce-40cf-9a9c-837c3bb0a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312886983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.312886983
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1008228099
Short name T362
Test name
Test status
Simulation time 87410196 ps
CPU time 1.46 seconds
Started Mar 19 02:57:10 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 217916 kb
Host smart-0d8aa3ec-391b-493c-aeb2-6a426b17191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008228099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1008228099
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.332061617
Short name T85
Test name
Test status
Simulation time 35940775 ps
CPU time 0.91 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 219120 kb
Host smart-7235edad-f1f8-487a-bdc0-ddec20f1745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332061617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.332061617
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.780421310
Short name T316
Test name
Test status
Simulation time 39630234 ps
CPU time 1.43 seconds
Started Mar 19 02:57:17 PM PDT 24
Finished Mar 19 02:57:18 PM PDT 24
Peak memory 216792 kb
Host smart-2200cfc5-244c-4e33-98a9-f82a3867319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780421310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.780421310
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2331219878
Short name T758
Test name
Test status
Simulation time 57115177 ps
CPU time 1.14 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 219472 kb
Host smart-cbaa76ad-fc86-40f5-af3f-bea2ec3d44b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331219878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2331219878
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2418924946
Short name T308
Test name
Test status
Simulation time 95343276 ps
CPU time 2.35 seconds
Started Mar 19 02:57:26 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 218028 kb
Host smart-17532d1e-6f25-4727-926b-c6b64851d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418924946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2418924946
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2172949108
Short name T96
Test name
Test status
Simulation time 31643897 ps
CPU time 1.05 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:28 PM PDT 24
Peak memory 219364 kb
Host smart-254e8ac6-4964-460e-994c-ad69f79ffc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172949108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2172949108
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.950380513
Short name T649
Test name
Test status
Simulation time 80491933 ps
CPU time 1.2 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 216652 kb
Host smart-2a198ac0-91c3-451e-a6d4-180da6d7c8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950380513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.950380513
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1442552112
Short name T274
Test name
Test status
Simulation time 24700758 ps
CPU time 1.2 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:05 PM PDT 24
Peak memory 215784 kb
Host smart-b9306610-3bd9-46ff-82a1-e0c9ae916581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442552112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1442552112
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2143680314
Short name T59
Test name
Test status
Simulation time 26299579 ps
CPU time 0.9 seconds
Started Mar 19 02:56:02 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 206220 kb
Host smart-00c424da-ecb1-4250-abc1-432288935b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143680314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2143680314
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1249591624
Short name T61
Test name
Test status
Simulation time 106993410 ps
CPU time 1.19 seconds
Started Mar 19 02:55:57 PM PDT 24
Finished Mar 19 02:55:58 PM PDT 24
Peak memory 216680 kb
Host smart-6b780402-aa17-48a9-83a8-1f0990b2b23d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249591624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1249591624
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.24358764
Short name T79
Test name
Test status
Simulation time 22816193 ps
CPU time 1.22 seconds
Started Mar 19 02:56:08 PM PDT 24
Finished Mar 19 02:56:10 PM PDT 24
Peak memory 219284 kb
Host smart-961ea4f1-4a12-4ab9-b9cd-9b6130fdbb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24358764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.24358764
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3267680549
Short name T365
Test name
Test status
Simulation time 50554623 ps
CPU time 1.79 seconds
Started Mar 19 02:55:57 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 218256 kb
Host smart-894b7453-cd2d-42c9-8374-5fdc1dbc5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267680549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3267680549
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2409969030
Short name T394
Test name
Test status
Simulation time 26416668 ps
CPU time 1.3 seconds
Started Mar 19 02:55:57 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 224124 kb
Host smart-7fd60293-4a57-4016-bb4a-bef915f516eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409969030 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2409969030
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.551107957
Short name T518
Test name
Test status
Simulation time 126262388 ps
CPU time 0.87 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 215704 kb
Host smart-f3dbf27a-3b93-4f3f-a700-01067e86fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551107957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.551107957
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3631740547
Short name T389
Test name
Test status
Simulation time 160850189 ps
CPU time 2.1 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:05 PM PDT 24
Peak memory 215424 kb
Host smart-5bc9333b-cb9b-4ff1-8deb-9567c9c2c023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631740547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3631740547
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.584456588
Short name T630
Test name
Test status
Simulation time 300679598794 ps
CPU time 1797.91 seconds
Started Mar 19 02:56:08 PM PDT 24
Finished Mar 19 03:26:07 PM PDT 24
Peak memory 224752 kb
Host smart-1c5baecd-8c56-4a9b-94df-7ac7cdca537a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584456588 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.584456588
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3851077123
Short name T777
Test name
Test status
Simulation time 32372212 ps
CPU time 0.88 seconds
Started Mar 19 02:57:11 PM PDT 24
Finished Mar 19 02:57:13 PM PDT 24
Peak memory 218288 kb
Host smart-e2130253-66cb-4d7b-b98a-d3b2e1361f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851077123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3851077123
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1363417701
Short name T500
Test name
Test status
Simulation time 94626198 ps
CPU time 1.2 seconds
Started Mar 19 02:57:08 PM PDT 24
Finished Mar 19 02:57:10 PM PDT 24
Peak memory 216844 kb
Host smart-62715f7e-f5f3-4d2d-bc78-88cdf0e3ff75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363417701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1363417701
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2013089732
Short name T477
Test name
Test status
Simulation time 94186864 ps
CPU time 0.81 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 217948 kb
Host smart-dda5e5b7-741d-42f6-8424-c1237bb64bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013089732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2013089732
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1585915767
Short name T765
Test name
Test status
Simulation time 90215427 ps
CPU time 1.21 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 218260 kb
Host smart-a5f3542d-af98-4000-b122-6246c2cef0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585915767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1585915767
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2094845409
Short name T837
Test name
Test status
Simulation time 27510613 ps
CPU time 0.91 seconds
Started Mar 19 02:57:09 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 217716 kb
Host smart-894e18c4-d63e-4477-8cf3-814a54d0cc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094845409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2094845409
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4229145468
Short name T402
Test name
Test status
Simulation time 107542372 ps
CPU time 1.69 seconds
Started Mar 19 02:57:27 PM PDT 24
Finished Mar 19 02:57:29 PM PDT 24
Peak memory 218088 kb
Host smart-8311d8c7-bdf5-4d4d-9e35-475dfab7ae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229145468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4229145468
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3558869225
Short name T54
Test name
Test status
Simulation time 29436682 ps
CPU time 1.22 seconds
Started Mar 19 02:57:17 PM PDT 24
Finished Mar 19 02:57:19 PM PDT 24
Peak memory 219352 kb
Host smart-55d73c5b-9eb7-4b7e-a3ce-26c485dc8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558869225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3558869225
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1633102065
Short name T594
Test name
Test status
Simulation time 161872002 ps
CPU time 1.67 seconds
Started Mar 19 02:57:30 PM PDT 24
Finished Mar 19 02:57:31 PM PDT 24
Peak memory 218436 kb
Host smart-c6f62115-7633-4d2d-9ba1-ee6182be96f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633102065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1633102065
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3292905611
Short name T361
Test name
Test status
Simulation time 32433364 ps
CPU time 0.87 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:13 PM PDT 24
Peak memory 218156 kb
Host smart-1df6b6cc-6059-4acb-bd65-2ed2f5f18d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292905611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3292905611
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3552437544
Short name T411
Test name
Test status
Simulation time 94333296 ps
CPU time 1.19 seconds
Started Mar 19 02:57:10 PM PDT 24
Finished Mar 19 02:57:12 PM PDT 24
Peak memory 216840 kb
Host smart-b0b73504-1b66-4a27-9de0-80c47a6b2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552437544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3552437544
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.4261479851
Short name T180
Test name
Test status
Simulation time 18953601 ps
CPU time 1.06 seconds
Started Mar 19 02:57:15 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 218068 kb
Host smart-e1cfb88b-8da2-4fbd-a4f3-6bf3246808f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261479851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4261479851
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2456994502
Short name T506
Test name
Test status
Simulation time 248742516 ps
CPU time 1.1 seconds
Started Mar 19 02:57:14 PM PDT 24
Finished Mar 19 02:57:16 PM PDT 24
Peak memory 216708 kb
Host smart-42b3bad8-365e-4164-83aa-5de3b92717b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456994502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2456994502
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1499261687
Short name T616
Test name
Test status
Simulation time 44848511 ps
CPU time 1.17 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:13 PM PDT 24
Peak memory 219532 kb
Host smart-fc1cbb83-0da6-4e29-b528-f4526370550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499261687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1499261687
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2066357137
Short name T843
Test name
Test status
Simulation time 128103115 ps
CPU time 1.15 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 216816 kb
Host smart-3fc86a54-dfa9-4a33-8d9a-e290730f964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066357137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2066357137
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3460601851
Short name T589
Test name
Test status
Simulation time 24661651 ps
CPU time 0.91 seconds
Started Mar 19 02:57:23 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 218140 kb
Host smart-fc1cfb42-6ef8-4a2b-8b69-1fb2ad3857a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460601851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3460601851
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2681649066
Short name T757
Test name
Test status
Simulation time 33658573 ps
CPU time 1.28 seconds
Started Mar 19 02:57:28 PM PDT 24
Finished Mar 19 02:57:30 PM PDT 24
Peak memory 217776 kb
Host smart-6a8871d0-a752-4c36-a18e-dbe4fe9fb7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681649066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2681649066
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1511004277
Short name T741
Test name
Test status
Simulation time 57939240 ps
CPU time 0.93 seconds
Started Mar 19 02:57:12 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 219444 kb
Host smart-45d06600-9163-4fff-ad09-a2b4de1ba706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511004277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1511004277
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.106840471
Short name T652
Test name
Test status
Simulation time 58699939 ps
CPU time 1.11 seconds
Started Mar 19 02:57:13 PM PDT 24
Finished Mar 19 02:57:14 PM PDT 24
Peak memory 216904 kb
Host smart-ae9b0549-184a-4148-a3d6-302300f5b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106840471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.106840471
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.639800710
Short name T776
Test name
Test status
Simulation time 47431281 ps
CPU time 0.98 seconds
Started Mar 19 02:57:10 PM PDT 24
Finished Mar 19 02:57:11 PM PDT 24
Peak memory 218336 kb
Host smart-1e914639-c25f-4c72-9d7a-5f8f4cabad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639800710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.639800710
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.330744770
Short name T472
Test name
Test status
Simulation time 89785994 ps
CPU time 1.24 seconds
Started Mar 19 02:57:34 PM PDT 24
Finished Mar 19 02:57:36 PM PDT 24
Peak memory 216924 kb
Host smart-9ac09d61-9501-4f32-9649-c16c45a43e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330744770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.330744770
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3937283983
Short name T682
Test name
Test status
Simulation time 98678339 ps
CPU time 1.09 seconds
Started Mar 19 02:56:02 PM PDT 24
Finished Mar 19 02:56:03 PM PDT 24
Peak memory 215792 kb
Host smart-a94ea314-326b-4958-a3ee-0bd24145d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937283983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3937283983
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1813435496
Short name T544
Test name
Test status
Simulation time 74988287 ps
CPU time 0.88 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 205936 kb
Host smart-e40d4cf8-edd9-4e44-ac77-e5dbcdef5dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813435496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1813435496
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.895129791
Short name T117
Test name
Test status
Simulation time 110718662 ps
CPU time 0.88 seconds
Started Mar 19 02:56:01 PM PDT 24
Finished Mar 19 02:56:02 PM PDT 24
Peak memory 215972 kb
Host smart-018db537-bf8c-4748-a920-e57e14bde0ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895129791 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.895129791
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4092533946
Short name T82
Test name
Test status
Simulation time 150326827 ps
CPU time 1.12 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 02:56:04 PM PDT 24
Peak memory 216508 kb
Host smart-8c26fb8d-2181-4433-a746-94d4b5eafa4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092533946 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4092533946
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1705257220
Short name T14
Test name
Test status
Simulation time 25397150 ps
CPU time 1.31 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:56:00 PM PDT 24
Peak memory 228696 kb
Host smart-227363a5-2341-4076-ad73-4e1b614b4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705257220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1705257220
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1381343081
Short name T564
Test name
Test status
Simulation time 68033998 ps
CPU time 1.28 seconds
Started Mar 19 02:56:00 PM PDT 24
Finished Mar 19 02:56:02 PM PDT 24
Peak memory 216928 kb
Host smart-42a434eb-da96-4a96-847b-4d70fafd7586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381343081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1381343081
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2184644944
Short name T448
Test name
Test status
Simulation time 24936972 ps
CPU time 0.89 seconds
Started Mar 19 02:56:00 PM PDT 24
Finished Mar 19 02:56:01 PM PDT 24
Peak memory 215444 kb
Host smart-624d77e9-bbbc-447a-be8e-b52859cefd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184644944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2184644944
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.962360793
Short name T224
Test name
Test status
Simulation time 64183511 ps
CPU time 0.95 seconds
Started Mar 19 02:55:58 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 215432 kb
Host smart-3ac13be6-0f9f-4939-8a6e-0e6f44f3ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962360793 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.962360793
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4241708780
Short name T670
Test name
Test status
Simulation time 151343170 ps
CPU time 3.18 seconds
Started Mar 19 02:55:59 PM PDT 24
Finished Mar 19 02:56:03 PM PDT 24
Peak memory 219056 kb
Host smart-5159934a-375a-48fe-87b7-f974a8d4a04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241708780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4241708780
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3288986168
Short name T211
Test name
Test status
Simulation time 147055589217 ps
CPU time 659.04 seconds
Started Mar 19 02:56:03 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 219212 kb
Host smart-60bc5780-59c5-43a8-910b-8e003d6c5e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288986168 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3288986168
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3186059495
Short name T644
Test name
Test status
Simulation time 19162372 ps
CPU time 1.13 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 223168 kb
Host smart-98c97bdd-345e-44d5-b793-78eac71f122a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186059495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3186059495
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3410996475
Short name T431
Test name
Test status
Simulation time 128137344 ps
CPU time 2.46 seconds
Started Mar 19 02:57:17 PM PDT 24
Finished Mar 19 02:57:19 PM PDT 24
Peak memory 215448 kb
Host smart-6d61dd50-cfb5-4e0d-af74-52ef06e72b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410996475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3410996475
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.1865876213
Short name T634
Test name
Test status
Simulation time 29982735 ps
CPU time 0.87 seconds
Started Mar 19 02:57:43 PM PDT 24
Finished Mar 19 02:57:44 PM PDT 24
Peak memory 218132 kb
Host smart-2b0f691e-90df-4cf9-a743-912eedcf7fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865876213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1865876213
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3208869622
Short name T671
Test name
Test status
Simulation time 84027724 ps
CPU time 1.33 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 218224 kb
Host smart-bcb74fe2-36b9-4d44-a1e7-57334c17ee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208869622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3208869622
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1119105395
Short name T457
Test name
Test status
Simulation time 21201595 ps
CPU time 1.1 seconds
Started Mar 19 02:57:40 PM PDT 24
Finished Mar 19 02:57:42 PM PDT 24
Peak memory 219292 kb
Host smart-a731c2d9-dae8-451f-a2f5-4e341839d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119105395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1119105395
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1220552247
Short name T698
Test name
Test status
Simulation time 69221516 ps
CPU time 0.98 seconds
Started Mar 19 02:57:39 PM PDT 24
Finished Mar 19 02:57:40 PM PDT 24
Peak memory 217032 kb
Host smart-8290164b-5232-4246-8ee6-5d6a858467a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220552247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1220552247
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3499439944
Short name T99
Test name
Test status
Simulation time 76948568 ps
CPU time 0.99 seconds
Started Mar 19 02:57:30 PM PDT 24
Finished Mar 19 02:57:31 PM PDT 24
Peak memory 220352 kb
Host smart-386d82c3-d108-4d3f-933f-4064ecb77574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499439944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3499439944
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2861618393
Short name T30
Test name
Test status
Simulation time 59247687 ps
CPU time 1.22 seconds
Started Mar 19 02:57:33 PM PDT 24
Finished Mar 19 02:57:34 PM PDT 24
Peak memory 218048 kb
Host smart-2890fc7f-631c-46d8-9c64-4dd1030d31f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861618393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2861618393
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3640690866
Short name T537
Test name
Test status
Simulation time 164008229 ps
CPU time 0.97 seconds
Started Mar 19 02:57:21 PM PDT 24
Finished Mar 19 02:57:22 PM PDT 24
Peak memory 219468 kb
Host smart-945b83b7-ada5-4c1f-a0b6-f9edb6386da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640690866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3640690866
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2260868119
Short name T586
Test name
Test status
Simulation time 67808091 ps
CPU time 1.63 seconds
Started Mar 19 02:57:25 PM PDT 24
Finished Mar 19 02:57:27 PM PDT 24
Peak memory 218232 kb
Host smart-3244d938-c7dd-4c97-bdbd-c5d9ef2cdb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260868119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2260868119
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1600146895
Short name T759
Test name
Test status
Simulation time 18121196 ps
CPU time 1.03 seconds
Started Mar 19 02:57:24 PM PDT 24
Finished Mar 19 02:57:25 PM PDT 24
Peak memory 217948 kb
Host smart-a0a07bb8-064d-477a-b0b8-aa15caf02bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600146895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1600146895
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.145904024
Short name T288
Test name
Test status
Simulation time 37567784 ps
CPU time 1.47 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:22 PM PDT 24
Peak memory 219532 kb
Host smart-ac21f0d9-8e63-4627-9876-59bba9e86e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145904024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.145904024
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3202377582
Short name T116
Test name
Test status
Simulation time 18276243 ps
CPU time 1.07 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 218192 kb
Host smart-f25a433e-cba7-4894-9d54-35cd57841264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202377582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3202377582
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4056412432
Short name T58
Test name
Test status
Simulation time 32935087 ps
CPU time 1 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 216664 kb
Host smart-aafbba0e-e56d-4478-8726-a64a28ee6a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056412432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4056412432
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.728316894
Short name T108
Test name
Test status
Simulation time 22075485 ps
CPU time 0.93 seconds
Started Mar 19 02:57:20 PM PDT 24
Finished Mar 19 02:57:21 PM PDT 24
Peak memory 218224 kb
Host smart-619ffb04-7672-4f2e-8dfd-f1a4da6fa9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728316894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.728316894
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.634906600
Short name T685
Test name
Test status
Simulation time 45279856 ps
CPU time 1.12 seconds
Started Mar 19 02:57:44 PM PDT 24
Finished Mar 19 02:57:45 PM PDT 24
Peak memory 218112 kb
Host smart-53eaa9a9-dd53-429f-83d0-22edf266a04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634906600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.634906600
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1416773325
Short name T72
Test name
Test status
Simulation time 81219914 ps
CPU time 0.98 seconds
Started Mar 19 02:57:17 PM PDT 24
Finished Mar 19 02:57:18 PM PDT 24
Peak memory 219536 kb
Host smart-f0992fca-5ac1-45f9-bb03-a16249fee08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416773325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1416773325
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2289766277
Short name T702
Test name
Test status
Simulation time 134948349 ps
CPU time 1.11 seconds
Started Mar 19 02:57:14 PM PDT 24
Finished Mar 19 02:57:16 PM PDT 24
Peak memory 216712 kb
Host smart-e4852910-eed0-49d4-8800-e51db00c1ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289766277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2289766277
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.732624312
Short name T608
Test name
Test status
Simulation time 19063177 ps
CPU time 1.19 seconds
Started Mar 19 02:57:22 PM PDT 24
Finished Mar 19 02:57:24 PM PDT 24
Peak memory 230532 kb
Host smart-887e3fa0-f501-4841-b8a4-ae1745b96c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732624312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.732624312
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2226796812
Short name T661
Test name
Test status
Simulation time 81550222 ps
CPU time 1.16 seconds
Started Mar 19 02:57:19 PM PDT 24
Finished Mar 19 02:57:20 PM PDT 24
Peak memory 216740 kb
Host smart-268c9eb2-b618-4ca6-ad96-6f8aa98cad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226796812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2226796812
Directory /workspace/99.edn_genbits/latest
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