Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.11 98.27 93.63 96.84 83.24 96.87 96.58 93.35


Total test records in report: 972
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T46 /workspace/coverage/default/2.edn_sec_cm.607773411 Mar 21 01:59:22 PM PDT 24 Mar 21 01:59:26 PM PDT 24 703687409 ps
T793 /workspace/coverage/default/19.edn_genbits.526110508 Mar 21 02:00:18 PM PDT 24 Mar 21 02:00:20 PM PDT 24 46906779 ps
T794 /workspace/coverage/default/264.edn_genbits.356207422 Mar 21 02:02:30 PM PDT 24 Mar 21 02:02:35 PM PDT 24 38893120 ps
T795 /workspace/coverage/default/5.edn_stress_all.668297440 Mar 21 01:59:35 PM PDT 24 Mar 21 01:59:39 PM PDT 24 174888886 ps
T796 /workspace/coverage/default/46.edn_err.2479676273 Mar 21 02:01:28 PM PDT 24 Mar 21 02:01:30 PM PDT 24 35059711 ps
T797 /workspace/coverage/default/109.edn_genbits.3069776178 Mar 21 02:01:53 PM PDT 24 Mar 21 02:01:55 PM PDT 24 41014038 ps
T798 /workspace/coverage/default/47.edn_stress_all.1939756258 Mar 21 02:01:25 PM PDT 24 Mar 21 02:01:29 PM PDT 24 378059371 ps
T799 /workspace/coverage/default/6.edn_smoke.2571817613 Mar 21 01:59:36 PM PDT 24 Mar 21 01:59:37 PM PDT 24 44074308 ps
T163 /workspace/coverage/default/35.edn_disable.2869237618 Mar 21 02:00:58 PM PDT 24 Mar 21 02:00:59 PM PDT 24 16134918 ps
T800 /workspace/coverage/default/21.edn_smoke.2136496182 Mar 21 02:00:31 PM PDT 24 Mar 21 02:00:32 PM PDT 24 55882446 ps
T801 /workspace/coverage/default/34.edn_alert_test.2979757804 Mar 21 02:00:55 PM PDT 24 Mar 21 02:00:56 PM PDT 24 202662736 ps
T802 /workspace/coverage/default/29.edn_genbits.2772094328 Mar 21 02:00:45 PM PDT 24 Mar 21 02:00:47 PM PDT 24 65629463 ps
T803 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1511997296 Mar 21 02:00:36 PM PDT 24 Mar 21 02:09:18 PM PDT 24 80130690775 ps
T137 /workspace/coverage/default/46.edn_intr.556936294 Mar 21 02:01:27 PM PDT 24 Mar 21 02:01:29 PM PDT 24 24012872 ps
T804 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2265730772 Mar 21 02:00:46 PM PDT 24 Mar 21 02:13:41 PM PDT 24 406907341987 ps
T805 /workspace/coverage/default/25.edn_alert.431448690 Mar 21 02:00:32 PM PDT 24 Mar 21 02:00:33 PM PDT 24 27041183 ps
T806 /workspace/coverage/default/23.edn_smoke.726298371 Mar 21 02:00:33 PM PDT 24 Mar 21 02:00:34 PM PDT 24 28747829 ps
T807 /workspace/coverage/default/7.edn_alert.3466988539 Mar 21 01:59:46 PM PDT 24 Mar 21 01:59:49 PM PDT 24 66908859 ps
T808 /workspace/coverage/default/275.edn_genbits.2927685348 Mar 21 02:02:31 PM PDT 24 Mar 21 02:02:35 PM PDT 24 59403681 ps
T809 /workspace/coverage/default/50.edn_genbits.2884872096 Mar 21 02:01:27 PM PDT 24 Mar 21 02:01:29 PM PDT 24 50987892 ps
T810 /workspace/coverage/default/26.edn_smoke.3739694455 Mar 21 02:00:41 PM PDT 24 Mar 21 02:00:42 PM PDT 24 29393500 ps
T811 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1023232737 Mar 21 02:00:18 PM PDT 24 Mar 21 02:09:45 PM PDT 24 41595509882 ps
T812 /workspace/coverage/default/61.edn_err.1162436130 Mar 21 02:01:40 PM PDT 24 Mar 21 02:01:41 PM PDT 24 23170981 ps
T813 /workspace/coverage/default/32.edn_alert.2303593026 Mar 21 02:00:58 PM PDT 24 Mar 21 02:00:59 PM PDT 24 186692493 ps
T814 /workspace/coverage/default/159.edn_genbits.702413142 Mar 21 02:02:14 PM PDT 24 Mar 21 02:02:15 PM PDT 24 60698509 ps
T815 /workspace/coverage/default/5.edn_err.1500175383 Mar 21 01:59:38 PM PDT 24 Mar 21 01:59:40 PM PDT 24 38616264 ps
T816 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1062058529 Mar 21 02:00:30 PM PDT 24 Mar 21 02:11:12 PM PDT 24 107145010995 ps
T817 /workspace/coverage/default/21.edn_disable_auto_req_mode.2265283895 Mar 21 02:00:35 PM PDT 24 Mar 21 02:00:36 PM PDT 24 37211998 ps
T262 /workspace/coverage/default/41.edn_alert.3360218862 Mar 21 02:01:09 PM PDT 24 Mar 21 02:01:10 PM PDT 24 30209176 ps
T818 /workspace/coverage/default/263.edn_genbits.4156211985 Mar 21 02:02:31 PM PDT 24 Mar 21 02:02:35 PM PDT 24 121051092 ps
T819 /workspace/coverage/default/137.edn_genbits.1252844055 Mar 21 02:01:55 PM PDT 24 Mar 21 02:01:56 PM PDT 24 74569819 ps
T820 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.903270628 Mar 21 02:00:41 PM PDT 24 Mar 21 02:13:00 PM PDT 24 61394618485 ps
T821 /workspace/coverage/default/8.edn_intr.874666160 Mar 21 01:59:52 PM PDT 24 Mar 21 01:59:54 PM PDT 24 23961869 ps
T822 /workspace/coverage/default/1.edn_disable.4167725011 Mar 21 01:59:20 PM PDT 24 Mar 21 01:59:21 PM PDT 24 26778488 ps
T823 /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1096587036 Mar 21 02:00:18 PM PDT 24 Mar 21 02:16:44 PM PDT 24 41227370317 ps
T159 /workspace/coverage/default/29.edn_err.2021452683 Mar 21 02:00:44 PM PDT 24 Mar 21 02:00:45 PM PDT 24 19058186 ps
T168 /workspace/coverage/default/47.edn_err.3052602107 Mar 21 02:01:29 PM PDT 24 Mar 21 02:01:30 PM PDT 24 32471026 ps
T824 /workspace/coverage/default/86.edn_genbits.1117345670 Mar 21 02:01:45 PM PDT 24 Mar 21 02:01:46 PM PDT 24 39785147 ps
T825 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2689300876 Mar 21 02:00:05 PM PDT 24 Mar 21 02:22:37 PM PDT 24 61927117017 ps
T826 /workspace/coverage/default/9.edn_alert_test.796567757 Mar 21 02:00:01 PM PDT 24 Mar 21 02:00:03 PM PDT 24 13157264 ps
T827 /workspace/coverage/default/34.edn_genbits.50377190 Mar 21 02:00:58 PM PDT 24 Mar 21 02:00:59 PM PDT 24 55958553 ps
T828 /workspace/coverage/default/19.edn_disable_auto_req_mode.3006421649 Mar 21 02:00:15 PM PDT 24 Mar 21 02:00:17 PM PDT 24 66644923 ps
T829 /workspace/coverage/default/45.edn_stress_all.89876441 Mar 21 02:01:26 PM PDT 24 Mar 21 02:01:29 PM PDT 24 138544565 ps
T830 /workspace/coverage/default/42.edn_disable.393243362 Mar 21 02:01:17 PM PDT 24 Mar 21 02:01:18 PM PDT 24 13671480 ps
T293 /workspace/coverage/default/247.edn_genbits.2285408520 Mar 21 02:02:27 PM PDT 24 Mar 21 02:02:33 PM PDT 24 113018853 ps
T831 /workspace/coverage/default/30.edn_stress_all.580738608 Mar 21 02:00:44 PM PDT 24 Mar 21 02:00:48 PM PDT 24 260584415 ps
T832 /workspace/coverage/default/203.edn_genbits.2278921230 Mar 21 02:02:09 PM PDT 24 Mar 21 02:02:10 PM PDT 24 36543104 ps
T833 /workspace/coverage/default/47.edn_genbits.3394577888 Mar 21 02:01:26 PM PDT 24 Mar 21 02:01:27 PM PDT 24 91169729 ps
T834 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1052919690 Mar 21 02:00:21 PM PDT 24 Mar 21 02:03:25 PM PDT 24 15033905615 ps
T835 /workspace/coverage/default/5.edn_alert.1121101335 Mar 21 01:59:35 PM PDT 24 Mar 21 01:59:36 PM PDT 24 92112077 ps
T134 /workspace/coverage/default/43.edn_intr.2031359601 Mar 21 02:01:13 PM PDT 24 Mar 21 02:01:14 PM PDT 24 60419499 ps
T836 /workspace/coverage/default/4.edn_disable_auto_req_mode.3996740582 Mar 21 01:59:32 PM PDT 24 Mar 21 01:59:34 PM PDT 24 79764614 ps
T837 /workspace/coverage/default/261.edn_genbits.3765654081 Mar 21 02:02:27 PM PDT 24 Mar 21 02:02:33 PM PDT 24 58058220 ps
T838 /workspace/coverage/default/125.edn_genbits.2054773089 Mar 21 02:01:56 PM PDT 24 Mar 21 02:01:57 PM PDT 24 61285569 ps
T839 /workspace/coverage/default/13.edn_genbits.2811963418 Mar 21 02:00:03 PM PDT 24 Mar 21 02:00:05 PM PDT 24 54256958 ps
T840 /workspace/coverage/default/24.edn_intr.2987759038 Mar 21 02:00:30 PM PDT 24 Mar 21 02:00:31 PM PDT 24 22715885 ps
T841 /workspace/coverage/default/28.edn_alert_test.1753678545 Mar 21 02:00:41 PM PDT 24 Mar 21 02:00:42 PM PDT 24 36417977 ps
T233 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3127926846 Mar 21 12:49:23 PM PDT 24 Mar 21 12:49:25 PM PDT 24 82142326 ps
T230 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3915489671 Mar 21 12:49:40 PM PDT 24 Mar 21 12:49:42 PM PDT 24 52939359 ps
T842 /workspace/coverage/cover_reg_top/20.edn_intr_test.3844111920 Mar 21 12:49:47 PM PDT 24 Mar 21 12:49:48 PM PDT 24 46682084 ps
T217 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2935160720 Mar 21 12:49:13 PM PDT 24 Mar 21 12:49:15 PM PDT 24 70168980 ps
T234 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.756589202 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 39493518 ps
T231 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2730064785 Mar 21 12:49:20 PM PDT 24 Mar 21 12:49:21 PM PDT 24 46231256 ps
T232 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2147525325 Mar 21 12:49:13 PM PDT 24 Mar 21 12:49:14 PM PDT 24 26706184 ps
T843 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2725478143 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:45 PM PDT 24 250666024 ps
T844 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3211975506 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 29599181 ps
T845 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3829228828 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 146665892 ps
T846 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1416469592 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 183874408 ps
T847 /workspace/coverage/cover_reg_top/3.edn_intr_test.1128404742 Mar 21 12:49:27 PM PDT 24 Mar 21 12:49:28 PM PDT 24 56770329 ps
T204 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3611943346 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 28828748 ps
T235 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4126088464 Mar 21 12:49:44 PM PDT 24 Mar 21 12:49:47 PM PDT 24 334040959 ps
T848 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2863777393 Mar 21 12:49:20 PM PDT 24 Mar 21 12:49:21 PM PDT 24 18157680 ps
T849 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1218053655 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:43 PM PDT 24 110602850 ps
T205 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4275411398 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:16 PM PDT 24 39040284 ps
T850 /workspace/coverage/cover_reg_top/29.edn_intr_test.3549247442 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:52 PM PDT 24 14735421 ps
T851 /workspace/coverage/cover_reg_top/17.edn_intr_test.1372694115 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 25668992 ps
T852 /workspace/coverage/cover_reg_top/27.edn_intr_test.1533222832 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 53915377 ps
T853 /workspace/coverage/cover_reg_top/45.edn_intr_test.3886708931 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:08 PM PDT 24 17160727 ps
T854 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3300927070 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 20850541 ps
T855 /workspace/coverage/cover_reg_top/32.edn_intr_test.1344569499 Mar 21 12:50:04 PM PDT 24 Mar 21 12:50:05 PM PDT 24 33788714 ps
T241 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3134024506 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:46 PM PDT 24 56829995 ps
T856 /workspace/coverage/cover_reg_top/40.edn_intr_test.2867185897 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:09 PM PDT 24 14350367 ps
T857 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3639340018 Mar 21 12:49:25 PM PDT 24 Mar 21 12:49:26 PM PDT 24 163303213 ps
T206 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4187954109 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:43 PM PDT 24 13094402 ps
T858 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2764746888 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:19 PM PDT 24 383260612 ps
T859 /workspace/coverage/cover_reg_top/9.edn_intr_test.1409518561 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 14815485 ps
T860 /workspace/coverage/cover_reg_top/28.edn_intr_test.244571036 Mar 21 12:49:49 PM PDT 24 Mar 21 12:49:51 PM PDT 24 15570089 ps
T246 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.206032545 Mar 21 12:49:49 PM PDT 24 Mar 21 12:49:51 PM PDT 24 189579317 ps
T861 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1705451428 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 35964506 ps
T862 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3440314940 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:53 PM PDT 24 64634913 ps
T218 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3549873274 Mar 21 12:49:30 PM PDT 24 Mar 21 12:49:31 PM PDT 24 74713693 ps
T863 /workspace/coverage/cover_reg_top/21.edn_intr_test.634534305 Mar 21 12:49:54 PM PDT 24 Mar 21 12:49:55 PM PDT 24 19196979 ps
T864 /workspace/coverage/cover_reg_top/8.edn_tl_errors.579632350 Mar 21 12:49:31 PM PDT 24 Mar 21 12:49:36 PM PDT 24 754289147 ps
T865 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3585831641 Mar 21 12:49:49 PM PDT 24 Mar 21 12:49:50 PM PDT 24 43965913 ps
T207 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1208769355 Mar 21 12:49:43 PM PDT 24 Mar 21 12:49:45 PM PDT 24 53771966 ps
T866 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2136323172 Mar 21 12:49:27 PM PDT 24 Mar 21 12:49:28 PM PDT 24 130707011 ps
T208 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1644993892 Mar 21 12:49:14 PM PDT 24 Mar 21 12:49:15 PM PDT 24 24101993 ps
T209 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2774784928 Mar 21 12:49:22 PM PDT 24 Mar 21 12:49:23 PM PDT 24 30422363 ps
T242 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3622127298 Mar 21 12:49:35 PM PDT 24 Mar 21 12:49:38 PM PDT 24 255468799 ps
T867 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.545845415 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:36 PM PDT 24 265764923 ps
T868 /workspace/coverage/cover_reg_top/18.edn_intr_test.2313683353 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 22525346 ps
T869 /workspace/coverage/cover_reg_top/41.edn_intr_test.4290500838 Mar 21 12:50:04 PM PDT 24 Mar 21 12:50:06 PM PDT 24 19622706 ps
T210 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1867796480 Mar 21 12:49:31 PM PDT 24 Mar 21 12:49:33 PM PDT 24 42041516 ps
T870 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4196136954 Mar 21 12:49:22 PM PDT 24 Mar 21 12:49:26 PM PDT 24 293499960 ps
T211 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3694440028 Mar 21 12:49:31 PM PDT 24 Mar 21 12:49:33 PM PDT 24 12416433 ps
T871 /workspace/coverage/cover_reg_top/2.edn_intr_test.3840557512 Mar 21 12:49:23 PM PDT 24 Mar 21 12:49:24 PM PDT 24 17929559 ps
T872 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2668629599 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:35 PM PDT 24 101428134 ps
T873 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1206294113 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:33 PM PDT 24 19921119 ps
T874 /workspace/coverage/cover_reg_top/38.edn_intr_test.257906903 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:09 PM PDT 24 18625746 ps
T875 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2147022688 Mar 21 12:49:21 PM PDT 24 Mar 21 12:49:23 PM PDT 24 74502967 ps
T212 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2488561793 Mar 21 12:50:49 PM PDT 24 Mar 21 12:50:50 PM PDT 24 40281625 ps
T213 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2320692931 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 14974510 ps
T243 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.575054452 Mar 21 12:49:13 PM PDT 24 Mar 21 12:49:15 PM PDT 24 101696512 ps
T876 /workspace/coverage/cover_reg_top/15.edn_intr_test.4278256803 Mar 21 12:49:44 PM PDT 24 Mar 21 12:49:45 PM PDT 24 53651487 ps
T877 /workspace/coverage/cover_reg_top/4.edn_tl_errors.300500217 Mar 21 12:49:22 PM PDT 24 Mar 21 12:49:24 PM PDT 24 211188350 ps
T878 /workspace/coverage/cover_reg_top/14.edn_intr_test.3320154064 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:42 PM PDT 24 14885208 ps
T879 /workspace/coverage/cover_reg_top/33.edn_intr_test.1170081075 Mar 21 12:50:05 PM PDT 24 Mar 21 12:50:06 PM PDT 24 26861005 ps
T219 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1718661871 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 145535730 ps
T880 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3115777538 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:44 PM PDT 24 72253874 ps
T881 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3098201106 Mar 21 12:49:13 PM PDT 24 Mar 21 12:49:15 PM PDT 24 26176104 ps
T882 /workspace/coverage/cover_reg_top/4.edn_intr_test.3022668570 Mar 21 12:49:21 PM PDT 24 Mar 21 12:49:22 PM PDT 24 18852472 ps
T883 /workspace/coverage/cover_reg_top/48.edn_intr_test.3526764313 Mar 21 12:50:03 PM PDT 24 Mar 21 12:50:04 PM PDT 24 36250951 ps
T884 /workspace/coverage/cover_reg_top/1.edn_intr_test.2124890474 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:16 PM PDT 24 25724539 ps
T885 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1091182147 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:34 PM PDT 24 28201538 ps
T886 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1636386180 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:35 PM PDT 24 43128541 ps
T247 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3847363040 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:17 PM PDT 24 100517004 ps
T887 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4138095757 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 25752428 ps
T888 /workspace/coverage/cover_reg_top/46.edn_intr_test.2330526334 Mar 21 12:50:04 PM PDT 24 Mar 21 12:50:05 PM PDT 24 23753126 ps
T889 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3474213692 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:53 PM PDT 24 22420356 ps
T248 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2963627395 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:53 PM PDT 24 48961238 ps
T890 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.641883523 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:35 PM PDT 24 50987159 ps
T891 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2432048179 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:46 PM PDT 24 119799271 ps
T892 /workspace/coverage/cover_reg_top/11.edn_intr_test.838680385 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 21298075 ps
T893 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3984986732 Mar 21 12:49:21 PM PDT 24 Mar 21 12:49:24 PM PDT 24 351635038 ps
T894 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1910584005 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:54 PM PDT 24 234023815 ps
T895 /workspace/coverage/cover_reg_top/43.edn_intr_test.4101971167 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:09 PM PDT 24 29543286 ps
T220 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2905442109 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 35401887 ps
T221 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3909700274 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:51 PM PDT 24 40137615 ps
T896 /workspace/coverage/cover_reg_top/23.edn_intr_test.1193388141 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 39042543 ps
T897 /workspace/coverage/cover_reg_top/15.edn_tl_errors.606256323 Mar 21 12:49:43 PM PDT 24 Mar 21 12:49:46 PM PDT 24 365687872 ps
T898 /workspace/coverage/cover_reg_top/13.edn_intr_test.553447927 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:42 PM PDT 24 15574831 ps
T899 /workspace/coverage/cover_reg_top/12.edn_intr_test.3440272897 Mar 21 12:49:44 PM PDT 24 Mar 21 12:49:46 PM PDT 24 14698148 ps
T900 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1765168167 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:35 PM PDT 24 129583413 ps
T901 /workspace/coverage/cover_reg_top/6.edn_intr_test.231126253 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:34 PM PDT 24 25224843 ps
T902 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.556837981 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:52 PM PDT 24 55523197 ps
T222 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2446318585 Mar 21 12:49:43 PM PDT 24 Mar 21 12:49:45 PM PDT 24 19006937 ps
T903 /workspace/coverage/cover_reg_top/37.edn_intr_test.3507829383 Mar 21 12:50:03 PM PDT 24 Mar 21 12:50:04 PM PDT 24 12556097 ps
T904 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1911664170 Mar 21 12:49:21 PM PDT 24 Mar 21 12:49:22 PM PDT 24 42529671 ps
T905 /workspace/coverage/cover_reg_top/10.edn_intr_test.1344542931 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 15005047 ps
T906 /workspace/coverage/cover_reg_top/5.edn_tl_errors.548713740 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:36 PM PDT 24 166755209 ps
T907 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2537465335 Mar 21 12:49:34 PM PDT 24 Mar 21 12:49:37 PM PDT 24 122189712 ps
T908 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1209237562 Mar 21 12:49:18 PM PDT 24 Mar 21 12:49:21 PM PDT 24 180396150 ps
T909 /workspace/coverage/cover_reg_top/39.edn_intr_test.196703720 Mar 21 12:50:03 PM PDT 24 Mar 21 12:50:05 PM PDT 24 25340061 ps
T910 /workspace/coverage/cover_reg_top/8.edn_intr_test.2418685573 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:33 PM PDT 24 57139659 ps
T911 /workspace/coverage/cover_reg_top/44.edn_intr_test.1865748095 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:08 PM PDT 24 28471907 ps
T912 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.572327431 Mar 21 12:49:31 PM PDT 24 Mar 21 12:49:33 PM PDT 24 673724848 ps
T223 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3190052074 Mar 21 12:49:14 PM PDT 24 Mar 21 12:49:15 PM PDT 24 22267897 ps
T913 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1294496356 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:54 PM PDT 24 191508904 ps
T914 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4133614432 Mar 21 12:49:19 PM PDT 24 Mar 21 12:49:20 PM PDT 24 47409589 ps
T915 /workspace/coverage/cover_reg_top/47.edn_intr_test.3926111828 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:09 PM PDT 24 24214260 ps
T916 /workspace/coverage/cover_reg_top/7.edn_intr_test.1699529707 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:35 PM PDT 24 16619895 ps
T917 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2516910698 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:44 PM PDT 24 29885729 ps
T244 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.593745826 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:36 PM PDT 24 49730593 ps
T918 /workspace/coverage/cover_reg_top/22.edn_intr_test.4282377920 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:52 PM PDT 24 25250011 ps
T919 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4067099001 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:35 PM PDT 24 77981478 ps
T920 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1437219723 Mar 21 12:49:34 PM PDT 24 Mar 21 12:49:35 PM PDT 24 38135171 ps
T921 /workspace/coverage/cover_reg_top/24.edn_intr_test.3393420957 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 23276005 ps
T922 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.565310348 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 38846661 ps
T923 /workspace/coverage/cover_reg_top/31.edn_intr_test.1361019621 Mar 21 12:50:06 PM PDT 24 Mar 21 12:50:07 PM PDT 24 14822144 ps
T924 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2207570172 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:21 PM PDT 24 677087018 ps
T925 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3623055827 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:53 PM PDT 24 149192315 ps
T926 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.397528349 Mar 21 12:49:46 PM PDT 24 Mar 21 12:49:48 PM PDT 24 35994044 ps
T245 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2226195155 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 156067992 ps
T927 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1228542433 Mar 21 12:49:26 PM PDT 24 Mar 21 12:49:28 PM PDT 24 19789807 ps
T928 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2106963940 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:33 PM PDT 24 68825823 ps
T929 /workspace/coverage/cover_reg_top/49.edn_intr_test.1304137688 Mar 21 12:50:11 PM PDT 24 Mar 21 12:50:12 PM PDT 24 25496844 ps
T930 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.778873475 Mar 21 12:49:22 PM PDT 24 Mar 21 12:49:23 PM PDT 24 265712557 ps
T931 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3136829460 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:44 PM PDT 24 64607944 ps
T932 /workspace/coverage/cover_reg_top/26.edn_intr_test.2411246648 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 31891044 ps
T933 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2980028887 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 24333624 ps
T934 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2684239948 Mar 21 12:49:38 PM PDT 24 Mar 21 12:49:40 PM PDT 24 198490563 ps
T935 /workspace/coverage/cover_reg_top/36.edn_intr_test.713182439 Mar 21 12:50:05 PM PDT 24 Mar 21 12:50:07 PM PDT 24 46324436 ps
T936 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3570020421 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:53 PM PDT 24 166345561 ps
T937 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3719928552 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 61913558 ps
T938 /workspace/coverage/cover_reg_top/34.edn_intr_test.2283345170 Mar 21 12:50:09 PM PDT 24 Mar 21 12:50:10 PM PDT 24 23775194 ps
T939 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3017404260 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:33 PM PDT 24 15981645 ps
T940 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4099659022 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 38760748 ps
T941 /workspace/coverage/cover_reg_top/19.edn_intr_test.327783524 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 44350046 ps
T942 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2033899144 Mar 21 12:49:42 PM PDT 24 Mar 21 12:49:45 PM PDT 24 34678135 ps
T943 /workspace/coverage/cover_reg_top/0.edn_tl_errors.193454011 Mar 21 12:49:16 PM PDT 24 Mar 21 12:49:19 PM PDT 24 62179087 ps
T944 /workspace/coverage/cover_reg_top/16.edn_intr_test.2851066121 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 12913355 ps
T945 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2499318654 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:34 PM PDT 24 59784454 ps
T946 /workspace/coverage/cover_reg_top/30.edn_intr_test.1897531964 Mar 21 12:50:07 PM PDT 24 Mar 21 12:50:08 PM PDT 24 37107494 ps
T947 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3134024317 Mar 21 12:49:16 PM PDT 24 Mar 21 12:49:17 PM PDT 24 26873058 ps
T948 /workspace/coverage/cover_reg_top/0.edn_intr_test.17600011 Mar 21 12:49:11 PM PDT 24 Mar 21 12:49:12 PM PDT 24 41554484 ps
T949 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.49866544 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:43 PM PDT 24 292427315 ps
T214 /workspace/coverage/cover_reg_top/19.edn_csr_rw.323624655 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:53 PM PDT 24 18875474 ps
T950 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2665232930 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 15084486 ps
T951 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4117953660 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:16 PM PDT 24 29950548 ps
T952 /workspace/coverage/cover_reg_top/6.edn_tl_errors.4156571818 Mar 21 12:49:32 PM PDT 24 Mar 21 12:49:36 PM PDT 24 81114563 ps
T953 /workspace/coverage/cover_reg_top/42.edn_intr_test.4112254819 Mar 21 12:50:04 PM PDT 24 Mar 21 12:50:05 PM PDT 24 39533548 ps
T954 /workspace/coverage/cover_reg_top/17.edn_tl_errors.4118499956 Mar 21 12:49:53 PM PDT 24 Mar 21 12:49:56 PM PDT 24 89233655 ps
T955 /workspace/coverage/cover_reg_top/25.edn_intr_test.1586587798 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:52 PM PDT 24 13281861 ps
T956 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1483419278 Mar 21 12:49:25 PM PDT 24 Mar 21 12:49:26 PM PDT 24 36310552 ps
T957 /workspace/coverage/cover_reg_top/35.edn_intr_test.3265804674 Mar 21 12:50:05 PM PDT 24 Mar 21 12:50:06 PM PDT 24 81965498 ps
T958 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3781699419 Mar 21 12:49:27 PM PDT 24 Mar 21 12:49:28 PM PDT 24 46837983 ps
T959 /workspace/coverage/cover_reg_top/10.edn_csr_rw.4018941155 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:34 PM PDT 24 14273576 ps
T216 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.908900664 Mar 21 12:50:49 PM PDT 24 Mar 21 12:50:53 PM PDT 24 132585713 ps
T960 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3651478091 Mar 21 12:49:40 PM PDT 24 Mar 21 12:49:42 PM PDT 24 779818379 ps
T961 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4157584999 Mar 21 12:49:22 PM PDT 24 Mar 21 12:49:23 PM PDT 24 28358469 ps
T962 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4246531744 Mar 21 12:49:22 PM PDT 24 Mar 21 12:49:23 PM PDT 24 68475956 ps
T963 /workspace/coverage/cover_reg_top/18.edn_tl_errors.810053395 Mar 21 12:49:52 PM PDT 24 Mar 21 12:49:54 PM PDT 24 69911266 ps
T964 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2691421746 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:35 PM PDT 24 13143782 ps
T965 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1420067987 Mar 21 12:49:49 PM PDT 24 Mar 21 12:49:50 PM PDT 24 33343087 ps
T966 /workspace/coverage/cover_reg_top/5.edn_intr_test.485855137 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:34 PM PDT 24 40361810 ps
T967 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1504396217 Mar 21 12:49:33 PM PDT 24 Mar 21 12:49:34 PM PDT 24 18605542 ps
T968 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3394982901 Mar 21 12:49:50 PM PDT 24 Mar 21 12:49:52 PM PDT 24 100216501 ps
T215 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3452634680 Mar 21 12:49:46 PM PDT 24 Mar 21 12:49:49 PM PDT 24 15976265 ps
T969 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1047262228 Mar 21 12:49:51 PM PDT 24 Mar 21 12:49:53 PM PDT 24 33667070 ps
T970 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1549537067 Mar 21 12:49:35 PM PDT 24 Mar 21 12:49:37 PM PDT 24 25376185 ps
T971 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2467625789 Mar 21 12:49:41 PM PDT 24 Mar 21 12:49:43 PM PDT 24 90255342 ps
T972 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3002671968 Mar 21 12:49:27 PM PDT 24 Mar 21 12:49:29 PM PDT 24 25539545 ps

Test location /workspace/coverage/default/81.edn_genbits.4244433016
Short name T28
Test name
Test status
Simulation time 41396152 ps
CPU time 1.68 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 217804 kb
Host smart-092147a2-dd55-499c-ad88-c5923f5203e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244433016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4244433016
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1633800813
Short name T24
Test name
Test status
Simulation time 181007394234 ps
CPU time 2457.63 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:42:10 PM PDT 24
Peak memory 230904 kb
Host smart-895c53c5-0c11-454e-9692-c75609e84af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633800813 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1633800813
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3631308676
Short name T20
Test name
Test status
Simulation time 392172154 ps
CPU time 6.77 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:42 PM PDT 24
Peak memory 235632 kb
Host smart-cad3506d-f663-429c-b1bb-643a1265cb5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631308676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3631308676
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/177.edn_genbits.2153298770
Short name T14
Test name
Test status
Simulation time 314164765 ps
CPU time 4.18 seconds
Started Mar 21 02:02:11 PM PDT 24
Finished Mar 21 02:02:15 PM PDT 24
Peak memory 218036 kb
Host smart-74ed18cc-0389-4050-afbe-5e74b12cceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153298770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2153298770
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.877741333
Short name T19
Test name
Test status
Simulation time 141600294 ps
CPU time 1.19 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 215804 kb
Host smart-4664f465-7992-4815-8022-ac5686a9893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877741333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.877741333
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.3780600756
Short name T36
Test name
Test status
Simulation time 15419975 ps
CPU time 0.82 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 216024 kb
Host smart-15486a77-1d5b-4a18-b0e9-ab43cf819d97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780600756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3780600756
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2824349714
Short name T64
Test name
Test status
Simulation time 88477557 ps
CPU time 1.16 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 216720 kb
Host smart-e3b5a27b-79ce-4dbd-9cf6-fe93b1f103fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824349714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2824349714
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_alert.2293577244
Short name T61
Test name
Test status
Simulation time 79001810 ps
CPU time 1.25 seconds
Started Mar 21 02:01:30 PM PDT 24
Finished Mar 21 02:01:31 PM PDT 24
Peak memory 215788 kb
Host smart-9934850f-d19c-4573-9f9f-ed73f68fee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293577244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2293577244
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.2668041489
Short name T118
Test name
Test status
Simulation time 17841166 ps
CPU time 0.99 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 207172 kb
Host smart-17c81161-211b-4dd2-ba1c-e0b63947243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668041489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2668041489
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/19.edn_intr.915395375
Short name T124
Test name
Test status
Simulation time 22803957 ps
CPU time 1.06 seconds
Started Mar 21 02:00:20 PM PDT 24
Finished Mar 21 02:00:21 PM PDT 24
Peak memory 215872 kb
Host smart-194151e5-97bd-4acc-88db-4b4e3b99c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915395375 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.915395375
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/15.edn_alert.945501435
Short name T146
Test name
Test status
Simulation time 79057708 ps
CPU time 1.13 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 215788 kb
Host smart-72d6f986-46c1-4541-b5f1-d1aa23fcc16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945501435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.945501435
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.4192712156
Short name T251
Test name
Test status
Simulation time 120202328 ps
CPU time 1.13 seconds
Started Mar 21 01:59:20 PM PDT 24
Finished Mar 21 01:59:21 PM PDT 24
Peak memory 215808 kb
Host smart-f277cafa-a8ba-4f40-be3d-4e45f66c70a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192712156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4192712156
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.685252831
Short name T161
Test name
Test status
Simulation time 85076768 ps
CPU time 1.07 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:26 PM PDT 24
Peak memory 216644 kb
Host smart-fe6958ef-351e-4727-b334-97c3c9b96797
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685252831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.685252831
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1208769355
Short name T207
Test name
Test status
Simulation time 53771966 ps
CPU time 0.96 seconds
Started Mar 21 12:49:43 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 205904 kb
Host smart-933fe197-162d-463d-8b65-7ff77524efc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208769355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1208769355
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1934588232
Short name T192
Test name
Test status
Simulation time 235811189992 ps
CPU time 2516.64 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:43:06 PM PDT 24
Peak memory 228420 kb
Host smart-7b246ed3-bb9a-47a3-bdb4-b06c5b31808b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934588232 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1934588232
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3847363040
Short name T247
Test name
Test status
Simulation time 100517004 ps
CPU time 2.27 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:17 PM PDT 24
Peak memory 206060 kb
Host smart-6bf73391-a666-4a2e-a8a5-60ece2c39e37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847363040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3847363040
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/14.edn_disable.1328457153
Short name T150
Test name
Test status
Simulation time 29242015 ps
CPU time 0.81 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 216000 kb
Host smart-0f37efd8-3a68-43b8-aac3-87dfdf1cec82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328457153 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1328457153
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.1124082101
Short name T165
Test name
Test status
Simulation time 10576866 ps
CPU time 0.89 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 216028 kb
Host smart-99f6170d-53c9-48a7-aaa9-93b858a4d40e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124082101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1124082101
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/289.edn_genbits.1693842660
Short name T29
Test name
Test status
Simulation time 48690808 ps
CPU time 1.4 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 218192 kb
Host smart-db8ca443-86e0-4489-bfab-265fc0335234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693842660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1693842660
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_disable.1502303335
Short name T103
Test name
Test status
Simulation time 13841481 ps
CPU time 0.83 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 216088 kb
Host smart-548a1d1f-7a51-4614-9b77-34503b81a86d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502303335 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1502303335
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_intr.2961129368
Short name T129
Test name
Test status
Simulation time 44510291 ps
CPU time 0.78 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 215704 kb
Host smart-08acb13b-6bf7-4ce6-b06e-caadc71179a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961129368 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2961129368
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.20893627
Short name T152
Test name
Test status
Simulation time 62978768723 ps
CPU time 1606.73 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:28:00 PM PDT 24
Peak memory 225348 kb
Host smart-01111c3c-e226-4daf-9640-07dbd44ab7f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20893627 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.20893627
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_err.3745006545
Short name T41
Test name
Test status
Simulation time 101528681 ps
CPU time 1.21 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 233456 kb
Host smart-4349365a-1faa-4c2c-9024-770fbe39943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745006545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3745006545
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/179.edn_genbits.2211059272
Short name T267
Test name
Test status
Simulation time 103290557 ps
CPU time 1.29 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 219536 kb
Host smart-f361d660-b466-40f9-aeb2-9dda06be230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211059272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2211059272
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_genbits.2664483120
Short name T185
Test name
Test status
Simulation time 64390814 ps
CPU time 1.43 seconds
Started Mar 21 02:01:06 PM PDT 24
Finished Mar 21 02:01:08 PM PDT 24
Peak memory 218860 kb
Host smart-0c7d65e9-ccd6-4657-ae46-19c399d974a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664483120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2664483120
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3357533200
Short name T59
Test name
Test status
Simulation time 48104879 ps
CPU time 1 seconds
Started Mar 21 02:00:21 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 217868 kb
Host smart-d4280351-6b0b-426d-98c5-265379f85a3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357533200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3357533200
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_disable.3078360910
Short name T90
Test name
Test status
Simulation time 12489298 ps
CPU time 0.9 seconds
Started Mar 21 01:59:36 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 207564 kb
Host smart-e0052f56-0480-4a61-b75f-4207d0e413e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078360910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3078360910
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.4239148133
Short name T37
Test name
Test status
Simulation time 84276548 ps
CPU time 0.87 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 216052 kb
Host smart-225102e3-2036-441a-9df1-bd425638d4b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239148133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4239148133
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable.2939765366
Short name T149
Test name
Test status
Simulation time 12950820 ps
CPU time 0.92 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 216256 kb
Host smart-be76efbf-88aa-433b-a10a-b9f8178647e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939765366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2939765366
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/3.edn_alert_test.4148189027
Short name T1
Test name
Test status
Simulation time 43516988 ps
CPU time 0.86 seconds
Started Mar 21 02:00:06 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 206500 kb
Host smart-a1738b82-e7ea-420f-a485-e7f367daebe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148189027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4148189027
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.222684786
Short name T651
Test name
Test status
Simulation time 88679955 ps
CPU time 1.29 seconds
Started Mar 21 02:00:06 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 216812 kb
Host smart-dc7267e9-ff09-4c63-b492-4b39d3da1fa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222684786 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.222684786
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1047545894
Short name T83
Test name
Test status
Simulation time 36758656 ps
CPU time 1.19 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:43 PM PDT 24
Peak memory 218264 kb
Host smart-16e37e8c-a08a-4733-9e89-fa37d641c364
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047545894 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1047545894
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_disable.3674448949
Short name T115
Test name
Test status
Simulation time 33852390 ps
CPU time 0.82 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 216024 kb
Host smart-227f1f17-b2a4-4d83-9e9f-dc8ce9177fe7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674448949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3674448949
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.2869237618
Short name T163
Test name
Test status
Simulation time 16134918 ps
CPU time 0.88 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 216024 kb
Host smart-d41abc55-789f-4120-afa4-9fd49d3b7c55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869237618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2869237618
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1697595919
Short name T70
Test name
Test status
Simulation time 44070193 ps
CPU time 1.4 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 219156 kb
Host smart-a9257d3d-5b8f-4944-a6b2-759f6a708a68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697595919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1697595919
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/229.edn_genbits.739874994
Short name T268
Test name
Test status
Simulation time 65280614 ps
CPU time 1.76 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 218308 kb
Host smart-ee6682bf-165b-44ec-9d6e-02bc9a466feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739874994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.739874994
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.998035156
Short name T119
Test name
Test status
Simulation time 50418416 ps
CPU time 0.95 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 207236 kb
Host smart-7925724d-ac95-441e-827a-e02d1c3c7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998035156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.998035156
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_regwen.3476044116
Short name T255
Test name
Test status
Simulation time 78093272 ps
CPU time 0.86 seconds
Started Mar 21 01:59:23 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 207168 kb
Host smart-b5600345-6b1c-45e6-9b1f-06d685013590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476044116 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3476044116
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/24.edn_alert.2757372442
Short name T263
Test name
Test status
Simulation time 104551906 ps
CPU time 1.31 seconds
Started Mar 21 02:00:33 PM PDT 24
Finished Mar 21 02:00:34 PM PDT 24
Peak memory 215792 kb
Host smart-5994bf46-14a2-4b9b-b3bc-9529269b6244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757372442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2757372442
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert.3141258253
Short name T239
Test name
Test status
Simulation time 42181816 ps
CPU time 1.12 seconds
Started Mar 21 02:00:48 PM PDT 24
Finished Mar 21 02:00:50 PM PDT 24
Peak memory 215792 kb
Host smart-40bb178a-4efb-409a-97e0-c71a53b00381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141258253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3141258253
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/4.edn_intr.2183464815
Short name T123
Test name
Test status
Simulation time 84835064 ps
CPU time 0.84 seconds
Started Mar 21 01:59:32 PM PDT 24
Finished Mar 21 01:59:33 PM PDT 24
Peak memory 215672 kb
Host smart-8a5af1a1-99ab-4285-b27d-c8ac1e4c41c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183464815 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2183464815
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3190052074
Short name T223
Test name
Test status
Simulation time 22267897 ps
CPU time 0.85 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 205848 kb
Host smart-effb501b-316c-44bc-b9bf-f5f806ea1222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190052074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3190052074
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2226195155
Short name T245
Test name
Test status
Simulation time 156067992 ps
CPU time 1.58 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 206028 kb
Host smart-3b68f6c4-230c-4352-a2c5-e0b5d77a2c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226195155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2226195155
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/100.edn_genbits.3670166471
Short name T280
Test name
Test status
Simulation time 62689564 ps
CPU time 1.15 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 218860 kb
Host smart-1b7a9e78-53d8-463f-9007-cafd19bbdd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670166471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3670166471
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2523299466
Short name T527
Test name
Test status
Simulation time 128022821 ps
CPU time 3.01 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:56 PM PDT 24
Peak memory 219576 kb
Host smart-f099d7ac-0adb-4df7-8ce0-b6dc40cc30fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523299466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2523299466
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3682927345
Short name T291
Test name
Test status
Simulation time 54780085 ps
CPU time 1.48 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:54 PM PDT 24
Peak memory 218004 kb
Host smart-7e724e65-ed8b-4347-8fb2-2bbd579a51fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682927345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3682927345
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all.779329337
Short name T782
Test name
Test status
Simulation time 284140798 ps
CPU time 2.41 seconds
Started Mar 21 02:00:00 PM PDT 24
Finished Mar 21 02:00:03 PM PDT 24
Peak memory 216980 kb
Host smart-94bf236b-7aa7-4e57-969a-e2e541ac5125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779329337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.779329337
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all.699408251
Short name T270
Test name
Test status
Simulation time 214534924 ps
CPU time 4.56 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:24 PM PDT 24
Peak memory 219540 kb
Host smart-4e12bfa7-e969-45f9-8721-f05adc440a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699408251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.699408251
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/165.edn_genbits.3542131737
Short name T274
Test name
Test status
Simulation time 72040281 ps
CPU time 1.29 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 219388 kb
Host smart-f5d789c4-91da-4edb-9d4f-0b20262952a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542131737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3542131737
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2739253976
Short name T257
Test name
Test status
Simulation time 43428366 ps
CPU time 1.15 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 215900 kb
Host smart-00cbcc99-4e42-482e-98ef-1d89e7d1a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739253976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2739253976
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.4061620758
Short name T283
Test name
Test status
Simulation time 125072286 ps
CPU time 1.11 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 216664 kb
Host smart-a30198eb-d2c4-44de-af1d-1851ea2b185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061620758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4061620758
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.360798185
Short name T620
Test name
Test status
Simulation time 97501643 ps
CPU time 1.05 seconds
Started Mar 21 02:02:10 PM PDT 24
Finished Mar 21 02:02:11 PM PDT 24
Peak memory 216764 kb
Host smart-c1d21f69-3696-4884-95f4-07ac63427e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360798185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.360798185
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.161094410
Short name T224
Test name
Test status
Simulation time 93603460 ps
CPU time 1.42 seconds
Started Mar 21 02:02:04 PM PDT 24
Finished Mar 21 02:02:05 PM PDT 24
Peak memory 218508 kb
Host smart-d1b12d8a-8fb7-4748-87eb-be315397591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161094410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.161094410
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2699574805
Short name T175
Test name
Test status
Simulation time 57401565 ps
CPU time 1.15 seconds
Started Mar 21 02:02:14 PM PDT 24
Finished Mar 21 02:02:16 PM PDT 24
Peak memory 218044 kb
Host smart-0be20f5d-7c4f-450c-8651-feee7e4a4c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699574805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2699574805
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3139139691
Short name T285
Test name
Test status
Simulation time 35161579 ps
CPU time 1.44 seconds
Started Mar 21 02:02:29 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218036 kb
Host smart-20664c4e-7651-45b1-b323-96de91b58d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139139691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3139139691
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_alert.3569871631
Short name T253
Test name
Test status
Simulation time 39164436 ps
CPU time 1.17 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 215896 kb
Host smart-f2d41b14-b1f0-473d-bd68-48bafde6fca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569871631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3569871631
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.1479621233
Short name T127
Test name
Test status
Simulation time 34831609 ps
CPU time 0.84 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 215684 kb
Host smart-daf6af80-924d-4967-98bc-38adf07d4914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479621233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1479621233
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/12.edn_err.3773718993
Short name T42
Test name
Test status
Simulation time 32112142 ps
CPU time 1 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 232316 kb
Host smart-69c7e699-b0a5-4941-b5eb-ff482e12a514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773718993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3773718993
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/1.edn_err.1808786708
Short name T155
Test name
Test status
Simulation time 21077267 ps
CPU time 1.11 seconds
Started Mar 21 01:59:24 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 219692 kb
Host smart-84ed0f48-961a-40a0-ae86-8f9c93b12e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808786708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1808786708
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.860785595
Short name T426
Test name
Test status
Simulation time 53010047 ps
CPU time 1.33 seconds
Started Mar 21 01:59:31 PM PDT 24
Finished Mar 21 01:59:32 PM PDT 24
Peak memory 217108 kb
Host smart-e8c9a3bc-2a9a-498e-9d35-bc8e27efe62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860785595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.860785595
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2367838626
Short name T131
Test name
Test status
Simulation time 111154631 ps
CPU time 1.69 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 219564 kb
Host smart-522b4b6b-f527-4b5d-9645-93a068424ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367838626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2367838626
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2147525325
Short name T232
Test name
Test status
Simulation time 26706184 ps
CPU time 1.09 seconds
Started Mar 21 12:49:13 PM PDT 24
Finished Mar 21 12:49:14 PM PDT 24
Peak memory 205888 kb
Host smart-86295a3f-a1be-4132-a5a8-2557790f519e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147525325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2147525325
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2207570172
Short name T924
Test name
Test status
Simulation time 677087018 ps
CPU time 5.69 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:21 PM PDT 24
Peak memory 205816 kb
Host smart-82152300-b6e6-482e-805f-70d9ce3edf4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207570172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2207570172
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4133614432
Short name T914
Test name
Test status
Simulation time 47409589 ps
CPU time 0.88 seconds
Started Mar 21 12:49:19 PM PDT 24
Finished Mar 21 12:49:20 PM PDT 24
Peak memory 205840 kb
Host smart-71c2ddc0-a6f7-49b1-a75e-67a0a4d8ad9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133614432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4133614432
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3098201106
Short name T881
Test name
Test status
Simulation time 26176104 ps
CPU time 1.75 seconds
Started Mar 21 12:49:13 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 214236 kb
Host smart-16005e31-6e4d-4dd5-b4f3-e0526df2bda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098201106 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3098201106
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.17600011
Short name T948
Test name
Test status
Simulation time 41554484 ps
CPU time 0.79 seconds
Started Mar 21 12:49:11 PM PDT 24
Finished Mar 21 12:49:12 PM PDT 24
Peak memory 205728 kb
Host smart-a3f1d9c0-3b3e-4cef-9d7c-04983a95f641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17600011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.17600011
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4117953660
Short name T951
Test name
Test status
Simulation time 29950548 ps
CPU time 1.18 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 206072 kb
Host smart-8d1e9fa0-51ca-4e2d-a2fd-c73c4b1cc8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117953660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4117953660
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.193454011
Short name T943
Test name
Test status
Simulation time 62179087 ps
CPU time 2.71 seconds
Started Mar 21 12:49:16 PM PDT 24
Finished Mar 21 12:49:19 PM PDT 24
Peak memory 214320 kb
Host smart-e6923be5-e4c4-4acf-b1b5-5b159080697d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193454011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.193454011
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.575054452
Short name T243
Test name
Test status
Simulation time 101696512 ps
CPU time 2.56 seconds
Started Mar 21 12:49:13 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 205940 kb
Host smart-49a5580f-7556-4591-acda-700b991011c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575054452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.575054452
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1644993892
Short name T208
Test name
Test status
Simulation time 24101993 ps
CPU time 1.01 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 205884 kb
Host smart-ec823ea3-746c-4fcb-a6f7-7950363f2243
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644993892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1644993892
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2764746888
Short name T858
Test name
Test status
Simulation time 383260612 ps
CPU time 3.61 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:19 PM PDT 24
Peak memory 205860 kb
Host smart-9de48e72-10a6-4b00-a19f-ed534fd1d05d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764746888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2764746888
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4275411398
Short name T205
Test name
Test status
Simulation time 39040284 ps
CPU time 0.83 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 205668 kb
Host smart-a9231b64-45f2-4f94-a86c-087fdadafaf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275411398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4275411398
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2147022688
Short name T875
Test name
Test status
Simulation time 74502967 ps
CPU time 1.43 seconds
Started Mar 21 12:49:21 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 214716 kb
Host smart-1aec3b23-861b-4f06-ae94-05646b8af183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147022688 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2147022688
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3134024317
Short name T947
Test name
Test status
Simulation time 26873058 ps
CPU time 0.9 seconds
Started Mar 21 12:49:16 PM PDT 24
Finished Mar 21 12:49:17 PM PDT 24
Peak memory 205812 kb
Host smart-1f4f09e7-e3a0-4410-9824-026a40c01593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134024317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3134024317
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2124890474
Short name T884
Test name
Test status
Simulation time 25724539 ps
CPU time 0.91 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 205868 kb
Host smart-5beb0d72-2a29-4f4f-bc66-62bbb54fef7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124890474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2124890474
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2935160720
Short name T217
Test name
Test status
Simulation time 70168980 ps
CPU time 1.25 seconds
Started Mar 21 12:49:13 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 205980 kb
Host smart-0eb1fc3a-91ef-47af-877c-04fcab7be6de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935160720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2935160720
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1209237562
Short name T908
Test name
Test status
Simulation time 180396150 ps
CPU time 3.09 seconds
Started Mar 21 12:49:18 PM PDT 24
Finished Mar 21 12:49:21 PM PDT 24
Peak memory 214216 kb
Host smart-6b156606-4376-42e7-96a7-60518ed340bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209237562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1209237562
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1218053655
Short name T849
Test name
Test status
Simulation time 110602850 ps
CPU time 1.24 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:43 PM PDT 24
Peak memory 214316 kb
Host smart-bec43417-3b7c-45ff-987d-aabd6a7b4f42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218053655 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1218053655
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.4018941155
Short name T959
Test name
Test status
Simulation time 14273576 ps
CPU time 0.87 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205912 kb
Host smart-b7f4084a-2ae3-4db9-ba01-fafe7fcae53d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018941155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.4018941155
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1344542931
Short name T905
Test name
Test status
Simulation time 15005047 ps
CPU time 0.84 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 205848 kb
Host smart-5f80fbd8-54d6-44d5-9da9-f8cf11006834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344542931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1344542931
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2106963940
Short name T928
Test name
Test status
Simulation time 68825823 ps
CPU time 0.92 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 206068 kb
Host smart-5e287ca6-b9bc-482f-b29a-cc4e8062f63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106963940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2106963940
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1765168167
Short name T900
Test name
Test status
Simulation time 129583413 ps
CPU time 2.45 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 214328 kb
Host smart-ba97dc2f-6295-43ac-adf5-38e395d32b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765168167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1765168167
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3622127298
Short name T242
Test name
Test status
Simulation time 255468799 ps
CPU time 2.04 seconds
Started Mar 21 12:49:35 PM PDT 24
Finished Mar 21 12:49:38 PM PDT 24
Peak memory 205896 kb
Host smart-e2fcafd5-1ba6-4247-8252-adf0e1d0f79c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622127298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3622127298
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3829228828
Short name T845
Test name
Test status
Simulation time 146665892 ps
CPU time 1.2 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 214268 kb
Host smart-148e9370-eb32-46a6-af87-74d33c8ed5ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829228828 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3829228828
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4187954109
Short name T206
Test name
Test status
Simulation time 13094402 ps
CPU time 0.9 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:43 PM PDT 24
Peak memory 205828 kb
Host smart-f660e687-f32e-43ac-866b-3e14d9104c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187954109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4187954109
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.838680385
Short name T892
Test name
Test status
Simulation time 21298075 ps
CPU time 0.89 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 205800 kb
Host smart-bf82a2c3-fd10-45c0-b0e5-767ff26cd362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838680385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.838680385
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2446318585
Short name T222
Test name
Test status
Simulation time 19006937 ps
CPU time 1.02 seconds
Started Mar 21 12:49:43 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 206152 kb
Host smart-de15c51c-800f-4ed4-82ca-18fe117cc47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446318585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2446318585
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3115777538
Short name T880
Test name
Test status
Simulation time 72253874 ps
CPU time 1.48 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:44 PM PDT 24
Peak memory 214372 kb
Host smart-d6be8c0e-68ed-4373-9b2d-bc7a3e3cbcd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115777538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3115777538
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2467625789
Short name T971
Test name
Test status
Simulation time 90255342 ps
CPU time 1.57 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:43 PM PDT 24
Peak memory 206064 kb
Host smart-29f607d0-dfe4-473d-9607-9ed3fcfab908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467625789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2467625789
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2033899144
Short name T942
Test name
Test status
Simulation time 34678135 ps
CPU time 1.28 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 214316 kb
Host smart-c3e0955b-1999-4678-be24-567261d25284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033899144 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2033899144
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2320692931
Short name T213
Test name
Test status
Simulation time 14974510 ps
CPU time 0.89 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 205844 kb
Host smart-b778fd91-4cd4-4133-af87-132840c0dcd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320692931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2320692931
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3440272897
Short name T899
Test name
Test status
Simulation time 14698148 ps
CPU time 0.91 seconds
Started Mar 21 12:49:44 PM PDT 24
Finished Mar 21 12:49:46 PM PDT 24
Peak memory 206012 kb
Host smart-73c27ace-2b18-4430-93ed-acb3112e47de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440272897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3440272897
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2516910698
Short name T917
Test name
Test status
Simulation time 29885729 ps
CPU time 1.31 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:44 PM PDT 24
Peak memory 205988 kb
Host smart-58780477-50fa-40e8-872f-85ae3a30aecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516910698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2516910698
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2432048179
Short name T891
Test name
Test status
Simulation time 119799271 ps
CPU time 2.36 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:46 PM PDT 24
Peak memory 214344 kb
Host smart-1b4810d5-0efb-4452-a2e9-0919f26b8a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432048179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2432048179
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4126088464
Short name T235
Test name
Test status
Simulation time 334040959 ps
CPU time 2.5 seconds
Started Mar 21 12:49:44 PM PDT 24
Finished Mar 21 12:49:47 PM PDT 24
Peak memory 205844 kb
Host smart-256dfaae-0615-4263-8386-4dd3f64d10df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126088464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4126088464
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3300927070
Short name T854
Test name
Test status
Simulation time 20850541 ps
CPU time 1.35 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 214328 kb
Host smart-042e8603-d1e0-420b-a426-96d86b1c6d47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300927070 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3300927070
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3915489671
Short name T230
Test name
Test status
Simulation time 52939359 ps
CPU time 0.92 seconds
Started Mar 21 12:49:40 PM PDT 24
Finished Mar 21 12:49:42 PM PDT 24
Peak memory 205856 kb
Host smart-98116931-ef56-4486-b360-f9f218a8360b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915489671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3915489671
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.553447927
Short name T898
Test name
Test status
Simulation time 15574831 ps
CPU time 0.81 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:42 PM PDT 24
Peak memory 205844 kb
Host smart-0bc4e97f-fc70-4696-b646-987f65156dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553447927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.553447927
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3136829460
Short name T931
Test name
Test status
Simulation time 64607944 ps
CPU time 1.46 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:44 PM PDT 24
Peak memory 206008 kb
Host smart-a520aa01-ad4f-46e6-b39f-31a9dcf11e16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136829460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3136829460
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3719928552
Short name T937
Test name
Test status
Simulation time 61913558 ps
CPU time 1.3 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 214288 kb
Host smart-34daeeec-f91c-4177-bb14-1a1ae757025b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719928552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3719928552
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.49866544
Short name T949
Test name
Test status
Simulation time 292427315 ps
CPU time 1.14 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:43 PM PDT 24
Peak memory 214212 kb
Host smart-80db4aeb-3469-4685-91fa-94ad3ded9e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49866544 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.49866544
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3320154064
Short name T878
Test name
Test status
Simulation time 14885208 ps
CPU time 0.9 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:42 PM PDT 24
Peak memory 205816 kb
Host smart-a95b02c2-a601-4d56-a9d4-fff1b7ebba3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320154064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3320154064
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3611943346
Short name T204
Test name
Test status
Simulation time 28828748 ps
CPU time 1.22 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 206000 kb
Host smart-8c4ee704-d3ef-4b40-94ae-b53ad0c09d14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611943346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3611943346
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2725478143
Short name T843
Test name
Test status
Simulation time 250666024 ps
CPU time 2.39 seconds
Started Mar 21 12:49:41 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 214204 kb
Host smart-5d340f44-e8a5-480b-9fea-561603430422
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725478143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2725478143
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3134024506
Short name T241
Test name
Test status
Simulation time 56829995 ps
CPU time 1.6 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:46 PM PDT 24
Peak memory 205996 kb
Host smart-a0d41fc3-b645-4e8f-8830-f9fa75cd8f51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134024506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3134024506
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3474213692
Short name T889
Test name
Test status
Simulation time 22420356 ps
CPU time 1.28 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 214452 kb
Host smart-f6c54ac7-e744-4ee1-b239-34e88982d984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474213692 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3474213692
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3452634680
Short name T215
Test name
Test status
Simulation time 15976265 ps
CPU time 0.96 seconds
Started Mar 21 12:49:46 PM PDT 24
Finished Mar 21 12:49:49 PM PDT 24
Peak memory 205836 kb
Host smart-4b00620b-97cc-4801-99eb-7a6e29a3abf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452634680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3452634680
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4278256803
Short name T876
Test name
Test status
Simulation time 53651487 ps
CPU time 0.76 seconds
Started Mar 21 12:49:44 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 205480 kb
Host smart-af9f6780-7ed1-40e6-ab5f-9d573e89136f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278256803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4278256803
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4099659022
Short name T940
Test name
Test status
Simulation time 38760748 ps
CPU time 1.47 seconds
Started Mar 21 12:49:42 PM PDT 24
Finished Mar 21 12:49:45 PM PDT 24
Peak memory 206164 kb
Host smart-f6f651aa-cb80-4445-92d4-9e1ac9cb1f4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099659022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4099659022
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.606256323
Short name T897
Test name
Test status
Simulation time 365687872 ps
CPU time 2.49 seconds
Started Mar 21 12:49:43 PM PDT 24
Finished Mar 21 12:49:46 PM PDT 24
Peak memory 214316 kb
Host smart-e9ff351c-bac7-4fe4-a143-3847b03bcecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606256323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.606256323
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3651478091
Short name T960
Test name
Test status
Simulation time 779818379 ps
CPU time 2.04 seconds
Started Mar 21 12:49:40 PM PDT 24
Finished Mar 21 12:49:42 PM PDT 24
Peak memory 205944 kb
Host smart-b9adbce5-a9b7-44c8-a025-cb18f418feaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651478091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3651478091
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3440314940
Short name T862
Test name
Test status
Simulation time 64634913 ps
CPU time 1.34 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 214244 kb
Host smart-84e14911-f082-4902-b024-7d730d4f2f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440314940 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3440314940
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1420067987
Short name T965
Test name
Test status
Simulation time 33343087 ps
CPU time 0.82 seconds
Started Mar 21 12:49:49 PM PDT 24
Finished Mar 21 12:49:50 PM PDT 24
Peak memory 205684 kb
Host smart-4a6feb68-4900-4bb4-938d-4dc1fa5d5cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420067987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1420067987
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2851066121
Short name T944
Test name
Test status
Simulation time 12913355 ps
CPU time 0.85 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205972 kb
Host smart-f7082ea2-6524-4e77-baba-18d544532a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851066121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2851066121
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3394982901
Short name T968
Test name
Test status
Simulation time 100216501 ps
CPU time 1.13 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 206064 kb
Host smart-3d4fea5d-1563-463d-81ab-d1bf48fa8ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394982901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3394982901
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1294496356
Short name T913
Test name
Test status
Simulation time 191508904 ps
CPU time 2.17 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:54 PM PDT 24
Peak memory 214448 kb
Host smart-b97b420c-1a75-47e5-8262-e63b3575de93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294496356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1294496356
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2963627395
Short name T248
Test name
Test status
Simulation time 48961238 ps
CPU time 1.61 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 206080 kb
Host smart-b8ff397a-f957-4ba3-adcc-592286263392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963627395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2963627395
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4138095757
Short name T887
Test name
Test status
Simulation time 25752428 ps
CPU time 1.28 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 214252 kb
Host smart-d0622dac-824d-4af1-99c8-1e939f978a7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138095757 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4138095757
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2980028887
Short name T933
Test name
Test status
Simulation time 24333624 ps
CPU time 0.9 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205900 kb
Host smart-65f87d72-303f-488f-af7e-2f3b3a515b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980028887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2980028887
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1372694115
Short name T851
Test name
Test status
Simulation time 25668992 ps
CPU time 0.84 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205760 kb
Host smart-c5fc78bd-2de4-44b0-b5ea-05ea14a54136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372694115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1372694115
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3909700274
Short name T221
Test name
Test status
Simulation time 40137615 ps
CPU time 1.07 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:51 PM PDT 24
Peak memory 205928 kb
Host smart-473abd4d-4f64-4504-8f2a-b6602f197288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909700274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3909700274
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4118499956
Short name T954
Test name
Test status
Simulation time 89233655 ps
CPU time 3.1 seconds
Started Mar 21 12:49:53 PM PDT 24
Finished Mar 21 12:49:56 PM PDT 24
Peak memory 214292 kb
Host smart-5b18d9ae-af2f-4146-8d6e-6e590f52002b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118499956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4118499956
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.206032545
Short name T246
Test name
Test status
Simulation time 189579317 ps
CPU time 1.63 seconds
Started Mar 21 12:49:49 PM PDT 24
Finished Mar 21 12:49:51 PM PDT 24
Peak memory 205980 kb
Host smart-88679e27-c1b2-4084-8a94-6e1671889b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206032545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.206032545
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3585831641
Short name T865
Test name
Test status
Simulation time 43965913 ps
CPU time 1.09 seconds
Started Mar 21 12:49:49 PM PDT 24
Finished Mar 21 12:49:50 PM PDT 24
Peak memory 214252 kb
Host smart-347f2aa8-cccd-4e7c-9b99-407a93d7fe69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585831641 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3585831641
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2665232930
Short name T950
Test name
Test status
Simulation time 15084486 ps
CPU time 0.87 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205828 kb
Host smart-f5ea0446-2d80-4da9-bce5-cd5201acf677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665232930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2665232930
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2313683353
Short name T868
Test name
Test status
Simulation time 22525346 ps
CPU time 0.85 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205904 kb
Host smart-9b99fd10-853e-4d16-ba1e-7843983ece1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313683353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2313683353
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3623055827
Short name T925
Test name
Test status
Simulation time 149192315 ps
CPU time 1.12 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 206044 kb
Host smart-f2e14df8-6f0c-4e6f-b7fd-3f65f553b4b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623055827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3623055827
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.810053395
Short name T963
Test name
Test status
Simulation time 69911266 ps
CPU time 1.72 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:54 PM PDT 24
Peak memory 214208 kb
Host smart-c55cb53a-73b9-427d-99ac-1e864aff7f71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810053395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.810053395
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3570020421
Short name T936
Test name
Test status
Simulation time 166345561 ps
CPU time 2.09 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205968 kb
Host smart-af99b633-7653-42c3-8bda-8d934717ead9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570020421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3570020421
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1047262228
Short name T969
Test name
Test status
Simulation time 33667070 ps
CPU time 1.44 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 214400 kb
Host smart-2c4875eb-a400-4e80-a019-1078dcd291da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047262228 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1047262228
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.323624655
Short name T214
Test name
Test status
Simulation time 18875474 ps
CPU time 0.8 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205708 kb
Host smart-ae613bda-d178-4018-9847-c78c0e6fae3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323624655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.323624655
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.327783524
Short name T941
Test name
Test status
Simulation time 44350046 ps
CPU time 0.82 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205664 kb
Host smart-caf843eb-4cae-4e98-88ec-b31b6fefa597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327783524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.327783524
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.565310348
Short name T922
Test name
Test status
Simulation time 38846661 ps
CPU time 1.1 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205956 kb
Host smart-ea2ca38b-013d-4988-8164-406c4781d049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565310348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.565310348
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1910584005
Short name T894
Test name
Test status
Simulation time 234023815 ps
CPU time 2.16 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:54 PM PDT 24
Peak memory 214400 kb
Host smart-f73f8a13-f241-45de-8f7d-326e6b4e18e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910584005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1910584005
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.556837981
Short name T902
Test name
Test status
Simulation time 55523197 ps
CPU time 1.76 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 206300 kb
Host smart-19b67292-f7a1-470e-b23c-0831d6e73a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556837981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.556837981
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2774784928
Short name T209
Test name
Test status
Simulation time 30422363 ps
CPU time 1.2 seconds
Started Mar 21 12:49:22 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 205884 kb
Host smart-d7b8bd54-341f-4b0c-b446-fd0363c71c74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774784928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2774784928
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.908900664
Short name T216
Test name
Test status
Simulation time 132585713 ps
CPU time 3.21 seconds
Started Mar 21 12:50:49 PM PDT 24
Finished Mar 21 12:50:53 PM PDT 24
Peak memory 204648 kb
Host smart-82dba0d6-66b6-4fde-bdac-544df412f2cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908900664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.908900664
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4157584999
Short name T961
Test name
Test status
Simulation time 28358469 ps
CPU time 0.9 seconds
Started Mar 21 12:49:22 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 205848 kb
Host smart-8b0e1dcd-2629-462a-912c-b1f1ad69c468
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157584999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4157584999
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3781699419
Short name T958
Test name
Test status
Simulation time 46837983 ps
CPU time 1.06 seconds
Started Mar 21 12:49:27 PM PDT 24
Finished Mar 21 12:49:28 PM PDT 24
Peak memory 214272 kb
Host smart-a3699a5b-8986-4cae-967a-76760cb0cbd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781699419 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3781699419
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2136323172
Short name T866
Test name
Test status
Simulation time 130707011 ps
CPU time 0.84 seconds
Started Mar 21 12:49:27 PM PDT 24
Finished Mar 21 12:49:28 PM PDT 24
Peak memory 205796 kb
Host smart-4f4cb9c0-29aa-445e-86f2-6629d21f9840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136323172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2136323172
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3840557512
Short name T871
Test name
Test status
Simulation time 17929559 ps
CPU time 0.83 seconds
Started Mar 21 12:49:23 PM PDT 24
Finished Mar 21 12:49:24 PM PDT 24
Peak memory 205976 kb
Host smart-54ea299a-1c95-48f7-8325-fc52aa8c72d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840557512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3840557512
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1483419278
Short name T956
Test name
Test status
Simulation time 36310552 ps
CPU time 1.4 seconds
Started Mar 21 12:49:25 PM PDT 24
Finished Mar 21 12:49:26 PM PDT 24
Peak memory 205984 kb
Host smart-a77c8056-746e-47dd-9ef6-2cbdb97c2488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483419278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1483419278
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4196136954
Short name T870
Test name
Test status
Simulation time 293499960 ps
CPU time 2.98 seconds
Started Mar 21 12:49:22 PM PDT 24
Finished Mar 21 12:49:26 PM PDT 24
Peak memory 214384 kb
Host smart-6a8b0515-21d4-4a7f-adf1-7fb4cd6c2ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196136954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4196136954
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3127926846
Short name T233
Test name
Test status
Simulation time 82142326 ps
CPU time 1.47 seconds
Started Mar 21 12:49:23 PM PDT 24
Finished Mar 21 12:49:25 PM PDT 24
Peak memory 206052 kb
Host smart-80d4f03b-53ff-4cd8-bf73-4e2ed9182acf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127926846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3127926846
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3844111920
Short name T842
Test name
Test status
Simulation time 46682084 ps
CPU time 0.81 seconds
Started Mar 21 12:49:47 PM PDT 24
Finished Mar 21 12:49:48 PM PDT 24
Peak memory 205916 kb
Host smart-090d190f-6c62-42b0-ab94-cbd4815f4785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844111920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3844111920
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.634534305
Short name T863
Test name
Test status
Simulation time 19196979 ps
CPU time 0.82 seconds
Started Mar 21 12:49:54 PM PDT 24
Finished Mar 21 12:49:55 PM PDT 24
Peak memory 205704 kb
Host smart-6c3f4aa3-6f5d-46e3-9b47-871dd9e67034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634534305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.634534305
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4282377920
Short name T918
Test name
Test status
Simulation time 25250011 ps
CPU time 0.93 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205816 kb
Host smart-098c3d61-d390-4301-b4fa-65c793f63be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282377920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4282377920
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1193388141
Short name T896
Test name
Test status
Simulation time 39042543 ps
CPU time 0.81 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205716 kb
Host smart-8fe6cf86-eb8d-4747-8ca1-e918e87f49e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193388141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1193388141
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3393420957
Short name T921
Test name
Test status
Simulation time 23276005 ps
CPU time 1.03 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205916 kb
Host smart-cbfb8c0c-8288-49f3-b3bb-9c55d4079d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393420957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3393420957
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1586587798
Short name T955
Test name
Test status
Simulation time 13281861 ps
CPU time 0.86 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205904 kb
Host smart-20c8b368-1462-4b82-8548-3ab39eac1744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586587798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1586587798
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2411246648
Short name T932
Test name
Test status
Simulation time 31891044 ps
CPU time 0.93 seconds
Started Mar 21 12:49:52 PM PDT 24
Finished Mar 21 12:49:53 PM PDT 24
Peak memory 205888 kb
Host smart-94cad38c-0b6b-47fe-8e73-c787b23d0243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411246648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2411246648
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1533222832
Short name T852
Test name
Test status
Simulation time 53915377 ps
CPU time 0.9 seconds
Started Mar 21 12:49:51 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 205836 kb
Host smart-7c129ddd-c935-455a-b482-eef3639beb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533222832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1533222832
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.244571036
Short name T860
Test name
Test status
Simulation time 15570089 ps
CPU time 0.85 seconds
Started Mar 21 12:49:49 PM PDT 24
Finished Mar 21 12:49:51 PM PDT 24
Peak memory 205844 kb
Host smart-78f5f734-8ff1-430c-8457-0c7c109a8891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244571036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.244571036
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3549247442
Short name T850
Test name
Test status
Simulation time 14735421 ps
CPU time 0.93 seconds
Started Mar 21 12:49:50 PM PDT 24
Finished Mar 21 12:49:52 PM PDT 24
Peak memory 206104 kb
Host smart-08fb29b1-278b-460c-8392-64159ae790ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549247442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3549247442
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2730064785
Short name T231
Test name
Test status
Simulation time 46231256 ps
CPU time 1.44 seconds
Started Mar 21 12:49:20 PM PDT 24
Finished Mar 21 12:49:21 PM PDT 24
Peak memory 205860 kb
Host smart-c3b36dc7-9684-4cd4-89ed-5e24b5970cc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730064785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2730064785
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3984986732
Short name T893
Test name
Test status
Simulation time 351635038 ps
CPU time 2.79 seconds
Started Mar 21 12:49:21 PM PDT 24
Finished Mar 21 12:49:24 PM PDT 24
Peak memory 205892 kb
Host smart-95fbe87e-15b3-49d2-a8e4-2b145a406129
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984986732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3984986732
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1228542433
Short name T927
Test name
Test status
Simulation time 19789807 ps
CPU time 0.95 seconds
Started Mar 21 12:49:26 PM PDT 24
Finished Mar 21 12:49:28 PM PDT 24
Peak memory 205804 kb
Host smart-c5a3f8c3-2e53-4515-8cad-33353f45a6b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228542433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1228542433
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2863777393
Short name T848
Test name
Test status
Simulation time 18157680 ps
CPU time 0.99 seconds
Started Mar 21 12:49:20 PM PDT 24
Finished Mar 21 12:49:21 PM PDT 24
Peak memory 214332 kb
Host smart-0ad7ccec-a3c0-446f-869e-8bcc5c6a235a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863777393 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2863777393
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2488561793
Short name T212
Test name
Test status
Simulation time 40281625 ps
CPU time 0.81 seconds
Started Mar 21 12:50:49 PM PDT 24
Finished Mar 21 12:50:50 PM PDT 24
Peak memory 204532 kb
Host smart-a83cc159-7b38-402d-a986-5b509d85aaa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488561793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2488561793
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1128404742
Short name T847
Test name
Test status
Simulation time 56770329 ps
CPU time 0.84 seconds
Started Mar 21 12:49:27 PM PDT 24
Finished Mar 21 12:49:28 PM PDT 24
Peak memory 205744 kb
Host smart-5a91a456-1a18-4188-adef-1f6932d27865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128404742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1128404742
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4246531744
Short name T962
Test name
Test status
Simulation time 68475956 ps
CPU time 1.09 seconds
Started Mar 21 12:49:22 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 205944 kb
Host smart-be9f570c-f18f-4f10-bc54-406c1e600ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246531744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4246531744
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3002671968
Short name T972
Test name
Test status
Simulation time 25539545 ps
CPU time 1.71 seconds
Started Mar 21 12:49:27 PM PDT 24
Finished Mar 21 12:49:29 PM PDT 24
Peak memory 214164 kb
Host smart-5c871421-d85c-4b35-843f-9b8cba1f1628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002671968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3002671968
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1911664170
Short name T904
Test name
Test status
Simulation time 42529671 ps
CPU time 1.52 seconds
Started Mar 21 12:49:21 PM PDT 24
Finished Mar 21 12:49:22 PM PDT 24
Peak memory 206056 kb
Host smart-ceb55ade-bf9c-444c-89aa-3f4eba718f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911664170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1911664170
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1897531964
Short name T946
Test name
Test status
Simulation time 37107494 ps
CPU time 0.88 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 205828 kb
Host smart-24e3da98-d591-49e6-8205-339fb1f7527c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897531964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1897531964
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1361019621
Short name T923
Test name
Test status
Simulation time 14822144 ps
CPU time 0.82 seconds
Started Mar 21 12:50:06 PM PDT 24
Finished Mar 21 12:50:07 PM PDT 24
Peak memory 205848 kb
Host smart-39cd8f51-638c-4bf7-86e8-b031000ca80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361019621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1361019621
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1344569499
Short name T855
Test name
Test status
Simulation time 33788714 ps
CPU time 0.81 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:50:05 PM PDT 24
Peak memory 205664 kb
Host smart-f0e63fec-184f-4296-b45f-1ac887439a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344569499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1344569499
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1170081075
Short name T879
Test name
Test status
Simulation time 26861005 ps
CPU time 0.88 seconds
Started Mar 21 12:50:05 PM PDT 24
Finished Mar 21 12:50:06 PM PDT 24
Peak memory 205800 kb
Host smart-93d1496f-926f-47a3-bb50-0cb2c4c7820f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170081075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1170081075
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2283345170
Short name T938
Test name
Test status
Simulation time 23775194 ps
CPU time 0.81 seconds
Started Mar 21 12:50:09 PM PDT 24
Finished Mar 21 12:50:10 PM PDT 24
Peak memory 205912 kb
Host smart-b68973a1-ad28-4f52-b0a4-59cbcba3021f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283345170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2283345170
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3265804674
Short name T957
Test name
Test status
Simulation time 81965498 ps
CPU time 0.9 seconds
Started Mar 21 12:50:05 PM PDT 24
Finished Mar 21 12:50:06 PM PDT 24
Peak memory 205836 kb
Host smart-506fed54-b197-4ecc-8bab-7e58c9d9b5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265804674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3265804674
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.713182439
Short name T935
Test name
Test status
Simulation time 46324436 ps
CPU time 0.88 seconds
Started Mar 21 12:50:05 PM PDT 24
Finished Mar 21 12:50:07 PM PDT 24
Peak memory 205808 kb
Host smart-352a6cb9-6bf2-481f-9367-c0576a296263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713182439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.713182439
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3507829383
Short name T903
Test name
Test status
Simulation time 12556097 ps
CPU time 0.82 seconds
Started Mar 21 12:50:03 PM PDT 24
Finished Mar 21 12:50:04 PM PDT 24
Peak memory 205848 kb
Host smart-26303737-7a55-443b-bef6-42d79923e6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507829383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3507829383
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.257906903
Short name T874
Test name
Test status
Simulation time 18625746 ps
CPU time 0.97 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:09 PM PDT 24
Peak memory 205852 kb
Host smart-04a748bf-8115-4c15-881e-554844079702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257906903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.257906903
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.196703720
Short name T909
Test name
Test status
Simulation time 25340061 ps
CPU time 0.96 seconds
Started Mar 21 12:50:03 PM PDT 24
Finished Mar 21 12:50:05 PM PDT 24
Peak memory 205836 kb
Host smart-86a5bf84-64aa-4576-93fe-ff0f6795dd10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196703720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.196703720
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1091182147
Short name T885
Test name
Test status
Simulation time 28201538 ps
CPU time 1.21 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205824 kb
Host smart-ed903d90-217a-4064-80ac-15f74dd18ca3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091182147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1091182147
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.545845415
Short name T867
Test name
Test status
Simulation time 265764923 ps
CPU time 3.36 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:36 PM PDT 24
Peak memory 205844 kb
Host smart-9bc4234d-deac-44df-bd11-885cc1fe3f13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545845415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.545845415
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.778873475
Short name T930
Test name
Test status
Simulation time 265712557 ps
CPU time 0.9 seconds
Started Mar 21 12:49:22 PM PDT 24
Finished Mar 21 12:49:23 PM PDT 24
Peak memory 206276 kb
Host smart-0b9730ae-9a6e-4bd9-909c-c15aee59601b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778873475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.778873475
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1416469592
Short name T846
Test name
Test status
Simulation time 183874408 ps
CPU time 1.16 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 214380 kb
Host smart-3058a32e-3388-4ed0-9971-e3b6cec54f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416469592 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1416469592
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3017404260
Short name T939
Test name
Test status
Simulation time 15981645 ps
CPU time 1 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 205824 kb
Host smart-8e19be48-80ce-4825-85a3-e2a06bedb019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017404260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3017404260
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3022668570
Short name T882
Test name
Test status
Simulation time 18852472 ps
CPU time 0.74 seconds
Started Mar 21 12:49:21 PM PDT 24
Finished Mar 21 12:49:22 PM PDT 24
Peak memory 205644 kb
Host smart-447d905d-268d-4ca0-9ad7-e764e4637d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022668570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3022668570
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1718661871
Short name T219
Test name
Test status
Simulation time 145535730 ps
CPU time 0.97 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 206084 kb
Host smart-4026e693-4fde-4920-81a5-57db00cdb722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718661871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1718661871
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.300500217
Short name T877
Test name
Test status
Simulation time 211188350 ps
CPU time 2.36 seconds
Started Mar 21 12:49:22 PM PDT 24
Finished Mar 21 12:49:24 PM PDT 24
Peak memory 214296 kb
Host smart-195f0ae7-d400-490c-a360-0b54ef28bafc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300500217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.300500217
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3639340018
Short name T857
Test name
Test status
Simulation time 163303213 ps
CPU time 1.55 seconds
Started Mar 21 12:49:25 PM PDT 24
Finished Mar 21 12:49:26 PM PDT 24
Peak memory 206020 kb
Host smart-38654911-f85a-4885-8d0b-d0bb56068253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639340018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3639340018
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2867185897
Short name T856
Test name
Test status
Simulation time 14350367 ps
CPU time 0.85 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:09 PM PDT 24
Peak memory 205828 kb
Host smart-4c523394-c7fa-482e-8acb-ecde727f6bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867185897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2867185897
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4290500838
Short name T869
Test name
Test status
Simulation time 19622706 ps
CPU time 0.83 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:50:06 PM PDT 24
Peak memory 205816 kb
Host smart-04896900-ea3a-4f4d-8a05-f5f87c09576c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290500838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4290500838
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4112254819
Short name T953
Test name
Test status
Simulation time 39533548 ps
CPU time 0.83 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:50:05 PM PDT 24
Peak memory 205664 kb
Host smart-1e1d7ba5-b4d5-439d-8fa3-66e46c379576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112254819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4112254819
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4101971167
Short name T895
Test name
Test status
Simulation time 29543286 ps
CPU time 0.9 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:09 PM PDT 24
Peak memory 205856 kb
Host smart-27c75bde-a373-4213-a520-3f32be0b8fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101971167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4101971167
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1865748095
Short name T911
Test name
Test status
Simulation time 28471907 ps
CPU time 0.82 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 205672 kb
Host smart-3d0a32e3-6ad3-432f-882b-02f584442933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865748095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1865748095
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3886708931
Short name T853
Test name
Test status
Simulation time 17160727 ps
CPU time 0.82 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 205944 kb
Host smart-d3f7cdbb-ecdd-4d44-a984-961d01a022a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886708931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3886708931
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2330526334
Short name T888
Test name
Test status
Simulation time 23753126 ps
CPU time 0.78 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:50:05 PM PDT 24
Peak memory 205644 kb
Host smart-b467dab2-8a62-4455-96e4-504cd6939da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330526334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2330526334
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3926111828
Short name T915
Test name
Test status
Simulation time 24214260 ps
CPU time 0.84 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:09 PM PDT 24
Peak memory 205828 kb
Host smart-4bc264dd-dcd0-4b9a-9bab-c82946d63518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926111828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3926111828
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3526764313
Short name T883
Test name
Test status
Simulation time 36250951 ps
CPU time 0.78 seconds
Started Mar 21 12:50:03 PM PDT 24
Finished Mar 21 12:50:04 PM PDT 24
Peak memory 205648 kb
Host smart-9aac989c-c679-4ffa-a60e-7a9172560296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526764313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3526764313
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1304137688
Short name T929
Test name
Test status
Simulation time 25496844 ps
CPU time 0.88 seconds
Started Mar 21 12:50:11 PM PDT 24
Finished Mar 21 12:50:12 PM PDT 24
Peak memory 205916 kb
Host smart-c9b74d1e-0ddf-4616-adad-b83e60169e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304137688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1304137688
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3211975506
Short name T844
Test name
Test status
Simulation time 29599181 ps
CPU time 1.04 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 214208 kb
Host smart-32119553-3fcc-4016-9278-32b6c805fc46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211975506 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3211975506
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1867796480
Short name T210
Test name
Test status
Simulation time 42041516 ps
CPU time 0.88 seconds
Started Mar 21 12:49:31 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 205852 kb
Host smart-69beebaa-46b8-4a89-aa7a-7134b07007c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867796480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1867796480
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.485855137
Short name T966
Test name
Test status
Simulation time 40361810 ps
CPU time 0.82 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205860 kb
Host smart-d802403a-53b6-411c-a92b-1671ed8fad61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485855137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.485855137
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1437219723
Short name T920
Test name
Test status
Simulation time 38135171 ps
CPU time 1.08 seconds
Started Mar 21 12:49:34 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 206024 kb
Host smart-94bb6d5c-cd7f-44f4-aab3-f69f0ca203c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437219723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1437219723
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.548713740
Short name T906
Test name
Test status
Simulation time 166755209 ps
CPU time 3.26 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:36 PM PDT 24
Peak memory 214424 kb
Host smart-f8ca0f1a-696b-41fb-b9c7-8d968693d06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548713740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.548713740
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.572327431
Short name T912
Test name
Test status
Simulation time 673724848 ps
CPU time 1.68 seconds
Started Mar 21 12:49:31 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 205976 kb
Host smart-7bd9ad8b-064a-40bc-8de7-de1787a1331c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572327431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.572327431
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1705451428
Short name T861
Test name
Test status
Simulation time 35964506 ps
CPU time 0.88 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 206056 kb
Host smart-2750a845-f50d-4428-a6f1-14150b1f20eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705451428 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1705451428
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1206294113
Short name T873
Test name
Test status
Simulation time 19921119 ps
CPU time 0.92 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 205836 kb
Host smart-308dde39-db1c-43d8-863c-39593307cbc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206294113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1206294113
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.231126253
Short name T901
Test name
Test status
Simulation time 25224843 ps
CPU time 0.81 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205728 kb
Host smart-0881c208-fd1a-4e50-bacb-f035bf541ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231126253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.231126253
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1504396217
Short name T967
Test name
Test status
Simulation time 18605542 ps
CPU time 1.13 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 206060 kb
Host smart-69639067-d921-411d-bbe0-fe38137e3437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504396217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1504396217
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4156571818
Short name T952
Test name
Test status
Simulation time 81114563 ps
CPU time 3.2 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:36 PM PDT 24
Peak memory 214308 kb
Host smart-b5f0d21e-5881-4c25-beb5-63afce262a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156571818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4156571818
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.756589202
Short name T234
Test name
Test status
Simulation time 39493518 ps
CPU time 1.49 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 206144 kb
Host smart-2441c815-d23c-4b4c-93fc-56037ff2d900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756589202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.756589202
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1636386180
Short name T886
Test name
Test status
Simulation time 43128541 ps
CPU time 1.51 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 214044 kb
Host smart-031bdaa1-59b1-4823-91a7-114403be8b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636386180 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1636386180
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2499318654
Short name T945
Test name
Test status
Simulation time 59784454 ps
CPU time 0.82 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205616 kb
Host smart-73b4ebcc-ac28-401a-8f75-ebf837acee2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499318654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2499318654
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1699529707
Short name T916
Test name
Test status
Simulation time 16619895 ps
CPU time 0.92 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 205800 kb
Host smart-2ec98d17-5f18-40fd-a9ac-9ec975670218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699529707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1699529707
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3549873274
Short name T218
Test name
Test status
Simulation time 74713693 ps
CPU time 1 seconds
Started Mar 21 12:49:30 PM PDT 24
Finished Mar 21 12:49:31 PM PDT 24
Peak memory 206016 kb
Host smart-92e99993-8911-424d-a52c-5ec61cbb0c8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549873274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3549873274
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2668629599
Short name T872
Test name
Test status
Simulation time 101428134 ps
CPU time 2.12 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 214376 kb
Host smart-b718ec82-600e-4b7c-a3ba-5b194918cc3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668629599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2668629599
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2684239948
Short name T934
Test name
Test status
Simulation time 198490563 ps
CPU time 1.65 seconds
Started Mar 21 12:49:38 PM PDT 24
Finished Mar 21 12:49:40 PM PDT 24
Peak memory 205952 kb
Host smart-c70515e1-bd58-4cc8-a31c-f8e9eb09688b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684239948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2684239948
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1549537067
Short name T970
Test name
Test status
Simulation time 25376185 ps
CPU time 1.6 seconds
Started Mar 21 12:49:35 PM PDT 24
Finished Mar 21 12:49:37 PM PDT 24
Peak memory 214164 kb
Host smart-ef800b2c-9065-4042-874d-256fa82297c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549537067 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1549537067
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3694440028
Short name T211
Test name
Test status
Simulation time 12416433 ps
CPU time 0.78 seconds
Started Mar 21 12:49:31 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 205648 kb
Host smart-0127aa22-9c3f-443d-8f4c-2dfd15babca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694440028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3694440028
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2418685573
Short name T910
Test name
Test status
Simulation time 57139659 ps
CPU time 0.96 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 205848 kb
Host smart-34b8c575-eea3-4a8a-a8ad-9426d21283ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418685573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2418685573
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2905442109
Short name T220
Test name
Test status
Simulation time 35401887 ps
CPU time 1.38 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205972 kb
Host smart-7b2bb7d6-991e-419c-a01c-9c89783ebb15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905442109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2905442109
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.579632350
Short name T864
Test name
Test status
Simulation time 754289147 ps
CPU time 4.69 seconds
Started Mar 21 12:49:31 PM PDT 24
Finished Mar 21 12:49:36 PM PDT 24
Peak memory 214296 kb
Host smart-33345d17-285c-4c6a-81bf-333920575754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579632350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.579632350
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.593745826
Short name T244
Test name
Test status
Simulation time 49730593 ps
CPU time 1.6 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:36 PM PDT 24
Peak memory 206116 kb
Host smart-3f302659-324e-4781-ad0f-97c6bd02a3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593745826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.593745826
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.641883523
Short name T890
Test name
Test status
Simulation time 50987159 ps
CPU time 1.56 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 214096 kb
Host smart-2372b58c-ff3d-45f9-8f1d-e1c67f12390d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641883523 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.641883523
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2691421746
Short name T964
Test name
Test status
Simulation time 13143782 ps
CPU time 0.87 seconds
Started Mar 21 12:49:33 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 205916 kb
Host smart-b68c4540-ba99-4a9d-aed4-2d7e237c7920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691421746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2691421746
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1409518561
Short name T859
Test name
Test status
Simulation time 14815485 ps
CPU time 0.84 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:34 PM PDT 24
Peak memory 205836 kb
Host smart-e17d1254-1b14-4a1c-b225-91a0b5681b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409518561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1409518561
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.397528349
Short name T926
Test name
Test status
Simulation time 35994044 ps
CPU time 1.4 seconds
Started Mar 21 12:49:46 PM PDT 24
Finished Mar 21 12:49:48 PM PDT 24
Peak memory 206020 kb
Host smart-fad03d18-da19-4e15-aebf-1fbed0377681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397528349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.397528349
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4067099001
Short name T919
Test name
Test status
Simulation time 77981478 ps
CPU time 2.8 seconds
Started Mar 21 12:49:32 PM PDT 24
Finished Mar 21 12:49:35 PM PDT 24
Peak memory 214556 kb
Host smart-4ac37687-58c4-4142-8f0e-ec5ce671fa86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067099001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4067099001
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2537465335
Short name T907
Test name
Test status
Simulation time 122189712 ps
CPU time 2.54 seconds
Started Mar 21 12:49:34 PM PDT 24
Finished Mar 21 12:49:37 PM PDT 24
Peak memory 205932 kb
Host smart-54a73ffc-6366-4174-85de-3dedb55a0387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537465335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2537465335
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1854825286
Short name T756
Test name
Test status
Simulation time 85575519 ps
CPU time 1.2 seconds
Started Mar 21 01:59:12 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 215744 kb
Host smart-a10d118c-2006-4287-9a7b-58e2c73cd312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854825286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1854825286
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.4221693902
Short name T404
Test name
Test status
Simulation time 32141266 ps
CPU time 0.78 seconds
Started Mar 21 01:59:11 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 205940 kb
Host smart-f378dc0b-cf86-402e-8ce2-8aa89628c2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221693902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4221693902
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3829463632
Short name T93
Test name
Test status
Simulation time 26093136 ps
CPU time 0.82 seconds
Started Mar 21 01:59:11 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 216028 kb
Host smart-2d925ce8-2fa5-4ea9-b0e7-2dc7de10bd93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829463632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3829463632
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3588648149
Short name T225
Test name
Test status
Simulation time 141593839 ps
CPU time 1.09 seconds
Started Mar 21 01:59:16 PM PDT 24
Finished Mar 21 01:59:18 PM PDT 24
Peak memory 216696 kb
Host smart-32861a43-8bbc-45a2-a3e5-07c69e4cdac8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588648149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3588648149
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3581027200
Short name T102
Test name
Test status
Simulation time 29046346 ps
CPU time 0.86 seconds
Started Mar 21 01:59:12 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 217992 kb
Host smart-49b1f33b-041a-4502-b725-bfbdf1a37461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581027200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3581027200
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2509482997
Short name T637
Test name
Test status
Simulation time 39842103 ps
CPU time 1.2 seconds
Started Mar 21 01:59:09 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 217024 kb
Host smart-bf62e410-0c82-4d46-a35a-09345e7984be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509482997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2509482997
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3874059374
Short name T21
Test name
Test status
Simulation time 359708228 ps
CPU time 5.62 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 01:59:18 PM PDT 24
Peak memory 237268 kb
Host smart-6d655bf7-b2e5-410e-828e-08e13beceece
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874059374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3874059374
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1308147488
Short name T596
Test name
Test status
Simulation time 25462085 ps
CPU time 0.91 seconds
Started Mar 21 01:59:11 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 215436 kb
Host smart-8cdff850-41c7-4989-a1a0-f32519b1fc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308147488 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1308147488
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.507062043
Short name T663
Test name
Test status
Simulation time 415717589 ps
CPU time 2.82 seconds
Started Mar 21 01:59:12 PM PDT 24
Finished Mar 21 01:59:15 PM PDT 24
Peak memory 216492 kb
Host smart-b0b761c1-34cb-4c6a-95dc-6bfde5674930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507062043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.507062043
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2947981195
Short name T726
Test name
Test status
Simulation time 188753405305 ps
CPU time 1242.83 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 02:19:55 PM PDT 24
Peak memory 224592 kb
Host smart-7f680b34-38cc-404b-b011-451349676b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947981195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2947981195
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1025944488
Short name T589
Test name
Test status
Simulation time 45829823 ps
CPU time 0.84 seconds
Started Mar 21 01:59:29 PM PDT 24
Finished Mar 21 01:59:30 PM PDT 24
Peak memory 206660 kb
Host smart-ed8a183a-34e3-4922-8035-6e41ff187040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025944488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1025944488
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.4167725011
Short name T822
Test name
Test status
Simulation time 26778488 ps
CPU time 0.76 seconds
Started Mar 21 01:59:20 PM PDT 24
Finished Mar 21 01:59:21 PM PDT 24
Peak memory 215988 kb
Host smart-bff72b57-3a11-48c4-bbdd-2ab6d92703c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167725011 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4167725011
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4158610243
Short name T571
Test name
Test status
Simulation time 20158155 ps
CPU time 0.98 seconds
Started Mar 21 01:59:20 PM PDT 24
Finished Mar 21 01:59:22 PM PDT 24
Peak memory 217808 kb
Host smart-00ae2445-43be-4458-a9f2-d39c45f431ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158610243 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4158610243
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_intr.3529944901
Short name T592
Test name
Test status
Simulation time 20971262 ps
CPU time 1.11 seconds
Started Mar 21 01:59:28 PM PDT 24
Finished Mar 21 01:59:29 PM PDT 24
Peak memory 215536 kb
Host smart-d04c41bd-050b-45a5-a606-d95d65814ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529944901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3529944901
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.578766416
Short name T693
Test name
Test status
Simulation time 55015435 ps
CPU time 0.92 seconds
Started Mar 21 01:59:23 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 207204 kb
Host smart-b200a5ab-12b2-4282-9b99-778809f29210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578766416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.578766416
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2731782064
Short name T45
Test name
Test status
Simulation time 669367837 ps
CPU time 10.64 seconds
Started Mar 21 01:59:29 PM PDT 24
Finished Mar 21 01:59:40 PM PDT 24
Peak memory 234724 kb
Host smart-c29bacfd-f65b-4d0d-8eb9-0ae82d311c67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731782064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2731782064
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2889079025
Short name T642
Test name
Test status
Simulation time 36259174 ps
CPU time 0.88 seconds
Started Mar 21 01:59:10 PM PDT 24
Finished Mar 21 01:59:13 PM PDT 24
Peak memory 207216 kb
Host smart-e0f08816-33e8-4566-8075-87ccd6435da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889079025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2889079025
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2222890533
Short name T372
Test name
Test status
Simulation time 194014007 ps
CPU time 2.48 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:25 PM PDT 24
Peak memory 218008 kb
Host smart-0a1d6415-90f5-4957-aa25-524d5fd31505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222890533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2222890533
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3091638404
Short name T191
Test name
Test status
Simulation time 236549861979 ps
CPU time 1388.42 seconds
Started Mar 21 01:59:29 PM PDT 24
Finished Mar 21 02:22:38 PM PDT 24
Peak memory 223816 kb
Host smart-c168b920-cfff-4907-8ba7-9f4942904afe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091638404 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3091638404
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.4267206776
Short name T475
Test name
Test status
Simulation time 421996900 ps
CPU time 1.7 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 215764 kb
Host smart-1d78479f-656e-438b-a9fc-419852789f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267206776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4267206776
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1141420720
Short name T576
Test name
Test status
Simulation time 40832005 ps
CPU time 0.89 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 206944 kb
Host smart-4f8c984e-f960-49be-9706-ba11806e9f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141420720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1141420720
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2542145470
Short name T405
Test name
Test status
Simulation time 15120289 ps
CPU time 0.87 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 215736 kb
Host smart-d2d429ae-d764-4fa2-9716-fff1152af5d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542145470 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2542145470
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2505323879
Short name T763
Test name
Test status
Simulation time 19329218 ps
CPU time 1.11 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 218296 kb
Host smart-48eb4703-7632-44ce-9e67-39fed816c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505323879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2505323879
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3369685458
Short name T641
Test name
Test status
Simulation time 265049240 ps
CPU time 1.26 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 217188 kb
Host smart-a673b541-0456-4dbe-a72e-c4079bcc0cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369685458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3369685458
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1580586285
Short name T16
Test name
Test status
Simulation time 23485056 ps
CPU time 1.24 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 224208 kb
Host smart-9c3e0ecb-886c-4436-84d7-a8f7993073e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580586285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1580586285
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2425887940
Short name T673
Test name
Test status
Simulation time 43090923 ps
CPU time 0.89 seconds
Started Mar 21 02:00:06 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 215420 kb
Host smart-2be0028c-9516-4bde-a2c0-3ecf1b24fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425887940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2425887940
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.335100872
Short name T203
Test name
Test status
Simulation time 415520228 ps
CPU time 4.44 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 216612 kb
Host smart-d83d8c53-43f9-4df5-a2e7-bba72cfca57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335100872 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.335100872
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2257853829
Short name T186
Test name
Test status
Simulation time 8624283740 ps
CPU time 101.8 seconds
Started Mar 21 02:00:01 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 218624 kb
Host smart-3bf60359-beed-442c-8cfd-39070ba86581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257853829 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2257853829
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.531031650
Short name T674
Test name
Test status
Simulation time 40599023 ps
CPU time 1.32 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:54 PM PDT 24
Peak memory 216704 kb
Host smart-06876aab-89f9-4c16-8893-ce07a70219e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531031650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.531031650
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3619788631
Short name T649
Test name
Test status
Simulation time 52651522 ps
CPU time 1.22 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 218144 kb
Host smart-da3b8c05-f2cb-41fb-bd3c-08a2e5877c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619788631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3619788631
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1086588449
Short name T724
Test name
Test status
Simulation time 46968539 ps
CPU time 1.18 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216860 kb
Host smart-aa66c0d9-162d-4d20-bf31-c26646648816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086588449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1086588449
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.250927315
Short name T369
Test name
Test status
Simulation time 37065120 ps
CPU time 1.42 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216552 kb
Host smart-add10cf4-c06f-4af9-bd49-9c243fd94c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250927315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.250927315
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3848046229
Short name T515
Test name
Test status
Simulation time 31963113 ps
CPU time 1.24 seconds
Started Mar 21 02:01:58 PM PDT 24
Finished Mar 21 02:01:59 PM PDT 24
Peak memory 216740 kb
Host smart-0426ba08-a826-412d-bcaf-9b9a40a8c411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848046229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3848046229
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.994517843
Short name T659
Test name
Test status
Simulation time 95064214 ps
CPU time 1.09 seconds
Started Mar 21 02:01:57 PM PDT 24
Finished Mar 21 02:01:58 PM PDT 24
Peak memory 216768 kb
Host smart-53802a58-11c1-41e1-93f8-70b568eddc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994517843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.994517843
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3069776178
Short name T797
Test name
Test status
Simulation time 41014038 ps
CPU time 1.21 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 218112 kb
Host smart-863d3c96-dccc-43e3-ac24-1e34f5e6e574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069776178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3069776178
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1787324421
Short name T658
Test name
Test status
Simulation time 30702857 ps
CPU time 1.26 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 215804 kb
Host smart-fd033a28-ef2f-4421-bee5-1de923c3a822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787324421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1787324421
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1265580883
Short name T440
Test name
Test status
Simulation time 13944454 ps
CPU time 0.99 seconds
Started Mar 21 02:00:05 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 206156 kb
Host smart-f6194c0b-dfa3-4701-be75-2fff1790fafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265580883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1265580883
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3749396973
Short name T588
Test name
Test status
Simulation time 42124124 ps
CPU time 0.9 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 215680 kb
Host smart-3627be88-65f4-4bac-97a1-95d99086e30f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749396973 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3749396973
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2778029500
Short name T91
Test name
Test status
Simulation time 21247624 ps
CPU time 0.91 seconds
Started Mar 21 02:00:05 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 218036 kb
Host smart-b07268b7-2ba4-451f-891e-00d9ea46f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778029500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2778029500
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3529494178
Short name T406
Test name
Test status
Simulation time 96211788 ps
CPU time 2.1 seconds
Started Mar 21 02:00:05 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 218864 kb
Host smart-a7e7ff51-48c0-4e9f-89df-fa4c384636d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529494178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3529494178
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2060320667
Short name T125
Test name
Test status
Simulation time 20227168 ps
CPU time 1.05 seconds
Started Mar 21 02:00:01 PM PDT 24
Finished Mar 21 02:00:02 PM PDT 24
Peak memory 216076 kb
Host smart-b610518f-9e85-4a02-9af6-430df01258d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060320667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2060320667
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3618970377
Short name T629
Test name
Test status
Simulation time 79062882 ps
CPU time 0.91 seconds
Started Mar 21 02:00:06 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 215400 kb
Host smart-ad0cf847-1418-47f0-b747-451fa7854bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618970377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3618970377
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2689300876
Short name T825
Test name
Test status
Simulation time 61927117017 ps
CPU time 1351.64 seconds
Started Mar 21 02:00:05 PM PDT 24
Finished Mar 21 02:22:37 PM PDT 24
Peak memory 223892 kb
Host smart-de381aed-1c39-4db3-9551-108badd10523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689300876 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2689300876
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1584840486
Short name T49
Test name
Test status
Simulation time 48529919 ps
CPU time 1.5 seconds
Started Mar 21 02:01:56 PM PDT 24
Finished Mar 21 02:01:58 PM PDT 24
Peak memory 218676 kb
Host smart-7cf94ccd-9c7d-4f85-8bd6-00c12ee29ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584840486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1584840486
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2315341917
Short name T581
Test name
Test status
Simulation time 74437697 ps
CPU time 1.28 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:54 PM PDT 24
Peak memory 216776 kb
Host smart-951b4b48-7a13-4ec9-856c-746601e4e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315341917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2315341917
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1353090810
Short name T741
Test name
Test status
Simulation time 46901278 ps
CPU time 1.46 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 217780 kb
Host smart-13a8c9fc-4e81-498c-8c44-0cc915410941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353090810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1353090810
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3504645217
Short name T441
Test name
Test status
Simulation time 84445906 ps
CPU time 1.09 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216816 kb
Host smart-2855ece7-7256-4117-bb66-e751346f5456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504645217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3504645217
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2052038882
Short name T353
Test name
Test status
Simulation time 584898447 ps
CPU time 4.68 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:57 PM PDT 24
Peak memory 217136 kb
Host smart-461e8c96-aedd-46ad-b070-c0e8e11975ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052038882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2052038882
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3562239790
Short name T697
Test name
Test status
Simulation time 100339735 ps
CPU time 0.95 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216580 kb
Host smart-5279b7b5-5f89-402a-a59d-a9a1f06d8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562239790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3562239790
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3914193707
Short name T757
Test name
Test status
Simulation time 91584855 ps
CPU time 1.55 seconds
Started Mar 21 02:01:55 PM PDT 24
Finished Mar 21 02:01:57 PM PDT 24
Peak memory 216928 kb
Host smart-dbe2e671-9b75-4646-8944-53ed959865df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914193707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3914193707
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3053688329
Short name T308
Test name
Test status
Simulation time 68627716 ps
CPU time 1.1 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216676 kb
Host smart-d8a31b61-cb88-43f4-9212-59ab7a7f879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053688329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3053688329
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3636457070
Short name T289
Test name
Test status
Simulation time 59169162 ps
CPU time 1.35 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 218184 kb
Host smart-19d88e05-72e9-4850-8ff1-bba932f4ce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636457070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3636457070
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.67340196
Short name T700
Test name
Test status
Simulation time 95878379 ps
CPU time 1.28 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 219484 kb
Host smart-26faf02e-3caf-4572-96b4-119be4cbebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67340196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.67340196
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1810586710
Short name T94
Test name
Test status
Simulation time 75527616 ps
CPU time 1.15 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 215800 kb
Host smart-b07c1401-57c1-434f-b932-d2cd7de47f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810586710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1810586710
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3582515841
Short name T336
Test name
Test status
Simulation time 17073738 ps
CPU time 0.92 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 206188 kb
Host smart-e96015e4-2861-4633-bb3f-4dc8c1c41ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582515841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3582515841
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.728817060
Short name T772
Test name
Test status
Simulation time 13072954 ps
CPU time 0.94 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 216128 kb
Host smart-a12b0a71-24e5-4092-8ce8-571c30ded748
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728817060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.728817060
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1450990656
Short name T172
Test name
Test status
Simulation time 83625320 ps
CPU time 1.09 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:03 PM PDT 24
Peak memory 216664 kb
Host smart-88f7550a-938d-44e4-8ed8-eaf512812b41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450990656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1450990656
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.1999929452
Short name T635
Test name
Test status
Simulation time 37013263 ps
CPU time 1.4 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:06 PM PDT 24
Peak memory 216820 kb
Host smart-8c72c046-8c3a-40be-9257-e1f08f3ff87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999929452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1999929452
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.766295651
Short name T487
Test name
Test status
Simulation time 35686703 ps
CPU time 0.88 seconds
Started Mar 21 02:00:01 PM PDT 24
Finished Mar 21 02:00:02 PM PDT 24
Peak memory 215536 kb
Host smart-f9bde94d-2281-41c2-b549-82fdc5118ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766295651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.766295651
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1498436307
Short name T337
Test name
Test status
Simulation time 142607676 ps
CPU time 0.97 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 215436 kb
Host smart-516343a9-b187-42df-9473-899c258172b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498436307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1498436307
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2238106181
Short name T667
Test name
Test status
Simulation time 322780818 ps
CPU time 6.22 seconds
Started Mar 21 02:00:01 PM PDT 24
Finished Mar 21 02:00:07 PM PDT 24
Peak memory 216576 kb
Host smart-c8a89b3e-8a13-47a8-9d08-c57597d45a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238106181 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2238106181
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2237241511
Short name T638
Test name
Test status
Simulation time 26519093638 ps
CPU time 338.75 seconds
Started Mar 21 02:00:00 PM PDT 24
Finished Mar 21 02:05:39 PM PDT 24
Peak memory 217580 kb
Host smart-efae0ff7-0f72-4b86-95e4-ed7b293e7000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237241511 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2237241511
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3592761283
Short name T444
Test name
Test status
Simulation time 78000588 ps
CPU time 1.2 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 218356 kb
Host smart-acf68436-03ec-4638-a088-72dc4dab0295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592761283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3592761283
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3704705302
Short name T711
Test name
Test status
Simulation time 48214685 ps
CPU time 1.77 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:54 PM PDT 24
Peak memory 217904 kb
Host smart-b8abf337-9753-43c7-af02-189754c52efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704705302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3704705302
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1222016421
Short name T490
Test name
Test status
Simulation time 134154209 ps
CPU time 3.18 seconds
Started Mar 21 02:01:55 PM PDT 24
Finished Mar 21 02:01:58 PM PDT 24
Peak memory 218576 kb
Host smart-a4b58de7-0c34-447d-a770-b25c476381e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222016421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1222016421
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2491487874
Short name T450
Test name
Test status
Simulation time 264712201 ps
CPU time 1.14 seconds
Started Mar 21 02:01:55 PM PDT 24
Finished Mar 21 02:01:56 PM PDT 24
Peak memory 216864 kb
Host smart-6d1f7970-bd1a-4af4-825b-cf943fab9d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491487874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2491487874
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2481592786
Short name T594
Test name
Test status
Simulation time 48583808 ps
CPU time 1.51 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 217760 kb
Host smart-07d0f982-ca1f-4690-ade6-6c9e7fb7f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481592786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2481592786
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2054773089
Short name T838
Test name
Test status
Simulation time 61285569 ps
CPU time 1.64 seconds
Started Mar 21 02:01:56 PM PDT 24
Finished Mar 21 02:01:57 PM PDT 24
Peak memory 218108 kb
Host smart-5e009ae6-1d35-4f15-8ff2-8973ea33a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054773089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2054773089
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.4238840410
Short name T465
Test name
Test status
Simulation time 161584316 ps
CPU time 2.57 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216996 kb
Host smart-ca59400d-a4cb-4cda-b668-7e30c21011f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238840410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4238840410
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2559262159
Short name T448
Test name
Test status
Simulation time 58522703 ps
CPU time 1.19 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:52 PM PDT 24
Peak memory 217916 kb
Host smart-5585bd9e-770b-49f9-a92b-c50cd7558e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559262159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2559262159
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2657075511
Short name T722
Test name
Test status
Simulation time 37495850 ps
CPU time 1.39 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 216668 kb
Host smart-12f4fd1b-e824-4c2a-b167-0556d743670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657075511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2657075511
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3539953089
Short name T752
Test name
Test status
Simulation time 52850438 ps
CPU time 1.29 seconds
Started Mar 21 02:01:57 PM PDT 24
Finished Mar 21 02:01:58 PM PDT 24
Peak memory 216588 kb
Host smart-609d57cb-18ff-4055-ade2-3a52ae3cd13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539953089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3539953089
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2874368690
Short name T99
Test name
Test status
Simulation time 397638691 ps
CPU time 1.27 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 215776 kb
Host smart-b9e13409-e76f-4902-8963-dc899ad6795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874368690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2874368690
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1802629902
Short name T338
Test name
Test status
Simulation time 19778615 ps
CPU time 0.96 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 206676 kb
Host smart-1c54829a-da92-4eee-ae6b-2bdb8cf5b200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802629902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1802629902
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3097395005
Short name T156
Test name
Test status
Simulation time 11715732 ps
CPU time 0.9 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:03 PM PDT 24
Peak memory 216016 kb
Host smart-8135b368-d3f8-4adf-b117-c8d0c4823b24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097395005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3097395005
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4261298154
Short name T538
Test name
Test status
Simulation time 100092890 ps
CPU time 1.16 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 217976 kb
Host smart-b210ba8f-cbb2-4459-9ecd-f781b8789b6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261298154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4261298154
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3854704950
Short name T774
Test name
Test status
Simulation time 21566615 ps
CPU time 1.11 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 219660 kb
Host smart-c70ab45b-5ee5-444d-8ed4-6fc6af337351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854704950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3854704950
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2811963418
Short name T839
Test name
Test status
Simulation time 54256958 ps
CPU time 1.05 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 219000 kb
Host smart-6786ed5d-e163-40df-b146-4ba4cff806e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811963418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2811963418
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.327524227
Short name T701
Test name
Test status
Simulation time 24575213 ps
CPU time 0.92 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 215880 kb
Host smart-4d4c57f1-8fe3-4646-afb0-d05720fb0ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327524227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.327524227
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1575803761
Short name T727
Test name
Test status
Simulation time 16607819 ps
CPU time 1.06 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:03 PM PDT 24
Peak memory 215420 kb
Host smart-5738d2e9-ce88-4f99-861c-878a0edfd42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575803761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1575803761
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2530359126
Short name T687
Test name
Test status
Simulation time 764881472 ps
CPU time 4.46 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:00:08 PM PDT 24
Peak memory 215408 kb
Host smart-13974cef-f18a-4e2e-b495-c5479693de4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530359126 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2530359126
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2536275342
Short name T469
Test name
Test status
Simulation time 48930341394 ps
CPU time 1306.34 seconds
Started Mar 21 02:00:03 PM PDT 24
Finished Mar 21 02:21:50 PM PDT 24
Peak memory 223836 kb
Host smart-479d5938-ee0c-42cd-957c-53a8f7192d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536275342 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2536275342
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1631073402
Short name T329
Test name
Test status
Simulation time 134137420 ps
CPU time 2.66 seconds
Started Mar 21 02:01:57 PM PDT 24
Finished Mar 21 02:01:59 PM PDT 24
Peak memory 219160 kb
Host smart-41c453d5-72c1-4247-aaec-8289537b1e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631073402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1631073402
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1143427372
Short name T498
Test name
Test status
Simulation time 48404731 ps
CPU time 1.75 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:56 PM PDT 24
Peak memory 217820 kb
Host smart-fb95ffeb-d3c6-438a-8647-6c4986e98404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143427372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1143427372
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1646670551
Short name T176
Test name
Test status
Simulation time 86984951 ps
CPU time 1.34 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 218068 kb
Host smart-72b1fe0c-b9d2-4f7a-be77-77ae7af3cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646670551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1646670551
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3906797044
Short name T177
Test name
Test status
Simulation time 149824268 ps
CPU time 1.77 seconds
Started Mar 21 02:01:57 PM PDT 24
Finished Mar 21 02:01:59 PM PDT 24
Peak memory 218316 kb
Host smart-cecc6d05-d7cb-4bd4-90e2-aa3f0de80073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906797044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3906797044
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.284850145
Short name T344
Test name
Test status
Simulation time 68298109 ps
CPU time 1.11 seconds
Started Mar 21 02:01:59 PM PDT 24
Finished Mar 21 02:02:00 PM PDT 24
Peak memory 218100 kb
Host smart-008f5d79-10b9-4ebb-b093-0b78602e3c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284850145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.284850145
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2504058953
Short name T290
Test name
Test status
Simulation time 48899005 ps
CPU time 1.37 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 218164 kb
Host smart-21890693-d40c-4f01-bb68-daf6707f5b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504058953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2504058953
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1904596016
Short name T626
Test name
Test status
Simulation time 121388982 ps
CPU time 1.76 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 219584 kb
Host smart-e3eb9354-62b5-448a-8e5f-89407e85c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904596016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1904596016
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1252844055
Short name T819
Test name
Test status
Simulation time 74569819 ps
CPU time 1.35 seconds
Started Mar 21 02:01:55 PM PDT 24
Finished Mar 21 02:01:56 PM PDT 24
Peak memory 218544 kb
Host smart-692eed51-4187-4233-81ed-d87a590275ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252844055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1252844055
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.459899
Short name T633
Test name
Test status
Simulation time 121300281 ps
CPU time 1.66 seconds
Started Mar 21 02:01:57 PM PDT 24
Finished Mar 21 02:01:59 PM PDT 24
Peak memory 218272 kb
Host smart-c5e3e83b-e6a7-490a-b9f3-70f9206d74d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.459899
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.2225086195
Short name T567
Test name
Test status
Simulation time 39763043 ps
CPU time 1.2 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 216744 kb
Host smart-be9dd6b2-84c9-40b5-a289-41f2579c8940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225086195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2225086195
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.887676859
Short name T178
Test name
Test status
Simulation time 44536371 ps
CPU time 1.23 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 215792 kb
Host smart-a998d2ae-e6ed-4bc2-8149-7327891627f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887676859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.887676859
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3142198538
Short name T526
Test name
Test status
Simulation time 46449430 ps
CPU time 0.82 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 206672 kb
Host smart-ac43d469-7ed4-4168-aa71-4e4d00eecda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142198538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3142198538
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1066623433
Short name T597
Test name
Test status
Simulation time 100056006 ps
CPU time 1.14 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 217760 kb
Host smart-1777a9a6-7f1e-491b-838b-b79f88e61cfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066623433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1066623433
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2136996983
Short name T6
Test name
Test status
Simulation time 60314383 ps
CPU time 1.08 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 229956 kb
Host smart-9907280a-bd79-43d3-9493-15b6b57c55a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136996983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2136996983
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.4181267213
Short name T609
Test name
Test status
Simulation time 36281177 ps
CPU time 1.59 seconds
Started Mar 21 02:00:21 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 217948 kb
Host smart-d6016d31-5ada-411b-aaf2-eef658276bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181267213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4181267213
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2009190458
Short name T121
Test name
Test status
Simulation time 25869645 ps
CPU time 0.93 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 215856 kb
Host smart-6eaf6b7e-e277-4e1a-8edc-51bd0dd09758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009190458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2009190458
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2484001370
Short name T742
Test name
Test status
Simulation time 35305929 ps
CPU time 0.93 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 215428 kb
Host smart-d1fb0f81-d63b-470e-b17f-5bf64c38a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484001370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2484001370
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.184838991
Short name T40
Test name
Test status
Simulation time 100772019 ps
CPU time 1.12 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 206308 kb
Host smart-9186a318-e625-424f-8988-c4bf3ac4f253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184838991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.184838991
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.953800030
Short name T688
Test name
Test status
Simulation time 57490419509 ps
CPU time 889.54 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:15:07 PM PDT 24
Peak memory 223860 kb
Host smart-c0665b72-6d9d-409f-b0a3-bf9f24dd3f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953800030 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.953800030
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3041629859
Short name T751
Test name
Test status
Simulation time 28037894 ps
CPU time 1.4 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 216972 kb
Host smart-532e2f79-3857-4949-87d8-f48263401868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041629859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3041629859
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2462657471
Short name T696
Test name
Test status
Simulation time 64713786 ps
CPU time 1.48 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:56 PM PDT 24
Peak memory 217940 kb
Host smart-6b3632eb-c074-4b81-934b-bc1698802fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462657471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2462657471
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2331093227
Short name T531
Test name
Test status
Simulation time 115526719 ps
CPU time 1.3 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:54 PM PDT 24
Peak memory 216744 kb
Host smart-30b86cbc-8a84-4a5c-9f51-dbc7b03d02c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331093227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2331093227
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.102904749
Short name T439
Test name
Test status
Simulation time 58177572 ps
CPU time 1.33 seconds
Started Mar 21 02:01:53 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 215540 kb
Host smart-5ac3d0ae-ceb9-45ad-9ab0-91de1f201d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102904749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.102904749
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3162193110
Short name T452
Test name
Test status
Simulation time 49096820 ps
CPU time 1.12 seconds
Started Mar 21 02:01:57 PM PDT 24
Finished Mar 21 02:01:58 PM PDT 24
Peak memory 216900 kb
Host smart-7fa180d6-1dbf-4281-83a4-4a5134513733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162193110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3162193110
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3206616992
Short name T354
Test name
Test status
Simulation time 76855694 ps
CPU time 1.26 seconds
Started Mar 21 02:01:54 PM PDT 24
Finished Mar 21 02:01:55 PM PDT 24
Peak memory 219520 kb
Host smart-58aa6ae7-baa5-4663-bf40-e06152f6bc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206616992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3206616992
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.4066018336
Short name T55
Test name
Test status
Simulation time 45259485 ps
CPU time 1.58 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 218136 kb
Host smart-8e5aaa95-0dfc-45f3-80c8-86e0951a6150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066018336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.4066018336
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2834283252
Short name T11
Test name
Test status
Simulation time 95063358 ps
CPU time 1.22 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 218664 kb
Host smart-7b7177c4-66c0-4d06-ba60-a576ce190a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834283252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2834283252
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2359656510
Short name T454
Test name
Test status
Simulation time 59621728 ps
CPU time 1.32 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 217968 kb
Host smart-8670f05a-1d63-4fdd-becd-96e5bd9e189e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359656510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2359656510
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1059534034
Short name T758
Test name
Test status
Simulation time 286829146 ps
CPU time 1.43 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 218092 kb
Host smart-6ca772a7-c81f-4b01-91e8-19f4479464de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059534034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1059534034
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.1340948294
Short name T466
Test name
Test status
Simulation time 37068683 ps
CPU time 0.85 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 206072 kb
Host smart-28d65ec0-393c-4da1-a541-4535b0dad33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340948294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1340948294
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2463766634
Short name T580
Test name
Test status
Simulation time 52319095 ps
CPU time 0.81 seconds
Started Mar 21 02:00:14 PM PDT 24
Finished Mar 21 02:00:15 PM PDT 24
Peak memory 215616 kb
Host smart-fb432c7b-f7d3-4866-8781-eb8b724a8ad7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463766634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2463766634
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2823380128
Short name T769
Test name
Test status
Simulation time 162174289 ps
CPU time 1.21 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 216648 kb
Host smart-672a8c5d-948c-4a3c-ac97-6e8a0126d318
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823380128 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2823380128
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.4148093188
Short name T167
Test name
Test status
Simulation time 40898947 ps
CPU time 1.13 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 219468 kb
Host smart-eda78fa1-c40f-4aaf-add6-83d1c6504a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148093188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.4148093188
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.4164996253
Short name T556
Test name
Test status
Simulation time 46791624 ps
CPU time 1.34 seconds
Started Mar 21 02:00:20 PM PDT 24
Finished Mar 21 02:00:21 PM PDT 24
Peak memory 218244 kb
Host smart-809b8ad5-2514-4c52-803b-acc93400c4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164996253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4164996253
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2315830797
Short name T126
Test name
Test status
Simulation time 25298988 ps
CPU time 0.9 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 215884 kb
Host smart-dda55de9-b40d-43b5-b473-04c42f146ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315830797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2315830797
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3566180182
Short name T502
Test name
Test status
Simulation time 52129454 ps
CPU time 0.94 seconds
Started Mar 21 02:00:20 PM PDT 24
Finished Mar 21 02:00:21 PM PDT 24
Peak memory 215260 kb
Host smart-ffbc7ea7-65b4-49c5-97eb-86827382b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566180182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3566180182
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1382596973
Short name T197
Test name
Test status
Simulation time 91962391905 ps
CPU time 2137.2 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:35:56 PM PDT 24
Peak memory 227032 kb
Host smart-a8095df1-b3db-40b1-b1ba-5c27072a7bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382596973 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1382596973
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1952978628
Short name T681
Test name
Test status
Simulation time 31178328 ps
CPU time 1.29 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:11 PM PDT 24
Peak memory 219388 kb
Host smart-8d0205f7-e35b-4a7b-8b99-0b927b185805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952978628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1952978628
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3053872144
Short name T328
Test name
Test status
Simulation time 104723117 ps
CPU time 1.11 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 217036 kb
Host smart-6efa3f6d-884b-4a56-819b-d06f629bfe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053872144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3053872144
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3672367352
Short name T582
Test name
Test status
Simulation time 112735242 ps
CPU time 2.64 seconds
Started Mar 21 02:02:04 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 219688 kb
Host smart-5672496c-879f-427e-bd5c-e2247588f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672367352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3672367352
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2829184695
Short name T520
Test name
Test status
Simulation time 28027781 ps
CPU time 1.07 seconds
Started Mar 21 02:02:05 PM PDT 24
Finished Mar 21 02:02:06 PM PDT 24
Peak memory 216764 kb
Host smart-bf3cb3df-fcdc-4c95-9937-6ac91a0913d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829184695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2829184695
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2876725738
Short name T500
Test name
Test status
Simulation time 106903143 ps
CPU time 1.14 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 216860 kb
Host smart-1ab2911f-0dfe-40f0-8dfa-ebc540a18b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876725738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2876725738
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2907452182
Short name T631
Test name
Test status
Simulation time 224026280 ps
CPU time 3.29 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:11 PM PDT 24
Peak memory 218128 kb
Host smart-91800c9b-628a-4b9f-986b-b15773adcfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907452182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2907452182
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.594245476
Short name T467
Test name
Test status
Simulation time 44282620 ps
CPU time 1.7 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 218272 kb
Host smart-2c445c70-5204-4a58-9d76-16d62d1ecdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594245476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.594245476
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1126209964
Short name T739
Test name
Test status
Simulation time 116911491 ps
CPU time 1.79 seconds
Started Mar 21 02:02:11 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 218048 kb
Host smart-565c4618-c190-46ab-b5bd-c4d67f90c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126209964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1126209964
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1098011610
Short name T599
Test name
Test status
Simulation time 97212070 ps
CPU time 1.41 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:11 PM PDT 24
Peak memory 216880 kb
Host smart-f807450e-9aec-412d-ae6a-dce9b2718a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098011610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1098011610
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.702413142
Short name T814
Test name
Test status
Simulation time 60698509 ps
CPU time 1.14 seconds
Started Mar 21 02:02:14 PM PDT 24
Finished Mar 21 02:02:15 PM PDT 24
Peak memory 216800 kb
Host smart-f18cc092-d0a8-4029-9ee8-9f4e04e88587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702413142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.702413142
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.717363959
Short name T237
Test name
Test status
Simulation time 107148524 ps
CPU time 1.22 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 215700 kb
Host smart-6acde12a-67d8-47b4-aed8-fae41556bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717363959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.717363959
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3192853673
Short name T348
Test name
Test status
Simulation time 24651831 ps
CPU time 0.89 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 207016 kb
Host smart-8214c1b4-7ea8-4af0-a0a8-2eaeb36d5bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192853673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3192853673
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2729938525
Short name T326
Test name
Test status
Simulation time 32203385 ps
CPU time 0.8 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 217536 kb
Host smart-2a441310-08fb-449b-9e36-b5f80cd5adfa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729938525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2729938525
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2989422630
Short name T74
Test name
Test status
Simulation time 51912253 ps
CPU time 1.14 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 216552 kb
Host smart-32f6c044-adb6-439f-a7c6-c4b430bd5650
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989422630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2989422630
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.264245668
Short name T72
Test name
Test status
Simulation time 65140313 ps
CPU time 1.04 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 219480 kb
Host smart-552ea399-de51-42c8-a994-20b46671535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264245668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.264245668
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1487747344
Short name T419
Test name
Test status
Simulation time 23434520 ps
CPU time 1.16 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 218912 kb
Host smart-e18011c5-a7f2-4656-94a8-8746d25a8f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487747344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1487747344
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4201881885
Short name T547
Test name
Test status
Simulation time 32808062 ps
CPU time 1.11 seconds
Started Mar 21 02:00:22 PM PDT 24
Finished Mar 21 02:00:23 PM PDT 24
Peak memory 224136 kb
Host smart-dd3d3ed9-e8b6-49fb-a926-da649b908aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201881885 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4201881885
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2177600080
Short name T632
Test name
Test status
Simulation time 18072731 ps
CPU time 1 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 215404 kb
Host smart-2f1c7ef8-bda7-4a45-ae13-5ada4dc47469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177600080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2177600080
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.115214584
Short name T611
Test name
Test status
Simulation time 346317153 ps
CPU time 2.54 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 216576 kb
Host smart-53c8743b-daab-414d-b547-2addd11ceadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115214584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.115214584
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2801503671
Short name T791
Test name
Test status
Simulation time 804781927685 ps
CPU time 2288.73 seconds
Started Mar 21 02:00:14 PM PDT 24
Finished Mar 21 02:38:23 PM PDT 24
Peak memory 225096 kb
Host smart-9f205f96-53a0-429d-a489-25251b977c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801503671 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2801503671
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.514240227
Short name T491
Test name
Test status
Simulation time 70964047 ps
CPU time 1.11 seconds
Started Mar 21 02:02:05 PM PDT 24
Finished Mar 21 02:02:06 PM PDT 24
Peak memory 216816 kb
Host smart-05d3f086-97e2-4bd2-9cbb-3c47049db295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514240227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.514240227
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1749128135
Short name T712
Test name
Test status
Simulation time 48879057 ps
CPU time 1.19 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 217032 kb
Host smart-e057a781-6e2b-4aea-8632-a3e0251d605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749128135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1749128135
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3659301771
Short name T240
Test name
Test status
Simulation time 66350314 ps
CPU time 1.3 seconds
Started Mar 21 02:02:10 PM PDT 24
Finished Mar 21 02:02:11 PM PDT 24
Peak memory 216760 kb
Host smart-95104d15-54ab-4c18-af83-6f859b7f9fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659301771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3659301771
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1530845123
Short name T718
Test name
Test status
Simulation time 55875140 ps
CPU time 1.24 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 216632 kb
Host smart-90888e7b-10f8-4e80-a409-908633638d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530845123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1530845123
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4112098142
Short name T574
Test name
Test status
Simulation time 70811111 ps
CPU time 1.47 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 217844 kb
Host smart-bce90a96-4f88-4d65-9546-6960a4b92c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112098142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4112098142
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3267089529
Short name T339
Test name
Test status
Simulation time 42261392 ps
CPU time 1.58 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 217956 kb
Host smart-6f78c838-47d3-4668-90da-916a0cd21afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267089529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3267089529
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2927890688
Short name T479
Test name
Test status
Simulation time 54461794 ps
CPU time 1.27 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 217988 kb
Host smart-06eff87d-f858-4f56-bd92-202a22c70b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927890688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2927890688
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.231426358
Short name T132
Test name
Test status
Simulation time 92157878 ps
CPU time 1.15 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 219552 kb
Host smart-77672a95-2efe-41d9-9af1-1e2587196156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231426358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.231426358
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3074846496
Short name T315
Test name
Test status
Simulation time 43121157 ps
CPU time 1.21 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 216644 kb
Host smart-809c36d6-497c-463f-b2e0-101192fe3bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074846496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3074846496
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.1507636250
Short name T148
Test name
Test status
Simulation time 34310567 ps
CPU time 0.99 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 206668 kb
Host smart-1ee09323-d9c8-4e34-ad8b-3ddaa35d6b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507636250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1507636250
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.583466882
Short name T643
Test name
Test status
Simulation time 17994632 ps
CPU time 0.83 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 215664 kb
Host smart-4f2e60fa-9954-4ec3-95c6-f64a14fcd27e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583466882 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.583466882
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.762221557
Short name T73
Test name
Test status
Simulation time 51267963 ps
CPU time 1.02 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 219548 kb
Host smart-99c918bc-f6c0-48a9-b9be-214f7744c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762221557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.762221557
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1817901598
Short name T699
Test name
Test status
Simulation time 70913428 ps
CPU time 1.38 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 218068 kb
Host smart-222932b5-2c20-47e0-9cb5-75827295e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817901598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1817901598
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.2146104415
Short name T376
Test name
Test status
Simulation time 34836902 ps
CPU time 0.9 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 215692 kb
Host smart-afc56e73-7e9d-443b-a4e2-6012849d61fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146104415 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2146104415
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4086667584
Short name T551
Test name
Test status
Simulation time 56503184 ps
CPU time 0.92 seconds
Started Mar 21 02:00:21 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 215428 kb
Host smart-aa7b7bb1-7b38-4636-abc8-3ef3994cf14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086667584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4086667584
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1343770015
Short name T322
Test name
Test status
Simulation time 19862475 ps
CPU time 1.08 seconds
Started Mar 21 02:00:21 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 215448 kb
Host smart-79367c61-51d6-40bc-b4dc-cad2756a82fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343770015 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1343770015
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1096587036
Short name T823
Test name
Test status
Simulation time 41227370317 ps
CPU time 985.35 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:16:44 PM PDT 24
Peak memory 218892 kb
Host smart-f9ff72db-dc13-4f48-8f95-8bb1c9649183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096587036 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1096587036
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3946790946
Short name T327
Test name
Test status
Simulation time 90199184 ps
CPU time 1.18 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 218416 kb
Host smart-67176c2e-c5e4-4836-a4ef-8462afbae2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946790946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3946790946
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1799583190
Short name T341
Test name
Test status
Simulation time 52452094 ps
CPU time 1.22 seconds
Started Mar 21 02:02:05 PM PDT 24
Finished Mar 21 02:02:06 PM PDT 24
Peak memory 218104 kb
Host smart-6685f16e-de39-4182-a979-d6926d97110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799583190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1799583190
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3869707864
Short name T3
Test name
Test status
Simulation time 24521939 ps
CPU time 1.14 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 217888 kb
Host smart-2005725b-6ce3-41b4-be1e-48b7fd21c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869707864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3869707864
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3686628511
Short name T612
Test name
Test status
Simulation time 36774742 ps
CPU time 1.41 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 217828 kb
Host smart-3b213c17-ab58-4867-aaa7-01e19b4545c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686628511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3686628511
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.483110451
Short name T750
Test name
Test status
Simulation time 53935149 ps
CPU time 1.39 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 218160 kb
Host smart-77f1159b-dc99-4979-b8cb-7675448146a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483110451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.483110451
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2056197693
Short name T366
Test name
Test status
Simulation time 168611226 ps
CPU time 1.62 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 218056 kb
Host smart-57565e8d-c094-4e27-b28f-81d6a2712199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056197693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2056197693
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.10610739
Short name T319
Test name
Test status
Simulation time 74904686 ps
CPU time 1.23 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 216640 kb
Host smart-1e37373b-d00c-4a1f-879b-276198909274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10610739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.10610739
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.934300469
Short name T457
Test name
Test status
Simulation time 40658275 ps
CPU time 1.28 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:16 PM PDT 24
Peak memory 215792 kb
Host smart-f5633236-1067-43ba-9ecf-ed3758e8cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934300469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.934300469
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3750713936
Short name T686
Test name
Test status
Simulation time 24187536 ps
CPU time 0.9 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 206108 kb
Host smart-ec77f678-80f5-4a66-8c67-85307c320952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750713936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3750713936
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1639245055
Short name T399
Test name
Test status
Simulation time 114267197 ps
CPU time 0.82 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 215664 kb
Host smart-3c353483-05b7-4674-b66d-446a73ef6ea1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639245055 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1639245055
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1049185004
Short name T749
Test name
Test status
Simulation time 42237918 ps
CPU time 1.22 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:19 PM PDT 24
Peak memory 216572 kb
Host smart-7eb0d8b5-40cb-4bec-85c8-ac5527a58faf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049185004 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1049185004
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2970065874
Short name T4
Test name
Test status
Simulation time 32123135 ps
CPU time 1.3 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 219476 kb
Host smart-1518a511-6600-4f27-8b8a-016c830e1b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970065874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2970065874
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.545133068
Short name T265
Test name
Test status
Simulation time 35441344 ps
CPU time 1.65 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 216996 kb
Host smart-fd890c71-051e-471c-a273-41a8b776e263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545133068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.545133068
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.283335189
Short name T533
Test name
Test status
Simulation time 22518563 ps
CPU time 0.96 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 215732 kb
Host smart-9f66b0a1-fe52-423c-9e83-9b43fe4a40cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283335189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.283335189
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3824939165
Short name T377
Test name
Test status
Simulation time 27502469 ps
CPU time 0.91 seconds
Started Mar 21 02:00:20 PM PDT 24
Finished Mar 21 02:00:21 PM PDT 24
Peak memory 215404 kb
Host smart-bdea2103-1d7b-485c-868c-56749f8f5024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824939165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3824939165
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1973615732
Short name T614
Test name
Test status
Simulation time 571651427 ps
CPU time 3.85 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 215512 kb
Host smart-aa0f101c-e980-4678-a398-c891c5b431c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973615732 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1973615732
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4021056387
Short name T765
Test name
Test status
Simulation time 160023566031 ps
CPU time 1917.27 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:32:14 PM PDT 24
Peak memory 226028 kb
Host smart-829a7a96-7bf2-417f-97a8-e8cfa168ecba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021056387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4021056387
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1625515909
Short name T410
Test name
Test status
Simulation time 57759022 ps
CPU time 1.14 seconds
Started Mar 21 02:02:13 PM PDT 24
Finished Mar 21 02:02:14 PM PDT 24
Peak memory 219296 kb
Host smart-632ec5eb-023a-4666-b549-95bfb2389743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625515909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1625515909
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.69608115
Short name T447
Test name
Test status
Simulation time 82415954 ps
CPU time 0.93 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 216860 kb
Host smart-9c2319c7-68bd-4423-8fb8-f8b79fc935da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69608115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.69608115
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3812373512
Short name T489
Test name
Test status
Simulation time 45295128 ps
CPU time 1.44 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 217908 kb
Host smart-bf7daac9-9994-429a-87c7-6a42f95d7acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812373512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3812373512
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3246124476
Short name T297
Test name
Test status
Simulation time 310774772 ps
CPU time 4.16 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 216940 kb
Host smart-338e4d49-d15f-4a12-8195-d99dceffb7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246124476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3246124476
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2300205473
Short name T652
Test name
Test status
Simulation time 62478500 ps
CPU time 1.31 seconds
Started Mar 21 02:02:13 PM PDT 24
Finished Mar 21 02:02:14 PM PDT 24
Peak memory 216884 kb
Host smart-dc79da27-b906-48ee-a9df-10f6c607b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300205473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2300205473
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2763779257
Short name T516
Test name
Test status
Simulation time 27876445 ps
CPU time 1.26 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 216692 kb
Host smart-0e8aaec0-6509-42c3-aefd-601019e31b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763779257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2763779257
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2762648608
Short name T485
Test name
Test status
Simulation time 87490096 ps
CPU time 1.34 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 216888 kb
Host smart-0c03fcf8-77b4-4537-8b97-797f5ce0734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762648608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2762648608
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1093508948
Short name T679
Test name
Test status
Simulation time 33458861 ps
CPU time 1.25 seconds
Started Mar 21 02:02:12 PM PDT 24
Finished Mar 21 02:02:14 PM PDT 24
Peak memory 216772 kb
Host smart-93150ef2-92fb-4dd5-8a53-2a6b66e568d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093508948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1093508948
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2091751512
Short name T117
Test name
Test status
Simulation time 22640418 ps
CPU time 1.13 seconds
Started Mar 21 02:00:20 PM PDT 24
Finished Mar 21 02:00:21 PM PDT 24
Peak memory 215784 kb
Host smart-0ed9e030-d531-4e29-bc21-9002239abdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091751512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2091751512
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2168943516
Short name T39
Test name
Test status
Simulation time 13261495 ps
CPU time 0.96 seconds
Started Mar 21 02:00:22 PM PDT 24
Finished Mar 21 02:00:23 PM PDT 24
Peak memory 207024 kb
Host smart-b5ad24db-5489-417b-87fc-63088542f73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168943516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2168943516
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.142934725
Short name T88
Test name
Test status
Simulation time 20106921 ps
CPU time 0.86 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 215484 kb
Host smart-fbec3b08-1019-43d4-a68c-4e812ae9b2cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142934725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.142934725
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3006421649
Short name T828
Test name
Test status
Simulation time 66644923 ps
CPU time 1.2 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 216652 kb
Host smart-1a87bbfb-ef30-44fd-b497-94932be30725
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006421649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3006421649
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3735498906
Short name T692
Test name
Test status
Simulation time 94149489 ps
CPU time 1.01 seconds
Started Mar 21 02:00:19 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 220428 kb
Host smart-528a855a-318a-4307-900c-594836f0c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735498906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3735498906
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.526110508
Short name T793
Test name
Test status
Simulation time 46906779 ps
CPU time 1.27 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:20 PM PDT 24
Peak memory 218276 kb
Host smart-583b1334-b549-4912-8553-1f82ec43ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526110508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.526110508
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.4019902383
Short name T143
Test name
Test status
Simulation time 27562088 ps
CPU time 0.92 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 215356 kb
Host smart-67daad9b-817d-4bb2-b13e-9c5f397ff6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019902383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4019902383
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.915299510
Short name T295
Test name
Test status
Simulation time 367643583 ps
CPU time 1.83 seconds
Started Mar 21 02:00:15 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 216932 kb
Host smart-b937ed99-10ff-4c5a-9631-c0fb4264c6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915299510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.915299510
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1052919690
Short name T834
Test name
Test status
Simulation time 15033905615 ps
CPU time 184.65 seconds
Started Mar 21 02:00:21 PM PDT 24
Finished Mar 21 02:03:25 PM PDT 24
Peak memory 217804 kb
Host smart-70d64cdd-5f7e-4e7f-bfa2-26e66d7e6d30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052919690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1052919690
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3525391481
Short name T521
Test name
Test status
Simulation time 44497418 ps
CPU time 1.47 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 218040 kb
Host smart-68108d57-a670-4f88-a5fd-88f8b4c4a8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525391481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3525391481
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.4156708548
Short name T653
Test name
Test status
Simulation time 56716979 ps
CPU time 1.07 seconds
Started Mar 21 02:02:04 PM PDT 24
Finished Mar 21 02:02:05 PM PDT 24
Peak memory 216700 kb
Host smart-cb825932-1790-4a5f-b87d-92a4c8a25867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156708548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4156708548
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1594855186
Short name T745
Test name
Test status
Simulation time 90160722 ps
CPU time 1.18 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 216748 kb
Host smart-528034fe-80eb-4c2b-bb23-07d138ce5dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594855186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1594855186
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3382833651
Short name T787
Test name
Test status
Simulation time 241130649 ps
CPU time 3.56 seconds
Started Mar 21 02:02:11 PM PDT 24
Finished Mar 21 02:02:15 PM PDT 24
Peak memory 216936 kb
Host smart-705a4503-2ff3-44e8-bd71-eabb35ee7d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382833651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3382833651
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1859016145
Short name T785
Test name
Test status
Simulation time 46686102 ps
CPU time 1.73 seconds
Started Mar 21 02:02:11 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 217888 kb
Host smart-deedf25c-02b3-4e1a-825c-b4e43b496c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859016145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1859016145
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2322647447
Short name T409
Test name
Test status
Simulation time 40775290 ps
CPU time 1.63 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 217932 kb
Host smart-eaf5b0e1-ed56-4e7c-ba0e-ecf537934a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322647447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2322647447
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.828899334
Short name T51
Test name
Test status
Simulation time 18770106 ps
CPU time 1.05 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 216576 kb
Host smart-23de9fd0-301c-4216-9dce-1edf0bf0e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828899334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.828899334
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2590084373
Short name T281
Test name
Test status
Simulation time 276930256 ps
CPU time 3.96 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 217344 kb
Host smart-c310b723-8add-4f19-b17a-3da79604fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590084373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2590084373
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2484355925
Short name T623
Test name
Test status
Simulation time 89276834 ps
CPU time 2.24 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 219696 kb
Host smart-93584c42-bfc1-495d-8f52-ba1d4234f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484355925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2484355925
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3270990234
Short name T559
Test name
Test status
Simulation time 30966518 ps
CPU time 1.32 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 215804 kb
Host smart-57f2f4a2-6d17-417d-bda6-4e8966a9a115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270990234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3270990234
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2885266281
Short name T307
Test name
Test status
Simulation time 214093634 ps
CPU time 1.05 seconds
Started Mar 21 01:59:29 PM PDT 24
Finished Mar 21 01:59:30 PM PDT 24
Peak memory 206348 kb
Host smart-0dc4e3f9-3e77-4708-9160-501ae238259f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885266281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2885266281
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1240502707
Short name T179
Test name
Test status
Simulation time 51919585 ps
CPU time 0.84 seconds
Started Mar 21 01:59:21 PM PDT 24
Finished Mar 21 01:59:22 PM PDT 24
Peak memory 216016 kb
Host smart-54fcabb9-6a60-4f5f-ace0-4519f9148793
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240502707 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1240502707
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.589939399
Short name T81
Test name
Test status
Simulation time 43086184 ps
CPU time 1.34 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 216740 kb
Host smart-452478ba-3155-4c31-a450-297411593341
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589939399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.589939399
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.360432592
Short name T76
Test name
Test status
Simulation time 30046036 ps
CPU time 1.38 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 233704 kb
Host smart-d1ea6cde-7a36-4032-8fae-42587c23a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360432592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.360432592
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2539345242
Short name T411
Test name
Test status
Simulation time 103024568 ps
CPU time 1.24 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 219264 kb
Host smart-5aca2fb9-28a1-4f43-8f51-d9040149b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539345242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2539345242
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1690775789
Short name T43
Test name
Test status
Simulation time 36122127 ps
CPU time 0.98 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 223904 kb
Host smart-002a1054-7db9-48b8-a280-1fc75b4588f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690775789 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1690775789
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.607773411
Short name T46
Test name
Test status
Simulation time 703687409 ps
CPU time 3.44 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:26 PM PDT 24
Peak memory 234852 kb
Host smart-c55f22f5-98a1-4f5b-8c85-3abeb8b675d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607773411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.607773411
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3616950269
Short name T305
Test name
Test status
Simulation time 29107205 ps
CPU time 0.89 seconds
Started Mar 21 01:59:30 PM PDT 24
Finished Mar 21 01:59:31 PM PDT 24
Peak memory 215436 kb
Host smart-1d2c8580-8dc6-410a-9e50-5447a6dfd68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616950269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3616950269
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2681255155
Short name T519
Test name
Test status
Simulation time 173022277 ps
CPU time 3.13 seconds
Started Mar 21 01:59:30 PM PDT 24
Finished Mar 21 01:59:34 PM PDT 24
Peak memory 215424 kb
Host smart-5f420a28-a289-4f29-ae67-3a128008c9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681255155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2681255155
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1301619458
Short name T656
Test name
Test status
Simulation time 108969057244 ps
CPU time 730.2 seconds
Started Mar 21 01:59:21 PM PDT 24
Finished Mar 21 02:11:32 PM PDT 24
Peak memory 220372 kb
Host smart-2d51145a-1332-4b03-b4c5-67734e43a653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301619458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1301619458
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.619051573
Short name T716
Test name
Test status
Simulation time 81645424 ps
CPU time 1.18 seconds
Started Mar 21 02:00:29 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 215824 kb
Host smart-50587c8a-ff8b-403e-ba5b-073c60863a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619051573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.619051573
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.278328421
Short name T346
Test name
Test status
Simulation time 58841364 ps
CPU time 0.9 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 206096 kb
Host smart-60c64df0-289d-4946-99d6-6af82590b5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278328421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.278328421
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1213121357
Short name T171
Test name
Test status
Simulation time 155097465 ps
CPU time 0.86 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 216016 kb
Host smart-036bfeca-b1d9-4dcb-b774-b71ac2729bed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213121357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1213121357
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.3053834533
Short name T507
Test name
Test status
Simulation time 36025161 ps
CPU time 1.09 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 232600 kb
Host smart-02aa4b3a-790d-4650-912d-91257935b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053834533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3053834533
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1730040101
Short name T10
Test name
Test status
Simulation time 32187956 ps
CPU time 1.06 seconds
Started Mar 21 02:00:20 PM PDT 24
Finished Mar 21 02:00:21 PM PDT 24
Peak memory 219340 kb
Host smart-7adccbec-cdbb-4bb5-ac06-f36ee6f058e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730040101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1730040101
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4001315889
Short name T604
Test name
Test status
Simulation time 22105852 ps
CPU time 0.92 seconds
Started Mar 21 02:00:16 PM PDT 24
Finished Mar 21 02:00:17 PM PDT 24
Peak memory 215868 kb
Host smart-79389dc1-2cf1-444e-a96b-09e42627a206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001315889 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4001315889
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2142607632
Short name T314
Test name
Test status
Simulation time 15577727 ps
CPU time 0.97 seconds
Started Mar 21 02:00:17 PM PDT 24
Finished Mar 21 02:00:18 PM PDT 24
Peak memory 215416 kb
Host smart-507fcbbb-9dc3-42e0-9f4c-6a283ccf0651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142607632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2142607632
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2448056427
Short name T504
Test name
Test status
Simulation time 797599271 ps
CPU time 3.41 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:00:22 PM PDT 24
Peak memory 219684 kb
Host smart-9000a192-1f45-4ba7-839d-dbc3e472a7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448056427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2448056427
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1023232737
Short name T811
Test name
Test status
Simulation time 41595509882 ps
CPU time 567.38 seconds
Started Mar 21 02:00:18 PM PDT 24
Finished Mar 21 02:09:45 PM PDT 24
Peak memory 219356 kb
Host smart-5ee91c41-8c12-471c-8f06-7d726989a92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023232737 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1023232737
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1902846680
Short name T340
Test name
Test status
Simulation time 109325285 ps
CPU time 1.13 seconds
Started Mar 21 02:02:03 PM PDT 24
Finished Mar 21 02:02:04 PM PDT 24
Peak memory 216688 kb
Host smart-b97a62a0-34b8-4b27-a855-ecb2a8c7bb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902846680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1902846680
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1301444843
Short name T493
Test name
Test status
Simulation time 53792538 ps
CPU time 1.93 seconds
Started Mar 21 02:02:10 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 216732 kb
Host smart-0cff86b5-ebb3-4895-addd-a5f7f50ff137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301444843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1301444843
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3252268115
Short name T445
Test name
Test status
Simulation time 75295721 ps
CPU time 1.05 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:08 PM PDT 24
Peak memory 217976 kb
Host smart-7f7b77eb-fde7-4466-a8bd-25c0feb25fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252268115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3252268115
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2278921230
Short name T832
Test name
Test status
Simulation time 36543104 ps
CPU time 1.33 seconds
Started Mar 21 02:02:09 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 216848 kb
Host smart-1e94579e-4a47-4ef4-9e96-bcc81fa0faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278921230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2278921230
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.57053117
Short name T272
Test name
Test status
Simulation time 66877656 ps
CPU time 1.18 seconds
Started Mar 21 02:02:14 PM PDT 24
Finished Mar 21 02:02:16 PM PDT 24
Peak memory 217952 kb
Host smart-bec4e3bb-b218-401b-8759-bc63b784b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57053117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.57053117
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2733860225
Short name T775
Test name
Test status
Simulation time 61257056 ps
CPU time 1.62 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 218032 kb
Host smart-32bedb06-1496-441a-b24b-e21d5c34e6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733860225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2733860225
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4152480780
Short name T593
Test name
Test status
Simulation time 84280560 ps
CPU time 1.17 seconds
Started Mar 21 02:02:07 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 216928 kb
Host smart-d6e4095e-7724-404f-a20d-35659ff1c310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152480780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4152480780
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1831376285
Short name T345
Test name
Test status
Simulation time 63874972 ps
CPU time 1.57 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:10 PM PDT 24
Peak memory 216360 kb
Host smart-025955f3-4dd6-4fd3-a75a-c2ed721edcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831376285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1831376285
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3138190707
Short name T13
Test name
Test status
Simulation time 36472155 ps
CPU time 1.35 seconds
Started Mar 21 02:02:05 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 218104 kb
Host smart-27915d1c-d4ee-4f63-8eaa-5b83d4860de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138190707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3138190707
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1082655934
Short name T545
Test name
Test status
Simulation time 74935477 ps
CPU time 1.23 seconds
Started Mar 21 02:02:14 PM PDT 24
Finished Mar 21 02:02:16 PM PDT 24
Peak memory 216660 kb
Host smart-b88c483e-0fc0-4104-99ff-415eb7515346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082655934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1082655934
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2735321674
Short name T778
Test name
Test status
Simulation time 25605664 ps
CPU time 1.25 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 215812 kb
Host smart-2eb37154-1509-4e55-9ee3-7550132bb518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735321674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2735321674
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3328694062
Short name T664
Test name
Test status
Simulation time 20153288 ps
CPU time 0.83 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 205948 kb
Host smart-788d07e9-3b27-456d-b997-d2d5c4418140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328694062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3328694062
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.109397214
Short name T92
Test name
Test status
Simulation time 38337264 ps
CPU time 0.85 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 216012 kb
Host smart-56c5f16b-ea88-4092-a322-663ed0f084bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109397214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.109397214
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2265283895
Short name T817
Test name
Test status
Simulation time 37211998 ps
CPU time 1.28 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 216556 kb
Host smart-2d33744b-aa6f-408d-adb5-e23fa1fbbad8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265283895 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2265283895
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3255407325
Short name T563
Test name
Test status
Simulation time 128219882 ps
CPU time 0.99 seconds
Started Mar 21 02:00:29 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 218204 kb
Host smart-852df0eb-42cc-412a-907d-87615a500c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255407325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3255407325
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.274497018
Short name T394
Test name
Test status
Simulation time 75271467 ps
CPU time 2.5 seconds
Started Mar 21 02:00:37 PM PDT 24
Finished Mar 21 02:00:39 PM PDT 24
Peak memory 218404 kb
Host smart-15a5c182-aed0-45fe-8f0e-d2508359c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274497018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.274497018
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4216850163
Short name T779
Test name
Test status
Simulation time 98970546 ps
CPU time 0.93 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 223904 kb
Host smart-f3d0bac4-be01-479c-b1e1-67c9707c671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216850163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4216850163
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2136496182
Short name T800
Test name
Test status
Simulation time 55882446 ps
CPU time 0.89 seconds
Started Mar 21 02:00:31 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 215432 kb
Host smart-6a6f2409-7eb3-4e0a-96a4-6cdb7408f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136496182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2136496182
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.383088579
Short name T532
Test name
Test status
Simulation time 115889356 ps
CPU time 2.64 seconds
Started Mar 21 02:00:37 PM PDT 24
Finished Mar 21 02:00:40 PM PDT 24
Peak memory 217920 kb
Host smart-7f5c73cd-4313-480c-bc2d-72fe8d0ca648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383088579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.383088579
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2478320967
Short name T139
Test name
Test status
Simulation time 57470611109 ps
CPU time 757.44 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:13:07 PM PDT 24
Peak memory 221104 kb
Host smart-a5cb1c3c-d891-4d9b-897e-c10daec5e339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478320967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2478320967
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.373132088
Short name T35
Test name
Test status
Simulation time 62287765 ps
CPU time 1.59 seconds
Started Mar 21 02:02:06 PM PDT 24
Finished Mar 21 02:02:07 PM PDT 24
Peak memory 218116 kb
Host smart-fe70d805-4cf5-4b87-a668-9d8230513823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373132088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.373132088
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1230531565
Short name T784
Test name
Test status
Simulation time 85161709 ps
CPU time 1.44 seconds
Started Mar 21 02:02:11 PM PDT 24
Finished Mar 21 02:02:13 PM PDT 24
Peak memory 218124 kb
Host smart-f497d5ee-846f-45df-b770-8893e84f9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230531565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1230531565
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3315934918
Short name T665
Test name
Test status
Simulation time 70797518 ps
CPU time 1.09 seconds
Started Mar 21 02:02:14 PM PDT 24
Finished Mar 21 02:02:15 PM PDT 24
Peak memory 216780 kb
Host smart-e5162ad0-88d4-434b-bc42-c071f51d6900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315934918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3315934918
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3140332675
Short name T672
Test name
Test status
Simulation time 49089857 ps
CPU time 1.14 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:09 PM PDT 24
Peak memory 216924 kb
Host smart-15ff6902-316c-46f9-b704-f0a26210f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140332675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3140332675
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1426793051
Short name T333
Test name
Test status
Simulation time 202045720 ps
CPU time 3.56 seconds
Started Mar 21 02:02:08 PM PDT 24
Finished Mar 21 02:02:12 PM PDT 24
Peak memory 218484 kb
Host smart-1eeff0c0-7c04-42f9-ba04-610835956d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426793051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1426793051
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.88591521
Short name T266
Test name
Test status
Simulation time 116140684 ps
CPU time 0.99 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 216764 kb
Host smart-2b102e5b-36f7-400a-92b1-c0238c27aec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88591521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.88591521
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2995626907
Short name T731
Test name
Test status
Simulation time 34236504 ps
CPU time 1.28 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 216872 kb
Host smart-933a0a04-47ab-49df-a570-c94ee7a8111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995626907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2995626907
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3941243824
Short name T568
Test name
Test status
Simulation time 85566488 ps
CPU time 1.06 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 216880 kb
Host smart-eb1b59c1-ddf1-45da-bca0-93cb8cded8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941243824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3941243824
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3292728859
Short name T480
Test name
Test status
Simulation time 321308860 ps
CPU time 4.02 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 216980 kb
Host smart-b671b03f-a41f-4fba-a829-ff1b1505bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292728859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3292728859
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2729830845
Short name T689
Test name
Test status
Simulation time 82659548 ps
CPU time 1.32 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 216900 kb
Host smart-ae20fd1a-eb30-45da-bc5c-1413b3fc9eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729830845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2729830845
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2626099291
Short name T776
Test name
Test status
Simulation time 100440492 ps
CPU time 1.33 seconds
Started Mar 21 02:00:31 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 215768 kb
Host smart-dcab9bad-e76d-42fa-a270-c162ca163aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626099291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2626099291
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3717481641
Short name T362
Test name
Test status
Simulation time 32747176 ps
CPU time 0.89 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 206636 kb
Host smart-23ea6943-35be-41f2-8930-29ba98f5f365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717481641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3717481641
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.3336191782
Short name T379
Test name
Test status
Simulation time 25319431 ps
CPU time 1.09 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 231276 kb
Host smart-068138f4-357b-4865-911e-62c43c9126da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336191782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3336191782
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2081713645
Short name T494
Test name
Test status
Simulation time 42612319 ps
CPU time 1.28 seconds
Started Mar 21 02:00:34 PM PDT 24
Finished Mar 21 02:00:35 PM PDT 24
Peak memory 216760 kb
Host smart-0f899cf7-f6df-4793-b4e5-cf626b5fa143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081713645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2081713645
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.32107027
Short name T52
Test name
Test status
Simulation time 22090770 ps
CPU time 1.12 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 215640 kb
Host smart-f82f5673-2b5c-4cf1-8e34-fb2880706d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32107027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.32107027
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2880840537
Short name T492
Test name
Test status
Simulation time 46578493 ps
CPU time 0.93 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 215384 kb
Host smart-b99a1ec8-f5dd-4bdd-b86b-bd75e346996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880840537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2880840537
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2081333973
Short name T790
Test name
Test status
Simulation time 208022378 ps
CPU time 4.22 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:39 PM PDT 24
Peak memory 215484 kb
Host smart-1ca6a8e7-e06e-4c3f-bf90-953d2adc3e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081333973 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2081333973
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1062058529
Short name T816
Test name
Test status
Simulation time 107145010995 ps
CPU time 642.34 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:11:12 PM PDT 24
Peak memory 220000 kb
Host smart-1feead32-9e8b-4a58-ad10-bf3972d5cb33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062058529 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1062058529
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.39629865
Short name T352
Test name
Test status
Simulation time 40544623 ps
CPU time 1.5 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 217848 kb
Host smart-f66885b8-3527-4d48-a71c-ae106ba24863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39629865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.39629865
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3412097565
Short name T579
Test name
Test status
Simulation time 175982949 ps
CPU time 1.49 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 218492 kb
Host smart-e5aa04f1-4ea6-4c1c-a634-388ec78f546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412097565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3412097565
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.991616727
Short name T565
Test name
Test status
Simulation time 42579274 ps
CPU time 1.07 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 219036 kb
Host smart-22819989-8790-4d49-8658-bb373b86f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991616727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.991616727
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.20468730
Short name T730
Test name
Test status
Simulation time 24679767 ps
CPU time 1.26 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 216748 kb
Host smart-63a9190d-2fa7-4529-9c3c-5a64bf365d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20468730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.20468730
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.766262312
Short name T670
Test name
Test status
Simulation time 63096531 ps
CPU time 1.23 seconds
Started Mar 21 02:02:24 PM PDT 24
Finished Mar 21 02:02:25 PM PDT 24
Peak memory 218260 kb
Host smart-790e6cf6-f06b-4577-b7da-0e762e70fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766262312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.766262312
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3845941989
Short name T685
Test name
Test status
Simulation time 66393423 ps
CPU time 1.03 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 216756 kb
Host smart-d94976f4-c2c8-438e-ab8e-4b172fc6eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845941989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3845941989
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2647032282
Short name T512
Test name
Test status
Simulation time 242988401 ps
CPU time 3.56 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 219636 kb
Host smart-4df06e1e-b852-47a5-ae12-15d4b84e6371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647032282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2647032282
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2993619780
Short name T358
Test name
Test status
Simulation time 80723456 ps
CPU time 1.26 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 216816 kb
Host smart-9140b14c-dcbc-49a3-9d4d-bc9091ad5fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993619780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2993619780
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2247425983
Short name T607
Test name
Test status
Simulation time 51896843 ps
CPU time 1.34 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 217900 kb
Host smart-2ad86b9d-2be8-46b0-b0bc-643478d8c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247425983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2247425983
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3857797239
Short name T260
Test name
Test status
Simulation time 27781402 ps
CPU time 1.29 seconds
Started Mar 21 02:00:37 PM PDT 24
Finished Mar 21 02:00:39 PM PDT 24
Peak memory 215788 kb
Host smart-079d3c0e-42f4-46e8-a96c-2aaf4442e163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857797239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3857797239
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1462459438
Short name T729
Test name
Test status
Simulation time 66098875 ps
CPU time 0.94 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 206132 kb
Host smart-c7466462-f2dd-4c04-a7d2-685ad38b3f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462459438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1462459438
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.911237273
Short name T332
Test name
Test status
Simulation time 12213402 ps
CPU time 0.91 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 215904 kb
Host smart-a9fef0b3-8b8b-40cd-9cf5-d50e4c8196e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911237273 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.911237273
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1630280155
Short name T644
Test name
Test status
Simulation time 31442980 ps
CPU time 1.13 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 216652 kb
Host smart-adaa47ae-e479-479f-83c2-eddfec429578
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630280155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1630280155
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1678198973
Short name T154
Test name
Test status
Simulation time 28469240 ps
CPU time 1.17 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 219300 kb
Host smart-384a5b70-bcb0-4a9a-8f4d-860ff1f61ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678198973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1678198973
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4225358608
Short name T461
Test name
Test status
Simulation time 56516113 ps
CPU time 1.27 seconds
Started Mar 21 02:00:28 PM PDT 24
Finished Mar 21 02:00:29 PM PDT 24
Peak memory 219328 kb
Host smart-d191b49b-6cef-4d85-8edf-4277f38c5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225358608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4225358608
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3082298211
Short name T386
Test name
Test status
Simulation time 58686968 ps
CPU time 0.88 seconds
Started Mar 21 02:00:29 PM PDT 24
Finished Mar 21 02:00:30 PM PDT 24
Peak memory 215552 kb
Host smart-d912f0c7-8e58-43ca-95a7-4dd75912b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082298211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3082298211
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.726298371
Short name T806
Test name
Test status
Simulation time 28747829 ps
CPU time 0.98 seconds
Started Mar 21 02:00:33 PM PDT 24
Finished Mar 21 02:00:34 PM PDT 24
Peak memory 215436 kb
Host smart-7ae09d69-241a-4530-8f22-711af782cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726298371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.726298371
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.604560316
Short name T435
Test name
Test status
Simulation time 597490286 ps
CPU time 3.81 seconds
Started Mar 21 02:00:28 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 216668 kb
Host smart-d923a035-64d8-4676-98b7-4aec289b0b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604560316 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.604560316
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.933826315
Short name T194
Test name
Test status
Simulation time 58922449617 ps
CPU time 496.27 seconds
Started Mar 21 02:00:29 PM PDT 24
Finished Mar 21 02:08:46 PM PDT 24
Peak memory 218024 kb
Host smart-afae2739-12ae-488a-9f25-6d4697f4d736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933826315 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.933826315
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1582194633
Short name T32
Test name
Test status
Simulation time 34766444 ps
CPU time 1.46 seconds
Started Mar 21 02:02:24 PM PDT 24
Finished Mar 21 02:02:29 PM PDT 24
Peak memory 218132 kb
Host smart-9b7a8748-fac8-4d72-bc66-b4b645934a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582194633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1582194633
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3751497343
Short name T682
Test name
Test status
Simulation time 30408298 ps
CPU time 1.21 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 216748 kb
Host smart-11328ce1-674b-4992-abfb-85c8fd354a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751497343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3751497343
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.30481479
Short name T249
Test name
Test status
Simulation time 86176401 ps
CPU time 1.43 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 218140 kb
Host smart-3769214d-16d9-4441-bd4d-7d43d09e2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30481479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.30481479
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.605527048
Short name T144
Test name
Test status
Simulation time 36295666 ps
CPU time 1.49 seconds
Started Mar 21 02:02:29 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218132 kb
Host smart-29b4b86a-792e-48ad-be4a-bb4b9dd79960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605527048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.605527048
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1428920904
Short name T706
Test name
Test status
Simulation time 46012457 ps
CPU time 1.52 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 218032 kb
Host smart-ff71283a-aa0b-4d4a-8c39-1af171530028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428920904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1428920904
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.118811473
Short name T300
Test name
Test status
Simulation time 62529605 ps
CPU time 1.58 seconds
Started Mar 21 02:02:23 PM PDT 24
Finished Mar 21 02:02:25 PM PDT 24
Peak memory 218180 kb
Host smart-64da8be5-d1ce-4632-a88f-b6b5dbfb162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118811473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.118811473
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1702651915
Short name T368
Test name
Test status
Simulation time 37727996 ps
CPU time 1.4 seconds
Started Mar 21 02:02:24 PM PDT 24
Finished Mar 21 02:02:28 PM PDT 24
Peak memory 218652 kb
Host smart-8e1a97a8-b84f-45ca-a61c-c8f8cc82f587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702651915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1702651915
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.363724108
Short name T271
Test name
Test status
Simulation time 95946728 ps
CPU time 1.67 seconds
Started Mar 21 02:02:32 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218112 kb
Host smart-b1a6fc63-50ab-4aac-811e-b756fc9267da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363724108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.363724108
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2760756188
Short name T747
Test name
Test status
Simulation time 62135997 ps
CPU time 2.23 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:32 PM PDT 24
Peak memory 217932 kb
Host smart-a8688caa-43a8-4f58-b09e-b95f8364c387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760756188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2760756188
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1041881587
Short name T324
Test name
Test status
Simulation time 90751439 ps
CPU time 1.59 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 219512 kb
Host smart-e87b065f-a175-4af5-b057-d2fba9c9bc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041881587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1041881587
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.410605869
Short name T575
Test name
Test status
Simulation time 85155703 ps
CPU time 0.86 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 207060 kb
Host smart-f784c279-c0b7-4468-8a4f-d266d2dd2bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410605869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.410605869
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4205755974
Short name T762
Test name
Test status
Simulation time 113570288 ps
CPU time 1.11 seconds
Started Mar 21 02:00:38 PM PDT 24
Finished Mar 21 02:00:39 PM PDT 24
Peak memory 217872 kb
Host smart-578a733a-fa8c-408f-a814-94979ba74253
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205755974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4205755974
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.176661913
Short name T370
Test name
Test status
Simulation time 25414851 ps
CPU time 0.97 seconds
Started Mar 21 02:00:31 PM PDT 24
Finished Mar 21 02:00:32 PM PDT 24
Peak memory 231204 kb
Host smart-1790d255-cdfa-48b7-9fd8-aa445d034803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176661913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.176661913
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2487184044
Short name T423
Test name
Test status
Simulation time 39352382 ps
CPU time 1.44 seconds
Started Mar 21 02:00:29 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 218124 kb
Host smart-0863bd8e-ca71-40ad-b2bb-f00c79c80bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487184044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2487184044
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2987759038
Short name T840
Test name
Test status
Simulation time 22715885 ps
CPU time 0.96 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 215860 kb
Host smart-6cb06385-50b0-405f-b95d-2239a1641cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987759038 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2987759038
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2846758657
Short name T691
Test name
Test status
Simulation time 18697695 ps
CPU time 1.03 seconds
Started Mar 21 02:00:27 PM PDT 24
Finished Mar 21 02:00:28 PM PDT 24
Peak memory 215396 kb
Host smart-096d18df-075d-459a-aba1-9b2711e8ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846758657 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2846758657
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2922463034
Short name T202
Test name
Test status
Simulation time 303831800 ps
CPU time 5.6 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:00:41 PM PDT 24
Peak memory 217992 kb
Host smart-4b90710e-a970-4686-9940-90041fa53066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922463034 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2922463034
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1925617945
Short name T783
Test name
Test status
Simulation time 46518251480 ps
CPU time 615.83 seconds
Started Mar 21 02:00:35 PM PDT 24
Finished Mar 21 02:10:51 PM PDT 24
Peak memory 218364 kb
Host smart-9b4f3741-97d0-4c61-b9dc-62454ce25fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925617945 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1925617945
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2321599491
Short name T684
Test name
Test status
Simulation time 118227852 ps
CPU time 1.31 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 218228 kb
Host smart-ba48ab97-5ec4-4ac7-805e-ab49da3e38fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321599491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2321599491
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3888436027
Short name T276
Test name
Test status
Simulation time 113151417 ps
CPU time 1.82 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:32 PM PDT 24
Peak memory 216904 kb
Host smart-4af2d2e1-0a37-4c70-8d28-f52aef92083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888436027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3888436027
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.524990772
Short name T625
Test name
Test status
Simulation time 233286467 ps
CPU time 1.4 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 219432 kb
Host smart-ea985687-9e29-4c60-985d-dc33115d931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524990772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.524990772
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2826551555
Short name T511
Test name
Test status
Simulation time 45487587 ps
CPU time 1.57 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:29 PM PDT 24
Peak memory 216900 kb
Host smart-71d53688-399b-4f1b-ab9d-5ccb29fcf891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826551555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2826551555
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1602003000
Short name T301
Test name
Test status
Simulation time 163119229 ps
CPU time 1.16 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:32 PM PDT 24
Peak memory 216652 kb
Host smart-a7d405b2-79b8-4f54-81cf-5a3c677e061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602003000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1602003000
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.232712281
Short name T481
Test name
Test status
Simulation time 69783225 ps
CPU time 1.33 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 218580 kb
Host smart-d205f1e6-4b8f-4674-a734-c2a4f14e7a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232712281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.232712281
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.173669981
Short name T501
Test name
Test status
Simulation time 53479519 ps
CPU time 1.85 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 215396 kb
Host smart-16247f7a-f76e-4fbc-8bf7-cb8ae2655afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173669981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.173669981
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2285408520
Short name T293
Test name
Test status
Simulation time 113018853 ps
CPU time 2.66 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 218032 kb
Host smart-2378bbce-a888-479a-8961-e03275199de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285408520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2285408520
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3735682091
Short name T474
Test name
Test status
Simulation time 90249118 ps
CPU time 1.17 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 216832 kb
Host smart-147b07ea-49c5-409d-8317-1f731be7cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735682091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3735682091
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3650723959
Short name T428
Test name
Test status
Simulation time 65308828 ps
CPU time 1.06 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 216852 kb
Host smart-37c9d785-b200-440e-b1bf-972ee5326628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650723959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3650723959
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.431448690
Short name T805
Test name
Test status
Simulation time 27041183 ps
CPU time 1.15 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 215804 kb
Host smart-e4ae25b5-9039-43e2-b8b5-5c6b7b66f130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431448690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.431448690
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2629010461
Short name T771
Test name
Test status
Simulation time 23372105 ps
CPU time 0.94 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:43 PM PDT 24
Peak memory 206112 kb
Host smart-aa0127f2-689c-4be8-94da-01a187df068b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629010461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2629010461
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1061576448
Short name T110
Test name
Test status
Simulation time 32770725 ps
CPU time 0.82 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 216016 kb
Host smart-c70b23b5-6b52-4f0e-8cfa-22417ab997b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061576448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1061576448
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.514264560
Short name T318
Test name
Test status
Simulation time 63563285 ps
CPU time 1.17 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:00:43 PM PDT 24
Peak memory 217768 kb
Host smart-111b0aed-82d5-4520-9788-8261fb7ceaa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514264560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.514264560
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1483317991
Short name T464
Test name
Test status
Simulation time 73116474 ps
CPU time 0.79 seconds
Started Mar 21 02:00:30 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 218044 kb
Host smart-e34abf35-9cda-4b22-83b6-f2a2bf0e8d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483317991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1483317991
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.4030127407
Short name T583
Test name
Test status
Simulation time 132598632 ps
CPU time 3.06 seconds
Started Mar 21 02:00:38 PM PDT 24
Finished Mar 21 02:00:41 PM PDT 24
Peak memory 218228 kb
Host smart-ba2f139b-27ac-45fd-b141-707b3f937d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030127407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.4030127407
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1402956613
Short name T470
Test name
Test status
Simulation time 45108960 ps
CPU time 0.84 seconds
Started Mar 21 02:00:29 PM PDT 24
Finished Mar 21 02:00:30 PM PDT 24
Peak memory 215532 kb
Host smart-efe2e525-5859-47f6-8d5d-c33fea24a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402956613 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1402956613
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.770983160
Short name T371
Test name
Test status
Simulation time 17440922 ps
CPU time 1.02 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:33 PM PDT 24
Peak memory 215356 kb
Host smart-5c4c4c5e-8243-44e8-b46f-813b49a5152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770983160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.770983160
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2730172476
Short name T455
Test name
Test status
Simulation time 838046222 ps
CPU time 4.01 seconds
Started Mar 21 02:00:32 PM PDT 24
Finished Mar 21 02:00:36 PM PDT 24
Peak memory 215440 kb
Host smart-b97b064b-42cc-4f24-bee2-af94a97af1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730172476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2730172476
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1511997296
Short name T803
Test name
Test status
Simulation time 80130690775 ps
CPU time 521.28 seconds
Started Mar 21 02:00:36 PM PDT 24
Finished Mar 21 02:09:18 PM PDT 24
Peak memory 223840 kb
Host smart-884c5252-c6ff-4e96-a425-6c77c9946503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511997296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1511997296
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1095390903
Short name T431
Test name
Test status
Simulation time 30300333 ps
CPU time 1.39 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:29 PM PDT 24
Peak memory 216964 kb
Host smart-a120d31b-59df-4f10-b9a7-bfdee2a2f124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095390903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1095390903
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4132507251
Short name T30
Test name
Test status
Simulation time 65947346 ps
CPU time 1.15 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:40 PM PDT 24
Peak memory 216796 kb
Host smart-5051e66d-d34d-4245-82f3-e51e4591f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132507251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4132507251
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3843155347
Short name T483
Test name
Test status
Simulation time 53268631 ps
CPU time 1.39 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:32 PM PDT 24
Peak memory 217964 kb
Host smart-beca52c5-d666-4abd-8a05-c170f3605ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843155347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3843155347
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3694626728
Short name T740
Test name
Test status
Simulation time 46523559 ps
CPU time 1.59 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:29 PM PDT 24
Peak memory 216836 kb
Host smart-97ca9862-bc24-4121-a297-b75f9b44fa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694626728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3694626728
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1185716963
Short name T690
Test name
Test status
Simulation time 65884614 ps
CPU time 2.03 seconds
Started Mar 21 02:02:30 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 216932 kb
Host smart-6d50188e-fb0a-4e66-ac68-046253cc893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185716963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1185716963
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4091703448
Short name T628
Test name
Test status
Simulation time 251484362 ps
CPU time 1.68 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 218420 kb
Host smart-e0402811-d082-4067-b64a-1ae85384be18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091703448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4091703448
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.626821423
Short name T264
Test name
Test status
Simulation time 63027766 ps
CPU time 1.66 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 218076 kb
Host smart-35b6edba-f74a-490b-9eac-5bad08dfe70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626821423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.626821423
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2887855336
Short name T347
Test name
Test status
Simulation time 70115417 ps
CPU time 1.41 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 217952 kb
Host smart-dc8717da-eefb-4f1e-a878-446f5ec57686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887855336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2887855336
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1654954009
Short name T425
Test name
Test status
Simulation time 25536944 ps
CPU time 1.35 seconds
Started Mar 21 02:02:25 PM PDT 24
Finished Mar 21 02:02:29 PM PDT 24
Peak memory 219312 kb
Host smart-0b7131a0-2383-4a5f-9104-5e8e4544a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654954009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1654954009
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4167098012
Short name T476
Test name
Test status
Simulation time 61016926 ps
CPU time 1.38 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 218236 kb
Host smart-7256d38f-d3f2-4af9-9a3b-d057f61b9fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167098012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4167098012
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2017424875
Short name T258
Test name
Test status
Simulation time 66571817 ps
CPU time 1.04 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215812 kb
Host smart-eb656706-9e33-44a9-910a-466f479fb031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017424875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2017424875
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2312612661
Short name T387
Test name
Test status
Simulation time 29406803 ps
CPU time 0.9 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 206652 kb
Host smart-3062ea75-1c86-448e-adec-e225d6c4a1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312612661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2312612661
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.367020289
Short name T320
Test name
Test status
Simulation time 16462784 ps
CPU time 0.8 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215644 kb
Host smart-4583978d-a396-41d4-b95e-b06e8f30e4f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367020289 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.367020289
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.4157835832
Short name T169
Test name
Test status
Simulation time 30349979 ps
CPU time 0.9 seconds
Started Mar 21 02:00:45 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 218204 kb
Host smart-f9177d34-8836-42e8-a439-5da2fdca4e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157835832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4157835832
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4219455812
Short name T602
Test name
Test status
Simulation time 35603228 ps
CPU time 1.54 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:45 PM PDT 24
Peak memory 218080 kb
Host smart-040edf98-d800-4654-8a6b-2a180e26a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219455812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4219455812
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3543799260
Short name T509
Test name
Test status
Simulation time 29962276 ps
CPU time 1.27 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:45 PM PDT 24
Peak memory 224720 kb
Host smart-6a3816d7-a0dd-4daf-8d8b-f2c78db83a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543799260 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3543799260
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3739694455
Short name T810
Test name
Test status
Simulation time 29393500 ps
CPU time 0.95 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 215448 kb
Host smart-b0b1992b-d8c5-47a6-a073-d53e92802df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739694455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3739694455
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3681768457
Short name T200
Test name
Test status
Simulation time 176414037 ps
CPU time 2.24 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 219188 kb
Host smart-6df468b2-177c-44cd-a9a3-d035affaf029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681768457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3681768457
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2265730772
Short name T804
Test name
Test status
Simulation time 406907341987 ps
CPU time 774.5 seconds
Started Mar 21 02:00:46 PM PDT 24
Finished Mar 21 02:13:41 PM PDT 24
Peak memory 223984 kb
Host smart-971f598b-647d-49f4-a47c-5f7d1c6bfaa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265730772 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2265730772
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.153810446
Short name T743
Test name
Test status
Simulation time 160760036 ps
CPU time 1.19 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:32 PM PDT 24
Peak memory 216772 kb
Host smart-6bd01991-e1bf-4662-ad5a-6207e30c794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153810446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.153810446
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3765654081
Short name T837
Test name
Test status
Simulation time 58058220 ps
CPU time 1.62 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 218064 kb
Host smart-68cd009c-9994-44dd-bd2c-85e1053bff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765654081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3765654081
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.627953312
Short name T661
Test name
Test status
Simulation time 27199408 ps
CPU time 1.16 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 216880 kb
Host smart-d46e7c2e-2638-46ab-a2d0-bede14a79b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627953312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.627953312
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4156211985
Short name T818
Test name
Test status
Simulation time 121051092 ps
CPU time 1.12 seconds
Started Mar 21 02:02:31 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 216848 kb
Host smart-77086511-c5c5-420c-9bcc-791db8543d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156211985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4156211985
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.356207422
Short name T794
Test name
Test status
Simulation time 38893120 ps
CPU time 1.35 seconds
Started Mar 21 02:02:30 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 217892 kb
Host smart-f203c9d0-903d-4750-a9ef-13415ea3fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356207422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.356207422
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2649579320
Short name T429
Test name
Test status
Simulation time 40218057 ps
CPU time 1.57 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 217692 kb
Host smart-7f3a24ce-0dc8-4214-8fb8-99fdadf3178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649579320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2649579320
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2720648644
Short name T591
Test name
Test status
Simulation time 251939555 ps
CPU time 1.42 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 218080 kb
Host smart-6d907d77-b69c-4bf3-89e2-e9720aedbb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720648644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2720648644
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3689178149
Short name T557
Test name
Test status
Simulation time 41489421 ps
CPU time 1.37 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 219268 kb
Host smart-34a5bd29-0322-478a-853a-7dc230ffe722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689178149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3689178149
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1191550164
Short name T38
Test name
Test status
Simulation time 48383123 ps
CPU time 1.43 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:32 PM PDT 24
Peak memory 217976 kb
Host smart-ee0657ca-9ade-47dc-bb7f-f2ea404f5a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191550164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1191550164
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3758961671
Short name T355
Test name
Test status
Simulation time 53496099 ps
CPU time 1.37 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 215496 kb
Host smart-91ce81c2-d867-486f-9af4-fc42b361cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758961671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3758961671
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1218603408
Short name T781
Test name
Test status
Simulation time 49607130 ps
CPU time 1.19 seconds
Started Mar 21 02:00:45 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 215812 kb
Host smart-c6d88271-070c-42d6-886f-789a6c766476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218603408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1218603408
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3642701220
Short name T503
Test name
Test status
Simulation time 80588110 ps
CPU time 0.85 seconds
Started Mar 21 02:00:40 PM PDT 24
Finished Mar 21 02:00:41 PM PDT 24
Peak memory 205968 kb
Host smart-ba2281e4-48b8-4a96-a51a-8b152fc0475b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642701220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3642701220
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1115680872
Short name T114
Test name
Test status
Simulation time 11309458 ps
CPU time 0.91 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 216020 kb
Host smart-d508730a-4b4c-4418-b4c6-6fc91374aecc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115680872 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1115680872
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2169971618
Short name T530
Test name
Test status
Simulation time 47689020 ps
CPU time 0.98 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:43 PM PDT 24
Peak memory 217952 kb
Host smart-cd3445d1-c1fa-46c5-b870-3803761ff1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169971618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2169971618
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3277665184
Short name T390
Test name
Test status
Simulation time 55028616 ps
CPU time 1.18 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 216564 kb
Host smart-5d384530-af76-41de-930e-53a310940ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277665184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3277665184
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4031463805
Short name T553
Test name
Test status
Simulation time 24002911 ps
CPU time 0.97 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215480 kb
Host smart-caa07dc5-27be-4956-991e-860c68e4f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031463805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4031463805
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.955185119
Short name T48
Test name
Test status
Simulation time 17621316 ps
CPU time 0.96 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 207200 kb
Host smart-f623e79f-67d5-4b00-b357-e442c0cbd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955185119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.955185119
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4224173127
Short name T142
Test name
Test status
Simulation time 276317104 ps
CPU time 5.52 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 219820 kb
Host smart-32479185-f20f-4c3e-953c-642cc8333018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224173127 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4224173127
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.903270628
Short name T820
Test name
Test status
Simulation time 61394618485 ps
CPU time 739.27 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:13:00 PM PDT 24
Peak memory 223852 kb
Host smart-42612c15-4a71-4ff8-8b86-a5f34abe431d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903270628 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.903270628
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.24522930
Short name T181
Test name
Test status
Simulation time 68076094 ps
CPU time 1.18 seconds
Started Mar 21 02:02:32 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 216564 kb
Host smart-7d5c31f4-e39b-45d1-bfb0-34d7f29c2815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24522930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.24522930
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3228986208
Short name T380
Test name
Test status
Simulation time 90343862 ps
CPU time 1.42 seconds
Started Mar 21 02:02:29 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218136 kb
Host smart-a72befe6-17a7-448c-ba7a-6e94661df830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228986208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3228986208
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.299334712
Short name T351
Test name
Test status
Simulation time 28650232 ps
CPU time 1.27 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:30 PM PDT 24
Peak memory 218064 kb
Host smart-61b73eb4-a97a-4cf6-9780-053b9025b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299334712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.299334712
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2762417127
Short name T506
Test name
Test status
Simulation time 43649851 ps
CPU time 1.11 seconds
Started Mar 21 02:02:26 PM PDT 24
Finished Mar 21 02:02:31 PM PDT 24
Peak memory 216648 kb
Host smart-704d8e80-16a1-405c-9e60-287ceaa66bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762417127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2762417127
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2927685348
Short name T808
Test name
Test status
Simulation time 59403681 ps
CPU time 1.78 seconds
Started Mar 21 02:02:31 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 219052 kb
Host smart-a9cab5da-98d7-4f45-ae92-c179d87baf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927685348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2927685348
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.392431144
Short name T746
Test name
Test status
Simulation time 69008878 ps
CPU time 1.48 seconds
Started Mar 21 02:02:32 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218136 kb
Host smart-60d16ef3-1bf2-4471-a5b1-4a8667d9c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392431144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.392431144
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4025215747
Short name T286
Test name
Test status
Simulation time 441698213 ps
CPU time 4.07 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:36 PM PDT 24
Peak memory 219228 kb
Host smart-3656acbf-c70c-4cf6-a3ec-10e2f9a41dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025215747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4025215747
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.174809433
Short name T56
Test name
Test status
Simulation time 132259401 ps
CPU time 2.55 seconds
Started Mar 21 02:02:32 PM PDT 24
Finished Mar 21 02:02:36 PM PDT 24
Peak memory 219144 kb
Host smart-dabb2fbd-b030-4210-bad6-9e7c433d3feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174809433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.174809433
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3939530781
Short name T442
Test name
Test status
Simulation time 31456892 ps
CPU time 1.01 seconds
Started Mar 21 02:02:27 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 216652 kb
Host smart-1a7764e1-5a65-4448-851b-819c60c40459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939530781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3939530781
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.643962044
Short name T259
Test name
Test status
Simulation time 28131377 ps
CPU time 1.3 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215688 kb
Host smart-5f060ece-e2ea-4686-af64-b166f5b9ccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643962044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.643962044
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1753678545
Short name T841
Test name
Test status
Simulation time 36417977 ps
CPU time 0.96 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 206152 kb
Host smart-771985ba-e039-4845-ac94-9f8b442e6cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753678545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1753678545
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3308294762
Short name T153
Test name
Test status
Simulation time 36314883 ps
CPU time 0.83 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:00:43 PM PDT 24
Peak memory 216004 kb
Host smart-926c1185-ccd6-4c9a-9845-3fbc9fc675f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308294762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3308294762
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2925972757
Short name T412
Test name
Test status
Simulation time 28782111 ps
CPU time 1.21 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:45 PM PDT 24
Peak memory 219212 kb
Host smart-931643af-f208-43f5-a398-5dc8a784f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925972757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2925972757
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.278833844
Short name T47
Test name
Test status
Simulation time 40524933 ps
CPU time 1.33 seconds
Started Mar 21 02:00:46 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 217892 kb
Host smart-3216ca32-eb4a-4e41-aae1-70390fb5846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278833844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.278833844
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1331013084
Short name T636
Test name
Test status
Simulation time 40628369 ps
CPU time 0.87 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215648 kb
Host smart-f7618962-cedc-4065-a510-b98425e259a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331013084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1331013084
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.693350745
Short name T414
Test name
Test status
Simulation time 53265599 ps
CPU time 0.95 seconds
Started Mar 21 02:00:43 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215396 kb
Host smart-87b0c108-5cdc-4cca-bc41-cee9480d845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693350745 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.693350745
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1820549435
Short name T518
Test name
Test status
Simulation time 867367155 ps
CPU time 4.03 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 216584 kb
Host smart-14c17b38-8fc3-4d78-a87f-db15044fa9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820549435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1820549435
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2834254997
Short name T707
Test name
Test status
Simulation time 229671286515 ps
CPU time 1360.4 seconds
Started Mar 21 02:00:40 PM PDT 24
Finished Mar 21 02:23:21 PM PDT 24
Peak memory 223968 kb
Host smart-e48e2d58-daca-4d08-a006-8b59587510f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834254997 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2834254997
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3144059782
Short name T600
Test name
Test status
Simulation time 46023036 ps
CPU time 1.48 seconds
Started Mar 21 02:02:31 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 216752 kb
Host smart-e528ff8c-99c2-4671-abeb-95d6ee65517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144059782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3144059782
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3703564908
Short name T356
Test name
Test status
Simulation time 47001221 ps
CPU time 1.46 seconds
Started Mar 21 02:02:28 PM PDT 24
Finished Mar 21 02:02:34 PM PDT 24
Peak memory 217768 kb
Host smart-066b5579-2c25-406d-bfe3-cc3e4eabe3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703564908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3703564908
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3570229698
Short name T306
Test name
Test status
Simulation time 192445912 ps
CPU time 1.49 seconds
Started Mar 21 02:02:29 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218196 kb
Host smart-9542c2a4-dbb7-4a11-86c3-89edb3b92e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570229698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3570229698
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2976851531
Short name T606
Test name
Test status
Simulation time 96926174 ps
CPU time 1.42 seconds
Started Mar 21 02:02:29 PM PDT 24
Finished Mar 21 02:02:35 PM PDT 24
Peak memory 218308 kb
Host smart-1a82f5cd-0c8b-45d2-baf9-47b8667f71ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976851531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2976851531
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3986431317
Short name T770
Test name
Test status
Simulation time 104526602 ps
CPU time 1.19 seconds
Started Mar 21 02:02:38 PM PDT 24
Finished Mar 21 02:02:39 PM PDT 24
Peak memory 216724 kb
Host smart-dd4eb69d-c6cb-46b1-8311-fb8b188eff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986431317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3986431317
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3134830379
Short name T671
Test name
Test status
Simulation time 53936409 ps
CPU time 1.25 seconds
Started Mar 21 02:02:38 PM PDT 24
Finished Mar 21 02:02:40 PM PDT 24
Peak memory 218020 kb
Host smart-62a181f0-f9a7-486f-b449-44e80651c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134830379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3134830379
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3952761833
Short name T278
Test name
Test status
Simulation time 34165661 ps
CPU time 1.37 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:44 PM PDT 24
Peak memory 217912 kb
Host smart-4bdd1cc2-36fc-4283-a307-b8b3946aa2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952761833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3952761833
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.588077483
Short name T273
Test name
Test status
Simulation time 41486081 ps
CPU time 1.07 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 218896 kb
Host smart-ea39083c-226d-46b8-85b6-9a093cdc9824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588077483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.588077483
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3508247235
Short name T459
Test name
Test status
Simulation time 67343862 ps
CPU time 1.49 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 219236 kb
Host smart-5f0700eb-21f6-4f25-8648-a2c856ee9a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508247235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3508247235
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1513767223
Short name T98
Test name
Test status
Simulation time 24816403 ps
CPU time 1.14 seconds
Started Mar 21 02:00:45 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 215760 kb
Host smart-96887ac6-dc0b-4334-a235-5cb951d439b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513767223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1513767223
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1434424933
Short name T733
Test name
Test status
Simulation time 114570879 ps
CPU time 0.82 seconds
Started Mar 21 02:00:41 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 206484 kb
Host smart-7dfdb01c-83d3-4ef1-a7f9-685c863361cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434424933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1434424933
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3105439434
Short name T420
Test name
Test status
Simulation time 28310085 ps
CPU time 0.86 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:45 PM PDT 24
Peak memory 215728 kb
Host smart-97c387f9-ee4c-416c-aac3-b6e5796be21e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105439434 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3105439434
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3807896145
Short name T646
Test name
Test status
Simulation time 37574692 ps
CPU time 1.15 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 216576 kb
Host smart-d75c0d70-5dbb-4b61-91b7-b4b58c8577c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807896145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3807896145
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2021452683
Short name T159
Test name
Test status
Simulation time 19058186 ps
CPU time 1.02 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:45 PM PDT 24
Peak memory 215656 kb
Host smart-e1b100b8-9f9c-4ef1-98eb-ccb2ad742d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021452683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2021452683
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2772094328
Short name T802
Test name
Test status
Simulation time 65629463 ps
CPU time 1.34 seconds
Started Mar 21 02:00:45 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 218008 kb
Host smart-04e9203c-36dd-4e91-a975-f8cebedd4a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772094328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2772094328
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.241521614
Short name T316
Test name
Test status
Simulation time 25115552 ps
CPU time 1.08 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:45 PM PDT 24
Peak memory 224152 kb
Host smart-b565436e-4b8d-4ddd-a51e-35120fbb7f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241521614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.241521614
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3241117507
Short name T505
Test name
Test status
Simulation time 15942101 ps
CPU time 1 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:44 PM PDT 24
Peak memory 215416 kb
Host smart-55a244e4-4717-4d20-8761-ac5ca5e84147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241117507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3241117507
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3704220633
Short name T458
Test name
Test status
Simulation time 108185333 ps
CPU time 2.11 seconds
Started Mar 21 02:00:45 PM PDT 24
Finished Mar 21 02:00:47 PM PDT 24
Peak memory 215476 kb
Host smart-5d4abdec-4acf-4ee3-8069-358bb8c65a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704220633 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3704220633
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1362197615
Short name T198
Test name
Test status
Simulation time 76694859104 ps
CPU time 1705.7 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:29:11 PM PDT 24
Peak memory 224032 kb
Host smart-3ea7fc84-ccb2-4bbe-b165-b31cd9587fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362197615 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1362197615
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2474247694
Short name T424
Test name
Test status
Simulation time 57937208 ps
CPU time 1.42 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:40 PM PDT 24
Peak memory 218100 kb
Host smart-33df8358-5f17-4d5b-9e9a-92d75ce6f736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474247694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2474247694
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.283097330
Short name T364
Test name
Test status
Simulation time 65556689 ps
CPU time 1.64 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 218260 kb
Host smart-d41ccd20-40b5-43c7-91c0-7d30dc2dc3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283097330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.283097330
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3336770490
Short name T525
Test name
Test status
Simulation time 66865360 ps
CPU time 1.31 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:43 PM PDT 24
Peak memory 219088 kb
Host smart-df2fd2d0-10dc-4a90-85c4-2f67394aa4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336770490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3336770490
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.495793174
Short name T708
Test name
Test status
Simulation time 25562336 ps
CPU time 1.23 seconds
Started Mar 21 02:02:40 PM PDT 24
Finished Mar 21 02:02:41 PM PDT 24
Peak memory 216908 kb
Host smart-209a72d5-18be-4f68-b37c-a9009210897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495793174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.495793174
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1615923758
Short name T174
Test name
Test status
Simulation time 277748309 ps
CPU time 1.06 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:40 PM PDT 24
Peak memory 216716 kb
Host smart-96ec2988-e3e0-4b01-9eca-39ad975601db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615923758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1615923758
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1081101132
Short name T288
Test name
Test status
Simulation time 86166910 ps
CPU time 1.14 seconds
Started Mar 21 02:02:41 PM PDT 24
Finished Mar 21 02:02:42 PM PDT 24
Peak memory 215456 kb
Host smart-b2194622-ccfc-4451-bd76-309cf3d30319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081101132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1081101132
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2428526687
Short name T562
Test name
Test status
Simulation time 101866490 ps
CPU time 2.98 seconds
Started Mar 21 02:02:42 PM PDT 24
Finished Mar 21 02:02:46 PM PDT 24
Peak memory 217984 kb
Host smart-8ad69e17-2cc1-4df6-893d-b209323b261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428526687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2428526687
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4270826797
Short name T754
Test name
Test status
Simulation time 84569549 ps
CPU time 1.08 seconds
Started Mar 21 02:02:38 PM PDT 24
Finished Mar 21 02:02:39 PM PDT 24
Peak memory 216752 kb
Host smart-dd158b32-463a-4668-ba09-1b99cf66ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270826797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4270826797
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.346593419
Short name T634
Test name
Test status
Simulation time 18591780 ps
CPU time 1.1 seconds
Started Mar 21 02:02:39 PM PDT 24
Finished Mar 21 02:02:40 PM PDT 24
Peak memory 219324 kb
Host smart-2841a624-b5b2-4ec5-a8b7-22761888f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346593419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.346593419
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2717492710
Short name T621
Test name
Test status
Simulation time 29381378 ps
CPU time 1.28 seconds
Started Mar 21 01:59:21 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 215768 kb
Host smart-c3a1d998-7cd9-4893-8452-2f94d0ab690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717492710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2717492710
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable.2432400719
Short name T560
Test name
Test status
Simulation time 21539033 ps
CPU time 0.87 seconds
Started Mar 21 01:59:37 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 216068 kb
Host smart-ada801f6-57d4-4461-bb52-474f9e86cc48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432400719 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2432400719
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.384625253
Short name T539
Test name
Test status
Simulation time 38741386 ps
CPU time 1.32 seconds
Started Mar 21 01:59:37 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 218984 kb
Host smart-73947ed6-f84c-4952-bca7-c68d0ef2ac21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384625253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.384625253
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3885696192
Short name T786
Test name
Test status
Simulation time 73459469 ps
CPU time 1.1 seconds
Started Mar 21 01:59:33 PM PDT 24
Finished Mar 21 01:59:35 PM PDT 24
Peak memory 219508 kb
Host smart-81bd8aec-88b2-4dcd-a288-6e53409cc358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885696192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3885696192
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.148581219
Short name T287
Test name
Test status
Simulation time 180865038 ps
CPU time 1.21 seconds
Started Mar 21 01:59:30 PM PDT 24
Finished Mar 21 01:59:31 PM PDT 24
Peak memory 216696 kb
Host smart-157179e0-3c48-4d18-aac9-20ce4a7011bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148581219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.148581219
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2431022181
Short name T395
Test name
Test status
Simulation time 21689436 ps
CPU time 1.1 seconds
Started Mar 21 01:59:21 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 215544 kb
Host smart-563bdcbf-80a1-4f80-b1f7-98e61325ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431022181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2431022181
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1651719215
Short name T252
Test name
Test status
Simulation time 27537105 ps
CPU time 0.91 seconds
Started Mar 21 01:59:22 PM PDT 24
Finished Mar 21 01:59:24 PM PDT 24
Peak memory 207284 kb
Host smart-44890911-0aed-49f8-826b-878afea7250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651719215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1651719215
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1032212989
Short name T456
Test name
Test status
Simulation time 17796777 ps
CPU time 0.97 seconds
Started Mar 21 01:59:21 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 215408 kb
Host smart-aa686d57-325e-4cf4-b1ee-cd7fcf220d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032212989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1032212989
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3325886992
Short name T566
Test name
Test status
Simulation time 137961821 ps
CPU time 1.37 seconds
Started Mar 21 01:59:21 PM PDT 24
Finished Mar 21 01:59:23 PM PDT 24
Peak memory 206008 kb
Host smart-485bac15-716c-4daa-88cf-83965ee380dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325886992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3325886992
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2249204907
Short name T408
Test name
Test status
Simulation time 556223261238 ps
CPU time 2226.65 seconds
Started Mar 21 01:59:23 PM PDT 24
Finished Mar 21 02:36:30 PM PDT 24
Peak memory 230140 kb
Host smart-71a1f0de-b7a7-41b5-8213-a8d5a075566b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249204907 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2249204907
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.860732749
Short name T446
Test name
Test status
Simulation time 66193014 ps
CPU time 0.75 seconds
Started Mar 21 02:00:47 PM PDT 24
Finished Mar 21 02:00:48 PM PDT 24
Peak memory 205696 kb
Host smart-a0e8d4a4-5e88-4d24-87c6-51ada3cc58b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860732749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.860732749
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4200867859
Short name T552
Test name
Test status
Simulation time 13280783 ps
CPU time 0.93 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 216204 kb
Host smart-4581c42b-107a-4b84-876b-ced69fd6d3e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200867859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4200867859
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4114511678
Short name T468
Test name
Test status
Simulation time 27232355 ps
CPU time 1.11 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 217868 kb
Host smart-b34dba58-f47d-4f80-acda-f110df3ecb7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114511678 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4114511678
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.676984281
Short name T67
Test name
Test status
Simulation time 45570850 ps
CPU time 0.9 seconds
Started Mar 21 02:00:48 PM PDT 24
Finished Mar 21 02:00:49 PM PDT 24
Peak memory 219464 kb
Host smart-74341109-398d-4d7a-b4d5-87672405fa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676984281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.676984281
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3042211886
Short name T544
Test name
Test status
Simulation time 57442285 ps
CPU time 1.6 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 218120 kb
Host smart-16c27dc1-56c3-40f6-8f4f-d1d56ea3262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042211886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3042211886
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1151615848
Short name T715
Test name
Test status
Simulation time 22602393 ps
CPU time 1.04 seconds
Started Mar 21 02:00:48 PM PDT 24
Finished Mar 21 02:00:50 PM PDT 24
Peak memory 215548 kb
Host smart-7cf21daf-a875-48dc-bb3d-5247739b2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151615848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1151615848
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3595148592
Short name T694
Test name
Test status
Simulation time 53699384 ps
CPU time 0.94 seconds
Started Mar 21 02:00:42 PM PDT 24
Finished Mar 21 02:00:43 PM PDT 24
Peak memory 215332 kb
Host smart-202651c9-d395-49d6-ac06-96e0c4e804c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595148592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3595148592
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.580738608
Short name T831
Test name
Test status
Simulation time 260584415 ps
CPU time 3.17 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:48 PM PDT 24
Peak memory 219408 kb
Host smart-17646ed4-5049-4b6d-94bb-e186b0bc8115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580738608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.580738608
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1007231994
Short name T189
Test name
Test status
Simulation time 32269823494 ps
CPU time 648.39 seconds
Started Mar 21 02:00:46 PM PDT 24
Finished Mar 21 02:11:35 PM PDT 24
Peak memory 218720 kb
Host smart-c649309e-7419-4005-a326-55ffeb57a425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007231994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1007231994
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2438873867
Short name T180
Test name
Test status
Simulation time 24827754 ps
CPU time 1.23 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 215776 kb
Host smart-87b5d101-df8e-441b-a545-f2fb45255f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438873867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2438873867
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1363320372
Short name T510
Test name
Test status
Simulation time 58293523 ps
CPU time 0.93 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:58 PM PDT 24
Peak memory 206168 kb
Host smart-e77cc26a-a9c5-4179-95fb-0d5773f6d742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363320372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1363320372
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.965232579
Short name T499
Test name
Test status
Simulation time 37398973 ps
CPU time 1.19 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 216756 kb
Host smart-ec78743f-5301-47d4-a52f-414b87ee4a89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965232579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.965232579
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1430278196
Short name T158
Test name
Test status
Simulation time 40021566 ps
CPU time 1.23 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:58 PM PDT 24
Peak memory 231336 kb
Host smart-9b8cc32a-c6d4-4de2-85fd-acf23fada297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430278196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1430278196
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2535304752
Short name T709
Test name
Test status
Simulation time 80050079 ps
CPU time 1.46 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 218164 kb
Host smart-14e11ef1-8073-4003-98ff-4b4cd8bdd4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535304752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2535304752
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3310968341
Short name T573
Test name
Test status
Simulation time 27506327 ps
CPU time 0.95 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 215720 kb
Host smart-e2264321-1584-4d2a-9d6b-bbc154145f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310968341 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3310968341
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2191473117
Short name T680
Test name
Test status
Simulation time 17186610 ps
CPU time 1.04 seconds
Started Mar 21 02:00:44 PM PDT 24
Finished Mar 21 02:00:46 PM PDT 24
Peak memory 215468 kb
Host smart-d1b2e955-0939-46b2-a66e-057b3943bf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191473117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2191473117
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.631242672
Short name T714
Test name
Test status
Simulation time 355203304 ps
CPU time 2.46 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 216652 kb
Host smart-412bdd40-3387-4e6f-b4ee-97bf14512535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631242672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.631242672
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1965186845
Short name T438
Test name
Test status
Simulation time 98053154926 ps
CPU time 944.91 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:16:42 PM PDT 24
Peak memory 222980 kb
Host smart-2bc10000-9b60-4c62-97e1-f8e244ef805d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965186845 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1965186845
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2303593026
Short name T813
Test name
Test status
Simulation time 186692493 ps
CPU time 1.09 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 215780 kb
Host smart-2be6fbd5-c6fd-4427-b12b-3822107c76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303593026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2303593026
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3926394466
Short name T403
Test name
Test status
Simulation time 32554502 ps
CPU time 0.83 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 206148 kb
Host smart-e85afc69-8950-4d27-bd64-30c30e0a614b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926394466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3926394466
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3365500817
Short name T534
Test name
Test status
Simulation time 32042180 ps
CPU time 0.83 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:58 PM PDT 24
Peak memory 216008 kb
Host smart-b9c9b464-1232-4985-b833-818862cf893d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365500817 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3365500817
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1028767801
Short name T75
Test name
Test status
Simulation time 113020139 ps
CPU time 1.02 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 216728 kb
Host smart-22f86f4e-606a-4041-aec3-fca618bf4300
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028767801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1028767801
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3793975646
Short name T613
Test name
Test status
Simulation time 30134337 ps
CPU time 0.9 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:58 PM PDT 24
Peak memory 218068 kb
Host smart-3a4e12bd-fef5-4acc-8d91-f0efb099c8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793975646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3793975646
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2563393337
Short name T284
Test name
Test status
Simulation time 79064484 ps
CPU time 1.37 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 218168 kb
Host smart-4b4e1f4c-f6c6-4899-b136-3af20d763e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563393337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2563393337
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3731499862
Short name T128
Test name
Test status
Simulation time 29584041 ps
CPU time 0.85 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 215712 kb
Host smart-27c4bc40-ff9c-4ad2-977b-7f2e39710add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731499862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3731499862
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1447165918
Short name T310
Test name
Test status
Simulation time 85110281 ps
CPU time 0.88 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 215400 kb
Host smart-36fe3a6b-7a4f-40ba-8d2f-996d2bf6959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447165918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1447165918
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4146946200
Short name T201
Test name
Test status
Simulation time 364053125 ps
CPU time 6.87 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:01:05 PM PDT 24
Peak memory 219640 kb
Host smart-e54f5a07-5b60-4d02-beec-64ef92ca2f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146946200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4146946200
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2065189572
Short name T25
Test name
Test status
Simulation time 120774023703 ps
CPU time 1386.42 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:24:04 PM PDT 24
Peak memory 223828 kb
Host smart-c9e95d40-054b-4d21-be5b-a6d4c9a11d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065189572 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2065189572
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3233051088
Short name T62
Test name
Test status
Simulation time 31121079 ps
CPU time 1.3 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:58 PM PDT 24
Peak memory 215784 kb
Host smart-af9e16d1-b69b-4d70-b1d9-9217fb208896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233051088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3233051088
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2583690353
Short name T761
Test name
Test status
Simulation time 38344196 ps
CPU time 0.8 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 205824 kb
Host smart-2ad1ad8c-ea41-457e-be7f-08fd91021db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583690353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2583690353
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1215871887
Short name T630
Test name
Test status
Simulation time 13425791 ps
CPU time 0.87 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 216264 kb
Host smart-31d0cd8f-f5aa-41d0-9643-f10251a0b3e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215871887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1215871887
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.4147806544
Short name T166
Test name
Test status
Simulation time 25629881 ps
CPU time 1.04 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 216680 kb
Host smart-6064f228-3cdc-47ea-9772-64a66b203de6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147806544 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.4147806544
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1604442300
Short name T676
Test name
Test status
Simulation time 29116343 ps
CPU time 1.36 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 224340 kb
Host smart-50301a4a-ae03-4c78-a510-6ca9b05ed364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604442300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1604442300
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3283404191
Short name T292
Test name
Test status
Simulation time 32503371 ps
CPU time 1.37 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 218264 kb
Host smart-18dc8bdf-f6ad-4395-8a02-2722a3042ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283404191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3283404191
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1120570986
Short name T34
Test name
Test status
Simulation time 25304267 ps
CPU time 1.12 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 224100 kb
Host smart-20f11dcf-7aa1-4d60-9189-6ab922c64513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120570986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1120570986
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2638968890
Short name T312
Test name
Test status
Simulation time 47816411 ps
CPU time 0.94 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:58 PM PDT 24
Peak memory 215364 kb
Host smart-75fee996-f6df-48e7-8f5a-a1d03697d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638968890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2638968890
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.56052211
Short name T647
Test name
Test status
Simulation time 610215284 ps
CPU time 2.33 seconds
Started Mar 21 02:01:24 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 216904 kb
Host smart-dcd89c2b-870e-42d3-b097-8bbb61d3b331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56052211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.56052211
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2558614050
Short name T528
Test name
Test status
Simulation time 247070377434 ps
CPU time 1367.62 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:23:43 PM PDT 24
Peak memory 225152 kb
Host smart-4fc545a6-689b-453c-9b83-dcbbceb58b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558614050 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2558614050
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2490441576
Short name T147
Test name
Test status
Simulation time 43135159 ps
CPU time 1.26 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 215744 kb
Host smart-cdda0bf7-6678-49e3-80ca-8a5f36ca7e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490441576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2490441576
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2979757804
Short name T801
Test name
Test status
Simulation time 202662736 ps
CPU time 0.99 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 206224 kb
Host smart-f1aba234-e242-4335-b4c3-8d9daafed82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979757804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2979757804
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2161113723
Short name T160
Test name
Test status
Simulation time 16489918 ps
CPU time 0.82 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 216024 kb
Host smart-c23f53f0-8fd1-40ad-bf4c-5913bb108ff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161113723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2161113723
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2772721380
Short name T229
Test name
Test status
Simulation time 37281562 ps
CPU time 0.99 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:55 PM PDT 24
Peak memory 217968 kb
Host smart-79aee671-3a69-4e83-9778-07fb489c586e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772721380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2772721380
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3478636141
Short name T514
Test name
Test status
Simulation time 19942718 ps
CPU time 1.02 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 218124 kb
Host smart-d68034cf-6fe7-455d-adb3-ad2e4875038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478636141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3478636141
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.50377190
Short name T827
Test name
Test status
Simulation time 55958553 ps
CPU time 1.29 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 216944 kb
Host smart-37ba691f-c242-4183-8e3e-25ce3775d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50377190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.50377190
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2490870342
Short name T226
Test name
Test status
Simulation time 44200551 ps
CPU time 0.84 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 215400 kb
Host smart-9f753339-53ce-4543-814c-8639579fa82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490870342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2490870342
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2086106263
Short name T546
Test name
Test status
Simulation time 23108254 ps
CPU time 0.92 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 215520 kb
Host smart-8d008a5b-a1c2-498c-ba98-19ef8fb3de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086106263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2086106263
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.831433155
Short name T721
Test name
Test status
Simulation time 1622248833 ps
CPU time 4.84 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:01:02 PM PDT 24
Peak memory 216624 kb
Host smart-44bd7890-1ca4-4aa2-a0a2-5de5a2ac6e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831433155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.831433155
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.364101442
Short name T554
Test name
Test status
Simulation time 893922652221 ps
CPU time 2442.25 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:41:39 PM PDT 24
Peak memory 227900 kb
Host smart-b7521373-8b19-43c0-9c2a-7f7c8cde3f99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364101442 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.364101442
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.828320121
Short name T95
Test name
Test status
Simulation time 49184314 ps
CPU time 1.2 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 215780 kb
Host smart-ea531d36-55ac-4222-ad27-3a022d0a829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828320121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.828320121
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.967977286
Short name T478
Test name
Test status
Simulation time 34995923 ps
CPU time 0.81 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 205992 kb
Host smart-0c6aa275-d273-4b6f-988f-bec728ff8dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967977286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.967977286
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.479559251
Short name T65
Test name
Test status
Simulation time 22125106 ps
CPU time 1.03 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:55 PM PDT 24
Peak memory 216716 kb
Host smart-2a6a093a-9225-4afd-b5f5-5288f4d63918
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479559251 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.479559251
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2736654599
Short name T101
Test name
Test status
Simulation time 33921242 ps
CPU time 1.02 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 232528 kb
Host smart-85b60354-5577-4b8b-8f24-9a95e70ee9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736654599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2736654599
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3390049056
Short name T279
Test name
Test status
Simulation time 71389253 ps
CPU time 1.11 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 217924 kb
Host smart-a0759d56-730f-43db-9d43-9a6b8312768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390049056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3390049056
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2448646373
Short name T335
Test name
Test status
Simulation time 20577647 ps
CPU time 1.19 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 224088 kb
Host smart-ecf97f65-e610-462b-b9ac-5b75b1a24b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448646373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2448646373
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3481954687
Short name T732
Test name
Test status
Simulation time 58903882 ps
CPU time 0.9 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:55 PM PDT 24
Peak memory 215412 kb
Host smart-71a52c5f-5660-4f0f-9108-b9027f84a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481954687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3481954687
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2671360156
Short name T704
Test name
Test status
Simulation time 590193755 ps
CPU time 1.76 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 216508 kb
Host smart-ad09958f-8db4-4c00-92b1-8cafe6f5c3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671360156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2671360156
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2552483561
Short name T26
Test name
Test status
Simulation time 134033047536 ps
CPU time 1406.33 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:24:23 PM PDT 24
Peak memory 223484 kb
Host smart-7f3e92a1-6d84-4811-abac-2bd7a5a7e2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552483561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2552483561
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3996536444
Short name T590
Test name
Test status
Simulation time 28854993 ps
CPU time 1.3 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:55 PM PDT 24
Peak memory 215820 kb
Host smart-338c1565-d978-4a66-892e-4aa7bbd92ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996536444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3996536444
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1537594689
Short name T543
Test name
Test status
Simulation time 20792454 ps
CPU time 0.86 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 206660 kb
Host smart-a72fa09a-621a-488d-bfb2-995eca6bc8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537594689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1537594689
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1147245625
Short name T361
Test name
Test status
Simulation time 19605545 ps
CPU time 0.85 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 215700 kb
Host smart-c63d2b54-54b9-452e-a110-552a572243cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147245625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1147245625
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.683164496
Short name T9
Test name
Test status
Simulation time 40227247 ps
CPU time 1.33 seconds
Started Mar 21 02:01:07 PM PDT 24
Finished Mar 21 02:01:09 PM PDT 24
Peak memory 216476 kb
Host smart-ef3beab5-a754-4122-a200-07390b5dabc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683164496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.683164496
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.20964903
Short name T100
Test name
Test status
Simulation time 30370915 ps
CPU time 0.84 seconds
Started Mar 21 02:00:55 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 218040 kb
Host smart-2a35a671-b0df-4972-af92-359c05ff24ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20964903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.20964903
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2410796388
Short name T517
Test name
Test status
Simulation time 68703497 ps
CPU time 1.03 seconds
Started Mar 21 02:00:54 PM PDT 24
Finished Mar 21 02:00:56 PM PDT 24
Peak memory 216592 kb
Host smart-6b6eeee0-3229-4a6c-abf8-14667beae0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410796388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2410796388
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1033260213
Short name T135
Test name
Test status
Simulation time 60948265 ps
CPU time 0.79 seconds
Started Mar 21 02:00:58 PM PDT 24
Finished Mar 21 02:00:59 PM PDT 24
Peak memory 215696 kb
Host smart-5ffad441-4139-47f5-bc0a-f119d77ceda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033260213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1033260213
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2868571039
Short name T654
Test name
Test status
Simulation time 18485122 ps
CPU time 0.98 seconds
Started Mar 21 02:00:56 PM PDT 24
Finished Mar 21 02:00:57 PM PDT 24
Peak memory 215436 kb
Host smart-2f52f328-701b-4b94-bb84-f7ab3f311dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868571039 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2868571039
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2726449768
Short name T2
Test name
Test status
Simulation time 933763340 ps
CPU time 3.14 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:01:01 PM PDT 24
Peak memory 215360 kb
Host smart-21d4370f-2f4b-445e-9f0c-0c787dac99eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726449768 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2726449768
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.121241979
Short name T759
Test name
Test status
Simulation time 172649111815 ps
CPU time 1961.31 seconds
Started Mar 21 02:00:57 PM PDT 24
Finished Mar 21 02:33:39 PM PDT 24
Peak memory 225232 kb
Host smart-6ce47a02-12ce-4f26-a0be-96428697d747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121241979 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.121241979
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.1776295047
Short name T389
Test name
Test status
Simulation time 36880235 ps
CPU time 0.93 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 206180 kb
Host smart-682000fc-ee13-4c54-9114-1937a4909a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776295047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1776295047
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2260575037
Short name T182
Test name
Test status
Simulation time 104441249 ps
CPU time 0.85 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 216080 kb
Host smart-8c654f5d-c92c-4bb8-93d7-55fcd25417ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260575037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2260575037
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3950867169
Short name T84
Test name
Test status
Simulation time 41586552 ps
CPU time 1.37 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 216572 kb
Host smart-0aa02ad2-2091-45ae-a277-f2a25b0216d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950867169 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3950867169
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3261795582
Short name T78
Test name
Test status
Simulation time 25021302 ps
CPU time 1.12 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 232476 kb
Host smart-37eb7a60-d27b-4345-b62b-17309e6909cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261795582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3261795582
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2686443177
Short name T388
Test name
Test status
Simulation time 274113037 ps
CPU time 1.53 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 218500 kb
Host smart-b62683f6-8fc8-40f3-b7a2-15e102031899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686443177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2686443177
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.4251534355
Short name T385
Test name
Test status
Simulation time 24665361 ps
CPU time 1.01 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:15 PM PDT 24
Peak memory 215724 kb
Host smart-c07720b9-016f-495c-8dbd-e9a65ddad2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251534355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.4251534355
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3719435768
Short name T317
Test name
Test status
Simulation time 22527948 ps
CPU time 1.01 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 215412 kb
Host smart-ef5e2ab7-79e3-4a43-af65-3330b0886c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719435768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3719435768
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.4173037408
Short name T610
Test name
Test status
Simulation time 192679785 ps
CPU time 4.14 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 216824 kb
Host smart-2b286e37-dc55-46a3-806e-6ded102c51fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173037408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.4173037408
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1180690225
Short name T569
Test name
Test status
Simulation time 195391887559 ps
CPU time 1311.64 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:23:02 PM PDT 24
Peak memory 224944 kb
Host smart-211bff52-4891-4545-9243-ee978bd340cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180690225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1180690225
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.4177588906
Short name T116
Test name
Test status
Simulation time 52296009 ps
CPU time 1.28 seconds
Started Mar 21 02:01:08 PM PDT 24
Finished Mar 21 02:01:09 PM PDT 24
Peak memory 215820 kb
Host smart-b365f500-b3b0-4990-ab29-a2bdbe6f1545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177588906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.4177588906
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.195246483
Short name T304
Test name
Test status
Simulation time 31520425 ps
CPU time 1.14 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 206268 kb
Host smart-528b5ce9-bd6d-40f4-9632-81d2a9587767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195246483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.195246483
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.558525930
Short name T104
Test name
Test status
Simulation time 20237112 ps
CPU time 0.91 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 216004 kb
Host smart-04ac76f5-6a45-4ec4-8903-1675cf9066f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558525930 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.558525930
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2104969001
Short name T640
Test name
Test status
Simulation time 37974716 ps
CPU time 1.1 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 217980 kb
Host smart-bca37ee3-6ed7-4d36-b1da-73783abacc07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104969001 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2104969001
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1184705120
Short name T57
Test name
Test status
Simulation time 25928053 ps
CPU time 1.17 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 219384 kb
Host smart-6e7a89bb-17c5-46a5-9241-6d301b6a723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184705120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1184705120
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_intr.1755830975
Short name T136
Test name
Test status
Simulation time 21413743 ps
CPU time 1.08 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 215828 kb
Host smart-de211aa9-a3a0-4c47-b267-a1a26505bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755830975 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1755830975
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3582205046
Short name T460
Test name
Test status
Simulation time 67188781 ps
CPU time 0.94 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 215424 kb
Host smart-dec522e2-54a9-412a-8135-73dc73614e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582205046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3582205046
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.92921515
Short name T540
Test name
Test status
Simulation time 308669966 ps
CPU time 3.55 seconds
Started Mar 21 02:01:08 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 219492 kb
Host smart-27354f62-8534-4c72-998e-6fea68de284c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92921515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.92921515
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3883736426
Short name T187
Test name
Test status
Simulation time 304718971380 ps
CPU time 1987.35 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:34:19 PM PDT 24
Peak memory 227636 kb
Host smart-98e2f054-953c-4e02-a3c1-2b923fe1da9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883736426 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3883736426
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3603752325
Short name T17
Test name
Test status
Simulation time 54827202 ps
CPU time 1.16 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 215776 kb
Host smart-3da8f6f1-cf47-42fe-b564-bb4e31bf996b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603752325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3603752325
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.123159913
Short name T299
Test name
Test status
Simulation time 20553061 ps
CPU time 0.99 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 206184 kb
Host smart-d829748f-d89c-4b24-8743-46c42c0bbef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123159913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.123159913
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3133092546
Short name T734
Test name
Test status
Simulation time 14054435 ps
CPU time 0.97 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 216188 kb
Host smart-d28f27f9-f795-4c71-98cc-ecd01349fb1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133092546 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3133092546
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1731138172
Short name T184
Test name
Test status
Simulation time 91238207 ps
CPU time 1.11 seconds
Started Mar 21 02:01:08 PM PDT 24
Finished Mar 21 02:01:09 PM PDT 24
Peak memory 216808 kb
Host smart-8b8471d1-11eb-43fe-a5c9-85d49d1769a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731138172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1731138172
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.494432793
Short name T608
Test name
Test status
Simulation time 60889108 ps
CPU time 1.1 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 220328 kb
Host smart-66c2d839-aa1f-45af-8d99-f0620d135fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494432793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.494432793
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1609630402
Short name T367
Test name
Test status
Simulation time 73972605 ps
CPU time 2.27 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 218636 kb
Host smart-b23ec654-f891-4007-848b-c95acadda704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609630402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1609630402
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.51387691
Short name T5
Test name
Test status
Simulation time 35394253 ps
CPU time 1.05 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 224088 kb
Host smart-af63c9f7-c89f-49cb-b9ca-de9014670ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51387691 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.51387691
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.27799458
Short name T524
Test name
Test status
Simulation time 19918474 ps
CPU time 1.11 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 215424 kb
Host smart-23baa6d4-12b9-4910-81a8-2298c2deed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27799458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.27799458
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3433371213
Short name T484
Test name
Test status
Simulation time 582280700 ps
CPU time 2.44 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 219548 kb
Host smart-2eeb6f96-8c93-439a-b0f5-8ea4b3bd92bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433371213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3433371213
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.3778930790
Short name T60
Test name
Test status
Simulation time 76661755 ps
CPU time 1.15 seconds
Started Mar 21 01:59:36 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 215808 kb
Host smart-b4c8c80f-3130-4694-9bb7-159042baac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778930790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3778930790
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2166267994
Short name T550
Test name
Test status
Simulation time 21917918 ps
CPU time 0.95 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 206976 kb
Host smart-64b99c48-0cdf-4392-ac07-bbffe2f34a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166267994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2166267994
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3996740582
Short name T836
Test name
Test status
Simulation time 79764614 ps
CPU time 1.08 seconds
Started Mar 21 01:59:32 PM PDT 24
Finished Mar 21 01:59:34 PM PDT 24
Peak memory 216844 kb
Host smart-55e522c9-4306-4734-b4ec-233dbf34e67b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996740582 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3996740582
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3470057309
Short name T773
Test name
Test status
Simulation time 18430693 ps
CPU time 1.06 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 218160 kb
Host smart-baf0a58b-17e8-44ea-9c97-99ce26a71b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470057309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3470057309
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3990970066
Short name T677
Test name
Test status
Simulation time 66296852 ps
CPU time 0.99 seconds
Started Mar 21 01:59:37 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 216760 kb
Host smart-0a798691-9081-4b01-b42d-db3f243ea292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990970066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3990970066
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.259303042
Short name T523
Test name
Test status
Simulation time 28040624 ps
CPU time 0.91 seconds
Started Mar 21 01:59:34 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 207268 kb
Host smart-9efcdcb2-410f-486d-bdc2-d0db907a60d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259303042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.259303042
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3085779191
Short name T22
Test name
Test status
Simulation time 359052963 ps
CPU time 3.31 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:39 PM PDT 24
Peak memory 233508 kb
Host smart-90de994f-50fd-4135-85a1-b535a3633fb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085779191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3085779191
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1703899022
Short name T496
Test name
Test status
Simulation time 17936309 ps
CPU time 0.93 seconds
Started Mar 21 01:59:45 PM PDT 24
Finished Mar 21 01:59:48 PM PDT 24
Peak memory 215440 kb
Host smart-6d34752b-f077-41d2-ad3f-3df0169568e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703899022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1703899022
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1644260868
Short name T744
Test name
Test status
Simulation time 141779241 ps
CPU time 3.3 seconds
Started Mar 21 01:59:34 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 216680 kb
Host smart-d17e5386-73c1-4a53-bdfa-358d2abd85b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644260868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1644260868
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.306293003
Short name T391
Test name
Test status
Simulation time 51639011613 ps
CPU time 1312.28 seconds
Started Mar 21 01:59:33 PM PDT 24
Finished Mar 21 02:21:26 PM PDT 24
Peak memory 223384 kb
Host smart-d0ede9d3-be16-463f-af80-da3ca86afcfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306293003 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.306293003
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4166672994
Short name T18
Test name
Test status
Simulation time 81714621 ps
CPU time 1.21 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 215792 kb
Host smart-880b7c40-99d2-4697-bffd-7263c710cd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166672994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4166672994
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3600771216
Short name T350
Test name
Test status
Simulation time 88265848 ps
CPU time 0.93 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 206668 kb
Host smart-e274f44a-d697-45c0-bef5-7cb3ea60cfb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600771216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3600771216
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4187822046
Short name T58
Test name
Test status
Simulation time 35615613 ps
CPU time 1.23 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 216596 kb
Host smart-db48dbc8-4e13-44ba-8c4e-5c6454f1bc09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187822046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4187822046
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.799655390
Short name T97
Test name
Test status
Simulation time 20595168 ps
CPU time 0.99 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 218224 kb
Host smart-b15909a2-90a8-4760-b081-2cedce0abf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799655390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.799655390
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1605980149
Short name T413
Test name
Test status
Simulation time 21961253 ps
CPU time 1.07 seconds
Started Mar 21 02:01:10 PM PDT 24
Finished Mar 21 02:01:11 PM PDT 24
Peak memory 216804 kb
Host smart-079765bd-a3bc-4d09-a12e-71e1bb3bc6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605980149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1605980149
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.685918795
Short name T705
Test name
Test status
Simulation time 42981367 ps
CPU time 0.84 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 215440 kb
Host smart-a8a67cde-9887-4bfc-99c9-13560039f7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685918795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.685918795
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1810418217
Short name T495
Test name
Test status
Simulation time 630631592 ps
CPU time 4.04 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:01:15 PM PDT 24
Peak memory 215448 kb
Host smart-80161c68-718b-4b70-ad52-6eeb536d3223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810418217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1810418217
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2536822559
Short name T627
Test name
Test status
Simulation time 53377324652 ps
CPU time 1438.94 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:25:11 PM PDT 24
Peak memory 223908 kb
Host smart-d6df5d56-baa5-4eef-abf1-e0f9fe2a8bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536822559 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2536822559
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3360218862
Short name T262
Test name
Test status
Simulation time 30209176 ps
CPU time 1.21 seconds
Started Mar 21 02:01:09 PM PDT 24
Finished Mar 21 02:01:10 PM PDT 24
Peak memory 215804 kb
Host smart-4e5e8dbd-f46f-459e-ab76-958061f42176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360218862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3360218862
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2251899837
Short name T321
Test name
Test status
Simulation time 28795286 ps
CPU time 0.84 seconds
Started Mar 21 02:01:17 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 206500 kb
Host smart-aa0b6583-b87e-439e-ad67-1eb214cd3bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251899837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2251899837
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2415788007
Short name T605
Test name
Test status
Simulation time 38953590 ps
CPU time 0.88 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 216000 kb
Host smart-0c44dd76-0963-47ed-bcc1-045b9f8e4fb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415788007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2415788007
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1116781673
Short name T737
Test name
Test status
Simulation time 114525425 ps
CPU time 1.1 seconds
Started Mar 21 02:01:14 PM PDT 24
Finished Mar 21 02:01:15 PM PDT 24
Peak memory 216500 kb
Host smart-d85913b4-d367-44d6-bbfb-fb4a048db72a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116781673 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1116781673
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3034085530
Short name T558
Test name
Test status
Simulation time 26925108 ps
CPU time 0.87 seconds
Started Mar 21 02:01:14 PM PDT 24
Finished Mar 21 02:01:15 PM PDT 24
Peak memory 215480 kb
Host smart-8926cbe0-373d-4600-b029-bc19aef350ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034085530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3034085530
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1825510480
Short name T462
Test name
Test status
Simulation time 130543545 ps
CPU time 1.25 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 216744 kb
Host smart-2e63d21b-d490-41b5-875c-e53f44d77f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825510480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1825510480
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1353292127
Short name T678
Test name
Test status
Simulation time 25070403 ps
CPU time 1.09 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:13 PM PDT 24
Peak memory 224116 kb
Host smart-828ffce6-f454-42d5-a5c9-829392695b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353292127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1353292127
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.778178397
Short name T422
Test name
Test status
Simulation time 41300705 ps
CPU time 0.89 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:01:12 PM PDT 24
Peak memory 215496 kb
Host smart-4a8e5ad5-790e-4cd9-b4d8-67538ae7a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778178397 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.778178397
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2137581052
Short name T719
Test name
Test status
Simulation time 300431174 ps
CPU time 5.88 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 215420 kb
Host smart-3c2cd2f5-f5e5-42d5-94a4-2c0f9b58751b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137581052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2137581052
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.3204568075
Short name T675
Test name
Test status
Simulation time 49531574 ps
CPU time 1.17 seconds
Started Mar 21 02:01:12 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 215808 kb
Host smart-4504d505-892c-4a94-b98a-9ef7486b5e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204568075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3204568075
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.167135111
Short name T788
Test name
Test status
Simulation time 27741689 ps
CPU time 0.92 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:17 PM PDT 24
Peak memory 206116 kb
Host smart-abdb3e8a-db65-4fe7-ac5a-50510a5730a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167135111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.167135111
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.393243362
Short name T830
Test name
Test status
Simulation time 13671480 ps
CPU time 0.93 seconds
Started Mar 21 02:01:17 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 216176 kb
Host smart-1494a280-3b98-4aa5-97b9-2ef0b4283d2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393243362 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.393243362
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.227425765
Short name T8
Test name
Test status
Simulation time 25363975 ps
CPU time 1.45 seconds
Started Mar 21 02:01:17 PM PDT 24
Finished Mar 21 02:01:19 PM PDT 24
Peak memory 229764 kb
Host smart-5b6897bd-703a-4802-9308-fb24260566dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227425765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.227425765
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4040913775
Short name T12
Test name
Test status
Simulation time 22971169 ps
CPU time 1.2 seconds
Started Mar 21 02:01:14 PM PDT 24
Finished Mar 21 02:01:15 PM PDT 24
Peak memory 219420 kb
Host smart-e0e82f8c-9e20-4b9f-83ec-11b70eda136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040913775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4040913775
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3845635324
Short name T130
Test name
Test status
Simulation time 28014067 ps
CPU time 0.89 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 215980 kb
Host smart-92a870b6-0822-4f18-ae52-fa6c22f44d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845635324 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3845635324
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.582571356
Short name T535
Test name
Test status
Simulation time 35201078 ps
CPU time 0.9 seconds
Started Mar 21 02:01:17 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 215404 kb
Host smart-a5adbadf-b935-4762-9a00-faff3991ccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582571356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.582571356
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1448393904
Short name T140
Test name
Test status
Simulation time 1235535280 ps
CPU time 4.96 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 216784 kb
Host smart-e10735a7-4ad1-464d-be74-d149a25fb107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448393904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1448393904
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2446550073
Short name T256
Test name
Test status
Simulation time 375988040 ps
CPU time 1.43 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 215664 kb
Host smart-5a21aed5-f2e1-44cc-a5db-00f4ae11da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446550073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2446550073
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.385937127
Short name T542
Test name
Test status
Simulation time 28819656 ps
CPU time 0.88 seconds
Started Mar 21 02:01:15 PM PDT 24
Finished Mar 21 02:01:17 PM PDT 24
Peak memory 206996 kb
Host smart-61abb302-be10-48c9-bf04-e3a1a9612c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385937127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.385937127
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.970582787
Short name T105
Test name
Test status
Simulation time 45375591 ps
CPU time 0.8 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 216024 kb
Host smart-c86b94f9-d491-4b41-9d4e-d73835a3aeae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970582787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.970582787
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.324206256
Short name T374
Test name
Test status
Simulation time 96762597 ps
CPU time 1.07 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:19 PM PDT 24
Peak memory 216512 kb
Host smart-af56f7fe-5dd7-4ac4-97de-798c47c28b6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324206256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.324206256
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.165258610
Short name T330
Test name
Test status
Simulation time 20988327 ps
CPU time 0.91 seconds
Started Mar 21 02:01:15 PM PDT 24
Finished Mar 21 02:01:17 PM PDT 24
Peak memory 217796 kb
Host smart-60b97ba8-f59e-4ef6-bb7c-f1830285b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165258610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.165258610
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2137445588
Short name T570
Test name
Test status
Simulation time 73803172 ps
CPU time 1.84 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:18 PM PDT 24
Peak memory 219716 kb
Host smart-81847f46-1a37-4662-8378-0036926ce60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137445588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2137445588
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2031359601
Short name T134
Test name
Test status
Simulation time 60419499 ps
CPU time 0.81 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 215692 kb
Host smart-f6e3d16b-e5cd-4bff-ba84-67ce47385223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031359601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2031359601
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1095606195
Short name T141
Test name
Test status
Simulation time 16091237 ps
CPU time 1 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:17 PM PDT 24
Peak memory 215280 kb
Host smart-b4da41be-2849-4edf-b00a-a10127b3edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095606195 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1095606195
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3030889775
Short name T549
Test name
Test status
Simulation time 195264332 ps
CPU time 2.46 seconds
Started Mar 21 02:01:16 PM PDT 24
Finished Mar 21 02:01:19 PM PDT 24
Peak memory 215300 kb
Host smart-21897efb-22eb-418b-b763-f75bb22bd701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030889775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3030889775
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1114675357
Short name T488
Test name
Test status
Simulation time 71306432987 ps
CPU time 1647.45 seconds
Started Mar 21 02:01:11 PM PDT 24
Finished Mar 21 02:28:39 PM PDT 24
Peak memory 226508 kb
Host smart-49dc8819-d112-45eb-9b24-a5aa2678f32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114675357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1114675357
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1613950832
Short name T616
Test name
Test status
Simulation time 78954383 ps
CPU time 1.43 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 215800 kb
Host smart-ac19be7d-37b1-41b6-9ad5-a766ccb9d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613950832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1613950832
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.611481580
Short name T434
Test name
Test status
Simulation time 60643470 ps
CPU time 0.88 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 206656 kb
Host smart-c0e14cf7-b250-44d6-800b-107dee42a5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611481580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.611481580
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_err.3199645647
Short name T79
Test name
Test status
Simulation time 46695553 ps
CPU time 1.03 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 219416 kb
Host smart-b4128c88-fb79-465d-95fc-01b87e23de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199645647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3199645647
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2714375358
Short name T669
Test name
Test status
Simulation time 41575235 ps
CPU time 1.47 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 217644 kb
Host smart-6f058d96-a723-45e0-b3e3-129d157d6af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714375358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2714375358
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1336025157
Short name T23
Test name
Test status
Simulation time 22438250 ps
CPU time 1.18 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 215540 kb
Host smart-749426eb-1b4c-4987-9983-0e37987752e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336025157 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1336025157
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1313846652
Short name T437
Test name
Test status
Simulation time 13878649 ps
CPU time 0.97 seconds
Started Mar 21 02:01:13 PM PDT 24
Finished Mar 21 02:01:14 PM PDT 24
Peak memory 215376 kb
Host smart-00106d27-f04e-4981-a7f8-03dcaadaaabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313846652 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1313846652
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.4009586073
Short name T311
Test name
Test status
Simulation time 19613744 ps
CPU time 1.06 seconds
Started Mar 21 02:01:30 PM PDT 24
Finished Mar 21 02:01:31 PM PDT 24
Peak memory 206080 kb
Host smart-4feb1b51-c76a-4bb9-81db-62847c3b4a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009586073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.4009586073
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.469973926
Short name T188
Test name
Test status
Simulation time 159611939500 ps
CPU time 1051.3 seconds
Started Mar 21 02:01:30 PM PDT 24
Finished Mar 21 02:19:02 PM PDT 24
Peak memory 223036 kb
Host smart-c05e29a9-2796-4962-8b17-31989719dd56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469973926 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.469973926
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2226011824
Short name T254
Test name
Test status
Simulation time 47016107 ps
CPU time 1.21 seconds
Started Mar 21 02:01:22 PM PDT 24
Finished Mar 21 02:01:24 PM PDT 24
Peak memory 215780 kb
Host smart-d01e2a31-ba29-4259-ab8b-13cbeb7d05e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226011824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2226011824
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1877710382
Short name T407
Test name
Test status
Simulation time 17103178 ps
CPU time 0.95 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 206676 kb
Host smart-5f5c98e1-5f23-45fa-ad8b-212768acae2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877710382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1877710382
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3167460510
Short name T768
Test name
Test status
Simulation time 15558691 ps
CPU time 0.89 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 216004 kb
Host smart-4df2783c-d6b6-4023-b00e-ddc7081d35fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167460510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3167460510
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.1653990339
Short name T53
Test name
Test status
Simulation time 30789153 ps
CPU time 1.25 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:26 PM PDT 24
Peak memory 219304 kb
Host smart-be6604f8-3a7c-4b64-924f-ef92b16c305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653990339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1653990339
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3267536000
Short name T228
Test name
Test status
Simulation time 93661420 ps
CPU time 1.06 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 216644 kb
Host smart-df8479e8-6120-4372-9183-fd1675abaf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267536000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3267536000
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3667405235
Short name T122
Test name
Test status
Simulation time 28330310 ps
CPU time 0.92 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 215884 kb
Host smart-b9312ffa-9d2b-4e32-951a-dc04db2d0150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667405235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3667405235
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3880810475
Short name T792
Test name
Test status
Simulation time 20126162 ps
CPU time 0.94 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 215420 kb
Host smart-fca4799d-3055-479e-b38b-6147d36b0a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880810475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3880810475
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.89876441
Short name T829
Test name
Test status
Simulation time 138544565 ps
CPU time 3.06 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 217900 kb
Host smart-9afbfe65-460c-4734-801f-95b27f5543d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89876441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.89876441
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2412634059
Short name T657
Test name
Test status
Simulation time 8757218677 ps
CPU time 219.87 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:05:06 PM PDT 24
Peak memory 221860 kb
Host smart-5250e2d6-8b0c-4521-b4b2-ec46c341cfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412634059 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2412634059
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1967953314
Short name T238
Test name
Test status
Simulation time 60996554 ps
CPU time 1.26 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 215804 kb
Host smart-5d0aa02c-58e9-48b6-89b9-a9392f1c7f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967953314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1967953314
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3850054634
Short name T383
Test name
Test status
Simulation time 28067558 ps
CPU time 0.89 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 205496 kb
Host smart-028161c4-8eb9-4a52-a196-57c803703b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850054634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3850054634
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2992507651
Short name T578
Test name
Test status
Simulation time 21448450 ps
CPU time 0.88 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 216020 kb
Host smart-6e170b9f-411d-48d2-976e-f26222aa4778
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992507651 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2992507651
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.136621090
Short name T618
Test name
Test status
Simulation time 47710051 ps
CPU time 1.22 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 218016 kb
Host smart-95d57557-0af3-433f-8483-dd7b74399043
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136621090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.136621090
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2479676273
Short name T796
Test name
Test status
Simulation time 35059711 ps
CPU time 1.21 seconds
Started Mar 21 02:01:28 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 229628 kb
Host smart-b322551f-968f-4067-aaf5-211e92177852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479676273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2479676273
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2407258941
Short name T453
Test name
Test status
Simulation time 61068098 ps
CPU time 1.17 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 219068 kb
Host smart-c63a7273-b0da-46f8-aca0-cc757904ffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407258941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2407258941
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.556936294
Short name T137
Test name
Test status
Simulation time 24012872 ps
CPU time 0.98 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 215888 kb
Host smart-efcb9fb2-f717-488e-93f0-53746ec790ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556936294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.556936294
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2459130122
Short name T313
Test name
Test status
Simulation time 45832609 ps
CPU time 0.89 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 215400 kb
Host smart-eef5159d-54cf-45cf-a216-32ce185e4c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459130122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2459130122
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4135797402
Short name T713
Test name
Test status
Simulation time 460552671 ps
CPU time 2.87 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 216640 kb
Host smart-3bae3243-7f7e-4ef2-9c3b-a814ccc332e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135797402 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4135797402
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1144174193
Short name T195
Test name
Test status
Simulation time 69067992566 ps
CPU time 435.13 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:08:42 PM PDT 24
Peak memory 218720 kb
Host smart-ce307bed-0231-46d1-bcdb-62e24f2d1ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144174193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1144174193
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1331669479
Short name T764
Test name
Test status
Simulation time 46770755 ps
CPU time 1.09 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 215780 kb
Host smart-db4dcc4f-8838-479a-a9f5-bd29422a4f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331669479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1331669479
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3906653271
Short name T666
Test name
Test status
Simulation time 43803950 ps
CPU time 0.92 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 206160 kb
Host smart-d8209fc1-d726-4939-944c-6d6d7a1236c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906653271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3906653271
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2713539393
Short name T164
Test name
Test status
Simulation time 26386019 ps
CPU time 0.85 seconds
Started Mar 21 02:01:24 PM PDT 24
Finished Mar 21 02:01:25 PM PDT 24
Peak memory 216016 kb
Host smart-58371c8d-dfc2-4701-9ad6-7ac0ec2d83ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713539393 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2713539393
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1340515706
Short name T396
Test name
Test status
Simulation time 31766267 ps
CPU time 1.08 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 217252 kb
Host smart-8e55d4db-5b54-481e-af58-8ac0b1bc2b62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340515706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1340515706
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3052602107
Short name T168
Test name
Test status
Simulation time 32471026 ps
CPU time 0.87 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 217848 kb
Host smart-ab3e866f-4f1b-4e60-8208-56f2918be324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052602107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3052602107
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3394577888
Short name T833
Test name
Test status
Simulation time 91169729 ps
CPU time 1.19 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 216880 kb
Host smart-17341b56-0e83-4468-bd1c-3924cad60862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394577888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3394577888
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1965598039
Short name T393
Test name
Test status
Simulation time 29852203 ps
CPU time 0.93 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 215528 kb
Host smart-b2af11ce-068a-4e82-b314-7c3a9f1875ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965598039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1965598039
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3529738495
Short name T443
Test name
Test status
Simulation time 127990315 ps
CPU time 0.92 seconds
Started Mar 21 02:01:24 PM PDT 24
Finished Mar 21 02:01:25 PM PDT 24
Peak memory 215408 kb
Host smart-5d2d460e-200e-4405-96a9-8b806a91487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529738495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3529738495
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1939756258
Short name T798
Test name
Test status
Simulation time 378059371 ps
CPU time 2.9 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 216660 kb
Host smart-aa79ab32-3096-415f-b4d5-7435884dfe4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939756258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1939756258
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3455056659
Short name T561
Test name
Test status
Simulation time 121508914740 ps
CPU time 1397.74 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:24:44 PM PDT 24
Peak memory 223680 kb
Host smart-7b3e4604-052c-4478-9533-16185d877e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455056659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3455056659
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1021288990
Short name T603
Test name
Test status
Simulation time 36182834 ps
CPU time 1.21 seconds
Started Mar 21 02:01:29 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 215760 kb
Host smart-6d796c6a-b8ad-433b-a49f-ffa1c1a94ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021288990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1021288990
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3417596565
Short name T717
Test name
Test status
Simulation time 49757500 ps
CPU time 0.83 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 206480 kb
Host smart-7c0afbc8-9e22-4945-914b-3fde4e9323fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417596565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3417596565
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2105542329
Short name T82
Test name
Test status
Simulation time 43760583 ps
CPU time 1.4 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 216560 kb
Host smart-22e8d60d-4594-414e-b2c1-25da59397af9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105542329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2105542329
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.399934891
Short name T601
Test name
Test status
Simulation time 41558823 ps
CPU time 1.6 seconds
Started Mar 21 02:01:30 PM PDT 24
Finished Mar 21 02:01:31 PM PDT 24
Peak memory 218136 kb
Host smart-a0770b96-0834-4fe0-b760-1df46a2a7e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399934891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.399934891
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4287307294
Short name T302
Test name
Test status
Simulation time 43033246 ps
CPU time 0.91 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 215704 kb
Host smart-b5d552bf-7dda-4398-b523-f98a499b95c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287307294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4287307294
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4206209734
Short name T44
Test name
Test status
Simulation time 19599510 ps
CPU time 0.99 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 215432 kb
Host smart-e9f147fe-7ed8-452e-8798-44df779cba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206209734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4206209734
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2043131675
Short name T31
Test name
Test status
Simulation time 488373316 ps
CPU time 4.69 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:32 PM PDT 24
Peak memory 216476 kb
Host smart-6fa81ad9-078f-475a-ab77-b9256702b796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043131675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2043131675
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1729846794
Short name T548
Test name
Test status
Simulation time 455870834098 ps
CPU time 2082.68 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:36:11 PM PDT 24
Peak memory 225924 kb
Host smart-e6b445c8-c46c-422f-aac6-c69c039e59db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729846794 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1729846794
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.4221785065
Short name T777
Test name
Test status
Simulation time 16973018 ps
CPU time 0.94 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 206192 kb
Host smart-2a266943-fef4-49ec-96bc-e442cefa6a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221785065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4221785065
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2631400623
Short name T50
Test name
Test status
Simulation time 15850645 ps
CPU time 0.96 seconds
Started Mar 21 02:01:30 PM PDT 24
Finished Mar 21 02:01:31 PM PDT 24
Peak memory 216204 kb
Host smart-cdd14bea-6631-4640-9c76-b1335c860e96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631400623 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2631400623
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.148393169
Short name T655
Test name
Test status
Simulation time 23129941 ps
CPU time 1.06 seconds
Started Mar 21 02:01:25 PM PDT 24
Finished Mar 21 02:01:26 PM PDT 24
Peak memory 232488 kb
Host smart-451aec21-eaef-4662-a5ad-a3740050966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148393169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.148393169
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3722375328
Short name T720
Test name
Test status
Simulation time 54234026 ps
CPU time 1.36 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 217984 kb
Host smart-ab4ce0eb-e6d1-4c11-900d-2a2e00190354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722375328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3722375328
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1541252577
Short name T133
Test name
Test status
Simulation time 29112874 ps
CPU time 0.93 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:27 PM PDT 24
Peak memory 215784 kb
Host smart-da9a108f-3fab-4a7e-969e-cc874bb50fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541252577 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1541252577
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.906069194
Short name T648
Test name
Test status
Simulation time 18564910 ps
CPU time 1.03 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 215412 kb
Host smart-3f5983b4-011d-4c80-aba8-e393214f5762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906069194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.906069194
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.379729323
Short name T639
Test name
Test status
Simulation time 2871064312 ps
CPU time 4.77 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:32 PM PDT 24
Peak memory 216844 kb
Host smart-ae7cf5b6-a31f-4048-bd16-760e65413e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379729323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.379729323
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3514484148
Short name T196
Test name
Test status
Simulation time 94092406913 ps
CPU time 909.5 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:16:36 PM PDT 24
Peak memory 221412 kb
Host smart-441cfc85-0487-4607-837c-7ce84b16e03b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514484148 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3514484148
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1121101335
Short name T835
Test name
Test status
Simulation time 92112077 ps
CPU time 1.19 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 215784 kb
Host smart-99b4019d-2490-49e9-81be-9e04a8e511d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121101335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1121101335
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.792706523
Short name T227
Test name
Test status
Simulation time 51499324 ps
CPU time 0.91 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 206652 kb
Host smart-62e30242-58d1-4743-b8b0-cc7c483ec49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792706523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.792706523
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1585716041
Short name T109
Test name
Test status
Simulation time 27193255 ps
CPU time 0.8 seconds
Started Mar 21 01:59:36 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 215996 kb
Host smart-0005a4c5-84fc-4a6d-a53f-21f2f06d2412
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585716041 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1585716041
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2992215435
Short name T343
Test name
Test status
Simulation time 44660387 ps
CPU time 1.42 seconds
Started Mar 21 01:59:38 PM PDT 24
Finished Mar 21 01:59:40 PM PDT 24
Peak memory 216880 kb
Host smart-6249e8aa-1144-401a-9a4d-55b0d9a1506f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992215435 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2992215435
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1500175383
Short name T815
Test name
Test status
Simulation time 38616264 ps
CPU time 0.87 seconds
Started Mar 21 01:59:38 PM PDT 24
Finished Mar 21 01:59:40 PM PDT 24
Peak memory 218136 kb
Host smart-5ddb1ece-1fb8-48df-9e5f-6796ff9b7530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500175383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1500175383
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4020593174
Short name T760
Test name
Test status
Simulation time 100571921 ps
CPU time 1.36 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 218496 kb
Host smart-97b32847-7576-4500-95a1-9f2bce48a92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020593174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4020593174
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1660690876
Short name T702
Test name
Test status
Simulation time 22131788 ps
CPU time 1.08 seconds
Started Mar 21 01:59:37 PM PDT 24
Finished Mar 21 01:59:38 PM PDT 24
Peak memory 215728 kb
Host smart-2d7ae3b9-032a-4b14-bf4e-44e0ae3ecfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660690876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1660690876
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1126024914
Short name T250
Test name
Test status
Simulation time 15937233 ps
CPU time 0.98 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:36 PM PDT 24
Peak memory 207228 kb
Host smart-ab1af7c8-8ca2-48c6-894a-3ea1ffdd9835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126024914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1126024914
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3002228389
Short name T199
Test name
Test status
Simulation time 40726311 ps
CPU time 0.93 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 207208 kb
Host smart-77041c10-4874-4e2a-8681-019540189229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002228389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3002228389
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.668297440
Short name T795
Test name
Test status
Simulation time 174888886 ps
CPU time 3.88 seconds
Started Mar 21 01:59:35 PM PDT 24
Finished Mar 21 01:59:39 PM PDT 24
Peak memory 219564 kb
Host smart-71c352e7-c081-4940-9912-69606554f5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668297440 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.668297440
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1804718787
Short name T138
Test name
Test status
Simulation time 12355741242 ps
CPU time 103.06 seconds
Started Mar 21 01:59:38 PM PDT 24
Finished Mar 21 02:01:22 PM PDT 24
Peak memory 219080 kb
Host smart-79bee50c-0280-44d0-854c-701eac19ac8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804718787 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1804718787
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.391575233
Short name T173
Test name
Test status
Simulation time 44007395 ps
CPU time 1.1 seconds
Started Mar 21 02:01:28 PM PDT 24
Finished Mar 21 02:01:30 PM PDT 24
Peak memory 219356 kb
Host smart-58aa79ce-2e70-433b-81c8-6353df87001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391575233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.391575233
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2884872096
Short name T809
Test name
Test status
Simulation time 50987892 ps
CPU time 1.64 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 217784 kb
Host smart-6474c595-8be5-4ec9-a39c-0fc1ab38aae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884872096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2884872096
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1988014289
Short name T111
Test name
Test status
Simulation time 20953127 ps
CPU time 1.09 seconds
Started Mar 21 02:01:27 PM PDT 24
Finished Mar 21 02:01:28 PM PDT 24
Peak memory 218268 kb
Host smart-8f459aa5-55fb-4d93-8f8a-32b115bd55cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988014289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1988014289
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2253123214
Short name T349
Test name
Test status
Simulation time 208486642 ps
CPU time 3.05 seconds
Started Mar 21 02:01:26 PM PDT 24
Finished Mar 21 02:01:29 PM PDT 24
Peak memory 219456 kb
Host smart-72852c71-0b39-4983-a2a8-68b02d701cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253123214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2253123214
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2238468324
Short name T296
Test name
Test status
Simulation time 40420553 ps
CPU time 1 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 218408 kb
Host smart-568da280-7b80-46a9-8f37-0c557315a268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238468324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2238468324
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3410711876
Short name T645
Test name
Test status
Simulation time 38420675 ps
CPU time 1.5 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 216736 kb
Host smart-47194298-70ba-40cf-a47d-23987b575b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410711876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3410711876
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.20661873
Short name T738
Test name
Test status
Simulation time 27095653 ps
CPU time 0.88 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 217804 kb
Host smart-d5fbc911-56b1-4934-8f5c-c36cd491e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20661873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.20661873
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1808116599
Short name T397
Test name
Test status
Simulation time 45752712 ps
CPU time 1.48 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 216844 kb
Host smart-b88cc2b0-0599-49a1-9eff-9772feb36e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808116599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1808116599
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3939978549
Short name T15
Test name
Test status
Simulation time 18704097 ps
CPU time 1.09 seconds
Started Mar 21 02:01:43 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 223140 kb
Host smart-cb31d9d9-8b29-49bf-8d0c-750fcb37eff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939978549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3939978549
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1479235936
Short name T451
Test name
Test status
Simulation time 56405568 ps
CPU time 1.21 seconds
Started Mar 21 02:01:49 PM PDT 24
Finished Mar 21 02:01:50 PM PDT 24
Peak memory 216704 kb
Host smart-81e5e2af-8d0b-4366-87b8-fa90d9601895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479235936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1479235936
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.320803871
Short name T417
Test name
Test status
Simulation time 30124658 ps
CPU time 0.83 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 217740 kb
Host smart-87f1fdf7-6ba6-4162-b0e1-f5ac5e805828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320803871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.320803871
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1908707790
Short name T363
Test name
Test status
Simulation time 83850581 ps
CPU time 1.28 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 218296 kb
Host smart-c4745aca-5d50-42b3-a5a0-e70effed77ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908707790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1908707790
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3554440245
Short name T108
Test name
Test status
Simulation time 18240852 ps
CPU time 1.03 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 217872 kb
Host smart-2e5ace39-2297-43a1-835f-843d380dc31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554440245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3554440245
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2946503787
Short name T587
Test name
Test status
Simulation time 45954295 ps
CPU time 1.21 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 216968 kb
Host smart-ca72127a-e7aa-4ced-b7ad-81c644bc0c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946503787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2946503787
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.793808552
Short name T323
Test name
Test status
Simulation time 88832313 ps
CPU time 1.08 seconds
Started Mar 21 02:01:38 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 219564 kb
Host smart-52cf737d-7d8e-407b-9ede-4b27e7af8073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793808552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.793808552
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3662988297
Short name T294
Test name
Test status
Simulation time 29448361 ps
CPU time 1.18 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 217744 kb
Host smart-245d5b70-5a12-498b-a6f2-c88cd9f39073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662988297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3662988297
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2490255989
Short name T170
Test name
Test status
Simulation time 41762487 ps
CPU time 1.19 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 224508 kb
Host smart-e3087b51-df46-4f75-9040-5c912f67cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490255989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2490255989
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.152961579
Short name T703
Test name
Test status
Simulation time 221352484 ps
CPU time 1.59 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 218356 kb
Host smart-b4684127-e573-48c5-96f1-812de72cda1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152961579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.152961579
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1400921301
Short name T736
Test name
Test status
Simulation time 27277235 ps
CPU time 0.87 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 217692 kb
Host smart-59910104-e88f-4711-b2ba-34b871b476a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400921301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1400921301
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1352782770
Short name T275
Test name
Test status
Simulation time 57674948 ps
CPU time 1.54 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 217760 kb
Host smart-f784da3e-13fe-4145-9342-db4c798f5d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352782770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1352782770
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3415191536
Short name T145
Test name
Test status
Simulation time 214663179 ps
CPU time 1.3 seconds
Started Mar 21 01:59:47 PM PDT 24
Finished Mar 21 01:59:50 PM PDT 24
Peak memory 215804 kb
Host smart-5dad2eac-6e7d-47ce-bdfb-2035a78be9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415191536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3415191536
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.76341366
Short name T477
Test name
Test status
Simulation time 15993711 ps
CPU time 0.9 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 206160 kb
Host smart-46aee485-6168-490f-b79e-cb01fceaab73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76341366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.76341366
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1864630396
Short name T157
Test name
Test status
Simulation time 46869027 ps
CPU time 0.85 seconds
Started Mar 21 01:59:46 PM PDT 24
Finished Mar 21 01:59:48 PM PDT 24
Peak memory 216020 kb
Host smart-eb5714aa-19f5-494a-adb7-563753b683be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864630396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1864630396
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3312815345
Short name T66
Test name
Test status
Simulation time 149958607 ps
CPU time 1.11 seconds
Started Mar 21 01:59:49 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 216764 kb
Host smart-c12bc0ad-1713-4263-b43a-93e0b5685d9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312815345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3312815345
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.401077382
Short name T71
Test name
Test status
Simulation time 49056623 ps
CPU time 0.97 seconds
Started Mar 21 01:59:49 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 219428 kb
Host smart-172a3eb2-df23-4f1f-a882-ab16d8ab2e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401077382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.401077382
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3129054886
Short name T402
Test name
Test status
Simulation time 57428540 ps
CPU time 1.8 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 218216 kb
Host smart-4b99a783-815e-4a17-aac2-835c07825f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129054886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3129054886
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1609514715
Short name T698
Test name
Test status
Simulation time 22376700 ps
CPU time 1.15 seconds
Started Mar 21 01:59:50 PM PDT 24
Finished Mar 21 01:59:53 PM PDT 24
Peak memory 215552 kb
Host smart-8e7a84f5-d6dd-4783-8ede-0223cf681afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609514715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1609514715
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1694526148
Short name T261
Test name
Test status
Simulation time 39351225 ps
CPU time 0.94 seconds
Started Mar 21 01:59:49 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 207236 kb
Host smart-9623d7b3-6b22-4239-8bb3-9bf18dc6c805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694526148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1694526148
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2571817613
Short name T799
Test name
Test status
Simulation time 44074308 ps
CPU time 0.86 seconds
Started Mar 21 01:59:36 PM PDT 24
Finished Mar 21 01:59:37 PM PDT 24
Peak memory 215240 kb
Host smart-7aa812c7-78ef-450f-8615-337e0d98ad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571817613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2571817613
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.686826222
Short name T513
Test name
Test status
Simulation time 98431153 ps
CPU time 2.54 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:53 PM PDT 24
Peak memory 216752 kb
Host smart-81f978a8-f1ae-45db-b37d-b2793ef3162f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686826222 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.686826222
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.419912073
Short name T193
Test name
Test status
Simulation time 52921582372 ps
CPU time 208.05 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 02:03:17 PM PDT 24
Peak memory 218496 kb
Host smart-bd4d335f-a555-46cf-99d7-6785473000de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419912073 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.419912073
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3764997768
Short name T433
Test name
Test status
Simulation time 25347236 ps
CPU time 1.19 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 220356 kb
Host smart-20f878b8-d96e-4103-b807-004fedc3323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764997768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3764997768
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2416360141
Short name T471
Test name
Test status
Simulation time 73999543 ps
CPU time 1.33 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 218296 kb
Host smart-2334e9c6-4737-4071-a6e2-f8138db003e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416360141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2416360141
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1162436130
Short name T812
Test name
Test status
Simulation time 23170981 ps
CPU time 1.02 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 231328 kb
Host smart-eeed35f2-b3e8-4059-b6ea-9090adc02acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162436130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1162436130
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2753310649
Short name T33
Test name
Test status
Simulation time 73239975 ps
CPU time 2.8 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 217112 kb
Host smart-6141b7ce-ad3a-43d7-a807-0ee5fe3af700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753310649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2753310649
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.361198077
Short name T373
Test name
Test status
Simulation time 28900603 ps
CPU time 0.97 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 217920 kb
Host smart-0ae01545-99e6-4b7d-a9d6-5f6d7cff9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361198077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.361198077
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1540803534
Short name T418
Test name
Test status
Simulation time 60655202 ps
CPU time 1.4 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 217904 kb
Host smart-1c0ad454-678c-49ea-bfb8-9f1c3e2e5444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540803534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1540803534
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.4044219719
Short name T398
Test name
Test status
Simulation time 81856792 ps
CPU time 1.05 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 219364 kb
Host smart-d7b0b3cb-c8c4-4a82-920c-a953145a8261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044219719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4044219719
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.423831536
Short name T463
Test name
Test status
Simulation time 88783397 ps
CPU time 3.06 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 217944 kb
Host smart-317fa5d4-0012-4265-b06c-4944a0d6a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423831536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.423831536
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.580591270
Short name T106
Test name
Test status
Simulation time 24958834 ps
CPU time 1.01 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 223148 kb
Host smart-135173dc-c52b-48c2-9307-102f16d0a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580591270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.580591270
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.4208486746
Short name T662
Test name
Test status
Simulation time 33620937 ps
CPU time 1.5 seconds
Started Mar 21 02:01:43 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 216900 kb
Host smart-71a73e41-c728-4f10-bad6-45fe4d884724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208486746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4208486746
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2296148994
Short name T357
Test name
Test status
Simulation time 32565447 ps
CPU time 0.95 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 218288 kb
Host smart-7a3f2dd6-7d9c-4757-81a4-fe46724c7e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296148994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2296148994
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.87678064
Short name T584
Test name
Test status
Simulation time 50040647 ps
CPU time 1.22 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 219268 kb
Host smart-01bbb5b5-b3c8-469f-bf0b-f6c4dae54a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87678064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.87678064
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.788356348
Short name T331
Test name
Test status
Simulation time 19676738 ps
CPU time 1.08 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 218312 kb
Host smart-bef715f8-3071-412f-b405-7fd34615e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788356348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.788356348
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3232308049
Short name T767
Test name
Test status
Simulation time 58997570 ps
CPU time 1.35 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 219572 kb
Host smart-f87a70ec-6100-4230-8ce8-78545a382da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232308049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3232308049
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2966872501
Short name T728
Test name
Test status
Simulation time 42568347 ps
CPU time 0.86 seconds
Started Mar 21 02:01:43 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 217760 kb
Host smart-c50c62bd-31a0-4579-841d-6f22dd1a4e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966872501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2966872501
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2992200805
Short name T430
Test name
Test status
Simulation time 104230794 ps
CPU time 1.69 seconds
Started Mar 21 02:01:38 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 218352 kb
Host smart-b8542646-d288-473c-9ec1-8d44f2103941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992200805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2992200805
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1216478735
Short name T378
Test name
Test status
Simulation time 40073661 ps
CPU time 1.14 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 219312 kb
Host smart-e06fed4e-305c-43cb-96f6-fbed2f392d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216478735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1216478735
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.663450886
Short name T725
Test name
Test status
Simulation time 278693146 ps
CPU time 1.28 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 216632 kb
Host smart-816dd9bc-a79e-4ed6-aab1-53cf0a848bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663450886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.663450886
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2791204442
Short name T7
Test name
Test status
Simulation time 25308614 ps
CPU time 1.18 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 216900 kb
Host smart-c3d3b621-03d8-4d2c-89dd-8a49003113ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791204442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2791204442
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1839643208
Short name T577
Test name
Test status
Simulation time 322762254 ps
CPU time 1.28 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 216700 kb
Host smart-2b802716-3d8f-40e3-9d9e-719a4f8c74fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839643208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1839643208
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3466988539
Short name T807
Test name
Test status
Simulation time 66908859 ps
CPU time 1.19 seconds
Started Mar 21 01:59:46 PM PDT 24
Finished Mar 21 01:59:49 PM PDT 24
Peak memory 215796 kb
Host smart-c7b4c10f-659c-4eea-8b8b-388621771cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466988539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3466988539
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4221733420
Short name T522
Test name
Test status
Simulation time 36396490 ps
CPU time 1.08 seconds
Started Mar 21 01:59:47 PM PDT 24
Finished Mar 21 01:59:50 PM PDT 24
Peak memory 206168 kb
Host smart-1016744b-cf22-401f-8f6c-71bacefb85be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221733420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4221733420
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3964402390
Short name T162
Test name
Test status
Simulation time 25005642 ps
CPU time 0.8 seconds
Started Mar 21 01:59:52 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 216004 kb
Host smart-d458a8c6-603c-4877-a0e9-dbb77e87798b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964402390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3964402390
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2662445438
Short name T107
Test name
Test status
Simulation time 19218257 ps
CPU time 1.04 seconds
Started Mar 21 01:59:52 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 218316 kb
Host smart-ac895c6b-48b6-4528-b756-d1ef32cd4fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662445438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2662445438
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1766643034
Short name T421
Test name
Test status
Simulation time 70409521 ps
CPU time 2.53 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 219616 kb
Host smart-a89e0b81-2fde-490f-9c45-96819872ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766643034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1766643034
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3339854910
Short name T54
Test name
Test status
Simulation time 38144455 ps
CPU time 0.86 seconds
Started Mar 21 01:59:47 PM PDT 24
Finished Mar 21 01:59:49 PM PDT 24
Peak memory 215716 kb
Host smart-f2e6386a-77e8-4178-b4c1-1d0c85816fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339854910 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3339854910
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.1585986112
Short name T416
Test name
Test status
Simulation time 32642020 ps
CPU time 0.96 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 215432 kb
Host smart-e3054e8e-f78c-4219-982b-a78d88313fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585986112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1585986112
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4272488629
Short name T472
Test name
Test status
Simulation time 109355746 ps
CPU time 2.72 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 219420 kb
Host smart-15cbb886-2a13-4436-b5ea-e9d79564acd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272488629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4272488629
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1749058999
Short name T619
Test name
Test status
Simulation time 63489212102 ps
CPU time 1585.94 seconds
Started Mar 21 01:59:49 PM PDT 24
Finished Mar 21 02:26:16 PM PDT 24
Peak memory 225688 kb
Host smart-f7d24d83-4f30-4ac4-877a-da53aa7479da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749058999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1749058999
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1613824365
Short name T436
Test name
Test status
Simulation time 45223208 ps
CPU time 1.06 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 231308 kb
Host smart-d1fc4a4e-e2e8-44dd-b59a-480d146d0350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613824365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1613824365
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1958704263
Short name T537
Test name
Test status
Simulation time 32181250 ps
CPU time 1.38 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 217856 kb
Host smart-78af855c-ad66-4516-8201-fa6e79b94991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958704263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1958704263
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.196590042
Short name T615
Test name
Test status
Simulation time 31238775 ps
CPU time 1.2 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:40 PM PDT 24
Peak memory 219456 kb
Host smart-99185110-cdf2-4bed-873f-5bf1e41b01cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196590042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.196590042
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3896438917
Short name T359
Test name
Test status
Simulation time 101305518 ps
CPU time 1.28 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 218236 kb
Host smart-10aa8eba-012a-46c8-83ef-a23be0de4335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896438917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3896438917
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2082300396
Short name T748
Test name
Test status
Simulation time 69156119 ps
CPU time 1.15 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 224296 kb
Host smart-086d0b12-89d4-4cf6-93b1-fbbbc49512c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082300396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2082300396
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2372554830
Short name T572
Test name
Test status
Simulation time 40268990 ps
CPU time 1.12 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 218972 kb
Host smart-44716aaa-465e-4798-b17f-9cb833d38828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372554830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2372554830
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1832079634
Short name T585
Test name
Test status
Simulation time 29787357 ps
CPU time 0.87 seconds
Started Mar 21 02:01:38 PM PDT 24
Finished Mar 21 02:01:39 PM PDT 24
Peak memory 218080 kb
Host smart-12cf6cdb-8c97-4a77-a4db-8aa0cfbee0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832079634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1832079634
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.892469724
Short name T622
Test name
Test status
Simulation time 82867918 ps
CPU time 1.3 seconds
Started Mar 21 02:01:39 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 219424 kb
Host smart-960fa8d7-94df-42a9-ae93-aeaca23c123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892469724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.892469724
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.147402181
Short name T77
Test name
Test status
Simulation time 41516981 ps
CPU time 0.93 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 218100 kb
Host smart-e7ef7c11-31e7-4a8c-b30f-bb56eef80c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147402181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.147402181
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.468120408
Short name T27
Test name
Test status
Simulation time 47957346 ps
CPU time 1.55 seconds
Started Mar 21 02:01:41 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 217732 kb
Host smart-2c9fc9d7-67dd-4ac2-855e-6cdcc2525fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468120408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.468120408
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3186858918
Short name T334
Test name
Test status
Simulation time 30697830 ps
CPU time 0.93 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 217844 kb
Host smart-e549710b-a030-43d7-b1e3-8e416cd117cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186858918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3186858918
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4046590525
Short name T723
Test name
Test status
Simulation time 58752029 ps
CPU time 2.1 seconds
Started Mar 21 02:01:43 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 219596 kb
Host smart-8677c255-7d43-4de2-90e7-fffd23ac7ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046590525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4046590525
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.425739167
Short name T342
Test name
Test status
Simulation time 22678449 ps
CPU time 1.01 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 231388 kb
Host smart-5631b8cd-55f6-44df-bfae-3a1f424c189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425739167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.425739167
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2458868128
Short name T282
Test name
Test status
Simulation time 31173458 ps
CPU time 1.37 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 216936 kb
Host smart-9b8f4d2a-6837-41b7-ac63-11e2a1668662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458868128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2458868128
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.882580123
Short name T735
Test name
Test status
Simulation time 31260296 ps
CPU time 0.88 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 218440 kb
Host smart-3ae7d3f4-49c6-4f0a-b92b-1a5869c50944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882580123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.882580123
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2384297982
Short name T683
Test name
Test status
Simulation time 118681484 ps
CPU time 1.83 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:44 PM PDT 24
Peak memory 218236 kb
Host smart-ca10a1fb-59f5-4697-809a-c37f0bb8916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384297982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2384297982
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3332411932
Short name T427
Test name
Test status
Simulation time 35255313 ps
CPU time 1.55 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 232380 kb
Host smart-01f8cc5a-514b-486d-9606-10c01cbdf1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332411932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3332411932
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2740730065
Short name T766
Test name
Test status
Simulation time 41729790 ps
CPU time 1.19 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:41 PM PDT 24
Peak memory 216896 kb
Host smart-dcd5cfc3-fde8-43fd-8634-f232e611a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740730065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2740730065
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3762315817
Short name T508
Test name
Test status
Simulation time 22790228 ps
CPU time 0.98 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 217764 kb
Host smart-54b1db78-67c9-4173-a808-80e19d3f89ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762315817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3762315817
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2291962607
Short name T564
Test name
Test status
Simulation time 70318761 ps
CPU time 1.13 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 216900 kb
Host smart-e633f51a-db50-4ddd-b6dd-225bf07fe0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291962607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2291962607
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3787788201
Short name T529
Test name
Test status
Simulation time 30820845 ps
CPU time 1.14 seconds
Started Mar 21 01:59:46 PM PDT 24
Finished Mar 21 01:59:48 PM PDT 24
Peak memory 215852 kb
Host smart-564f4eef-3a7d-4f07-b603-37cf0aff7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787788201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3787788201
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.291350656
Short name T381
Test name
Test status
Simulation time 38617385 ps
CPU time 0.97 seconds
Started Mar 21 01:59:51 PM PDT 24
Finished Mar 21 01:59:53 PM PDT 24
Peak memory 206232 kb
Host smart-9a439e36-6ed0-403a-8723-ad866c592ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291350656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.291350656
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2898904510
Short name T382
Test name
Test status
Simulation time 11852952 ps
CPU time 0.86 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:50 PM PDT 24
Peak memory 215988 kb
Host smart-1d49db8d-b990-4b1c-844d-312728f5ea57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898904510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2898904510
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.1059203189
Short name T753
Test name
Test status
Simulation time 27323029 ps
CPU time 0.83 seconds
Started Mar 21 01:59:52 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 217640 kb
Host smart-7f160a8d-9d68-4ec7-90f8-88c57867463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059203189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1059203189
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.770016151
Short name T269
Test name
Test status
Simulation time 25787661 ps
CPU time 1.2 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 217880 kb
Host smart-b87ccdad-08de-4130-be32-9dbad4dae012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770016151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.770016151
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.874666160
Short name T821
Test name
Test status
Simulation time 23961869 ps
CPU time 1.02 seconds
Started Mar 21 01:59:52 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 224396 kb
Host smart-cc887daf-f85f-4b27-a5fe-4ee1e576f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874666160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.874666160
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3913311606
Short name T650
Test name
Test status
Simulation time 39571966 ps
CPU time 0.93 seconds
Started Mar 21 01:59:52 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 207212 kb
Host smart-b86974c8-29e9-46d6-84d0-536c087e6361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913311606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3913311606
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3963193345
Short name T400
Test name
Test status
Simulation time 51592967 ps
CPU time 0.92 seconds
Started Mar 21 01:59:46 PM PDT 24
Finished Mar 21 01:59:48 PM PDT 24
Peak memory 215452 kb
Host smart-2000b6c4-91f2-449b-8317-39dee8ac867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963193345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3963193345
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.402103728
Short name T497
Test name
Test status
Simulation time 641824690 ps
CPU time 4.06 seconds
Started Mar 21 01:59:47 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 216624 kb
Host smart-e07a20a1-c2da-40a1-9346-020e37f52bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402103728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.402103728
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.91716043
Short name T668
Test name
Test status
Simulation time 351550876969 ps
CPU time 2121.96 seconds
Started Mar 21 02:00:22 PM PDT 24
Finished Mar 21 02:35:44 PM PDT 24
Peak memory 228596 kb
Host smart-aa8a01ba-f325-40ab-b518-1cc4c0d3cdde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91716043 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.91716043
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.514912802
Short name T68
Test name
Test status
Simulation time 30924788 ps
CPU time 0.93 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 216828 kb
Host smart-4f055058-2ae8-451e-8353-085a3b779254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514912802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.514912802
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2739862246
Short name T365
Test name
Test status
Simulation time 357154671 ps
CPU time 2.99 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:47 PM PDT 24
Peak memory 219808 kb
Host smart-3350594b-0f58-4e33-beab-32803f9f6d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739862246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2739862246
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3650671227
Short name T555
Test name
Test status
Simulation time 23514994 ps
CPU time 0.92 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 217920 kb
Host smart-6182e76b-6b3d-4e9c-9140-9a43bdac2f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650671227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3650671227
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.958169782
Short name T695
Test name
Test status
Simulation time 56948733 ps
CPU time 1.14 seconds
Started Mar 21 02:01:49 PM PDT 24
Finished Mar 21 02:01:50 PM PDT 24
Peak memory 224368 kb
Host smart-eb2312bb-2ca4-4099-821e-d34bd4495d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958169782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.958169782
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.533584882
Short name T482
Test name
Test status
Simulation time 62081790 ps
CPU time 1.27 seconds
Started Mar 21 02:01:49 PM PDT 24
Finished Mar 21 02:01:50 PM PDT 24
Peak memory 217764 kb
Host smart-ed65e501-126b-424c-b918-6bee6e9564c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533584882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.533584882
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3422706612
Short name T113
Test name
Test status
Simulation time 87211181 ps
CPU time 0.8 seconds
Started Mar 21 02:01:49 PM PDT 24
Finished Mar 21 02:01:50 PM PDT 24
Peak memory 217852 kb
Host smart-59943325-0965-4667-a906-8c9217583af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422706612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3422706612
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1765683418
Short name T473
Test name
Test status
Simulation time 32957553 ps
CPU time 1.32 seconds
Started Mar 21 02:01:40 PM PDT 24
Finished Mar 21 02:01:42 PM PDT 24
Peak memory 216768 kb
Host smart-e6e1a14d-23b4-449c-a756-72c682791b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765683418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1765683418
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1229379189
Short name T151
Test name
Test status
Simulation time 27580425 ps
CPU time 0.85 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 218052 kb
Host smart-f7f36323-7e6e-4a86-b28e-7989df6225a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229379189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1229379189
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.951501647
Short name T617
Test name
Test status
Simulation time 61299224 ps
CPU time 1.48 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 217136 kb
Host smart-b1cbe405-a934-4078-a6ca-dd887df1cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951501647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.951501647
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2972403546
Short name T595
Test name
Test status
Simulation time 31974983 ps
CPU time 0.92 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 217824 kb
Host smart-84340ea3-e263-4a34-93ee-a2e49a69356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972403546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2972403546
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.697348918
Short name T586
Test name
Test status
Simulation time 67155307 ps
CPU time 1.38 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 218056 kb
Host smart-3824ac0e-bbac-4ef7-8909-7763ad032f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697348918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.697348918
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3407605053
Short name T86
Test name
Test status
Simulation time 27156422 ps
CPU time 0.88 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 218056 kb
Host smart-9c2b1940-f7eb-4a0b-a302-b57b796629c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407605053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3407605053
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1117345670
Short name T824
Test name
Test status
Simulation time 39785147 ps
CPU time 1.05 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 216664 kb
Host smart-5464d9d1-54a3-49dc-9157-960ba758c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117345670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1117345670
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2494301579
Short name T85
Test name
Test status
Simulation time 31907435 ps
CPU time 1.32 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 219128 kb
Host smart-90fa293d-409e-4d24-ae20-83bccd5d4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494301579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2494301579
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3495266425
Short name T598
Test name
Test status
Simulation time 40435835 ps
CPU time 1.56 seconds
Started Mar 21 02:01:49 PM PDT 24
Finished Mar 21 02:01:51 PM PDT 24
Peak memory 218520 kb
Host smart-a2ca5792-bdd3-49a6-b71c-961cc1d6aa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495266425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3495266425
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1255536715
Short name T384
Test name
Test status
Simulation time 31528559 ps
CPU time 0.86 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:52 PM PDT 24
Peak memory 217660 kb
Host smart-7cb0999e-be84-4e3d-8a0d-85c63fb76095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255536715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1255536715
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.679517484
Short name T486
Test name
Test status
Simulation time 59186992 ps
CPU time 1.35 seconds
Started Mar 21 02:01:42 PM PDT 24
Finished Mar 21 02:01:43 PM PDT 24
Peak memory 216640 kb
Host smart-8a74a1d6-777c-476e-9670-3b48bc671027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679517484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.679517484
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3161332617
Short name T87
Test name
Test status
Simulation time 22926371 ps
CPU time 0.96 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 215548 kb
Host smart-95ff48d5-cd1b-4877-aa39-3da8d81305ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161332617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3161332617
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.430224276
Short name T277
Test name
Test status
Simulation time 40481931 ps
CPU time 1.44 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 217968 kb
Host smart-eb5c98c2-8101-44a7-85ce-abd08f9a5ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430224276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.430224276
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.796567757
Short name T826
Test name
Test status
Simulation time 13157264 ps
CPU time 0.86 seconds
Started Mar 21 02:00:01 PM PDT 24
Finished Mar 21 02:00:03 PM PDT 24
Peak memory 206028 kb
Host smart-8db7bf0e-7375-4d99-9cda-218bca104ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796567757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.796567757
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3520586271
Short name T89
Test name
Test status
Simulation time 35561972 ps
CPU time 0.87 seconds
Started Mar 21 02:00:04 PM PDT 24
Finished Mar 21 02:00:05 PM PDT 24
Peak memory 215584 kb
Host smart-cf454aba-754a-4d0c-bc10-996dd1a483a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520586271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3520586271
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2211394581
Short name T536
Test name
Test status
Simulation time 36334582 ps
CPU time 1.05 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:04 PM PDT 24
Peak memory 217696 kb
Host smart-3655f783-c047-46ba-aede-12f398b6dbc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211394581 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2211394581
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3378633953
Short name T63
Test name
Test status
Simulation time 21024162 ps
CPU time 1.18 seconds
Started Mar 21 02:00:02 PM PDT 24
Finished Mar 21 02:00:03 PM PDT 24
Peak memory 219484 kb
Host smart-8f7680e3-8911-4fd1-81f3-e528938dd9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378633953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3378633953
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3670534032
Short name T432
Test name
Test status
Simulation time 84799260 ps
CPU time 1.11 seconds
Started Mar 21 01:59:48 PM PDT 24
Finished Mar 21 01:59:50 PM PDT 24
Peak memory 216880 kb
Host smart-604907a2-8d8a-47ad-ae0a-531418de41eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670534032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3670534032
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3245486672
Short name T303
Test name
Test status
Simulation time 39902782 ps
CPU time 0.89 seconds
Started Mar 21 01:59:49 PM PDT 24
Finished Mar 21 01:59:51 PM PDT 24
Peak memory 215556 kb
Host smart-f90503ea-a5f8-4958-a594-b23bde1a0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245486672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3245486672
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2779110639
Short name T120
Test name
Test status
Simulation time 27382416 ps
CPU time 0.97 seconds
Started Mar 21 01:59:52 PM PDT 24
Finished Mar 21 01:59:54 PM PDT 24
Peak memory 207220 kb
Host smart-44043e1b-5434-44c9-88ee-be253172eccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779110639 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2779110639
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1722459615
Short name T710
Test name
Test status
Simulation time 26015754 ps
CPU time 0.9 seconds
Started Mar 21 01:59:49 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 215432 kb
Host smart-46f61ed9-687b-49c5-ae90-82df9c666b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722459615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1722459615
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.935875293
Short name T789
Test name
Test status
Simulation time 301146002 ps
CPU time 3.37 seconds
Started Mar 21 01:59:47 PM PDT 24
Finished Mar 21 01:59:52 PM PDT 24
Peak memory 216700 kb
Host smart-b474fd14-6e0f-4258-9e4e-8cc023254e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935875293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.935875293
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2950075239
Short name T190
Test name
Test status
Simulation time 61525948771 ps
CPU time 1299.03 seconds
Started Mar 21 01:59:50 PM PDT 24
Finished Mar 21 02:21:31 PM PDT 24
Peak memory 221340 kb
Host smart-b322e8b5-7b30-43cc-9d33-83bca1865c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950075239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2950075239
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.538377042
Short name T112
Test name
Test status
Simulation time 34694763 ps
CPU time 1.04 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:47 PM PDT 24
Peak memory 231232 kb
Host smart-71b3c048-ad22-4d3c-a751-1aee1eec5472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538377042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.538377042
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2824223857
Short name T624
Test name
Test status
Simulation time 46301455 ps
CPU time 1.71 seconds
Started Mar 21 02:01:47 PM PDT 24
Finished Mar 21 02:01:48 PM PDT 24
Peak memory 217920 kb
Host smart-25c6c8c8-67c4-4c06-ae04-f25b8395acf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824223857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2824223857
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2439589033
Short name T415
Test name
Test status
Simulation time 43737228 ps
CPU time 0.87 seconds
Started Mar 21 02:01:46 PM PDT 24
Finished Mar 21 02:01:48 PM PDT 24
Peak memory 218508 kb
Host smart-96fdb356-7b3a-462e-9a20-80266842cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439589033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2439589033
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.405517717
Short name T780
Test name
Test status
Simulation time 42189685 ps
CPU time 1.44 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216704 kb
Host smart-791e124e-fe14-48f9-900c-094024ef748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405517717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.405517717
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1063132120
Short name T375
Test name
Test status
Simulation time 23729018 ps
CPU time 0.95 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 218340 kb
Host smart-d050d325-ccef-44d9-8c4f-a8dc4880d121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063132120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1063132120
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3242021012
Short name T449
Test name
Test status
Simulation time 39041110 ps
CPU time 1.54 seconds
Started Mar 21 02:01:51 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 218088 kb
Host smart-4d33b5dd-2374-413a-999d-0f0ea3b0d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242021012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3242021012
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.909119140
Short name T309
Test name
Test status
Simulation time 19262216 ps
CPU time 1.06 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 218408 kb
Host smart-ed045a3b-5d46-4575-b4dc-485b974498e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909119140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.909119140
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4171710202
Short name T401
Test name
Test status
Simulation time 37825669 ps
CPU time 1.16 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 216704 kb
Host smart-533deb1d-aee2-436e-b923-2bcfc1829347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171710202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4171710202
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2512100152
Short name T325
Test name
Test status
Simulation time 24562315 ps
CPU time 0.98 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 219620 kb
Host smart-2bf8feaa-3ab8-4dad-bbd5-a0677746fc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512100152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2512100152
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3992919238
Short name T298
Test name
Test status
Simulation time 34967185 ps
CPU time 1.42 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 219592 kb
Host smart-8a497fad-cd5b-41b6-84c4-f678ebaf08b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992919238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3992919238
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3610971131
Short name T69
Test name
Test status
Simulation time 47711435 ps
CPU time 0.93 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 219452 kb
Host smart-459fafac-0a1f-4698-9e52-a5e8b9e1181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610971131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3610971131
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.879804868
Short name T236
Test name
Test status
Simulation time 57683016 ps
CPU time 1.18 seconds
Started Mar 21 02:01:44 PM PDT 24
Finished Mar 21 02:01:45 PM PDT 24
Peak memory 216896 kb
Host smart-9053656d-3e23-40ae-a136-d22f96f7b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879804868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.879804868
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.971551038
Short name T80
Test name
Test status
Simulation time 23568297 ps
CPU time 1.26 seconds
Started Mar 21 02:01:56 PM PDT 24
Finished Mar 21 02:01:57 PM PDT 24
Peak memory 229740 kb
Host smart-700c93bb-bcf7-49a6-b146-58b828165f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971551038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.971551038
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3183077188
Short name T755
Test name
Test status
Simulation time 48740830 ps
CPU time 1.44 seconds
Started Mar 21 02:01:45 PM PDT 24
Finished Mar 21 02:01:46 PM PDT 24
Peak memory 217960 kb
Host smart-54f897ed-7de9-4e79-b44d-8e891331a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183077188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3183077188
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.913727525
Short name T392
Test name
Test status
Simulation time 26022146 ps
CPU time 0.88 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 218136 kb
Host smart-1e8d3605-08dd-436a-8c25-0d8ca83a3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913727525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.913727525
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3463416471
Short name T541
Test name
Test status
Simulation time 260948269 ps
CPU time 1.73 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:54 PM PDT 24
Peak memory 218104 kb
Host smart-bcc95de4-916a-4976-8b02-388ea2291eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463416471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3463416471
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.189884601
Short name T96
Test name
Test status
Simulation time 76623380 ps
CPU time 1.06 seconds
Started Mar 21 02:01:58 PM PDT 24
Finished Mar 21 02:01:59 PM PDT 24
Peak memory 219368 kb
Host smart-4cf54235-9f2d-4fd5-a04e-23da59bcec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189884601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.189884601
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3799028430
Short name T360
Test name
Test status
Simulation time 39340814 ps
CPU time 1.39 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 216628 kb
Host smart-2d15933e-8ca9-47c6-b5d2-d50d7bd2aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799028430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3799028430
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.754924287
Short name T660
Test name
Test status
Simulation time 44094158 ps
CPU time 1.13 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 215600 kb
Host smart-541a772e-4902-4815-b98b-3865e56d14b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754924287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.754924287
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4136360354
Short name T183
Test name
Test status
Simulation time 68331244 ps
CPU time 1.52 seconds
Started Mar 21 02:01:52 PM PDT 24
Finished Mar 21 02:01:53 PM PDT 24
Peak memory 218336 kb
Host smart-c5ddb2f4-0c00-4c07-9882-2bc7ce30da76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136360354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4136360354
Directory /workspace/99.edn_genbits/latest
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