Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.02 98.27 93.63 96.79 82.66 96.87 96.58 93.35


Total test records in report: 966
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T792 /workspace/coverage/default/126.edn_genbits.3383107401 Mar 24 01:07:35 PM PDT 24 Mar 24 01:07:38 PM PDT 24 77119913 ps
T793 /workspace/coverage/default/38.edn_smoke.1673666565 Mar 24 01:06:38 PM PDT 24 Mar 24 01:06:46 PM PDT 24 17022072 ps
T794 /workspace/coverage/default/170.edn_genbits.3341450412 Mar 24 01:07:36 PM PDT 24 Mar 24 01:07:38 PM PDT 24 51165845 ps
T795 /workspace/coverage/default/53.edn_genbits.2267948340 Mar 24 01:06:58 PM PDT 24 Mar 24 01:07:01 PM PDT 24 96539688 ps
T796 /workspace/coverage/default/9.edn_intr.3020574799 Mar 24 01:05:45 PM PDT 24 Mar 24 01:05:46 PM PDT 24 27997892 ps
T797 /workspace/coverage/default/14.edn_err.756511577 Mar 24 01:05:57 PM PDT 24 Mar 24 01:05:58 PM PDT 24 19524156 ps
T798 /workspace/coverage/default/4.edn_regwen.1494058641 Mar 24 01:05:29 PM PDT 24 Mar 24 01:05:31 PM PDT 24 19343284 ps
T799 /workspace/coverage/default/250.edn_genbits.1166106454 Mar 24 01:07:43 PM PDT 24 Mar 24 01:07:44 PM PDT 24 74303270 ps
T800 /workspace/coverage/default/54.edn_err.1793694026 Mar 24 01:07:00 PM PDT 24 Mar 24 01:07:03 PM PDT 24 208306066 ps
T801 /workspace/coverage/default/16.edn_smoke.1181439107 Mar 24 01:05:54 PM PDT 24 Mar 24 01:05:57 PM PDT 24 176392416 ps
T802 /workspace/coverage/default/47.edn_disable.1880102149 Mar 24 01:06:54 PM PDT 24 Mar 24 01:06:57 PM PDT 24 36852243 ps
T803 /workspace/coverage/default/34.edn_alert_test.2363878603 Mar 24 01:06:33 PM PDT 24 Mar 24 01:06:34 PM PDT 24 14384768 ps
T804 /workspace/coverage/default/16.edn_intr.2901847730 Mar 24 01:05:54 PM PDT 24 Mar 24 01:05:57 PM PDT 24 24393091 ps
T805 /workspace/coverage/default/18.edn_stress_all.2112313461 Mar 24 01:06:03 PM PDT 24 Mar 24 01:06:08 PM PDT 24 788410054 ps
T806 /workspace/coverage/default/14.edn_genbits.1167084736 Mar 24 01:05:49 PM PDT 24 Mar 24 01:05:51 PM PDT 24 45289234 ps
T807 /workspace/coverage/default/30.edn_genbits.2509924089 Mar 24 01:06:25 PM PDT 24 Mar 24 01:06:28 PM PDT 24 68863455 ps
T808 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.618045047 Mar 24 01:06:40 PM PDT 24 Mar 24 01:16:39 PM PDT 24 22521827522 ps
T809 /workspace/coverage/default/25.edn_stress_all.2585658800 Mar 24 01:06:12 PM PDT 24 Mar 24 01:06:21 PM PDT 24 366471112 ps
T810 /workspace/coverage/default/31.edn_stress_all.3490365476 Mar 24 01:06:22 PM PDT 24 Mar 24 01:06:28 PM PDT 24 432130269 ps
T811 /workspace/coverage/default/191.edn_genbits.1375925040 Mar 24 01:07:35 PM PDT 24 Mar 24 01:07:37 PM PDT 24 37940516 ps
T812 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1572469408 Mar 24 01:06:01 PM PDT 24 Mar 24 01:18:08 PM PDT 24 32229757215 ps
T813 /workspace/coverage/default/63.edn_genbits.3601603171 Mar 24 01:07:07 PM PDT 24 Mar 24 01:07:09 PM PDT 24 52792657 ps
T814 /workspace/coverage/default/58.edn_err.1081951422 Mar 24 01:07:00 PM PDT 24 Mar 24 01:07:03 PM PDT 24 22453277 ps
T815 /workspace/coverage/default/48.edn_disable.3850569564 Mar 24 01:07:02 PM PDT 24 Mar 24 01:07:05 PM PDT 24 28993570 ps
T816 /workspace/coverage/default/84.edn_err.1618976261 Mar 24 01:07:10 PM PDT 24 Mar 24 01:07:11 PM PDT 24 82491317 ps
T290 /workspace/coverage/default/142.edn_genbits.3271683799 Mar 24 01:07:35 PM PDT 24 Mar 24 01:07:37 PM PDT 24 78613287 ps
T817 /workspace/coverage/default/45.edn_err.4043480447 Mar 24 01:06:58 PM PDT 24 Mar 24 01:07:01 PM PDT 24 33356105 ps
T180 /workspace/coverage/default/32.edn_alert.2991624333 Mar 24 01:06:31 PM PDT 24 Mar 24 01:06:33 PM PDT 24 44549309 ps
T818 /workspace/coverage/default/74.edn_genbits.2333061042 Mar 24 01:07:04 PM PDT 24 Mar 24 01:07:05 PM PDT 24 37214943 ps
T819 /workspace/coverage/default/246.edn_genbits.2631109395 Mar 24 01:07:47 PM PDT 24 Mar 24 01:07:48 PM PDT 24 44794485 ps
T820 /workspace/coverage/default/121.edn_genbits.1435586627 Mar 24 01:07:26 PM PDT 24 Mar 24 01:07:28 PM PDT 24 141302001 ps
T99 /workspace/coverage/default/82.edn_err.2080813301 Mar 24 01:07:12 PM PDT 24 Mar 24 01:07:13 PM PDT 24 83377478 ps
T821 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.657649007 Mar 24 01:05:19 PM PDT 24 Mar 24 01:14:26 PM PDT 24 25178041257 ps
T822 /workspace/coverage/default/48.edn_err.3046759918 Mar 24 01:06:57 PM PDT 24 Mar 24 01:07:01 PM PDT 24 32744051 ps
T823 /workspace/coverage/default/178.edn_genbits.663862768 Mar 24 01:07:36 PM PDT 24 Mar 24 01:07:38 PM PDT 24 109689254 ps
T824 /workspace/coverage/default/160.edn_genbits.3874490416 Mar 24 01:07:34 PM PDT 24 Mar 24 01:07:35 PM PDT 24 98087888 ps
T825 /workspace/coverage/default/133.edn_genbits.1542738145 Mar 24 01:07:24 PM PDT 24 Mar 24 01:07:26 PM PDT 24 27873558 ps
T826 /workspace/coverage/default/39.edn_alert_test.3876398826 Mar 24 01:06:40 PM PDT 24 Mar 24 01:06:47 PM PDT 24 16860496 ps
T827 /workspace/coverage/default/35.edn_alert_test.3308191436 Mar 24 01:06:33 PM PDT 24 Mar 24 01:06:34 PM PDT 24 19973047 ps
T828 /workspace/coverage/default/78.edn_genbits.3852491680 Mar 24 01:07:09 PM PDT 24 Mar 24 01:07:11 PM PDT 24 63952526 ps
T829 /workspace/coverage/default/209.edn_genbits.674926922 Mar 24 01:07:36 PM PDT 24 Mar 24 01:07:38 PM PDT 24 95245567 ps
T830 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.480311927 Mar 24 01:06:37 PM PDT 24 Mar 24 01:28:22 PM PDT 24 60798922382 ps
T270 /workspace/coverage/default/6.edn_regwen.286942744 Mar 24 01:05:35 PM PDT 24 Mar 24 01:05:36 PM PDT 24 17859676 ps
T133 /workspace/coverage/default/15.edn_intr.225213434 Mar 24 01:05:55 PM PDT 24 Mar 24 01:05:57 PM PDT 24 58228120 ps
T831 /workspace/coverage/default/35.edn_genbits.1713385720 Mar 24 01:06:34 PM PDT 24 Mar 24 01:06:36 PM PDT 24 149152665 ps
T832 /workspace/coverage/default/0.edn_disable.675261357 Mar 24 01:05:17 PM PDT 24 Mar 24 01:05:19 PM PDT 24 10314167 ps
T833 /workspace/coverage/default/248.edn_genbits.104071109 Mar 24 01:07:46 PM PDT 24 Mar 24 01:07:47 PM PDT 24 92177545 ps
T834 /workspace/coverage/default/156.edn_genbits.1180709827 Mar 24 01:07:30 PM PDT 24 Mar 24 01:07:31 PM PDT 24 43965505 ps
T835 /workspace/coverage/default/39.edn_intr.646857954 Mar 24 01:06:38 PM PDT 24 Mar 24 01:06:47 PM PDT 24 22463629 ps
T836 /workspace/coverage/default/65.edn_genbits.478110642 Mar 24 01:07:05 PM PDT 24 Mar 24 01:07:06 PM PDT 24 53096930 ps
T837 /workspace/coverage/default/14.edn_alert.3685147092 Mar 24 01:05:53 PM PDT 24 Mar 24 01:05:58 PM PDT 24 34037538 ps
T838 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3015086693 Mar 24 12:35:21 PM PDT 24 Mar 24 12:35:22 PM PDT 24 14417795 ps
T246 /workspace/coverage/cover_reg_top/1.edn_csr_rw.198764038 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:29 PM PDT 24 16731574 ps
T241 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4010139436 Mar 24 12:35:22 PM PDT 24 Mar 24 12:35:24 PM PDT 24 28309125 ps
T839 /workspace/coverage/cover_reg_top/27.edn_intr_test.1717800293 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:02 PM PDT 24 30600016 ps
T247 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1624905196 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:23 PM PDT 24 795178929 ps
T840 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1236203365 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:36 PM PDT 24 98722973 ps
T841 /workspace/coverage/cover_reg_top/45.edn_intr_test.1677579795 Mar 24 12:35:46 PM PDT 24 Mar 24 12:35:47 PM PDT 24 13957117 ps
T842 /workspace/coverage/cover_reg_top/7.edn_intr_test.91599330 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:31 PM PDT 24 41410769 ps
T843 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1669365151 Mar 24 12:35:52 PM PDT 24 Mar 24 12:35:53 PM PDT 24 163588038 ps
T844 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3922867120 Mar 24 12:35:37 PM PDT 24 Mar 24 12:35:39 PM PDT 24 25675620 ps
T845 /workspace/coverage/cover_reg_top/48.edn_intr_test.4146136974 Mar 24 12:35:48 PM PDT 24 Mar 24 12:35:49 PM PDT 24 24959917 ps
T248 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2127207184 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:27 PM PDT 24 424884496 ps
T846 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3616507978 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:29 PM PDT 24 94737920 ps
T249 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1442221896 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 305373431 ps
T847 /workspace/coverage/cover_reg_top/10.edn_intr_test.4087391831 Mar 24 12:35:42 PM PDT 24 Mar 24 12:35:43 PM PDT 24 12879644 ps
T848 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2761229994 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:36 PM PDT 24 44942981 ps
T849 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.74060922 Mar 24 12:35:50 PM PDT 24 Mar 24 12:35:52 PM PDT 24 20307088 ps
T850 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2760677752 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:08 PM PDT 24 34032989 ps
T218 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3884960999 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:21 PM PDT 24 38973933 ps
T242 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.950405253 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 55626488 ps
T851 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3073897566 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:21 PM PDT 24 70216922 ps
T852 /workspace/coverage/cover_reg_top/29.edn_intr_test.419839982 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 55535393 ps
T243 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4158645783 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:37 PM PDT 24 76326943 ps
T250 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2446449108 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:35 PM PDT 24 251163401 ps
T244 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1232470582 Mar 24 12:35:22 PM PDT 24 Mar 24 12:35:24 PM PDT 24 55796360 ps
T219 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.627583620 Mar 24 12:35:26 PM PDT 24 Mar 24 12:35:28 PM PDT 24 31879593 ps
T853 /workspace/coverage/cover_reg_top/2.edn_intr_test.482059223 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:37 PM PDT 24 14097115 ps
T854 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2296353026 Mar 24 12:35:26 PM PDT 24 Mar 24 12:35:27 PM PDT 24 25455677 ps
T855 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1448811960 Mar 24 12:35:49 PM PDT 24 Mar 24 12:35:50 PM PDT 24 56813206 ps
T856 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2876698206 Mar 24 12:35:54 PM PDT 24 Mar 24 12:35:55 PM PDT 24 23568914 ps
T857 /workspace/coverage/cover_reg_top/8.edn_intr_test.2642886406 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:36 PM PDT 24 20775512 ps
T245 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2071839334 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:42 PM PDT 24 14425278 ps
T220 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3635315426 Mar 24 12:35:48 PM PDT 24 Mar 24 12:35:49 PM PDT 24 33692076 ps
T221 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.188896314 Mar 24 12:35:26 PM PDT 24 Mar 24 12:35:27 PM PDT 24 15778402 ps
T858 /workspace/coverage/cover_reg_top/32.edn_intr_test.44192329 Mar 24 12:35:53 PM PDT 24 Mar 24 12:35:54 PM PDT 24 24866979 ps
T859 /workspace/coverage/cover_reg_top/49.edn_intr_test.243329832 Mar 24 12:35:40 PM PDT 24 Mar 24 12:35:41 PM PDT 24 21334628 ps
T257 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1604256914 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:33 PM PDT 24 542398253 ps
T860 /workspace/coverage/cover_reg_top/23.edn_intr_test.3061564107 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:41 PM PDT 24 24724196 ps
T222 /workspace/coverage/cover_reg_top/7.edn_csr_rw.805465153 Mar 24 12:35:46 PM PDT 24 Mar 24 12:35:47 PM PDT 24 14814361 ps
T861 /workspace/coverage/cover_reg_top/34.edn_intr_test.2929268217 Mar 24 12:35:55 PM PDT 24 Mar 24 12:35:56 PM PDT 24 20019605 ps
T862 /workspace/coverage/cover_reg_top/44.edn_intr_test.3066983000 Mar 24 12:35:51 PM PDT 24 Mar 24 12:35:52 PM PDT 24 16298856 ps
T863 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1350937433 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:40 PM PDT 24 65279112 ps
T864 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2547231181 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:42 PM PDT 24 213974473 ps
T865 /workspace/coverage/cover_reg_top/5.edn_intr_test.1821858270 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 28899814 ps
T866 /workspace/coverage/cover_reg_top/6.edn_tl_errors.263910863 Mar 24 12:35:54 PM PDT 24 Mar 24 12:35:59 PM PDT 24 112291701 ps
T867 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1846274665 Mar 24 12:35:52 PM PDT 24 Mar 24 12:35:55 PM PDT 24 233869073 ps
T223 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1144040940 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:37 PM PDT 24 296059189 ps
T224 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3181467072 Mar 24 12:35:53 PM PDT 24 Mar 24 12:35:54 PM PDT 24 14830449 ps
T868 /workspace/coverage/cover_reg_top/21.edn_intr_test.2271270374 Mar 24 12:35:54 PM PDT 24 Mar 24 12:35:56 PM PDT 24 22493467 ps
T869 /workspace/coverage/cover_reg_top/42.edn_intr_test.975546081 Mar 24 12:35:49 PM PDT 24 Mar 24 12:35:50 PM PDT 24 26435881 ps
T870 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.785113872 Mar 24 12:35:31 PM PDT 24 Mar 24 12:35:34 PM PDT 24 190516302 ps
T871 /workspace/coverage/cover_reg_top/0.edn_intr_test.2790664123 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 15645023 ps
T872 /workspace/coverage/cover_reg_top/46.edn_intr_test.1047870217 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 66280080 ps
T873 /workspace/coverage/cover_reg_top/31.edn_intr_test.1625300790 Mar 24 12:35:52 PM PDT 24 Mar 24 12:35:53 PM PDT 24 40613994 ps
T874 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1270929243 Mar 24 12:35:44 PM PDT 24 Mar 24 12:35:45 PM PDT 24 139099889 ps
T875 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.413587325 Mar 24 12:36:00 PM PDT 24 Mar 24 12:36:02 PM PDT 24 54631277 ps
T258 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4037025280 Mar 24 12:35:49 PM PDT 24 Mar 24 12:35:50 PM PDT 24 50969782 ps
T876 /workspace/coverage/cover_reg_top/37.edn_intr_test.2843041021 Mar 24 12:35:43 PM PDT 24 Mar 24 12:35:44 PM PDT 24 13936012 ps
T877 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1813715718 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:35 PM PDT 24 41719235 ps
T878 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.587416028 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:31 PM PDT 24 80573061 ps
T879 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.229086720 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:35 PM PDT 24 37014568 ps
T880 /workspace/coverage/cover_reg_top/33.edn_intr_test.517841123 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:40 PM PDT 24 13946817 ps
T881 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2809603517 Mar 24 12:35:22 PM PDT 24 Mar 24 12:35:25 PM PDT 24 96323298 ps
T225 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.655266800 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:31 PM PDT 24 44475882 ps
T882 /workspace/coverage/cover_reg_top/26.edn_intr_test.1164742054 Mar 24 12:35:47 PM PDT 24 Mar 24 12:35:48 PM PDT 24 20037683 ps
T883 /workspace/coverage/cover_reg_top/43.edn_intr_test.3925648791 Mar 24 12:35:44 PM PDT 24 Mar 24 12:35:46 PM PDT 24 14336169 ps
T884 /workspace/coverage/cover_reg_top/25.edn_intr_test.2315638878 Mar 24 12:36:02 PM PDT 24 Mar 24 12:36:04 PM PDT 24 26794333 ps
T226 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.466532977 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:39 PM PDT 24 96397946 ps
T885 /workspace/coverage/cover_reg_top/30.edn_intr_test.2643665384 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 19276234 ps
T886 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1908726484 Mar 24 12:35:53 PM PDT 24 Mar 24 12:35:54 PM PDT 24 167934328 ps
T887 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3800720215 Mar 24 12:35:32 PM PDT 24 Mar 24 12:35:34 PM PDT 24 22757853 ps
T888 /workspace/coverage/cover_reg_top/14.edn_intr_test.3619927950 Mar 24 12:36:16 PM PDT 24 Mar 24 12:36:19 PM PDT 24 16602888 ps
T889 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.958572544 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 115848422 ps
T890 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1411103894 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:27 PM PDT 24 224315830 ps
T227 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2992851700 Mar 24 12:35:27 PM PDT 24 Mar 24 12:35:30 PM PDT 24 223504429 ps
T891 /workspace/coverage/cover_reg_top/41.edn_intr_test.777766692 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 24778053 ps
T892 /workspace/coverage/cover_reg_top/40.edn_intr_test.3658313745 Mar 24 12:35:46 PM PDT 24 Mar 24 12:35:47 PM PDT 24 15515174 ps
T893 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3461430918 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:39 PM PDT 24 13619215 ps
T894 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1377201495 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:24 PM PDT 24 16596797 ps
T895 /workspace/coverage/cover_reg_top/39.edn_intr_test.803791725 Mar 24 12:35:56 PM PDT 24 Mar 24 12:35:57 PM PDT 24 75988915 ps
T896 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2602539026 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:32 PM PDT 24 39417453 ps
T897 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2137225543 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:26 PM PDT 24 145967126 ps
T228 /workspace/coverage/cover_reg_top/5.edn_csr_rw.225276227 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:21 PM PDT 24 15567079 ps
T229 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.720296559 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 40086342 ps
T898 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3464431327 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:39 PM PDT 24 387320533 ps
T899 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2803831635 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:35 PM PDT 24 28125873 ps
T900 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3847034022 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:35 PM PDT 24 453255023 ps
T901 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2381594390 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:42 PM PDT 24 18230769 ps
T902 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3145405259 Mar 24 12:35:37 PM PDT 24 Mar 24 12:35:40 PM PDT 24 129934806 ps
T903 /workspace/coverage/cover_reg_top/16.edn_intr_test.94976508 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:36 PM PDT 24 11981163 ps
T904 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1848055126 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:03 PM PDT 24 22308329 ps
T905 /workspace/coverage/cover_reg_top/13.edn_intr_test.1207217866 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:25 PM PDT 24 23654071 ps
T230 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2224491686 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:19 PM PDT 24 39388978 ps
T906 /workspace/coverage/cover_reg_top/14.edn_tl_errors.789174615 Mar 24 12:35:31 PM PDT 24 Mar 24 12:35:33 PM PDT 24 39001333 ps
T907 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1621788271 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:32 PM PDT 24 124369852 ps
T908 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3180949266 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:36 PM PDT 24 171262339 ps
T909 /workspace/coverage/cover_reg_top/9.edn_intr_test.3784274620 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:32 PM PDT 24 55386960 ps
T910 /workspace/coverage/cover_reg_top/4.edn_intr_test.27317974 Mar 24 12:35:40 PM PDT 24 Mar 24 12:35:46 PM PDT 24 14362582 ps
T231 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3785716234 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:41 PM PDT 24 12568641 ps
T911 /workspace/coverage/cover_reg_top/22.edn_intr_test.2993386999 Mar 24 12:36:00 PM PDT 24 Mar 24 12:36:01 PM PDT 24 14959362 ps
T912 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4232085084 Mar 24 12:35:40 PM PDT 24 Mar 24 12:35:42 PM PDT 24 27033305 ps
T913 /workspace/coverage/cover_reg_top/47.edn_intr_test.1658415324 Mar 24 12:35:43 PM PDT 24 Mar 24 12:35:44 PM PDT 24 60473639 ps
T914 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1075145566 Mar 24 12:35:37 PM PDT 24 Mar 24 12:35:38 PM PDT 24 49431088 ps
T915 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2138301205 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:25 PM PDT 24 54329642 ps
T916 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3821549060 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:32 PM PDT 24 147175543 ps
T917 /workspace/coverage/cover_reg_top/19.edn_intr_test.2658857732 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:36 PM PDT 24 14558737 ps
T918 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2859128431 Mar 24 12:35:26 PM PDT 24 Mar 24 12:35:32 PM PDT 24 28753059 ps
T232 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2481103845 Mar 24 12:35:56 PM PDT 24 Mar 24 12:35:57 PM PDT 24 61895918 ps
T233 /workspace/coverage/cover_reg_top/12.edn_csr_rw.662507451 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:02 PM PDT 24 25846008 ps
T234 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1162318610 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:40 PM PDT 24 29045220 ps
T919 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3345545025 Mar 24 12:35:32 PM PDT 24 Mar 24 12:35:33 PM PDT 24 36947233 ps
T920 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2508754194 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:38 PM PDT 24 897240573 ps
T921 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.422806309 Mar 24 12:35:27 PM PDT 24 Mar 24 12:35:29 PM PDT 24 61579913 ps
T922 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3781752474 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:24 PM PDT 24 99974695 ps
T923 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.737407157 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:37 PM PDT 24 18797769 ps
T924 /workspace/coverage/cover_reg_top/35.edn_intr_test.3880517570 Mar 24 12:36:00 PM PDT 24 Mar 24 12:36:01 PM PDT 24 19422123 ps
T925 /workspace/coverage/cover_reg_top/12.edn_intr_test.3776055842 Mar 24 12:35:50 PM PDT 24 Mar 24 12:35:51 PM PDT 24 15234292 ps
T926 /workspace/coverage/cover_reg_top/6.edn_intr_test.260714780 Mar 24 12:35:31 PM PDT 24 Mar 24 12:35:32 PM PDT 24 20022309 ps
T927 /workspace/coverage/cover_reg_top/24.edn_intr_test.2359877525 Mar 24 12:35:45 PM PDT 24 Mar 24 12:35:46 PM PDT 24 15651631 ps
T928 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2650626368 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:31 PM PDT 24 71699301 ps
T929 /workspace/coverage/cover_reg_top/6.edn_csr_rw.4070385203 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:42 PM PDT 24 71037017 ps
T930 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2105232117 Mar 24 12:35:37 PM PDT 24 Mar 24 12:35:38 PM PDT 24 67568138 ps
T931 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1536628459 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:34 PM PDT 24 109398779 ps
T235 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2072268273 Mar 24 12:35:43 PM PDT 24 Mar 24 12:35:44 PM PDT 24 68714897 ps
T932 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1808396700 Mar 24 12:35:40 PM PDT 24 Mar 24 12:35:41 PM PDT 24 85024649 ps
T933 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2872110335 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:26 PM PDT 24 111139405 ps
T236 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1849864264 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:29 PM PDT 24 16075016 ps
T934 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2405064058 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:38 PM PDT 24 52635750 ps
T935 /workspace/coverage/cover_reg_top/17.edn_tl_errors.722191297 Mar 24 12:36:14 PM PDT 24 Mar 24 12:36:16 PM PDT 24 64586487 ps
T936 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2800973644 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:25 PM PDT 24 110430935 ps
T937 /workspace/coverage/cover_reg_top/15.edn_intr_test.3326680673 Mar 24 12:35:40 PM PDT 24 Mar 24 12:35:41 PM PDT 24 37305402 ps
T938 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.245037220 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:31 PM PDT 24 54442923 ps
T239 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3102727739 Mar 24 12:35:21 PM PDT 24 Mar 24 12:35:27 PM PDT 24 67764038 ps
T939 /workspace/coverage/cover_reg_top/17.edn_intr_test.1403557474 Mar 24 12:35:44 PM PDT 24 Mar 24 12:35:45 PM PDT 24 16832814 ps
T940 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2551816993 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:36 PM PDT 24 68965496 ps
T941 /workspace/coverage/cover_reg_top/36.edn_intr_test.2990697455 Mar 24 12:35:49 PM PDT 24 Mar 24 12:35:50 PM PDT 24 37182841 ps
T942 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3923549813 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:31 PM PDT 24 22737641 ps
T943 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.54986100 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:31 PM PDT 24 72254819 ps
T944 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.405434469 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:38 PM PDT 24 56489129 ps
T237 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2192038838 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:31 PM PDT 24 86115155 ps
T945 /workspace/coverage/cover_reg_top/20.edn_intr_test.1046507735 Mar 24 12:35:43 PM PDT 24 Mar 24 12:35:44 PM PDT 24 47775435 ps
T946 /workspace/coverage/cover_reg_top/11.edn_intr_test.3886311129 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:29 PM PDT 24 14717355 ps
T947 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2409260212 Mar 24 12:35:52 PM PDT 24 Mar 24 12:35:55 PM PDT 24 162814025 ps
T948 /workspace/coverage/cover_reg_top/3.edn_intr_test.2039979701 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:42 PM PDT 24 13213608 ps
T949 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3162546957 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:39 PM PDT 24 21983938 ps
T950 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4073289469 Mar 24 12:35:27 PM PDT 24 Mar 24 12:35:29 PM PDT 24 25032021 ps
T951 /workspace/coverage/cover_reg_top/1.edn_intr_test.2529263323 Mar 24 12:35:49 PM PDT 24 Mar 24 12:35:50 PM PDT 24 14026902 ps
T952 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.155839195 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:39 PM PDT 24 17622919 ps
T953 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2595327499 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:43 PM PDT 24 280759070 ps
T954 /workspace/coverage/cover_reg_top/1.edn_tl_errors.36662062 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:26 PM PDT 24 61046756 ps
T240 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2034122683 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:31 PM PDT 24 50447684 ps
T955 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3963777811 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:03 PM PDT 24 161041219 ps
T956 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.638707086 Mar 24 12:35:44 PM PDT 24 Mar 24 12:35:46 PM PDT 24 128687765 ps
T957 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1324961095 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:43 PM PDT 24 182079327 ps
T958 /workspace/coverage/cover_reg_top/28.edn_intr_test.3860200068 Mar 24 12:36:07 PM PDT 24 Mar 24 12:36:07 PM PDT 24 21118682 ps
T959 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2616448510 Mar 24 12:35:44 PM PDT 24 Mar 24 12:35:45 PM PDT 24 38420441 ps
T960 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2676003153 Mar 24 12:35:36 PM PDT 24 Mar 24 12:35:47 PM PDT 24 338139595 ps
T961 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1903936193 Mar 24 12:35:43 PM PDT 24 Mar 24 12:35:45 PM PDT 24 31557459 ps
T259 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2522448523 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 49242343 ps
T962 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1828668745 Mar 24 12:35:45 PM PDT 24 Mar 24 12:35:52 PM PDT 24 89016069 ps
T238 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.278041607 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:35 PM PDT 24 17223632 ps
T963 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3715615679 Mar 24 12:35:32 PM PDT 24 Mar 24 12:35:34 PM PDT 24 42799040 ps
T964 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3112739308 Mar 24 12:35:37 PM PDT 24 Mar 24 12:35:45 PM PDT 24 49530083 ps
T965 /workspace/coverage/cover_reg_top/18.edn_intr_test.3187379013 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:36 PM PDT 24 18648023 ps
T966 /workspace/coverage/cover_reg_top/38.edn_intr_test.3108800215 Mar 24 12:35:53 PM PDT 24 Mar 24 12:35:54 PM PDT 24 14284048 ps

Test location /workspace/coverage/default/180.edn_genbits.2225273009
Short name T3
Test name
Test status
Simulation time 91162976 ps
CPU time 1.29 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 217880 kb
Host smart-3a0926ba-d479-4c5a-bb71-3b9a942e5edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225273009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2225273009
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_alert.380119011
Short name T8
Test name
Test status
Simulation time 52625942 ps
CPU time 1.22 seconds
Started Mar 24 01:06:02 PM PDT 24
Finished Mar 24 01:06:03 PM PDT 24
Peak memory 215780 kb
Host smart-5ffcd550-03c1-400f-9ef1-c93dd74d685f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380119011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.380119011
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3267394787
Short name T21
Test name
Test status
Simulation time 166813116457 ps
CPU time 1380.41 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:28:57 PM PDT 24
Peak memory 225600 kb
Host smart-aad38709-e4c3-4726-a906-f43fb1a31fad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267394787 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3267394787
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_err.2708339996
Short name T13
Test name
Test status
Simulation time 75585994 ps
CPU time 1.2 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 224380 kb
Host smart-a127550e-0789-4b28-a596-5e1286b3e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708339996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2708339996
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1247614238
Short name T19
Test name
Test status
Simulation time 3661759181 ps
CPU time 6.84 seconds
Started Mar 24 01:05:21 PM PDT 24
Finished Mar 24 01:05:28 PM PDT 24
Peak memory 235504 kb
Host smart-16e43bd4-7976-41be-8d29-ea2d53ed0343
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247614238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1247614238
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/42.edn_stress_all.2294819191
Short name T40
Test name
Test status
Simulation time 278078709 ps
CPU time 5.42 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:51 PM PDT 24
Peak memory 219676 kb
Host smart-00323bde-14b9-49cf-b5dc-5724abcef96b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294819191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2294819191
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1701769958
Short name T63
Test name
Test status
Simulation time 47332070 ps
CPU time 1.43 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 216592 kb
Host smart-4065e50f-a44b-40af-a3fa-bed089a21a31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701769958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1701769958
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_alert.1979070136
Short name T53
Test name
Test status
Simulation time 27916385 ps
CPU time 1.18 seconds
Started Mar 24 01:06:42 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215712 kb
Host smart-2d846713-2c1c-47f0-bbe4-074a07a9f4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979070136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1979070136
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1424779071
Short name T33
Test name
Test status
Simulation time 98364104 ps
CPU time 1.26 seconds
Started Mar 24 01:07:26 PM PDT 24
Finished Mar 24 01:07:28 PM PDT 24
Peak memory 218204 kb
Host smart-eee82a0d-8b49-4b94-8bdc-6606e9dd47e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424779071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1424779071
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_err.2015212500
Short name T4
Test name
Test status
Simulation time 67372325 ps
CPU time 1.2 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 219136 kb
Host smart-7a107c08-9cf2-4ea2-b8ba-40b8971ddf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015212500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2015212500
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/1.edn_regwen.2391685518
Short name T136
Test name
Test status
Simulation time 42421756 ps
CPU time 0.88 seconds
Started Mar 24 01:05:22 PM PDT 24
Finished Mar 24 01:05:23 PM PDT 24
Peak memory 207224 kb
Host smart-0dbbdaea-5936-4b81-a7b3-393cee670c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391685518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2391685518
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_intr.3548033963
Short name T124
Test name
Test status
Simulation time 20645592 ps
CPU time 1.1 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 215732 kb
Host smart-75fe6201-95e1-4761-a9ca-2eff79d12cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548033963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3548033963
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1604256914
Short name T257
Test name
Test status
Simulation time 542398253 ps
CPU time 5.19 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 206328 kb
Host smart-6f3a4a7f-d986-4aff-8f72-5e469da65802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604256914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1604256914
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2776754026
Short name T22
Test name
Test status
Simulation time 83474067397 ps
CPU time 1014.47 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:23:18 PM PDT 24
Peak memory 220596 kb
Host smart-22f1a79a-c278-4721-9af8-99c4bf0b93c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776754026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2776754026
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2248720430
Short name T88
Test name
Test status
Simulation time 57046986 ps
CPU time 1.06 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 216508 kb
Host smart-323b2411-60f3-44a2-a2e8-f76b3173ac2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248720430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2248720430
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.3414097628
Short name T108
Test name
Test status
Simulation time 70894886 ps
CPU time 1.09 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 215876 kb
Host smart-6354e4cf-a81c-4627-88c2-9ad6b96a52cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414097628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3414097628
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/15.edn_genbits.2752744493
Short name T277
Test name
Test status
Simulation time 49890020 ps
CPU time 1.75 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 217952 kb
Host smart-dee0589d-2e2f-4b86-be89-fb744226e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752744493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2752744493
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_disable.1518109182
Short name T173
Test name
Test status
Simulation time 23577276 ps
CPU time 0.9 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 216164 kb
Host smart-5c7d3d12-b0d1-4601-b3e6-231698c89c5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518109182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1518109182
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.675261357
Short name T832
Test name
Test status
Simulation time 10314167 ps
CPU time 0.86 seconds
Started Mar 24 01:05:17 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 215964 kb
Host smart-6aa8229e-4ac4-4cef-ad8c-424ed8e8afe7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675261357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.675261357
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.2536968019
Short name T128
Test name
Test status
Simulation time 37451834 ps
CPU time 0.87 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 215692 kb
Host smart-9d9283e7-0141-4819-afbe-0b409ec40975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536968019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2536968019
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.720296559
Short name T229
Test name
Test status
Simulation time 40086342 ps
CPU time 1.55 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206196 kb
Host smart-f9144482-0db0-4c80-84a6-85afdc0f39fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720296559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.720296559
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/default/28.edn_alert.2611687657
Short name T15
Test name
Test status
Simulation time 50162579 ps
CPU time 1.07 seconds
Started Mar 24 01:06:21 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 215800 kb
Host smart-db09b178-f1cb-4d56-a3f8-4f975966baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611687657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2611687657
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.1999559812
Short name T105
Test name
Test status
Simulation time 14599909 ps
CPU time 0.96 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 216264 kb
Host smart-13906620-ba20-468c-99f9-832c2acff4ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999559812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1999559812
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3876260224
Short name T81
Test name
Test status
Simulation time 53134075 ps
CPU time 1.09 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 216688 kb
Host smart-96ce2edf-0bed-4ed7-8858-8fe453b5a620
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876260224 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3876260224
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/270.edn_genbits.1365391833
Short name T284
Test name
Test status
Simulation time 71371277 ps
CPU time 1.44 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 219676 kb
Host smart-8b08ba5e-4455-4e2b-8287-850a79cf522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365391833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1365391833
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_disable.607391571
Short name T95
Test name
Test status
Simulation time 56636397 ps
CPU time 0.92 seconds
Started Mar 24 01:05:30 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 215564 kb
Host smart-d88496d0-534b-4388-a52a-f6815a8bffed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607391571 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.607391571
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/27.edn_alert.334019126
Short name T264
Test name
Test status
Simulation time 32047856 ps
CPU time 1.29 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 216008 kb
Host smart-abc0fd25-7ed8-4ec9-ac14-86f9c465f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334019126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.334019126
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert.2313795495
Short name T268
Test name
Test status
Simulation time 63166021 ps
CPU time 1.22 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 215796 kb
Host smart-9da9e4ec-ee2f-4264-af5c-9d6c7b0f18cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313795495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2313795495
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3832438362
Short name T76
Test name
Test status
Simulation time 55482114 ps
CPU time 1.09 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:24 PM PDT 24
Peak memory 216592 kb
Host smart-f6e70937-373d-4608-9c05-eb666bbcd2e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832438362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3832438362
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.3826805614
Short name T115
Test name
Test status
Simulation time 13298668 ps
CPU time 0.9 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 216280 kb
Host smart-293a3ff2-e521-452a-96da-4f378b1b3d8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826805614 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3826805614
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.1100494942
Short name T110
Test name
Test status
Simulation time 11299008 ps
CPU time 0.87 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:52 PM PDT 24
Peak memory 216104 kb
Host smart-e61114d6-a031-4a74-bce1-024f492393bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100494942 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1100494942
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2777693352
Short name T174
Test name
Test status
Simulation time 75580932 ps
CPU time 1.13 seconds
Started Mar 24 01:06:01 PM PDT 24
Finished Mar 24 01:06:02 PM PDT 24
Peak memory 216556 kb
Host smart-31d45155-34f1-4e66-9f14-273f63bdf962
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777693352 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2777693352
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable.1366454889
Short name T112
Test name
Test status
Simulation time 112915718 ps
CPU time 0.86 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 215920 kb
Host smart-7e7a53f0-b783-4392-8b5a-331ea92b0717
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366454889 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1366454889
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.1978710580
Short name T159
Test name
Test status
Simulation time 30415958 ps
CPU time 0.84 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 215928 kb
Host smart-10d1eb49-0359-458c-8979-29f0b4dbb94e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978710580 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1978710580
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.3689059694
Short name T168
Test name
Test status
Simulation time 12360521 ps
CPU time 0.91 seconds
Started Mar 24 01:06:21 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 216148 kb
Host smart-515f63c2-d78e-4d2c-9d10-9a73744d87a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689059694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3689059694
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable.3378915598
Short name T119
Test name
Test status
Simulation time 30515317 ps
CPU time 0.83 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 215920 kb
Host smart-2dbba84b-a5a7-431d-9cdd-6cc518f02a04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378915598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3378915598
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable.3562474096
Short name T118
Test name
Test status
Simulation time 76101600 ps
CPU time 0.91 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 215908 kb
Host smart-43f58256-8801-4a7c-90ca-1095651e76b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562474096 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3562474096
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3635315426
Short name T220
Test name
Test status
Simulation time 33692076 ps
CPU time 1.1 seconds
Started Mar 24 12:35:48 PM PDT 24
Finished Mar 24 12:35:49 PM PDT 24
Peak memory 206368 kb
Host smart-663f6c45-45c1-4381-8541-6b3abd054fbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635315426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3635315426
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.edn_alert_test.3599132530
Short name T323
Test name
Test status
Simulation time 29736875 ps
CPU time 0.95 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 206148 kb
Host smart-16578023-a15a-484c-96db-79b7e481b9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599132530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3599132530
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/204.edn_genbits.2190737801
Short name T294
Test name
Test status
Simulation time 87293614 ps
CPU time 1.27 seconds
Started Mar 24 01:07:39 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218160 kb
Host smart-7b286ec3-474f-4a94-98d9-888a33de9d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190737801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2190737801
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.10730893
Short name T266
Test name
Test status
Simulation time 34612854 ps
CPU time 0.9 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:24 PM PDT 24
Peak memory 207220 kb
Host smart-611315bb-011a-4312-8a2a-b8e91a5bac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10730893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.10730893
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/274.edn_genbits.3681476127
Short name T29
Test name
Test status
Simulation time 52374880 ps
CPU time 1.16 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 216560 kb
Host smart-599d9450-1866-44c3-ac4b-bf2e15a19677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681476127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3681476127
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2147129097
Short name T9
Test name
Test status
Simulation time 33085098 ps
CPU time 1.4 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 219224 kb
Host smart-1756cab9-2e4f-472c-9b25-5f26ca113889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147129097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2147129097
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2087987969
Short name T291
Test name
Test status
Simulation time 76732989 ps
CPU time 1.1 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 219280 kb
Host smart-9a20e213-b054-431f-9cc5-2aca566e5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087987969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2087987969
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2103344398
Short name T280
Test name
Test status
Simulation time 42980692 ps
CPU time 1.18 seconds
Started Mar 24 01:07:48 PM PDT 24
Finished Mar 24 01:07:49 PM PDT 24
Peak memory 218176 kb
Host smart-52fdd1e2-2658-40b2-8132-8c2ffde969c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103344398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2103344398
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.286942744
Short name T270
Test name
Test status
Simulation time 17859676 ps
CPU time 0.99 seconds
Started Mar 24 01:05:35 PM PDT 24
Finished Mar 24 01:05:36 PM PDT 24
Peak memory 207220 kb
Host smart-81d7b9be-62cc-45b8-a655-cb14b6a4f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286942744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.286942744
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/23.edn_intr.1531490562
Short name T130
Test name
Test status
Simulation time 20946231 ps
CPU time 1.09 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:09 PM PDT 24
Peak memory 215952 kb
Host smart-7a29ef63-bd9d-4043-9016-2c31d73eeb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531490562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1531490562
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3547559962
Short name T17
Test name
Test status
Simulation time 697791059 ps
CPU time 3.79 seconds
Started Mar 24 01:05:27 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 234484 kb
Host smart-b4366b78-ebdb-40b5-afc5-2de21288bc9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547559962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3547559962
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/108.edn_genbits.1827063630
Short name T343
Test name
Test status
Simulation time 63603456 ps
CPU time 1.31 seconds
Started Mar 24 01:07:25 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 218468 kb
Host smart-7b5bc273-f6bd-48f1-b90b-1918809ca630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827063630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1827063630
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1652106873
Short name T288
Test name
Test status
Simulation time 91473240 ps
CPU time 1.18 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 219004 kb
Host smart-1288bfb0-3e61-461e-878f-cae06deacb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652106873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1652106873
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.2299574175
Short name T452
Test name
Test status
Simulation time 76268704 ps
CPU time 1.12 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 216812 kb
Host smart-2ad57e5f-d87d-4cc3-9302-59913e64362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299574175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2299574175
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3271683799
Short name T290
Test name
Test status
Simulation time 78613287 ps
CPU time 1.76 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 218192 kb
Host smart-91adc219-9294-4284-bf3e-89344b4ab4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271683799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3271683799
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2303555580
Short name T253
Test name
Test status
Simulation time 41933252 ps
CPU time 1.1 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 216632 kb
Host smart-8b985fe1-4e8c-4685-90f8-b076fe340271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303555580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2303555580
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.741673539
Short name T1
Test name
Test status
Simulation time 63530844 ps
CPU time 1.08 seconds
Started Mar 24 01:07:33 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 216816 kb
Host smart-c8383527-8f40-429f-89a3-1ca045c34c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741673539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.741673539
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/200.edn_genbits.3061541953
Short name T287
Test name
Test status
Simulation time 55925605 ps
CPU time 1.48 seconds
Started Mar 24 01:07:34 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 218064 kb
Host smart-71470759-20ff-4f89-9afd-3887b988ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061541953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3061541953
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.667677014
Short name T267
Test name
Test status
Simulation time 46958551 ps
CPU time 1.22 seconds
Started Mar 24 01:06:04 PM PDT 24
Finished Mar 24 01:06:05 PM PDT 24
Peak memory 215804 kb
Host smart-487bec4f-5cb9-424b-97fd-4a1b4eeda720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667677014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.667677014
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/220.edn_genbits.1360711446
Short name T273
Test name
Test status
Simulation time 55952608 ps
CPU time 0.93 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 216552 kb
Host smart-befd2166-0e2b-4cdc-84b6-a342299f1571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360711446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1360711446
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1127125132
Short name T274
Test name
Test status
Simulation time 35733200 ps
CPU time 1.47 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 218076 kb
Host smart-6ec1649e-cb87-4b64-a989-6b066e158a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127125132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1127125132
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_alert.3678985728
Short name T102
Test name
Test status
Simulation time 38680903 ps
CPU time 1.25 seconds
Started Mar 24 01:06:30 PM PDT 24
Finished Mar 24 01:06:31 PM PDT 24
Peak memory 215776 kb
Host smart-e02ea930-03e6-4543-a888-b71c752bdc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678985728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3678985728
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert.2328434714
Short name T251
Test name
Test status
Simulation time 54699194 ps
CPU time 1.17 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215756 kb
Host smart-6849914f-8c80-4c0f-a71e-b6fb9899b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328434714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2328434714
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/22.edn_intr.3094738374
Short name T134
Test name
Test status
Simulation time 20507151 ps
CPU time 1.07 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 216088 kb
Host smart-5f5573c0-34f8-4b9b-955c-1be46da840d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094738374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3094738374
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/12.edn_alert.2692992432
Short name T181
Test name
Test status
Simulation time 86990154 ps
CPU time 1.2 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 215780 kb
Host smart-a5cd4f9c-144d-4cb5-aad9-1c99c6b0849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692992432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2692992432
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.3476228305
Short name T166
Test name
Test status
Simulation time 67705955 ps
CPU time 0.88 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 216104 kb
Host smart-d4c8d183-35c8-4e67-b36a-76d988bcb49b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476228305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3476228305
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/32.edn_alert.2991624333
Short name T180
Test name
Test status
Simulation time 44549309 ps
CPU time 1.18 seconds
Started Mar 24 01:06:31 PM PDT 24
Finished Mar 24 01:06:33 PM PDT 24
Peak memory 215652 kb
Host smart-2aa0a0cf-5104-4f6d-a388-0869a5e0922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991624333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2991624333
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2890359076
Short name T790
Test name
Test status
Simulation time 91243707 ps
CPU time 1.38 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:39 PM PDT 24
Peak memory 219460 kb
Host smart-17d31b94-3744-4203-93c5-715b064cb9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890359076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2890359076
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.188896314
Short name T221
Test name
Test status
Simulation time 15778402 ps
CPU time 1.06 seconds
Started Mar 24 12:35:26 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 206200 kb
Host smart-46595ea0-b141-46ae-b8ab-e050b7b7368e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188896314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.188896314
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1624905196
Short name T247
Test name
Test status
Simulation time 795178929 ps
CPU time 5.08 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 206248 kb
Host smart-d233578e-e1d3-4318-bc52-0fbfab137863
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624905196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1624905196
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.737407157
Short name T923
Test name
Test status
Simulation time 18797769 ps
CPU time 0.97 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:37 PM PDT 24
Peak memory 206220 kb
Host smart-7633655d-9a94-42b3-af63-b89f467f0bd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737407157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.737407157
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.422806309
Short name T921
Test name
Test status
Simulation time 61579913 ps
CPU time 2.15 seconds
Started Mar 24 12:35:27 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 214680 kb
Host smart-9996115e-d606-49cf-85f7-0a80ce21adf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422806309 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.422806309
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3781752474
Short name T922
Test name
Test status
Simulation time 99974695 ps
CPU time 0.88 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 206212 kb
Host smart-bc6eda8c-93da-4045-8c98-29fa94e63241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781752474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3781752474
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2790664123
Short name T871
Test name
Test status
Simulation time 15645023 ps
CPU time 0.86 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 206208 kb
Host smart-561cb1f2-e5dd-44fb-a376-f86ae5ecd9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790664123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2790664123
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4010139436
Short name T241
Test name
Test status
Simulation time 28309125 ps
CPU time 1.03 seconds
Started Mar 24 12:35:22 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 206320 kb
Host smart-e8d81c58-c1ba-4c7a-bada-ecb54cced097
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010139436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4010139436
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3073897566
Short name T851
Test name
Test status
Simulation time 70216922 ps
CPU time 2.55 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 214760 kb
Host smart-0a5be4a0-ad54-4aa1-8858-011ba9cf3deb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073897566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3073897566
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2138301205
Short name T915
Test name
Test status
Simulation time 54329642 ps
CPU time 1.71 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 206324 kb
Host smart-3f859eff-44ee-40c9-a86e-08fa1990b7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138301205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2138301205
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4073289469
Short name T950
Test name
Test status
Simulation time 25032021 ps
CPU time 1.14 seconds
Started Mar 24 12:35:27 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 206220 kb
Host smart-db88d38a-715f-4a1a-bcd8-c4c1623a49d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073289469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4073289469
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2809603517
Short name T881
Test name
Test status
Simulation time 96323298 ps
CPU time 3.17 seconds
Started Mar 24 12:35:22 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 206212 kb
Host smart-61c10ecc-2940-4890-961e-53c5efc8694d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809603517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2809603517
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2224491686
Short name T230
Test name
Test status
Simulation time 39388978 ps
CPU time 0.87 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 206180 kb
Host smart-72278ba1-1d18-4089-9e2f-b7d627e339b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224491686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2224491686
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.587416028
Short name T878
Test name
Test status
Simulation time 80573061 ps
CPU time 1.46 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 214664 kb
Host smart-50e35e0c-40a8-491d-8313-4ffedbe68a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587416028 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.587416028
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.198764038
Short name T246
Test name
Test status
Simulation time 16731574 ps
CPU time 0.95 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 206228 kb
Host smart-a7b4fcc0-afcc-471d-a853-cc993a8d0453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198764038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.198764038
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2529263323
Short name T951
Test name
Test status
Simulation time 14026902 ps
CPU time 0.86 seconds
Started Mar 24 12:35:49 PM PDT 24
Finished Mar 24 12:35:50 PM PDT 24
Peak memory 206272 kb
Host smart-0099da5c-d986-4246-9098-9bf5f397fc14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529263323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2529263323
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.950405253
Short name T242
Test name
Test status
Simulation time 55626488 ps
CPU time 1.32 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 206352 kb
Host smart-924b3cbd-05ad-4b2c-b9e2-70f14f7b0457
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950405253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.950405253
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.36662062
Short name T954
Test name
Test status
Simulation time 61046756 ps
CPU time 2.1 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 214712 kb
Host smart-084ea8a2-e21a-438a-bee0-318cfe5c4eca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36662062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.36662062
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2137225543
Short name T897
Test name
Test status
Simulation time 145967126 ps
CPU time 1.87 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 206316 kb
Host smart-63dbe8bf-42fa-4b49-a200-74a42776fd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137225543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2137225543
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2760677752
Short name T850
Test name
Test status
Simulation time 34032989 ps
CPU time 1.45 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:08 PM PDT 24
Peak memory 214596 kb
Host smart-2d485798-fb85-4371-976e-d636343db0f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760677752 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2760677752
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3461430918
Short name T893
Test name
Test status
Simulation time 13619215 ps
CPU time 0.91 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 206216 kb
Host smart-5858d638-4770-47cd-b1dc-6800c8b12825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461430918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3461430918
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.4087391831
Short name T847
Test name
Test status
Simulation time 12879644 ps
CPU time 0.87 seconds
Started Mar 24 12:35:42 PM PDT 24
Finished Mar 24 12:35:43 PM PDT 24
Peak memory 206216 kb
Host smart-0d42fbe2-9ae5-4fbc-aa5d-117ae2122ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087391831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4087391831
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2616448510
Short name T959
Test name
Test status
Simulation time 38420441 ps
CPU time 0.95 seconds
Started Mar 24 12:35:44 PM PDT 24
Finished Mar 24 12:35:45 PM PDT 24
Peak memory 206704 kb
Host smart-23455d03-f547-43f5-ba87-3d86cf98cade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616448510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2616448510
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2508754194
Short name T920
Test name
Test status
Simulation time 897240573 ps
CPU time 3.25 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:38 PM PDT 24
Peak memory 213748 kb
Host smart-67e6baf9-3e5a-4567-9b44-0e61949b426b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508754194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2508754194
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.638707086
Short name T956
Test name
Test status
Simulation time 128687765 ps
CPU time 2.49 seconds
Started Mar 24 12:35:44 PM PDT 24
Finished Mar 24 12:35:46 PM PDT 24
Peak memory 206428 kb
Host smart-bb644449-b05d-4345-97b9-e48f2974fef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638707086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.638707086
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1448811960
Short name T855
Test name
Test status
Simulation time 56813206 ps
CPU time 1.01 seconds
Started Mar 24 12:35:49 PM PDT 24
Finished Mar 24 12:35:50 PM PDT 24
Peak memory 206484 kb
Host smart-72fa886e-8650-4ed6-a631-aaeb59a8cf49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448811960 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1448811960
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2481103845
Short name T232
Test name
Test status
Simulation time 61895918 ps
CPU time 0.84 seconds
Started Mar 24 12:35:56 PM PDT 24
Finished Mar 24 12:35:57 PM PDT 24
Peak memory 206060 kb
Host smart-f1dc0665-fa2b-47d2-a25f-7cfebb53519f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481103845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2481103845
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3886311129
Short name T946
Test name
Test status
Simulation time 14717355 ps
CPU time 0.86 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 206224 kb
Host smart-0e918758-bad7-4784-b91f-45be13b74d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886311129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3886311129
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.245037220
Short name T938
Test name
Test status
Simulation time 54442923 ps
CPU time 1.06 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206328 kb
Host smart-ede57c5e-2fd1-4782-94c7-fcf04423e515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245037220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.245037220
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2602539026
Short name T896
Test name
Test status
Simulation time 39417453 ps
CPU time 1.85 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 214584 kb
Host smart-6b8b3c1f-eac2-4e56-996e-e5c8a3e06e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602539026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2602539026
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3145405259
Short name T902
Test name
Test status
Simulation time 129934806 ps
CPU time 2.82 seconds
Started Mar 24 12:35:37 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206456 kb
Host smart-2b02191c-077f-4c77-b37f-5f6fe708bf57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145405259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3145405259
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.74060922
Short name T849
Test name
Test status
Simulation time 20307088 ps
CPU time 1.39 seconds
Started Mar 24 12:35:50 PM PDT 24
Finished Mar 24 12:35:52 PM PDT 24
Peak memory 214672 kb
Host smart-d7fc9728-e722-478a-b865-05cdadaa50cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74060922 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.74060922
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.662507451
Short name T233
Test name
Test status
Simulation time 25846008 ps
CPU time 0.89 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:02 PM PDT 24
Peak memory 206216 kb
Host smart-58acbc8c-cbce-4024-aeb2-359f34fa5fd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662507451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.662507451
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3776055842
Short name T925
Test name
Test status
Simulation time 15234292 ps
CPU time 0.9 seconds
Started Mar 24 12:35:50 PM PDT 24
Finished Mar 24 12:35:51 PM PDT 24
Peak memory 206216 kb
Host smart-448e6fea-cfb2-4d16-8678-55e917489ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776055842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3776055842
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3800720215
Short name T887
Test name
Test status
Simulation time 22757853 ps
CPU time 1.11 seconds
Started Mar 24 12:35:32 PM PDT 24
Finished Mar 24 12:35:34 PM PDT 24
Peak memory 206396 kb
Host smart-397deb15-0e35-43a9-80ec-5df5d5b101e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800720215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3800720215
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1411103894
Short name T890
Test name
Test status
Simulation time 224315830 ps
CPU time 3.9 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 214620 kb
Host smart-7d1c3bb8-94f1-4702-834e-0dde44e16ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411103894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1411103894
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3821549060
Short name T916
Test name
Test status
Simulation time 147175543 ps
CPU time 2.2 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 206388 kb
Host smart-9a20c304-3e7f-4f36-acb2-a88b1a8c3ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821549060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3821549060
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2381594390
Short name T901
Test name
Test status
Simulation time 18230769 ps
CPU time 1.31 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:42 PM PDT 24
Peak memory 214604 kb
Host smart-0809dc64-6a3b-490d-8996-cf161a26e3ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381594390 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2381594390
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3923549813
Short name T942
Test name
Test status
Simulation time 22737641 ps
CPU time 0.93 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206200 kb
Host smart-6c6a59cb-bf06-4498-a889-094e99d57f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923549813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3923549813
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1207217866
Short name T905
Test name
Test status
Simulation time 23654071 ps
CPU time 0.82 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 206224 kb
Host smart-939bc6c1-b185-4b11-beff-ae586298965c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207217866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1207217866
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.155839195
Short name T952
Test name
Test status
Simulation time 17622919 ps
CPU time 0.98 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 206380 kb
Host smart-0c13f8bb-8035-4872-9c72-bcb766aafc28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155839195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.155839195
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1236203365
Short name T840
Test name
Test status
Simulation time 98722973 ps
CPU time 2 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 214616 kb
Host smart-7b2b8130-9922-4fa5-99e7-f093c435be07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236203365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1236203365
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1442221896
Short name T249
Test name
Test status
Simulation time 305373431 ps
CPU time 1.5 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206396 kb
Host smart-076e8457-9ed1-4fc1-8be8-1c7c279b677f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442221896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1442221896
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.958572544
Short name T889
Test name
Test status
Simulation time 115848422 ps
CPU time 1.16 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 222764 kb
Host smart-be691148-70d7-41cc-b993-3b1311803c55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958572544 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.958572544
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2071839334
Short name T245
Test name
Test status
Simulation time 14425278 ps
CPU time 0.96 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:42 PM PDT 24
Peak memory 206228 kb
Host smart-99a76668-8e46-4439-9055-c8bc2c7991db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071839334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2071839334
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3619927950
Short name T888
Test name
Test status
Simulation time 16602888 ps
CPU time 0.88 seconds
Started Mar 24 12:36:16 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 206196 kb
Host smart-0460ad9e-be2b-49e8-82ac-0cfd60860838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619927950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3619927950
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3345545025
Short name T919
Test name
Test status
Simulation time 36947233 ps
CPU time 1.06 seconds
Started Mar 24 12:35:32 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 206292 kb
Host smart-2342bf84-2562-42db-a960-14372d83bd4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345545025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3345545025
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.789174615
Short name T906
Test name
Test status
Simulation time 39001333 ps
CPU time 2.03 seconds
Started Mar 24 12:35:31 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 214604 kb
Host smart-578ac6c3-aa8d-441c-b30f-9fd3c83cc8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789174615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.789174615
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2446449108
Short name T250
Test name
Test status
Simulation time 251163401 ps
CPU time 2.03 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 206356 kb
Host smart-445dc338-98e5-4380-881e-02e006455fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446449108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2446449108
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1669365151
Short name T843
Test name
Test status
Simulation time 163588038 ps
CPU time 1.15 seconds
Started Mar 24 12:35:52 PM PDT 24
Finished Mar 24 12:35:53 PM PDT 24
Peak memory 214588 kb
Host smart-a03276cc-9848-48a1-a2ea-6dba7992f943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669365151 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1669365151
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2072268273
Short name T235
Test name
Test status
Simulation time 68714897 ps
CPU time 0.89 seconds
Started Mar 24 12:35:43 PM PDT 24
Finished Mar 24 12:35:44 PM PDT 24
Peak memory 206204 kb
Host smart-08deae8c-4422-442e-8188-3b6103d64b9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072268273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2072268273
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3326680673
Short name T937
Test name
Test status
Simulation time 37305402 ps
CPU time 0.78 seconds
Started Mar 24 12:35:40 PM PDT 24
Finished Mar 24 12:35:41 PM PDT 24
Peak memory 205996 kb
Host smart-d1a18df3-79d3-4319-ae22-a02f612d9acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326680673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3326680673
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2803831635
Short name T899
Test name
Test status
Simulation time 28125873 ps
CPU time 1.04 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 206408 kb
Host smart-1a32ee79-57f1-4536-bbd4-d0ec7ba6912b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803831635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2803831635
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1324961095
Short name T957
Test name
Test status
Simulation time 182079327 ps
CPU time 3.17 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:43 PM PDT 24
Peak memory 214196 kb
Host smart-99689f00-a3e4-45e7-9224-6aee0135cba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324961095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1324961095
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2676003153
Short name T960
Test name
Test status
Simulation time 338139595 ps
CPU time 5.72 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:47 PM PDT 24
Peak memory 206344 kb
Host smart-1e8d7fcc-32ff-49f3-b304-17ebe8af572b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676003153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2676003153
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2876698206
Short name T856
Test name
Test status
Simulation time 23568914 ps
CPU time 1.21 seconds
Started Mar 24 12:35:54 PM PDT 24
Finished Mar 24 12:35:55 PM PDT 24
Peak memory 214672 kb
Host smart-04e20369-be41-424d-8046-70d9069a7168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876698206 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2876698206
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3785716234
Short name T231
Test name
Test status
Simulation time 12568641 ps
CPU time 0.81 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:41 PM PDT 24
Peak memory 206024 kb
Host smart-9405ec0b-6fe6-4199-84b2-0e7eb3df143f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785716234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3785716234
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.94976508
Short name T903
Test name
Test status
Simulation time 11981163 ps
CPU time 0.82 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 206220 kb
Host smart-0d680c54-4de3-404c-811b-6bfb2b197b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94976508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.94976508
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1903936193
Short name T961
Test name
Test status
Simulation time 31557459 ps
CPU time 2.11 seconds
Started Mar 24 12:35:43 PM PDT 24
Finished Mar 24 12:35:45 PM PDT 24
Peak memory 214580 kb
Host smart-e1967730-555b-4928-9f65-a706f610b6c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903936193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1903936193
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2650626368
Short name T928
Test name
Test status
Simulation time 71699301 ps
CPU time 1.43 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206344 kb
Host smart-f8c4150d-837d-40c3-ae93-1dbdcfca2611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650626368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2650626368
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.229086720
Short name T879
Test name
Test status
Simulation time 37014568 ps
CPU time 2.12 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 214600 kb
Host smart-f13f5e79-0ed7-4fba-910c-6c6498ce8eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229086720 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.229086720
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1162318610
Short name T234
Test name
Test status
Simulation time 29045220 ps
CPU time 0.93 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 205676 kb
Host smart-7978647e-566e-490b-9100-3e69a574931c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162318610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1162318610
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1403557474
Short name T939
Test name
Test status
Simulation time 16832814 ps
CPU time 0.82 seconds
Started Mar 24 12:35:44 PM PDT 24
Finished Mar 24 12:35:45 PM PDT 24
Peak memory 206044 kb
Host smart-b2f142fa-aa7f-4a1a-94e6-fe82fbaeacec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403557474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1403557474
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3181467072
Short name T224
Test name
Test status
Simulation time 14830449 ps
CPU time 0.96 seconds
Started Mar 24 12:35:53 PM PDT 24
Finished Mar 24 12:35:54 PM PDT 24
Peak memory 206444 kb
Host smart-7d059f71-58f7-4cf6-89d3-0968e0a8d2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181467072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3181467072
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.722191297
Short name T935
Test name
Test status
Simulation time 64586487 ps
CPU time 2.43 seconds
Started Mar 24 12:36:14 PM PDT 24
Finished Mar 24 12:36:16 PM PDT 24
Peak memory 214548 kb
Host smart-0ad54de8-5970-40ce-afc5-c49bea14d335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722191297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.722191297
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2522448523
Short name T259
Test name
Test status
Simulation time 49242343 ps
CPU time 1.57 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 206344 kb
Host smart-a833e939-2f1e-47ad-a038-a75e9401ca45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522448523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2522448523
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2761229994
Short name T848
Test name
Test status
Simulation time 44942981 ps
CPU time 1.24 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 214944 kb
Host smart-c5ab3b40-2073-4d37-a73e-4617535222de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761229994 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2761229994
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1813715718
Short name T877
Test name
Test status
Simulation time 41719235 ps
CPU time 0.84 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 205964 kb
Host smart-d9821b86-b606-4a8e-b85f-e63a523f474d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813715718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1813715718
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3187379013
Short name T965
Test name
Test status
Simulation time 18648023 ps
CPU time 0.82 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 206200 kb
Host smart-11bfb8a3-664c-47fc-a0e3-279c0ce84fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187379013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3187379013
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.466532977
Short name T226
Test name
Test status
Simulation time 96397946 ps
CPU time 1.08 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 206460 kb
Host smart-3574b62d-1d8e-4efd-84ff-ff1b661eee5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466532977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.466532977
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2800973644
Short name T936
Test name
Test status
Simulation time 110430935 ps
CPU time 3.48 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:25 PM PDT 24
Peak memory 214656 kb
Host smart-4b275995-5a06-4e61-b256-68ff11836ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800973644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2800973644
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1908726484
Short name T886
Test name
Test status
Simulation time 167934328 ps
CPU time 1.63 seconds
Started Mar 24 12:35:53 PM PDT 24
Finished Mar 24 12:35:54 PM PDT 24
Peak memory 206332 kb
Host smart-dd1f93cc-c93c-4446-8192-6b6430c2fb3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908726484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1908726484
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1621788271
Short name T907
Test name
Test status
Simulation time 124369852 ps
CPU time 1.5 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 222820 kb
Host smart-a5c82fd1-fff2-4177-a73d-bc7015437f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621788271 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1621788271
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2859128431
Short name T918
Test name
Test status
Simulation time 28753059 ps
CPU time 0.86 seconds
Started Mar 24 12:35:26 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 206208 kb
Host smart-8cff89c9-f44a-43a2-a11d-d767c2cd0eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859128431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2859128431
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2658857732
Short name T917
Test name
Test status
Simulation time 14558737 ps
CPU time 0.86 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 206204 kb
Host smart-46631876-3bb3-4fc7-a9fe-524e2f7456e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658857732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2658857732
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4158645783
Short name T243
Test name
Test status
Simulation time 76326943 ps
CPU time 1.4 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:37 PM PDT 24
Peak memory 206416 kb
Host smart-d5dab53b-23ec-41df-a86b-0c5f4fb6f774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158645783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.4158645783
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2409260212
Short name T947
Test name
Test status
Simulation time 162814025 ps
CPU time 3.83 seconds
Started Mar 24 12:35:52 PM PDT 24
Finished Mar 24 12:35:55 PM PDT 24
Peak memory 214980 kb
Host smart-74fa9175-99a1-455f-b06c-fc920622ad75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409260212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2409260212
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2595327499
Short name T953
Test name
Test status
Simulation time 280759070 ps
CPU time 2.12 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:43 PM PDT 24
Peak memory 206392 kb
Host smart-7eb2f0be-8f8c-46f4-afa8-51acf8280c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595327499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2595327499
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.785113872
Short name T870
Test name
Test status
Simulation time 190516302 ps
CPU time 2.98 seconds
Started Mar 24 12:35:31 PM PDT 24
Finished Mar 24 12:35:34 PM PDT 24
Peak memory 206196 kb
Host smart-808ff2a1-61bf-4960-b763-7f2cbb695e23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785113872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.785113872
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1849864264
Short name T236
Test name
Test status
Simulation time 16075016 ps
CPU time 0.91 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 206212 kb
Host smart-6b5b65b0-7be6-4929-bb47-d7d3f1694002
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849864264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1849864264
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2105232117
Short name T930
Test name
Test status
Simulation time 67568138 ps
CPU time 1.46 seconds
Started Mar 24 12:35:37 PM PDT 24
Finished Mar 24 12:35:38 PM PDT 24
Peak memory 214456 kb
Host smart-b53a9f4b-3e52-4420-bfeb-68eb422f69cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105232117 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2105232117
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3015086693
Short name T838
Test name
Test status
Simulation time 14417795 ps
CPU time 0.89 seconds
Started Mar 24 12:35:21 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 206184 kb
Host smart-64239717-9e31-4251-81b6-f05c3e83f346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015086693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3015086693
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.482059223
Short name T853
Test name
Test status
Simulation time 14097115 ps
CPU time 0.8 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:37 PM PDT 24
Peak memory 206304 kb
Host smart-c0b2e430-c721-4623-a993-30155c9b5a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482059223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.482059223
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1232470582
Short name T244
Test name
Test status
Simulation time 55796360 ps
CPU time 1.31 seconds
Started Mar 24 12:35:22 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 206320 kb
Host smart-a45bf10c-e266-43d6-8345-f51fcb40dbe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232470582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1232470582
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2547231181
Short name T864
Test name
Test status
Simulation time 213974473 ps
CPU time 3.88 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:42 PM PDT 24
Peak memory 214600 kb
Host smart-a20b363e-f52e-4410-a5de-9863749859cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547231181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2547231181
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1270929243
Short name T874
Test name
Test status
Simulation time 139099889 ps
CPU time 1.76 seconds
Started Mar 24 12:35:44 PM PDT 24
Finished Mar 24 12:35:45 PM PDT 24
Peak memory 206328 kb
Host smart-79c021b4-4d81-4fe3-82b5-68b77ea68728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270929243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1270929243
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1046507735
Short name T945
Test name
Test status
Simulation time 47775435 ps
CPU time 0.87 seconds
Started Mar 24 12:35:43 PM PDT 24
Finished Mar 24 12:35:44 PM PDT 24
Peak memory 206152 kb
Host smart-7c7571c0-d154-4c20-8fd3-82660c1bd8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046507735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1046507735
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2271270374
Short name T868
Test name
Test status
Simulation time 22493467 ps
CPU time 0.79 seconds
Started Mar 24 12:35:54 PM PDT 24
Finished Mar 24 12:35:56 PM PDT 24
Peak memory 206036 kb
Host smart-c62e8b1b-41c5-4e71-8067-e1c87bc55e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271270374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2271270374
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2993386999
Short name T911
Test name
Test status
Simulation time 14959362 ps
CPU time 0.88 seconds
Started Mar 24 12:36:00 PM PDT 24
Finished Mar 24 12:36:01 PM PDT 24
Peak memory 206224 kb
Host smart-7c17d6af-09ad-43a1-943e-bab392250619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993386999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2993386999
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3061564107
Short name T860
Test name
Test status
Simulation time 24724196 ps
CPU time 0.81 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:41 PM PDT 24
Peak memory 206208 kb
Host smart-0aa64de4-38e6-4ee8-a002-f958f7573a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061564107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3061564107
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2359877525
Short name T927
Test name
Test status
Simulation time 15651631 ps
CPU time 0.85 seconds
Started Mar 24 12:35:45 PM PDT 24
Finished Mar 24 12:35:46 PM PDT 24
Peak memory 206204 kb
Host smart-c0fae506-f543-4e49-bc32-a7aaf3cd02f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359877525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2359877525
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2315638878
Short name T884
Test name
Test status
Simulation time 26794333 ps
CPU time 0.76 seconds
Started Mar 24 12:36:02 PM PDT 24
Finished Mar 24 12:36:04 PM PDT 24
Peak memory 206044 kb
Host smart-cbcaabd5-f5bf-496a-a21d-1c5b1e34cbfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315638878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2315638878
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1164742054
Short name T882
Test name
Test status
Simulation time 20037683 ps
CPU time 0.83 seconds
Started Mar 24 12:35:47 PM PDT 24
Finished Mar 24 12:35:48 PM PDT 24
Peak memory 206192 kb
Host smart-4fdea648-dce5-4bfc-accf-cccd03810aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164742054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1164742054
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1717800293
Short name T839
Test name
Test status
Simulation time 30600016 ps
CPU time 0.78 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:02 PM PDT 24
Peak memory 206008 kb
Host smart-c69c9d69-d85d-45b5-841a-fca8fd96d99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717800293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1717800293
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3860200068
Short name T958
Test name
Test status
Simulation time 21118682 ps
CPU time 0.85 seconds
Started Mar 24 12:36:07 PM PDT 24
Finished Mar 24 12:36:07 PM PDT 24
Peak memory 206184 kb
Host smart-19c841c7-1392-46c3-863e-9103c2fe4fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860200068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3860200068
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.419839982
Short name T852
Test name
Test status
Simulation time 55535393 ps
CPU time 0.84 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206024 kb
Host smart-b80ea3b0-98ab-42b4-bb0d-5e644f0b43a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419839982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.419839982
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.278041607
Short name T238
Test name
Test status
Simulation time 17223632 ps
CPU time 1.06 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 206232 kb
Host smart-af1c3b11-222b-4076-89a8-c6284907c2b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278041607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.278041607
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2551816993
Short name T940
Test name
Test status
Simulation time 68965496 ps
CPU time 3.26 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 206224 kb
Host smart-2bb382bb-3ce4-482f-b0dc-b03e2be84a99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551816993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2551816993
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.655266800
Short name T225
Test name
Test status
Simulation time 44475882 ps
CPU time 0.83 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206208 kb
Host smart-ad6c3cbb-8520-446f-8743-eb6f481961f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655266800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.655266800
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3162546957
Short name T949
Test name
Test status
Simulation time 21983938 ps
CPU time 0.93 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 206392 kb
Host smart-67120f43-5ab2-4a66-9ddf-6d21fea5ef1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162546957 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3162546957
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1377201495
Short name T894
Test name
Test status
Simulation time 16596797 ps
CPU time 0.81 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 206036 kb
Host smart-026a6330-f4c8-472d-b788-894fac7b9957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377201495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1377201495
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2039979701
Short name T948
Test name
Test status
Simulation time 13213608 ps
CPU time 0.9 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:42 PM PDT 24
Peak memory 206216 kb
Host smart-554a088e-f7fa-4460-8a5f-6bc51ac58032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039979701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2039979701
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.54986100
Short name T943
Test name
Test status
Simulation time 72254819 ps
CPU time 1.43 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206328 kb
Host smart-7a77fd31-2cef-47c8-8d7e-5fd6273eca19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54986100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outs
tanding.54986100
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4232085084
Short name T912
Test name
Test status
Simulation time 27033305 ps
CPU time 1.81 seconds
Started Mar 24 12:35:40 PM PDT 24
Finished Mar 24 12:35:42 PM PDT 24
Peak memory 214684 kb
Host smart-9ff0a0d2-83e1-4fa4-b3e8-a7b2d59bc4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232085084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4232085084
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1846274665
Short name T867
Test name
Test status
Simulation time 233869073 ps
CPU time 2.41 seconds
Started Mar 24 12:35:52 PM PDT 24
Finished Mar 24 12:35:55 PM PDT 24
Peak memory 206356 kb
Host smart-3a88fbeb-1829-4e92-9969-423104e3cead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846274665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1846274665
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2643665384
Short name T885
Test name
Test status
Simulation time 19276234 ps
CPU time 0.86 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 205976 kb
Host smart-84823614-e925-47e8-a482-00e1d3402614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643665384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2643665384
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1625300790
Short name T873
Test name
Test status
Simulation time 40613994 ps
CPU time 0.8 seconds
Started Mar 24 12:35:52 PM PDT 24
Finished Mar 24 12:35:53 PM PDT 24
Peak memory 206048 kb
Host smart-1bc7d048-8dea-4047-a2a0-4278d2ed3cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625300790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1625300790
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.44192329
Short name T858
Test name
Test status
Simulation time 24866979 ps
CPU time 0.85 seconds
Started Mar 24 12:35:53 PM PDT 24
Finished Mar 24 12:35:54 PM PDT 24
Peak memory 206228 kb
Host smart-e438808b-2ec1-4523-a376-0fd336c51e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44192329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.44192329
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.517841123
Short name T880
Test name
Test status
Simulation time 13946817 ps
CPU time 0.88 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206304 kb
Host smart-724c5cba-bcc5-414a-86a0-30bf64d77d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517841123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.517841123
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2929268217
Short name T861
Test name
Test status
Simulation time 20019605 ps
CPU time 0.91 seconds
Started Mar 24 12:35:55 PM PDT 24
Finished Mar 24 12:35:56 PM PDT 24
Peak memory 206220 kb
Host smart-0f00980c-43d0-4a2b-b9f7-bec3cb48bfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929268217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2929268217
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3880517570
Short name T924
Test name
Test status
Simulation time 19422123 ps
CPU time 0.84 seconds
Started Mar 24 12:36:00 PM PDT 24
Finished Mar 24 12:36:01 PM PDT 24
Peak memory 206228 kb
Host smart-1b9fb732-c0c0-4bdd-b793-3bcc180e8cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880517570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3880517570
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2990697455
Short name T941
Test name
Test status
Simulation time 37182841 ps
CPU time 0.92 seconds
Started Mar 24 12:35:49 PM PDT 24
Finished Mar 24 12:35:50 PM PDT 24
Peak memory 206228 kb
Host smart-f324db39-21e2-48de-b181-20c14d5be4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990697455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2990697455
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2843041021
Short name T876
Test name
Test status
Simulation time 13936012 ps
CPU time 0.88 seconds
Started Mar 24 12:35:43 PM PDT 24
Finished Mar 24 12:35:44 PM PDT 24
Peak memory 206192 kb
Host smart-ebb1d0c1-4d34-459d-ada7-141281643f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843041021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2843041021
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3108800215
Short name T966
Test name
Test status
Simulation time 14284048 ps
CPU time 0.86 seconds
Started Mar 24 12:35:53 PM PDT 24
Finished Mar 24 12:35:54 PM PDT 24
Peak memory 206220 kb
Host smart-7c28ddfb-ee7c-4ba6-bd2e-5db2448bcd07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108800215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3108800215
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.803791725
Short name T895
Test name
Test status
Simulation time 75988915 ps
CPU time 0.81 seconds
Started Mar 24 12:35:56 PM PDT 24
Finished Mar 24 12:35:57 PM PDT 24
Peak memory 206044 kb
Host smart-c0404012-6be4-43e8-9575-496e31af19ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803791725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.803791725
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.405434469
Short name T944
Test name
Test status
Simulation time 56489129 ps
CPU time 1.1 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:38 PM PDT 24
Peak memory 206208 kb
Host smart-4531b396-c0ce-4cf0-b60f-3e72a74f0855
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405434469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.405434469
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2992851700
Short name T227
Test name
Test status
Simulation time 223504429 ps
CPU time 2.04 seconds
Started Mar 24 12:35:27 PM PDT 24
Finished Mar 24 12:35:30 PM PDT 24
Peak memory 206184 kb
Host smart-874ac252-2a13-48a4-873b-ebd151ba840b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992851700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2992851700
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2192038838
Short name T237
Test name
Test status
Simulation time 86115155 ps
CPU time 0.86 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206240 kb
Host smart-68a42b9a-b44d-46da-b671-92ca0fdde686
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192038838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2192038838
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1808396700
Short name T932
Test name
Test status
Simulation time 85024649 ps
CPU time 1.18 seconds
Started Mar 24 12:35:40 PM PDT 24
Finished Mar 24 12:35:41 PM PDT 24
Peak memory 214632 kb
Host smart-365b1831-0aaa-4116-bdff-484b42ee40b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808396700 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1808396700
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1075145566
Short name T914
Test name
Test status
Simulation time 49431088 ps
CPU time 0.85 seconds
Started Mar 24 12:35:37 PM PDT 24
Finished Mar 24 12:35:38 PM PDT 24
Peak memory 206200 kb
Host smart-a0e3dc88-9475-41b7-b250-93f2b2fd92d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075145566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1075145566
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.27317974
Short name T910
Test name
Test status
Simulation time 14362582 ps
CPU time 0.85 seconds
Started Mar 24 12:35:40 PM PDT 24
Finished Mar 24 12:35:46 PM PDT 24
Peak memory 206200 kb
Host smart-e5ea43c0-d227-4e84-87e6-64bbc1990875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27317974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.27317974
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.413587325
Short name T875
Test name
Test status
Simulation time 54631277 ps
CPU time 1.46 seconds
Started Mar 24 12:36:00 PM PDT 24
Finished Mar 24 12:36:02 PM PDT 24
Peak memory 206444 kb
Host smart-d53d6c98-25dd-4285-b341-cbd5f0908e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413587325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.413587325
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2405064058
Short name T934
Test name
Test status
Simulation time 52635750 ps
CPU time 1.92 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:38 PM PDT 24
Peak memory 214680 kb
Host smart-738e3673-29d9-4f43-9c3a-dee66b797d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405064058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2405064058
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1828668745
Short name T962
Test name
Test status
Simulation time 89016069 ps
CPU time 2.18 seconds
Started Mar 24 12:35:45 PM PDT 24
Finished Mar 24 12:35:52 PM PDT 24
Peak memory 206396 kb
Host smart-c68f431e-3fec-4da2-b73b-f9fb291ba86b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828668745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1828668745
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3658313745
Short name T892
Test name
Test status
Simulation time 15515174 ps
CPU time 0.94 seconds
Started Mar 24 12:35:46 PM PDT 24
Finished Mar 24 12:35:47 PM PDT 24
Peak memory 206176 kb
Host smart-3cee4796-70e7-4073-8dd7-c5a40fed22d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658313745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3658313745
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.777766692
Short name T891
Test name
Test status
Simulation time 24778053 ps
CPU time 0.85 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206204 kb
Host smart-fab881d7-acf0-446a-88b5-8fdf9c24b69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777766692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.777766692
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.975546081
Short name T869
Test name
Test status
Simulation time 26435881 ps
CPU time 0.84 seconds
Started Mar 24 12:35:49 PM PDT 24
Finished Mar 24 12:35:50 PM PDT 24
Peak memory 206216 kb
Host smart-88b116b2-1294-43ff-8714-c63062da6581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975546081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.975546081
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3925648791
Short name T883
Test name
Test status
Simulation time 14336169 ps
CPU time 0.88 seconds
Started Mar 24 12:35:44 PM PDT 24
Finished Mar 24 12:35:46 PM PDT 24
Peak memory 206196 kb
Host smart-73f4e595-ab5c-41b1-943d-39ff5a82d3ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925648791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3925648791
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3066983000
Short name T862
Test name
Test status
Simulation time 16298856 ps
CPU time 0.93 seconds
Started Mar 24 12:35:51 PM PDT 24
Finished Mar 24 12:35:52 PM PDT 24
Peak memory 206568 kb
Host smart-26196839-a729-4ab6-9de5-742bf5e48da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066983000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3066983000
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1677579795
Short name T841
Test name
Test status
Simulation time 13957117 ps
CPU time 0.91 seconds
Started Mar 24 12:35:46 PM PDT 24
Finished Mar 24 12:35:47 PM PDT 24
Peak memory 206272 kb
Host smart-5873dfcb-600c-43a4-b9d6-0bd81cb6b15b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677579795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1677579795
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1047870217
Short name T872
Test name
Test status
Simulation time 66280080 ps
CPU time 0.78 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 206016 kb
Host smart-06c3f23c-9d12-4fa1-a4f2-c44e2895b4ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047870217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1047870217
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1658415324
Short name T913
Test name
Test status
Simulation time 60473639 ps
CPU time 0.76 seconds
Started Mar 24 12:35:43 PM PDT 24
Finished Mar 24 12:35:44 PM PDT 24
Peak memory 206032 kb
Host smart-f7de3250-aab4-4b18-af45-ae139cc3637f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658415324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1658415324
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4146136974
Short name T845
Test name
Test status
Simulation time 24959917 ps
CPU time 0.9 seconds
Started Mar 24 12:35:48 PM PDT 24
Finished Mar 24 12:35:49 PM PDT 24
Peak memory 206572 kb
Host smart-bee76706-5be1-49a9-a656-559122fd2f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146136974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4146136974
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.243329832
Short name T859
Test name
Test status
Simulation time 21334628 ps
CPU time 0.85 seconds
Started Mar 24 12:35:40 PM PDT 24
Finished Mar 24 12:35:41 PM PDT 24
Peak memory 206200 kb
Host smart-a1bad163-93a0-4255-8f55-ea4f3841d2d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243329832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.243329832
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2296353026
Short name T854
Test name
Test status
Simulation time 25455677 ps
CPU time 1.01 seconds
Started Mar 24 12:35:26 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 206436 kb
Host smart-ad468182-9209-4979-8aba-2cf43560d94f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296353026 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2296353026
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.225276227
Short name T228
Test name
Test status
Simulation time 15567079 ps
CPU time 1 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 206220 kb
Host smart-28e24436-82fa-47ee-b036-24a5b0f3ad1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225276227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.225276227
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1821858270
Short name T865
Test name
Test status
Simulation time 28899814 ps
CPU time 0.78 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 205964 kb
Host smart-952e92a7-7e6f-46cc-bbb1-6594fdb25288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821858270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1821858270
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3884960999
Short name T218
Test name
Test status
Simulation time 38973933 ps
CPU time 1.49 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 206424 kb
Host smart-e42eb39b-d113-46a8-9ee3-ab4fb6da2771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884960999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3884960999
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1536628459
Short name T931
Test name
Test status
Simulation time 109398779 ps
CPU time 3.62 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:34 PM PDT 24
Peak memory 214612 kb
Host smart-c7800c1b-9beb-4cae-848b-991c84618548
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536628459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1536628459
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3616507978
Short name T846
Test name
Test status
Simulation time 94737920 ps
CPU time 1.27 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:29 PM PDT 24
Peak memory 214604 kb
Host smart-91c2e80f-ba5c-48a6-aca0-8cc3957636ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616507978 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3616507978
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.4070385203
Short name T929
Test name
Test status
Simulation time 71037017 ps
CPU time 0.85 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:42 PM PDT 24
Peak memory 206020 kb
Host smart-af23c0be-e1e0-452a-8221-b3b9a0012257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070385203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4070385203
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.260714780
Short name T926
Test name
Test status
Simulation time 20022309 ps
CPU time 0.84 seconds
Started Mar 24 12:35:31 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 205972 kb
Host smart-d5641246-6ee9-4ae3-b0fe-a130b3a7c918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260714780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.260714780
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1144040940
Short name T223
Test name
Test status
Simulation time 296059189 ps
CPU time 1.02 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:37 PM PDT 24
Peak memory 206084 kb
Host smart-5d292f13-e59d-4b55-90f4-dc33e05fec64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144040940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1144040940
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.263910863
Short name T866
Test name
Test status
Simulation time 112291701 ps
CPU time 4.04 seconds
Started Mar 24 12:35:54 PM PDT 24
Finished Mar 24 12:35:59 PM PDT 24
Peak memory 214760 kb
Host smart-3e9742e0-af75-42f7-b68a-a5bd22ac7e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263910863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.263910863
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2127207184
Short name T248
Test name
Test status
Simulation time 424884496 ps
CPU time 2.5 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 206340 kb
Host smart-8c9d12fd-2733-4d87-b9d7-e1fa32c64603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127207184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2127207184
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3922867120
Short name T844
Test name
Test status
Simulation time 25675620 ps
CPU time 1.34 seconds
Started Mar 24 12:35:37 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 214656 kb
Host smart-4303d014-e957-415b-9314-527d890e2d2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922867120 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3922867120
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.805465153
Short name T222
Test name
Test status
Simulation time 14814361 ps
CPU time 0.93 seconds
Started Mar 24 12:35:46 PM PDT 24
Finished Mar 24 12:35:47 PM PDT 24
Peak memory 206200 kb
Host smart-3aa0e1dc-1357-4bec-b19b-e9ee2d29ec2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805465153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.805465153
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.91599330
Short name T842
Test name
Test status
Simulation time 41410769 ps
CPU time 0.8 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206212 kb
Host smart-2a5d214f-6dd8-4e71-bb32-c9c77f52e9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91599330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.91599330
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.627583620
Short name T219
Test name
Test status
Simulation time 31879593 ps
CPU time 1.28 seconds
Started Mar 24 12:35:26 PM PDT 24
Finished Mar 24 12:35:28 PM PDT 24
Peak memory 206416 kb
Host smart-7e5d9706-20ba-4dd8-9d6c-74036aa8f7f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627583620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.627583620
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3112739308
Short name T964
Test name
Test status
Simulation time 49530083 ps
CPU time 2.28 seconds
Started Mar 24 12:35:37 PM PDT 24
Finished Mar 24 12:35:45 PM PDT 24
Peak memory 214612 kb
Host smart-4cfd75e5-6d6e-459d-b20d-bed2a9a59e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112739308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3112739308
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2872110335
Short name T933
Test name
Test status
Simulation time 111139405 ps
CPU time 2.67 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 206424 kb
Host smart-130ff288-8755-4a33-8b77-0a19d55bb0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872110335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2872110335
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3847034022
Short name T900
Test name
Test status
Simulation time 453255023 ps
CPU time 1.74 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 214600 kb
Host smart-d114d2b1-10d8-4417-afce-5644c0fb1b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847034022 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3847034022
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3102727739
Short name T239
Test name
Test status
Simulation time 67764038 ps
CPU time 0.84 seconds
Started Mar 24 12:35:21 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 206264 kb
Host smart-fc8efd35-d394-4a03-9afa-39be61cf61af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102727739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3102727739
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2642886406
Short name T857
Test name
Test status
Simulation time 20775512 ps
CPU time 0.78 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 206212 kb
Host smart-5837c073-e9c0-42f5-af10-37c4b18f4d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642886406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2642886406
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3715615679
Short name T963
Test name
Test status
Simulation time 42799040 ps
CPU time 1.08 seconds
Started Mar 24 12:35:32 PM PDT 24
Finished Mar 24 12:35:34 PM PDT 24
Peak memory 206340 kb
Host smart-cc255394-b41f-41b0-8267-3e5ba063a6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715615679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3715615679
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1350937433
Short name T863
Test name
Test status
Simulation time 65279112 ps
CPU time 2.25 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:40 PM PDT 24
Peak memory 214612 kb
Host smart-8a9df48b-8485-4728-bee0-480ff80eeeb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350937433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1350937433
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4037025280
Short name T258
Test name
Test status
Simulation time 50969782 ps
CPU time 1.58 seconds
Started Mar 24 12:35:49 PM PDT 24
Finished Mar 24 12:35:50 PM PDT 24
Peak memory 206320 kb
Host smart-75abdb61-964f-4859-9346-aebd840ab0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037025280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4037025280
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1848055126
Short name T904
Test name
Test status
Simulation time 22308329 ps
CPU time 1.1 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:03 PM PDT 24
Peak memory 214676 kb
Host smart-1c9cdfe4-e9fd-40d2-ac33-64b29641ef5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848055126 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1848055126
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2034122683
Short name T240
Test name
Test status
Simulation time 50447684 ps
CPU time 0.91 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 206196 kb
Host smart-18fb83d0-5d3d-416c-8b82-575cba9a4aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034122683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2034122683
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3784274620
Short name T909
Test name
Test status
Simulation time 55386960 ps
CPU time 0.95 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 206216 kb
Host smart-aaf4a000-7dcb-458f-9bac-2fb7d76b7c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784274620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3784274620
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3963777811
Short name T955
Test name
Test status
Simulation time 161041219 ps
CPU time 1.32 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:03 PM PDT 24
Peak memory 206384 kb
Host smart-5e5b8071-a2d9-4e26-81d5-8e4736690dc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963777811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3963777811
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3464431327
Short name T898
Test name
Test status
Simulation time 387320533 ps
CPU time 2.38 seconds
Started Mar 24 12:35:36 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 214824 kb
Host smart-2ca09a85-087a-4c5a-9c3b-5733ea0d86e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464431327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3464431327
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3180949266
Short name T908
Test name
Test status
Simulation time 171262339 ps
CPU time 1.6 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 206368 kb
Host smart-b75bf15a-7eb2-47d6-bd93-00787f55444b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180949266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3180949266
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.593448313
Short name T151
Test name
Test status
Simulation time 23388239 ps
CPU time 1.23 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 215836 kb
Host smart-3c40ce78-0255-4013-86f5-215da2751f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593448313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.593448313
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2918023532
Short name T391
Test name
Test status
Simulation time 18732352 ps
CPU time 1.01 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 207004 kb
Host smart-b7d8bad1-ab87-4334-ae5f-2094632028c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918023532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2918023532
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.120950585
Short name T657
Test name
Test status
Simulation time 87901174 ps
CPU time 1.09 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 216668 kb
Host smart-d6e40a71-ee87-462e-8082-e44d3bbc56cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120950585 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.120950585
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1027579271
Short name T109
Test name
Test status
Simulation time 20240026 ps
CPU time 1.1 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 218200 kb
Host smart-1b77b93a-e5a8-4339-9543-eac4c0864edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027579271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1027579271
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3688346537
Short name T312
Test name
Test status
Simulation time 39667414 ps
CPU time 1.45 seconds
Started Mar 24 01:05:16 PM PDT 24
Finished Mar 24 01:05:20 PM PDT 24
Peak memory 218240 kb
Host smart-fca3e647-21b2-418f-9755-185845cc9e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688346537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3688346537
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2427121973
Short name T561
Test name
Test status
Simulation time 23272914 ps
CPU time 1.06 seconds
Started Mar 24 01:05:17 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 215708 kb
Host smart-8f3c4c4b-2c47-4ab7-bd6f-347ed9ac6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427121973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2427121973
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1957899749
Short name T137
Test name
Test status
Simulation time 26410165 ps
CPU time 0.94 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 207208 kb
Host smart-b23d6ca5-f8cc-434e-95cb-a84fe427ffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957899749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1957899749
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3539436426
Short name T317
Test name
Test status
Simulation time 20204962 ps
CPU time 0.97 seconds
Started Mar 24 01:05:19 PM PDT 24
Finished Mar 24 01:05:20 PM PDT 24
Peak memory 215444 kb
Host smart-3e22b1ed-245a-4e03-b0a1-a7f6df465314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539436426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3539436426
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3254409573
Short name T715
Test name
Test status
Simulation time 282566619 ps
CPU time 5.95 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:24 PM PDT 24
Peak memory 215436 kb
Host smart-115f2fe0-ab74-48dc-8cda-02387d37bfbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254409573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3254409573
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.657649007
Short name T821
Test name
Test status
Simulation time 25178041257 ps
CPU time 547 seconds
Started Mar 24 01:05:19 PM PDT 24
Finished Mar 24 01:14:26 PM PDT 24
Peak memory 221300 kb
Host smart-46f208e9-71d4-4919-805f-6dcae6c53c56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657649007 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.657649007
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2207991094
Short name T590
Test name
Test status
Simulation time 271294905 ps
CPU time 1.38 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215708 kb
Host smart-b8a08d0b-1bf9-4f9c-a8bc-b592eeda4540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207991094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2207991094
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3181043033
Short name T771
Test name
Test status
Simulation time 34203685 ps
CPU time 1.19 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 206304 kb
Host smart-807f3fce-b5e5-4b75-8edc-18ed8addd9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181043033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3181043033
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1657782254
Short name T720
Test name
Test status
Simulation time 60439142 ps
CPU time 0.86 seconds
Started Mar 24 01:05:24 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215640 kb
Host smart-b367d2a0-fde8-4620-bb48-e244a8cf318c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657782254 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1657782254
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.4265075024
Short name T86
Test name
Test status
Simulation time 32719543 ps
CPU time 1.13 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 220088 kb
Host smart-70811f0a-8bf0-4818-8f81-717f40e62ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265075024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4265075024
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1511613888
Short name T295
Test name
Test status
Simulation time 55374883 ps
CPU time 2 seconds
Started Mar 24 01:05:17 PM PDT 24
Finished Mar 24 01:05:20 PM PDT 24
Peak memory 216744 kb
Host smart-e770fee0-3b12-4898-bb8a-86974130f4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511613888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1511613888
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3175879944
Short name T140
Test name
Test status
Simulation time 21968437 ps
CPU time 1.1 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 215872 kb
Host smart-aa69ab28-550e-41d0-af38-01b8a70f6b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175879944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3175879944
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.1131037036
Short name T747
Test name
Test status
Simulation time 18149512 ps
CPU time 1.06 seconds
Started Mar 24 01:05:22 PM PDT 24
Finished Mar 24 01:05:23 PM PDT 24
Peak memory 215404 kb
Host smart-2a125ded-56bb-46bf-8c2a-6f869ddf43b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131037036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1131037036
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1639955343
Short name T640
Test name
Test status
Simulation time 78468431 ps
CPU time 2.04 seconds
Started Mar 24 01:05:17 PM PDT 24
Finished Mar 24 01:05:20 PM PDT 24
Peak memory 216884 kb
Host smart-3d66e905-b8ec-41c0-b0ed-2b505a02a387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639955343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1639955343
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.706282810
Short name T654
Test name
Test status
Simulation time 27851986097 ps
CPU time 304.64 seconds
Started Mar 24 01:05:21 PM PDT 24
Finished Mar 24 01:10:25 PM PDT 24
Peak memory 218868 kb
Host smart-151dfe2c-0204-4535-8a27-a7dd05dd6506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706282810 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.706282810
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2384226498
Short name T642
Test name
Test status
Simulation time 30976217 ps
CPU time 1.27 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 215748 kb
Host smart-bd3dbf9e-672a-407c-ae86-dd2028419abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384226498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2384226498
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1774798854
Short name T574
Test name
Test status
Simulation time 27255824 ps
CPU time 0.9 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 206544 kb
Host smart-b102b704-e681-4f3c-a80f-8ea62bd8b408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774798854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1774798854
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.390820358
Short name T77
Test name
Test status
Simulation time 122169048 ps
CPU time 1.23 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 216660 kb
Host smart-9e6681ec-9365-420f-874c-c7603d0d0ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390820358 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.390820358
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2199378868
Short name T505
Test name
Test status
Simulation time 51231387 ps
CPU time 0.82 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 217628 kb
Host smart-356474a7-a555-4062-a520-40175605e99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199378868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2199378868
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1869651422
Short name T728
Test name
Test status
Simulation time 312832059 ps
CPU time 1.6 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:49 PM PDT 24
Peak memory 218304 kb
Host smart-b8de3c4f-1233-4398-8432-9fd8744ab9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869651422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1869651422
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.960141630
Short name T405
Test name
Test status
Simulation time 29578190 ps
CPU time 0.94 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 215388 kb
Host smart-8d36a62d-59ae-4f7c-a634-1638baaf156d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960141630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.960141630
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3617563073
Short name T613
Test name
Test status
Simulation time 238732386 ps
CPU time 4.87 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:50 PM PDT 24
Peak memory 219512 kb
Host smart-2450a8fe-b4eb-4933-aca5-07767a4c2d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617563073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3617563073
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4123844135
Short name T500
Test name
Test status
Simulation time 59331358544 ps
CPU time 1500.64 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:30:47 PM PDT 24
Peak memory 223172 kb
Host smart-d0d84c86-a4cf-40b2-a193-3472a580fa67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123844135 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4123844135
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3781323846
Short name T187
Test name
Test status
Simulation time 84424006 ps
CPU time 1.25 seconds
Started Mar 24 01:07:18 PM PDT 24
Finished Mar 24 01:07:19 PM PDT 24
Peak memory 218016 kb
Host smart-ab6503ca-3e52-4269-bccd-8488b0fdfa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781323846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3781323846
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.195049886
Short name T663
Test name
Test status
Simulation time 29586931 ps
CPU time 1.4 seconds
Started Mar 24 01:07:20 PM PDT 24
Finished Mar 24 01:07:23 PM PDT 24
Peak memory 216884 kb
Host smart-f701e357-5633-4416-920e-572eb409e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195049886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.195049886
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3282949517
Short name T428
Test name
Test status
Simulation time 230712210 ps
CPU time 2.6 seconds
Started Mar 24 01:07:20 PM PDT 24
Finished Mar 24 01:07:24 PM PDT 24
Peak memory 216972 kb
Host smart-70145aab-6854-497a-95ee-8418a03b17c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282949517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3282949517
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3443762489
Short name T517
Test name
Test status
Simulation time 53245308 ps
CPU time 1.22 seconds
Started Mar 24 01:07:18 PM PDT 24
Finished Mar 24 01:07:19 PM PDT 24
Peak memory 216812 kb
Host smart-a85d57ea-c12a-483e-bc0e-92e4fdae8f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443762489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3443762489
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1467906333
Short name T513
Test name
Test status
Simulation time 68577156 ps
CPU time 1.45 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 217848 kb
Host smart-f47dd703-8793-43e2-bbd3-630a700de968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467906333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1467906333
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2462809886
Short name T688
Test name
Test status
Simulation time 121405313 ps
CPU time 1.72 seconds
Started Mar 24 01:07:25 PM PDT 24
Finished Mar 24 01:07:27 PM PDT 24
Peak memory 216980 kb
Host smart-a9bf6dc9-ac68-4bdd-85be-a7e6df416516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462809886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2462809886
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1785835361
Short name T652
Test name
Test status
Simulation time 78515607 ps
CPU time 1.14 seconds
Started Mar 24 01:07:27 PM PDT 24
Finished Mar 24 01:07:29 PM PDT 24
Peak memory 216736 kb
Host smart-a590978b-3122-413e-9968-e32b6b3d0131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785835361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1785835361
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3686955247
Short name T492
Test name
Test status
Simulation time 50704662 ps
CPU time 1.14 seconds
Started Mar 24 01:07:23 PM PDT 24
Finished Mar 24 01:07:24 PM PDT 24
Peak memory 216732 kb
Host smart-972a4b6e-5d45-4b37-984b-3c7ca618e921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686955247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3686955247
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.891667006
Short name T527
Test name
Test status
Simulation time 43646140 ps
CPU time 1.65 seconds
Started Mar 24 01:07:27 PM PDT 24
Finished Mar 24 01:07:29 PM PDT 24
Peak memory 218116 kb
Host smart-bc3b5df4-eaa5-4db0-a9f9-cecfc0e64e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891667006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.891667006
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1034533986
Short name T488
Test name
Test status
Simulation time 54594560 ps
CPU time 0.8 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 206708 kb
Host smart-072961f2-acc7-4684-bf99-d406a6a7a57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034533986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1034533986
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3918876506
Short name T96
Test name
Test status
Simulation time 22893725 ps
CPU time 1 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 215760 kb
Host smart-0c2beabd-7297-45d9-ad4d-9a1afaa20e45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918876506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3918876506
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.1084533075
Short name T176
Test name
Test status
Simulation time 53539127 ps
CPU time 0.83 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 215440 kb
Host smart-dc0a395d-e479-44c2-8bc4-8ebad62355aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084533075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1084533075
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.4105936002
Short name T463
Test name
Test status
Simulation time 33851547 ps
CPU time 1.4 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 217580 kb
Host smart-7a8ea004-fce9-48c9-8149-ae923f52a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105936002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4105936002
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1305296068
Short name T45
Test name
Test status
Simulation time 24633159 ps
CPU time 1.05 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 224112 kb
Host smart-0502e1db-64d8-4528-9c73-a306cdc1842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305296068 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1305296068
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3381580825
Short name T423
Test name
Test status
Simulation time 235871427 ps
CPU time 0.96 seconds
Started Mar 24 01:05:48 PM PDT 24
Finished Mar 24 01:05:49 PM PDT 24
Peak memory 215388 kb
Host smart-ceb598d4-d473-4e44-bb75-901be3651af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381580825 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3381580825
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.549729652
Short name T683
Test name
Test status
Simulation time 179298978 ps
CPU time 2.48 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 216488 kb
Host smart-5536af05-c4cc-4b00-bd25-79a198531488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549729652 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.549729652
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1292241937
Short name T429
Test name
Test status
Simulation time 55010683225 ps
CPU time 1370.16 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:28:37 PM PDT 24
Peak memory 223844 kb
Host smart-d31ac952-5043-4ec5-938e-5464a94ffd1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292241937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1292241937
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1706361617
Short name T421
Test name
Test status
Simulation time 33305328 ps
CPU time 1.22 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:30 PM PDT 24
Peak memory 216532 kb
Host smart-5b2f29ac-332c-4107-baaa-00dbfd903ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706361617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1706361617
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.889440765
Short name T456
Test name
Test status
Simulation time 53840829 ps
CPU time 1.24 seconds
Started Mar 24 01:07:25 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 216704 kb
Host smart-a6661930-83a8-47bd-ad16-9ebdb130e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889440765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.889440765
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2340738990
Short name T281
Test name
Test status
Simulation time 110358490 ps
CPU time 1.13 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 218468 kb
Host smart-427185cd-df03-4c55-9d6b-bdbdd37f3751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340738990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2340738990
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3148670888
Short name T580
Test name
Test status
Simulation time 39018137 ps
CPU time 1.58 seconds
Started Mar 24 01:07:33 PM PDT 24
Finished Mar 24 01:07:35 PM PDT 24
Peak memory 217828 kb
Host smart-e9f9f8b7-8cc0-4e62-a77d-7e334a2aec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148670888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3148670888
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2989963208
Short name T696
Test name
Test status
Simulation time 62916169 ps
CPU time 1.29 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 216572 kb
Host smart-15abf894-bc99-4aee-803f-92c128f607c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989963208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2989963208
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1240272021
Short name T679
Test name
Test status
Simulation time 35630121 ps
CPU time 1.05 seconds
Started Mar 24 01:07:25 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 216988 kb
Host smart-8833d2af-5dab-4e8e-bd45-ab033e55f8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240272021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1240272021
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.4083569105
Short name T471
Test name
Test status
Simulation time 35157777 ps
CPU time 1.36 seconds
Started Mar 24 01:07:26 PM PDT 24
Finished Mar 24 01:07:27 PM PDT 24
Peak memory 216832 kb
Host smart-6a18953c-2e6b-48ee-b39b-83c0e0f68cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083569105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4083569105
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3089925066
Short name T462
Test name
Test status
Simulation time 42254560 ps
CPU time 1.6 seconds
Started Mar 24 01:07:27 PM PDT 24
Finished Mar 24 01:07:29 PM PDT 24
Peak memory 218068 kb
Host smart-7c2551f4-e450-44e1-b964-2390b414564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089925066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3089925066
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.4037471586
Short name T282
Test name
Test status
Simulation time 51876152 ps
CPU time 1.88 seconds
Started Mar 24 01:07:24 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 217844 kb
Host smart-22e84a61-1315-4d3a-ace7-bf3b30bee0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037471586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4037471586
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2746289360
Short name T431
Test name
Test status
Simulation time 27334798 ps
CPU time 0.87 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:52 PM PDT 24
Peak memory 206972 kb
Host smart-e4ae2389-7a58-4865-9a6e-25384185fc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746289360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2746289360
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.372738664
Short name T515
Test name
Test status
Simulation time 21546290 ps
CPU time 0.9 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 216072 kb
Host smart-825fb399-594f-41b9-b1e0-5939012ab3fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372738664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.372738664
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1341340977
Short name T651
Test name
Test status
Simulation time 25901831 ps
CPU time 0.97 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 232388 kb
Host smart-6c277ce9-90d9-4f80-b35d-aafe1aaffcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341340977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1341340977
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1059293372
Short name T364
Test name
Test status
Simulation time 4592684685 ps
CPU time 91.06 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:07:27 PM PDT 24
Peak memory 220184 kb
Host smart-85f7a412-fadb-4421-b24a-ba26832aeeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059293372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1059293372
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2655454914
Short name T141
Test name
Test status
Simulation time 34094423 ps
CPU time 0.84 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:50 PM PDT 24
Peak memory 215604 kb
Host smart-34cfbf05-40b0-4eaa-a9c5-47dc6e039a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655454914 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2655454914
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1563770443
Short name T636
Test name
Test status
Simulation time 68614053 ps
CPU time 0.89 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:52 PM PDT 24
Peak memory 215420 kb
Host smart-79a41290-bf4a-4f6d-ab84-5ec88b2158cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563770443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1563770443
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3397153311
Short name T374
Test name
Test status
Simulation time 370811093 ps
CPU time 3.56 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:55 PM PDT 24
Peak memory 216480 kb
Host smart-52789837-8f60-467d-935f-2006c7aa52b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397153311 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3397153311
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2421587697
Short name T192
Test name
Test status
Simulation time 51233879916 ps
CPU time 1280.68 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:27:12 PM PDT 24
Peak memory 223008 kb
Host smart-bfae2136-8b0c-4c17-ba52-b9ddb78de9cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421587697 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2421587697
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2000292603
Short name T508
Test name
Test status
Simulation time 580988696 ps
CPU time 4.42 seconds
Started Mar 24 01:07:27 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 216856 kb
Host smart-c4ae2cf0-8735-4d5b-8d20-77abee56efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000292603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2000292603
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1435586627
Short name T820
Test name
Test status
Simulation time 141302001 ps
CPU time 2.2 seconds
Started Mar 24 01:07:26 PM PDT 24
Finished Mar 24 01:07:28 PM PDT 24
Peak memory 216956 kb
Host smart-68c515c3-abb1-427c-a553-46b99b81f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435586627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1435586627
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1780207494
Short name T703
Test name
Test status
Simulation time 920578904 ps
CPU time 7.23 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 219668 kb
Host smart-4328c78a-7ba8-4a29-8337-6d23eeb46028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780207494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1780207494
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1845069188
Short name T146
Test name
Test status
Simulation time 63029518 ps
CPU time 1.05 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 216680 kb
Host smart-006f7849-4b91-49b2-9c89-8368c2b4a20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845069188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1845069188
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1829351279
Short name T758
Test name
Test status
Simulation time 42628303 ps
CPU time 1.64 seconds
Started Mar 24 01:07:24 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 216944 kb
Host smart-5dca94b5-5633-4b61-bca9-d25ff78c49a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829351279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1829351279
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3383107401
Short name T792
Test name
Test status
Simulation time 77119913 ps
CPU time 2.71 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 219616 kb
Host smart-2159bbdd-e2ab-4228-976a-efa38c3b1f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383107401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3383107401
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.367564807
Short name T297
Test name
Test status
Simulation time 21841050 ps
CPU time 1.16 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 216968 kb
Host smart-acffb51a-dc6e-4068-ac1c-6a4c2bcb340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367564807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.367564807
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2871112142
Short name T498
Test name
Test status
Simulation time 68168197 ps
CPU time 1.02 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 215464 kb
Host smart-ab6a7fb4-d769-4ac2-8c02-9e140d0cb06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871112142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2871112142
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3435982200
Short name T656
Test name
Test status
Simulation time 88445732 ps
CPU time 1.55 seconds
Started Mar 24 01:07:24 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 218272 kb
Host smart-3d9ff660-1691-4885-a49c-83008b0442e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435982200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3435982200
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3624204537
Short name T717
Test name
Test status
Simulation time 70914479 ps
CPU time 1.21 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 215780 kb
Host smart-0894e47a-ad48-4265-a238-2ca9b6d21333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624204537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3624204537
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1797683570
Short name T759
Test name
Test status
Simulation time 15187564 ps
CPU time 0.93 seconds
Started Mar 24 01:05:48 PM PDT 24
Finished Mar 24 01:05:49 PM PDT 24
Peak memory 206732 kb
Host smart-6dab1614-70cf-41be-b295-8974c28f62db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797683570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1797683570
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3226154278
Short name T749
Test name
Test status
Simulation time 20886064 ps
CPU time 0.88 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 216084 kb
Host smart-1d4e455e-f32c-4bd4-b567-4c1223364786
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226154278 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3226154278
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3943758699
Short name T470
Test name
Test status
Simulation time 261354018 ps
CPU time 1.14 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 217952 kb
Host smart-df315116-7640-4dcc-a83b-f7a3c77bf1d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943758699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3943758699
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2509148203
Short name T58
Test name
Test status
Simulation time 21754083 ps
CPU time 0.94 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 218000 kb
Host smart-50062b65-bcf7-44bb-8847-51122705f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509148203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2509148203
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2023597384
Short name T745
Test name
Test status
Simulation time 323651089 ps
CPU time 1.64 seconds
Started Mar 24 01:05:49 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 217036 kb
Host smart-f31aafc5-af14-48c6-935b-e882c594fa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023597384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2023597384
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3297419015
Short name T714
Test name
Test status
Simulation time 20674810 ps
CPU time 1.1 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:52 PM PDT 24
Peak memory 215844 kb
Host smart-1d6c412b-8752-40a1-b4ff-707409229e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297419015 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3297419015
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2716423904
Short name T348
Test name
Test status
Simulation time 15026867 ps
CPU time 0.96 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215528 kb
Host smart-6c63ae81-2d17-44a5-87a3-d3c1a1c32fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716423904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2716423904
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.804636684
Short name T572
Test name
Test status
Simulation time 2538817591 ps
CPU time 4.46 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:56 PM PDT 24
Peak memory 215664 kb
Host smart-28206048-8bab-4ff8-b324-ebc125178938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804636684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.804636684
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2132654937
Short name T697
Test name
Test status
Simulation time 73177628735 ps
CPU time 1635.58 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:33:06 PM PDT 24
Peak memory 223480 kb
Host smart-adb980ee-a7e6-4f80-ae36-7a5300815cda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132654937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2132654937
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.2827093275
Short name T422
Test name
Test status
Simulation time 107768532 ps
CPU time 2.41 seconds
Started Mar 24 01:07:33 PM PDT 24
Finished Mar 24 01:07:36 PM PDT 24
Peak memory 219628 kb
Host smart-ee0c60d6-cda5-457d-b756-19cdfa5b35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827093275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2827093275
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2126567191
Short name T149
Test name
Test status
Simulation time 48514404 ps
CPU time 1.09 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:36 PM PDT 24
Peak memory 216792 kb
Host smart-8ca49f21-da08-40c5-af55-f64dcad499ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126567191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2126567191
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1542738145
Short name T825
Test name
Test status
Simulation time 27873558 ps
CPU time 1.12 seconds
Started Mar 24 01:07:24 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 216572 kb
Host smart-097d6ba2-99f9-44a7-9d16-9097dd7a9176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542738145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1542738145
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.667427596
Short name T209
Test name
Test status
Simulation time 42256409 ps
CPU time 1.55 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 218056 kb
Host smart-6ab0faa0-e2c0-43e3-925f-fecbf7b47fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667427596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.667427596
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2086325881
Short name T285
Test name
Test status
Simulation time 81672197 ps
CPU time 2.54 seconds
Started Mar 24 01:07:25 PM PDT 24
Finished Mar 24 01:07:28 PM PDT 24
Peak memory 219036 kb
Host smart-3d73af33-4e02-4218-a1f2-6646f43c212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086325881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2086325881
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2423413728
Short name T723
Test name
Test status
Simulation time 54143295 ps
CPU time 1.6 seconds
Started Mar 24 01:07:23 PM PDT 24
Finished Mar 24 01:07:24 PM PDT 24
Peak memory 217716 kb
Host smart-0d51a156-ea75-447c-9644-ac3cbe8478ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423413728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2423413728
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1315300360
Short name T189
Test name
Test status
Simulation time 108082099 ps
CPU time 1.28 seconds
Started Mar 24 01:07:25 PM PDT 24
Finished Mar 24 01:07:26 PM PDT 24
Peak memory 217032 kb
Host smart-e466f72b-9bd7-48e4-8ea4-df7f675323d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315300360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1315300360
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3685147092
Short name T837
Test name
Test status
Simulation time 34037538 ps
CPU time 1.35 seconds
Started Mar 24 01:05:53 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 216016 kb
Host smart-16f655de-fefe-4e1c-98b2-6a5fc3f09cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685147092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3685147092
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3675434228
Short name T530
Test name
Test status
Simulation time 57880807 ps
CPU time 1.08 seconds
Started Mar 24 01:05:49 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 216720 kb
Host smart-80bbf289-72eb-4c30-ab6a-90708594ae1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675434228 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3675434228
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.756511577
Short name T797
Test name
Test status
Simulation time 19524156 ps
CPU time 1.05 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 217960 kb
Host smart-2ba06a33-b358-492f-9d3d-c227858199a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756511577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.756511577
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1167084736
Short name T806
Test name
Test status
Simulation time 45289234 ps
CPU time 1.49 seconds
Started Mar 24 01:05:49 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 216916 kb
Host smart-7e516d76-a7f0-44b5-8f83-8645f6e7df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167084736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1167084736
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.137636255
Short name T142
Test name
Test status
Simulation time 19574397 ps
CPU time 1.15 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 215884 kb
Host smart-73549fa5-bffe-4076-95dd-f0d7296c4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137636255 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.137636255
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.769303128
Short name T543
Test name
Test status
Simulation time 44486496 ps
CPU time 0.9 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:05:52 PM PDT 24
Peak memory 215480 kb
Host smart-a349e286-7a8a-4656-8d3f-c7b5ddb0ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769303128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.769303128
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2538729975
Short name T774
Test name
Test status
Simulation time 493445353 ps
CPU time 6.48 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215396 kb
Host smart-d351696b-50d3-4adc-9699-465e424c979b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538729975 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2538729975
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3978819554
Short name T615
Test name
Test status
Simulation time 234011011050 ps
CPU time 1191.17 seconds
Started Mar 24 01:05:51 PM PDT 24
Finished Mar 24 01:25:43 PM PDT 24
Peak memory 224132 kb
Host smart-a6fd0951-9e46-4a29-9905-6ec15e6f40df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978819554 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3978819554
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.972952219
Short name T473
Test name
Test status
Simulation time 112112216 ps
CPU time 2.53 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 219824 kb
Host smart-7ab20452-1033-4a51-b81d-1c27161b1d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972952219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.972952219
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2105913338
Short name T742
Test name
Test status
Simulation time 99499731 ps
CPU time 1.66 seconds
Started Mar 24 01:07:33 PM PDT 24
Finished Mar 24 01:07:35 PM PDT 24
Peak memory 218232 kb
Host smart-35496e60-c4f7-40d6-88eb-59a7c92deb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105913338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2105913338
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.150590998
Short name T548
Test name
Test status
Simulation time 26490402 ps
CPU time 1.18 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 219456 kb
Host smart-5fdc2ab7-0708-4391-9fdc-e5506d8526a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150590998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.150590998
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1626014230
Short name T328
Test name
Test status
Simulation time 39049635 ps
CPU time 1.06 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 216884 kb
Host smart-b0bbf708-8fdb-402d-925d-eae54b72b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626014230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1626014230
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.343634809
Short name T292
Test name
Test status
Simulation time 95361102 ps
CPU time 1.9 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 218268 kb
Host smart-87d2a8db-e89e-4700-be20-6d4322fcaefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343634809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.343634809
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.559599164
Short name T278
Test name
Test status
Simulation time 303639242 ps
CPU time 3.83 seconds
Started Mar 24 01:07:28 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 216956 kb
Host smart-504432d8-488c-4f64-97ba-f1e41aed0288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559599164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.559599164
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2619189754
Short name T289
Test name
Test status
Simulation time 48722492 ps
CPU time 2.01 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:40 PM PDT 24
Peak memory 217876 kb
Host smart-5ccc87a7-6b5c-48f9-8603-006c9b0e1bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619189754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2619189754
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.843666046
Short name T279
Test name
Test status
Simulation time 97159926 ps
CPU time 1.53 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 218616 kb
Host smart-611d222f-7916-41a6-a5fe-88e48269d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843666046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.843666046
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1867891350
Short name T489
Test name
Test status
Simulation time 64968465 ps
CPU time 1.24 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 219308 kb
Host smart-a1123259-d44e-40d3-9dc8-4c699bb47d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867891350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1867891350
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.825105666
Short name T713
Test name
Test status
Simulation time 35742835 ps
CPU time 1.12 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215808 kb
Host smart-f5e1e124-dc51-4abd-a2e1-b11ed6b251be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825105666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.825105666
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2351255849
Short name T369
Test name
Test status
Simulation time 57958867 ps
CPU time 0.94 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 207020 kb
Host smart-2ff17aac-d2df-429d-a70f-ac1cab2eb167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351255849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2351255849
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4104735370
Short name T178
Test name
Test status
Simulation time 18615626 ps
CPU time 0.84 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 216076 kb
Host smart-c6d4f11d-bd8f-41c6-aa5b-79cd43fe47cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104735370 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4104735370
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1186351309
Short name T478
Test name
Test status
Simulation time 24279984 ps
CPU time 0.94 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 218344 kb
Host smart-94b65d93-5033-459f-b004-98b7a6dbee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186351309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1186351309
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.225213434
Short name T133
Test name
Test status
Simulation time 58228120 ps
CPU time 0.85 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215672 kb
Host smart-8398ad9c-d60d-487d-861b-5621b82dca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225213434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.225213434
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1245165871
Short name T357
Test name
Test status
Simulation time 44325439 ps
CPU time 0.97 seconds
Started Mar 24 01:05:50 PM PDT 24
Finished Mar 24 01:05:51 PM PDT 24
Peak memory 207088 kb
Host smart-a50f2671-3a90-4558-84dd-a6738ce05aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245165871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1245165871
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1035170675
Short name T41
Test name
Test status
Simulation time 935754632 ps
CPU time 2.51 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:59 PM PDT 24
Peak memory 216840 kb
Host smart-3007eade-1d7a-43c2-a55a-f4f4e7a462ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035170675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1035170675
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.624529947
Short name T563
Test name
Test status
Simulation time 15065737933 ps
CPU time 318.05 seconds
Started Mar 24 01:06:05 PM PDT 24
Finished Mar 24 01:11:24 PM PDT 24
Peak memory 220456 kb
Host smart-cfcde755-b0a3-4f06-8730-fa6a537c5841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624529947 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.624529947
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3235022482
Short name T332
Test name
Test status
Simulation time 72777042 ps
CPU time 2.56 seconds
Started Mar 24 01:07:33 PM PDT 24
Finished Mar 24 01:07:36 PM PDT 24
Peak memory 219520 kb
Host smart-4c065b50-c9a8-4493-bec1-466a4bfa44fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235022482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3235022482
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1622848967
Short name T719
Test name
Test status
Simulation time 127737018 ps
CPU time 1.05 seconds
Started Mar 24 01:07:31 PM PDT 24
Finished Mar 24 01:07:33 PM PDT 24
Peak memory 216600 kb
Host smart-af152ccb-3876-4019-80d4-149b7986289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622848967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1622848967
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3041863226
Short name T571
Test name
Test status
Simulation time 119877954 ps
CPU time 2.88 seconds
Started Mar 24 01:07:31 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 219608 kb
Host smart-2f3b1189-1046-46e8-b752-164709f51690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041863226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3041863226
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3388053631
Short name T777
Test name
Test status
Simulation time 93896704 ps
CPU time 1.65 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 217944 kb
Host smart-9151405d-2c7b-42ea-a2ee-cfec65943286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388053631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3388053631
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2982798324
Short name T300
Test name
Test status
Simulation time 61713118 ps
CPU time 2.32 seconds
Started Mar 24 01:07:31 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 218512 kb
Host smart-3143cd1e-da1a-40b2-b24f-97d47a3d7cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982798324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2982798324
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1734384262
Short name T438
Test name
Test status
Simulation time 42253617 ps
CPU time 1.49 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 217908 kb
Host smart-e6c812de-1b37-4005-973a-155ae3e7a14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734384262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1734384262
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1180709827
Short name T834
Test name
Test status
Simulation time 43965505 ps
CPU time 1.18 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 216840 kb
Host smart-465ef8f5-df26-4d9b-98b9-5c741bf9b318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180709827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1180709827
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.969964178
Short name T11
Test name
Test status
Simulation time 46837035 ps
CPU time 1.18 seconds
Started Mar 24 01:07:32 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 217152 kb
Host smart-ebcab699-7d85-4e2d-a8c5-f5a81ace42ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969964178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.969964178
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3521329087
Short name T51
Test name
Test status
Simulation time 43810924 ps
CPU time 1.41 seconds
Started Mar 24 01:07:31 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 217740 kb
Host smart-dad8df61-45cc-412e-a7cf-0caa4ab07e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521329087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3521329087
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2294789777
Short name T150
Test name
Test status
Simulation time 91952670 ps
CPU time 1.29 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 215764 kb
Host smart-004becbd-7d39-4fad-baed-c6dd208fcca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294789777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2294789777
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.931423233
Short name T20
Test name
Test status
Simulation time 34023404 ps
CPU time 0.83 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 205916 kb
Host smart-cd427776-46e3-4694-bbde-787eae7ea51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931423233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.931423233
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3528694696
Short name T495
Test name
Test status
Simulation time 52316759 ps
CPU time 1.08 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 216484 kb
Host smart-dd1fd81a-119e-4bcc-9f74-6c6f7103a978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528694696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3528694696
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1556330007
Short name T66
Test name
Test status
Simulation time 24185379 ps
CPU time 1.07 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 219668 kb
Host smart-581cf2cd-e4a6-417e-a872-f3b2ab5a676b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556330007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1556330007
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.219866770
Short name T400
Test name
Test status
Simulation time 75414545 ps
CPU time 2.08 seconds
Started Mar 24 01:05:53 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 218104 kb
Host smart-5b644f3b-e684-4cd8-ad36-17e2fa394459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219866770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.219866770
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2901847730
Short name T804
Test name
Test status
Simulation time 24393091 ps
CPU time 1.1 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 224076 kb
Host smart-290bd98c-1ba6-4fcd-9e9e-64dec1aef382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901847730 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2901847730
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1181439107
Short name T801
Test name
Test status
Simulation time 176392416 ps
CPU time 0.94 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215208 kb
Host smart-34b79366-5de0-49ec-9d1f-18160d95f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181439107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1181439107
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.973309645
Short name T735
Test name
Test status
Simulation time 177300514 ps
CPU time 3.69 seconds
Started Mar 24 01:05:53 PM PDT 24
Finished Mar 24 01:06:00 PM PDT 24
Peak memory 219724 kb
Host smart-a984fa21-5396-4d4e-8f9f-c4e232d07dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973309645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.973309645
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.3874490416
Short name T824
Test name
Test status
Simulation time 98087888 ps
CPU time 1.34 seconds
Started Mar 24 01:07:34 PM PDT 24
Finished Mar 24 01:07:35 PM PDT 24
Peak memory 217868 kb
Host smart-5db7ab1c-415c-4f42-bd46-2557616480e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874490416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3874490416
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1292648002
Short name T551
Test name
Test status
Simulation time 63515826 ps
CPU time 2.49 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 217120 kb
Host smart-e48b1fc9-c5d1-4c30-8fd8-5be7e8f5796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292648002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1292648002
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2690948133
Short name T207
Test name
Test status
Simulation time 91611374 ps
CPU time 1.24 seconds
Started Mar 24 01:07:32 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 218100 kb
Host smart-8d39e3f8-808d-45e8-8319-dd4335ac327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690948133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2690948133
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.703710235
Short name T349
Test name
Test status
Simulation time 109513215 ps
CPU time 1.07 seconds
Started Mar 24 01:07:30 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 216692 kb
Host smart-b844d7da-1d8c-47e7-be4b-ce1075be1ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703710235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.703710235
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3778022504
Short name T619
Test name
Test status
Simulation time 193363732 ps
CPU time 1.53 seconds
Started Mar 24 01:07:31 PM PDT 24
Finished Mar 24 01:07:32 PM PDT 24
Peak memory 217000 kb
Host smart-2dd94e42-165d-4d93-8a4d-ee9ff452eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778022504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3778022504
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2163978425
Short name T2
Test name
Test status
Simulation time 43283031 ps
CPU time 1.47 seconds
Started Mar 24 01:07:32 PM PDT 24
Finished Mar 24 01:07:34 PM PDT 24
Peak memory 217836 kb
Host smart-64629062-4498-46ff-8f11-7c12dfcc8b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163978425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2163978425
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1860347419
Short name T62
Test name
Test status
Simulation time 55232267 ps
CPU time 1.27 seconds
Started Mar 24 01:07:29 PM PDT 24
Finished Mar 24 01:07:31 PM PDT 24
Peak memory 218540 kb
Host smart-c8db264c-1d58-4e6e-9ea2-0d7bf1ab9d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860347419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1860347419
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1284790333
Short name T629
Test name
Test status
Simulation time 43223805 ps
CPU time 1.38 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 217672 kb
Host smart-89d8ec50-51e6-49b6-a450-c9dbf039ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284790333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1284790333
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.295453706
Short name T677
Test name
Test status
Simulation time 64303906 ps
CPU time 1.33 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 216832 kb
Host smart-3ae2ccba-2056-42d0-aca3-99cfe8e0b173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295453706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.295453706
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1422965525
Short name T770
Test name
Test status
Simulation time 29860167 ps
CPU time 1.28 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 216104 kb
Host smart-d26882b4-4715-4d50-85d4-e120a07f1345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422965525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1422965525
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.891733639
Short name T398
Test name
Test status
Simulation time 134710595 ps
CPU time 0.88 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 206076 kb
Host smart-9b8110bb-e14c-419a-b9eb-c53019c1b0c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891733639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.891733639
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2290295881
Short name T120
Test name
Test status
Simulation time 16905697 ps
CPU time 0.83 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 215984 kb
Host smart-88697c01-9548-474f-ab6a-1fd37146f9d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290295881 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2290295881
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2243951688
Short name T330
Test name
Test status
Simulation time 54999461 ps
CPU time 1.24 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 217008 kb
Host smart-fd373919-5ac2-4571-bc8b-0f283068955b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243951688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2243951688
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3052961647
Short name T778
Test name
Test status
Simulation time 22997902 ps
CPU time 1.01 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 223092 kb
Host smart-515d50db-97d0-48aa-a9df-56b0a5ca22a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052961647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3052961647
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.878263639
Short name T334
Test name
Test status
Simulation time 208385298 ps
CPU time 1.82 seconds
Started Mar 24 01:06:03 PM PDT 24
Finished Mar 24 01:06:06 PM PDT 24
Peak memory 217924 kb
Host smart-eee518d3-5920-4f56-b214-92fd7d9fda15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878263639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.878263639
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.3087016659
Short name T684
Test name
Test status
Simulation time 33945419 ps
CPU time 0.87 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215388 kb
Host smart-aad851c6-0051-45bb-93a9-25fb5fdf3a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087016659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3087016659
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2340405717
Short name T785
Test name
Test status
Simulation time 868332781 ps
CPU time 5.29 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:06:02 PM PDT 24
Peak memory 215316 kb
Host smart-8a62dacc-c8c1-4657-8468-a73edb4d66f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340405717 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2340405717
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2052388784
Short name T191
Test name
Test status
Simulation time 142777744761 ps
CPU time 2300.74 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:44:17 PM PDT 24
Peak memory 227208 kb
Host smart-949c49b2-bda6-4409-9207-8bf157b78779
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052388784 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2052388784
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3341450412
Short name T794
Test name
Test status
Simulation time 51165845 ps
CPU time 1.31 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 219272 kb
Host smart-cec541e4-65aa-48b8-aad7-e2feac519f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341450412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3341450412
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3277794579
Short name T534
Test name
Test status
Simulation time 53102119 ps
CPU time 1.22 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 216700 kb
Host smart-5aaa8ca1-1001-4a07-b107-12237f7a7e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277794579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3277794579
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.24083283
Short name T474
Test name
Test status
Simulation time 45575209 ps
CPU time 1.62 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:39 PM PDT 24
Peak memory 217988 kb
Host smart-6560da95-957f-4af8-8161-a6efb68a1c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24083283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.24083283
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.756444837
Short name T664
Test name
Test status
Simulation time 70567172 ps
CPU time 1.43 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 216692 kb
Host smart-bfbd4571-062f-41ec-834b-a089a8ce33cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756444837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.756444837
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3044818018
Short name T566
Test name
Test status
Simulation time 37015869 ps
CPU time 1.49 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 217108 kb
Host smart-5b74334c-8392-4c7b-8341-9132e9d7bc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044818018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3044818018
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1282272279
Short name T559
Test name
Test status
Simulation time 41447143 ps
CPU time 1.46 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 217924 kb
Host smart-dbb16de5-3bd5-4688-8935-d6266a5517d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282272279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1282272279
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2873826969
Short name T685
Test name
Test status
Simulation time 96605354 ps
CPU time 1.41 seconds
Started Mar 24 01:07:37 PM PDT 24
Finished Mar 24 01:07:39 PM PDT 24
Peak memory 218012 kb
Host smart-f13ac1f9-ef63-4d62-93d5-2ec9d37c2fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873826969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2873826969
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.893711359
Short name T556
Test name
Test status
Simulation time 65495754 ps
CPU time 1.34 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 217936 kb
Host smart-93c15cf8-c2db-487c-83d4-6348ac6a6b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893711359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.893711359
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.663862768
Short name T823
Test name
Test status
Simulation time 109689254 ps
CPU time 1.03 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 216820 kb
Host smart-0586edb3-f7bd-4727-b804-26c14b8a2a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663862768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.663862768
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3723862588
Short name T579
Test name
Test status
Simulation time 33612163 ps
CPU time 1.43 seconds
Started Mar 24 01:07:40 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218184 kb
Host smart-2c5f3534-57c0-4735-abce-7989698f96d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723862588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3723862588
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.905657760
Short name T587
Test name
Test status
Simulation time 24379544 ps
CPU time 1.22 seconds
Started Mar 24 01:05:57 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 215744 kb
Host smart-33604733-5ca7-44a3-a8e0-ee0e9ada953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905657760 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.905657760
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1165558439
Short name T310
Test name
Test status
Simulation time 92220634 ps
CPU time 0.88 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 206184 kb
Host smart-c420032c-b158-48a8-b80b-63e19ff0061f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165558439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1165558439
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3826901101
Short name T94
Test name
Test status
Simulation time 11957257 ps
CPU time 0.9 seconds
Started Mar 24 01:05:58 PM PDT 24
Finished Mar 24 01:05:59 PM PDT 24
Peak memory 215724 kb
Host smart-e6629960-f6c7-4d90-a47b-3e694479f8c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826901101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3826901101
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.513045019
Short name T60
Test name
Test status
Simulation time 32880544 ps
CPU time 0.9 seconds
Started Mar 24 01:05:58 PM PDT 24
Finished Mar 24 01:05:59 PM PDT 24
Peak memory 217624 kb
Host smart-a7c56ae8-7339-494f-b850-06a116e5b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513045019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.513045019
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3102890600
Short name T764
Test name
Test status
Simulation time 31937174 ps
CPU time 1.3 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 216652 kb
Host smart-d86ecf6f-0853-4f06-b60b-189d54039c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102890600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3102890600
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3260205911
Short name T138
Test name
Test status
Simulation time 19254523 ps
CPU time 1.07 seconds
Started Mar 24 01:05:55 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215924 kb
Host smart-45728f65-e11b-49e4-b7eb-28e0b021fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260205911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3260205911
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3304084199
Short name T344
Test name
Test status
Simulation time 30103903 ps
CPU time 0.94 seconds
Started Mar 24 01:05:58 PM PDT 24
Finished Mar 24 01:05:59 PM PDT 24
Peak memory 215440 kb
Host smart-2e62816b-8529-4cff-9459-e65a602213f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304084199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3304084199
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2112313461
Short name T805
Test name
Test status
Simulation time 788410054 ps
CPU time 4.06 seconds
Started Mar 24 01:06:03 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 219832 kb
Host smart-64dcda87-e9de-44d1-a23e-34d49df4ca83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112313461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2112313461
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4151353033
Short name T204
Test name
Test status
Simulation time 72826009240 ps
CPU time 397.74 seconds
Started Mar 24 01:05:56 PM PDT 24
Finished Mar 24 01:12:34 PM PDT 24
Peak memory 217720 kb
Host smart-cb368c38-83e1-4fdf-9240-d47bc0fd410f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151353033 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4151353033
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.edn_genbits.2679691081
Short name T595
Test name
Test status
Simulation time 94842350 ps
CPU time 1.24 seconds
Started Mar 24 01:07:40 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218132 kb
Host smart-e50542dd-3c2e-4782-a919-0183b8e28170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679691081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2679691081
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3953444199
Short name T678
Test name
Test status
Simulation time 53123741 ps
CPU time 1.65 seconds
Started Mar 24 01:07:39 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 217988 kb
Host smart-4e82d830-1267-4664-aa1e-b2ecdb06647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953444199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3953444199
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3257726097
Short name T669
Test name
Test status
Simulation time 189225298 ps
CPU time 1.02 seconds
Started Mar 24 01:07:41 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216548 kb
Host smart-0f54b506-e866-416e-bead-1a150bb67e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257726097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3257726097
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3663894604
Short name T416
Test name
Test status
Simulation time 33315337 ps
CPU time 1.35 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 216900 kb
Host smart-288fe79a-9afe-4a58-996e-006e0394dab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663894604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3663894604
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.903467448
Short name T255
Test name
Test status
Simulation time 50980141 ps
CPU time 1.23 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216856 kb
Host smart-9b2cfcd1-4584-47e6-8c8f-bfc5e7175cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903467448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.903467448
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2982229297
Short name T593
Test name
Test status
Simulation time 45458864 ps
CPU time 1.57 seconds
Started Mar 24 01:07:39 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 217692 kb
Host smart-5dbe497e-1b85-4158-a116-1685fd2c38a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982229297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2982229297
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3884196731
Short name T385
Test name
Test status
Simulation time 62295548 ps
CPU time 1.1 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 216848 kb
Host smart-2a4ba921-2be9-4f0e-9718-7dcfe153c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884196731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3884196731
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2083456414
Short name T320
Test name
Test status
Simulation time 49793562 ps
CPU time 1.52 seconds
Started Mar 24 01:07:37 PM PDT 24
Finished Mar 24 01:07:39 PM PDT 24
Peak memory 215380 kb
Host smart-b9a4243c-d6ee-42b1-87c2-8ebeadf612be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083456414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2083456414
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.810943098
Short name T689
Test name
Test status
Simulation time 141383352 ps
CPU time 2.86 seconds
Started Mar 24 01:07:38 PM PDT 24
Finished Mar 24 01:07:42 PM PDT 24
Peak memory 219048 kb
Host smart-979376bc-3625-4b00-b4f2-8ef303987121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810943098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.810943098
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3367332086
Short name T708
Test name
Test status
Simulation time 23962965 ps
CPU time 1.22 seconds
Started Mar 24 01:06:02 PM PDT 24
Finished Mar 24 01:06:03 PM PDT 24
Peak memory 215808 kb
Host smart-dbcd3673-080f-41e7-866f-1a45965714e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367332086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3367332086
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3585194882
Short name T782
Test name
Test status
Simulation time 26194409 ps
CPU time 1.08 seconds
Started Mar 24 01:06:02 PM PDT 24
Finished Mar 24 01:06:04 PM PDT 24
Peak memory 206212 kb
Host smart-26ebe86f-6e97-4dc0-89d2-0a8576b1ed31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585194882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3585194882
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.3995978684
Short name T160
Test name
Test status
Simulation time 35289522 ps
CPU time 1.1 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 219496 kb
Host smart-41dd57b0-4eea-4fe8-be9a-5f2a473b9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995978684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3995978684
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3202957660
Short name T637
Test name
Test status
Simulation time 62251845 ps
CPU time 1.29 seconds
Started Mar 24 01:05:59 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 215432 kb
Host smart-ffe5876c-d520-48d4-8f5f-fb8d158187aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202957660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3202957660
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2815778055
Short name T143
Test name
Test status
Simulation time 27122991 ps
CPU time 1.02 seconds
Started Mar 24 01:06:02 PM PDT 24
Finished Mar 24 01:06:03 PM PDT 24
Peak memory 215712 kb
Host smart-19caf592-9a1a-480c-bd98-1172a1a3b6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815778055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2815778055
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1822453703
Short name T341
Test name
Test status
Simulation time 15527882 ps
CPU time 1 seconds
Started Mar 24 01:06:05 PM PDT 24
Finished Mar 24 01:06:07 PM PDT 24
Peak memory 215440 kb
Host smart-6d64de87-f658-4a61-9e0c-92fc6da78ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822453703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1822453703
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3712023486
Short name T305
Test name
Test status
Simulation time 1006005395 ps
CPU time 4.28 seconds
Started Mar 24 01:06:01 PM PDT 24
Finished Mar 24 01:06:05 PM PDT 24
Peak memory 219696 kb
Host smart-88352907-9fb9-4853-81a1-62897925b0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712023486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3712023486
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1344909073
Short name T457
Test name
Test status
Simulation time 213666673213 ps
CPU time 820.23 seconds
Started Mar 24 01:05:59 PM PDT 24
Finished Mar 24 01:19:40 PM PDT 24
Peak memory 221060 kb
Host smart-9a43ed69-7e63-4077-bdff-24365372279f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344909073 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1344909073
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.278274938
Short name T512
Test name
Test status
Simulation time 121290588 ps
CPU time 1.24 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 216656 kb
Host smart-1a19ee37-9080-475b-90b7-310ac6ee4870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278274938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.278274938
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1375925040
Short name T811
Test name
Test status
Simulation time 37940516 ps
CPU time 1.61 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 216896 kb
Host smart-e78f30fc-16e2-458d-b498-869392a74f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375925040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1375925040
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1558057396
Short name T329
Test name
Test status
Simulation time 62479469 ps
CPU time 1.56 seconds
Started Mar 24 01:07:39 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218240 kb
Host smart-ea070d53-0a98-43fd-96d3-2fb8769585ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558057396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1558057396
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3582064794
Short name T555
Test name
Test status
Simulation time 30507368 ps
CPU time 1.32 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216768 kb
Host smart-4bf03836-fc46-4e3c-be0f-d2cea2430bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582064794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3582064794
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3015900392
Short name T336
Test name
Test status
Simulation time 82897307 ps
CPU time 1.17 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 216796 kb
Host smart-2af1246e-e50e-4f26-b933-a6264ad95b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015900392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3015900392
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1191772240
Short name T701
Test name
Test status
Simulation time 58831782 ps
CPU time 1.13 seconds
Started Mar 24 01:07:40 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218356 kb
Host smart-1a784c12-a846-4718-9e55-7c8be9137085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191772240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1191772240
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2962953152
Short name T620
Test name
Test status
Simulation time 92614891 ps
CPU time 1.4 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 216792 kb
Host smart-0887234c-db56-41a6-a061-3bddd4354461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962953152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2962953152
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1162222502
Short name T536
Test name
Test status
Simulation time 194150381 ps
CPU time 1.34 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 218204 kb
Host smart-c2fead0a-d7cf-4955-9e2c-a305c2654b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162222502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1162222502
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.64587861
Short name T34
Test name
Test status
Simulation time 352650196 ps
CPU time 3.39 seconds
Started Mar 24 01:07:38 PM PDT 24
Finished Mar 24 01:07:43 PM PDT 24
Peak memory 219700 kb
Host smart-d72e2270-58be-476b-84f7-80ab86099e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64587861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.64587861
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.419486736
Short name T648
Test name
Test status
Simulation time 66969187 ps
CPU time 1.38 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 219184 kb
Host smart-2d09ba69-faa9-4539-86f1-84fe8db10750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419486736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.419486736
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.905731544
Short name T106
Test name
Test status
Simulation time 39728516 ps
CPU time 1.17 seconds
Started Mar 24 01:05:25 PM PDT 24
Finished Mar 24 01:05:27 PM PDT 24
Peak memory 215840 kb
Host smart-487a1e3a-7939-4111-a497-84bde47f3c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905731544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.905731544
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.516091910
Short name T359
Test name
Test status
Simulation time 53926912 ps
CPU time 0.86 seconds
Started Mar 24 01:05:24 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 205748 kb
Host smart-ab50b532-4559-4a7f-8995-555427424250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516091910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.516091910
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3038755554
Short name T165
Test name
Test status
Simulation time 17831154 ps
CPU time 0.87 seconds
Started Mar 24 01:05:24 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215924 kb
Host smart-b58f501a-08f7-4441-a828-d2efb63cc006
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038755554 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3038755554
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.754363876
Short name T91
Test name
Test status
Simulation time 48158748 ps
CPU time 1.09 seconds
Started Mar 24 01:05:27 PM PDT 24
Finished Mar 24 01:05:29 PM PDT 24
Peak memory 229620 kb
Host smart-81e4d126-0d50-4e2a-835a-f591166b00e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754363876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.754363876
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.731838938
Short name T54
Test name
Test status
Simulation time 60178116 ps
CPU time 1.29 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 216784 kb
Host smart-1dbc1d5f-ad78-4322-8d32-c9ce466a98f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731838938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.731838938
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3348593245
Short name T144
Test name
Test status
Simulation time 23266492 ps
CPU time 0.93 seconds
Started Mar 24 01:05:24 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215952 kb
Host smart-98885603-b8e3-4d08-9312-14a80efb5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348593245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3348593245
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3396158892
Short name T18
Test name
Test status
Simulation time 5215457727 ps
CPU time 5.94 seconds
Started Mar 24 01:05:24 PM PDT 24
Finished Mar 24 01:05:30 PM PDT 24
Peak memory 236288 kb
Host smart-68a4d258-d88d-4ddf-981b-9e1bd95c51c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396158892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3396158892
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1485283850
Short name T674
Test name
Test status
Simulation time 57073512 ps
CPU time 0.96 seconds
Started Mar 24 01:05:27 PM PDT 24
Finished Mar 24 01:05:29 PM PDT 24
Peak memory 215328 kb
Host smart-4c2e8953-cd24-4f2d-831a-93a368f87289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485283850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1485283850
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1475248380
Short name T316
Test name
Test status
Simulation time 98118703 ps
CPU time 1.11 seconds
Started Mar 24 01:05:26 PM PDT 24
Finished Mar 24 01:05:27 PM PDT 24
Peak memory 206152 kb
Host smart-7b1ccc74-bfee-4a55-acbc-b3eae36d9bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475248380 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1475248380
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.446663799
Short name T203
Test name
Test status
Simulation time 205872423371 ps
CPU time 1494.16 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:30:17 PM PDT 24
Peak memory 223440 kb
Host smart-3d6512d8-eaa6-48b7-a8b3-cc288a3084c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446663799 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.446663799
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.1099066715
Short name T760
Test name
Test status
Simulation time 67449898 ps
CPU time 0.99 seconds
Started Mar 24 01:05:59 PM PDT 24
Finished Mar 24 01:06:00 PM PDT 24
Peak memory 206608 kb
Host smart-5d1cdd74-f520-43a3-a8f4-0c8263e72536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099066715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1099066715
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3551420872
Short name T575
Test name
Test status
Simulation time 14365655 ps
CPU time 0.93 seconds
Started Mar 24 01:06:03 PM PDT 24
Finished Mar 24 01:06:04 PM PDT 24
Peak memory 216048 kb
Host smart-9440b9ab-e3f9-4744-8e0b-e3929203a727
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551420872 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3551420872
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2070517407
Short name T162
Test name
Test status
Simulation time 32592819 ps
CPU time 1.19 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 216564 kb
Host smart-6483ca03-4bf8-4714-9887-a7fde5d5d1af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070517407 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2070517407
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2319266598
Short name T560
Test name
Test status
Simulation time 21522726 ps
CPU time 0.97 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 218184 kb
Host smart-6205b363-2cc3-40b1-ac9a-e16e81a1567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319266598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2319266598
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.255668846
Short name T351
Test name
Test status
Simulation time 108906674 ps
CPU time 1.09 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:02 PM PDT 24
Peak memory 216780 kb
Host smart-95797980-5d72-46fc-bd4c-326bf216967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255668846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.255668846
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.902201554
Short name T618
Test name
Test status
Simulation time 46471454 ps
CPU time 0.91 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 215448 kb
Host smart-6bdd6b02-3c0b-4567-a4c9-576924d0cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902201554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.902201554
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4172746709
Short name T511
Test name
Test status
Simulation time 159536003 ps
CPU time 0.87 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:01 PM PDT 24
Peak memory 215424 kb
Host smart-d8a02bfd-68f1-408c-a68e-72f139ae4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172746709 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4172746709
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1189594723
Short name T352
Test name
Test status
Simulation time 274220055 ps
CPU time 2.09 seconds
Started Mar 24 01:06:02 PM PDT 24
Finished Mar 24 01:06:04 PM PDT 24
Peak memory 216876 kb
Host smart-d8904a60-3ec8-4b29-9df5-4d9efe79e283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189594723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1189594723
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1750808723
Short name T193
Test name
Test status
Simulation time 51049213505 ps
CPU time 1137.77 seconds
Started Mar 24 01:06:03 PM PDT 24
Finished Mar 24 01:25:01 PM PDT 24
Peak memory 220152 kb
Host smart-94a6bc61-8fd7-481d-9e03-e61e191f72c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750808723 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1750808723
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.edn_genbits.472275860
Short name T769
Test name
Test status
Simulation time 60465626 ps
CPU time 1.37 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 217044 kb
Host smart-7f067f8d-3c58-4582-a731-18381462a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472275860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.472275860
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3429793303
Short name T761
Test name
Test status
Simulation time 36723665 ps
CPU time 1.4 seconds
Started Mar 24 01:07:35 PM PDT 24
Finished Mar 24 01:07:37 PM PDT 24
Peak memory 218932 kb
Host smart-8c9dc198-5f7a-4970-a5b6-1ca35467db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429793303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3429793303
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.44616557
Short name T607
Test name
Test status
Simulation time 45244020 ps
CPU time 1.26 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 218024 kb
Host smart-a1200406-fe41-46d6-89cb-dc155e18c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44616557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.44616557
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1278481120
Short name T506
Test name
Test status
Simulation time 128286343 ps
CPU time 1.3 seconds
Started Mar 24 01:07:37 PM PDT 24
Finished Mar 24 01:07:39 PM PDT 24
Peak memory 218024 kb
Host smart-66360648-cb7e-4e84-be85-2413aa853b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278481120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1278481120
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3786977902
Short name T568
Test name
Test status
Simulation time 45235951 ps
CPU time 1.93 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 217772 kb
Host smart-1f7cf46f-b8d3-4712-81ee-c06c27747dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786977902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3786977902
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.670056358
Short name T626
Test name
Test status
Simulation time 142577887 ps
CPU time 2.91 seconds
Started Mar 24 01:07:39 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 218852 kb
Host smart-10b651c0-bcbb-4f3c-9365-2da41faf1a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670056358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.670056358
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.360153098
Short name T718
Test name
Test status
Simulation time 40671260 ps
CPU time 1.7 seconds
Started Mar 24 01:07:40 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 217820 kb
Host smart-c452d47a-1c44-40ce-9b7e-270d1e6aaaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360153098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.360153098
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.674926922
Short name T829
Test name
Test status
Simulation time 95245567 ps
CPU time 1.4 seconds
Started Mar 24 01:07:36 PM PDT 24
Finished Mar 24 01:07:38 PM PDT 24
Peak memory 219360 kb
Host smart-14bd8b8e-6116-45c6-b84c-f3aa7ed4fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674926922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.674926922
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.4105004753
Short name T667
Test name
Test status
Simulation time 22243430 ps
CPU time 0.87 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 206136 kb
Host smart-507126cf-3a0e-42e2-8522-2dd76b3ce887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105004753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4105004753
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_err.1216561862
Short name T5
Test name
Test status
Simulation time 71302727 ps
CPU time 1.01 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 229828 kb
Host smart-2aa0e241-68c8-4eab-9531-3ef66fac1c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216561862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1216561862
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.4128830320
Short name T414
Test name
Test status
Simulation time 36435736 ps
CPU time 1.29 seconds
Started Mar 24 01:06:03 PM PDT 24
Finished Mar 24 01:06:04 PM PDT 24
Peak memory 216664 kb
Host smart-2f1d667b-9202-4bf5-a2be-cc2f70c31803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128830320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4128830320
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1415379387
Short name T610
Test name
Test status
Simulation time 22551937 ps
CPU time 1.17 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:02 PM PDT 24
Peak memory 223956 kb
Host smart-3a32efad-e3d5-44cd-9d9d-9413ec039b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415379387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1415379387
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1075317843
Short name T444
Test name
Test status
Simulation time 22206627 ps
CPU time 0.96 seconds
Started Mar 24 01:06:05 PM PDT 24
Finished Mar 24 01:06:06 PM PDT 24
Peak memory 207228 kb
Host smart-04f89509-8025-4073-b60b-a3b62bbd3243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075317843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1075317843
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.525784562
Short name T339
Test name
Test status
Simulation time 111071960 ps
CPU time 2.48 seconds
Started Mar 24 01:06:00 PM PDT 24
Finished Mar 24 01:06:02 PM PDT 24
Peak memory 216780 kb
Host smart-633e169b-ee01-4dfa-9ea1-e104b98827b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525784562 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.525784562
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1572469408
Short name T812
Test name
Test status
Simulation time 32229757215 ps
CPU time 726.92 seconds
Started Mar 24 01:06:01 PM PDT 24
Finished Mar 24 01:18:08 PM PDT 24
Peak memory 219776 kb
Host smart-9fd57eb4-de9d-4f71-a3a6-67bcde26ebdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572469408 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1572469408
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.140081281
Short name T721
Test name
Test status
Simulation time 68942354 ps
CPU time 1.71 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 218252 kb
Host smart-0a8d980b-89c0-44c1-a54d-de96ea23841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140081281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.140081281
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2397333084
Short name T754
Test name
Test status
Simulation time 66637589 ps
CPU time 1.07 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 216560 kb
Host smart-9dbeedcc-3a70-4b14-b305-755145cbc036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397333084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2397333084
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3245647996
Short name T589
Test name
Test status
Simulation time 29264048 ps
CPU time 1.19 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 216716 kb
Host smart-8767f9ab-d895-4a37-8700-c7f1366065a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245647996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3245647996
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3943228417
Short name T486
Test name
Test status
Simulation time 69673731 ps
CPU time 1.17 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 215300 kb
Host smart-eb4595f3-df9c-495d-b237-418c17edf221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943228417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3943228417
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2613609845
Short name T628
Test name
Test status
Simulation time 61832536 ps
CPU time 1.18 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 216856 kb
Host smart-933bb326-b6ef-486d-8b61-43f70f77f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613609845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2613609845
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.179480682
Short name T659
Test name
Test status
Simulation time 43747165 ps
CPU time 1.57 seconds
Started Mar 24 01:07:38 PM PDT 24
Finished Mar 24 01:07:41 PM PDT 24
Peak memory 216892 kb
Host smart-9515a62e-b525-43ac-895b-e366a02257d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179480682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.179480682
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1095484933
Short name T503
Test name
Test status
Simulation time 206461942 ps
CPU time 1.1 seconds
Started Mar 24 01:07:39 PM PDT 24
Finished Mar 24 01:07:41 PM PDT 24
Peak memory 216732 kb
Host smart-aab2d5e6-4984-4f87-b52a-8d7f59ed3269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095484933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1095484933
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1169122146
Short name T583
Test name
Test status
Simulation time 55466445 ps
CPU time 1.25 seconds
Started Mar 24 01:07:45 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 218016 kb
Host smart-6c0bd2ab-b566-4b8a-892a-ce0f18230d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169122146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1169122146
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3609053604
Short name T445
Test name
Test status
Simulation time 41522473 ps
CPU time 1.48 seconds
Started Mar 24 01:07:45 PM PDT 24
Finished Mar 24 01:07:47 PM PDT 24
Peak memory 219068 kb
Host smart-a77321e3-0c63-421e-b9b6-ebc44576c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609053604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3609053604
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1170302691
Short name T658
Test name
Test status
Simulation time 402549774 ps
CPU time 1.94 seconds
Started Mar 24 01:07:41 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 218156 kb
Host smart-95f0a766-27c9-4320-a6ad-cf4558ce1976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170302691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1170302691
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.161166453
Short name T472
Test name
Test status
Simulation time 34922126 ps
CPU time 1.22 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:09 PM PDT 24
Peak memory 215764 kb
Host smart-7942bf29-fcfc-4c88-92e2-824ad82a7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161166453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.161166453
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2417111212
Short name T390
Test name
Test status
Simulation time 72394254 ps
CPU time 1.26 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:09 PM PDT 24
Peak memory 207004 kb
Host smart-18b85e62-4291-48da-9d5d-5f5941d992d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417111212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2417111212
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3928890327
Short name T406
Test name
Test status
Simulation time 30143571 ps
CPU time 1.13 seconds
Started Mar 24 01:06:10 PM PDT 24
Finished Mar 24 01:06:12 PM PDT 24
Peak memory 218044 kb
Host smart-91e90faa-dd4f-4dbf-aa41-55861d25ecc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928890327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3928890327
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2877380192
Short name T704
Test name
Test status
Simulation time 38911249 ps
CPU time 1 seconds
Started Mar 24 01:06:09 PM PDT 24
Finished Mar 24 01:06:12 PM PDT 24
Peak memory 219592 kb
Host smart-a99cf0f0-2a1b-4419-ab7a-24f64c648d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877380192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2877380192
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3907515191
Short name T766
Test name
Test status
Simulation time 54616192 ps
CPU time 1.19 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:09 PM PDT 24
Peak memory 216696 kb
Host smart-039dca94-9650-47e8-aaa4-2b06ddd59b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907515191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3907515191
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.3121103519
Short name T208
Test name
Test status
Simulation time 16745412 ps
CPU time 1.02 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 215428 kb
Host smart-bb127b6d-0b79-4fb3-b0b3-01136260c3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121103519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3121103519
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2954274552
Short name T210
Test name
Test status
Simulation time 908202010 ps
CPU time 5.18 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:13 PM PDT 24
Peak memory 216528 kb
Host smart-b709be47-2a93-4944-9a17-a8dd1d306794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954274552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2954274552
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2775499833
Short name T195
Test name
Test status
Simulation time 538726199734 ps
CPU time 1349.85 seconds
Started Mar 24 01:06:10 PM PDT 24
Finished Mar 24 01:28:41 PM PDT 24
Peak memory 222964 kb
Host smart-36806d3a-6ac0-4300-9320-9c13f10fcb8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775499833 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2775499833
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.1098520131
Short name T388
Test name
Test status
Simulation time 82887605 ps
CPU time 1.26 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216860 kb
Host smart-92cb9d13-9350-4e6d-85c3-39e452d53184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098520131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1098520131
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1488984362
Short name T617
Test name
Test status
Simulation time 40361472 ps
CPU time 1.42 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 217920 kb
Host smart-e63b4bb4-0798-489d-91b7-502cb9215dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488984362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1488984362
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.164254313
Short name T361
Test name
Test status
Simulation time 55275580 ps
CPU time 1.19 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 219500 kb
Host smart-7d9d3488-e149-4141-8b80-a2463dc618b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164254313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.164254313
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2154079885
Short name T188
Test name
Test status
Simulation time 35044737 ps
CPU time 1.54 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 217808 kb
Host smart-57a2540a-eb4a-4eed-93d8-17eebe624bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154079885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2154079885
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1428282786
Short name T338
Test name
Test status
Simulation time 99048278 ps
CPU time 1.32 seconds
Started Mar 24 01:07:43 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 216712 kb
Host smart-bbbb5b63-2f22-40c7-87d6-1ee345d3cf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428282786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1428282786
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2477381955
Short name T686
Test name
Test status
Simulation time 85635231 ps
CPU time 1.28 seconds
Started Mar 24 01:07:46 PM PDT 24
Finished Mar 24 01:07:47 PM PDT 24
Peak memory 218080 kb
Host smart-849466ed-a37c-46c3-8d90-fd5b7c555925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477381955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2477381955
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3304956039
Short name T147
Test name
Test status
Simulation time 43029018 ps
CPU time 1.43 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 218072 kb
Host smart-6ed393ef-82dc-4764-a786-fccf02505eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304956039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3304956039
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2082829820
Short name T254
Test name
Test status
Simulation time 24235198 ps
CPU time 1.2 seconds
Started Mar 24 01:07:46 PM PDT 24
Finished Mar 24 01:07:48 PM PDT 24
Peak memory 216588 kb
Host smart-9d0a6c87-c0d7-43b2-b673-00e9f1d20693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082829820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2082829820
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2907957452
Short name T647
Test name
Test status
Simulation time 32012636 ps
CPU time 1.39 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 217880 kb
Host smart-b24d2ff8-725e-487b-b840-3a93ae6d1cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907957452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2907957452
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1447873023
Short name T107
Test name
Test status
Simulation time 23826823 ps
CPU time 1.18 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:09 PM PDT 24
Peak memory 215776 kb
Host smart-8234b561-a078-4859-b2cb-b152935e698d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447873023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1447873023
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3060024160
Short name T531
Test name
Test status
Simulation time 28597017 ps
CPU time 0.85 seconds
Started Mar 24 01:06:09 PM PDT 24
Finished Mar 24 01:06:10 PM PDT 24
Peak memory 206560 kb
Host smart-cd0ff3af-ade7-42a8-a1fe-18f8864f21cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060024160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3060024160
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3830946265
Short name T175
Test name
Test status
Simulation time 183413736 ps
CPU time 0.92 seconds
Started Mar 24 01:06:08 PM PDT 24
Finished Mar 24 01:06:10 PM PDT 24
Peak memory 216048 kb
Host smart-570cda61-13b0-4ff9-83d8-fa0fc93e7476
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830946265 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3830946265
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.122268096
Short name T430
Test name
Test status
Simulation time 19247547 ps
CPU time 1 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 218104 kb
Host smart-ba630ea0-2496-47fb-9f13-6a30f2e407d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122268096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.122268096
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2601121877
Short name T306
Test name
Test status
Simulation time 161181971 ps
CPU time 1 seconds
Started Mar 24 01:06:09 PM PDT 24
Finished Mar 24 01:06:10 PM PDT 24
Peak memory 216724 kb
Host smart-483ed6e1-33e8-45c7-8b26-bdfadcc999e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601121877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2601121877
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.2855959063
Short name T695
Test name
Test status
Simulation time 16648615 ps
CPU time 1.04 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 215440 kb
Host smart-9c0582c5-1d11-43f0-bf00-63d27a197fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855959063 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2855959063
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3018593116
Short name T502
Test name
Test status
Simulation time 536504829 ps
CPU time 3.88 seconds
Started Mar 24 01:06:08 PM PDT 24
Finished Mar 24 01:06:13 PM PDT 24
Peak memory 216804 kb
Host smart-a070e73c-5e66-43d4-82fc-ab0edd095147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018593116 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3018593116
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.516585957
Short name T591
Test name
Test status
Simulation time 276741276514 ps
CPU time 1052.03 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:23:40 PM PDT 24
Peak memory 222916 kb
Host smart-931d15c9-5771-4c0a-9928-747d1fa4c2dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516585957 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.516585957
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2516544635
Short name T606
Test name
Test status
Simulation time 78573405 ps
CPU time 1.66 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 217368 kb
Host smart-035a22f4-09bf-4514-bdcc-47b786f418cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516544635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2516544635
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1000892437
Short name T407
Test name
Test status
Simulation time 41492788 ps
CPU time 1.28 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 218080 kb
Host smart-8af889d7-950b-4e89-aecf-2b24337eefa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000892437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1000892437
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3236924151
Short name T741
Test name
Test status
Simulation time 69236253 ps
CPU time 2.39 seconds
Started Mar 24 01:07:47 PM PDT 24
Finished Mar 24 01:07:50 PM PDT 24
Peak memory 219556 kb
Host smart-9407d1cc-1da7-44fd-a082-a1192abe080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236924151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3236924151
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1503353066
Short name T573
Test name
Test status
Simulation time 32396216 ps
CPU time 1.36 seconds
Started Mar 24 01:07:41 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218244 kb
Host smart-3d9d2069-55b2-4836-9d61-5a3da7f2f4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503353066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1503353066
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.240129793
Short name T752
Test name
Test status
Simulation time 37076466 ps
CPU time 1.17 seconds
Started Mar 24 01:07:43 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 216800 kb
Host smart-745b63bd-5db7-4022-8fb8-49838b691d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240129793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.240129793
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1001673643
Short name T625
Test name
Test status
Simulation time 101522407 ps
CPU time 1.28 seconds
Started Mar 24 01:07:45 PM PDT 24
Finished Mar 24 01:07:47 PM PDT 24
Peak memory 219248 kb
Host smart-74c7bef3-2b0a-4d73-8f97-7d976043c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001673643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1001673643
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.706134763
Short name T623
Test name
Test status
Simulation time 30794406 ps
CPU time 0.98 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216852 kb
Host smart-beafa978-3f97-4220-b1e1-60985b598a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706134763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.706134763
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2266970607
Short name T286
Test name
Test status
Simulation time 48586600 ps
CPU time 1.34 seconds
Started Mar 24 01:07:43 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 218072 kb
Host smart-ec359170-b792-423c-b3e6-7205197ddc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266970607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2266970607
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2036243555
Short name T665
Test name
Test status
Simulation time 64459160 ps
CPU time 1.99 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 217848 kb
Host smart-6586d762-49f8-4580-b056-02d145164ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036243555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2036243555
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1393657799
Short name T455
Test name
Test status
Simulation time 52618326 ps
CPU time 1.57 seconds
Started Mar 24 01:07:46 PM PDT 24
Finished Mar 24 01:07:47 PM PDT 24
Peak memory 217960 kb
Host smart-0db097ad-e88f-4d20-a2f1-6c5f37a0b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393657799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1393657799
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2060240943
Short name T302
Test name
Test status
Simulation time 26275372 ps
CPU time 1.3 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 215776 kb
Host smart-1dac4283-3101-4bf9-a636-991b2b2a1c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060240943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2060240943
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2484127287
Short name T605
Test name
Test status
Simulation time 29985666 ps
CPU time 0.99 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 206204 kb
Host smart-6cf78b40-3952-49aa-ae29-b57b1d479a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484127287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2484127287
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1375782166
Short name T633
Test name
Test status
Simulation time 41069124 ps
CPU time 0.87 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 215716 kb
Host smart-006c4ce5-d53c-4911-b34a-23503a79a1ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375782166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1375782166
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2691317542
Short name T716
Test name
Test status
Simulation time 94310475 ps
CPU time 1.1 seconds
Started Mar 24 01:06:16 PM PDT 24
Finished Mar 24 01:06:18 PM PDT 24
Peak memory 216628 kb
Host smart-15d35e48-fb1b-4101-8878-f69bd7e8b45d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691317542 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2691317542
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2893388801
Short name T171
Test name
Test status
Simulation time 25669769 ps
CPU time 1.22 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 219784 kb
Host smart-61fef66c-1198-47fa-a4ec-a24f882e9338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893388801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2893388801
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2214457916
Short name T581
Test name
Test status
Simulation time 78404657 ps
CPU time 1.75 seconds
Started Mar 24 01:06:08 PM PDT 24
Finished Mar 24 01:06:11 PM PDT 24
Peak memory 216888 kb
Host smart-9041d3ea-51ee-4bfc-bcbd-548eca01f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214457916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2214457916
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3782344031
Short name T650
Test name
Test status
Simulation time 20432229 ps
CPU time 1.1 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:18 PM PDT 24
Peak memory 215544 kb
Host smart-58a2e783-70bc-4de5-8c15-8a44563d328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782344031 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3782344031
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3323742899
Short name T358
Test name
Test status
Simulation time 50843561 ps
CPU time 0.93 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:06:08 PM PDT 24
Peak memory 215400 kb
Host smart-aa422dad-db06-4a2d-a263-2756c3921879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323742899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3323742899
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2851394362
Short name T532
Test name
Test status
Simulation time 204994705 ps
CPU time 1.05 seconds
Started Mar 24 01:06:07 PM PDT 24
Finished Mar 24 01:06:09 PM PDT 24
Peak memory 206016 kb
Host smart-f201faeb-4698-471a-95b8-5045410363aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851394362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2851394362
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1267086604
Short name T355
Test name
Test status
Simulation time 60710390673 ps
CPU time 761.35 seconds
Started Mar 24 01:06:06 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 219240 kb
Host smart-b51a663b-ce64-4ebd-8242-482d03f24906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267086604 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1267086604
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2598089764
Short name T345
Test name
Test status
Simulation time 181023016 ps
CPU time 1.1 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216824 kb
Host smart-590dc9bc-c3bb-4d76-b5dc-487d9a752750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598089764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2598089764
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.36219819
Short name T342
Test name
Test status
Simulation time 184561567 ps
CPU time 1 seconds
Started Mar 24 01:07:40 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216720 kb
Host smart-2b89d777-460d-4660-a361-0034c6837906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36219819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.36219819
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3937084802
Short name T325
Test name
Test status
Simulation time 183510208 ps
CPU time 1.05 seconds
Started Mar 24 01:07:46 PM PDT 24
Finished Mar 24 01:07:47 PM PDT 24
Peak memory 216760 kb
Host smart-3628d088-2234-4c02-9ddd-222f45155111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937084802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3937084802
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2263837059
Short name T604
Test name
Test status
Simulation time 75574537 ps
CPU time 1.7 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 218092 kb
Host smart-34e16046-fa45-4df9-a282-fb1d24259220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263837059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2263837059
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1933276651
Short name T425
Test name
Test status
Simulation time 104375541 ps
CPU time 1.39 seconds
Started Mar 24 01:07:45 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 218300 kb
Host smart-dbead3cd-d823-4f54-9be0-ffea1c20f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933276651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1933276651
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3688204209
Short name T603
Test name
Test status
Simulation time 37317489 ps
CPU time 1.51 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 217960 kb
Host smart-b018bf06-7ded-4d87-9398-b427f7a76adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688204209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3688204209
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2631109395
Short name T819
Test name
Test status
Simulation time 44794485 ps
CPU time 1.53 seconds
Started Mar 24 01:07:47 PM PDT 24
Finished Mar 24 01:07:48 PM PDT 24
Peak memory 217896 kb
Host smart-7f3b7409-f68e-414b-8f1f-adaf38a1a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631109395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2631109395
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2337418966
Short name T413
Test name
Test status
Simulation time 55779356 ps
CPU time 2.18 seconds
Started Mar 24 01:07:42 PM PDT 24
Finished Mar 24 01:07:45 PM PDT 24
Peak memory 218120 kb
Host smart-4e87f420-7e5a-4d0f-8ec6-20f88ac5eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337418966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2337418966
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.104071109
Short name T833
Test name
Test status
Simulation time 92177545 ps
CPU time 1.2 seconds
Started Mar 24 01:07:46 PM PDT 24
Finished Mar 24 01:07:47 PM PDT 24
Peak memory 216796 kb
Host smart-c613bc53-7f53-41f2-8680-aab633a6d7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104071109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.104071109
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1544357281
Short name T185
Test name
Test status
Simulation time 54139840 ps
CPU time 1.17 seconds
Started Mar 24 01:07:41 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 217756 kb
Host smart-e571eda5-3152-4073-8d9a-ad9340adb9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544357281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1544357281
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2610755792
Short name T154
Test name
Test status
Simulation time 68350742 ps
CPU time 1.22 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 215748 kb
Host smart-8173ef6c-4d79-4e4b-9cb4-d0b47e619547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610755792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2610755792
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2567031869
Short name T450
Test name
Test status
Simulation time 104509941 ps
CPU time 0.92 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 206496 kb
Host smart-fa3e9335-4c6f-4cff-9152-a877b5c99de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567031869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2567031869
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.521492999
Short name T73
Test name
Test status
Simulation time 361178848 ps
CPU time 1.24 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 216688 kb
Host smart-1dc14183-91ee-41db-8ff0-0170386379cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521492999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.521492999
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.957257299
Short name T544
Test name
Test status
Simulation time 41398040 ps
CPU time 1.24 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:18 PM PDT 24
Peak memory 224216 kb
Host smart-a4fe5f93-72fb-4101-a869-756836c30879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957257299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.957257299
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1346427441
Short name T121
Test name
Test status
Simulation time 109033123 ps
CPU time 1.44 seconds
Started Mar 24 01:06:16 PM PDT 24
Finished Mar 24 01:06:18 PM PDT 24
Peak memory 218212 kb
Host smart-e8a8c823-b875-40ac-b5d6-83cc788639ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346427441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1346427441
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3161463726
Short name T482
Test name
Test status
Simulation time 34963353 ps
CPU time 0.88 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 215348 kb
Host smart-23ce7d74-060a-4628-98b6-44086e99533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161463726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3161463726
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2690276630
Short name T616
Test name
Test status
Simulation time 25198491 ps
CPU time 0.95 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 215388 kb
Host smart-9f1c1e07-f1c7-409d-a1a6-5a79b89aed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690276630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2690276630
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2585658800
Short name T809
Test name
Test status
Simulation time 366471112 ps
CPU time 7.13 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:21 PM PDT 24
Peak memory 216624 kb
Host smart-c428ff9e-a0f8-4f46-b295-6470012e013c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585658800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2585658800
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4225359398
Short name T671
Test name
Test status
Simulation time 209177290811 ps
CPU time 2649.79 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:50:24 PM PDT 24
Peak memory 232456 kb
Host smart-98b07bf7-119d-4dba-adad-f90d755aed43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225359398 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4225359398
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1166106454
Short name T799
Test name
Test status
Simulation time 74303270 ps
CPU time 0.99 seconds
Started Mar 24 01:07:43 PM PDT 24
Finished Mar 24 01:07:44 PM PDT 24
Peak memory 216748 kb
Host smart-b718b72a-093d-477f-905e-a0a16ad773ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166106454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1166106454
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.851483843
Short name T751
Test name
Test status
Simulation time 415042492 ps
CPU time 1.36 seconds
Started Mar 24 01:07:44 PM PDT 24
Finished Mar 24 01:07:46 PM PDT 24
Peak memory 216832 kb
Host smart-ae24a952-4a8b-4637-868e-66e8d8238aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851483843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.851483843
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1778511750
Short name T377
Test name
Test status
Simulation time 55318422 ps
CPU time 1.28 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 216660 kb
Host smart-4484129f-e22d-44fc-9acf-16e37bbb5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778511750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1778511750
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1362082663
Short name T360
Test name
Test status
Simulation time 45186782 ps
CPU time 1.62 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 219152 kb
Host smart-f656f0e7-3521-4f09-94d8-999a087804d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362082663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1362082663
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1852062486
Short name T631
Test name
Test status
Simulation time 30231643 ps
CPU time 1.22 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 216576 kb
Host smart-02f771ca-880a-42ca-88c8-8e93c19aabb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852062486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1852062486
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3227253528
Short name T394
Test name
Test status
Simulation time 95661949 ps
CPU time 1.2 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 216580 kb
Host smart-ec824ec6-21be-4d29-a08a-72db027f9b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227253528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3227253528
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.226400258
Short name T537
Test name
Test status
Simulation time 46177662 ps
CPU time 1.72 seconds
Started Mar 24 01:07:47 PM PDT 24
Finished Mar 24 01:07:49 PM PDT 24
Peak memory 217988 kb
Host smart-c2e4a0c5-a230-428a-897f-5c4b8d744c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226400258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.226400258
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2641224449
Short name T576
Test name
Test status
Simulation time 155155046 ps
CPU time 1.24 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 216672 kb
Host smart-21abd418-66e1-4052-bdc2-5cfcc3e04d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641224449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2641224449
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.642868932
Short name T10
Test name
Test status
Simulation time 48539402 ps
CPU time 1.31 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:50 PM PDT 24
Peak memory 219328 kb
Host smart-d0efdc35-2341-4966-be11-daf79eca09fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642868932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.642868932
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3024581671
Short name T177
Test name
Test status
Simulation time 28590453 ps
CPU time 1.2 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:50 PM PDT 24
Peak memory 217880 kb
Host smart-a864d250-68d5-4dac-88d0-5d8010390250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024581671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3024581671
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4006992643
Short name T781
Test name
Test status
Simulation time 43068750 ps
CPU time 1.12 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 215716 kb
Host smart-f9754931-81c1-4aac-ab29-6b96cf992e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006992643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4006992643
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2323461202
Short name T372
Test name
Test status
Simulation time 102574837 ps
CPU time 0.89 seconds
Started Mar 24 01:06:18 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 206164 kb
Host smart-700d1158-3483-4665-b59d-e11aaadc1f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323461202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2323461202
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4261022445
Short name T578
Test name
Test status
Simulation time 16623290 ps
CPU time 0.91 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 216100 kb
Host smart-f63ba8e8-37d5-406c-b65d-709692459814
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261022445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4261022445
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1165144191
Short name T403
Test name
Test status
Simulation time 62701694 ps
CPU time 1.15 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 216672 kb
Host smart-054d5191-9deb-478c-b431-6ba38de1effc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165144191 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1165144191
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3154070917
Short name T731
Test name
Test status
Simulation time 101977693 ps
CPU time 1.1 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 219100 kb
Host smart-759eef2c-224c-4334-b591-e37b4594bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154070917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3154070917
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3235201870
Short name T644
Test name
Test status
Simulation time 47865563 ps
CPU time 1.5 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:18 PM PDT 24
Peak memory 218068 kb
Host smart-38c2a59e-43e1-4c7c-a12e-1d1cd532e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235201870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3235201870
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3515115192
Short name T449
Test name
Test status
Simulation time 21677288 ps
CPU time 1.23 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 224492 kb
Host smart-fe529242-51be-48da-86f4-4af0f078d9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515115192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3515115192
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4274518574
Short name T303
Test name
Test status
Simulation time 33924279 ps
CPU time 0.93 seconds
Started Mar 24 01:06:12 PM PDT 24
Finished Mar 24 01:06:14 PM PDT 24
Peak memory 215428 kb
Host smart-8e3e4e0a-a871-4c0a-aa0c-bcbf55b6c34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274518574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4274518574
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2458641609
Short name T214
Test name
Test status
Simulation time 50240534 ps
CPU time 1.65 seconds
Started Mar 24 01:06:13 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 217528 kb
Host smart-76a0a1e0-764c-46b4-863b-65585b313993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458641609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2458641609
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.814909712
Short name T365
Test name
Test status
Simulation time 44535837984 ps
CPU time 660.35 seconds
Started Mar 24 01:06:11 PM PDT 24
Finished Mar 24 01:17:14 PM PDT 24
Peak memory 218640 kb
Host smart-d8eee64c-59cf-4e8c-9f67-b4aef01ab7ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814909712 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.814909712
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3907142447
Short name T382
Test name
Test status
Simulation time 31986191 ps
CPU time 1.38 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 217784 kb
Host smart-cfd38d8f-348f-4cba-a028-51d3c6e254de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907142447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3907142447
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1714529379
Short name T27
Test name
Test status
Simulation time 239303959 ps
CPU time 1.16 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 216868 kb
Host smart-2a092549-49f2-439a-bb0b-899244b5f447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714529379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1714529379
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3222081470
Short name T768
Test name
Test status
Simulation time 78240068 ps
CPU time 2.78 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 218056 kb
Host smart-f4ee1031-a630-405f-a006-ffd946515332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222081470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3222081470
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3518794437
Short name T370
Test name
Test status
Simulation time 52330183 ps
CPU time 1.71 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 219120 kb
Host smart-35c3ca62-1dbc-4c37-b7b9-17684a268696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518794437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3518794437
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2454400222
Short name T687
Test name
Test status
Simulation time 179617050 ps
CPU time 2.62 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 219128 kb
Host smart-93028871-0f2d-4ca2-93a4-bb5fd455d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454400222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2454400222
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2563988651
Short name T524
Test name
Test status
Simulation time 139275426 ps
CPU time 1.08 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 216608 kb
Host smart-7066d58b-8d4c-4ea0-9f7b-9a55fdbfc905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563988651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2563988651
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3727553146
Short name T12
Test name
Test status
Simulation time 197678089 ps
CPU time 3.51 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 217944 kb
Host smart-0ea733a8-fdb4-42bb-967d-151b8c8ae481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727553146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3727553146
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1681391125
Short name T520
Test name
Test status
Simulation time 27140614 ps
CPU time 1.19 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 216456 kb
Host smart-5ecaa0ae-b439-48e4-b147-fd3f0b6f7b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681391125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1681391125
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3054930485
Short name T737
Test name
Test status
Simulation time 26335039 ps
CPU time 1.12 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 216624 kb
Host smart-3924af42-7c36-4f5a-a0f0-b6d60cc65a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054930485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3054930485
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.1839330077
Short name T557
Test name
Test status
Simulation time 31984924 ps
CPU time 0.94 seconds
Started Mar 24 01:06:18 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 206200 kb
Host smart-e48014f0-f42c-438e-8477-353bd72a100a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839330077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1839330077
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1202625897
Short name T739
Test name
Test status
Simulation time 40468476 ps
CPU time 0.99 seconds
Started Mar 24 01:06:19 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 217816 kb
Host smart-4d01054f-3f65-423a-8bfe-aaeb81e654b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202625897 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1202625897
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.825743341
Short name T734
Test name
Test status
Simulation time 18020161 ps
CPU time 1.07 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 218044 kb
Host smart-aeb21c04-557f-4b7b-9026-50140067dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825743341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.825743341
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3394153469
Short name T763
Test name
Test status
Simulation time 54174793 ps
CPU time 1.33 seconds
Started Mar 24 01:06:18 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 218192 kb
Host smart-189eb391-ebe1-4521-9ab5-38c6c35906fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394153469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3394153469
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1626769744
Short name T315
Test name
Test status
Simulation time 53108906 ps
CPU time 0.84 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 215292 kb
Host smart-62e98f98-66f1-4d05-b756-78e58ff4ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626769744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1626769744
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4228009977
Short name T545
Test name
Test status
Simulation time 50514963 ps
CPU time 0.92 seconds
Started Mar 24 01:06:18 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 215424 kb
Host smart-781a34c4-3f4b-48e9-91aa-0bb43129dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228009977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4228009977
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3220008018
Short name T197
Test name
Test status
Simulation time 71733558 ps
CPU time 1.55 seconds
Started Mar 24 01:06:18 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 216684 kb
Host smart-effc2922-6281-4df1-abf0-f8f1f102e560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220008018 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3220008018
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1452047834
Short name T740
Test name
Test status
Simulation time 153193852752 ps
CPU time 1043.83 seconds
Started Mar 24 01:06:20 PM PDT 24
Finished Mar 24 01:23:44 PM PDT 24
Peak memory 223412 kb
Host smart-dc9d83a2-95fb-49a9-9b1b-18923ca77979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452047834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1452047834
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/271.edn_genbits.3831599003
Short name T313
Test name
Test status
Simulation time 75771186 ps
CPU time 1.12 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 217760 kb
Host smart-15322d59-7ab0-4b3b-b6d6-b3097adf228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831599003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3831599003
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1860967382
Short name T691
Test name
Test status
Simulation time 96241323 ps
CPU time 1.38 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 218232 kb
Host smart-4b0a8f50-e9e8-4919-a65b-0622893082f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860967382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1860967382
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.929410667
Short name T490
Test name
Test status
Simulation time 38166493 ps
CPU time 1.04 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 216788 kb
Host smart-391f2ccc-55c1-4736-ac3d-f9948f24856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929410667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.929410667
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2450461059
Short name T35
Test name
Test status
Simulation time 63010192 ps
CPU time 2.38 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:56 PM PDT 24
Peak memory 217976 kb
Host smart-b4c38b8b-12ab-4dc2-bf28-ee59212daca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450461059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2450461059
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1249798368
Short name T299
Test name
Test status
Simulation time 344505209 ps
CPU time 1.59 seconds
Started Mar 24 01:07:48 PM PDT 24
Finished Mar 24 01:07:50 PM PDT 24
Peak memory 216996 kb
Host smart-d0634a55-ab81-46b3-bd66-1a3837f39afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249798368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1249798368
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3212612395
Short name T408
Test name
Test status
Simulation time 140507827 ps
CPU time 1.94 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 216960 kb
Host smart-fbed34ee-0f9e-4042-82b9-f77075d88dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212612395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3212612395
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3214835944
Short name T461
Test name
Test status
Simulation time 57606646 ps
CPU time 1.08 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 218128 kb
Host smart-d3349180-40b2-46c3-8b56-38312df32ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214835944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3214835944
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2859629649
Short name T569
Test name
Test status
Simulation time 4900402079 ps
CPU time 85.15 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:09:19 PM PDT 24
Peak memory 216980 kb
Host smart-6fa8f7e6-e4b2-48aa-b46c-c5fec6da6e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859629649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2859629649
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.465593804
Short name T602
Test name
Test status
Simulation time 49576497 ps
CPU time 0.91 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:06:26 PM PDT 24
Peak memory 206668 kb
Host smart-4dbf2edf-82cf-4bf3-a5d1-4ab6fc5b5bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465593804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.465593804
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1692296044
Short name T567
Test name
Test status
Simulation time 11814691 ps
CPU time 0.89 seconds
Started Mar 24 01:06:23 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 215624 kb
Host smart-9113eea2-507c-461d-84ed-148aa2aafe89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692296044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1692296044
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4086114784
Short name T693
Test name
Test status
Simulation time 74034614 ps
CPU time 0.99 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 217716 kb
Host smart-44e24a26-306b-4cf3-9a49-141675e8b2ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086114784 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4086114784
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.727686045
Short name T113
Test name
Test status
Simulation time 28368906 ps
CPU time 0.95 seconds
Started Mar 24 01:06:21 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 222936 kb
Host smart-0fe4416b-b7bf-4a50-843f-52c28d42a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727686045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.727686045
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2160080054
Short name T755
Test name
Test status
Simulation time 67463043 ps
CPU time 1.26 seconds
Started Mar 24 01:06:20 PM PDT 24
Finished Mar 24 01:06:21 PM PDT 24
Peak memory 217060 kb
Host smart-bf55af07-0d17-4463-8f14-d1ce4982ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160080054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2160080054
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2442302358
Short name T466
Test name
Test status
Simulation time 35894017 ps
CPU time 1.04 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:20 PM PDT 24
Peak memory 215900 kb
Host smart-2061daa7-483b-4cfe-bf8a-d758ae690570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442302358 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2442302358
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3186248721
Short name T501
Test name
Test status
Simulation time 19562076 ps
CPU time 0.96 seconds
Started Mar 24 01:06:19 PM PDT 24
Finished Mar 24 01:06:21 PM PDT 24
Peak memory 215420 kb
Host smart-f81dd87a-8cd1-43ea-954a-1a82600c8843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186248721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3186248721
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2491723310
Short name T401
Test name
Test status
Simulation time 220730268 ps
CPU time 2.91 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:06:22 PM PDT 24
Peak memory 216684 kb
Host smart-f7ebf5f5-e5d8-4a0c-b374-8de00d6b0bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491723310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2491723310
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.10575067
Short name T205
Test name
Test status
Simulation time 15263955713 ps
CPU time 117.76 seconds
Started Mar 24 01:06:17 PM PDT 24
Finished Mar 24 01:08:17 PM PDT 24
Peak memory 223824 kb
Host smart-bb641c6a-4813-42bd-b042-a5fc00d4a115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575067 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.10575067
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1999010351
Short name T558
Test name
Test status
Simulation time 72810048 ps
CPU time 1.3 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 218088 kb
Host smart-6a1e92f8-e60d-4ac1-838a-e27f79f6ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999010351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1999010351
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3719741920
Short name T432
Test name
Test status
Simulation time 44595904 ps
CPU time 1.6 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 219368 kb
Host smart-27cd1b97-9a76-44d9-b481-1b53ce70322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719741920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3719741920
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3008077771
Short name T283
Test name
Test status
Simulation time 97962330 ps
CPU time 2.06 seconds
Started Mar 24 01:07:54 PM PDT 24
Finished Mar 24 01:07:56 PM PDT 24
Peak memory 219012 kb
Host smart-44b5685e-a574-47f6-854c-87d6cef2083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008077771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3008077771
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2031998657
Short name T30
Test name
Test status
Simulation time 47984813 ps
CPU time 1.24 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 216576 kb
Host smart-462393d6-36d6-4368-8000-a5fb15ed1020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031998657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2031998657
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.544689623
Short name T393
Test name
Test status
Simulation time 127240903 ps
CPU time 2.44 seconds
Started Mar 24 01:07:48 PM PDT 24
Finished Mar 24 01:07:50 PM PDT 24
Peak memory 218972 kb
Host smart-ba79addf-be6a-4a95-a294-7afd7f54f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544689623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.544689623
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.661418511
Short name T434
Test name
Test status
Simulation time 72731850 ps
CPU time 2.45 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 219472 kb
Host smart-109db2c9-b1a7-4bb2-82ff-5e74aec548c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661418511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.661418511
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2300519270
Short name T479
Test name
Test status
Simulation time 180763192 ps
CPU time 3.18 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 219744 kb
Host smart-350f422f-4c7d-4630-8a58-304e32301f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300519270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2300519270
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1892169396
Short name T322
Test name
Test status
Simulation time 56141464 ps
CPU time 1.2 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 216772 kb
Host smart-1e035d0d-0d1f-4586-ad8f-82ed28924a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892169396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1892169396
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.620830850
Short name T582
Test name
Test status
Simulation time 85080653 ps
CPU time 1.31 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 218212 kb
Host smart-8c6dbad3-1f6a-4697-b02f-e9e593468756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620830850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.620830850
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2115259142
Short name T331
Test name
Test status
Simulation time 48474682 ps
CPU time 1.29 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:07:52 PM PDT 24
Peak memory 216776 kb
Host smart-e6acc3c1-5186-4e93-8ede-a0c55dc5422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115259142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2115259142
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1547350161
Short name T269
Test name
Test status
Simulation time 76975945 ps
CPU time 1.21 seconds
Started Mar 24 01:06:23 PM PDT 24
Finished Mar 24 01:06:25 PM PDT 24
Peak memory 215800 kb
Host smart-210157b1-e323-44c6-a5a9-027bce988667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547350161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1547350161
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3948870167
Short name T448
Test name
Test status
Simulation time 70995291 ps
CPU time 1.04 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 206148 kb
Host smart-5a309c89-9799-4189-8b8c-3ce9e6c6b1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948870167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3948870167
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.45498520
Short name T111
Test name
Test status
Simulation time 11912436 ps
CPU time 0.9 seconds
Started Mar 24 01:06:22 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 216112 kb
Host smart-8271956d-fec4-4f00-87b5-46748aa9fe31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45498520 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.45498520
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.524847735
Short name T183
Test name
Test status
Simulation time 21619518 ps
CPU time 1.04 seconds
Started Mar 24 01:06:20 PM PDT 24
Finished Mar 24 01:06:21 PM PDT 24
Peak memory 216832 kb
Host smart-da78af1e-aa76-4ac7-a8e4-60139e0ecad0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524847735 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.524847735
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.474096474
Short name T75
Test name
Test status
Simulation time 20687933 ps
CPU time 1.11 seconds
Started Mar 24 01:06:23 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 219456 kb
Host smart-d9b8ccd8-ac0a-4396-a6b8-5f2b24a56801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474096474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.474096474
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.919870389
Short name T539
Test name
Test status
Simulation time 63756242 ps
CPU time 1.35 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:06:26 PM PDT 24
Peak memory 216672 kb
Host smart-2bf08053-5da9-40cf-9180-6af2a695a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919870389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.919870389
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2812299409
Short name T126
Test name
Test status
Simulation time 24857948 ps
CPU time 0.92 seconds
Started Mar 24 01:06:22 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 215952 kb
Host smart-8819d856-0486-4548-b3c2-3e28e8085cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812299409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2812299409
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2799383804
Short name T353
Test name
Test status
Simulation time 16110111 ps
CPU time 0.94 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215436 kb
Host smart-13010d4a-afbf-4fea-b50a-956e5d3607b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799383804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2799383804
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.17235836
Short name T483
Test name
Test status
Simulation time 663830199 ps
CPU time 1.36 seconds
Started Mar 24 01:06:23 PM PDT 24
Finished Mar 24 01:06:25 PM PDT 24
Peak memory 216872 kb
Host smart-cb32faa6-ac28-4c2e-80f0-aaa2efe0153c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17235836 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.17235836
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.959251480
Short name T436
Test name
Test status
Simulation time 38773529181 ps
CPU time 879.61 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:21:07 PM PDT 24
Peak memory 218420 kb
Host smart-7f98c309-57cf-4bc2-9ba2-5b74efd467d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959251480 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.959251480
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1985571326
Short name T64
Test name
Test status
Simulation time 48756854 ps
CPU time 1.21 seconds
Started Mar 24 01:07:51 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 218076 kb
Host smart-1e1bb3d5-7f6c-433a-a491-abb47c4952c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985571326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1985571326
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1912687301
Short name T464
Test name
Test status
Simulation time 80411082 ps
CPU time 1.1 seconds
Started Mar 24 01:07:50 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 216624 kb
Host smart-feeee0f9-df24-45cf-aefd-ee733ee64a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912687301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1912687301
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2272615442
Short name T738
Test name
Test status
Simulation time 105248829 ps
CPU time 2.08 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 216928 kb
Host smart-64a80d82-7d58-4ea3-a3f7-f85d1d292eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272615442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2272615442
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1878007659
Short name T601
Test name
Test status
Simulation time 138105324 ps
CPU time 3.14 seconds
Started Mar 24 01:07:47 PM PDT 24
Finished Mar 24 01:07:50 PM PDT 24
Peak memory 219760 kb
Host smart-3e8feaca-b44d-4518-b419-fbbb33b063f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878007659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1878007659
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.900171723
Short name T682
Test name
Test status
Simulation time 39044697 ps
CPU time 1.61 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 218160 kb
Host smart-fc7edb6c-9d21-495c-a809-569876d27861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900171723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.900171723
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4174729464
Short name T301
Test name
Test status
Simulation time 38975867 ps
CPU time 1.1 seconds
Started Mar 24 01:07:53 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 216884 kb
Host smart-a22ce7d2-30af-43dd-878c-0ebfac32be5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174729464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4174729464
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1038807453
Short name T319
Test name
Test status
Simulation time 127974775 ps
CPU time 1.71 seconds
Started Mar 24 01:07:52 PM PDT 24
Finished Mar 24 01:07:54 PM PDT 24
Peak memory 218336 kb
Host smart-0fd6a82e-fad5-4751-b5c9-b567b3b45ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038807453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1038807453
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3107794818
Short name T380
Test name
Test status
Simulation time 58600183 ps
CPU time 1.56 seconds
Started Mar 24 01:07:49 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 218220 kb
Host smart-aa513829-3cf7-4ba7-9ebd-f0edbf661f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107794818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3107794818
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.247482702
Short name T662
Test name
Test status
Simulation time 68596513 ps
CPU time 1.24 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215740 kb
Host smart-b91ab42c-5a2f-40de-9ffd-1241a15b355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247482702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.247482702
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2709805250
Short name T415
Test name
Test status
Simulation time 35055354 ps
CPU time 0.82 seconds
Started Mar 24 01:05:30 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 205772 kb
Host smart-a9ed0b8f-3912-46c8-b943-f3d7485621b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709805250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2709805250
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2487718850
Short name T641
Test name
Test status
Simulation time 71347792 ps
CPU time 1.28 seconds
Started Mar 24 01:05:36 PM PDT 24
Finished Mar 24 01:05:37 PM PDT 24
Peak memory 216532 kb
Host smart-0f88cbfe-3a1e-453a-b380-c72777e98ab5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487718850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2487718850
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3426961633
Short name T78
Test name
Test status
Simulation time 21918407 ps
CPU time 1.11 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:24 PM PDT 24
Peak memory 219304 kb
Host smart-aaf6ce78-6feb-4cfb-9547-ea2e3d855725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426961633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3426961633
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1096779608
Short name T31
Test name
Test status
Simulation time 52759471 ps
CPU time 1.3 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:24 PM PDT 24
Peak memory 216784 kb
Host smart-3ca49612-3175-4aab-b7eb-2915a0bf6da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096779608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1096779608
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.294578028
Short name T354
Test name
Test status
Simulation time 23168127 ps
CPU time 1.09 seconds
Started Mar 24 01:05:24 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215736 kb
Host smart-670b3641-d487-4ae4-b2ef-9627ea5a3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294578028 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.294578028
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1500868333
Short name T262
Test name
Test status
Simulation time 22743239 ps
CPU time 0.88 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:24 PM PDT 24
Peak memory 207092 kb
Host smart-a69f6b00-d004-44ae-9fd9-9e65ebb937a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500868333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1500868333
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.872380302
Short name T48
Test name
Test status
Simulation time 185397510 ps
CPU time 3.5 seconds
Started Mar 24 01:05:29 PM PDT 24
Finished Mar 24 01:05:33 PM PDT 24
Peak memory 234556 kb
Host smart-4acddafa-8b85-428e-b920-fa2af41fa117
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872380302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.872380302
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1805155036
Short name T376
Test name
Test status
Simulation time 15738655 ps
CPU time 1 seconds
Started Mar 24 01:05:25 PM PDT 24
Finished Mar 24 01:05:26 PM PDT 24
Peak memory 215444 kb
Host smart-68ff8e29-076b-4193-9836-fa8ef869ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805155036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1805155036
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.120288279
Short name T632
Test name
Test status
Simulation time 153900883 ps
CPU time 1.67 seconds
Started Mar 24 01:05:23 PM PDT 24
Finished Mar 24 01:05:25 PM PDT 24
Peak memory 215256 kb
Host smart-48f088d8-3726-4a28-a0ca-eb224c3050d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120288279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.120288279
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2454901323
Short name T630
Test name
Test status
Simulation time 57098184437 ps
CPU time 651.69 seconds
Started Mar 24 01:05:22 PM PDT 24
Finished Mar 24 01:16:14 PM PDT 24
Peak memory 218732 kb
Host smart-ba74b9f9-ccff-4284-b01e-b7d203dd9642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454901323 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2454901323
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2380991466
Short name T748
Test name
Test status
Simulation time 23313111 ps
CPU time 1.12 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:06:26 PM PDT 24
Peak memory 215776 kb
Host smart-b6b180f7-5fcf-4266-9d4b-9bbd179d2e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380991466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2380991466
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2213122294
Short name T196
Test name
Test status
Simulation time 47567172 ps
CPU time 0.81 seconds
Started Mar 24 01:06:21 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 206400 kb
Host smart-93dc1a9a-99ca-421c-842a-7f4c761c6629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213122294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2213122294
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3673309083
Short name T496
Test name
Test status
Simulation time 20715781 ps
CPU time 0.85 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:06:25 PM PDT 24
Peak memory 215616 kb
Host smart-7df93482-9548-48e7-a655-09bd85f8b975
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673309083 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3673309083
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3438986765
Short name T776
Test name
Test status
Simulation time 50831068 ps
CPU time 1.24 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 216424 kb
Host smart-691d31d4-5682-41d5-a27e-f4d3d0d28f94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438986765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3438986765
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1729926336
Short name T694
Test name
Test status
Simulation time 36070587 ps
CPU time 1.12 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:06:26 PM PDT 24
Peak memory 218312 kb
Host smart-f017adf3-e15c-4245-bd9a-0203635791ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729926336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1729926336
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2509924089
Short name T807
Test name
Test status
Simulation time 68863455 ps
CPU time 1.12 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 219508 kb
Host smart-d73f381e-2421-4435-9ff5-441a5583a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509924089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2509924089
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2711249625
Short name T378
Test name
Test status
Simulation time 20793638 ps
CPU time 1.03 seconds
Started Mar 24 01:06:23 PM PDT 24
Finished Mar 24 01:06:24 PM PDT 24
Peak memory 215800 kb
Host smart-8fed438d-31b7-4f6b-9322-875930741154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711249625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2711249625
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3576685726
Short name T666
Test name
Test status
Simulation time 77860743 ps
CPU time 0.93 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215408 kb
Host smart-5680d6c0-b887-42b2-b205-6e1a6a65f2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576685726 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3576685726
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2711819228
Short name T215
Test name
Test status
Simulation time 2429173526 ps
CPU time 3.03 seconds
Started Mar 24 01:06:22 PM PDT 24
Finished Mar 24 01:06:26 PM PDT 24
Peak memory 217028 kb
Host smart-43185e53-31bf-451b-a040-28aee8289ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711819228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2711819228
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3692425740
Short name T493
Test name
Test status
Simulation time 10579893085 ps
CPU time 270.95 seconds
Started Mar 24 01:06:23 PM PDT 24
Finished Mar 24 01:10:54 PM PDT 24
Peak memory 218176 kb
Host smart-8ab57aee-ded8-402d-af5f-3ec98bae139f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692425740 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3692425740
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.63609525
Short name T542
Test name
Test status
Simulation time 69407388 ps
CPU time 1.12 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215760 kb
Host smart-f871b257-6691-4b44-8a4e-f4194fb6d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63609525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.63609525
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2391403706
Short name T418
Test name
Test status
Simulation time 22493464 ps
CPU time 0.88 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 206500 kb
Host smart-6bdbb8da-9fc5-4e32-bda0-fe6e9831d2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391403706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2391403706
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.161391156
Short name T375
Test name
Test status
Simulation time 11615434 ps
CPU time 0.86 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:06:25 PM PDT 24
Peak memory 215620 kb
Host smart-c36fe5e9-05b9-46b1-a690-d0a7f5cfb9f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161391156 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.161391156
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.3434724108
Short name T308
Test name
Test status
Simulation time 170449706 ps
CPU time 1.02 seconds
Started Mar 24 01:06:27 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 220472 kb
Host smart-16ef35be-69d0-41dc-a668-2b8755c0af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434724108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3434724108
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.143191571
Short name T541
Test name
Test status
Simulation time 51558703 ps
CPU time 1.85 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:06:26 PM PDT 24
Peak memory 217868 kb
Host smart-f1b07165-2d89-4c85-93ea-d8c401a1a2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143191571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.143191571
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3649193836
Short name T38
Test name
Test status
Simulation time 24993550 ps
CPU time 0.99 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215584 kb
Host smart-18ebf4fb-25d0-42b6-81b0-89993dd203af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649193836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3649193836
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1335317521
Short name T467
Test name
Test status
Simulation time 19979880 ps
CPU time 1.02 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215380 kb
Host smart-e4e92967-aad0-4575-868b-37e95e069d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335317521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1335317521
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3490365476
Short name T810
Test name
Test status
Simulation time 432130269 ps
CPU time 4.62 seconds
Started Mar 24 01:06:22 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215440 kb
Host smart-ac1f4172-09d3-45ed-ba41-bf4e3950f8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490365476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3490365476
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert_test.2501021158
Short name T404
Test name
Test status
Simulation time 91901867 ps
CPU time 0.93 seconds
Started Mar 24 01:06:28 PM PDT 24
Finished Mar 24 01:06:29 PM PDT 24
Peak memory 206168 kb
Host smart-251e845f-9686-47b4-aedd-f3867b7c23f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501021158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2501021158
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1080197009
Short name T123
Test name
Test status
Simulation time 57924137 ps
CPU time 0.86 seconds
Started Mar 24 01:06:32 PM PDT 24
Finished Mar 24 01:06:33 PM PDT 24
Peak memory 215584 kb
Host smart-e5886df6-dc37-430e-b3d5-b9a916d62c99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080197009 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1080197009
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2512327748
Short name T83
Test name
Test status
Simulation time 52050102 ps
CPU time 1.16 seconds
Started Mar 24 01:06:31 PM PDT 24
Finished Mar 24 01:06:32 PM PDT 24
Peak memory 216724 kb
Host smart-f706a18e-0324-4cac-a189-ec77b6b732a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512327748 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2512327748
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3036266262
Short name T433
Test name
Test status
Simulation time 19555456 ps
CPU time 1.11 seconds
Started Mar 24 01:06:29 PM PDT 24
Finished Mar 24 01:06:30 PM PDT 24
Peak memory 218268 kb
Host smart-52ba2525-17ac-41dd-bd03-17c2b8f9e69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036266262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3036266262
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.417545630
Short name T366
Test name
Test status
Simulation time 44648834 ps
CPU time 1.09 seconds
Started Mar 24 01:06:25 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 216768 kb
Host smart-a341b254-97df-4fb2-81d3-e4f69722cbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417545630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.417545630
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1660722272
Short name T522
Test name
Test status
Simulation time 28299193 ps
CPU time 1.21 seconds
Started Mar 24 01:06:27 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 224604 kb
Host smart-c5afa2fa-4678-4dda-beae-9a1ab066e3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660722272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1660722272
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4075662449
Short name T645
Test name
Test status
Simulation time 15381397 ps
CPU time 0.94 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 215388 kb
Host smart-58940245-52cd-415a-a47b-7e69aaf3eabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075662449 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4075662449
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3114165551
Short name T217
Test name
Test status
Simulation time 394916517 ps
CPU time 2.54 seconds
Started Mar 24 01:06:24 PM PDT 24
Finished Mar 24 01:06:27 PM PDT 24
Peak memory 216512 kb
Host smart-fd634cf8-3cff-46bc-8ec9-734f2649cb73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114165551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3114165551
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.838863990
Short name T190
Test name
Test status
Simulation time 275747087694 ps
CPU time 1362.72 seconds
Started Mar 24 01:06:26 PM PDT 24
Finished Mar 24 01:29:10 PM PDT 24
Peak memory 222244 kb
Host smart-8e928417-2e08-4fb1-8e67-564b3e63e60a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838863990 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.838863990
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.683645132
Short name T675
Test name
Test status
Simulation time 50945181 ps
CPU time 0.96 seconds
Started Mar 24 01:06:27 PM PDT 24
Finished Mar 24 01:06:28 PM PDT 24
Peak memory 206992 kb
Host smart-3d6c6aca-0e76-42d5-b025-54f6a4779539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683645132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.683645132
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3297078416
Short name T784
Test name
Test status
Simulation time 41284473 ps
CPU time 0.88 seconds
Started Mar 24 01:06:28 PM PDT 24
Finished Mar 24 01:06:29 PM PDT 24
Peak memory 215572 kb
Host smart-cd26d4af-c881-4627-99b3-e914aa67f5bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297078416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3297078416
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.1773984776
Short name T59
Test name
Test status
Simulation time 19771481 ps
CPU time 1.14 seconds
Started Mar 24 01:06:32 PM PDT 24
Finished Mar 24 01:06:34 PM PDT 24
Peak memory 218316 kb
Host smart-ed9a4aa5-ed65-48cc-8e72-1404f34bb632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773984776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1773984776
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3788323095
Short name T584
Test name
Test status
Simulation time 78281450 ps
CPU time 1.18 seconds
Started Mar 24 01:06:28 PM PDT 24
Finished Mar 24 01:06:29 PM PDT 24
Peak memory 217868 kb
Host smart-64e10d13-8fb4-40b0-aeaf-9ff7144cfe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788323095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3788323095
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2541530265
Short name T491
Test name
Test status
Simulation time 25936607 ps
CPU time 0.99 seconds
Started Mar 24 01:06:29 PM PDT 24
Finished Mar 24 01:06:30 PM PDT 24
Peak memory 215552 kb
Host smart-b251d902-13e3-455d-807a-13cd71ea6593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541530265 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2541530265
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2715172921
Short name T599
Test name
Test status
Simulation time 40799161 ps
CPU time 0.88 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:35 PM PDT 24
Peak memory 215396 kb
Host smart-cb011c25-a000-4dbf-bf90-ca6883f61b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715172921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2715172921
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2033181485
Short name T318
Test name
Test status
Simulation time 1268477820 ps
CPU time 4.6 seconds
Started Mar 24 01:06:30 PM PDT 24
Finished Mar 24 01:06:35 PM PDT 24
Peak memory 215400 kb
Host smart-8e0ca6ef-f272-43be-bf07-a38c9a927afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033181485 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2033181485
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1317083161
Short name T199
Test name
Test status
Simulation time 28797548993 ps
CPU time 344.24 seconds
Started Mar 24 01:06:33 PM PDT 24
Finished Mar 24 01:12:18 PM PDT 24
Peak memory 218180 kb
Host smart-3b8da3b2-be45-411a-825d-aa4f6d20d1f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317083161 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1317083161
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1061949235
Short name T69
Test name
Test status
Simulation time 26603651 ps
CPU time 1.23 seconds
Started Mar 24 01:06:29 PM PDT 24
Finished Mar 24 01:06:30 PM PDT 24
Peak memory 215800 kb
Host smart-cf54c783-1620-4382-94c3-3fbb2a858c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061949235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1061949235
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2363878603
Short name T803
Test name
Test status
Simulation time 14384768 ps
CPU time 0.9 seconds
Started Mar 24 01:06:33 PM PDT 24
Finished Mar 24 01:06:34 PM PDT 24
Peak memory 206692 kb
Host smart-b80b0c34-9248-4cd9-a8ea-ca0108777dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363878603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2363878603
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.535954008
Short name T169
Test name
Test status
Simulation time 27451729 ps
CPU time 0.84 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:35 PM PDT 24
Peak memory 216052 kb
Host smart-e67cd3bc-4ca3-4ecb-96fb-6af4f078ded9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535954008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.535954008
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.1378574314
Short name T14
Test name
Test status
Simulation time 35315159 ps
CPU time 1.11 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:06:45 PM PDT 24
Peak memory 229752 kb
Host smart-a81c1070-bc48-4da3-9a3a-6e27d7104201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378574314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1378574314
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3698379650
Short name T32
Test name
Test status
Simulation time 62276721 ps
CPU time 1.36 seconds
Started Mar 24 01:06:29 PM PDT 24
Finished Mar 24 01:06:30 PM PDT 24
Peak memory 216752 kb
Host smart-09487547-5fa0-4a5c-b68c-2d0cb03b8c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698379650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3698379650
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3260459181
Short name T350
Test name
Test status
Simulation time 26864963 ps
CPU time 0.89 seconds
Started Mar 24 01:06:31 PM PDT 24
Finished Mar 24 01:06:32 PM PDT 24
Peak memory 215588 kb
Host smart-0ef74dbc-9d5e-461e-aaa0-8e386feb79f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260459181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3260459181
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1888484062
Short name T725
Test name
Test status
Simulation time 43185842 ps
CPU time 0.94 seconds
Started Mar 24 01:06:30 PM PDT 24
Finished Mar 24 01:06:31 PM PDT 24
Peak memory 215472 kb
Host smart-b56376aa-dfdf-4bff-91be-a9e3e4cfe496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888484062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1888484062
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2398094905
Short name T765
Test name
Test status
Simulation time 66237228 ps
CPU time 1.55 seconds
Started Mar 24 01:06:29 PM PDT 24
Finished Mar 24 01:06:31 PM PDT 24
Peak memory 215432 kb
Host smart-0dc6fc46-5f73-44fc-bb9e-14068ffc1ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398094905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2398094905
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3264052444
Short name T200
Test name
Test status
Simulation time 161181517775 ps
CPU time 392.77 seconds
Started Mar 24 01:06:27 PM PDT 24
Finished Mar 24 01:13:00 PM PDT 24
Peak memory 223828 kb
Host smart-d4d801a3-0076-4c02-916f-f283ce2253f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264052444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3264052444
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3562315456
Short name T519
Test name
Test status
Simulation time 27813291 ps
CPU time 1.34 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 215796 kb
Host smart-8e398127-8678-4353-b5aa-e179278ba7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562315456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3562315456
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3308191436
Short name T827
Test name
Test status
Simulation time 19973047 ps
CPU time 0.84 seconds
Started Mar 24 01:06:33 PM PDT 24
Finished Mar 24 01:06:34 PM PDT 24
Peak memory 206568 kb
Host smart-92db69ee-fe15-4be3-ac39-8a8061d8c8b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308191436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3308191436
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1659043536
Short name T158
Test name
Test status
Simulation time 22629225 ps
CPU time 0.87 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:46 PM PDT 24
Peak memory 216012 kb
Host smart-949c81c9-e361-4842-bc3c-4366e06be80b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659043536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1659043536
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.1953050384
Short name T392
Test name
Test status
Simulation time 35204566 ps
CPU time 0.86 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 218184 kb
Host smart-bafec87d-bfa9-462c-91eb-6ec79bc61028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953050384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1953050384
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1713385720
Short name T831
Test name
Test status
Simulation time 149152665 ps
CPU time 1.92 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:36 PM PDT 24
Peak memory 218036 kb
Host smart-912877ae-9d38-4e65-a72b-de09d2be877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713385720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1713385720
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1199476487
Short name T389
Test name
Test status
Simulation time 86606472 ps
CPU time 0.85 seconds
Started Mar 24 01:06:37 PM PDT 24
Finished Mar 24 01:06:45 PM PDT 24
Peak memory 215484 kb
Host smart-c041db7f-2b44-44ca-b60f-67f8fb0a71bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199476487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1199476487
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.410264950
Short name T198
Test name
Test status
Simulation time 54303146 ps
CPU time 0.89 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 215424 kb
Host smart-08908af8-e439-4ba0-a418-053087c783f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410264950 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.410264950
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.390114280
Short name T772
Test name
Test status
Simulation time 359718938 ps
CPU time 4.09 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:50 PM PDT 24
Peak memory 216572 kb
Host smart-67853f5b-450e-464c-a388-d7631118c599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390114280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.390114280
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1057363313
Short name T594
Test name
Test status
Simulation time 136894083251 ps
CPU time 804.25 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:20:00 PM PDT 24
Peak memory 221240 kb
Host smart-ab1ddfe6-c6b2-4472-9ca6-a05f397cd70b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057363313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1057363313
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1072926897
Short name T184
Test name
Test status
Simulation time 142429382 ps
CPU time 1.35 seconds
Started Mar 24 01:06:33 PM PDT 24
Finished Mar 24 01:06:35 PM PDT 24
Peak memory 215800 kb
Host smart-1cb1136e-2fd5-4d97-a49c-d45d1d064cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072926897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1072926897
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3085395
Short name T586
Test name
Test status
Simulation time 18573801 ps
CPU time 0.87 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:45 PM PDT 24
Peak memory 206960 kb
Host smart-2fc54490-18d0-425c-9f32-5174f4af2b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3085395
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.772724151
Short name T788
Test name
Test status
Simulation time 37673337 ps
CPU time 0.86 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:35 PM PDT 24
Peak memory 215908 kb
Host smart-14fa0c40-92f3-4ea8-9858-b8057afdb278
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772724151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.772724151
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.1449196207
Short name T103
Test name
Test status
Simulation time 51715226 ps
CPU time 1.12 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:42 PM PDT 24
Peak memory 218208 kb
Host smart-1211b481-00e4-4f1a-b6cf-7aa8a2ffa118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449196207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1449196207
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.469448011
Short name T627
Test name
Test status
Simulation time 21620435 ps
CPU time 1.1 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 216520 kb
Host smart-1a0a402d-941d-4663-98ae-4f13170dd263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469448011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.469448011
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4083495274
Short name T131
Test name
Test status
Simulation time 20338234 ps
CPU time 1.14 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215876 kb
Host smart-7ad95246-4198-4460-9103-2a70f71eee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083495274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4083495274
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.116358151
Short name T442
Test name
Test status
Simulation time 17322725 ps
CPU time 0.99 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 215400 kb
Host smart-647b269d-4719-4a56-b04a-f1c0f9429085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116358151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.116358151
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.185689884
Short name T56
Test name
Test status
Simulation time 188146682 ps
CPU time 2.2 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:48 PM PDT 24
Peak memory 215384 kb
Host smart-0c62f009-4115-4070-a9e4-f84f045830e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185689884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.185689884
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.701719879
Short name T476
Test name
Test status
Simulation time 18149188852 ps
CPU time 481.58 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:14:36 PM PDT 24
Peak memory 217080 kb
Host smart-57efd0dc-d3dc-43b4-9875-a5d2369b2bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701719879 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.701719879
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1607559025
Short name T655
Test name
Test status
Simulation time 37837978 ps
CPU time 1.21 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215764 kb
Host smart-bc9a2bfa-9486-44e9-8fec-3084d02e4808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607559025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1607559025
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.630931120
Short name T661
Test name
Test status
Simulation time 16457026 ps
CPU time 0.93 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:46 PM PDT 24
Peak memory 206548 kb
Host smart-835027e0-821c-4d82-be88-90c6f58222e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630931120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.630931120
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3527071450
Short name T182
Test name
Test status
Simulation time 28391036 ps
CPU time 0.84 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:38 PM PDT 24
Peak memory 215528 kb
Host smart-51b3158c-3532-4b4d-99f4-9831e77d7283
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527071450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3527071450
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.1012929685
Short name T92
Test name
Test status
Simulation time 44304960 ps
CPU time 1.13 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 219296 kb
Host smart-0a7ef410-072a-4531-bd8a-94305299ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012929685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1012929685
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1158941246
Short name T789
Test name
Test status
Simulation time 355204974 ps
CPU time 3.49 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:44 PM PDT 24
Peak memory 217120 kb
Host smart-84ff6acd-283b-4817-ae20-cda60e37e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158941246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1158941246
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3354379425
Short name T132
Test name
Test status
Simulation time 63176397 ps
CPU time 0.79 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:41 PM PDT 24
Peak memory 215640 kb
Host smart-aeb3ae7c-b1fe-4006-8a45-ec1dbb0d22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354379425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3354379425
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2087980218
Short name T307
Test name
Test status
Simulation time 46035770 ps
CPU time 0.99 seconds
Started Mar 24 01:06:35 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 215428 kb
Host smart-d91e0ff3-b164-4949-a794-1f15c13aed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087980218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2087980218
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1221199233
Short name T148
Test name
Test status
Simulation time 547537554 ps
CPU time 3.72 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:44 PM PDT 24
Peak memory 216892 kb
Host smart-76cc90e5-27e3-491d-803b-af34a806572d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221199233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1221199233
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4139673230
Short name T609
Test name
Test status
Simulation time 40877184932 ps
CPU time 950.37 seconds
Started Mar 24 01:06:33 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 223948 kb
Host smart-8f466ce9-88c3-43f0-9399-b0acf942c615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139673230 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4139673230
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3285021082
Short name T451
Test name
Test status
Simulation time 83923020 ps
CPU time 1.21 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215752 kb
Host smart-b8283086-8e05-4462-8b00-ea065b88b45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285021082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3285021082
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.751767848
Short name T314
Test name
Test status
Simulation time 20674552 ps
CPU time 1 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:46 PM PDT 24
Peak memory 206068 kb
Host smart-d265c526-61a8-4504-85c8-b96ffb4652a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751767848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.751767848
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3126968175
Short name T621
Test name
Test status
Simulation time 11706156 ps
CPU time 0.85 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 215600 kb
Host smart-b21263c7-bf78-4931-97fc-e9fab62b5dee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126968175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3126968175
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2784618245
Short name T74
Test name
Test status
Simulation time 45666956 ps
CPU time 1.39 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 216544 kb
Host smart-6e69b5b1-13ac-4730-b9d6-7c51d80ad626
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784618245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2784618245
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3825252163
Short name T71
Test name
Test status
Simulation time 35758125 ps
CPU time 1.02 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 229800 kb
Host smart-e2a21cdc-a2fb-46e4-b581-100db17a4e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825252163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3825252163
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3562913946
Short name T507
Test name
Test status
Simulation time 51627244 ps
CPU time 1.26 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:37 PM PDT 24
Peak memory 216924 kb
Host smart-6b1b7ef2-98f1-450c-a953-3164be0b3e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562913946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3562913946
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1394076417
Short name T585
Test name
Test status
Simulation time 38171588 ps
CPU time 0.98 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 223796 kb
Host smart-a8bdadd9-0f5a-44e4-9ea9-697c53e828a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394076417 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1394076417
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1673666565
Short name T793
Test name
Test status
Simulation time 17022072 ps
CPU time 0.98 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:06:46 PM PDT 24
Peak memory 207204 kb
Host smart-fcbe0b95-88ef-4d63-8d7d-94fc47ac0500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673666565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1673666565
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2228929968
Short name T676
Test name
Test status
Simulation time 139597684 ps
CPU time 3.1 seconds
Started Mar 24 01:06:34 PM PDT 24
Finished Mar 24 01:06:39 PM PDT 24
Peak memory 215440 kb
Host smart-39be743b-918e-4937-abc0-264e9afa148f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228929968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2228929968
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3806290031
Short name T293
Test name
Test status
Simulation time 34124789864 ps
CPU time 779.36 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:19:44 PM PDT 24
Peak memory 218036 kb
Host smart-f28b7a70-0d91-404f-a476-088a9a60d5d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806290031 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3806290031
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.8120124
Short name T122
Test name
Test status
Simulation time 113929387 ps
CPU time 1.22 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215784 kb
Host smart-cbf0f7e2-3e2f-4a7a-aa73-cccebc83e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8120124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.8120124
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3876398826
Short name T826
Test name
Test status
Simulation time 16860496 ps
CPU time 0.91 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 206332 kb
Host smart-0d227623-b98b-442b-a91b-66737bdc3914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876398826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3876398826
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3636153408
Short name T780
Test name
Test status
Simulation time 16395860 ps
CPU time 0.86 seconds
Started Mar 24 01:06:36 PM PDT 24
Finished Mar 24 01:06:41 PM PDT 24
Peak memory 215556 kb
Host smart-ecb8bd2e-a0cc-4dde-8c30-313f42adde03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636153408 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3636153408
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.1937014612
Short name T70
Test name
Test status
Simulation time 21395005 ps
CPU time 1.06 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 219240 kb
Host smart-93aadfc5-9ac5-4091-bd0d-d9b5b62ccc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937014612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1937014612
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4010458834
Short name T773
Test name
Test status
Simulation time 44247910 ps
CPU time 0.97 seconds
Started Mar 24 01:06:37 PM PDT 24
Finished Mar 24 01:06:41 PM PDT 24
Peak memory 216680 kb
Host smart-e530ac70-ca95-4364-9635-b02229e5004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010458834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4010458834
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.646857954
Short name T835
Test name
Test status
Simulation time 22463629 ps
CPU time 1.12 seconds
Started Mar 24 01:06:38 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215520 kb
Host smart-0bb54ab5-72d6-4777-bf55-bc714f24cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646857954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.646857954
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1448237630
Short name T762
Test name
Test status
Simulation time 44401149 ps
CPU time 0.92 seconds
Started Mar 24 01:06:37 PM PDT 24
Finished Mar 24 01:06:45 PM PDT 24
Peak memory 215400 kb
Host smart-f1357c64-af11-4e41-8022-beae4ef8988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448237630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1448237630
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3749638132
Short name T553
Test name
Test status
Simulation time 99551479 ps
CPU time 1.19 seconds
Started Mar 24 01:06:33 PM PDT 24
Finished Mar 24 01:06:35 PM PDT 24
Peak memory 207312 kb
Host smart-870640ce-5e82-481d-a8c6-9ebeffea19b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749638132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3749638132
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.480311927
Short name T830
Test name
Test status
Simulation time 60798922382 ps
CPU time 1297.94 seconds
Started Mar 24 01:06:37 PM PDT 24
Finished Mar 24 01:28:22 PM PDT 24
Peak memory 221420 kb
Host smart-66070134-85cc-40f2-b2ce-26b96d9da1c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480311927 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.480311927
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2806420085
Short name T577
Test name
Test status
Simulation time 228844687 ps
CPU time 1.32 seconds
Started Mar 24 01:05:29 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 215776 kb
Host smart-c5bf9cbc-3a10-4609-9215-b109771ebca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806420085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2806420085
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3221094773
Short name T724
Test name
Test status
Simulation time 43716093 ps
CPU time 1.1 seconds
Started Mar 24 01:05:28 PM PDT 24
Finished Mar 24 01:05:29 PM PDT 24
Peak memory 206644 kb
Host smart-96df58dc-54ff-4696-ae10-c6626ca5b666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221094773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3221094773
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1446152063
Short name T612
Test name
Test status
Simulation time 27100631 ps
CPU time 0.88 seconds
Started Mar 24 01:05:32 PM PDT 24
Finished Mar 24 01:05:33 PM PDT 24
Peak memory 215588 kb
Host smart-e2847e22-8c46-4816-9282-afe591ae7598
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446152063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1446152063
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1929835685
Short name T611
Test name
Test status
Simulation time 420911647 ps
CPU time 1.29 seconds
Started Mar 24 01:05:32 PM PDT 24
Finished Mar 24 01:05:34 PM PDT 24
Peak memory 216516 kb
Host smart-b1fe135a-bed4-44f6-b1b6-da8b574dd45b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929835685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1929835685
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.603147448
Short name T362
Test name
Test status
Simulation time 79908360 ps
CPU time 0.82 seconds
Started Mar 24 01:05:28 PM PDT 24
Finished Mar 24 01:05:29 PM PDT 24
Peak memory 217876 kb
Host smart-b51cfa8e-b4c7-489a-a73d-4c5c88ab2749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603147448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.603147448
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2183629517
Short name T453
Test name
Test status
Simulation time 72166034 ps
CPU time 1.32 seconds
Started Mar 24 01:05:29 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 217996 kb
Host smart-bfd08138-edcc-41cf-9770-4ce6a39b48eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183629517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2183629517
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1423206193
Short name T485
Test name
Test status
Simulation time 25338184 ps
CPU time 1.07 seconds
Started Mar 24 01:05:30 PM PDT 24
Finished Mar 24 01:05:32 PM PDT 24
Peak memory 224020 kb
Host smart-4800ce8c-21b6-4368-8fd0-fc81e1bee808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423206193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1423206193
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1494058641
Short name T798
Test name
Test status
Simulation time 19343284 ps
CPU time 0.98 seconds
Started Mar 24 01:05:29 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 207196 kb
Host smart-7baea2b9-fd4f-436d-9249-1f26bde50b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494058641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1494058641
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.549403189
Short name T49
Test name
Test status
Simulation time 2948673124 ps
CPU time 4.21 seconds
Started Mar 24 01:05:28 PM PDT 24
Finished Mar 24 01:05:32 PM PDT 24
Peak memory 233820 kb
Host smart-5f1bad0d-d3e9-4137-9ce2-b777802a707e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549403189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.549403189
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3298812977
Short name T333
Test name
Test status
Simulation time 19195121 ps
CPU time 1.01 seconds
Started Mar 24 01:05:28 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 215404 kb
Host smart-218f8cf7-9e36-474f-9a90-def6a7351635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298812977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3298812977
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4239449690
Short name T212
Test name
Test status
Simulation time 869194293 ps
CPU time 5.12 seconds
Started Mar 24 01:05:32 PM PDT 24
Finished Mar 24 01:05:37 PM PDT 24
Peak memory 215400 kb
Host smart-1d7ab95f-cced-4707-9ba2-062dd6b9bfe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239449690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4239449690
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2313907744
Short name T729
Test name
Test status
Simulation time 336493250973 ps
CPU time 751.15 seconds
Started Mar 24 01:05:32 PM PDT 24
Finished Mar 24 01:18:03 PM PDT 24
Peak memory 223808 kb
Host smart-7f98d5ef-cee9-435a-8d28-75e5e3fec901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313907744 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2313907744
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.3984243718
Short name T156
Test name
Test status
Simulation time 26055526 ps
CPU time 0.89 seconds
Started Mar 24 01:06:42 PM PDT 24
Finished Mar 24 01:06:48 PM PDT 24
Peak memory 206120 kb
Host smart-92c94210-b456-483d-80e0-7df0805d3601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984243718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3984243718
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1359980497
Short name T170
Test name
Test status
Simulation time 17149430 ps
CPU time 0.81 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 216084 kb
Host smart-e8f3580d-c6e1-424c-8ba0-4e1f293116a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359980497 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1359980497
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2151740452
Short name T89
Test name
Test status
Simulation time 131741131 ps
CPU time 1.29 seconds
Started Mar 24 01:06:45 PM PDT 24
Finished Mar 24 01:06:49 PM PDT 24
Peak memory 216716 kb
Host smart-7cacb044-1056-4774-88fc-040a72b728d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151740452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2151740452
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1984092387
Short name T757
Test name
Test status
Simulation time 21447587 ps
CPU time 0.89 seconds
Started Mar 24 01:06:42 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 217888 kb
Host smart-f03684c3-6538-4357-afb8-1877ed5c1e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984092387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1984092387
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.376358127
Short name T692
Test name
Test status
Simulation time 114227056 ps
CPU time 1.6 seconds
Started Mar 24 01:06:37 PM PDT 24
Finished Mar 24 01:06:44 PM PDT 24
Peak memory 218208 kb
Host smart-4674cfba-e0d6-4b68-8a8c-a19d4d239cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376358127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.376358127
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1213785477
Short name T646
Test name
Test status
Simulation time 47108943 ps
CPU time 0.98 seconds
Started Mar 24 01:06:42 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 223908 kb
Host smart-fe3e70fc-7a03-4cc4-92ae-d096efcd0754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213785477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1213785477
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3032124374
Short name T622
Test name
Test status
Simulation time 50044479 ps
CPU time 0.95 seconds
Started Mar 24 01:06:37 PM PDT 24
Finished Mar 24 01:06:41 PM PDT 24
Peak memory 215376 kb
Host smart-7dbce29f-dc50-4d8d-a6ac-0cd6831dc3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032124374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3032124374
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.751455428
Short name T419
Test name
Test status
Simulation time 137808829 ps
CPU time 1.41 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215332 kb
Host smart-d121a62d-6e68-4d46-b0ec-21032a99953f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751455428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.751455428
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.566482757
Short name T638
Test name
Test status
Simulation time 193449153921 ps
CPU time 1224.83 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:27:11 PM PDT 24
Peak memory 223332 kb
Host smart-f97a79e0-984d-459b-9c2a-b6a164f7edee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566482757 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.566482757
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3098272148
Short name T709
Test name
Test status
Simulation time 49588399 ps
CPU time 1.11 seconds
Started Mar 24 01:06:45 PM PDT 24
Finished Mar 24 01:06:48 PM PDT 24
Peak memory 215780 kb
Host smart-726154f1-ccc0-45bc-bd90-55addee621ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098272148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3098272148
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3536419698
Short name T549
Test name
Test status
Simulation time 91128003 ps
CPU time 0.96 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 207080 kb
Host smart-220b04e1-bcd3-4bed-9193-b354436152a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536419698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3536419698
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.137862399
Short name T497
Test name
Test status
Simulation time 31842310 ps
CPU time 0.85 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215508 kb
Host smart-f008d506-19ff-43f0-af1e-8b20cdfd58c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137862399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.137862399
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4009338076
Short name T37
Test name
Test status
Simulation time 104022490 ps
CPU time 1.21 seconds
Started Mar 24 01:06:42 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 217644 kb
Host smart-e747fea8-6fa0-4333-9887-31c61b0bc887
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009338076 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4009338076
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_genbits.1864043769
Short name T783
Test name
Test status
Simulation time 56009313 ps
CPU time 1.76 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:48 PM PDT 24
Peak memory 217892 kb
Host smart-8509904c-4051-4e8a-813d-63b12003943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864043769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1864043769
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2140881020
Short name T145
Test name
Test status
Simulation time 19990016 ps
CPU time 1.12 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215756 kb
Host smart-8bb12e05-8727-489b-bc49-b45097f80f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140881020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2140881020
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.932902019
Short name T700
Test name
Test status
Simulation time 25022729 ps
CPU time 1 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:46 PM PDT 24
Peak memory 215424 kb
Host smart-f8e2ade9-11db-441c-b751-da5892ec56f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932902019 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.932902019
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3499568538
Short name T42
Test name
Test status
Simulation time 1569082649 ps
CPU time 5.84 seconds
Started Mar 24 01:06:39 PM PDT 24
Finished Mar 24 01:06:50 PM PDT 24
Peak memory 216620 kb
Host smart-4d32ad85-fad3-4ba2-83e9-d79853eefba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499568538 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3499568538
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1106018139
Short name T756
Test name
Test status
Simulation time 123014256535 ps
CPU time 858.28 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:21:04 PM PDT 24
Peak memory 221404 kb
Host smart-706f29fb-6750-4c81-b82e-7df5f73e77e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106018139 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1106018139
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1052467894
Short name T68
Test name
Test status
Simulation time 77449332 ps
CPU time 1.19 seconds
Started Mar 24 01:06:49 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 215752 kb
Host smart-80e5a44b-03e8-4b76-afbf-c40a18d2b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052467894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1052467894
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2147196035
Short name T337
Test name
Test status
Simulation time 22464117 ps
CPU time 1.18 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 206424 kb
Host smart-42f5394e-0f81-4d91-8935-48801493fd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147196035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2147196035
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2548605041
Short name T660
Test name
Test status
Simulation time 29136659 ps
CPU time 0.82 seconds
Started Mar 24 01:06:48 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 215968 kb
Host smart-d9e119f7-356b-4ab2-a2f7-853581a5b219
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548605041 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2548605041
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4022224243
Short name T172
Test name
Test status
Simulation time 63517482 ps
CPU time 1.04 seconds
Started Mar 24 01:06:48 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 216604 kb
Host smart-0e389a58-92b4-4dd9-9c8a-6a02cd123566
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022224243 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4022224243
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3074100663
Short name T98
Test name
Test status
Simulation time 20446563 ps
CPU time 1.23 seconds
Started Mar 24 01:06:47 PM PDT 24
Finished Mar 24 01:06:51 PM PDT 24
Peak memory 232564 kb
Host smart-c7db4851-394e-4291-be5b-4a364de9319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074100663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3074100663
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1691127594
Short name T727
Test name
Test status
Simulation time 61998136 ps
CPU time 1.19 seconds
Started Mar 24 01:06:46 PM PDT 24
Finished Mar 24 01:06:49 PM PDT 24
Peak memory 216656 kb
Host smart-152e91bb-aae6-4ca4-b698-20900e89b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691127594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1691127594
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4246137473
Short name T125
Test name
Test status
Simulation time 30306172 ps
CPU time 0.89 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215784 kb
Host smart-bb74910b-b86b-45cf-9802-a120d2f29ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246137473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4246137473
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3195521765
Short name T347
Test name
Test status
Simulation time 17789416 ps
CPU time 1.05 seconds
Started Mar 24 01:06:41 PM PDT 24
Finished Mar 24 01:06:47 PM PDT 24
Peak memory 215348 kb
Host smart-9f774f3b-e6e2-44ed-ac26-3b633240609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195521765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3195521765
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.618045047
Short name T808
Test name
Test status
Simulation time 22521827522 ps
CPU time 592.9 seconds
Started Mar 24 01:06:40 PM PDT 24
Finished Mar 24 01:16:39 PM PDT 24
Peak memory 218108 kb
Host smart-22cae019-55b7-40dc-aae3-48f6031c67cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618045047 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.618045047
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2105084655
Short name T152
Test name
Test status
Simulation time 57821897 ps
CPU time 1.35 seconds
Started Mar 24 01:06:49 PM PDT 24
Finished Mar 24 01:06:53 PM PDT 24
Peak memory 215784 kb
Host smart-53ac0358-c6a7-42f3-9e21-5d922faff228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105084655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2105084655
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1447877298
Short name T744
Test name
Test status
Simulation time 38780903 ps
CPU time 0.88 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:57 PM PDT 24
Peak memory 205916 kb
Host smart-3fad122c-5541-4063-b408-10b3300353ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447877298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1447877298
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3652059282
Short name T481
Test name
Test status
Simulation time 28843593 ps
CPU time 0.79 seconds
Started Mar 24 01:06:50 PM PDT 24
Finished Mar 24 01:06:53 PM PDT 24
Peak memory 215476 kb
Host smart-e07a9a8d-71af-4cde-aced-c1a92aa4795f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652059282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3652059282
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.45793959
Short name T164
Test name
Test status
Simulation time 176201993 ps
CPU time 1.03 seconds
Started Mar 24 01:06:47 PM PDT 24
Finished Mar 24 01:06:50 PM PDT 24
Peak memory 216604 kb
Host smart-ba58028d-573e-4e70-849b-d0c6fa689226
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45793959 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_dis
able_auto_req_mode.45793959
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1415606539
Short name T93
Test name
Test status
Simulation time 66396490 ps
CPU time 1.24 seconds
Started Mar 24 01:06:50 PM PDT 24
Finished Mar 24 01:06:54 PM PDT 24
Peak memory 224460 kb
Host smart-3aad9845-d717-42a2-9bc7-799980809aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415606539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1415606539
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1859986843
Short name T504
Test name
Test status
Simulation time 35035594 ps
CPU time 1.4 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:57 PM PDT 24
Peak memory 216688 kb
Host smart-7148e2ad-1cdf-4ceb-bc5c-5e9c05a47325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859986843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1859986843
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1387776404
Short name T6
Test name
Test status
Simulation time 21521134 ps
CPU time 1.13 seconds
Started Mar 24 01:06:48 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 215696 kb
Host smart-be1b74e4-8285-4749-8701-98783e8ff6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387776404 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1387776404
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.4093504451
Short name T397
Test name
Test status
Simulation time 25649333 ps
CPU time 0.93 seconds
Started Mar 24 01:06:49 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 215428 kb
Host smart-2a62ac61-11b9-4c56-9aed-a353d9e0c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093504451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.4093504451
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1057396300
Short name T510
Test name
Test status
Simulation time 601825970 ps
CPU time 2.99 seconds
Started Mar 24 01:06:47 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 216652 kb
Host smart-11b349eb-65a6-4a5f-be29-f036733b192f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057396300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1057396300
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.718422119
Short name T540
Test name
Test status
Simulation time 165645139052 ps
CPU time 1102.26 seconds
Started Mar 24 01:06:51 PM PDT 24
Finished Mar 24 01:25:15 PM PDT 24
Peak memory 223732 kb
Host smart-1c1324cb-3938-4a0c-bf27-0bfcd05e3315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718422119 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.718422119
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3993053983
Short name T668
Test name
Test status
Simulation time 67953393 ps
CPU time 1.1 seconds
Started Mar 24 01:06:49 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 215804 kb
Host smart-bd2bc825-b5fe-4b34-b3b6-d6167b3802df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993053983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3993053983
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1539032702
Short name T730
Test name
Test status
Simulation time 23611255 ps
CPU time 1.15 seconds
Started Mar 24 01:06:49 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 206628 kb
Host smart-95120fac-3510-4e6a-a693-2be1e2e9a5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539032702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1539032702
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3916236685
Short name T26
Test name
Test status
Simulation time 10925708 ps
CPU time 0.87 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215992 kb
Host smart-c949a292-a129-482a-a4eb-a509e27203ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916236685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3916236685
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2513774265
Short name T90
Test name
Test status
Simulation time 42455370 ps
CPU time 1.04 seconds
Started Mar 24 01:06:48 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 217016 kb
Host smart-bd802a03-0352-43f0-88a2-06a0830a9c0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513774265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2513774265
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1817447189
Short name T87
Test name
Test status
Simulation time 27790966 ps
CPU time 1.24 seconds
Started Mar 24 01:06:48 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 220096 kb
Host smart-939ddf71-470e-4d55-8d66-9c4495c32de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817447189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1817447189
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1641085045
Short name T256
Test name
Test status
Simulation time 71752095 ps
CPU time 1.66 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 218068 kb
Host smart-5f352489-bca1-4db9-92bc-b6c4c4c3c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641085045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1641085045
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3891268560
Short name T711
Test name
Test status
Simulation time 38303029 ps
CPU time 0.98 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 223920 kb
Host smart-81b6e6d6-f891-4f27-8fbb-204351795055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891268560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3891268560
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2729928398
Short name T409
Test name
Test status
Simulation time 39170573 ps
CPU time 0.87 seconds
Started Mar 24 01:06:47 PM PDT 24
Finished Mar 24 01:06:51 PM PDT 24
Peak memory 215416 kb
Host smart-ee562b44-8d09-4231-90b3-163560b8edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729928398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2729928398
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.714449086
Short name T458
Test name
Test status
Simulation time 105905349 ps
CPU time 2.76 seconds
Started Mar 24 01:06:49 PM PDT 24
Finished Mar 24 01:06:54 PM PDT 24
Peak memory 216544 kb
Host smart-6680a64e-3652-4a21-9df7-3a320ea32d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714449086 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.714449086
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2613011099
Short name T494
Test name
Test status
Simulation time 138673072512 ps
CPU time 1195.85 seconds
Started Mar 24 01:06:51 PM PDT 24
Finished Mar 24 01:26:48 PM PDT 24
Peak memory 224096 kb
Host smart-8040ba25-394f-4d97-bbf0-4ca5edf4705f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613011099 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2613011099
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.2997285374
Short name T386
Test name
Test status
Simulation time 20477774 ps
CPU time 0.99 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 206964 kb
Host smart-afba6854-75fa-4e62-8343-ed98b300380d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997285374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2997285374
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_err.4043480447
Short name T817
Test name
Test status
Simulation time 33356105 ps
CPU time 0.9 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 218244 kb
Host smart-c57a9e52-7b75-470e-bda7-c65b4f4e4020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043480447 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.4043480447
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1359676588
Short name T592
Test name
Test status
Simulation time 34241165 ps
CPU time 1.33 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 217076 kb
Host smart-01c78491-6884-4afd-835f-51053e11b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359676588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1359676588
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2678347070
Short name T129
Test name
Test status
Simulation time 23599994 ps
CPU time 0.98 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 215788 kb
Host smart-536dc735-2e3e-47d0-a3bb-a86cfebbd2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678347070 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2678347070
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3641192463
Short name T597
Test name
Test status
Simulation time 42755686 ps
CPU time 0.9 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 214420 kb
Host smart-57c7fe7f-5a33-47af-9985-62124949babe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641192463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3641192463
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2095930239
Short name T211
Test name
Test status
Simulation time 543323692 ps
CPU time 3.23 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:03 PM PDT 24
Peak memory 216636 kb
Host smart-72ca2382-7d38-4b5f-bb5e-8ae1f5393bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095930239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2095930239
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.77627830
Short name T202
Test name
Test status
Simulation time 286830282385 ps
CPU time 1646.08 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:34:26 PM PDT 24
Peak memory 224552 kb
Host smart-50532796-e5f4-4eaa-9d89-e4c548363455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77627830 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.77627830
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3110698754
Short name T710
Test name
Test status
Simulation time 44155790 ps
CPU time 1.16 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 215780 kb
Host smart-dbae548a-b369-4e58-8f1e-f1e63f076200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110698754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3110698754
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3116289260
Short name T440
Test name
Test status
Simulation time 51404753 ps
CPU time 1.05 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:56 PM PDT 24
Peak memory 206140 kb
Host smart-ba749b0b-124e-493f-b166-4435aaf354a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116289260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3116289260
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1055306050
Short name T441
Test name
Test status
Simulation time 31564261 ps
CPU time 0.86 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 215640 kb
Host smart-d4407b2f-97b2-46a3-a144-abe22131b5ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055306050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1055306050
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.188464164
Short name T712
Test name
Test status
Simulation time 128324593 ps
CPU time 1.13 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 216272 kb
Host smart-e5d796f4-e0a3-46e2-9da9-5d309d799839
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188464164 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.188464164
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3947108386
Short name T114
Test name
Test status
Simulation time 21121941 ps
CPU time 1.06 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 231252 kb
Host smart-4e828187-074d-4ea8-99c0-309b73d2d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947108386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3947108386
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1943934777
Short name T705
Test name
Test status
Simulation time 91863565 ps
CPU time 3.23 seconds
Started Mar 24 01:06:53 PM PDT 24
Finished Mar 24 01:06:58 PM PDT 24
Peak memory 218628 kb
Host smart-a07b396a-720b-453f-97c3-a40bb971c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943934777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1943934777
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3939890590
Short name T127
Test name
Test status
Simulation time 33349181 ps
CPU time 0.9 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 215564 kb
Host smart-26201441-3a31-41f6-9be1-b4b2e242c557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939890590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3939890590
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2403881703
Short name T564
Test name
Test status
Simulation time 23410099 ps
CPU time 1.01 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215416 kb
Host smart-a0e325cb-b567-4087-9910-25efc934e625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403881703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2403881703
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2157823263
Short name T50
Test name
Test status
Simulation time 200733515 ps
CPU time 4.22 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:04 PM PDT 24
Peak memory 216756 kb
Host smart-793e693a-9e59-45bf-8a0e-73cb600b0dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157823263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2157823263
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3048200727
Short name T399
Test name
Test status
Simulation time 29140956505 ps
CPU time 322.22 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:12:32 PM PDT 24
Peak memory 218392 kb
Host smart-b479a80a-2ec6-4fb5-a785-30200a2c0d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048200727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3048200727
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3578350188
Short name T179
Test name
Test status
Simulation time 24771381 ps
CPU time 1.22 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215776 kb
Host smart-fb6cffcb-88aa-4b9f-8b97-e176037d4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578350188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3578350188
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.950532937
Short name T487
Test name
Test status
Simulation time 16099937 ps
CPU time 0.94 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 206660 kb
Host smart-a2286d19-8e72-46b8-a839-113b6ced0bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950532937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.950532937
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1880102149
Short name T802
Test name
Test status
Simulation time 36852243 ps
CPU time 0.79 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:57 PM PDT 24
Peak memory 215492 kb
Host smart-d6bd0289-dced-45d4-9b29-bdd27fab10b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880102149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1880102149
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.447707190
Short name T324
Test name
Test status
Simulation time 61451542 ps
CPU time 0.81 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 217780 kb
Host smart-dea3241e-3e7d-47df-b3c5-702de20e7b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447707190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.447707190
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.188193507
Short name T552
Test name
Test status
Simulation time 76344248 ps
CPU time 1.43 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 215692 kb
Host smart-bfc10e7c-1ab0-4ac2-8c3c-f740daa86ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188193507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.188193507
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1529442350
Short name T787
Test name
Test status
Simulation time 29354268 ps
CPU time 0.98 seconds
Started Mar 24 01:06:53 PM PDT 24
Finished Mar 24 01:06:54 PM PDT 24
Peak memory 215516 kb
Host smart-2d894907-da6e-4c38-b292-59fde30ce047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529442350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1529442350
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2572629678
Short name T363
Test name
Test status
Simulation time 17679944 ps
CPU time 1.03 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215420 kb
Host smart-60941841-c3a0-409f-80d1-cbd563ce8c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572629678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2572629678
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3029819564
Short name T216
Test name
Test status
Simulation time 644865580 ps
CPU time 3.78 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:14 PM PDT 24
Peak memory 216620 kb
Host smart-c23dc76a-be6b-42ad-a0e7-1ad8355b0f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029819564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3029819564
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3867262350
Short name T201
Test name
Test status
Simulation time 27815630673 ps
CPU time 620.1 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:17:20 PM PDT 24
Peak memory 216712 kb
Host smart-b4963eed-cd98-4446-8362-92346c22a240
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867262350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3867262350
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3825568721
Short name T271
Test name
Test status
Simulation time 67027674 ps
CPU time 1.16 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:57 PM PDT 24
Peak memory 215816 kb
Host smart-dbd14f89-bee7-4011-a3d8-325607cd7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825568721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3825568721
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.4121815017
Short name T454
Test name
Test status
Simulation time 23580578 ps
CPU time 0.87 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 206972 kb
Host smart-74377fc5-702c-4b45-bcd1-a5aa607b482d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121815017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4121815017
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3850569564
Short name T815
Test name
Test status
Simulation time 28993570 ps
CPU time 0.9 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 215600 kb
Host smart-ae81bb30-1a9d-486b-88e2-b7bb336faf65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850569564 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3850569564
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3389949939
Short name T681
Test name
Test status
Simulation time 28013686 ps
CPU time 1.12 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 216696 kb
Host smart-68435f09-5ff7-41e8-8aff-bee79ff8fe22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389949939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3389949939
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3046759918
Short name T822
Test name
Test status
Simulation time 32744051 ps
CPU time 0.96 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 232368 kb
Host smart-bf754814-2771-48a7-ad57-a559e7a09df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046759918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3046759918
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.373132009
Short name T39
Test name
Test status
Simulation time 65189366 ps
CPU time 1.06 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 216820 kb
Host smart-feb23b1f-0c69-47bd-b813-ce992956c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373132009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.373132009
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2521301182
Short name T379
Test name
Test status
Simulation time 34788592 ps
CPU time 0.88 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 215632 kb
Host smart-900dd699-2d70-4cc9-9813-219d9c8e859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521301182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2521301182
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.357621074
Short name T387
Test name
Test status
Simulation time 41871936 ps
CPU time 0.97 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215612 kb
Host smart-b384b653-4394-48db-8c7c-9d5ed41340a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357621074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.357621074
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1770735297
Short name T477
Test name
Test status
Simulation time 2361880662 ps
CPU time 4.47 seconds
Started Mar 24 01:06:52 PM PDT 24
Finished Mar 24 01:06:57 PM PDT 24
Peak memory 215640 kb
Host smart-0c903c5f-84cc-4622-ae9b-2b847aa7c818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770735297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1770735297
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2872119715
Short name T52
Test name
Test status
Simulation time 237666182751 ps
CPU time 1761.17 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:36:21 PM PDT 24
Peak memory 228052 kb
Host smart-83fbe372-6d8b-4900-8a78-39141fe40fb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872119715 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2872119715
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.377706343
Short name T263
Test name
Test status
Simulation time 37235710 ps
CPU time 1.26 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 215836 kb
Host smart-ccde1fb9-9423-453b-9fb7-e2fec3787541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377706343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.377706343
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.250807185
Short name T335
Test name
Test status
Simulation time 21657565 ps
CPU time 1.05 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 206732 kb
Host smart-0870bea2-2515-4ecc-9b25-ea37c7b00796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250807185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.250807185
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3429067943
Short name T484
Test name
Test status
Simulation time 48323186 ps
CPU time 0.81 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 215316 kb
Host smart-b3c99920-3641-409e-b299-3f0ef9207aed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429067943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3429067943
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4218115715
Short name T412
Test name
Test status
Simulation time 49784303 ps
CPU time 1.37 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 215780 kb
Host smart-35c08c74-48d5-474b-b162-5d3c129a0ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218115715 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4218115715
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_genbits.4195911793
Short name T395
Test name
Test status
Simulation time 124132884 ps
CPU time 1.74 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:57 PM PDT 24
Peak memory 218072 kb
Host smart-f3445163-018b-44d9-9c07-4eeda94b2f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195911793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4195911793
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1041844612
Short name T139
Test name
Test status
Simulation time 21654873 ps
CPU time 1 seconds
Started Mar 24 01:06:54 PM PDT 24
Finished Mar 24 01:06:56 PM PDT 24
Peak memory 215868 kb
Host smart-9eb635a8-e171-4f12-a48f-2c63dd835c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041844612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1041844612
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2982347703
Short name T707
Test name
Test status
Simulation time 46564374 ps
CPU time 0.99 seconds
Started Mar 24 01:06:57 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 207200 kb
Host smart-096c1be9-5acc-4ff6-8fed-e36ebfceb458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982347703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2982347703
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3833492546
Short name T746
Test name
Test status
Simulation time 1160941725 ps
CPU time 3.92 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 215384 kb
Host smart-cf00a5f9-3c78-499f-803b-4205e0dfdc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833492546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3833492546
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.4292686523
Short name T23
Test name
Test status
Simulation time 96458403656 ps
CPU time 1063.14 seconds
Started Mar 24 01:06:55 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 223748 kb
Host smart-50007cd3-5234-4907-a671-6f4135957070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292686523 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.4292686523
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3474731546
Short name T16
Test name
Test status
Simulation time 46096007 ps
CPU time 1.17 seconds
Started Mar 24 01:05:28 PM PDT 24
Finished Mar 24 01:05:29 PM PDT 24
Peak memory 215804 kb
Host smart-54593374-5512-4174-a531-993055eb7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474731546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3474731546
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2995265379
Short name T368
Test name
Test status
Simulation time 236914229 ps
CPU time 0.92 seconds
Started Mar 24 01:05:34 PM PDT 24
Finished Mar 24 01:05:35 PM PDT 24
Peak memory 206752 kb
Host smart-707c504d-959a-4b1a-b885-b5ba4c5d1cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995265379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2995265379
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2518629416
Short name T100
Test name
Test status
Simulation time 10787347 ps
CPU time 0.86 seconds
Started Mar 24 01:05:33 PM PDT 24
Finished Mar 24 01:05:34 PM PDT 24
Peak memory 215996 kb
Host smart-affb2073-0fd9-462c-8bd9-4cdfa9347fa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518629416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2518629416
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1568248468
Short name T298
Test name
Test status
Simulation time 27953571 ps
CPU time 1.02 seconds
Started Mar 24 01:05:34 PM PDT 24
Finished Mar 24 01:05:35 PM PDT 24
Peak memory 217776 kb
Host smart-9b8247e7-5933-415c-abb1-0c22b6b52d73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568248468 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1568248468
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3282515680
Short name T43
Test name
Test status
Simulation time 29035708 ps
CPU time 1.3 seconds
Started Mar 24 01:05:29 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 233484 kb
Host smart-b7e94f9e-2701-4117-b240-e7250ce2e246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282515680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3282515680
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2271488796
Short name T275
Test name
Test status
Simulation time 121161565 ps
CPU time 1.31 seconds
Started Mar 24 01:05:36 PM PDT 24
Finished Mar 24 01:05:37 PM PDT 24
Peak memory 218316 kb
Host smart-d6bea9fc-a4fd-4625-82ca-817595865059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271488796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2271488796
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.78663886
Short name T25
Test name
Test status
Simulation time 36031296 ps
CPU time 0.93 seconds
Started Mar 24 01:05:32 PM PDT 24
Finished Mar 24 01:05:33 PM PDT 24
Peak memory 215708 kb
Host smart-c2bb625f-868f-4c98-bad4-4edc70eacb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78663886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.78663886
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1146045724
Short name T528
Test name
Test status
Simulation time 73006972 ps
CPU time 0.93 seconds
Started Mar 24 01:05:29 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 207236 kb
Host smart-8a3abe4f-f4c6-4164-a061-3424527c9dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146045724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1146045724
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4131763024
Short name T435
Test name
Test status
Simulation time 66478797 ps
CPU time 0.92 seconds
Started Mar 24 01:05:30 PM PDT 24
Finished Mar 24 01:05:31 PM PDT 24
Peak memory 215456 kb
Host smart-af4771ee-5c4a-41fa-9846-32a7c3684213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131763024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4131763024
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1643148432
Short name T529
Test name
Test status
Simulation time 76512467 ps
CPU time 1.33 seconds
Started Mar 24 01:05:31 PM PDT 24
Finished Mar 24 01:05:33 PM PDT 24
Peak memory 215396 kb
Host smart-0d1d84ff-048d-4d37-863e-7e6b3c4705f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643148432 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1643148432
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.52415602
Short name T509
Test name
Test status
Simulation time 162341479776 ps
CPU time 1049.28 seconds
Started Mar 24 01:05:32 PM PDT 24
Finished Mar 24 01:23:01 PM PDT 24
Peak memory 222300 kb
Host smart-7d85a6af-41fb-499a-a184-b40255171201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52415602 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.52415602
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2965265144
Short name T570
Test name
Test status
Simulation time 80387062 ps
CPU time 0.85 seconds
Started Mar 24 01:07:00 PM PDT 24
Finished Mar 24 01:07:03 PM PDT 24
Peak memory 218124 kb
Host smart-3c4f9f49-265c-4ccb-8dcf-1e72aeecdd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965265144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2965265144
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.586149658
Short name T775
Test name
Test status
Simulation time 24723783 ps
CPU time 1.16 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 216856 kb
Host smart-2651c0f7-6e06-445f-8b17-19ac9ddea763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586149658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.586149658
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.442899609
Short name T424
Test name
Test status
Simulation time 20032837 ps
CPU time 1.02 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:02 PM PDT 24
Peak memory 223132 kb
Host smart-6f8e39c5-794d-47ea-9a76-19351fb5075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442899609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.442899609
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4261317150
Short name T468
Test name
Test status
Simulation time 39461986 ps
CPU time 1.43 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 216564 kb
Host smart-ee735869-e8a0-4a7b-84c2-33f3ce43609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261317150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4261317150
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3650325240
Short name T117
Test name
Test status
Simulation time 37525815 ps
CPU time 0.98 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 231176 kb
Host smart-28d32178-5bac-493f-bd97-cd85f2cf7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650325240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3650325240
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1121069703
Short name T732
Test name
Test status
Simulation time 54418273 ps
CPU time 1 seconds
Started Mar 24 01:06:56 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 215848 kb
Host smart-eb495fe5-c813-4caa-b609-1d65eba18891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121069703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1121069703
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.489413546
Short name T733
Test name
Test status
Simulation time 23615697 ps
CPU time 0.96 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 218080 kb
Host smart-6f2887f6-9f80-41d2-b696-0f835d41a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489413546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.489413546
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2267948340
Short name T795
Test name
Test status
Simulation time 96539688 ps
CPU time 1.15 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 216604 kb
Host smart-57d8783e-b570-4fa7-b037-b1b8f36c5db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267948340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2267948340
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1793694026
Short name T800
Test name
Test status
Simulation time 208306066 ps
CPU time 0.97 seconds
Started Mar 24 01:07:00 PM PDT 24
Finished Mar 24 01:07:03 PM PDT 24
Peak memory 219540 kb
Host smart-7a9999e9-4746-4aee-8eb6-90de448efa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793694026 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1793694026
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.766561568
Short name T411
Test name
Test status
Simulation time 30716595 ps
CPU time 1.28 seconds
Started Mar 24 01:06:59 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 218056 kb
Host smart-875e1d91-9ea2-4757-a1f5-70b11cd6c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766561568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.766561568
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.4046088810
Short name T84
Test name
Test status
Simulation time 19403735 ps
CPU time 1.09 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 218180 kb
Host smart-d04edf85-3915-45a8-952b-5317c66d709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046088810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4046088810
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1303379902
Short name T276
Test name
Test status
Simulation time 80773456 ps
CPU time 1.38 seconds
Started Mar 24 01:06:59 PM PDT 24
Finished Mar 24 01:07:02 PM PDT 24
Peak memory 218372 kb
Host smart-08e10f7a-6842-46af-b5df-20b99d117156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303379902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1303379902
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3623298754
Short name T437
Test name
Test status
Simulation time 37464272 ps
CPU time 0.87 seconds
Started Mar 24 01:06:58 PM PDT 24
Finished Mar 24 01:07:00 PM PDT 24
Peak memory 222964 kb
Host smart-7876662a-7668-447c-a744-c9a638936b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623298754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3623298754
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3290471227
Short name T624
Test name
Test status
Simulation time 23542577 ps
CPU time 1.15 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 216700 kb
Host smart-3d548298-3b71-4db0-8fa5-9c2ed764cbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290471227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3290471227
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3830033775
Short name T673
Test name
Test status
Simulation time 22569380 ps
CPU time 0.93 seconds
Started Mar 24 01:06:59 PM PDT 24
Finished Mar 24 01:07:02 PM PDT 24
Peak memory 217976 kb
Host smart-66dc5feb-7fd0-46d2-93c8-91b2d2f405d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830033775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3830033775
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3512371215
Short name T340
Test name
Test status
Simulation time 67234974 ps
CPU time 1.08 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 216736 kb
Host smart-c1e23114-8d19-4a93-ac49-1ffd5e2b049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512371215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3512371215
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1081951422
Short name T814
Test name
Test status
Simulation time 22453277 ps
CPU time 1.16 seconds
Started Mar 24 01:07:00 PM PDT 24
Finished Mar 24 01:07:03 PM PDT 24
Peak memory 218332 kb
Host smart-3e32f177-812f-42fd-b570-71e0d77ec16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081951422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1081951422
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1094691422
Short name T296
Test name
Test status
Simulation time 70648809 ps
CPU time 1.68 seconds
Started Mar 24 01:06:59 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 217884 kb
Host smart-13d01ecd-d4c0-45e5-857d-6fdae1ed2b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094691422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1094691422
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3193573257
Short name T44
Test name
Test status
Simulation time 72130200 ps
CPU time 1.18 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 233684 kb
Host smart-96b0bbed-bc87-4c0e-bcaa-fee6a2b0ab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193573257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3193573257
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4279981295
Short name T443
Test name
Test status
Simulation time 32165484 ps
CPU time 1.49 seconds
Started Mar 24 01:06:59 PM PDT 24
Finished Mar 24 01:07:01 PM PDT 24
Peak memory 218192 kb
Host smart-becf9de6-4041-41d8-8c2b-2d9a57095171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279981295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4279981295
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3385724362
Short name T101
Test name
Test status
Simulation time 29985540 ps
CPU time 1.28 seconds
Started Mar 24 01:05:35 PM PDT 24
Finished Mar 24 01:05:37 PM PDT 24
Peak memory 215732 kb
Host smart-f31835fd-edac-480c-be59-e4865129c502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385724362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3385724362
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1895749442
Short name T521
Test name
Test status
Simulation time 28569434 ps
CPU time 0.93 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 207056 kb
Host smart-830b7ec1-614f-476d-b98a-d3327381f49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895749442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1895749442
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.336009048
Short name T459
Test name
Test status
Simulation time 30171254 ps
CPU time 0.85 seconds
Started Mar 24 01:05:34 PM PDT 24
Finished Mar 24 01:05:35 PM PDT 24
Peak memory 215596 kb
Host smart-ba7771c8-f7eb-4719-b9e2-8e90d927e249
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336009048 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.336009048
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3601908820
Short name T67
Test name
Test status
Simulation time 24083523 ps
CPU time 1.01 seconds
Started Mar 24 01:05:35 PM PDT 24
Finished Mar 24 01:05:37 PM PDT 24
Peak memory 216628 kb
Host smart-389b5975-9f6c-442f-b938-4537e5ad4a01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601908820 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3601908820
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2186839537
Short name T163
Test name
Test status
Simulation time 32059503 ps
CPU time 0.86 seconds
Started Mar 24 01:05:33 PM PDT 24
Finished Mar 24 01:05:34 PM PDT 24
Peak memory 217920 kb
Host smart-03ad1b31-81a4-4097-9e7b-ff526776635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186839537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2186839537
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.69555074
Short name T608
Test name
Test status
Simulation time 210205138 ps
CPU time 1.21 seconds
Started Mar 24 01:05:34 PM PDT 24
Finished Mar 24 01:05:36 PM PDT 24
Peak memory 216880 kb
Host smart-87107ba9-e408-4383-adf1-52e5a5a88cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69555074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.69555074
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3870977789
Short name T670
Test name
Test status
Simulation time 21658268 ps
CPU time 0.99 seconds
Started Mar 24 01:05:35 PM PDT 24
Finished Mar 24 01:05:36 PM PDT 24
Peak memory 215520 kb
Host smart-b8ac0865-5a32-466c-b05d-9368c222da1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870977789 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3870977789
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.4072138909
Short name T410
Test name
Test status
Simulation time 16845946 ps
CPU time 0.99 seconds
Started Mar 24 01:05:35 PM PDT 24
Finished Mar 24 01:05:36 PM PDT 24
Peak memory 215292 kb
Host smart-137cb9b3-e25c-41e2-a92b-730ccb39621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072138909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4072138909
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.444422502
Short name T213
Test name
Test status
Simulation time 592957634 ps
CPU time 3.25 seconds
Started Mar 24 01:05:33 PM PDT 24
Finished Mar 24 01:05:37 PM PDT 24
Peak memory 216552 kb
Host smart-15683f3d-4290-4006-a044-3364efb19461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444422502 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.444422502
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1783059070
Short name T706
Test name
Test status
Simulation time 37238759995 ps
CPU time 969.86 seconds
Started Mar 24 01:05:35 PM PDT 24
Finished Mar 24 01:21:45 PM PDT 24
Peak memory 218612 kb
Host smart-f78944b7-0556-4ae8-9204-86d25aa15f2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783059070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1783059070
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3228447034
Short name T260
Test name
Test status
Simulation time 30630430 ps
CPU time 1.02 seconds
Started Mar 24 01:07:03 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 218260 kb
Host smart-6bfa4d44-d8ce-4a79-8a8a-7d574ee4980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228447034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3228447034
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.683469287
Short name T321
Test name
Test status
Simulation time 43606620 ps
CPU time 1.64 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 216764 kb
Host smart-1b2d819e-d55f-41d7-bbd0-8d76e25466c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683469287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.683469287
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3300199292
Short name T614
Test name
Test status
Simulation time 41788550 ps
CPU time 1.25 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 224332 kb
Host smart-d5581990-68a0-4584-a930-813423623780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300199292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3300199292
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3831207228
Short name T402
Test name
Test status
Simulation time 243147568 ps
CPU time 3.23 seconds
Started Mar 24 01:07:05 PM PDT 24
Finished Mar 24 01:07:08 PM PDT 24
Peak memory 218808 kb
Host smart-dfe0baf7-989b-4f93-9db8-0bf793f66e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831207228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3831207228
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2348526837
Short name T588
Test name
Test status
Simulation time 19043936 ps
CPU time 1.16 seconds
Started Mar 24 01:07:04 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 223176 kb
Host smart-3565b522-0bef-49a9-90b3-2ea606d365c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348526837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2348526837
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3408947101
Short name T396
Test name
Test status
Simulation time 27912646 ps
CPU time 1.32 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 218036 kb
Host smart-1685b130-732a-47f1-a434-30a6f063cc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408947101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3408947101
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.428725316
Short name T79
Test name
Test status
Simulation time 20357080 ps
CPU time 1.21 seconds
Started Mar 24 01:07:06 PM PDT 24
Finished Mar 24 01:07:08 PM PDT 24
Peak memory 229564 kb
Host smart-830df120-9c8e-4f01-9c5b-b693d150c1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428725316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.428725316
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3601603171
Short name T813
Test name
Test status
Simulation time 52792657 ps
CPU time 1.21 seconds
Started Mar 24 01:07:07 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 218180 kb
Host smart-0e4951d7-550e-413d-8dce-2ffbec77f7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601603171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3601603171
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1543458759
Short name T116
Test name
Test status
Simulation time 70051460 ps
CPU time 0.95 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 231308 kb
Host smart-491ce3fa-4459-4b9d-baf2-96d2b3cc530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543458759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1543458759
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3921546673
Short name T327
Test name
Test status
Simulation time 370057278 ps
CPU time 2.26 seconds
Started Mar 24 01:07:07 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 218100 kb
Host smart-72f59895-d4c9-4dc8-9850-bf8c2ccc7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921546673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3921546673
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3392173536
Short name T97
Test name
Test status
Simulation time 33424522 ps
CPU time 1.01 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 232420 kb
Host smart-d24754d9-9c17-4cd0-9314-e3ba7a7e75da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392173536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3392173536
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.478110642
Short name T836
Test name
Test status
Simulation time 53096930 ps
CPU time 1.18 seconds
Started Mar 24 01:07:05 PM PDT 24
Finished Mar 24 01:07:06 PM PDT 24
Peak memory 216612 kb
Host smart-1cb531c9-da2c-4a8d-b38c-df46e248eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478110642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.478110642
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.975322315
Short name T47
Test name
Test status
Simulation time 24090625 ps
CPU time 1.04 seconds
Started Mar 24 01:07:03 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 232548 kb
Host smart-ab1e5dab-99c0-40f6-b3a4-a76f99dedc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975322315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.975322315
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.316007464
Short name T36
Test name
Test status
Simulation time 73775311 ps
CPU time 1.35 seconds
Started Mar 24 01:07:04 PM PDT 24
Finished Mar 24 01:07:06 PM PDT 24
Peak memory 217884 kb
Host smart-380bac62-3169-4be4-9e8a-d5c55363934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316007464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.316007464
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1908206252
Short name T311
Test name
Test status
Simulation time 22547471 ps
CPU time 0.93 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 218188 kb
Host smart-edb89369-df74-48da-9d21-d93bb1a91e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908206252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1908206252
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3425072965
Short name T565
Test name
Test status
Simulation time 42671771 ps
CPU time 1.05 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 216528 kb
Host smart-306d05fe-cbc5-401f-b8ee-ea3828cfb4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425072965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3425072965
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.961494244
Short name T72
Test name
Test status
Simulation time 37805126 ps
CPU time 1.08 seconds
Started Mar 24 01:07:04 PM PDT 24
Finished Mar 24 01:07:06 PM PDT 24
Peak memory 220040 kb
Host smart-8bded5a4-5a5b-4f15-b196-2ba94f882907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961494244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.961494244
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2194324778
Short name T639
Test name
Test status
Simulation time 120754394 ps
CPU time 1.14 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 216980 kb
Host smart-c39d506a-94df-4261-902f-9b7bfe8ced60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194324778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2194324778
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.158672546
Short name T157
Test name
Test status
Simulation time 22471452 ps
CPU time 1.12 seconds
Started Mar 24 01:07:03 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 218180 kb
Host smart-367760a7-dc1c-4b0e-96b8-07f0dc19fa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158672546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.158672546
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.461878048
Short name T635
Test name
Test status
Simulation time 63077141 ps
CPU time 1.46 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 218036 kb
Host smart-365413d8-5a19-4f63-9375-1cd28ffe81e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461878048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.461878048
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1256466437
Short name T743
Test name
Test status
Simulation time 26731320 ps
CPU time 1.25 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 215752 kb
Host smart-f5f5f5d5-e5ec-4f59-b6e7-fd32bf38a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256466437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1256466437
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3652551130
Short name T155
Test name
Test status
Simulation time 33131636 ps
CPU time 1.11 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 206228 kb
Host smart-7c11cb80-e897-4bc2-b5d0-f511e2ff38fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652551130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3652551130
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.134959589
Short name T600
Test name
Test status
Simulation time 237104786 ps
CPU time 0.91 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 216456 kb
Host smart-7047417d-e5ca-4769-84a5-d183ac2d43f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134959589 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.134959589
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2800200691
Short name T649
Test name
Test status
Simulation time 21885829 ps
CPU time 1.13 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 219520 kb
Host smart-9cb68842-d42b-47ba-8700-fd49f5ae1ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800200691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2800200691
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3224784595
Short name T384
Test name
Test status
Simulation time 45398645 ps
CPU time 1.62 seconds
Started Mar 24 01:05:39 PM PDT 24
Finished Mar 24 01:05:40 PM PDT 24
Peak memory 219628 kb
Host smart-d7710435-d1cd-4ce3-b307-1ea707e531b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224784595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3224784595
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1049164675
Short name T469
Test name
Test status
Simulation time 25770768 ps
CPU time 1 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 215708 kb
Host smart-0642245f-aea8-4684-9451-1b053481d7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049164675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1049164675
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.450933172
Short name T265
Test name
Test status
Simulation time 15276890 ps
CPU time 0.96 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 207220 kb
Host smart-5ef98bdf-32f3-4b88-9beb-84ef56d433b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450933172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.450933172
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3787631403
Short name T499
Test name
Test status
Simulation time 16090427 ps
CPU time 0.98 seconds
Started Mar 24 01:05:39 PM PDT 24
Finished Mar 24 01:05:40 PM PDT 24
Peak memory 215456 kb
Host smart-e3a9dbe5-dba9-4158-b2da-50c4edb5487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787631403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3787631403
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.607998298
Short name T653
Test name
Test status
Simulation time 495209070 ps
CPU time 3.35 seconds
Started Mar 24 01:05:39 PM PDT 24
Finished Mar 24 01:05:42 PM PDT 24
Peak memory 215400 kb
Host smart-7eaae691-19ad-4083-8b0a-a72edea0b66a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607998298 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.607998298
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3387410576
Short name T427
Test name
Test status
Simulation time 45635638224 ps
CPU time 1021.91 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:22:42 PM PDT 24
Peak memory 219524 kb
Host smart-ceb79a8b-a3ef-4923-8378-e932c97ec2d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387410576 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3387410576
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.526991659
Short name T525
Test name
Test status
Simulation time 33465155 ps
CPU time 0.91 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 217788 kb
Host smart-47ad4b96-f9e5-4b70-9514-ea44df084b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526991659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.526991659
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2932310685
Short name T475
Test name
Test status
Simulation time 80681220 ps
CPU time 1.2 seconds
Started Mar 24 01:07:03 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 219068 kb
Host smart-12a52f87-04ee-4555-bfef-5b25dd95b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932310685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2932310685
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.698074010
Short name T643
Test name
Test status
Simulation time 18726944 ps
CPU time 1.16 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 231244 kb
Host smart-3e4ebe91-0e95-40a8-9677-41863358ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698074010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.698074010
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3504661664
Short name T535
Test name
Test status
Simulation time 26722925 ps
CPU time 1.14 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 216612 kb
Host smart-04424e4b-72a7-41b2-bbba-b3f6d84707b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504661664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3504661664
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2716653653
Short name T514
Test name
Test status
Simulation time 29640758 ps
CPU time 0.89 seconds
Started Mar 24 01:07:06 PM PDT 24
Finished Mar 24 01:07:07 PM PDT 24
Peak memory 218044 kb
Host smart-cdf24ff0-8299-4ef3-980e-f3ef8b7e01c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716653653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2716653653
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1097733034
Short name T533
Test name
Test status
Simulation time 33531034 ps
CPU time 1.26 seconds
Started Mar 24 01:07:04 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 219376 kb
Host smart-c5cacfba-c55e-4f4b-90c5-125d0d5d42d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097733034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1097733034
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2820517773
Short name T261
Test name
Test status
Simulation time 28616900 ps
CPU time 1.26 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 215656 kb
Host smart-53471737-254a-4002-b613-1929d1cb5a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820517773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2820517773
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2918986411
Short name T465
Test name
Test status
Simulation time 86397995 ps
CPU time 1.24 seconds
Started Mar 24 01:07:03 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 218116 kb
Host smart-337e813c-5a40-4900-8ad7-3d9eb539ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918986411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2918986411
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2515192384
Short name T750
Test name
Test status
Simulation time 30063236 ps
CPU time 0.96 seconds
Started Mar 24 01:07:05 PM PDT 24
Finished Mar 24 01:07:06 PM PDT 24
Peak memory 231048 kb
Host smart-2d7bee5d-9083-4943-875b-2f1788fddc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515192384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2515192384
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2333061042
Short name T818
Test name
Test status
Simulation time 37214943 ps
CPU time 1.34 seconds
Started Mar 24 01:07:04 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 217996 kb
Host smart-6418c27c-fabf-4e9a-9a94-a5038649b783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333061042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2333061042
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2429312896
Short name T420
Test name
Test status
Simulation time 23584276 ps
CPU time 1.18 seconds
Started Mar 24 01:07:06 PM PDT 24
Finished Mar 24 01:07:08 PM PDT 24
Peak memory 217984 kb
Host smart-23ea074d-e9d6-4ab9-bd94-2bc7e8f86082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429312896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2429312896
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1207994004
Short name T272
Test name
Test status
Simulation time 68975009 ps
CPU time 1.41 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 217700 kb
Host smart-685939dc-6a7b-4256-8f15-91903113acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207994004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1207994004
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3351241854
Short name T7
Test name
Test status
Simulation time 26001114 ps
CPU time 1.3 seconds
Started Mar 24 01:07:02 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 217032 kb
Host smart-07229fe6-dbb3-462a-8fc8-4afcd2795299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351241854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3351241854
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2417919533
Short name T373
Test name
Test status
Simulation time 65127130 ps
CPU time 1.05 seconds
Started Mar 24 01:07:03 PM PDT 24
Finished Mar 24 01:07:05 PM PDT 24
Peak memory 216568 kb
Host smart-5c39e231-ae8b-407f-a651-b1d617d8a71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417919533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2417919533
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1587613719
Short name T672
Test name
Test status
Simulation time 63145530 ps
CPU time 0.85 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 217832 kb
Host smart-af74505b-c37e-4c10-93de-21a51237e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587613719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1587613719
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.658523678
Short name T24
Test name
Test status
Simulation time 171640066 ps
CPU time 1.23 seconds
Started Mar 24 01:07:05 PM PDT 24
Finished Mar 24 01:07:06 PM PDT 24
Peak memory 216616 kb
Host smart-d5db9b9c-2a95-4eb0-824a-0ac70225eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658523678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.658523678
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3296665445
Short name T167
Test name
Test status
Simulation time 25161880 ps
CPU time 0.88 seconds
Started Mar 24 01:07:12 PM PDT 24
Finished Mar 24 01:07:13 PM PDT 24
Peak memory 218216 kb
Host smart-c2308416-f6c0-4bbc-a7c7-16b2446c1e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296665445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3296665445
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3852491680
Short name T828
Test name
Test status
Simulation time 63952526 ps
CPU time 1.32 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 217852 kb
Host smart-487c3d62-bc72-4648-a43b-5eb3c2aff2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852491680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3852491680
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3311972904
Short name T526
Test name
Test status
Simulation time 26307230 ps
CPU time 0.8 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 217892 kb
Host smart-6ae34389-4f43-4091-ac15-bf78e256a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311972904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3311972904
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3903694522
Short name T371
Test name
Test status
Simulation time 42163994 ps
CPU time 1.52 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 217944 kb
Host smart-02987da1-a501-476e-b105-7977f38d1a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903694522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3903694522
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3849744386
Short name T153
Test name
Test status
Simulation time 49052710 ps
CPU time 1.24 seconds
Started Mar 24 01:05:44 PM PDT 24
Finished Mar 24 01:05:45 PM PDT 24
Peak memory 215784 kb
Host smart-f56a839b-1763-40fa-b173-a417901d40c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849744386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3849744386
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3153420733
Short name T346
Test name
Test status
Simulation time 64331860 ps
CPU time 0.88 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 206544 kb
Host smart-67b9ea97-ee94-458e-b335-8d05b420673c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153420733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3153420733
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2709572690
Short name T547
Test name
Test status
Simulation time 33816196 ps
CPU time 0.85 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 215592 kb
Host smart-c5286551-468b-437b-9615-b2b00c6c2eac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709572690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2709572690
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.2183694593
Short name T550
Test name
Test status
Simulation time 58825712 ps
CPU time 0.97 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 231372 kb
Host smart-05e7ec9f-bdba-4d21-84ec-bf9170deb339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183694593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2183694593
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1498787772
Short name T786
Test name
Test status
Simulation time 26749383 ps
CPU time 1.22 seconds
Started Mar 24 01:05:39 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 218060 kb
Host smart-32b442b0-47bc-4ade-bed5-ef7b69aea489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498787772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1498787772
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3982313418
Short name T46
Test name
Test status
Simulation time 37782597 ps
CPU time 0.99 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 224072 kb
Host smart-c690f9e0-1f01-431c-9809-ce85208154a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982313418 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3982313418
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3326905995
Short name T135
Test name
Test status
Simulation time 16476221 ps
CPU time 1.01 seconds
Started Mar 24 01:05:49 PM PDT 24
Finished Mar 24 01:05:50 PM PDT 24
Peak memory 207200 kb
Host smart-778b2afe-5b9d-464c-924d-8fb4961e747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326905995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3326905995
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.831948728
Short name T304
Test name
Test status
Simulation time 48747464 ps
CPU time 0.92 seconds
Started Mar 24 01:05:40 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 215404 kb
Host smart-21c37fbd-2add-4b25-a482-10c1957c8978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831948728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.831948728
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1630850383
Short name T480
Test name
Test status
Simulation time 1697219525 ps
CPU time 5.81 seconds
Started Mar 24 01:05:48 PM PDT 24
Finished Mar 24 01:05:54 PM PDT 24
Peak memory 219984 kb
Host smart-149c3088-b5c2-49bb-bc27-586c0b33a35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630850383 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1630850383
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2632283169
Short name T206
Test name
Test status
Simulation time 120309319215 ps
CPU time 1022.67 seconds
Started Mar 24 01:05:54 PM PDT 24
Finished Mar 24 01:22:59 PM PDT 24
Peak memory 223948 kb
Host smart-b28253ba-4cbd-41bf-a550-3898c8afa730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632283169 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2632283169
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2392261317
Short name T104
Test name
Test status
Simulation time 20584067 ps
CPU time 1.01 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 218008 kb
Host smart-424ec261-8f17-4339-9c33-8dbe606c9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392261317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2392261317
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2043239742
Short name T460
Test name
Test status
Simulation time 35905215 ps
CPU time 1.45 seconds
Started Mar 24 01:07:11 PM PDT 24
Finished Mar 24 01:07:12 PM PDT 24
Peak memory 218140 kb
Host smart-97af3d72-3837-41f1-80bf-d53c74574da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043239742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2043239742
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3297785890
Short name T80
Test name
Test status
Simulation time 56716292 ps
CPU time 0.96 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 219376 kb
Host smart-de558579-9298-4fcd-b8a0-647cb4e96734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297785890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3297785890
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3791962400
Short name T690
Test name
Test status
Simulation time 60547168 ps
CPU time 2.21 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:13 PM PDT 24
Peak memory 216996 kb
Host smart-b815ca73-25dd-435f-ab4e-1ee206b56458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791962400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3791962400
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2080813301
Short name T99
Test name
Test status
Simulation time 83377478 ps
CPU time 0.87 seconds
Started Mar 24 01:07:12 PM PDT 24
Finished Mar 24 01:07:13 PM PDT 24
Peak memory 217944 kb
Host smart-4773bab3-617c-4dfc-9290-61db0a0703cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080813301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2080813301
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1718927434
Short name T523
Test name
Test status
Simulation time 83624101 ps
CPU time 1.14 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 216776 kb
Host smart-fdea39d3-ed98-4a83-a3d4-c429382a2999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718927434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1718927434
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3585981973
Short name T446
Test name
Test status
Simulation time 33791192 ps
CPU time 0.87 seconds
Started Mar 24 01:07:08 PM PDT 24
Finished Mar 24 01:07:09 PM PDT 24
Peak memory 217636 kb
Host smart-62c03bfb-3099-49dc-a959-5d6376661696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585981973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3585981973
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3545878428
Short name T28
Test name
Test status
Simulation time 150160246 ps
CPU time 1.32 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:12 PM PDT 24
Peak memory 218828 kb
Host smart-4725f04e-e159-4766-8d1c-2e2b78993b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545878428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3545878428
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1618976261
Short name T816
Test name
Test status
Simulation time 82491317 ps
CPU time 1.1 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 231268 kb
Host smart-5f93de16-98b9-4ed3-9cbb-bceca3a76dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618976261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1618976261
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1251572655
Short name T356
Test name
Test status
Simulation time 67730658 ps
CPU time 1.18 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 218440 kb
Host smart-9828e6c0-c618-46b6-87da-92c2302f000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251572655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1251572655
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.462024435
Short name T562
Test name
Test status
Simulation time 23323108 ps
CPU time 1.04 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 232648 kb
Host smart-28596d31-e4c7-410e-afc1-eb5c937cd203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462024435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.462024435
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2359493193
Short name T426
Test name
Test status
Simulation time 37329981 ps
CPU time 1.4 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 219340 kb
Host smart-070e50ad-a203-426c-aff6-343a26e44883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359493193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2359493193
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3023196632
Short name T699
Test name
Test status
Simulation time 58935074 ps
CPU time 0.99 seconds
Started Mar 24 01:07:10 PM PDT 24
Finished Mar 24 01:07:11 PM PDT 24
Peak memory 218280 kb
Host smart-98dccf00-9a23-4381-a259-628059abf87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023196632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3023196632
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2693515378
Short name T634
Test name
Test status
Simulation time 109092694 ps
CPU time 1.16 seconds
Started Mar 24 01:07:09 PM PDT 24
Finished Mar 24 01:07:10 PM PDT 24
Peak memory 216564 kb
Host smart-9f717616-4762-4cc0-b90e-e7f01a2e4273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693515378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2693515378
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2303403696
Short name T516
Test name
Test status
Simulation time 43419254 ps
CPU time 1.14 seconds
Started Mar 24 01:07:15 PM PDT 24
Finished Mar 24 01:07:17 PM PDT 24
Peak memory 219404 kb
Host smart-a61ea97b-5e7d-4b77-bdf2-07d7c4ab7c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303403696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2303403696
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1808675244
Short name T252
Test name
Test status
Simulation time 93095125 ps
CPU time 1.44 seconds
Started Mar 24 01:07:12 PM PDT 24
Finished Mar 24 01:07:14 PM PDT 24
Peak memory 218348 kb
Host smart-173326e2-8805-4107-ae7d-f0d004a18465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808675244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1808675244
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3680901372
Short name T326
Test name
Test status
Simulation time 18483327 ps
CPU time 1.05 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:15 PM PDT 24
Peak memory 218368 kb
Host smart-41c2257b-fb45-456a-bf2e-893309734e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680901372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3680901372
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3312849038
Short name T680
Test name
Test status
Simulation time 135767635 ps
CPU time 0.89 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:13 PM PDT 24
Peak memory 216856 kb
Host smart-a9cd2d59-4006-4eac-bce5-0388c14f0f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312849038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3312849038
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.4293849477
Short name T309
Test name
Test status
Simulation time 51618980 ps
CPU time 0.77 seconds
Started Mar 24 01:07:12 PM PDT 24
Finished Mar 24 01:07:13 PM PDT 24
Peak memory 217736 kb
Host smart-482b9c69-e3ba-4c98-b197-63f03f099ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293849477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4293849477
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1266801184
Short name T381
Test name
Test status
Simulation time 33692970 ps
CPU time 1.2 seconds
Started Mar 24 01:07:14 PM PDT 24
Finished Mar 24 01:07:15 PM PDT 24
Peak memory 218016 kb
Host smart-0341ab39-c6d9-42e8-98b0-cfe6bc189e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266801184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1266801184
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.3114784206
Short name T383
Test name
Test status
Simulation time 47227475 ps
CPU time 0.89 seconds
Started Mar 24 01:05:49 PM PDT 24
Finished Mar 24 01:05:50 PM PDT 24
Peak memory 206148 kb
Host smart-89cd4b9d-9e67-4575-9c15-8126427fdf20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114784206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3114784206
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.525718741
Short name T538
Test name
Test status
Simulation time 40359386 ps
CPU time 0.86 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:47 PM PDT 24
Peak memory 216084 kb
Host smart-db83fb36-173e-4a04-906b-60f7e405ebaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525718741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.525718741
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.157067674
Short name T82
Test name
Test status
Simulation time 44095783 ps
CPU time 1.22 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 218056 kb
Host smart-e0496091-c2b8-457c-ad25-d0010e8e9f4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157067674 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.157067674
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3260378902
Short name T65
Test name
Test status
Simulation time 66953193 ps
CPU time 1.06 seconds
Started Mar 24 01:05:46 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 229956 kb
Host smart-060304f3-ebca-46ba-ae62-2907ef2b6880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260378902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3260378902
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.504067609
Short name T186
Test name
Test status
Simulation time 55105315 ps
CPU time 1.64 seconds
Started Mar 24 01:05:44 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 218220 kb
Host smart-3ed39b17-0bbd-4bba-a1e0-e50985467736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504067609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.504067609
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3020574799
Short name T796
Test name
Test status
Simulation time 27997892 ps
CPU time 0.84 seconds
Started Mar 24 01:05:45 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 215664 kb
Host smart-cecda259-0c2e-4c7f-ba4b-5121e1dc2bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020574799 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3020574799
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2720924669
Short name T698
Test name
Test status
Simulation time 17968335 ps
CPU time 1 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 207244 kb
Host smart-3b63fd84-37d5-4460-8390-33dfa65d1431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720924669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2720924669
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.785500340
Short name T736
Test name
Test status
Simulation time 18883802 ps
CPU time 1.05 seconds
Started Mar 24 01:05:44 PM PDT 24
Finished Mar 24 01:05:46 PM PDT 24
Peak memory 215444 kb
Host smart-24918d6e-a02b-47c1-8007-7b05b9c0190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785500340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.785500340
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.915961921
Short name T753
Test name
Test status
Simulation time 679038944 ps
CPU time 5.91 seconds
Started Mar 24 01:05:47 PM PDT 24
Finished Mar 24 01:05:53 PM PDT 24
Peak memory 216856 kb
Host smart-2f621fb9-c497-46df-ba1f-0a73cf269031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915961921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.915961921
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1216709423
Short name T194
Test name
Test status
Simulation time 114209422714 ps
CPU time 692.38 seconds
Started Mar 24 01:05:44 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 220428 kb
Host smart-dba641fd-3350-42fb-a325-47469b94e728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216709423 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1216709423
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.510618814
Short name T554
Test name
Test status
Simulation time 32689208 ps
CPU time 0.88 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:15 PM PDT 24
Peak memory 218140 kb
Host smart-5af5fc6c-b35c-49fa-8197-df939ddb0c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510618814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.510618814
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.254701716
Short name T518
Test name
Test status
Simulation time 40339709 ps
CPU time 1.61 seconds
Started Mar 24 01:07:14 PM PDT 24
Finished Mar 24 01:07:17 PM PDT 24
Peak memory 218212 kb
Host smart-8a59532d-309c-4b1b-b991-f2d39f81bbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254701716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.254701716
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3358900607
Short name T702
Test name
Test status
Simulation time 18385428 ps
CPU time 1.12 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:15 PM PDT 24
Peak memory 223044 kb
Host smart-5217410b-0de3-4cf2-85c1-96ea4708420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358900607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3358900607
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.839158832
Short name T55
Test name
Test status
Simulation time 68030056 ps
CPU time 1.28 seconds
Started Mar 24 01:07:14 PM PDT 24
Finished Mar 24 01:07:17 PM PDT 24
Peak memory 217784 kb
Host smart-ef24bf45-da80-4786-861e-a2b158d3636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839158832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.839158832
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3834589703
Short name T791
Test name
Test status
Simulation time 33300607 ps
CPU time 0.95 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:15 PM PDT 24
Peak memory 222916 kb
Host smart-667d77c2-4742-42c8-bf99-e4cd3fd78c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834589703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3834589703
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2481158553
Short name T57
Test name
Test status
Simulation time 23372031 ps
CPU time 1.02 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:15 PM PDT 24
Peak memory 216672 kb
Host smart-4c66508f-3d8a-4461-8e5a-8d354eadbe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481158553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2481158553
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.917319621
Short name T596
Test name
Test status
Simulation time 30112172 ps
CPU time 1.32 seconds
Started Mar 24 01:07:13 PM PDT 24
Finished Mar 24 01:07:14 PM PDT 24
Peak memory 219512 kb
Host smart-931158f0-351f-40bb-88c4-201e3052c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917319621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.917319621
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2611753055
Short name T779
Test name
Test status
Simulation time 22196995 ps
CPU time 1.09 seconds
Started Mar 24 01:07:14 PM PDT 24
Finished Mar 24 01:07:16 PM PDT 24
Peak memory 217976 kb
Host smart-df2e428c-3533-44d5-889c-27a916f73ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611753055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2611753055
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3339548750
Short name T161
Test name
Test status
Simulation time 27889436 ps
CPU time 0.92 seconds
Started Mar 24 01:07:14 PM PDT 24
Finished Mar 24 01:07:16 PM PDT 24
Peak memory 218368 kb
Host smart-365e5400-1392-403c-a318-e8ceaad5b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339548750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3339548750
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2595739140
Short name T439
Test name
Test status
Simulation time 51521377 ps
CPU time 1.55 seconds
Started Mar 24 01:07:15 PM PDT 24
Finished Mar 24 01:07:17 PM PDT 24
Peak memory 217956 kb
Host smart-ebf6d07c-11bb-4a6f-a016-0360582b75a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595739140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2595739140
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.904521173
Short name T85
Test name
Test status
Simulation time 40279591 ps
CPU time 1.45 seconds
Started Mar 24 01:07:19 PM PDT 24
Finished Mar 24 01:07:21 PM PDT 24
Peak memory 224504 kb
Host smart-0cd4c34a-40b2-48da-98b2-c91f061cfe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904521173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.904521173
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2987488181
Short name T546
Test name
Test status
Simulation time 44838698 ps
CPU time 1.13 seconds
Started Mar 24 01:07:20 PM PDT 24
Finished Mar 24 01:07:23 PM PDT 24
Peak memory 219344 kb
Host smart-c2ae3de9-c09e-49a7-a13e-29e31c24fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987488181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2987488181
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3273840187
Short name T726
Test name
Test status
Simulation time 18442063 ps
CPU time 1.08 seconds
Started Mar 24 01:07:19 PM PDT 24
Finished Mar 24 01:07:20 PM PDT 24
Peak memory 218072 kb
Host smart-57988dbf-98c6-4054-b463-da1a556746f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273840187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3273840187
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2590746712
Short name T598
Test name
Test status
Simulation time 73961827 ps
CPU time 1.45 seconds
Started Mar 24 01:07:20 PM PDT 24
Finished Mar 24 01:07:23 PM PDT 24
Peak memory 217836 kb
Host smart-23602e6c-21e0-4071-8ace-0f6dcedb7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590746712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2590746712
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1067523847
Short name T61
Test name
Test status
Simulation time 31540598 ps
CPU time 1.16 seconds
Started Mar 24 01:07:18 PM PDT 24
Finished Mar 24 01:07:19 PM PDT 24
Peak memory 219316 kb
Host smart-6eeb09fb-8c64-457e-b6f7-24afbe93bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067523847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1067523847
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1452282596
Short name T767
Test name
Test status
Simulation time 39437320 ps
CPU time 1.52 seconds
Started Mar 24 01:07:21 PM PDT 24
Finished Mar 24 01:07:23 PM PDT 24
Peak memory 217832 kb
Host smart-75def668-8104-4fd8-abf4-95aa9e067d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452282596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1452282596
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.468016084
Short name T447
Test name
Test status
Simulation time 20167377 ps
CPU time 1.19 seconds
Started Mar 24 01:07:19 PM PDT 24
Finished Mar 24 01:07:20 PM PDT 24
Peak memory 223060 kb
Host smart-ef251622-15cc-4fc6-baae-2d01222c9c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468016084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.468016084
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2759155497
Short name T367
Test name
Test status
Simulation time 49469027 ps
CPU time 1.59 seconds
Started Mar 24 01:07:19 PM PDT 24
Finished Mar 24 01:07:21 PM PDT 24
Peak memory 217760 kb
Host smart-58800466-f2f1-4a00-b0d8-799bf7cdd358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759155497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2759155497
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3635818163
Short name T722
Test name
Test status
Simulation time 21801040 ps
CPU time 1.14 seconds
Started Mar 24 01:07:18 PM PDT 24
Finished Mar 24 01:07:19 PM PDT 24
Peak memory 219568 kb
Host smart-f4e46a9b-a1ad-413a-a584-21ef5c43ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635818163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3635818163
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2445432635
Short name T417
Test name
Test status
Simulation time 155280762 ps
CPU time 3.16 seconds
Started Mar 24 01:07:18 PM PDT 24
Finished Mar 24 01:07:21 PM PDT 24
Peak memory 219984 kb
Host smart-99aec899-a1d5-4625-80bd-7819dc3460a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445432635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2445432635
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%