Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 7340 1 T1 22 T3 160 T22 115
all_values[1] 7340 1 T1 22 T3 160 T22 115


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7608 1 T1 32 T3 143 T22 109
auto[1] 7072 1 T1 12 T3 177 T22 121


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5842 1 T1 18 T3 122 T22 80
auto[1] 8838 1 T1 26 T3 198 T22 150


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8736 1 T1 24 T3 187 T22 132
auto[1] 5944 1 T1 20 T3 133 T22 98


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1561 1 T1 7 T3 30 T22 19
all_values[0] auto[0] auto[0] auto[1] 732 1 T1 3 T3 12 T22 14
all_values[0] auto[0] auto[1] auto[0] 1355 1 T3 33 T22 22 T23 37
all_values[0] auto[0] auto[1] auto[1] 699 1 T1 1 T3 16 T22 9
all_values[0] auto[1] auto[0] auto[1] 1578 1 T1 8 T3 30 T22 28
all_values[0] auto[1] auto[1] auto[1] 1415 1 T1 3 T3 39 T22 23
all_values[1] auto[0] auto[0] auto[0] 1491 1 T1 7 T3 16 T22 17
all_values[1] auto[0] auto[0] auto[1] 716 1 T1 1 T3 20 T22 12
all_values[1] auto[0] auto[1] auto[0] 1435 1 T1 4 T3 43 T22 22
all_values[1] auto[0] auto[1] auto[1] 747 1 T1 1 T3 17 T22 17
all_values[1] auto[1] auto[0] auto[1] 1530 1 T1 6 T3 35 T22 19
all_values[1] auto[1] auto[1] auto[1] 1421 1 T1 3 T3 29 T22 28


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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