Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.89 98.27 93.52 96.79 82.08 96.87 96.58 93.15


Total test records in report: 970
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T787 /workspace/coverage/default/88.edn_genbits.977373179 Mar 26 03:27:51 PM PDT 24 Mar 26 03:27:53 PM PDT 24 43631761 ps
T788 /workspace/coverage/default/123.edn_genbits.4022855738 Mar 26 03:27:48 PM PDT 24 Mar 26 03:27:50 PM PDT 24 37029304 ps
T789 /workspace/coverage/default/26.edn_err.2966579257 Mar 26 03:26:57 PM PDT 24 Mar 26 03:26:58 PM PDT 24 43275437 ps
T790 /workspace/coverage/default/102.edn_genbits.3553961537 Mar 26 03:27:45 PM PDT 24 Mar 26 03:27:47 PM PDT 24 76693827 ps
T68 /workspace/coverage/default/3.edn_err.2577250546 Mar 26 03:26:25 PM PDT 24 Mar 26 03:26:26 PM PDT 24 48171897 ps
T791 /workspace/coverage/default/6.edn_intr.1384208133 Mar 26 03:26:26 PM PDT 24 Mar 26 03:26:27 PM PDT 24 33300291 ps
T792 /workspace/coverage/default/55.edn_err.2441768653 Mar 26 03:27:57 PM PDT 24 Mar 26 03:27:58 PM PDT 24 63190452 ps
T793 /workspace/coverage/default/43.edn_disable_auto_req_mode.808048691 Mar 26 03:27:14 PM PDT 24 Mar 26 03:27:16 PM PDT 24 73946905 ps
T794 /workspace/coverage/default/33.edn_alert_test.547144897 Mar 26 03:27:07 PM PDT 24 Mar 26 03:27:08 PM PDT 24 47777856 ps
T795 /workspace/coverage/default/45.edn_alert_test.3300809415 Mar 26 03:27:24 PM PDT 24 Mar 26 03:27:25 PM PDT 24 18552781 ps
T796 /workspace/coverage/default/12.edn_disable.104955374 Mar 26 03:26:30 PM PDT 24 Mar 26 03:26:30 PM PDT 24 16337482 ps
T797 /workspace/coverage/default/196.edn_genbits.3138963674 Mar 26 03:27:59 PM PDT 24 Mar 26 03:28:00 PM PDT 24 78354125 ps
T798 /workspace/coverage/default/3.edn_genbits.2208703396 Mar 26 03:26:23 PM PDT 24 Mar 26 03:26:25 PM PDT 24 266238022 ps
T799 /workspace/coverage/default/34.edn_genbits.241194621 Mar 26 03:27:10 PM PDT 24 Mar 26 03:27:11 PM PDT 24 58213535 ps
T800 /workspace/coverage/default/7.edn_disable.3958904235 Mar 26 03:26:26 PM PDT 24 Mar 26 03:26:27 PM PDT 24 11232082 ps
T801 /workspace/coverage/default/43.edn_alert.4122484025 Mar 26 03:27:29 PM PDT 24 Mar 26 03:27:30 PM PDT 24 26415380 ps
T802 /workspace/coverage/default/47.edn_stress_all.1270958813 Mar 26 03:27:26 PM PDT 24 Mar 26 03:27:30 PM PDT 24 671296412 ps
T803 /workspace/coverage/default/203.edn_genbits.4236448220 Mar 26 03:27:53 PM PDT 24 Mar 26 03:27:54 PM PDT 24 43105191 ps
T65 /workspace/coverage/default/8.edn_disable_auto_req_mode.855713220 Mar 26 03:26:29 PM PDT 24 Mar 26 03:26:30 PM PDT 24 98179930 ps
T126 /workspace/coverage/default/17.edn_intr.3247804097 Mar 26 03:26:42 PM PDT 24 Mar 26 03:26:43 PM PDT 24 27931363 ps
T804 /workspace/coverage/default/47.edn_alert.1035191652 Mar 26 03:27:25 PM PDT 24 Mar 26 03:27:28 PM PDT 24 48175699 ps
T805 /workspace/coverage/default/42.edn_stress_all.622422886 Mar 26 03:27:24 PM PDT 24 Mar 26 03:27:27 PM PDT 24 86434923 ps
T806 /workspace/coverage/default/22.edn_alert.4076231807 Mar 26 03:26:33 PM PDT 24 Mar 26 03:26:35 PM PDT 24 22617951 ps
T807 /workspace/coverage/default/21.edn_intr.888378268 Mar 26 03:26:43 PM PDT 24 Mar 26 03:26:44 PM PDT 24 26101775 ps
T264 /workspace/coverage/default/289.edn_genbits.1779074508 Mar 26 03:28:27 PM PDT 24 Mar 26 03:28:31 PM PDT 24 138227664 ps
T808 /workspace/coverage/default/159.edn_genbits.513767568 Mar 26 03:27:49 PM PDT 24 Mar 26 03:27:50 PM PDT 24 57013830 ps
T809 /workspace/coverage/default/5.edn_genbits.4293783921 Mar 26 03:26:32 PM PDT 24 Mar 26 03:26:33 PM PDT 24 33397986 ps
T810 /workspace/coverage/default/11.edn_stress_all.1844629872 Mar 26 03:26:30 PM PDT 24 Mar 26 03:26:34 PM PDT 24 229306954 ps
T811 /workspace/coverage/default/21.edn_smoke.2707272563 Mar 26 03:26:50 PM PDT 24 Mar 26 03:26:52 PM PDT 24 61372625 ps
T812 /workspace/coverage/default/94.edn_err.2837529940 Mar 26 03:27:54 PM PDT 24 Mar 26 03:27:55 PM PDT 24 24349981 ps
T813 /workspace/coverage/default/27.edn_smoke.2103794464 Mar 26 03:26:50 PM PDT 24 Mar 26 03:26:51 PM PDT 24 106070986 ps
T814 /workspace/coverage/default/31.edn_intr.3423741468 Mar 26 03:27:06 PM PDT 24 Mar 26 03:27:07 PM PDT 24 21062478 ps
T815 /workspace/coverage/default/225.edn_genbits.3095066584 Mar 26 03:28:06 PM PDT 24 Mar 26 03:28:08 PM PDT 24 51365459 ps
T816 /workspace/coverage/default/28.edn_alert_test.3180925586 Mar 26 03:26:58 PM PDT 24 Mar 26 03:26:59 PM PDT 24 46120202 ps
T817 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3347435190 Mar 26 03:26:30 PM PDT 24 Mar 26 03:39:31 PM PDT 24 71548953168 ps
T818 /workspace/coverage/default/180.edn_genbits.758019154 Mar 26 03:27:51 PM PDT 24 Mar 26 03:27:52 PM PDT 24 46548066 ps
T819 /workspace/coverage/default/7.edn_intr.1403636775 Mar 26 03:26:27 PM PDT 24 Mar 26 03:26:28 PM PDT 24 19796887 ps
T820 /workspace/coverage/default/257.edn_genbits.3162595906 Mar 26 03:27:56 PM PDT 24 Mar 26 03:27:57 PM PDT 24 95619312 ps
T821 /workspace/coverage/default/24.edn_genbits.4243203495 Mar 26 03:26:55 PM PDT 24 Mar 26 03:26:57 PM PDT 24 48993867 ps
T78 /workspace/coverage/default/57.edn_err.3739995531 Mar 26 03:27:54 PM PDT 24 Mar 26 03:27:56 PM PDT 24 49192518 ps
T822 /workspace/coverage/default/10.edn_alert.3081189208 Mar 26 03:26:26 PM PDT 24 Mar 26 03:26:28 PM PDT 24 213470800 ps
T823 /workspace/coverage/default/14.edn_smoke.2639696954 Mar 26 03:26:26 PM PDT 24 Mar 26 03:26:27 PM PDT 24 43797121 ps
T824 /workspace/coverage/default/16.edn_intr.1226802202 Mar 26 03:26:34 PM PDT 24 Mar 26 03:26:35 PM PDT 24 45894109 ps
T825 /workspace/coverage/default/35.edn_genbits.3414153274 Mar 26 03:27:25 PM PDT 24 Mar 26 03:27:29 PM PDT 24 282599124 ps
T826 /workspace/coverage/default/118.edn_genbits.3673813101 Mar 26 03:27:55 PM PDT 24 Mar 26 03:27:56 PM PDT 24 90620356 ps
T827 /workspace/coverage/default/278.edn_genbits.2168376016 Mar 26 03:28:05 PM PDT 24 Mar 26 03:28:07 PM PDT 24 38916309 ps
T828 /workspace/coverage/default/5.edn_alert.2264730109 Mar 26 03:26:22 PM PDT 24 Mar 26 03:26:28 PM PDT 24 51565223 ps
T829 /workspace/coverage/default/31.edn_disable.860262234 Mar 26 03:27:02 PM PDT 24 Mar 26 03:27:03 PM PDT 24 21095756 ps
T830 /workspace/coverage/default/10.edn_disable.3123817795 Mar 26 03:26:47 PM PDT 24 Mar 26 03:26:48 PM PDT 24 94364995 ps
T831 /workspace/coverage/default/295.edn_genbits.2091714376 Mar 26 03:28:07 PM PDT 24 Mar 26 03:28:08 PM PDT 24 82605458 ps
T832 /workspace/coverage/default/284.edn_genbits.1188788551 Mar 26 03:28:10 PM PDT 24 Mar 26 03:28:12 PM PDT 24 75836801 ps
T833 /workspace/coverage/default/290.edn_genbits.3157067719 Mar 26 03:28:16 PM PDT 24 Mar 26 03:28:17 PM PDT 24 32877680 ps
T834 /workspace/coverage/default/41.edn_stress_all.336068494 Mar 26 03:27:10 PM PDT 24 Mar 26 03:27:12 PM PDT 24 221933605 ps
T835 /workspace/coverage/default/97.edn_err.603642215 Mar 26 03:27:35 PM PDT 24 Mar 26 03:27:36 PM PDT 24 33355229 ps
T836 /workspace/coverage/default/13.edn_stress_all.60158820 Mar 26 03:26:30 PM PDT 24 Mar 26 03:26:31 PM PDT 24 81475718 ps
T837 /workspace/coverage/cover_reg_top/47.edn_intr_test.1046476062 Mar 26 02:46:16 PM PDT 24 Mar 26 02:46:17 PM PDT 24 47514863 ps
T838 /workspace/coverage/cover_reg_top/33.edn_intr_test.1521421981 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 45489033 ps
T203 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3784978610 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:08 PM PDT 24 37477557 ps
T839 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3421731004 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:08 PM PDT 24 212014040 ps
T840 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.505660020 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 30694835 ps
T841 /workspace/coverage/cover_reg_top/6.edn_intr_test.1457680087 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:57 PM PDT 24 100124681 ps
T842 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1660649911 Mar 26 02:46:03 PM PDT 24 Mar 26 02:46:05 PM PDT 24 37196349 ps
T843 /workspace/coverage/cover_reg_top/48.edn_intr_test.2696351592 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 24223052 ps
T844 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2321770965 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:08 PM PDT 24 58054353 ps
T845 /workspace/coverage/cover_reg_top/17.edn_intr_test.509313961 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:07 PM PDT 24 33209810 ps
T218 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2245192669 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 108477999 ps
T846 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1074492521 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:12 PM PDT 24 473901093 ps
T219 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.844576389 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:08 PM PDT 24 108727017 ps
T204 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.41835899 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 23864615 ps
T205 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1215560363 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:58 PM PDT 24 61143835 ps
T847 /workspace/coverage/cover_reg_top/9.edn_intr_test.1295912659 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 23760067 ps
T848 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1904379185 Mar 26 02:45:43 PM PDT 24 Mar 26 02:45:46 PM PDT 24 69920237 ps
T849 /workspace/coverage/cover_reg_top/27.edn_intr_test.1095629834 Mar 26 02:46:23 PM PDT 24 Mar 26 02:46:24 PM PDT 24 13226596 ps
T850 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3041570879 Mar 26 02:46:13 PM PDT 24 Mar 26 02:46:14 PM PDT 24 74400353 ps
T851 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3604083861 Mar 26 02:45:44 PM PDT 24 Mar 26 02:45:46 PM PDT 24 21091207 ps
T852 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3091865681 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:07 PM PDT 24 65761941 ps
T853 /workspace/coverage/cover_reg_top/38.edn_intr_test.1616105043 Mar 26 02:46:16 PM PDT 24 Mar 26 02:46:17 PM PDT 24 13179671 ps
T220 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3545650435 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:07 PM PDT 24 21839712 ps
T854 /workspace/coverage/cover_reg_top/30.edn_intr_test.3601403147 Mar 26 02:46:23 PM PDT 24 Mar 26 02:46:24 PM PDT 24 28702265 ps
T855 /workspace/coverage/cover_reg_top/11.edn_intr_test.2808718398 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:09 PM PDT 24 42324527 ps
T856 /workspace/coverage/cover_reg_top/44.edn_intr_test.78279896 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 25906500 ps
T857 /workspace/coverage/cover_reg_top/28.edn_intr_test.2257752894 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 19957931 ps
T206 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2488798354 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:57 PM PDT 24 38329426 ps
T858 /workspace/coverage/cover_reg_top/31.edn_intr_test.1247300680 Mar 26 02:46:19 PM PDT 24 Mar 26 02:46:20 PM PDT 24 32769977 ps
T225 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3670255223 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:07 PM PDT 24 43991615 ps
T207 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2386102932 Mar 26 02:46:03 PM PDT 24 Mar 26 02:46:04 PM PDT 24 11016861 ps
T859 /workspace/coverage/cover_reg_top/43.edn_intr_test.3177886737 Mar 26 02:46:15 PM PDT 24 Mar 26 02:46:16 PM PDT 24 31109094 ps
T860 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2391911396 Mar 26 02:45:42 PM PDT 24 Mar 26 02:45:45 PM PDT 24 521175743 ps
T221 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1065318330 Mar 26 02:45:53 PM PDT 24 Mar 26 02:45:55 PM PDT 24 26611055 ps
T224 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3195749530 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 57220379 ps
T208 /workspace/coverage/cover_reg_top/15.edn_csr_rw.204673045 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:07 PM PDT 24 19819125 ps
T861 /workspace/coverage/cover_reg_top/26.edn_intr_test.2217183769 Mar 26 02:46:12 PM PDT 24 Mar 26 02:46:13 PM PDT 24 30063824 ps
T226 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.17611297 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:09 PM PDT 24 234465782 ps
T209 /workspace/coverage/cover_reg_top/6.edn_csr_rw.848608310 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:57 PM PDT 24 116993014 ps
T227 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3503572528 Mar 26 02:45:53 PM PDT 24 Mar 26 02:45:55 PM PDT 24 89809759 ps
T862 /workspace/coverage/cover_reg_top/20.edn_intr_test.4140631697 Mar 26 02:46:13 PM PDT 24 Mar 26 02:46:14 PM PDT 24 45128364 ps
T230 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.366197083 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 368095041 ps
T863 /workspace/coverage/cover_reg_top/19.edn_intr_test.1634858437 Mar 26 02:46:11 PM PDT 24 Mar 26 02:46:12 PM PDT 24 20993862 ps
T222 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2379491058 Mar 26 02:45:58 PM PDT 24 Mar 26 02:45:59 PM PDT 24 101120494 ps
T864 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2220051574 Mar 26 02:46:04 PM PDT 24 Mar 26 02:46:05 PM PDT 24 133126916 ps
T233 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4196621168 Mar 26 02:46:04 PM PDT 24 Mar 26 02:46:06 PM PDT 24 134424941 ps
T865 /workspace/coverage/cover_reg_top/40.edn_intr_test.1383138940 Mar 26 02:46:16 PM PDT 24 Mar 26 02:46:17 PM PDT 24 14548616 ps
T210 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1921694632 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:08 PM PDT 24 82501754 ps
T866 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.623377175 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 26411387 ps
T867 /workspace/coverage/cover_reg_top/2.edn_intr_test.1355012663 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:57 PM PDT 24 39632114 ps
T868 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2358584889 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 39962808 ps
T223 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2659499377 Mar 26 02:45:53 PM PDT 24 Mar 26 02:45:54 PM PDT 24 20588724 ps
T869 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2939719226 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 51088129 ps
T211 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.833907590 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:16 PM PDT 24 138048508 ps
T870 /workspace/coverage/cover_reg_top/14.edn_intr_test.2562299872 Mar 26 02:46:02 PM PDT 24 Mar 26 02:46:03 PM PDT 24 115373340 ps
T871 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.950787475 Mar 26 02:45:41 PM PDT 24 Mar 26 02:45:42 PM PDT 24 24625168 ps
T872 /workspace/coverage/cover_reg_top/41.edn_intr_test.2201694208 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 32662313 ps
T873 /workspace/coverage/cover_reg_top/1.edn_intr_test.2769289133 Mar 26 02:45:42 PM PDT 24 Mar 26 02:45:43 PM PDT 24 43258492 ps
T874 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4095080116 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:58 PM PDT 24 30408022 ps
T875 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2452640068 Mar 26 02:45:44 PM PDT 24 Mar 26 02:45:47 PM PDT 24 94489399 ps
T876 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.365573492 Mar 26 02:45:58 PM PDT 24 Mar 26 02:45:59 PM PDT 24 299770040 ps
T234 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1744412087 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:57 PM PDT 24 204404860 ps
T877 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.787072853 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:10 PM PDT 24 30923481 ps
T878 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1766550503 Mar 26 02:45:56 PM PDT 24 Mar 26 02:46:03 PM PDT 24 1008522160 ps
T879 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2003002934 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 38614252 ps
T880 /workspace/coverage/cover_reg_top/8.edn_intr_test.975293581 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 14653665 ps
T881 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1158687206 Mar 26 02:45:41 PM PDT 24 Mar 26 02:45:42 PM PDT 24 49539803 ps
T882 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1536248925 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:58 PM PDT 24 28298467 ps
T883 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1133674685 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:59 PM PDT 24 32582317 ps
T884 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2111514390 Mar 26 02:45:53 PM PDT 24 Mar 26 02:45:56 PM PDT 24 219788939 ps
T885 /workspace/coverage/cover_reg_top/21.edn_intr_test.169847803 Mar 26 02:46:13 PM PDT 24 Mar 26 02:46:14 PM PDT 24 28287773 ps
T886 /workspace/coverage/cover_reg_top/18.edn_intr_test.2540444872 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:06 PM PDT 24 61059954 ps
T887 /workspace/coverage/cover_reg_top/7.edn_intr_test.2304439444 Mar 26 02:45:58 PM PDT 24 Mar 26 02:45:59 PM PDT 24 12898187 ps
T888 /workspace/coverage/cover_reg_top/24.edn_intr_test.991569249 Mar 26 02:46:13 PM PDT 24 Mar 26 02:46:14 PM PDT 24 14935361 ps
T889 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3471390100 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 193223508 ps
T890 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2222271465 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 23381390 ps
T891 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3576361413 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 40661033 ps
T892 /workspace/coverage/cover_reg_top/5.edn_csr_rw.465458345 Mar 26 02:45:53 PM PDT 24 Mar 26 02:45:55 PM PDT 24 17034802 ps
T893 /workspace/coverage/cover_reg_top/10.edn_intr_test.998236567 Mar 26 02:46:09 PM PDT 24 Mar 26 02:46:10 PM PDT 24 38916176 ps
T894 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1641258962 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 41414228 ps
T895 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3339752697 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 23121308 ps
T896 /workspace/coverage/cover_reg_top/22.edn_intr_test.2433847561 Mar 26 02:46:15 PM PDT 24 Mar 26 02:46:16 PM PDT 24 21179702 ps
T897 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.437191855 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 42141679 ps
T898 /workspace/coverage/cover_reg_top/39.edn_intr_test.1286641027 Mar 26 02:46:15 PM PDT 24 Mar 26 02:46:16 PM PDT 24 27057777 ps
T899 /workspace/coverage/cover_reg_top/5.edn_intr_test.2931205949 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:57 PM PDT 24 67066625 ps
T235 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.540091090 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:09 PM PDT 24 82781427 ps
T212 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4260908373 Mar 26 02:45:43 PM PDT 24 Mar 26 02:45:44 PM PDT 24 25708029 ps
T900 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1277572800 Mar 26 02:46:09 PM PDT 24 Mar 26 02:46:11 PM PDT 24 36352043 ps
T901 /workspace/coverage/cover_reg_top/0.edn_intr_test.795238512 Mar 26 02:45:44 PM PDT 24 Mar 26 02:45:45 PM PDT 24 63537793 ps
T902 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.970891934 Mar 26 02:45:47 PM PDT 24 Mar 26 02:45:50 PM PDT 24 1245805546 ps
T903 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2325568699 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 64790827 ps
T213 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2374068478 Mar 26 02:46:04 PM PDT 24 Mar 26 02:46:06 PM PDT 24 32002601 ps
T904 /workspace/coverage/cover_reg_top/18.edn_csr_rw.467943372 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:09 PM PDT 24 27322751 ps
T905 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.126809800 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 90543046 ps
T906 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2635937989 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:58 PM PDT 24 18444007 ps
T907 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2973771442 Mar 26 02:46:13 PM PDT 24 Mar 26 02:46:15 PM PDT 24 126735671 ps
T908 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.965176565 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:07 PM PDT 24 1076979994 ps
T909 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4100284067 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:57 PM PDT 24 97286624 ps
T910 /workspace/coverage/cover_reg_top/45.edn_intr_test.3386003947 Mar 26 02:46:18 PM PDT 24 Mar 26 02:46:19 PM PDT 24 55960895 ps
T911 /workspace/coverage/cover_reg_top/3.edn_intr_test.869795181 Mar 26 02:45:57 PM PDT 24 Mar 26 02:45:58 PM PDT 24 22634105 ps
T912 /workspace/coverage/cover_reg_top/15.edn_intr_test.454153987 Mar 26 02:46:11 PM PDT 24 Mar 26 02:46:12 PM PDT 24 40359018 ps
T214 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3307875518 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 17875199 ps
T913 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1786619372 Mar 26 02:45:47 PM PDT 24 Mar 26 02:45:48 PM PDT 24 15268616 ps
T914 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1732425992 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:07 PM PDT 24 45338570 ps
T915 /workspace/coverage/cover_reg_top/12.edn_intr_test.731257038 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:07 PM PDT 24 43707819 ps
T916 /workspace/coverage/cover_reg_top/16.edn_intr_test.3950391348 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:07 PM PDT 24 13483497 ps
T917 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1937940970 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:58 PM PDT 24 154573515 ps
T918 /workspace/coverage/cover_reg_top/23.edn_intr_test.1935993586 Mar 26 02:46:17 PM PDT 24 Mar 26 02:46:18 PM PDT 24 41897316 ps
T919 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1895611786 Mar 26 02:45:43 PM PDT 24 Mar 26 02:45:44 PM PDT 24 14197467 ps
T920 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3341847771 Mar 26 02:45:44 PM PDT 24 Mar 26 02:45:45 PM PDT 24 27484682 ps
T921 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3074881500 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 75201559 ps
T922 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1309108027 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 45206742 ps
T923 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4276136553 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:09 PM PDT 24 68993801 ps
T924 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4277073749 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:07 PM PDT 24 31813262 ps
T925 /workspace/coverage/cover_reg_top/49.edn_intr_test.945698520 Mar 26 02:46:30 PM PDT 24 Mar 26 02:46:31 PM PDT 24 15494019 ps
T231 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3246406293 Mar 26 02:46:06 PM PDT 24 Mar 26 02:46:08 PM PDT 24 70925361 ps
T926 /workspace/coverage/cover_reg_top/25.edn_intr_test.52190265 Mar 26 02:46:17 PM PDT 24 Mar 26 02:46:18 PM PDT 24 15253095 ps
T927 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2972260974 Mar 26 02:46:42 PM PDT 24 Mar 26 02:46:45 PM PDT 24 357800855 ps
T928 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2095798311 Mar 26 02:46:03 PM PDT 24 Mar 26 02:46:05 PM PDT 24 95153188 ps
T929 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3282966812 Mar 26 02:46:04 PM PDT 24 Mar 26 02:46:08 PM PDT 24 101323363 ps
T930 /workspace/coverage/cover_reg_top/36.edn_intr_test.4138134324 Mar 26 02:46:15 PM PDT 24 Mar 26 02:46:16 PM PDT 24 21544779 ps
T931 /workspace/coverage/cover_reg_top/29.edn_intr_test.3935501062 Mar 26 02:46:16 PM PDT 24 Mar 26 02:46:17 PM PDT 24 19141571 ps
T215 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3406461087 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 125369981 ps
T932 /workspace/coverage/cover_reg_top/32.edn_intr_test.3633849154 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 17765044 ps
T933 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.662225983 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:09 PM PDT 24 157331654 ps
T934 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1385887987 Mar 26 02:46:03 PM PDT 24 Mar 26 02:46:05 PM PDT 24 118283849 ps
T935 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3006270980 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:09 PM PDT 24 44545439 ps
T936 /workspace/coverage/cover_reg_top/34.edn_intr_test.781763774 Mar 26 02:46:13 PM PDT 24 Mar 26 02:46:14 PM PDT 24 14279428 ps
T937 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2955425742 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:06 PM PDT 24 83187091 ps
T938 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2027730059 Mar 26 02:46:04 PM PDT 24 Mar 26 02:46:06 PM PDT 24 244795681 ps
T939 /workspace/coverage/cover_reg_top/4.edn_intr_test.1756146503 Mar 26 02:45:53 PM PDT 24 Mar 26 02:45:54 PM PDT 24 56052437 ps
T940 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2567297180 Mar 26 02:46:09 PM PDT 24 Mar 26 02:46:11 PM PDT 24 60420212 ps
T941 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3002028627 Mar 26 02:45:59 PM PDT 24 Mar 26 02:46:02 PM PDT 24 341407078 ps
T232 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1431769053 Mar 26 02:46:02 PM PDT 24 Mar 26 02:46:04 PM PDT 24 257316043 ps
T942 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3921872649 Mar 26 02:46:03 PM PDT 24 Mar 26 02:46:05 PM PDT 24 75464635 ps
T943 /workspace/coverage/cover_reg_top/10.edn_csr_rw.935780460 Mar 26 02:46:08 PM PDT 24 Mar 26 02:46:09 PM PDT 24 16876141 ps
T944 /workspace/coverage/cover_reg_top/1.edn_csr_rw.655170045 Mar 26 02:45:43 PM PDT 24 Mar 26 02:45:44 PM PDT 24 21193082 ps
T945 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.350967717 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:08 PM PDT 24 22587309 ps
T216 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3314758246 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:56 PM PDT 24 53698129 ps
T946 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1923986731 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:56 PM PDT 24 488798321 ps
T947 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2968371320 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:07 PM PDT 24 90214171 ps
T948 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3615803872 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:59 PM PDT 24 458472669 ps
T217 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3317907415 Mar 26 02:45:45 PM PDT 24 Mar 26 02:45:46 PM PDT 24 15808248 ps
T949 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3452878238 Mar 26 02:45:55 PM PDT 24 Mar 26 02:45:58 PM PDT 24 163218207 ps
T950 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3052532901 Mar 26 02:46:03 PM PDT 24 Mar 26 02:46:05 PM PDT 24 26053728 ps
T951 /workspace/coverage/cover_reg_top/35.edn_intr_test.3773449639 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 54154594 ps
T952 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2895335185 Mar 26 02:46:09 PM PDT 24 Mar 26 02:46:13 PM PDT 24 91837160 ps
T953 /workspace/coverage/cover_reg_top/13.edn_intr_test.4182063415 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:08 PM PDT 24 51229812 ps
T954 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.94439995 Mar 26 02:45:42 PM PDT 24 Mar 26 02:45:46 PM PDT 24 143550848 ps
T955 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.857196038 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:57 PM PDT 24 38357212 ps
T956 /workspace/coverage/cover_reg_top/42.edn_intr_test.2491468769 Mar 26 02:46:15 PM PDT 24 Mar 26 02:46:16 PM PDT 24 23746001 ps
T957 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1107590641 Mar 26 02:45:56 PM PDT 24 Mar 26 02:45:59 PM PDT 24 207201085 ps
T958 /workspace/coverage/cover_reg_top/46.edn_intr_test.4003927151 Mar 26 02:46:15 PM PDT 24 Mar 26 02:46:16 PM PDT 24 23121724 ps
T959 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1295058966 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 105569881 ps
T960 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3176371367 Mar 26 02:46:14 PM PDT 24 Mar 26 02:46:15 PM PDT 24 26456755 ps
T961 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2020692647 Mar 26 02:46:05 PM PDT 24 Mar 26 02:46:07 PM PDT 24 91050372 ps
T962 /workspace/coverage/cover_reg_top/37.edn_intr_test.1123379144 Mar 26 02:46:23 PM PDT 24 Mar 26 02:46:24 PM PDT 24 28437788 ps
T963 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1366792698 Mar 26 02:45:43 PM PDT 24 Mar 26 02:45:46 PM PDT 24 115817564 ps
T964 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1111963804 Mar 26 02:45:58 PM PDT 24 Mar 26 02:46:04 PM PDT 24 253041257 ps
T965 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1975828442 Mar 26 02:45:52 PM PDT 24 Mar 26 02:45:54 PM PDT 24 35341055 ps
T966 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2850299486 Mar 26 02:46:09 PM PDT 24 Mar 26 02:46:11 PM PDT 24 49431704 ps
T967 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3634474332 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:56 PM PDT 24 119636857 ps
T968 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3434045032 Mar 26 02:45:54 PM PDT 24 Mar 26 02:45:55 PM PDT 24 39943133 ps
T969 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.423988806 Mar 26 02:46:07 PM PDT 24 Mar 26 02:46:09 PM PDT 24 105265529 ps
T970 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1029811325 Mar 26 02:45:43 PM PDT 24 Mar 26 02:45:45 PM PDT 24 39902620 ps

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3990229630
Short name T3
Test name
Test status
Simulation time 204463819060 ps
CPU time 2744.49 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 04:13:01 PM PDT 24
Peak memory 231828 kb
Host smart-148f751d-60cf-453c-87c1-ae47b8be480f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990229630 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3990229630
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/267.edn_genbits.2945418340
Short name T9
Test name
Test status
Simulation time 259844548 ps
CPU time 1.53 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 219312 kb
Host smart-f9b9c240-ec0e-4541-882d-085c29229501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945418340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2945418340
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2482954152
Short name T13
Test name
Test status
Simulation time 2247759840 ps
CPU time 3.66 seconds
Started Mar 26 03:26:15 PM PDT 24
Finished Mar 26 03:26:19 PM PDT 24
Peak memory 235604 kb
Host smart-9d0cb9f9-e920-462a-9f24-6eba32572363
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482954152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2482954152
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/9.edn_err.4248892448
Short name T4
Test name
Test status
Simulation time 29872945 ps
CPU time 1.22 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 218992 kb
Host smart-afb09ca0-f2c1-4a0f-a2da-b6448028e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248892448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.4248892448
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/41.edn_alert.4278053040
Short name T16
Test name
Test status
Simulation time 33867844 ps
CPU time 1.29 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 215596 kb
Host smart-12e832de-0823-4c8e-a330-b79320ebdbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278053040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4278053040
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2548352388
Short name T29
Test name
Test status
Simulation time 48856759 ps
CPU time 1.68 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 217936 kb
Host smart-6e951e33-d3fc-4207-a817-1b9cb8aa2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548352388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2548352388
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2942076072
Short name T143
Test name
Test status
Simulation time 31332479 ps
CPU time 1.12 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 217700 kb
Host smart-c9fb63a1-d313-4cb6-9075-52fc9a79dbec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942076072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2942076072
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/152.edn_genbits.3465183864
Short name T33
Test name
Test status
Simulation time 208094896 ps
CPU time 1.1 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 216940 kb
Host smart-388ee841-0c11-431a-b866-461681929f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465183864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3465183864
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.322331327
Short name T17
Test name
Test status
Simulation time 77293234 ps
CPU time 1.08 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215684 kb
Host smart-4fc7c864-074f-4167-aea6-ff6cfc6b8f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322331327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.322331327
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.5898325
Short name T23
Test name
Test status
Simulation time 424924490310 ps
CPU time 1862.65 seconds
Started Mar 26 03:26:59 PM PDT 24
Finished Mar 26 03:58:02 PM PDT 24
Peak memory 224168 kb
Host smart-7f96c8f9-3367-4a87-b3ac-3df1f5a8d49b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5898325 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.5898325
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_intr.1677669215
Short name T110
Test name
Test status
Simulation time 21617597 ps
CPU time 1.11 seconds
Started Mar 26 03:26:14 PM PDT 24
Finished Mar 26 03:26:15 PM PDT 24
Peak memory 215848 kb
Host smart-a4a8cd31-9d4a-448d-a691-626283d9da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677669215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1677669215
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3396362127
Short name T241
Test name
Test status
Simulation time 20900804 ps
CPU time 0.97 seconds
Started Mar 26 03:26:19 PM PDT 24
Finished Mar 26 03:26:20 PM PDT 24
Peak memory 207092 kb
Host smart-99fee54b-7135-4356-b1ac-7d84724f6f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396362127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3396362127
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_alert.4099575138
Short name T108
Test name
Test status
Simulation time 44749971 ps
CPU time 1.17 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 215600 kb
Host smart-755ff2a1-c561-46f6-9668-f6f04d4968f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099575138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4099575138
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3664260043
Short name T57
Test name
Test status
Simulation time 71326534 ps
CPU time 1.18 seconds
Started Mar 26 03:26:19 PM PDT 24
Finished Mar 26 03:26:21 PM PDT 24
Peak memory 216580 kb
Host smart-1bfae98a-c363-4d65-9fce-b11c7ce1eed7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664260043 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3664260043
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3784978610
Short name T203
Test name
Test status
Simulation time 37477557 ps
CPU time 0.86 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 206312 kb
Host smart-c6bfe718-f719-4471-b6b7-57f521dbc8ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784978610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3784978610
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.17611297
Short name T226
Test name
Test status
Simulation time 234465782 ps
CPU time 2.09 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206452 kb
Host smart-09eabea1-9567-4d6b-b7ec-cf5d7dde603e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.17611297
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/6.edn_disable.941596809
Short name T87
Test name
Test status
Simulation time 14052849 ps
CPU time 0.93 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 216132 kb
Host smart-7c805d0f-74dd-40ed-9ba7-b62ec2ea53c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941596809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.941596809
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.4020202399
Short name T105
Test name
Test status
Simulation time 22111757 ps
CPU time 0.85 seconds
Started Mar 26 03:26:53 PM PDT 24
Finished Mar 26 03:26:54 PM PDT 24
Peak memory 215864 kb
Host smart-820d2f8c-fd1a-44cd-af84-86375a8648ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020202399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4020202399
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2536091838
Short name T73
Test name
Test status
Simulation time 52060986 ps
CPU time 1.26 seconds
Started Mar 26 03:27:03 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 216452 kb
Host smart-a04a8fb2-2c5b-40bb-8c47-4fd6e145fb28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536091838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2536091838
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_alert.3910323194
Short name T242
Test name
Test status
Simulation time 88518807 ps
CPU time 1.1 seconds
Started Mar 26 03:26:48 PM PDT 24
Finished Mar 26 03:26:49 PM PDT 24
Peak memory 215612 kb
Host smart-b7a139e8-0fca-4c56-9ae1-89fffd2cb5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910323194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3910323194
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.3595075397
Short name T486
Test name
Test status
Simulation time 20639157 ps
CPU time 0.89 seconds
Started Mar 26 03:26:35 PM PDT 24
Finished Mar 26 03:26:36 PM PDT 24
Peak memory 215808 kb
Host smart-d130b420-7014-4869-94e7-76e3396d5192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595075397 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3595075397
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/19.edn_intr.3471975693
Short name T113
Test name
Test status
Simulation time 30656968 ps
CPU time 0.86 seconds
Started Mar 26 03:26:45 PM PDT 24
Finished Mar 26 03:26:46 PM PDT 24
Peak memory 215532 kb
Host smart-f2f9246b-e5fd-4eba-86df-f6302a571ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471975693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3471975693
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/259.edn_genbits.1345695413
Short name T31
Test name
Test status
Simulation time 40005779 ps
CPU time 1.44 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:18 PM PDT 24
Peak memory 217796 kb
Host smart-9fc48fe7-2931-4dc8-a823-8b0e84ddeb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345695413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1345695413
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2510622280
Short name T60
Test name
Test status
Simulation time 87139141 ps
CPU time 1.23 seconds
Started Mar 26 03:26:45 PM PDT 24
Finished Mar 26 03:26:47 PM PDT 24
Peak memory 216548 kb
Host smart-b8c3e4c6-5cf3-495d-8cec-17ea4fdd1295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510622280 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2510622280
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2105177705
Short name T56
Test name
Test status
Simulation time 44592525 ps
CPU time 1.17 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 216660 kb
Host smart-e1ba2e1d-d5f7-4ee2-b341-4cd58dc7d685
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105177705 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2105177705
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.2577752194
Short name T275
Test name
Test status
Simulation time 61941800 ps
CPU time 0.97 seconds
Started Mar 26 03:26:41 PM PDT 24
Finished Mar 26 03:26:42 PM PDT 24
Peak memory 216556 kb
Host smart-edc52e0f-f88c-4bfa-bee8-71f42afb1b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577752194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2577752194
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2663274099
Short name T22
Test name
Test status
Simulation time 42513559427 ps
CPU time 1028.56 seconds
Started Mar 26 03:26:46 PM PDT 24
Finished Mar 26 03:43:55 PM PDT 24
Peak memory 218512 kb
Host smart-f35f7f96-6e66-470e-be51-0dc77ff14386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663274099 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2663274099
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_disable.3048850837
Short name T83
Test name
Test status
Simulation time 65156584 ps
CPU time 0.83 seconds
Started Mar 26 03:26:10 PM PDT 24
Finished Mar 26 03:26:11 PM PDT 24
Peak memory 215392 kb
Host smart-a3c84892-78fa-40e9-96f6-9b21138151b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048850837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3048850837
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.970281725
Short name T139
Test name
Test status
Simulation time 78759321 ps
CPU time 0.9 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215852 kb
Host smart-1921d4bc-0e87-40e6-86f1-f92a5768c774
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970281725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.970281725
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.605274142
Short name T152
Test name
Test status
Simulation time 37805305 ps
CPU time 1.2 seconds
Started Mar 26 03:26:56 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 216460 kb
Host smart-972f7e70-2ec7-423c-8e5a-bbf8751dc1c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605274142 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.605274142
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1512890462
Short name T79
Test name
Test status
Simulation time 126849011 ps
CPU time 1.2 seconds
Started Mar 26 03:26:49 PM PDT 24
Finished Mar 26 03:26:51 PM PDT 24
Peak memory 216432 kb
Host smart-357edbae-7c8d-4a8d-83d1-8a4c77b53a05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512890462 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1512890462
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_disable.3391044213
Short name T159
Test name
Test status
Simulation time 90519381 ps
CPU time 0.84 seconds
Started Mar 26 03:26:40 PM PDT 24
Finished Mar 26 03:26:41 PM PDT 24
Peak memory 215784 kb
Host smart-5af527d9-615d-4315-949e-2d1848442def
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391044213 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3391044213
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.3020715234
Short name T106
Test name
Test status
Simulation time 12285677 ps
CPU time 0.85 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:26:39 PM PDT 24
Peak memory 215796 kb
Host smart-503330db-f9e3-49a1-8ee6-7652caabcc34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020715234 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3020715234
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.2682135438
Short name T98
Test name
Test status
Simulation time 13745446 ps
CPU time 0.87 seconds
Started Mar 26 03:27:08 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 215812 kb
Host smart-6226ba1e-e2c0-4126-b1fe-3e7dbd8bd77a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682135438 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2682135438
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2604777629
Short name T63
Test name
Test status
Simulation time 47085949 ps
CPU time 1.41 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 216368 kb
Host smart-da581152-30f9-4b39-bf5f-1e981d2cd1a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604777629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2604777629
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_regwen.993757413
Short name T239
Test name
Test status
Simulation time 18694664 ps
CPU time 1.03 seconds
Started Mar 26 03:26:12 PM PDT 24
Finished Mar 26 03:26:14 PM PDT 24
Peak memory 207104 kb
Host smart-b3caec3c-1cb2-4872-8115-9323232f7dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993757413 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.993757413
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_alert_test.1025243977
Short name T324
Test name
Test status
Simulation time 38212368 ps
CPU time 0.95 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 206464 kb
Host smart-ea9f0d10-519c-4393-ae5e-8b106e6792b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025243977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1025243977
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/124.edn_genbits.1923591827
Short name T261
Test name
Test status
Simulation time 131421442 ps
CPU time 1.65 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 218164 kb
Host smart-8bba31e6-0fb0-4dae-95ba-b9574b255473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923591827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1923591827
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.565412775
Short name T259
Test name
Test status
Simulation time 58676929 ps
CPU time 1.36 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 218064 kb
Host smart-4b8e3d2a-8196-4f18-b44f-4ac289faeed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565412775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.565412775
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.4246963486
Short name T365
Test name
Test status
Simulation time 290207987 ps
CPU time 1.16 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 215208 kb
Host smart-b5e2c464-a62d-4aec-b05d-ded454386427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246963486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4246963486
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2225509797
Short name T58
Test name
Test status
Simulation time 73655362 ps
CPU time 1.21 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 215660 kb
Host smart-edf9d223-c009-40fd-bdb0-4bf39cc26063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225509797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2225509797
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/4.edn_regwen.4029541544
Short name T236
Test name
Test status
Simulation time 43288145 ps
CPU time 0.82 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 207084 kb
Host smart-e825b064-7deb-455c-97b7-f367fc4fea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029541544 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4029541544
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/61.edn_genbits.1850021497
Short name T281
Test name
Test status
Simulation time 46622415 ps
CPU time 1.62 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 217824 kb
Host smart-f21ff195-58fd-4d14-ad1c-b449079f339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850021497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1850021497
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.2917741779
Short name T120
Test name
Test status
Simulation time 26110585 ps
CPU time 0.91 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 207076 kb
Host smart-63926a04-2b4e-4494-a7d6-b2d5d44c7a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917741779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2917741779
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/88.edn_err.978616674
Short name T55
Test name
Test status
Simulation time 44916733 ps
CPU time 0.99 seconds
Started Mar 26 03:27:38 PM PDT 24
Finished Mar 26 03:27:40 PM PDT 24
Peak memory 229716 kb
Host smart-f3e0d06f-8a7d-4ab6-a47e-10e729584741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978616674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.978616674
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3317907415
Short name T217
Test name
Test status
Simulation time 15808248 ps
CPU time 0.97 seconds
Started Mar 26 02:45:45 PM PDT 24
Finished Mar 26 02:45:46 PM PDT 24
Peak memory 206292 kb
Host smart-6f2c5c88-e6fa-4f88-8534-ed891280ce6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317907415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3317907415
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1366792698
Short name T963
Test name
Test status
Simulation time 115817564 ps
CPU time 2.83 seconds
Started Mar 26 02:45:43 PM PDT 24
Finished Mar 26 02:45:46 PM PDT 24
Peak memory 206384 kb
Host smart-78671e99-e983-4943-ba32-bdb8e58e4d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366792698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1366792698
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_stress_all.4185669646
Short name T413
Test name
Test status
Simulation time 165164840 ps
CPU time 3.65 seconds
Started Mar 26 03:26:12 PM PDT 24
Finished Mar 26 03:26:16 PM PDT 24
Peak memory 215332 kb
Host smart-a3f0fe24-000b-4ac8-872f-ecb677082054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185669646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4185669646
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_genbits.666242866
Short name T632
Test name
Test status
Simulation time 62809677 ps
CPU time 1.21 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 217880 kb
Host smart-9b9ed15b-3bc3-4d44-ae1e-737718814a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666242866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.666242866
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.1239581585
Short name T273
Test name
Test status
Simulation time 33764470 ps
CPU time 1.41 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 216888 kb
Host smart-94c66c0b-f5dc-4f03-81f5-1f023792eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239581585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1239581585
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.326163669
Short name T2
Test name
Test status
Simulation time 55456174 ps
CPU time 1.25 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 216432 kb
Host smart-af818aff-ee35-4d09-a062-b2d19dcf811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326163669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.326163669
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1963448687
Short name T412
Test name
Test status
Simulation time 79146014 ps
CPU time 1.12 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 216420 kb
Host smart-17b291d8-78a8-4925-a89c-7cc86dd9b817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963448687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1963448687
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.302690836
Short name T744
Test name
Test status
Simulation time 64119657 ps
CPU time 1.09 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:26:39 PM PDT 24
Peak memory 215624 kb
Host smart-d6ae38ff-0055-4476-a19b-222410947f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302690836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.302690836
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3168795571
Short name T263
Test name
Test status
Simulation time 999940850 ps
CPU time 7.4 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 216968 kb
Host smart-73d5c8ec-18f6-4797-972a-c185acb3362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168795571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3168795571
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2482574248
Short name T257
Test name
Test status
Simulation time 61790048 ps
CPU time 1.41 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 217944 kb
Host smart-0b83f23d-9be4-4d58-89a2-5140bd2e2470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482574248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2482574248
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.385657847
Short name T272
Test name
Test status
Simulation time 34169209 ps
CPU time 1.12 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 217968 kb
Host smart-20c14283-d350-44dd-832a-dba0a07123f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385657847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.385657847
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_alert.1931269361
Short name T243
Test name
Test status
Simulation time 73431413 ps
CPU time 1.15 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:27:20 PM PDT 24
Peak memory 215588 kb
Host smart-8ca37875-3efb-4f6e-a528-64fa3bb0853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931269361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1931269361
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/38.edn_genbits.4007867594
Short name T268
Test name
Test status
Simulation time 36312508 ps
CPU time 1.39 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 217776 kb
Host smart-4f93e39d-62d6-43b9-a1da-f7a3caeef358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007867594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4007867594
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1403579359
Short name T118
Test name
Test status
Simulation time 82992911 ps
CPU time 0.8 seconds
Started Mar 26 03:26:47 PM PDT 24
Finished Mar 26 03:26:48 PM PDT 24
Peak memory 215464 kb
Host smart-5e396ef3-608c-42dc-ab86-ef4c1e19506f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403579359 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1403579359
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/13.edn_intr.2347478959
Short name T124
Test name
Test status
Simulation time 29188170 ps
CPU time 0.85 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 215472 kb
Host smart-a8a6686a-d763-4d50-9e6d-8196e7c8231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347478959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2347478959
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/220.edn_genbits.2106693916
Short name T11
Test name
Test status
Simulation time 46828181 ps
CPU time 1.62 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 219140 kb
Host smart-9c290841-f40d-411a-9c20-ca78a4f97e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106693916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2106693916
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3619557310
Short name T171
Test name
Test status
Simulation time 24001374 ps
CPU time 1.18 seconds
Started Mar 26 03:26:44 PM PDT 24
Finished Mar 26 03:26:45 PM PDT 24
Peak memory 215584 kb
Host smart-c3345e10-ecd5-40a7-8594-bc66c0dc4898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619557310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3619557310
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/11.edn_err.1806582850
Short name T52
Test name
Test status
Simulation time 28357999 ps
CPU time 0.94 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 219404 kb
Host smart-5e38524e-b915-49f9-b3d4-541b9dfbd062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806582850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1806582850
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1029811325
Short name T970
Test name
Test status
Simulation time 39902620 ps
CPU time 1.22 seconds
Started Mar 26 02:45:43 PM PDT 24
Finished Mar 26 02:45:45 PM PDT 24
Peak memory 206308 kb
Host smart-73896a12-6306-446e-bf7d-1de0528bf4b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029811325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1029811325
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2391911396
Short name T860
Test name
Test status
Simulation time 521175743 ps
CPU time 3.5 seconds
Started Mar 26 02:45:42 PM PDT 24
Finished Mar 26 02:45:45 PM PDT 24
Peak memory 206284 kb
Host smart-a621c31a-702c-4e73-9478-90e1ca3594c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391911396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2391911396
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.950787475
Short name T871
Test name
Test status
Simulation time 24625168 ps
CPU time 0.94 seconds
Started Mar 26 02:45:41 PM PDT 24
Finished Mar 26 02:45:42 PM PDT 24
Peak memory 206208 kb
Host smart-2b73fe22-3b1b-4918-97b5-bf38ab6b51c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950787475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.950787475
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3604083861
Short name T851
Test name
Test status
Simulation time 21091207 ps
CPU time 1.06 seconds
Started Mar 26 02:45:44 PM PDT 24
Finished Mar 26 02:45:46 PM PDT 24
Peak memory 215672 kb
Host smart-cb229e9a-d21d-4d8e-b5b1-8072c9e2bf6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604083861 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3604083861
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.795238512
Short name T901
Test name
Test status
Simulation time 63537793 ps
CPU time 0.81 seconds
Started Mar 26 02:45:44 PM PDT 24
Finished Mar 26 02:45:45 PM PDT 24
Peak memory 206076 kb
Host smart-39964878-c937-43e7-8005-86a4e267cb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795238512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.795238512
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1895611786
Short name T919
Test name
Test status
Simulation time 14197467 ps
CPU time 1.03 seconds
Started Mar 26 02:45:43 PM PDT 24
Finished Mar 26 02:45:44 PM PDT 24
Peak memory 206524 kb
Host smart-9ded0ebb-a160-4ae8-be49-3005f2deceb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895611786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1895611786
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1904379185
Short name T848
Test name
Test status
Simulation time 69920237 ps
CPU time 2.38 seconds
Started Mar 26 02:45:43 PM PDT 24
Finished Mar 26 02:45:46 PM PDT 24
Peak memory 214628 kb
Host smart-1604ff80-c2fb-4c14-9341-ac46a8c90a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904379185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1904379185
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3341847771
Short name T920
Test name
Test status
Simulation time 27484682 ps
CPU time 1.12 seconds
Started Mar 26 02:45:44 PM PDT 24
Finished Mar 26 02:45:45 PM PDT 24
Peak memory 206292 kb
Host smart-7f00b209-c5eb-4345-876f-029701cfc2e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341847771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3341847771
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.94439995
Short name T954
Test name
Test status
Simulation time 143550848 ps
CPU time 3.28 seconds
Started Mar 26 02:45:42 PM PDT 24
Finished Mar 26 02:45:46 PM PDT 24
Peak memory 206220 kb
Host smart-95962fcf-21df-47b5-bdce-94c4d7a2283a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94439995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.94439995
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4260908373
Short name T212
Test name
Test status
Simulation time 25708029 ps
CPU time 0.89 seconds
Started Mar 26 02:45:43 PM PDT 24
Finished Mar 26 02:45:44 PM PDT 24
Peak memory 206284 kb
Host smart-02179d3f-1f19-4683-9dcd-936213cbb34e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260908373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4260908373
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1158687206
Short name T881
Test name
Test status
Simulation time 49539803 ps
CPU time 1.1 seconds
Started Mar 26 02:45:41 PM PDT 24
Finished Mar 26 02:45:42 PM PDT 24
Peak memory 214660 kb
Host smart-e50613f6-630d-4312-8e63-b789c8f75413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158687206 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1158687206
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.655170045
Short name T944
Test name
Test status
Simulation time 21193082 ps
CPU time 0.83 seconds
Started Mar 26 02:45:43 PM PDT 24
Finished Mar 26 02:45:44 PM PDT 24
Peak memory 206068 kb
Host smart-994cd7de-d161-46b9-8296-d4bb5fd1d17f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655170045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.655170045
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2769289133
Short name T873
Test name
Test status
Simulation time 43258492 ps
CPU time 0.89 seconds
Started Mar 26 02:45:42 PM PDT 24
Finished Mar 26 02:45:43 PM PDT 24
Peak memory 206300 kb
Host smart-c0400786-fb96-4fd1-9f62-d686b48192c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769289133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2769289133
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1786619372
Short name T913
Test name
Test status
Simulation time 15268616 ps
CPU time 1.01 seconds
Started Mar 26 02:45:47 PM PDT 24
Finished Mar 26 02:45:48 PM PDT 24
Peak memory 206492 kb
Host smart-6a00b247-321a-4149-bd22-c5f27e7dd8a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786619372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1786619372
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2452640068
Short name T875
Test name
Test status
Simulation time 94489399 ps
CPU time 3.28 seconds
Started Mar 26 02:45:44 PM PDT 24
Finished Mar 26 02:45:47 PM PDT 24
Peak memory 214640 kb
Host smart-cec3c785-f9fa-4ae1-b9a2-2113bbbb229a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452640068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2452640068
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.970891934
Short name T902
Test name
Test status
Simulation time 1245805546 ps
CPU time 2.63 seconds
Started Mar 26 02:45:47 PM PDT 24
Finished Mar 26 02:45:50 PM PDT 24
Peak memory 206456 kb
Host smart-dc03b8d2-61b3-429a-b305-fc6385f32b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970891934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.970891934
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2220051574
Short name T864
Test name
Test status
Simulation time 133126916 ps
CPU time 0.97 seconds
Started Mar 26 02:46:04 PM PDT 24
Finished Mar 26 02:46:05 PM PDT 24
Peak memory 206500 kb
Host smart-996b2a4d-6a32-4361-9fda-eb1465b730e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220051574 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2220051574
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.935780460
Short name T943
Test name
Test status
Simulation time 16876141 ps
CPU time 0.96 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206288 kb
Host smart-45348f89-d4bf-4265-9f51-4ae6c3532010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935780460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.935780460
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.998236567
Short name T893
Test name
Test status
Simulation time 38916176 ps
CPU time 0.8 seconds
Started Mar 26 02:46:09 PM PDT 24
Finished Mar 26 02:46:10 PM PDT 24
Peak memory 206044 kb
Host smart-e27f56ce-f381-4c2f-94e6-dc5c36306121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998236567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.998236567
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2955425742
Short name T937
Test name
Test status
Simulation time 83187091 ps
CPU time 1.11 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:06 PM PDT 24
Peak memory 206432 kb
Host smart-9731cdb5-1cc9-4eff-bd32-4a567cca70fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955425742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2955425742
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1923986731
Short name T946
Test name
Test status
Simulation time 488798321 ps
CPU time 1.95 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 214808 kb
Host smart-42e01567-5877-41e3-9413-269a5cf810cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923986731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1923986731
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1107590641
Short name T957
Test name
Test status
Simulation time 207201085 ps
CPU time 1.99 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:59 PM PDT 24
Peak memory 206508 kb
Host smart-8ee7132f-aa48-4eba-bec3-c14928a70110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107590641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1107590641
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2567297180
Short name T940
Test name
Test status
Simulation time 60420212 ps
CPU time 1.09 seconds
Started Mar 26 02:46:09 PM PDT 24
Finished Mar 26 02:46:11 PM PDT 24
Peak memory 214620 kb
Host smart-f2537eb0-f12e-4dea-815a-7d61ecb8bb6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567297180 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2567297180
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2386102932
Short name T207
Test name
Test status
Simulation time 11016861 ps
CPU time 0.86 seconds
Started Mar 26 02:46:03 PM PDT 24
Finished Mar 26 02:46:04 PM PDT 24
Peak memory 206268 kb
Host smart-7f447022-5aed-4c5f-babd-515d43c8d611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386102932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2386102932
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2808718398
Short name T855
Test name
Test status
Simulation time 42324527 ps
CPU time 0.9 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206288 kb
Host smart-504fec41-eb86-457e-a102-206ebb39824e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808718398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2808718398
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.423988806
Short name T969
Test name
Test status
Simulation time 105265529 ps
CPU time 1.14 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206420 kb
Host smart-ad17121f-549f-49a0-afa3-17cfa5ad4d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423988806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.423988806
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1074492521
Short name T846
Test name
Test status
Simulation time 473901093 ps
CPU time 4.15 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:12 PM PDT 24
Peak memory 214740 kb
Host smart-c6c1e0fa-2964-4704-9f91-5c2fcda10161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074492521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1074492521
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1431769053
Short name T232
Test name
Test status
Simulation time 257316043 ps
CPU time 2.14 seconds
Started Mar 26 02:46:02 PM PDT 24
Finished Mar 26 02:46:04 PM PDT 24
Peak memory 206472 kb
Host smart-f28cf4c4-f51f-4974-888b-1c1dab6908d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431769053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1431769053
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.787072853
Short name T877
Test name
Test status
Simulation time 30923481 ps
CPU time 1.47 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:10 PM PDT 24
Peak memory 214680 kb
Host smart-dd0a5c9e-4b62-476d-aa4d-b2833b79fc91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787072853 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.787072853
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3006270980
Short name T935
Test name
Test status
Simulation time 44545439 ps
CPU time 0.85 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206288 kb
Host smart-63d58eee-1f5d-47ed-a51a-390c90ddfb3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006270980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3006270980
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.731257038
Short name T915
Test name
Test status
Simulation time 43707819 ps
CPU time 0.86 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206264 kb
Host smart-327b942f-d385-4e0a-99af-9c1e463ac7f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731257038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.731257038
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.844576389
Short name T219
Test name
Test status
Simulation time 108727017 ps
CPU time 1.32 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 206472 kb
Host smart-d1ba3e6e-b23d-4f5b-85e0-1846543be8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844576389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.844576389
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3282966812
Short name T929
Test name
Test status
Simulation time 101323363 ps
CPU time 3.54 seconds
Started Mar 26 02:46:04 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 214760 kb
Host smart-a672b232-048d-4d37-b53a-4d95a8e1e129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282966812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3282966812
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3246406293
Short name T231
Test name
Test status
Simulation time 70925361 ps
CPU time 2.14 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 206488 kb
Host smart-32441287-4216-443d-9517-fd54305ea1af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246406293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3246406293
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2095798311
Short name T928
Test name
Test status
Simulation time 95153188 ps
CPU time 1.22 seconds
Started Mar 26 02:46:03 PM PDT 24
Finished Mar 26 02:46:05 PM PDT 24
Peak memory 214724 kb
Host smart-8d0505b4-e7b8-498f-beec-3d47677eecd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095798311 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2095798311
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4182063415
Short name T953
Test name
Test status
Simulation time 51229812 ps
CPU time 0.85 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 206132 kb
Host smart-3d3a6a89-ded5-4a10-a391-34262d147a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182063415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4182063415
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3921872649
Short name T942
Test name
Test status
Simulation time 75464635 ps
CPU time 1.33 seconds
Started Mar 26 02:46:03 PM PDT 24
Finished Mar 26 02:46:05 PM PDT 24
Peak memory 206364 kb
Host smart-4b046b19-a8a0-46e0-8798-0d1c5af9b741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921872649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3921872649
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2968371320
Short name T947
Test name
Test status
Simulation time 90214171 ps
CPU time 1.66 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 214760 kb
Host smart-de8001c2-f289-4ed8-81f5-4e87cddaf989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968371320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2968371320
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2020692647
Short name T961
Test name
Test status
Simulation time 91050372 ps
CPU time 1.49 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206380 kb
Host smart-ae7efc5c-9cda-4174-80a0-d3d600fe82ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020692647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2020692647
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2027730059
Short name T938
Test name
Test status
Simulation time 244795681 ps
CPU time 1.01 seconds
Started Mar 26 02:46:04 PM PDT 24
Finished Mar 26 02:46:06 PM PDT 24
Peak memory 214692 kb
Host smart-548e52aa-edff-4757-b541-6bccdba73602
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027730059 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2027730059
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2374068478
Short name T213
Test name
Test status
Simulation time 32002601 ps
CPU time 1.24 seconds
Started Mar 26 02:46:04 PM PDT 24
Finished Mar 26 02:46:06 PM PDT 24
Peak memory 206288 kb
Host smart-7cde55f2-3538-4817-b61f-f4ee3d469f79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374068478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2374068478
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2562299872
Short name T870
Test name
Test status
Simulation time 115373340 ps
CPU time 0.83 seconds
Started Mar 26 02:46:02 PM PDT 24
Finished Mar 26 02:46:03 PM PDT 24
Peak memory 206020 kb
Host smart-5478e4db-cd2a-4d2b-a885-316b068272e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562299872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2562299872
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1732425992
Short name T914
Test name
Test status
Simulation time 45338570 ps
CPU time 1.12 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206416 kb
Host smart-ab13976a-6819-41d4-84e4-8a3aa159e37c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732425992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1732425992
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3421731004
Short name T839
Test name
Test status
Simulation time 212014040 ps
CPU time 2.62 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 214696 kb
Host smart-40658001-89cb-4a8f-82a7-7b90361c4e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421731004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3421731004
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.965176565
Short name T908
Test name
Test status
Simulation time 1076979994 ps
CPU time 2.26 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206528 kb
Host smart-47be8780-8303-4101-b545-3c0aec6bf8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965176565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.965176565
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1660649911
Short name T842
Test name
Test status
Simulation time 37196349 ps
CPU time 1.54 seconds
Started Mar 26 02:46:03 PM PDT 24
Finished Mar 26 02:46:05 PM PDT 24
Peak memory 214664 kb
Host smart-de6cbad1-a631-4f40-80ee-38edfa1e2d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660649911 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1660649911
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.204673045
Short name T208
Test name
Test status
Simulation time 19819125 ps
CPU time 0.9 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206172 kb
Host smart-76e4248e-dd86-4db3-9cc4-e96e146d95f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204673045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.204673045
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.454153987
Short name T912
Test name
Test status
Simulation time 40359018 ps
CPU time 0.87 seconds
Started Mar 26 02:46:11 PM PDT 24
Finished Mar 26 02:46:12 PM PDT 24
Peak memory 206080 kb
Host smart-c41f642d-0c6f-4f8b-b7ae-eb321b1f6ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454153987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.454153987
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.833907590
Short name T211
Test name
Test status
Simulation time 138048508 ps
CPU time 1.3 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206428 kb
Host smart-9854c08d-7f30-40c4-9a8a-872ec201ecdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833907590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.833907590
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2321770965
Short name T844
Test name
Test status
Simulation time 58054353 ps
CPU time 2.32 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 214716 kb
Host smart-3764e784-a332-4ac7-a36b-0d8dc0dcba0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321770965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2321770965
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3091865681
Short name T852
Test name
Test status
Simulation time 65761941 ps
CPU time 1.1 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 214700 kb
Host smart-8e1163d3-ecac-4f10-af07-b9c2bf7d493f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091865681 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3091865681
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4277073749
Short name T924
Test name
Test status
Simulation time 31813262 ps
CPU time 0.9 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206224 kb
Host smart-7801aa42-1442-462c-8420-23d349111d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277073749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4277073749
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3950391348
Short name T916
Test name
Test status
Simulation time 13483497 ps
CPU time 0.85 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206280 kb
Host smart-3eb596e9-c8e3-43c1-b067-8618374b3491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950391348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3950391348
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3052532901
Short name T950
Test name
Test status
Simulation time 26053728 ps
CPU time 0.95 seconds
Started Mar 26 02:46:03 PM PDT 24
Finished Mar 26 02:46:05 PM PDT 24
Peak memory 206448 kb
Host smart-6a8fd9f8-6a76-4d05-bf1a-02d2e5384054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052532901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3052532901
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2895335185
Short name T952
Test name
Test status
Simulation time 91837160 ps
CPU time 3.69 seconds
Started Mar 26 02:46:09 PM PDT 24
Finished Mar 26 02:46:13 PM PDT 24
Peak memory 214696 kb
Host smart-edd4a7e7-80c6-450d-b10c-8301af50f351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895335185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2895335185
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4196621168
Short name T233
Test name
Test status
Simulation time 134424941 ps
CPU time 1.34 seconds
Started Mar 26 02:46:04 PM PDT 24
Finished Mar 26 02:46:06 PM PDT 24
Peak memory 206404 kb
Host smart-1fe14d2c-c1a3-491e-bca3-dd3717220cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196621168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4196621168
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4276136553
Short name T923
Test name
Test status
Simulation time 68993801 ps
CPU time 1.51 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 214776 kb
Host smart-036e3322-fe20-4cae-af6f-22af03ec46c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276136553 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4276136553
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1921694632
Short name T210
Test name
Test status
Simulation time 82501754 ps
CPU time 0.82 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 206104 kb
Host smart-3f03348d-c83c-4191-8812-c25e8fe38c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921694632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1921694632
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.509313961
Short name T845
Test name
Test status
Simulation time 33209810 ps
CPU time 0.8 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206040 kb
Host smart-600f5491-f7ab-4dfd-8117-fea8d1f87e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509313961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.509313961
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3545650435
Short name T220
Test name
Test status
Simulation time 21839712 ps
CPU time 0.91 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206368 kb
Host smart-99ac227b-3f8f-4afe-a78d-da1d829e3d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545650435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3545650435
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2850299486
Short name T966
Test name
Test status
Simulation time 49431704 ps
CPU time 1.97 seconds
Started Mar 26 02:46:09 PM PDT 24
Finished Mar 26 02:46:11 PM PDT 24
Peak memory 214732 kb
Host smart-bd1db79f-4041-4186-8d24-e38b166e8957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850299486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2850299486
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3670255223
Short name T225
Test name
Test status
Simulation time 43991615 ps
CPU time 1.51 seconds
Started Mar 26 02:46:06 PM PDT 24
Finished Mar 26 02:46:07 PM PDT 24
Peak memory 206460 kb
Host smart-d8739765-324a-4181-9c03-532e00f46fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670255223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3670255223
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1277572800
Short name T900
Test name
Test status
Simulation time 36352043 ps
CPU time 1.12 seconds
Started Mar 26 02:46:09 PM PDT 24
Finished Mar 26 02:46:11 PM PDT 24
Peak memory 214684 kb
Host smart-65c98d0b-b8f8-4574-84e4-d849d0cb7d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277572800 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1277572800
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.467943372
Short name T904
Test name
Test status
Simulation time 27322751 ps
CPU time 0.92 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206260 kb
Host smart-cd2e2148-4562-4dd1-919d-dcef2f989ba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467943372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.467943372
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2540444872
Short name T886
Test name
Test status
Simulation time 61059954 ps
CPU time 0.82 seconds
Started Mar 26 02:46:05 PM PDT 24
Finished Mar 26 02:46:06 PM PDT 24
Peak memory 206124 kb
Host smart-d3ab7673-01f5-43a4-b5fa-4eb7a8b5bb8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540444872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2540444872
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.350967717
Short name T945
Test name
Test status
Simulation time 22587309 ps
CPU time 1.04 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:08 PM PDT 24
Peak memory 206408 kb
Host smart-e8f593d2-e391-442d-8767-970fd7a05968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350967717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.350967717
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1385887987
Short name T934
Test name
Test status
Simulation time 118283849 ps
CPU time 2.5 seconds
Started Mar 26 02:46:03 PM PDT 24
Finished Mar 26 02:46:05 PM PDT 24
Peak memory 214748 kb
Host smart-2e8da10e-67be-4dc0-a556-f27f64b01947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385887987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1385887987
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.540091090
Short name T235
Test name
Test status
Simulation time 82781427 ps
CPU time 1.67 seconds
Started Mar 26 02:46:07 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206456 kb
Host smart-d3b6713e-8a90-40d1-b43c-4685e2bf03c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540091090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.540091090
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3041570879
Short name T850
Test name
Test status
Simulation time 74400353 ps
CPU time 1.17 seconds
Started Mar 26 02:46:13 PM PDT 24
Finished Mar 26 02:46:14 PM PDT 24
Peak memory 216240 kb
Host smart-7c42815a-a6cd-4d69-98d8-dc214bd88b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041570879 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3041570879
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3176371367
Short name T960
Test name
Test status
Simulation time 26456755 ps
CPU time 0.95 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206320 kb
Host smart-5e63146b-5a9c-4b3d-bf9c-138b50b22b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176371367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3176371367
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1634858437
Short name T863
Test name
Test status
Simulation time 20993862 ps
CPU time 0.83 seconds
Started Mar 26 02:46:11 PM PDT 24
Finished Mar 26 02:46:12 PM PDT 24
Peak memory 206260 kb
Host smart-07c911c9-de85-488c-b881-157aecb9e2aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634858437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1634858437
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1309108027
Short name T922
Test name
Test status
Simulation time 45206742 ps
CPU time 1.04 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206424 kb
Host smart-35e1a0af-4c11-4132-8624-4cd2dc1f2adb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309108027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1309108027
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2972260974
Short name T927
Test name
Test status
Simulation time 357800855 ps
CPU time 3.49 seconds
Started Mar 26 02:46:42 PM PDT 24
Finished Mar 26 02:46:45 PM PDT 24
Peak memory 214696 kb
Host smart-f822a36f-0e8a-431d-b8c4-52b018c8b077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972260974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2972260974
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.662225983
Short name T933
Test name
Test status
Simulation time 157331654 ps
CPU time 1.52 seconds
Started Mar 26 02:46:08 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 206496 kb
Host smart-9881a632-ce18-4aef-b116-94d0fb0ba20f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662225983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.662225983
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3406461087
Short name T215
Test name
Test status
Simulation time 125369981 ps
CPU time 1.54 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206296 kb
Host smart-8377e7b7-bfcf-4f80-a082-d134e68d82f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406461087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3406461087
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1215560363
Short name T205
Test name
Test status
Simulation time 61143835 ps
CPU time 3.13 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206384 kb
Host smart-cc0a31b2-c1bb-4b16-877b-188ae4f51447
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215560363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1215560363
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3195749530
Short name T224
Test name
Test status
Simulation time 57220379 ps
CPU time 0.93 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206280 kb
Host smart-9505eee1-3fd4-4858-84c3-5e70f3f09463
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195749530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3195749530
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2222271465
Short name T890
Test name
Test status
Simulation time 23381390 ps
CPU time 1.19 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 216024 kb
Host smart-89b2bccc-4645-4c30-abf1-35f5320fc675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222271465 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2222271465
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3314758246
Short name T216
Test name
Test status
Simulation time 53698129 ps
CPU time 0.89 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206320 kb
Host smart-9799e521-02e9-4101-afb9-533a5bc9ef46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314758246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3314758246
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1355012663
Short name T867
Test name
Test status
Simulation time 39632114 ps
CPU time 0.82 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206108 kb
Host smart-f200fefe-cecd-4d7c-a8f0-5c4312d68d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355012663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1355012663
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2635937989
Short name T906
Test name
Test status
Simulation time 18444007 ps
CPU time 1.17 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206492 kb
Host smart-d08b5748-42d7-4ea9-bd0d-697c89199c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635937989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2635937989
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2111514390
Short name T884
Test name
Test status
Simulation time 219788939 ps
CPU time 2.36 seconds
Started Mar 26 02:45:53 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 222956 kb
Host smart-b079f1ab-01db-473f-899a-2f6e5796bf8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111514390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2111514390
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3634474332
Short name T967
Test name
Test status
Simulation time 119636857 ps
CPU time 1.39 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206416 kb
Host smart-54db1676-ee48-4d43-878b-9d71be3b0bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634474332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3634474332
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.4140631697
Short name T862
Test name
Test status
Simulation time 45128364 ps
CPU time 0.9 seconds
Started Mar 26 02:46:13 PM PDT 24
Finished Mar 26 02:46:14 PM PDT 24
Peak memory 206280 kb
Host smart-235008aa-91cc-40bc-a550-dec41260707c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140631697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4140631697
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.169847803
Short name T885
Test name
Test status
Simulation time 28287773 ps
CPU time 0.86 seconds
Started Mar 26 02:46:13 PM PDT 24
Finished Mar 26 02:46:14 PM PDT 24
Peak memory 206072 kb
Host smart-854dde5a-a67c-4b7f-adee-7e1039ce2f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169847803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.169847803
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2433847561
Short name T896
Test name
Test status
Simulation time 21179702 ps
CPU time 0.8 seconds
Started Mar 26 02:46:15 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206080 kb
Host smart-0dab1e8b-779f-4972-828b-98c52f4c8eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433847561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2433847561
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1935993586
Short name T918
Test name
Test status
Simulation time 41897316 ps
CPU time 0.81 seconds
Started Mar 26 02:46:17 PM PDT 24
Finished Mar 26 02:46:18 PM PDT 24
Peak memory 206252 kb
Host smart-63094802-fafa-4334-9f5b-8a89e0442e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935993586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1935993586
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.991569249
Short name T888
Test name
Test status
Simulation time 14935361 ps
CPU time 0.9 seconds
Started Mar 26 02:46:13 PM PDT 24
Finished Mar 26 02:46:14 PM PDT 24
Peak memory 206288 kb
Host smart-610e8a4f-41db-499f-b087-6fcf95e916fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991569249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.991569249
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.52190265
Short name T926
Test name
Test status
Simulation time 15253095 ps
CPU time 0.89 seconds
Started Mar 26 02:46:17 PM PDT 24
Finished Mar 26 02:46:18 PM PDT 24
Peak memory 206304 kb
Host smart-b97d71d5-0143-4eab-bdd2-4eeae44c44fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52190265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.52190265
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2217183769
Short name T861
Test name
Test status
Simulation time 30063824 ps
CPU time 0.87 seconds
Started Mar 26 02:46:12 PM PDT 24
Finished Mar 26 02:46:13 PM PDT 24
Peak memory 206308 kb
Host smart-9a217295-93ae-4f4a-8399-04307735549f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217183769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2217183769
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1095629834
Short name T849
Test name
Test status
Simulation time 13226596 ps
CPU time 0.88 seconds
Started Mar 26 02:46:23 PM PDT 24
Finished Mar 26 02:46:24 PM PDT 24
Peak memory 206200 kb
Host smart-1385dfa3-cb6e-4421-b72d-9a606428698e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095629834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1095629834
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2257752894
Short name T857
Test name
Test status
Simulation time 19957931 ps
CPU time 0.99 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206208 kb
Host smart-cbac3011-8dd3-46e5-b85d-391befa25d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257752894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2257752894
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3935501062
Short name T931
Test name
Test status
Simulation time 19141571 ps
CPU time 0.82 seconds
Started Mar 26 02:46:16 PM PDT 24
Finished Mar 26 02:46:17 PM PDT 24
Peak memory 206288 kb
Host smart-af5db445-32e7-4937-a7db-e656f3c873af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935501062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3935501062
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.437191855
Short name T897
Test name
Test status
Simulation time 42141679 ps
CPU time 1.13 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206256 kb
Host smart-15b96ce7-41a0-4a33-80ac-6e5edfd3bbea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437191855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.437191855
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1766550503
Short name T878
Test name
Test status
Simulation time 1008522160 ps
CPU time 6.68 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:46:03 PM PDT 24
Peak memory 206296 kb
Host smart-0e4795b0-527d-4259-b633-d8f206e02334
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766550503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1766550503
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.41835899
Short name T204
Test name
Test status
Simulation time 23864615 ps
CPU time 0.88 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206268 kb
Host smart-4be4e716-c9d9-4ce9-904c-5f8052287efd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41835899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.41835899
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2003002934
Short name T879
Test name
Test status
Simulation time 38614252 ps
CPU time 1.12 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 214740 kb
Host smart-2058a9b4-f920-4e89-bb65-184a7c547741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003002934 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2003002934
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3307875518
Short name T214
Test name
Test status
Simulation time 17875199 ps
CPU time 0.88 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206264 kb
Host smart-2d5b34ff-484c-436c-9339-e7ab74f3a88e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307875518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3307875518
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.869795181
Short name T911
Test name
Test status
Simulation time 22634105 ps
CPU time 0.84 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206292 kb
Host smart-f814990c-8aee-4c26-aa3e-ac2ef9bcbb78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869795181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.869795181
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2245192669
Short name T218
Test name
Test status
Simulation time 108477999 ps
CPU time 1.38 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206448 kb
Host smart-1f0ffdad-8b3a-4347-9058-b17d73aea09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245192669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2245192669
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3615803872
Short name T948
Test name
Test status
Simulation time 458472669 ps
CPU time 4.53 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:59 PM PDT 24
Peak memory 214692 kb
Host smart-42bd1d39-3e0f-48fd-bc61-8e230aeec4f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615803872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3615803872
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3503572528
Short name T227
Test name
Test status
Simulation time 89809759 ps
CPU time 2.23 seconds
Started Mar 26 02:45:53 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206400 kb
Host smart-66729be7-d91a-487f-a254-469f8c7c2362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503572528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3503572528
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3601403147
Short name T854
Test name
Test status
Simulation time 28702265 ps
CPU time 0.94 seconds
Started Mar 26 02:46:23 PM PDT 24
Finished Mar 26 02:46:24 PM PDT 24
Peak memory 206200 kb
Host smart-50fa6167-6568-4fd3-afc3-35ae656481df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601403147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3601403147
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1247300680
Short name T858
Test name
Test status
Simulation time 32769977 ps
CPU time 0.81 seconds
Started Mar 26 02:46:19 PM PDT 24
Finished Mar 26 02:46:20 PM PDT 24
Peak memory 206088 kb
Host smart-549dbeef-ef9e-45b9-9935-6f4f8088fd06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247300680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1247300680
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3633849154
Short name T932
Test name
Test status
Simulation time 17765044 ps
CPU time 0.89 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206288 kb
Host smart-59fccbcb-1848-457b-8bb1-dfd0bc3b4beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633849154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3633849154
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1521421981
Short name T838
Test name
Test status
Simulation time 45489033 ps
CPU time 0.86 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206288 kb
Host smart-8deaa138-bc65-4a65-a3a8-5069ad9da381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521421981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1521421981
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.781763774
Short name T936
Test name
Test status
Simulation time 14279428 ps
CPU time 0.92 seconds
Started Mar 26 02:46:13 PM PDT 24
Finished Mar 26 02:46:14 PM PDT 24
Peak memory 206288 kb
Host smart-3dc0de9a-c12e-492f-b2b7-a5f0869b2cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781763774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.781763774
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3773449639
Short name T951
Test name
Test status
Simulation time 54154594 ps
CPU time 0.92 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206128 kb
Host smart-bee14724-3baf-4f3e-bac7-a6100af64491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773449639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3773449639
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4138134324
Short name T930
Test name
Test status
Simulation time 21544779 ps
CPU time 0.88 seconds
Started Mar 26 02:46:15 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206304 kb
Host smart-482c7187-033d-4fd2-848b-9e9f80dc0e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138134324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4138134324
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1123379144
Short name T962
Test name
Test status
Simulation time 28437788 ps
CPU time 0.92 seconds
Started Mar 26 02:46:23 PM PDT 24
Finished Mar 26 02:46:24 PM PDT 24
Peak memory 206200 kb
Host smart-0f203bcb-b146-4978-b6e0-72a5356e9987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123379144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1123379144
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1616105043
Short name T853
Test name
Test status
Simulation time 13179671 ps
CPU time 0.84 seconds
Started Mar 26 02:46:16 PM PDT 24
Finished Mar 26 02:46:17 PM PDT 24
Peak memory 206280 kb
Host smart-8bd92de5-c01a-490e-b7e8-0c57755bcf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616105043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1616105043
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1286641027
Short name T898
Test name
Test status
Simulation time 27057777 ps
CPU time 0.91 seconds
Started Mar 26 02:46:15 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206220 kb
Host smart-32ac2739-6ae8-4cd3-8d2e-09d0ab7da4c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286641027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1286641027
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.126809800
Short name T905
Test name
Test status
Simulation time 90543046 ps
CPU time 1.64 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206212 kb
Host smart-51644ab4-cd56-4014-92df-3e8e46845df7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126809800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.126809800
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1111963804
Short name T964
Test name
Test status
Simulation time 253041257 ps
CPU time 6.45 seconds
Started Mar 26 02:45:58 PM PDT 24
Finished Mar 26 02:46:04 PM PDT 24
Peak memory 206284 kb
Host smart-ba44891b-4c24-457f-82c9-368604750ba4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111963804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1111963804
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3434045032
Short name T968
Test name
Test status
Simulation time 39943133 ps
CPU time 0.92 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206284 kb
Host smart-dbbbe513-c17d-4350-9d0a-130948c2681b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434045032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3434045032
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.623377175
Short name T866
Test name
Test status
Simulation time 26411387 ps
CPU time 1.84 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 214776 kb
Host smart-1b213b40-a444-4ece-aed1-b1b1049aab55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623377175 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.623377175
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3339752697
Short name T895
Test name
Test status
Simulation time 23121308 ps
CPU time 0.97 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206216 kb
Host smart-f73c0e65-d4f9-4058-b35a-85c12bc6503a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339752697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3339752697
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1756146503
Short name T939
Test name
Test status
Simulation time 56052437 ps
CPU time 0.83 seconds
Started Mar 26 02:45:53 PM PDT 24
Finished Mar 26 02:45:54 PM PDT 24
Peak memory 206276 kb
Host smart-9791233f-59b8-4a69-8d46-de1b0ea8c723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756146503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1756146503
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1536248925
Short name T882
Test name
Test status
Simulation time 28298467 ps
CPU time 1 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206416 kb
Host smart-6ffb3249-29dc-42b5-8307-0218422effa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536248925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1536248925
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1937940970
Short name T917
Test name
Test status
Simulation time 154573515 ps
CPU time 1.92 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 214736 kb
Host smart-62bafdcb-862e-4c60-b7b6-d63fc35958d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937940970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1937940970
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.366197083
Short name T230
Test name
Test status
Simulation time 368095041 ps
CPU time 1.62 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206384 kb
Host smart-a44ac893-b750-4dd2-bee1-acc97392e80d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366197083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.366197083
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1383138940
Short name T865
Test name
Test status
Simulation time 14548616 ps
CPU time 0.9 seconds
Started Mar 26 02:46:16 PM PDT 24
Finished Mar 26 02:46:17 PM PDT 24
Peak memory 206288 kb
Host smart-9cbc9ba0-917e-4636-91b5-6dd5791fe601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383138940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1383138940
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2201694208
Short name T872
Test name
Test status
Simulation time 32662313 ps
CPU time 0.82 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206096 kb
Host smart-71abac70-6027-4d3b-b206-605fdf43fa5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201694208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2201694208
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2491468769
Short name T956
Test name
Test status
Simulation time 23746001 ps
CPU time 0.79 seconds
Started Mar 26 02:46:15 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206072 kb
Host smart-62d2d56f-49af-492f-ad69-3f0d2ac5f85c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491468769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2491468769
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3177886737
Short name T859
Test name
Test status
Simulation time 31109094 ps
CPU time 0.86 seconds
Started Mar 26 02:46:15 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206252 kb
Host smart-3614e91b-6701-4db8-b4eb-77167fbd9a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177886737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3177886737
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.78279896
Short name T856
Test name
Test status
Simulation time 25906500 ps
CPU time 0.87 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206404 kb
Host smart-a3c0bed0-4417-4206-87ab-39cfd3a883a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78279896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.78279896
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3386003947
Short name T910
Test name
Test status
Simulation time 55960895 ps
CPU time 0.81 seconds
Started Mar 26 02:46:18 PM PDT 24
Finished Mar 26 02:46:19 PM PDT 24
Peak memory 206088 kb
Host smart-5d8e407b-c053-4cfe-a488-a5b2eb7017e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386003947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3386003947
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4003927151
Short name T958
Test name
Test status
Simulation time 23121724 ps
CPU time 0.85 seconds
Started Mar 26 02:46:15 PM PDT 24
Finished Mar 26 02:46:16 PM PDT 24
Peak memory 206212 kb
Host smart-64da58ca-1687-4a81-a920-f8410cd9e004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003927151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4003927151
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1046476062
Short name T837
Test name
Test status
Simulation time 47514863 ps
CPU time 0.88 seconds
Started Mar 26 02:46:16 PM PDT 24
Finished Mar 26 02:46:17 PM PDT 24
Peak memory 206280 kb
Host smart-a8945d08-1ce1-4f5b-b222-095821a8e29f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046476062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1046476062
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2696351592
Short name T843
Test name
Test status
Simulation time 24223052 ps
CPU time 0.91 seconds
Started Mar 26 02:46:14 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206208 kb
Host smart-aa5c3f8c-37f3-437e-b7ce-e97c1a66231f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696351592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2696351592
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.945698520
Short name T925
Test name
Test status
Simulation time 15494019 ps
CPU time 0.92 seconds
Started Mar 26 02:46:30 PM PDT 24
Finished Mar 26 02:46:31 PM PDT 24
Peak memory 206224 kb
Host smart-7482cb95-3654-4571-8d02-f0d82d8ed144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945698520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.945698520
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4095080116
Short name T874
Test name
Test status
Simulation time 30408022 ps
CPU time 1.29 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 214676 kb
Host smart-812f5cc2-8fad-4ec2-b55d-164670ed46ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095080116 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4095080116
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.465458345
Short name T892
Test name
Test status
Simulation time 17034802 ps
CPU time 0.93 seconds
Started Mar 26 02:45:53 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206208 kb
Host smart-eb82873a-8d43-4ca8-bdc0-f6e84ca41138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465458345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.465458345
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2931205949
Short name T899
Test name
Test status
Simulation time 67066625 ps
CPU time 0.83 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206240 kb
Host smart-eff26bba-bc77-40e4-bdc7-8dabdbadb607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931205949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2931205949
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1975828442
Short name T965
Test name
Test status
Simulation time 35341055 ps
CPU time 1.42 seconds
Started Mar 26 02:45:52 PM PDT 24
Finished Mar 26 02:45:54 PM PDT 24
Peak memory 206460 kb
Host smart-216bec17-a4fd-4e23-bace-59d4da17ec7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975828442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1975828442
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3002028627
Short name T941
Test name
Test status
Simulation time 341407078 ps
CPU time 3.06 seconds
Started Mar 26 02:45:59 PM PDT 24
Finished Mar 26 02:46:02 PM PDT 24
Peak memory 214668 kb
Host smart-81acba01-352d-469d-a37c-d35a9f041d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002028627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3002028627
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1744412087
Short name T234
Test name
Test status
Simulation time 204404860 ps
CPU time 1.68 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206412 kb
Host smart-7d5c689c-36d9-41ea-882a-fa71282e8991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744412087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1744412087
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3074881500
Short name T921
Test name
Test status
Simulation time 75201559 ps
CPU time 1.1 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 214724 kb
Host smart-8cd72971-18f3-4c89-be46-dba4de076233
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074881500 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3074881500
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.848608310
Short name T209
Test name
Test status
Simulation time 116993014 ps
CPU time 0.84 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206100 kb
Host smart-b207fc52-1b4f-4bf8-ab44-da7bdc0edf9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848608310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.848608310
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1457680087
Short name T841
Test name
Test status
Simulation time 100124681 ps
CPU time 0.85 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206032 kb
Host smart-feb786bc-06a5-4608-8223-0a826b477a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457680087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1457680087
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.365573492
Short name T876
Test name
Test status
Simulation time 299770040 ps
CPU time 1.31 seconds
Started Mar 26 02:45:58 PM PDT 24
Finished Mar 26 02:45:59 PM PDT 24
Peak memory 206444 kb
Host smart-5c268bdb-6035-4776-bde7-0cfeebd771f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365573492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.365573492
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1641258962
Short name T894
Test name
Test status
Simulation time 41414228 ps
CPU time 1.61 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 217756 kb
Host smart-0f7276f8-b15c-4b4e-a92d-fc02f3574578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641258962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1641258962
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3576361413
Short name T891
Test name
Test status
Simulation time 40661033 ps
CPU time 1.58 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206352 kb
Host smart-219638cd-7914-42d3-9861-1973cfe5e64a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576361413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3576361413
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.505660020
Short name T840
Test name
Test status
Simulation time 30694835 ps
CPU time 1.2 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 214644 kb
Host smart-5bfbf460-c523-472b-99cb-898380ddca22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505660020 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.505660020
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2488798354
Short name T206
Test name
Test status
Simulation time 38329426 ps
CPU time 0.8 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206292 kb
Host smart-07b6bb0f-9234-4875-bc2e-aecfabfdd80d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488798354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2488798354
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2304439444
Short name T887
Test name
Test status
Simulation time 12898187 ps
CPU time 0.87 seconds
Started Mar 26 02:45:58 PM PDT 24
Finished Mar 26 02:45:59 PM PDT 24
Peak memory 206220 kb
Host smart-7cac3390-6a01-4118-9ec1-e466aa378b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304439444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2304439444
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2939719226
Short name T869
Test name
Test status
Simulation time 51088129 ps
CPU time 1.03 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206444 kb
Host smart-2c17cdea-27ca-44b6-a423-f0df8bc06d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939719226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2939719226
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2325568699
Short name T903
Test name
Test status
Simulation time 64790827 ps
CPU time 2.6 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 214708 kb
Host smart-c8eeb379-cef2-40c7-b6be-1e42c2845405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325568699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2325568699
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2358584889
Short name T868
Test name
Test status
Simulation time 39962808 ps
CPU time 1.56 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:56 PM PDT 24
Peak memory 206504 kb
Host smart-df3fbc56-71f8-4264-9c90-7a7c2a64a3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358584889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2358584889
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.857196038
Short name T955
Test name
Test status
Simulation time 38357212 ps
CPU time 1.1 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 214608 kb
Host smart-e3a590d6-a621-4349-9843-dd368d38369e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857196038 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.857196038
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1065318330
Short name T221
Test name
Test status
Simulation time 26611055 ps
CPU time 0.93 seconds
Started Mar 26 02:45:53 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206240 kb
Host smart-1baead0e-fb7c-42bc-a753-9d87684455cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065318330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1065318330
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.975293581
Short name T880
Test name
Test status
Simulation time 14653665 ps
CPU time 0.9 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206300 kb
Host smart-421db771-8812-4bba-896a-6b174da032f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975293581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.975293581
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2659499377
Short name T223
Test name
Test status
Simulation time 20588724 ps
CPU time 1.17 seconds
Started Mar 26 02:45:53 PM PDT 24
Finished Mar 26 02:45:54 PM PDT 24
Peak memory 206468 kb
Host smart-9d840f66-5c32-4387-be7c-eea418ca1011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659499377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2659499377
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1133674685
Short name T883
Test name
Test status
Simulation time 32582317 ps
CPU time 2.18 seconds
Started Mar 26 02:45:57 PM PDT 24
Finished Mar 26 02:45:59 PM PDT 24
Peak memory 214476 kb
Host smart-2dc4b4a1-1031-40cf-8ccb-318aab168ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133674685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1133674685
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3452878238
Short name T949
Test name
Test status
Simulation time 163218207 ps
CPU time 2.34 seconds
Started Mar 26 02:45:55 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 206480 kb
Host smart-2f0bc4f6-40cd-40e3-b2b5-fa65ffdda9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452878238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3452878238
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1295058966
Short name T959
Test name
Test status
Simulation time 105569881 ps
CPU time 1.35 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 217180 kb
Host smart-46e60804-9819-4b99-b1b6-84d77dcd3b67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295058966 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1295058966
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2379491058
Short name T222
Test name
Test status
Simulation time 101120494 ps
CPU time 0.86 seconds
Started Mar 26 02:45:58 PM PDT 24
Finished Mar 26 02:45:59 PM PDT 24
Peak memory 206104 kb
Host smart-e713dbb7-ba45-4172-a288-f8473cccb9b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379491058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2379491058
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1295912659
Short name T847
Test name
Test status
Simulation time 23760067 ps
CPU time 0.85 seconds
Started Mar 26 02:45:54 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 206320 kb
Host smart-81c84311-db96-4989-b0f0-51688df3e9b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295912659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1295912659
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4100284067
Short name T909
Test name
Test status
Simulation time 97286624 ps
CPU time 1.06 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 206432 kb
Host smart-322e40bc-73cb-428d-8582-f86859fa5a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100284067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4100284067
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3471390100
Short name T889
Test name
Test status
Simulation time 193223508 ps
CPU time 1.77 seconds
Started Mar 26 02:45:56 PM PDT 24
Finished Mar 26 02:45:58 PM PDT 24
Peak memory 214672 kb
Host smart-ca40e0db-6e4c-4aaf-a993-d6a5ff211988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471390100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3471390100
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2973771442
Short name T907
Test name
Test status
Simulation time 126735671 ps
CPU time 1.83 seconds
Started Mar 26 02:46:13 PM PDT 24
Finished Mar 26 02:46:15 PM PDT 24
Peak memory 206440 kb
Host smart-d2025e8c-070c-45d4-830a-b3547f7ca292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973771442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2973771442
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3979700405
Short name T679
Test name
Test status
Simulation time 83065762 ps
CPU time 1.2 seconds
Started Mar 26 03:26:13 PM PDT 24
Finished Mar 26 03:26:15 PM PDT 24
Peak memory 215788 kb
Host smart-b75f7910-046f-4c2e-8eeb-8796d9befd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979700405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3979700405
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.668657764
Short name T673
Test name
Test status
Simulation time 14672075 ps
CPU time 0.93 seconds
Started Mar 26 03:26:18 PM PDT 24
Finished Mar 26 03:26:19 PM PDT 24
Peak memory 205948 kb
Host smart-efdcce27-464b-4536-b6f5-e9337eeb6b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668657764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.668657764
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3969458869
Short name T165
Test name
Test status
Simulation time 26781681 ps
CPU time 0.81 seconds
Started Mar 26 03:26:09 PM PDT 24
Finished Mar 26 03:26:10 PM PDT 24
Peak memory 215800 kb
Host smart-3e2d98c8-fd06-46d3-a067-0bb0cf76ce0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969458869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3969458869
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.2429526521
Short name T91
Test name
Test status
Simulation time 43884879 ps
CPU time 1.09 seconds
Started Mar 26 03:26:17 PM PDT 24
Finished Mar 26 03:26:18 PM PDT 24
Peak memory 219084 kb
Host smart-b50075f2-09a2-4efb-a7a3-dcfb2914e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429526521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2429526521
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.448719433
Short name T654
Test name
Test status
Simulation time 86783705 ps
CPU time 1.51 seconds
Started Mar 26 03:26:17 PM PDT 24
Finished Mar 26 03:26:18 PM PDT 24
Peak memory 217956 kb
Host smart-b69227ed-9a0e-47db-8110-7aa0f012876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448719433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.448719433
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3980354526
Short name T621
Test name
Test status
Simulation time 32810610 ps
CPU time 1.08 seconds
Started Mar 26 03:26:07 PM PDT 24
Finished Mar 26 03:26:09 PM PDT 24
Peak memory 224148 kb
Host smart-a3a9d630-53e0-4b50-b256-7b05e9cde8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980354526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3980354526
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1364162767
Short name T18
Test name
Test status
Simulation time 520736861 ps
CPU time 3.7 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:24 PM PDT 24
Peak memory 235632 kb
Host smart-9d06fe71-a339-4ed8-b0d0-60d886136d52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364162767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1364162767
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.465431900
Short name T662
Test name
Test status
Simulation time 45370116 ps
CPU time 0.93 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:21 PM PDT 24
Peak memory 215264 kb
Host smart-f2b259c0-d14a-4217-9914-2e54dc57cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465431900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.465431900
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.209442047
Short name T552
Test name
Test status
Simulation time 76755411 ps
CPU time 2.06 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 215280 kb
Host smart-36476fa6-2e56-4954-a84c-6f46d6d26ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209442047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.209442047
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3207221137
Short name T183
Test name
Test status
Simulation time 136450444199 ps
CPU time 1575.74 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:52:36 PM PDT 24
Peak memory 224064 kb
Host smart-f0a6a310-d058-40fa-b729-631786239d55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207221137 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3207221137
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2309247930
Short name T776
Test name
Test status
Simulation time 38191187 ps
CPU time 1.26 seconds
Started Mar 26 03:26:19 PM PDT 24
Finished Mar 26 03:26:21 PM PDT 24
Peak memory 215596 kb
Host smart-044600fc-4ab5-451a-8596-b0f7eb0f7b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309247930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2309247930
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3162607974
Short name T422
Test name
Test status
Simulation time 127129380 ps
CPU time 0.85 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 205928 kb
Host smart-e2858cfa-b990-4b23-add2-68167e759010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162607974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3162607974
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3000716543
Short name T512
Test name
Test status
Simulation time 54304657 ps
CPU time 1.11 seconds
Started Mar 26 03:26:12 PM PDT 24
Finished Mar 26 03:26:13 PM PDT 24
Peak memory 217676 kb
Host smart-4e9a14ec-a258-4fb5-b813-8a27c8da49a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000716543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3000716543
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3463590520
Short name T72
Test name
Test status
Simulation time 28011412 ps
CPU time 1.14 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 218080 kb
Host smart-3fef2a05-7cc6-41ca-8656-0d084f92ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463590520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3463590520
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3767342625
Short name T713
Test name
Test status
Simulation time 147271241 ps
CPU time 1.11 seconds
Started Mar 26 03:26:23 PM PDT 24
Finished Mar 26 03:26:24 PM PDT 24
Peak memory 216544 kb
Host smart-e1f989ab-2e1e-48ce-bdf7-64b3e26ac6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767342625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3767342625
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3321332907
Short name T358
Test name
Test status
Simulation time 64684932 ps
CPU time 0.84 seconds
Started Mar 26 03:26:10 PM PDT 24
Finished Mar 26 03:26:11 PM PDT 24
Peak memory 215360 kb
Host smart-20e12c3e-29e3-4144-a513-a8a9d8a11b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321332907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3321332907
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3294182777
Short name T629
Test name
Test status
Simulation time 25977690 ps
CPU time 0.93 seconds
Started Mar 26 03:26:13 PM PDT 24
Finished Mar 26 03:26:14 PM PDT 24
Peak memory 207024 kb
Host smart-19a04747-6ba8-4882-9bf6-b8985121bc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294182777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3294182777
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2962656140
Short name T50
Test name
Test status
Simulation time 878646733 ps
CPU time 5.46 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:36 PM PDT 24
Peak memory 236328 kb
Host smart-b7bf7b54-69b9-4183-a248-27f6389746f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962656140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2962656140
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2335020294
Short name T701
Test name
Test status
Simulation time 42676340 ps
CPU time 0.87 seconds
Started Mar 26 03:26:11 PM PDT 24
Finished Mar 26 03:26:12 PM PDT 24
Peak memory 215308 kb
Host smart-83573f5a-f904-44c8-b66e-5905bb34d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335020294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2335020294
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1898821019
Short name T187
Test name
Test status
Simulation time 112067932164 ps
CPU time 2607.87 seconds
Started Mar 26 03:26:11 PM PDT 24
Finished Mar 26 04:09:39 PM PDT 24
Peak memory 227500 kb
Host smart-18501a34-d492-48ef-af41-485312e524b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898821019 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1898821019
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3081189208
Short name T822
Test name
Test status
Simulation time 213470800 ps
CPU time 1.43 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 215572 kb
Host smart-54def3ac-1d65-487a-84df-aa06f6e9f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081189208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3081189208
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.3123817795
Short name T830
Test name
Test status
Simulation time 94364995 ps
CPU time 0.82 seconds
Started Mar 26 03:26:47 PM PDT 24
Finished Mar 26 03:26:48 PM PDT 24
Peak memory 215896 kb
Host smart-9391125e-dcb6-484b-973b-bc6198166105
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123817795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3123817795
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1819243040
Short name T359
Test name
Test status
Simulation time 20759270 ps
CPU time 1.11 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 219472 kb
Host smart-d61ebe3f-45c1-4cb7-9851-246dd298b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819243040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1819243040
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3316155818
Short name T122
Test name
Test status
Simulation time 45446730 ps
CPU time 0.81 seconds
Started Mar 26 03:26:24 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 215504 kb
Host smart-d15790a9-6e1a-4973-9823-98e71ab2e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316155818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3316155818
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2344253785
Short name T674
Test name
Test status
Simulation time 18000261 ps
CPU time 1 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215280 kb
Host smart-baffa6db-5971-4040-baf5-04a65bd1ba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344253785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2344253785
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2851398202
Short name T780
Test name
Test status
Simulation time 557421059 ps
CPU time 2.14 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 215152 kb
Host smart-b0acf5b6-f741-4e7d-b8ee-1894d86d227f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851398202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2851398202
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.545696877
Short name T177
Test name
Test status
Simulation time 63567553348 ps
CPU time 1724.36 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:55:15 PM PDT 24
Peak memory 225304 kb
Host smart-054516d1-0875-4a36-9692-4cfbf3e383d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545696877 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.545696877
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3284513513
Short name T321
Test name
Test status
Simulation time 22605128 ps
CPU time 1.08 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 216732 kb
Host smart-b41f59a3-3a44-462c-bb90-58cdd2bbeb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284513513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3284513513
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3114378502
Short name T601
Test name
Test status
Simulation time 53747367 ps
CPU time 1.88 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 217996 kb
Host smart-6c7ea64f-d8f8-47b9-a74a-5ba146cdf5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114378502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3114378502
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3553961537
Short name T790
Test name
Test status
Simulation time 76693827 ps
CPU time 1.33 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 217636 kb
Host smart-cde0b0c2-7aa5-44a6-8aa3-826e39e455f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553961537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3553961537
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1364616953
Short name T623
Test name
Test status
Simulation time 61497495 ps
CPU time 1.02 seconds
Started Mar 26 03:27:31 PM PDT 24
Finished Mar 26 03:27:32 PM PDT 24
Peak memory 216576 kb
Host smart-96c22fb6-5c2c-4a1b-afe4-2b33ab6d2d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364616953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1364616953
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1500254642
Short name T518
Test name
Test status
Simulation time 172589168 ps
CPU time 1.27 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 217900 kb
Host smart-6f040575-e58f-473d-8d6a-5326d5f8baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500254642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1500254642
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3238007165
Short name T280
Test name
Test status
Simulation time 81695866 ps
CPU time 2.91 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 217932 kb
Host smart-2503018b-299d-4b16-99a3-008a2a8bc4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238007165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3238007165
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1997231658
Short name T357
Test name
Test status
Simulation time 54303097 ps
CPU time 1.21 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 218844 kb
Host smart-3794d591-59a4-4066-b08d-6d0b64ba0b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997231658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1997231658
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2719907854
Short name T605
Test name
Test status
Simulation time 109632949 ps
CPU time 1.37 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 218040 kb
Host smart-d6e4a175-fef1-4bab-b188-1becd53ca2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719907854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2719907854
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.41564460
Short name T431
Test name
Test status
Simulation time 57827348 ps
CPU time 1.13 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 215312 kb
Host smart-bb48aef4-1042-42b4-ae74-a19a70ce82cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41564460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.41564460
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2984903631
Short name T460
Test name
Test status
Simulation time 98592649 ps
CPU time 2.26 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 218460 kb
Host smart-378a2d2b-cecc-48d2-9329-9a876b6b035a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984903631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2984903631
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3918299815
Short name T693
Test name
Test status
Simulation time 53972050 ps
CPU time 0.89 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 206448 kb
Host smart-62c7af24-4dba-4945-abfb-54bacd838f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918299815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3918299815
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2611542525
Short name T99
Test name
Test status
Simulation time 21421484 ps
CPU time 0.85 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215860 kb
Host smart-fe161cd1-6e30-4a70-97cb-efb63c350eeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611542525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2611542525
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4184765754
Short name T74
Test name
Test status
Simulation time 40082774 ps
CPU time 1.35 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 216472 kb
Host smart-8b585b4b-3700-4d79-8972-46b3277b79f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184765754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4184765754
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2219123620
Short name T304
Test name
Test status
Simulation time 43390984 ps
CPU time 1.19 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 216696 kb
Host smart-e23160ae-42f1-460c-9970-2282a160f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219123620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2219123620
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1031188208
Short name T350
Test name
Test status
Simulation time 47175556 ps
CPU time 0.81 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 215224 kb
Host smart-b537df50-2cdd-4f93-8e94-40cf6bfb08fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031188208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1031188208
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3860253850
Short name T756
Test name
Test status
Simulation time 62391248 ps
CPU time 0.88 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 215300 kb
Host smart-ddf584b7-5eef-4970-9656-aae4f2800a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860253850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3860253850
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1844629872
Short name T810
Test name
Test status
Simulation time 229306954 ps
CPU time 4.39 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 215280 kb
Host smart-d5b19244-257a-4548-80af-c87386e9b5a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844629872 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1844629872
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1680529264
Short name T405
Test name
Test status
Simulation time 46039829983 ps
CPU time 356.34 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:32:34 PM PDT 24
Peak memory 218532 kb
Host smart-9b592d7c-1aa3-454f-81d1-215b282f7cd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680529264 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1680529264
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.316800835
Short name T544
Test name
Test status
Simulation time 45905454 ps
CPU time 1.08 seconds
Started Mar 26 03:27:41 PM PDT 24
Finished Mar 26 03:27:42 PM PDT 24
Peak memory 216488 kb
Host smart-de2a8a6a-ff81-466b-a303-c32aefa9815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316800835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.316800835
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2886468157
Short name T26
Test name
Test status
Simulation time 49593946 ps
CPU time 1.22 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 217824 kb
Host smart-55cddb64-c110-4f96-8d81-63fe8c29ebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886468157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2886468157
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2575917750
Short name T117
Test name
Test status
Simulation time 63478778 ps
CPU time 1.45 seconds
Started Mar 26 03:27:35 PM PDT 24
Finished Mar 26 03:27:36 PM PDT 24
Peak memory 218904 kb
Host smart-c3e82d02-989e-441c-b894-0574264680de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575917750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2575917750
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3546870975
Short name T353
Test name
Test status
Simulation time 109387971 ps
CPU time 2.33 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 217860 kb
Host smart-049c4faf-e926-45e4-9fc1-3c6f16232048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546870975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3546870975
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3400638441
Short name T569
Test name
Test status
Simulation time 139851771 ps
CPU time 1.24 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 216564 kb
Host smart-858f457a-1f90-4dde-9a31-c68433586eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400638441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3400638441
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.114474276
Short name T583
Test name
Test status
Simulation time 82992794 ps
CPU time 1.1 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 215272 kb
Host smart-2f3ff00d-dbd8-4fde-9166-75ea184e9394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114474276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.114474276
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.624509439
Short name T375
Test name
Test status
Simulation time 38173725 ps
CPU time 1.45 seconds
Started Mar 26 03:27:34 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 214964 kb
Host smart-e8b5e123-d80a-474d-b8b5-d073dca9ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624509439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.624509439
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3743787419
Short name T196
Test name
Test status
Simulation time 27691845 ps
CPU time 1.2 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 216780 kb
Host smart-5185a6ed-4899-4aeb-865c-57d47eb31e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743787419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3743787419
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3673813101
Short name T826
Test name
Test status
Simulation time 90620356 ps
CPU time 1.14 seconds
Started Mar 26 03:27:55 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 216508 kb
Host smart-c6fc9e5c-1b5f-4749-b3f3-96cbb2591a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673813101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3673813101
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3265638729
Short name T681
Test name
Test status
Simulation time 214150374 ps
CPU time 1.3 seconds
Started Mar 26 03:27:41 PM PDT 24
Finished Mar 26 03:27:43 PM PDT 24
Peak memory 216732 kb
Host smart-1597925e-8dd3-496b-a273-9083edc47e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265638729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3265638729
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1244438262
Short name T130
Test name
Test status
Simulation time 29911840 ps
CPU time 1.24 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 215600 kb
Host smart-2520345d-bd3f-42a9-b732-f6bd461dfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244438262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1244438262
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.608542757
Short name T339
Test name
Test status
Simulation time 37243681 ps
CPU time 0.98 seconds
Started Mar 26 03:26:40 PM PDT 24
Finished Mar 26 03:26:41 PM PDT 24
Peak memory 205952 kb
Host smart-3a61294b-7194-4bd5-a027-8255b72a36f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608542757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.608542757
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.104955374
Short name T796
Test name
Test status
Simulation time 16337482 ps
CPU time 0.84 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 215904 kb
Host smart-7bae566c-763b-484f-b0b8-43cd18d39c41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104955374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.104955374
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1014754161
Short name T421
Test name
Test status
Simulation time 31766384 ps
CPU time 0.84 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 217780 kb
Host smart-b69e67d9-2ff6-458f-bf85-e8f6f7b4380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014754161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1014754161
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.3919700671
Short name T47
Test name
Test status
Simulation time 24431808 ps
CPU time 1.26 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:48 PM PDT 24
Peak memory 224004 kb
Host smart-3d83eb9d-731b-4b8f-83e9-dbfaae9bef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919700671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3919700671
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.412386166
Short name T287
Test name
Test status
Simulation time 50951111 ps
CPU time 0.94 seconds
Started Mar 26 03:26:33 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 215284 kb
Host smart-1b1ac471-dabd-41bc-beed-02137f059bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412386166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.412386166
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3071090804
Short name T703
Test name
Test status
Simulation time 163318442 ps
CPU time 3.56 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215356 kb
Host smart-4eba9c2b-70f2-40fb-af10-bf7f380c329b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071090804 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3071090804
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3650492977
Short name T186
Test name
Test status
Simulation time 16097830240 ps
CPU time 185.75 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 218268 kb
Host smart-f742a2f0-d858-418b-8cfb-487ec43b6e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650492977 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3650492977
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2447295862
Short name T466
Test name
Test status
Simulation time 30571232 ps
CPU time 1.39 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 217912 kb
Host smart-54e33302-6272-4634-a5ed-9f1575c05d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447295862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2447295862
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3787652825
Short name T336
Test name
Test status
Simulation time 94019213 ps
CPU time 1.16 seconds
Started Mar 26 03:27:35 PM PDT 24
Finished Mar 26 03:27:37 PM PDT 24
Peak memory 218684 kb
Host smart-99e4bb0f-adc0-4ab9-8c67-bf0647f38009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787652825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3787652825
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.8358753
Short name T579
Test name
Test status
Simulation time 320183590 ps
CPU time 1.42 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 216780 kb
Host smart-c517f759-2a53-4709-9327-2a43b1de7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8358753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.8358753
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.4022855738
Short name T788
Test name
Test status
Simulation time 37029304 ps
CPU time 1.33 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 216712 kb
Host smart-57754ed2-643d-4818-ba70-838c94a85b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022855738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.4022855738
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2781160754
Short name T768
Test name
Test status
Simulation time 53881662 ps
CPU time 1.61 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 217584 kb
Host smart-762930b1-b11b-438d-8c10-2153253ddd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781160754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2781160754
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2091023259
Short name T191
Test name
Test status
Simulation time 110170045 ps
CPU time 1.38 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 218320 kb
Host smart-c05297a2-df4b-4d21-8bd4-bbc4e9d75bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091023259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2091023259
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.604700329
Short name T417
Test name
Test status
Simulation time 101913281 ps
CPU time 2.41 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 218036 kb
Host smart-ab5e43d8-68b4-4497-a9a5-ae351cda9737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604700329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.604700329
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1324636518
Short name T733
Test name
Test status
Simulation time 14819463 ps
CPU time 0.9 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 205876 kb
Host smart-e0cb6b21-afc2-49ec-b462-7dd52c108e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324636518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1324636518
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1362712425
Short name T154
Test name
Test status
Simulation time 13192257 ps
CPU time 0.88 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 215976 kb
Host smart-0a2738d9-eb25-4fbc-9955-eb379808e56c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362712425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1362712425
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1132393471
Short name T656
Test name
Test status
Simulation time 35391050 ps
CPU time 1.02 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 216480 kb
Host smart-f150130b-49a2-482b-97f6-1c2223596689
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132393471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1132393471
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3532174126
Short name T727
Test name
Test status
Simulation time 30289577 ps
CPU time 0.84 seconds
Started Mar 26 03:26:43 PM PDT 24
Finished Mar 26 03:26:44 PM PDT 24
Peak memory 217944 kb
Host smart-10844e93-0b35-4f70-9d4b-e0306a987498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532174126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3532174126
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1801092272
Short name T607
Test name
Test status
Simulation time 115292382 ps
CPU time 1.36 seconds
Started Mar 26 03:26:35 PM PDT 24
Finished Mar 26 03:26:36 PM PDT 24
Peak memory 218184 kb
Host smart-dd914f25-8828-467f-8f35-64d6ae6178cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801092272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1801092272
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.3277538306
Short name T289
Test name
Test status
Simulation time 70744856 ps
CPU time 1.01 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 215276 kb
Host smart-105afaa2-7925-4850-981a-1151ad445985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277538306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3277538306
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.60158820
Short name T836
Test name
Test status
Simulation time 81475718 ps
CPU time 1.29 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215280 kb
Host smart-baa5506f-a9a2-4057-a07e-ac69093dbf61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60158820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.60158820
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3347435190
Short name T817
Test name
Test status
Simulation time 71548953168 ps
CPU time 780.18 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:39:31 PM PDT 24
Peak memory 218536 kb
Host smart-5d4ffaeb-d788-4543-b2cf-e13502f64240
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347435190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3347435190
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1774185871
Short name T545
Test name
Test status
Simulation time 52850045 ps
CPU time 1.15 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 217568 kb
Host smart-622b258e-9baf-4eb1-ad39-8056e3781fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774185871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1774185871
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.4259904097
Short name T346
Test name
Test status
Simulation time 31207362 ps
CPU time 1.24 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 217708 kb
Host smart-6b89343f-5d97-4aab-ad70-25874f767466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259904097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.4259904097
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.425577447
Short name T686
Test name
Test status
Simulation time 61527358 ps
CPU time 1.2 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:48 PM PDT 24
Peak memory 216592 kb
Host smart-158123f1-aaff-4071-b7e9-528305c32adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425577447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.425577447
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2328878605
Short name T599
Test name
Test status
Simulation time 36824308 ps
CPU time 1.55 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 217816 kb
Host smart-a281fecb-4f25-4abf-9440-7202b97724b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328878605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2328878605
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2272725418
Short name T751
Test name
Test status
Simulation time 72622209 ps
CPU time 1 seconds
Started Mar 26 03:27:30 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 216620 kb
Host smart-07ee8466-4621-451b-80bd-66abdb520783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272725418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2272725418
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.146028777
Short name T722
Test name
Test status
Simulation time 95430074 ps
CPU time 1.28 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 218076 kb
Host smart-16e0a981-f059-4f78-beb7-7aac0c1c2f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146028777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.146028777
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.17020002
Short name T427
Test name
Test status
Simulation time 64172102 ps
CPU time 1.21 seconds
Started Mar 26 03:27:53 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 218352 kb
Host smart-1db9c08a-5a39-4b3d-aba5-d825fb4babd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17020002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.17020002
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2761438924
Short name T772
Test name
Test status
Simulation time 27531829 ps
CPU time 1.45 seconds
Started Mar 26 03:27:41 PM PDT 24
Finished Mar 26 03:27:42 PM PDT 24
Peak memory 217748 kb
Host smart-e1a6c4eb-7f4e-489d-be14-1a306dd9c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761438924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2761438924
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1699067443
Short name T253
Test name
Test status
Simulation time 22468127 ps
CPU time 1.11 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 219108 kb
Host smart-c7cde1ef-7751-4e82-890e-8a827e12fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699067443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1699067443
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.51641861
Short name T450
Test name
Test status
Simulation time 33613343 ps
CPU time 0.86 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 205948 kb
Host smart-7996ec40-7a39-4be4-9147-c14cce67f765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51641861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.51641861
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3477160642
Short name T25
Test name
Test status
Simulation time 17807309 ps
CPU time 0.82 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 215824 kb
Host smart-98c8d777-f9b5-4268-83ea-d242ce01d3b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477160642 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3477160642
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2803526009
Short name T146
Test name
Test status
Simulation time 57934802 ps
CPU time 1.1 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 216468 kb
Host smart-c99525aa-9144-4d50-b04e-6ee4a6d4c5b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803526009 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2803526009
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3860468507
Short name T559
Test name
Test status
Simulation time 57130808 ps
CPU time 1.13 seconds
Started Mar 26 03:26:49 PM PDT 24
Finished Mar 26 03:26:50 PM PDT 24
Peak memory 219168 kb
Host smart-c98d8b35-294b-471b-9be2-f09a24b31763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860468507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3860468507
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.814594261
Short name T513
Test name
Test status
Simulation time 45529403 ps
CPU time 1.64 seconds
Started Mar 26 03:26:43 PM PDT 24
Finished Mar 26 03:26:44 PM PDT 24
Peak memory 217896 kb
Host smart-f70ba7f7-f880-4033-8f3e-c7f6f6998a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814594261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.814594261
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4236868107
Short name T44
Test name
Test status
Simulation time 53616235 ps
CPU time 0.95 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:43 PM PDT 24
Peak memory 223840 kb
Host smart-bfb3a045-9dca-47d0-81d5-c5c4ab06209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236868107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4236868107
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2639696954
Short name T823
Test name
Test status
Simulation time 43797121 ps
CPU time 0.86 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215240 kb
Host smart-9afdd961-5162-460a-91c2-713daca18789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639696954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2639696954
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.760546744
Short name T730
Test name
Test status
Simulation time 1698470183 ps
CPU time 4.11 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 216344 kb
Host smart-c87903b8-8c2d-4293-a948-74cfe8782683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760546744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.760546744
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3444497807
Short name T631
Test name
Test status
Simulation time 127058098800 ps
CPU time 699.03 seconds
Started Mar 26 03:26:47 PM PDT 24
Finished Mar 26 03:38:26 PM PDT 24
Peak memory 223676 kb
Host smart-b7c96084-d058-4f6c-9728-4be412d535c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444497807 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3444497807
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1575495862
Short name T229
Test name
Test status
Simulation time 43758778 ps
CPU time 1.74 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 217864 kb
Host smart-c645b53c-7316-42f8-b904-aa58d18447be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575495862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1575495862
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3325178193
Short name T308
Test name
Test status
Simulation time 90560188 ps
CPU time 1.25 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 219416 kb
Host smart-3fc7cbab-d73c-47a6-bdaa-8164a6f65122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325178193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3325178193
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3280602268
Short name T717
Test name
Test status
Simulation time 74353305 ps
CPU time 2.79 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 219308 kb
Host smart-f3512af7-4b98-4d5e-8456-d17910712bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280602268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3280602268
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.31160987
Short name T475
Test name
Test status
Simulation time 64435487 ps
CPU time 1.15 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 218100 kb
Host smart-9f9bcb3f-efca-4b33-8cf8-e9cb501ef310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31160987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.31160987
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1699457548
Short name T519
Test name
Test status
Simulation time 29852515 ps
CPU time 1.26 seconds
Started Mar 26 03:27:41 PM PDT 24
Finished Mar 26 03:27:42 PM PDT 24
Peak memory 219072 kb
Host smart-40428633-4e39-46af-b516-001d03c18321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699457548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1699457548
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3970151447
Short name T560
Test name
Test status
Simulation time 457839385 ps
CPU time 4.14 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 216736 kb
Host smart-06238f89-1cd5-45d3-b031-efcb1677d1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970151447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3970151447
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2244360790
Short name T27
Test name
Test status
Simulation time 92820174 ps
CPU time 1.05 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 216460 kb
Host smart-81dd748b-4966-462e-86c7-7c0d2a8e760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244360790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2244360790
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2447552149
Short name T279
Test name
Test status
Simulation time 31467204 ps
CPU time 1.23 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 219480 kb
Host smart-26b38404-d14a-427d-8497-2e3ac402bf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447552149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2447552149
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1765040145
Short name T691
Test name
Test status
Simulation time 27565967 ps
CPU time 1.21 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 215528 kb
Host smart-e9315239-f942-4e10-945e-014006dd915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765040145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1765040145
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2070593543
Short name T688
Test name
Test status
Simulation time 30232675 ps
CPU time 0.94 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 206776 kb
Host smart-bf55fd60-d3cc-4fd0-a1bd-50164ed6d60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070593543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2070593543
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1211042292
Short name T140
Test name
Test status
Simulation time 15446316 ps
CPU time 0.91 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:36 PM PDT 24
Peak memory 215572 kb
Host smart-e8b61462-d56f-4457-943c-f30b342e3391
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211042292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1211042292
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4139875159
Short name T687
Test name
Test status
Simulation time 47573442 ps
CPU time 1.06 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 216316 kb
Host smart-918d2866-7284-4203-9c1a-660768c0ded7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139875159 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4139875159
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2560546460
Short name T585
Test name
Test status
Simulation time 55320862 ps
CPU time 1.12 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:26:40 PM PDT 24
Peak memory 232464 kb
Host smart-eaed9112-823e-41a6-b115-975f8b716732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560546460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2560546460
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.543178399
Short name T528
Test name
Test status
Simulation time 91145125 ps
CPU time 1.18 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 216728 kb
Host smart-6417be17-89ee-4d2d-adbd-4e9ff520558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543178399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.543178399
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1732733681
Short name T667
Test name
Test status
Simulation time 31949685 ps
CPU time 0.98 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 223808 kb
Host smart-e79d8c23-5786-42be-9d61-6a8e07a12fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732733681 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1732733681
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3336463841
Short name T439
Test name
Test status
Simulation time 23681118 ps
CPU time 0.98 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 215164 kb
Host smart-35d8fff0-e3a6-4d9e-b23d-11bebcc0eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336463841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3336463841
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.916257357
Short name T505
Test name
Test status
Simulation time 402654369 ps
CPU time 2.59 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:26:41 PM PDT 24
Peak memory 216548 kb
Host smart-4af42210-5b6a-4357-94c4-b4c632d09f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916257357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.916257357
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2202462264
Short name T627
Test name
Test status
Simulation time 127792316602 ps
CPU time 3346.97 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 04:22:19 PM PDT 24
Peak memory 235620 kb
Host smart-5550a778-6ee7-42cd-9c00-c411db524dc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202462264 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2202462264
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3537510402
Short name T618
Test name
Test status
Simulation time 46144506 ps
CPU time 1.55 seconds
Started Mar 26 03:27:53 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 219208 kb
Host smart-4df759f5-9169-42d1-9c5e-b6660c0b6a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537510402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3537510402
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.467751827
Short name T403
Test name
Test status
Simulation time 59594708 ps
CPU time 1.08 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 216876 kb
Host smart-7c364d9f-b809-46d8-bd60-670b7e38b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467751827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.467751827
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.41935827
Short name T537
Test name
Test status
Simulation time 83240082 ps
CPU time 1.35 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 217792 kb
Host smart-7f46ce19-1e27-4b7d-8291-7b6a235c4320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41935827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.41935827
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2017694906
Short name T360
Test name
Test status
Simulation time 71092796 ps
CPU time 1.22 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 216688 kb
Host smart-da727b08-4f78-4dc1-93e7-29c3409c4327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017694906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2017694906
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3866722411
Short name T636
Test name
Test status
Simulation time 66304594 ps
CPU time 1.2 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 216424 kb
Host smart-d7f6051b-73df-4bd1-a6ff-cd34489ed387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866722411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3866722411
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2617612994
Short name T294
Test name
Test status
Simulation time 33589297 ps
CPU time 1.06 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 216712 kb
Host smart-407c945b-30f5-4ba5-8481-bbe68976d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617612994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2617612994
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3219388503
Short name T603
Test name
Test status
Simulation time 55647254 ps
CPU time 1.33 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 218688 kb
Host smart-5d154a30-c9e8-4337-8f02-95a6c6f5e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219388503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3219388503
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2363149907
Short name T692
Test name
Test status
Simulation time 57944195 ps
CPU time 1.19 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 218464 kb
Host smart-58651d25-4030-4aba-9329-c19742fc8437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363149907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2363149907
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.513767568
Short name T808
Test name
Test status
Simulation time 57013830 ps
CPU time 1.14 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 217792 kb
Host smart-515bb55d-ca15-4764-827d-d24f445908ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513767568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.513767568
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1360490841
Short name T109
Test name
Test status
Simulation time 29493480 ps
CPU time 1.26 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215608 kb
Host smart-501e0fa1-4cbe-4d4c-81db-9b570979882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360490841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1360490841
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1342041754
Short name T745
Test name
Test status
Simulation time 190402581 ps
CPU time 0.92 seconds
Started Mar 26 03:26:33 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 205996 kb
Host smart-b0733e73-ffbd-4f90-888c-433ceade46fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342041754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1342041754
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_err.3074791267
Short name T458
Test name
Test status
Simulation time 22043075 ps
CPU time 0.91 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 217800 kb
Host smart-229babc2-ebb3-4b21-aa7e-999670658012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074791267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3074791267
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1393497107
Short name T742
Test name
Test status
Simulation time 40008250 ps
CPU time 1.61 seconds
Started Mar 26 03:26:41 PM PDT 24
Finished Mar 26 03:26:43 PM PDT 24
Peak memory 217780 kb
Host smart-5deb9591-0a50-4016-883f-0fe4b7ddffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393497107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1393497107
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1226802202
Short name T824
Test name
Test status
Simulation time 45894109 ps
CPU time 1.03 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 223872 kb
Host smart-89c9f945-faf9-4202-b652-7d86065985f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226802202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1226802202
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3026223252
Short name T755
Test name
Test status
Simulation time 48899909 ps
CPU time 0.87 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215288 kb
Host smart-42b97034-3d80-42e9-896e-5e1dedb53784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026223252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3026223252
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2821033457
Short name T452
Test name
Test status
Simulation time 295318468 ps
CPU time 3.3 seconds
Started Mar 26 03:26:45 PM PDT 24
Finished Mar 26 03:26:49 PM PDT 24
Peak memory 216356 kb
Host smart-f2a8541e-409f-4e26-91c1-62f4b67319ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821033457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2821033457
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.786983302
Short name T496
Test name
Test status
Simulation time 51099840863 ps
CPU time 1340.67 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:49:12 PM PDT 24
Peak memory 222552 kb
Host smart-3019c4d4-9de4-4c47-9ff4-b136e18fd674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786983302 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.786983302
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2329998237
Short name T634
Test name
Test status
Simulation time 200503165 ps
CPU time 0.99 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:48 PM PDT 24
Peak memory 216600 kb
Host smart-c6cd954c-f573-4523-871a-330d6bad0d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329998237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2329998237
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3213796654
Short name T561
Test name
Test status
Simulation time 95456967 ps
CPU time 1 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:46 PM PDT 24
Peak memory 216684 kb
Host smart-58d2fbda-107a-452b-b291-84abfdac130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213796654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3213796654
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.239039512
Short name T514
Test name
Test status
Simulation time 79872121 ps
CPU time 1.34 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 217900 kb
Host smart-ed237996-6660-4165-8dc8-667b90faad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239039512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.239039512
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2402800625
Short name T444
Test name
Test status
Simulation time 207469792 ps
CPU time 0.93 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 216548 kb
Host smart-556a3c57-20f8-4e69-b5d4-3f74c223e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402800625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2402800625
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2308531874
Short name T442
Test name
Test status
Simulation time 54714196 ps
CPU time 1.79 seconds
Started Mar 26 03:27:33 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 218100 kb
Host smart-f2faf006-9388-45cc-9c2b-8475eee6c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308531874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2308531874
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.832652649
Short name T550
Test name
Test status
Simulation time 156239322 ps
CPU time 2.53 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 219428 kb
Host smart-bc326770-7dfe-4e16-905b-cd2a656991e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832652649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.832652649
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.272523257
Short name T426
Test name
Test status
Simulation time 105100614 ps
CPU time 1.05 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 216576 kb
Host smart-f39a4718-1bdf-40fe-b396-64e47375e7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272523257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.272523257
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.574267563
Short name T716
Test name
Test status
Simulation time 76258256 ps
CPU time 1.55 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 218012 kb
Host smart-97246e86-937d-4a24-bece-ff4c52e1a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574267563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.574267563
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.471792870
Short name T335
Test name
Test status
Simulation time 28754316 ps
CPU time 1.14 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 218020 kb
Host smart-069cef9d-39c3-40fa-a16d-4dc36bc22928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471792870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.471792870
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.826829191
Short name T459
Test name
Test status
Simulation time 57857427 ps
CPU time 1.28 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 216612 kb
Host smart-cb600f35-d522-41cc-89b4-6f55989d9629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826829191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.826829191
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.2924296450
Short name T759
Test name
Test status
Simulation time 21735122 ps
CPU time 1.01 seconds
Started Mar 26 03:26:40 PM PDT 24
Finished Mar 26 03:26:41 PM PDT 24
Peak memory 206084 kb
Host smart-e4b57ce8-ee94-4bfd-b9a5-c238a1026427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924296450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2924296450
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3343966054
Short name T530
Test name
Test status
Simulation time 13113614 ps
CPU time 0.93 seconds
Started Mar 26 03:26:45 PM PDT 24
Finished Mar 26 03:26:46 PM PDT 24
Peak memory 215792 kb
Host smart-d35c1128-e8e7-4a4c-bee8-c21089a381d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343966054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3343966054
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.3578499081
Short name T332
Test name
Test status
Simulation time 22697638 ps
CPU time 0.92 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 217796 kb
Host smart-35697485-c374-42f2-b3e8-67d500d5bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578499081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3578499081
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.3247804097
Short name T126
Test name
Test status
Simulation time 27931363 ps
CPU time 0.88 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:43 PM PDT 24
Peak memory 215452 kb
Host smart-9d014f62-b336-4004-8ce4-57a6facd192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247804097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3247804097
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1472187747
Short name T317
Test name
Test status
Simulation time 30120711 ps
CPU time 0.92 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 215336 kb
Host smart-09ceec0a-7da2-473e-9be7-18fa72cbd7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472187747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1472187747
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.319307545
Short name T192
Test name
Test status
Simulation time 213137425 ps
CPU time 4.41 seconds
Started Mar 26 03:26:56 PM PDT 24
Finished Mar 26 03:27:01 PM PDT 24
Peak memory 217820 kb
Host smart-43723a07-dc55-475c-9dd0-114ee1df1631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319307545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.319307545
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.97155808
Short name T741
Test name
Test status
Simulation time 296207930428 ps
CPU time 1579.05 seconds
Started Mar 26 03:26:44 PM PDT 24
Finished Mar 26 03:53:03 PM PDT 24
Peak memory 224192 kb
Host smart-63ada9b3-d356-48ac-bd65-dc13eb12dbeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97155808 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.97155808
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2936880643
Short name T10
Test name
Test status
Simulation time 63554187 ps
CPU time 1.29 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 217060 kb
Host smart-2e80ce6a-6c49-40a7-ad1f-095632b42c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936880643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2936880643
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3191428138
Short name T408
Test name
Test status
Simulation time 458146024 ps
CPU time 2.19 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 218060 kb
Host smart-80dfd5bb-0875-46c9-9cc9-999d1b3fb9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191428138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3191428138
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2560445770
Short name T782
Test name
Test status
Simulation time 90714494 ps
CPU time 1.15 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 219348 kb
Host smart-d2342a2a-83a5-49db-8693-d894b2a5bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560445770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2560445770
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2976928045
Short name T482
Test name
Test status
Simulation time 50396020 ps
CPU time 1.52 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 217608 kb
Host smart-c7a958cf-ff9c-4a62-8909-78fcb3d1dcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976928045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2976928045
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1653685510
Short name T463
Test name
Test status
Simulation time 51445514 ps
CPU time 1.31 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 218012 kb
Host smart-7e96e39c-ca4a-41ab-8a6c-a337ecc0df3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653685510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1653685510
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3429629238
Short name T575
Test name
Test status
Simulation time 33215821 ps
CPU time 1.3 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 216764 kb
Host smart-3538314d-da5c-4fe2-9278-36dd44542c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429629238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3429629238
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.399173835
Short name T526
Test name
Test status
Simulation time 40517537 ps
CPU time 1.39 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 217860 kb
Host smart-e4f562a5-fd1c-44fc-aafb-5c93b6015bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399173835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.399173835
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2277738380
Short name T511
Test name
Test status
Simulation time 50886384 ps
CPU time 2.08 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 219480 kb
Host smart-7ede57c2-ff13-4a65-88f7-c330f43eca79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277738380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2277738380
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2587199653
Short name T347
Test name
Test status
Simulation time 56139810 ps
CPU time 1.41 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 217852 kb
Host smart-41fc3815-fd14-4fb2-a6f7-843cb848abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587199653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2587199653
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1378420037
Short name T468
Test name
Test status
Simulation time 121045445 ps
CPU time 1.06 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 216356 kb
Host smart-54b70d1a-62a9-4b07-82dd-68f39e2a72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378420037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1378420037
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2561539189
Short name T240
Test name
Test status
Simulation time 31185636 ps
CPU time 1.3 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 215608 kb
Host smart-841a9908-4371-4d9b-932c-156266a6a478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561539189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2561539189
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3963816172
Short name T604
Test name
Test status
Simulation time 36802735 ps
CPU time 0.83 seconds
Started Mar 26 03:26:51 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 206720 kb
Host smart-91db5d16-298a-4e0c-b138-baaab7d15165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963816172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3963816172
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3751999174
Short name T587
Test name
Test status
Simulation time 17953928 ps
CPU time 0.86 seconds
Started Mar 26 03:26:49 PM PDT 24
Finished Mar 26 03:26:50 PM PDT 24
Peak memory 215880 kb
Host smart-f7aa4e20-73ea-426e-b493-1887e7d054ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751999174 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3751999174
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.1809533896
Short name T739
Test name
Test status
Simulation time 19569151 ps
CPU time 1.14 seconds
Started Mar 26 03:26:44 PM PDT 24
Finished Mar 26 03:26:46 PM PDT 24
Peak memory 232584 kb
Host smart-92f3f671-97af-48bf-89cb-d23a52c3537b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809533896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1809533896
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2285030037
Short name T504
Test name
Test status
Simulation time 72853656 ps
CPU time 1.65 seconds
Started Mar 26 03:26:44 PM PDT 24
Finished Mar 26 03:26:45 PM PDT 24
Peak memory 217792 kb
Host smart-b3bd5a4c-68e8-4e33-bc14-cdcd26ef4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285030037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2285030037
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2410931227
Short name T434
Test name
Test status
Simulation time 34468277 ps
CPU time 0.89 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 215428 kb
Host smart-b3e938fd-5e32-403a-ab99-35ceaa6b8bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410931227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2410931227
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3282124291
Short name T344
Test name
Test status
Simulation time 62332362 ps
CPU time 0.89 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 215304 kb
Host smart-f4070536-8225-4216-a1a7-6a3293bd62cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282124291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3282124291
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4070097699
Short name T677
Test name
Test status
Simulation time 744508700 ps
CPU time 4.36 seconds
Started Mar 26 03:26:35 PM PDT 24
Finished Mar 26 03:26:39 PM PDT 24
Peak memory 216576 kb
Host smart-1d8a01cc-c90d-4056-aaf7-09cf066906ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070097699 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4070097699
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1860166069
Short name T728
Test name
Test status
Simulation time 152377661966 ps
CPU time 903.46 seconds
Started Mar 26 03:26:48 PM PDT 24
Finished Mar 26 03:41:52 PM PDT 24
Peak memory 222288 kb
Host smart-8fd9662a-d1e1-4edc-9924-fc6e8e026abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860166069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1860166069
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.758019154
Short name T818
Test name
Test status
Simulation time 46548066 ps
CPU time 1.39 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 216544 kb
Host smart-cc6a10a1-d691-4c37-962e-5dc44245c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758019154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.758019154
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2253354409
Short name T446
Test name
Test status
Simulation time 63538384 ps
CPU time 1.62 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 217824 kb
Host smart-d2771475-63d6-4c49-8e0e-f7febaa21be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253354409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2253354409
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1021243427
Short name T588
Test name
Test status
Simulation time 45253611 ps
CPU time 1.11 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 216832 kb
Host smart-e0fadf48-67f4-460f-965a-20c7edbe2b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021243427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1021243427
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1778941617
Short name T34
Test name
Test status
Simulation time 99878224 ps
CPU time 1.15 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 216732 kb
Host smart-78cc9792-7d0b-48a8-a092-0fcbab65d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778941617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1778941617
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3121216576
Short name T574
Test name
Test status
Simulation time 102248188 ps
CPU time 1.18 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 218648 kb
Host smart-7d0d7921-3041-4419-a3a6-5f1e9d13a2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121216576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3121216576
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1582611131
Short name T499
Test name
Test status
Simulation time 93337597 ps
CPU time 1.41 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 218668 kb
Host smart-d49357ad-8f03-471b-981f-8544092d199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582611131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1582611131
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3493091240
Short name T699
Test name
Test status
Simulation time 28754182 ps
CPU time 1.11 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 216700 kb
Host smart-7c1e8be3-c764-4faf-b336-e7b261afd884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493091240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3493091240
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3244098725
Short name T571
Test name
Test status
Simulation time 27829702 ps
CPU time 1.2 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 217924 kb
Host smart-0af5d92c-4b8d-49d5-b40f-0c69193a19d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244098725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3244098725
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3670875172
Short name T361
Test name
Test status
Simulation time 132489236 ps
CPU time 1.07 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 216384 kb
Host smart-a4ae6554-72c7-4350-aa3e-33d474ea51d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670875172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3670875172
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3175415533
Short name T488
Test name
Test status
Simulation time 49067579 ps
CPU time 1.21 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 216584 kb
Host smart-fa8fce74-147e-427d-bbbf-3e81c5a967b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175415533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3175415533
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1844929911
Short name T624
Test name
Test status
Simulation time 26943510 ps
CPU time 1.36 seconds
Started Mar 26 03:26:36 PM PDT 24
Finished Mar 26 03:26:48 PM PDT 24
Peak memory 215492 kb
Host smart-dd9a4e30-4eeb-4f8a-b4f4-2bfb1c75c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844929911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1844929911
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.573122352
Short name T40
Test name
Test status
Simulation time 23988915 ps
CPU time 0.83 seconds
Started Mar 26 03:26:52 PM PDT 24
Finished Mar 26 03:26:53 PM PDT 24
Peak memory 205756 kb
Host smart-c253247f-65d1-400e-b7b1-455a2739225c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573122352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.573122352
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1906149064
Short name T88
Test name
Test status
Simulation time 15349972 ps
CPU time 0.82 seconds
Started Mar 26 03:26:53 PM PDT 24
Finished Mar 26 03:26:54 PM PDT 24
Peak memory 215824 kb
Host smart-3e1e6738-006a-4437-98a1-1cae664ce8e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906149064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1906149064
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.764523118
Short name T684
Test name
Test status
Simulation time 30360143 ps
CPU time 1.17 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:26:39 PM PDT 24
Peak memory 217568 kb
Host smart-b7c0d449-da2f-444f-8888-970ffdbf91da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764523118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.764523118
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1690259577
Short name T82
Test name
Test status
Simulation time 89262142 ps
CPU time 1.16 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:43 PM PDT 24
Peak memory 224192 kb
Host smart-2255ba3a-ccc9-41ce-95e9-c1a82e7865ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690259577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1690259577
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1339303203
Short name T469
Test name
Test status
Simulation time 67828391 ps
CPU time 1.09 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 216532 kb
Host smart-f1ad640a-7faa-4716-ad92-b92147881f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339303203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1339303203
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.494450602
Short name T415
Test name
Test status
Simulation time 19466230 ps
CPU time 1 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 215260 kb
Host smart-eec101c2-43e5-4b9c-96d9-74c786d97f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494450602 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.494450602
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2236356311
Short name T193
Test name
Test status
Simulation time 187365311 ps
CPU time 2.2 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 216684 kb
Host smart-77bdfd50-0367-4b7d-a9f6-fb46b6f41b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236356311 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2236356311
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1684268055
Short name T180
Test name
Test status
Simulation time 116161143706 ps
CPU time 3181.21 seconds
Started Mar 26 03:26:52 PM PDT 24
Finished Mar 26 04:19:54 PM PDT 24
Peak memory 233936 kb
Host smart-86d5a4a8-d74d-4ce2-b712-50f16bd42f19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684268055 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1684268055
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1839012170
Short name T440
Test name
Test status
Simulation time 138390683 ps
CPU time 1.07 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 216716 kb
Host smart-12545a10-af92-46e6-96d2-9c2efa0ab9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839012170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1839012170
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3083721649
Short name T266
Test name
Test status
Simulation time 42675508 ps
CPU time 1.45 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 217620 kb
Host smart-764f3b6d-a044-4420-85d4-9542c345e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083721649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3083721649
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4149066442
Short name T568
Test name
Test status
Simulation time 103185424 ps
CPU time 1.19 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 216100 kb
Host smart-f1c6da26-ca2b-4b53-b99d-a09b4e9021e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149066442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4149066442
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2141628491
Short name T578
Test name
Test status
Simulation time 55398687 ps
CPU time 1.77 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 217800 kb
Host smart-05a659cc-08b3-4f66-9690-0a7b7faf2798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141628491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2141628491
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1654568718
Short name T433
Test name
Test status
Simulation time 79383138 ps
CPU time 1.31 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 216728 kb
Host smart-9043f7a5-f4bb-4929-86cf-40debe2f236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654568718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1654568718
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.413967295
Short name T447
Test name
Test status
Simulation time 86091751 ps
CPU time 1.11 seconds
Started Mar 26 03:27:55 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 216632 kb
Host smart-ac958fa0-ad57-4900-b354-65bbb4b86401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413967295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.413967295
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3138963674
Short name T797
Test name
Test status
Simulation time 78354125 ps
CPU time 1.17 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 216456 kb
Host smart-b4ead417-f0e3-4cc6-b469-38b96717e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138963674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3138963674
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1467378741
Short name T649
Test name
Test status
Simulation time 66645346 ps
CPU time 1.51 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 218100 kb
Host smart-0c8312a1-2e91-4de7-bd55-1dc3df7bd5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467378741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1467378741
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3096787199
Short name T698
Test name
Test status
Simulation time 65654348 ps
CPU time 1.2 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 216504 kb
Host smart-0c371897-af82-4578-b83f-a36a5dfa6439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096787199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3096787199
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2725968189
Short name T107
Test name
Test status
Simulation time 149389758 ps
CPU time 1.14 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 215600 kb
Host smart-09504063-0f44-46ce-87d1-a9804893b1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725968189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2725968189
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3122404804
Short name T774
Test name
Test status
Simulation time 46029043 ps
CPU time 0.88 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 205960 kb
Host smart-48536a8b-3069-475a-b38d-9636f212c72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122404804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3122404804
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3901474347
Short name T301
Test name
Test status
Simulation time 75659295 ps
CPU time 0.89 seconds
Started Mar 26 03:26:18 PM PDT 24
Finished Mar 26 03:26:19 PM PDT 24
Peak memory 215588 kb
Host smart-276a71e6-3e2d-4689-9064-99933106ce73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901474347 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3901474347
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.2946186528
Short name T410
Test name
Test status
Simulation time 56608879 ps
CPU time 1.02 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:21 PM PDT 24
Peak memory 218180 kb
Host smart-770fe6f2-dc4e-46f4-9756-0f69c23a326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946186528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2946186528
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3997110374
Short name T493
Test name
Test status
Simulation time 46632118 ps
CPU time 1.9 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:24 PM PDT 24
Peak memory 218840 kb
Host smart-e1c080d6-4a90-478f-8627-fcb77af150f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997110374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3997110374
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.935065339
Short name T19
Test name
Test status
Simulation time 200529492 ps
CPU time 3.73 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 236304 kb
Host smart-08de6215-3b1c-4403-aa35-b3072016f596
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935065339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.935065339
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.464523814
Short name T643
Test name
Test status
Simulation time 24949313 ps
CPU time 0.9 seconds
Started Mar 26 03:26:12 PM PDT 24
Finished Mar 26 03:26:13 PM PDT 24
Peak memory 215284 kb
Host smart-7e423fb4-da5b-4567-87f4-516862c3ebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464523814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.464523814
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2370829535
Short name T610
Test name
Test status
Simulation time 54546131 ps
CPU time 1.7 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 216476 kb
Host smart-8c2a4aa3-97ff-4176-b038-9e135964a439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370829535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2370829535
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2594365695
Short name T724
Test name
Test status
Simulation time 44918324043 ps
CPU time 1026.2 seconds
Started Mar 26 03:26:13 PM PDT 24
Finished Mar 26 03:43:19 PM PDT 24
Peak memory 217892 kb
Host smart-16c1024c-37f1-4634-8208-dc9f8bd17832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594365695 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2594365695
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4170386687
Short name T245
Test name
Test status
Simulation time 200017523 ps
CPU time 1.27 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215608 kb
Host smart-a40a8895-1ad2-4392-acd1-ff43865b1e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170386687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4170386687
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2054585618
Short name T311
Test name
Test status
Simulation time 63521540 ps
CPU time 0.94 seconds
Started Mar 26 03:26:59 PM PDT 24
Finished Mar 26 03:27:00 PM PDT 24
Peak memory 206820 kb
Host smart-2323ec65-db82-4fd8-b2d6-94fcac03dff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054585618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2054585618
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1293180868
Short name T173
Test name
Test status
Simulation time 110826927 ps
CPU time 0.88 seconds
Started Mar 26 03:26:52 PM PDT 24
Finished Mar 26 03:26:54 PM PDT 24
Peak memory 215928 kb
Host smart-9c1cf945-69ac-4d46-889d-d385d9ac3bd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293180868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1293180868
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.847306661
Short name T96
Test name
Test status
Simulation time 37931588 ps
CPU time 0.91 seconds
Started Mar 26 03:26:48 PM PDT 24
Finished Mar 26 03:26:49 PM PDT 24
Peak memory 217684 kb
Host smart-6509066b-466a-488f-a197-8958b7bfe6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847306661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.847306661
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1959518353
Short name T328
Test name
Test status
Simulation time 138904377 ps
CPU time 1.16 seconds
Started Mar 26 03:26:43 PM PDT 24
Finished Mar 26 03:26:44 PM PDT 24
Peak memory 216484 kb
Host smart-413ba56f-ce12-4a6b-8936-77dae0d4dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959518353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1959518353
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.3033748323
Short name T721
Test name
Test status
Simulation time 76426114 ps
CPU time 0.96 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 215300 kb
Host smart-8ffb3ccf-c3ff-485e-9362-2c7ddaaeae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033748323 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3033748323
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1634168134
Short name T142
Test name
Test status
Simulation time 156657103 ps
CPU time 2.13 seconds
Started Mar 26 03:26:37 PM PDT 24
Finished Mar 26 03:26:39 PM PDT 24
Peak memory 219436 kb
Host smart-69cf4772-5428-4789-b6bc-9d3e844a7220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634168134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1634168134
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1096140112
Short name T510
Test name
Test status
Simulation time 28723602970 ps
CPU time 765.56 seconds
Started Mar 26 03:26:43 PM PDT 24
Finished Mar 26 03:39:29 PM PDT 24
Peak memory 217736 kb
Host smart-0e8b1caf-8d14-477a-9a61-db0c6a457eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096140112 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1096140112
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1704890832
Short name T620
Test name
Test status
Simulation time 62701833 ps
CPU time 1.27 seconds
Started Mar 26 03:27:55 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 216732 kb
Host smart-1657d9a5-b4b9-4081-9130-fb7c24074643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704890832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1704890832
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3303848544
Short name T676
Test name
Test status
Simulation time 227129949 ps
CPU time 1.47 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 218068 kb
Host smart-cf0d1a33-8c07-4306-9677-8d3679e6330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303848544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3303848544
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.821638998
Short name T628
Test name
Test status
Simulation time 39254984 ps
CPU time 1.22 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 218072 kb
Host smart-be4f63f4-de27-4559-9cf8-4697256feb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821638998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.821638998
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4236448220
Short name T803
Test name
Test status
Simulation time 43105191 ps
CPU time 1.58 seconds
Started Mar 26 03:27:53 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 216712 kb
Host smart-c8cb4998-5a21-4396-8cab-f9d787f25cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236448220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4236448220
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1919782003
Short name T558
Test name
Test status
Simulation time 130577147 ps
CPU time 1.42 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 218104 kb
Host smart-5040ca1b-a6c8-4240-9c05-e683e5a539ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919782003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1919782003
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3947674540
Short name T785
Test name
Test status
Simulation time 97365980 ps
CPU time 1.11 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 215296 kb
Host smart-5f647166-aaf6-484c-b3c9-f665c69a8acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947674540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3947674540
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4045811626
Short name T38
Test name
Test status
Simulation time 210057790 ps
CPU time 1.44 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 218388 kb
Host smart-35a5c99b-5c43-45d0-819e-86c128f6273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045811626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4045811626
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1969802077
Short name T30
Test name
Test status
Simulation time 98798081 ps
CPU time 1.19 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 216716 kb
Host smart-872134f3-293a-42a0-96e9-f96b5d2a8eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969802077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1969802077
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2144388422
Short name T655
Test name
Test status
Simulation time 84242714 ps
CPU time 1.12 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 217972 kb
Host smart-6f2fc36e-f40f-405e-bacc-49ccaf60040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144388422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2144388422
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1019601941
Short name T278
Test name
Test status
Simulation time 28294724 ps
CPU time 0.99 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 216488 kb
Host smart-b9208fa4-0557-450e-b843-a3d430ef79af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019601941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1019601941
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.390639720
Short name T288
Test name
Test status
Simulation time 16491393 ps
CPU time 0.93 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 206532 kb
Host smart-9856ef51-7b41-4e8d-a2fe-9c3a61bf886c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390639720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.390639720
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1129708291
Short name T454
Test name
Test status
Simulation time 38854887 ps
CPU time 0.86 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 215384 kb
Host smart-b2fc34f6-3d75-452b-a4ff-88acd59c9c93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129708291 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1129708291
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1250747121
Short name T379
Test name
Test status
Simulation time 31323517 ps
CPU time 1.13 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 219188 kb
Host smart-ebc5a83a-dfac-4cff-a183-8ee272baee52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250747121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1250747121
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2767068248
Short name T86
Test name
Test status
Simulation time 22555379 ps
CPU time 1 seconds
Started Mar 26 03:26:59 PM PDT 24
Finished Mar 26 03:27:00 PM PDT 24
Peak memory 231236 kb
Host smart-e0e118e5-8ce2-4625-ade8-e1834024b3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767068248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2767068248
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.52761579
Short name T771
Test name
Test status
Simulation time 98714521 ps
CPU time 1.57 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:27:00 PM PDT 24
Peak memory 216996 kb
Host smart-855cae75-baab-46e7-90f3-2f33654e74fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52761579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.52761579
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.888378268
Short name T807
Test name
Test status
Simulation time 26101775 ps
CPU time 0.91 seconds
Started Mar 26 03:26:43 PM PDT 24
Finished Mar 26 03:26:44 PM PDT 24
Peak memory 215416 kb
Host smart-2e44e56c-6707-4dbd-83f3-e0bdd5144872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888378268 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.888378268
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2707272563
Short name T811
Test name
Test status
Simulation time 61372625 ps
CPU time 0.87 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 215256 kb
Host smart-eca60eb2-5d22-4555-a6aa-52600d834e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707272563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2707272563
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.68282592
Short name T477
Test name
Test status
Simulation time 324060677 ps
CPU time 2.69 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:53 PM PDT 24
Peak memory 218096 kb
Host smart-c84cc089-c7b7-47a9-94f0-800e97a93fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68282592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.68282592
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.348832493
Short name T637
Test name
Test status
Simulation time 30217084 ps
CPU time 1.21 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 216672 kb
Host smart-700252ef-7b5e-4b09-8f81-0bfa8c34e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348832493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.348832493
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3188870525
Short name T249
Test name
Test status
Simulation time 245958655 ps
CPU time 3.81 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 216840 kb
Host smart-8e7e6eb7-21c0-47cf-b3c0-2485090f5015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188870525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3188870525
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1394137114
Short name T265
Test name
Test status
Simulation time 166694498 ps
CPU time 1.04 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 216740 kb
Host smart-03b6df38-8c1f-4c1b-9a73-39f5d8a3d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394137114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1394137114
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1114263534
Short name T297
Test name
Test status
Simulation time 73713218 ps
CPU time 1.13 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 218148 kb
Host smart-550ce8c7-fba5-4965-9583-ba4c137ee83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114263534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1114263534
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1690895653
Short name T387
Test name
Test status
Simulation time 50901467 ps
CPU time 1.07 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 216708 kb
Host smart-b6c54200-5f8b-4963-82d6-8b753a589a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690895653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1690895653
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2909666349
Short name T398
Test name
Test status
Simulation time 116596755 ps
CPU time 1.07 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 217924 kb
Host smart-82c43ce5-f6c6-4115-8cd4-58dbd94a98b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909666349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2909666349
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2619677363
Short name T630
Test name
Test status
Simulation time 81701016 ps
CPU time 1.28 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 217916 kb
Host smart-b9d1ff2d-769d-4c86-a311-81f97129c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619677363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2619677363
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1593784919
Short name T706
Test name
Test status
Simulation time 227220743 ps
CPU time 2.67 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 219808 kb
Host smart-6d2a5435-cbb2-43f5-ba42-4c8e3e1963ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593784919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1593784919
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3106425836
Short name T591
Test name
Test status
Simulation time 91001392 ps
CPU time 1.26 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 216840 kb
Host smart-4186f887-4d39-439c-bb45-e6bbef32d1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106425836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3106425836
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.4076231807
Short name T806
Test name
Test status
Simulation time 22617951 ps
CPU time 1.15 seconds
Started Mar 26 03:26:33 PM PDT 24
Finished Mar 26 03:26:35 PM PDT 24
Peak memory 215656 kb
Host smart-0ea1b8c1-7180-474d-8944-d606d86e2360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076231807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4076231807
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2139739286
Short name T355
Test name
Test status
Simulation time 53050806 ps
CPU time 1.01 seconds
Started Mar 26 03:27:03 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 206432 kb
Host smart-bd60d22d-86f6-49eb-aba0-8536d417bf5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139739286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2139739286
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2553751233
Short name T696
Test name
Test status
Simulation time 18556742 ps
CPU time 0.84 seconds
Started Mar 26 03:26:46 PM PDT 24
Finished Mar 26 03:26:47 PM PDT 24
Peak memory 215488 kb
Host smart-89db3c39-aa83-4af9-9234-84f27680f663
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553751233 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2553751233
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.3891803030
Short name T778
Test name
Test status
Simulation time 23271454 ps
CPU time 1.06 seconds
Started Mar 26 03:27:01 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 231232 kb
Host smart-a821f2a8-8933-4e57-8160-eff27bf014cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891803030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3891803030
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.612187410
Short name T21
Test name
Test status
Simulation time 65924887 ps
CPU time 1.11 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:27:00 PM PDT 24
Peak memory 216756 kb
Host smart-6871b343-734d-442a-a830-d2a85f5efaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612187410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.612187410
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.650095043
Short name T757
Test name
Test status
Simulation time 22767302 ps
CPU time 1.02 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 215704 kb
Host smart-5b25ed38-1598-44fa-8fce-680a5c76fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650095043 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.650095043
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2561306651
Short name T765
Test name
Test status
Simulation time 71524897 ps
CPU time 0.93 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:43 PM PDT 24
Peak memory 215280 kb
Host smart-6e544eac-9759-4d43-a967-7495fd0fb786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561306651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2561306651
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3364497584
Short name T786
Test name
Test status
Simulation time 1017461284 ps
CPU time 5.23 seconds
Started Mar 26 03:26:44 PM PDT 24
Finished Mar 26 03:26:50 PM PDT 24
Peak memory 216568 kb
Host smart-daa4a6ec-80e5-42bd-ad21-7bc5eda24df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364497584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3364497584
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1798386027
Short name T188
Test name
Test status
Simulation time 972523567097 ps
CPU time 1950.83 seconds
Started Mar 26 03:26:34 PM PDT 24
Finished Mar 26 03:59:06 PM PDT 24
Peak memory 223496 kb
Host smart-a9a531a7-71f1-4102-b168-76266f8adabd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798386027 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1798386027
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/222.edn_genbits.574148671
Short name T770
Test name
Test status
Simulation time 31726523 ps
CPU time 1 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 216512 kb
Host smart-9cd7797f-a378-4c1a-8925-1f32cabb46e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574148671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.574148671
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1810876150
Short name T581
Test name
Test status
Simulation time 252612563 ps
CPU time 1.07 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 216712 kb
Host smart-a32a86f5-16b5-48e4-bab8-90cc2b3b9271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810876150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1810876150
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2300149511
Short name T709
Test name
Test status
Simulation time 31580826 ps
CPU time 1.23 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 218208 kb
Host smart-e4e84631-e897-406d-87d0-d5bfe0453434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300149511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2300149511
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3095066584
Short name T815
Test name
Test status
Simulation time 51365459 ps
CPU time 1.76 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 217788 kb
Host smart-5fc9ecaf-35bf-4751-b86f-d8411cb38bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095066584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3095066584
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3673312991
Short name T35
Test name
Test status
Simulation time 56777316 ps
CPU time 1.44 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 216880 kb
Host smart-596c23e8-10af-4b76-b6af-b5521fcb7abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673312991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3673312991
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1205158326
Short name T277
Test name
Test status
Simulation time 31377355 ps
CPU time 1.29 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 217684 kb
Host smart-ffc02b9e-b371-48f1-859e-a1a661876ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205158326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1205158326
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4018922433
Short name T592
Test name
Test status
Simulation time 86453890 ps
CPU time 1.01 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 216468 kb
Host smart-025e2a5a-f77b-48f5-9845-892c8ca71f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018922433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4018922433
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1556772371
Short name T494
Test name
Test status
Simulation time 37278313 ps
CPU time 1 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 215304 kb
Host smart-6b1dc128-54d8-49e8-98bb-b2ae03b58f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556772371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1556772371
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3913195373
Short name T94
Test name
Test status
Simulation time 69179852 ps
CPU time 1.1 seconds
Started Mar 26 03:26:53 PM PDT 24
Finished Mar 26 03:26:54 PM PDT 24
Peak memory 215572 kb
Host smart-6a6f683d-3a0b-4efd-9a4c-8d38a8dc947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913195373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3913195373
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1075771833
Short name T508
Test name
Test status
Simulation time 39023311 ps
CPU time 0.83 seconds
Started Mar 26 03:26:49 PM PDT 24
Finished Mar 26 03:26:50 PM PDT 24
Peak memory 205736 kb
Host smart-a518a469-e0ff-4873-95e1-4c64629ddb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075771833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1075771833
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1271350596
Short name T70
Test name
Test status
Simulation time 205236326 ps
CPU time 1.13 seconds
Started Mar 26 03:26:55 PM PDT 24
Finished Mar 26 03:26:57 PM PDT 24
Peak memory 217532 kb
Host smart-5bfbdbbd-87b8-49f0-90f9-e4e851f73390
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271350596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1271350596
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2966984679
Short name T331
Test name
Test status
Simulation time 20802775 ps
CPU time 1.1 seconds
Started Mar 26 03:26:56 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 219340 kb
Host smart-3d261846-2348-42a5-8885-4ee8867aa2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966984679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2966984679
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.452549230
Short name T565
Test name
Test status
Simulation time 52416829 ps
CPU time 1.55 seconds
Started Mar 26 03:26:35 PM PDT 24
Finished Mar 26 03:26:37 PM PDT 24
Peak memory 218008 kb
Host smart-4c7df638-e90e-4d8b-921b-796a60313117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452549230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.452549230
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1945638669
Short name T37
Test name
Test status
Simulation time 27038970 ps
CPU time 1.13 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215500 kb
Host smart-c5c70bb9-5216-41bc-beca-ce927b036fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945638669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1945638669
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2192359394
Short name T664
Test name
Test status
Simulation time 26934091 ps
CPU time 0.9 seconds
Started Mar 26 03:26:51 PM PDT 24
Finished Mar 26 03:26:53 PM PDT 24
Peak memory 215236 kb
Host smart-f5b7f855-240f-4668-92e8-682cef2d8c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192359394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2192359394
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3202386443
Short name T424
Test name
Test status
Simulation time 140277252 ps
CPU time 2.1 seconds
Started Mar 26 03:26:53 PM PDT 24
Finished Mar 26 03:26:56 PM PDT 24
Peak memory 215368 kb
Host smart-06590f41-6223-4857-b213-6ed0eda0e8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202386443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3202386443
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.578835595
Short name T189
Test name
Test status
Simulation time 4232355762 ps
CPU time 93.55 seconds
Started Mar 26 03:26:49 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 217684 kb
Host smart-088736ac-04d6-4768-880b-cc3fd45b1617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578835595 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.578835595
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.960835939
Short name T435
Test name
Test status
Simulation time 34359765 ps
CPU time 1.28 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 217716 kb
Host smart-fe417cd6-9fe6-4e12-a909-6b3462015275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960835939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.960835939
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3650395185
Short name T420
Test name
Test status
Simulation time 84613313 ps
CPU time 1.2 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 217856 kb
Host smart-c7f45577-5544-4d32-bebe-3d2ec11b9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650395185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3650395185
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2639860226
Short name T723
Test name
Test status
Simulation time 56887167 ps
CPU time 1.97 seconds
Started Mar 26 03:28:26 PM PDT 24
Finished Mar 26 03:28:28 PM PDT 24
Peak memory 217976 kb
Host smart-b91aaa44-8fd8-48d9-8349-fd322563fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639860226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2639860226
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.4237260592
Short name T748
Test name
Test status
Simulation time 96969496 ps
CPU time 2.31 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 218372 kb
Host smart-e873cea2-535e-440e-a2ca-1c5420e6b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237260592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.4237260592
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1674991729
Short name T175
Test name
Test status
Simulation time 267124409 ps
CPU time 3.67 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 215320 kb
Host smart-76205ea8-7ef7-4618-b3e3-81e6e075d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674991729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1674991729
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.721182792
Short name T451
Test name
Test status
Simulation time 87017984 ps
CPU time 1.06 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 216560 kb
Host smart-7663f2d3-3624-4f81-906b-8d7fd256e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721182792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.721182792
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2867749409
Short name T391
Test name
Test status
Simulation time 38632580 ps
CPU time 1.5 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 217864 kb
Host smart-969dced5-bbc9-492d-862c-c3d496fa1f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867749409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2867749409
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2104710906
Short name T734
Test name
Test status
Simulation time 4507322355 ps
CPU time 77.44 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 219836 kb
Host smart-4fe0522c-b679-4fab-a156-a3f49a86ce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104710906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2104710906
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.4170409286
Short name T461
Test name
Test status
Simulation time 75670715 ps
CPU time 1.39 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 216796 kb
Host smart-6dc5d024-bbb8-47d1-a855-31687f8b101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170409286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.4170409286
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3447331455
Short name T274
Test name
Test status
Simulation time 397659241 ps
CPU time 3.43 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 219064 kb
Host smart-9e0cb707-9ecb-4a33-a42a-dabfc2bbbc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447331455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3447331455
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4187082733
Short name T543
Test name
Test status
Simulation time 67778613 ps
CPU time 1.08 seconds
Started Mar 26 03:26:56 PM PDT 24
Finished Mar 26 03:26:57 PM PDT 24
Peak memory 215632 kb
Host smart-ad881aac-74bf-4bc0-93bf-522ad0d1547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187082733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4187082733
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4291607527
Short name T669
Test name
Test status
Simulation time 56870980 ps
CPU time 1 seconds
Started Mar 26 03:26:52 PM PDT 24
Finished Mar 26 03:26:54 PM PDT 24
Peak memory 206492 kb
Host smart-3154cbc3-51d7-492d-912c-09714f8cb88d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291607527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4291607527
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1439668429
Short name T151
Test name
Test status
Simulation time 13012783 ps
CPU time 0.91 seconds
Started Mar 26 03:26:48 PM PDT 24
Finished Mar 26 03:26:49 PM PDT 24
Peak memory 216012 kb
Host smart-48ba720d-8df4-4764-a2f1-0aea5b7a987b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439668429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1439668429
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.540649046
Short name T738
Test name
Test status
Simulation time 100734875 ps
CPU time 1.11 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 217816 kb
Host smart-6b746685-9f38-4862-8cb1-fa894ff7819c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540649046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.540649046
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2954051655
Short name T80
Test name
Test status
Simulation time 22073929 ps
CPU time 1.03 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 232812 kb
Host smart-7aab40d1-e365-465e-9837-c2771b641e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954051655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2954051655
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4243203495
Short name T821
Test name
Test status
Simulation time 48993867 ps
CPU time 1.15 seconds
Started Mar 26 03:26:55 PM PDT 24
Finished Mar 26 03:26:57 PM PDT 24
Peak memory 216460 kb
Host smart-fcd4a120-183b-4f52-9369-13478138fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243203495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4243203495
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3480724921
Short name T399
Test name
Test status
Simulation time 20668586 ps
CPU time 1.07 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215556 kb
Host smart-ec1e6f46-3467-445c-a762-b999a8802f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480724921 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3480724921
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1414892209
Short name T284
Test name
Test status
Simulation time 16763624 ps
CPU time 0.98 seconds
Started Mar 26 03:26:48 PM PDT 24
Finished Mar 26 03:26:49 PM PDT 24
Peak memory 215312 kb
Host smart-5fe8bcb5-5692-4202-b623-902e201247e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414892209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1414892209
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.476162663
Short name T141
Test name
Test status
Simulation time 359617473 ps
CPU time 7.12 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:49 PM PDT 24
Peak memory 215312 kb
Host smart-83cacbb7-c4d5-4a72-a66e-f67944acaa0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476162663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.476162663
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4019133259
Short name T642
Test name
Test status
Simulation time 23330998359 ps
CPU time 588.53 seconds
Started Mar 26 03:26:56 PM PDT 24
Finished Mar 26 03:36:44 PM PDT 24
Peak memory 220012 kb
Host smart-dd514941-f358-4de0-92f6-15a25f6b6458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019133259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4019133259
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3816926006
Short name T476
Test name
Test status
Simulation time 36882520 ps
CPU time 1.31 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 217732 kb
Host smart-8cd5b756-aad9-4e07-9133-64b424f52e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816926006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3816926006
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.770702293
Short name T534
Test name
Test status
Simulation time 52774975 ps
CPU time 1.38 seconds
Started Mar 26 03:27:55 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 218000 kb
Host smart-44ca76b7-1129-4f50-8db7-0f1b0b2a949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770702293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.770702293
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2496106794
Short name T726
Test name
Test status
Simulation time 39188397 ps
CPU time 1.05 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 216632 kb
Host smart-0c3ddd6a-b5ee-4232-979d-04c09f2cbae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496106794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2496106794
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3949416959
Short name T343
Test name
Test status
Simulation time 36215434 ps
CPU time 1.04 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 218952 kb
Host smart-666c0a5d-11ce-47dd-ae36-06b97469a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949416959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3949416959
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2222666983
Short name T473
Test name
Test status
Simulation time 39513975 ps
CPU time 1.4 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:10 PM PDT 24
Peak memory 217792 kb
Host smart-ba55af95-f361-411f-8a68-0319cd8adf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222666983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2222666983
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1794648783
Short name T573
Test name
Test status
Simulation time 42692427 ps
CPU time 1.49 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 217724 kb
Host smart-8e0289a6-d8a1-4331-a84d-86e0fe749253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794648783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1794648783
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.394338889
Short name T608
Test name
Test status
Simulation time 40025175 ps
CPU time 1.42 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 216436 kb
Host smart-061eccbb-c18d-4934-9eb5-ba90e186be5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394338889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.394338889
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2456558201
Short name T595
Test name
Test status
Simulation time 57029820 ps
CPU time 2 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 216732 kb
Host smart-d45949ba-85e1-47ee-84b2-856084af6bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456558201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2456558201
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.336809958
Short name T564
Test name
Test status
Simulation time 47979770 ps
CPU time 1.36 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 216464 kb
Host smart-8d1f5589-459d-4cc1-9dc5-55b506f92084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336809958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.336809958
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.828979608
Short name T323
Test name
Test status
Simulation time 72535993 ps
CPU time 0.97 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 216688 kb
Host smart-4726038f-4084-42f6-840e-e4cf5e439a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828979608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.828979608
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1569910228
Short name T95
Test name
Test status
Simulation time 59592332 ps
CPU time 1.14 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215620 kb
Host smart-eaf290ac-273d-4fac-9a90-a0a81d3a4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569910228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1569910228
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3318357562
Short name T382
Test name
Test status
Simulation time 22194616 ps
CPU time 0.97 seconds
Started Mar 26 03:26:49 PM PDT 24
Finished Mar 26 03:26:50 PM PDT 24
Peak memory 205996 kb
Host smart-eb6847a1-d068-4c27-a05c-06e8c8f170f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318357562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3318357562
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_err.3712736503
Short name T156
Test name
Test status
Simulation time 23486986 ps
CPU time 0.85 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 217992 kb
Host smart-a93d8ce0-16cd-4ba6-868f-ec98779be922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712736503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3712736503
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.940949963
Short name T645
Test name
Test status
Simulation time 119410357 ps
CPU time 1.3 seconds
Started Mar 26 03:26:42 PM PDT 24
Finished Mar 26 03:26:43 PM PDT 24
Peak memory 216704 kb
Host smart-bad6c9a9-656e-4325-ba66-009261c0a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940949963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.940949963
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.626135070
Short name T554
Test name
Test status
Simulation time 22490104 ps
CPU time 1.08 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 215428 kb
Host smart-7b68c34c-846b-4d71-84bc-c170421a4d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626135070 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.626135070
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4293611569
Short name T732
Test name
Test status
Simulation time 24040361 ps
CPU time 0.96 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:27:05 PM PDT 24
Peak memory 215292 kb
Host smart-a169931b-3b30-40a3-8707-48eff666cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293611569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4293611569
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1088650395
Short name T777
Test name
Test status
Simulation time 106331347 ps
CPU time 2.47 seconds
Started Mar 26 03:26:53 PM PDT 24
Finished Mar 26 03:26:56 PM PDT 24
Peak memory 216476 kb
Host smart-3fca44ab-7a0e-4c6e-a943-113b33726c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088650395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1088650395
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4052085553
Short name T773
Test name
Test status
Simulation time 127582463208 ps
CPU time 293.83 seconds
Started Mar 26 03:26:55 PM PDT 24
Finished Mar 26 03:31:50 PM PDT 24
Peak memory 218292 kb
Host smart-3026f694-f41c-4f30-9c7c-64288db4bd72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052085553 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4052085553
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2813496859
Short name T32
Test name
Test status
Simulation time 58935987 ps
CPU time 1.08 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 216492 kb
Host smart-6d08ef73-67c8-4abf-86e0-ca8c31aa927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813496859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2813496859
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2571093687
Short name T563
Test name
Test status
Simulation time 46852994 ps
CPU time 1.15 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 216376 kb
Host smart-7185e0f9-b76e-4cf9-88b1-32338a624fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571093687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2571093687
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1353075202
Short name T254
Test name
Test status
Simulation time 60796902 ps
CPU time 0.98 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 216508 kb
Host smart-0e3f41d4-c286-4bda-8da0-b4968bf8678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353075202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1353075202
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.478303203
Short name T472
Test name
Test status
Simulation time 35738651 ps
CPU time 1.27 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 219352 kb
Host smart-7778ace7-03c0-41b8-bc75-04908385b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478303203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.478303203
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.338407363
Short name T333
Test name
Test status
Simulation time 39471041 ps
CPU time 1.33 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 217768 kb
Host smart-4b4d17e0-6ca1-432e-90f4-a87863cd98ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338407363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.338407363
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2045874986
Short name T615
Test name
Test status
Simulation time 46633847 ps
CPU time 1.89 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 219412 kb
Host smart-39e4306f-73d2-40bb-8394-db6b7d5b7e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045874986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2045874986
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.240077106
Short name T271
Test name
Test status
Simulation time 72550294 ps
CPU time 1.04 seconds
Started Mar 26 03:28:01 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 216636 kb
Host smart-8f8526d7-b393-4f47-b43e-e18df0452909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240077106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.240077106
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3162595906
Short name T820
Test name
Test status
Simulation time 95619312 ps
CPU time 1.47 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 217664 kb
Host smart-b97c6fd0-79f9-40dd-819a-c0bdb11f0a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162595906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3162595906
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1216621691
Short name T480
Test name
Test status
Simulation time 33477470 ps
CPU time 1.09 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 218936 kb
Host smart-06fa2eeb-7696-4eb4-89e9-871cdd9c656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216621691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1216621691
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1815990191
Short name T753
Test name
Test status
Simulation time 31508552 ps
CPU time 1.17 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215600 kb
Host smart-17b3e69e-c52c-4167-afd8-00f3f0563d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815990191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1815990191
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.639955124
Short name T525
Test name
Test status
Simulation time 51156053 ps
CPU time 0.9 seconds
Started Mar 26 03:26:51 PM PDT 24
Finished Mar 26 03:26:52 PM PDT 24
Peak memory 205708 kb
Host smart-696878da-3164-439f-8fe3-d8c732c97f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639955124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.639955124
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4122850077
Short name T429
Test name
Test status
Simulation time 107982284 ps
CPU time 1.14 seconds
Started Mar 26 03:26:51 PM PDT 24
Finished Mar 26 03:26:53 PM PDT 24
Peak memory 217436 kb
Host smart-f3ac896c-3a74-48ec-8342-3ed0ec849427
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122850077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4122850077
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2966579257
Short name T789
Test name
Test status
Simulation time 43275437 ps
CPU time 0.82 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 217672 kb
Host smart-c1a265f0-8a64-4ac4-8fce-0d1e56f6f526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966579257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2966579257
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2304293643
Short name T747
Test name
Test status
Simulation time 90028140 ps
CPU time 1.27 seconds
Started Mar 26 03:26:53 PM PDT 24
Finished Mar 26 03:26:55 PM PDT 24
Peak memory 218672 kb
Host smart-edbde69c-006c-453c-996f-ce4c4b1238fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304293643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2304293643
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3960929316
Short name T668
Test name
Test status
Simulation time 21606684 ps
CPU time 1.04 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 215512 kb
Host smart-9ef6c685-e78d-4d72-8770-38c5e15164a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960929316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3960929316
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3655811619
Short name T704
Test name
Test status
Simulation time 14453130 ps
CPU time 1.03 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 215292 kb
Host smart-8375307e-bebd-4d78-85df-421d83beb789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655811619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3655811619
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.511993379
Short name T195
Test name
Test status
Simulation time 122780784 ps
CPU time 1.24 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 205796 kb
Host smart-53af58b9-21a1-49be-9640-97eec4cddfc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511993379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.511993379
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2556900417
Short name T397
Test name
Test status
Simulation time 453185412463 ps
CPU time 1431.99 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:50:56 PM PDT 24
Peak memory 234904 kb
Host smart-bca3ecfb-02a9-4403-8567-e0ab26f11c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556900417 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2556900417
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.962468939
Short name T453
Test name
Test status
Simulation time 164136530 ps
CPU time 0.94 seconds
Started Mar 26 03:28:15 PM PDT 24
Finished Mar 26 03:28:16 PM PDT 24
Peak memory 216652 kb
Host smart-57222685-2a82-481c-a7d0-931173600713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962468939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.962468939
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.80713920
Short name T250
Test name
Test status
Simulation time 55643108 ps
CPU time 1.02 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:04 PM PDT 24
Peak memory 216480 kb
Host smart-a42a6567-e832-44e9-94a6-6a89815c5787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80713920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.80713920
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.116845190
Short name T651
Test name
Test status
Simulation time 148427361 ps
CPU time 1.21 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 218860 kb
Host smart-49f6a588-2e7b-4c9a-82ad-b57199b6ed28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116845190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.116845190
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2480413641
Short name T485
Test name
Test status
Simulation time 69722966 ps
CPU time 1.67 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 217952 kb
Host smart-2baae5e8-1bb4-455c-9189-d35b8ecbf880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480413641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2480413641
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1927967236
Short name T457
Test name
Test status
Simulation time 67827630 ps
CPU time 1.4 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 216636 kb
Host smart-d49dce26-1350-4ffb-9bce-209b13e376a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927967236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1927967236
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.354932115
Short name T371
Test name
Test status
Simulation time 52257502 ps
CPU time 1.43 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:02 PM PDT 24
Peak memory 217824 kb
Host smart-5972f424-f8d0-4f30-a75c-da9ef57ba009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354932115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.354932115
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1468651988
Short name T775
Test name
Test status
Simulation time 82993502 ps
CPU time 1.58 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 217808 kb
Host smart-f3a6e1a7-bb75-49e8-9a4a-4e34a276eb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468651988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1468651988
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3707452946
Short name T368
Test name
Test status
Simulation time 48581812 ps
CPU time 1.26 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:05 PM PDT 24
Peak memory 218076 kb
Host smart-ddc1cd32-f5b9-4ed2-9437-3bc1f55a2c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707452946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3707452946
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1269253178
Short name T697
Test name
Test status
Simulation time 29083318 ps
CPU time 1.26 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 216788 kb
Host smart-cef674cc-c807-4534-bb14-ae70c82b8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269253178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1269253178
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.323257115
Short name T729
Test name
Test status
Simulation time 247102440 ps
CPU time 1.35 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:27:05 PM PDT 24
Peak memory 215604 kb
Host smart-f471bd04-af0a-4b29-abc1-cb5b1efc2771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323257115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.323257115
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3916486584
Short name T39
Test name
Test status
Simulation time 21324842 ps
CPU time 0.99 seconds
Started Mar 26 03:27:01 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 206428 kb
Host smart-89fd72ba-5626-49fc-9d4a-ed8ee9af766f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916486584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3916486584
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2773089508
Short name T302
Test name
Test status
Simulation time 228623614 ps
CPU time 1.2 seconds
Started Mar 26 03:26:52 PM PDT 24
Finished Mar 26 03:26:53 PM PDT 24
Peak memory 218780 kb
Host smart-a27be8e4-6e06-4e27-836b-06721e07bf76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773089508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2773089508
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4105929638
Short name T81
Test name
Test status
Simulation time 34246723 ps
CPU time 0.89 seconds
Started Mar 26 03:27:03 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 217860 kb
Host smart-9e336911-b452-4906-b139-c96b453a03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105929638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4105929638
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2438065004
Short name T407
Test name
Test status
Simulation time 70176639 ps
CPU time 1.72 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 218764 kb
Host smart-55a8764b-8c1a-4dcd-805d-91bf51936424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438065004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2438065004
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.192143398
Short name T45
Test name
Test status
Simulation time 35964896 ps
CPU time 0.94 seconds
Started Mar 26 03:26:52 PM PDT 24
Finished Mar 26 03:26:54 PM PDT 24
Peak memory 223872 kb
Host smart-b487629c-ca7d-4596-b6e9-f09397e22f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192143398 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.192143398
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2103794464
Short name T813
Test name
Test status
Simulation time 106070986 ps
CPU time 0.9 seconds
Started Mar 26 03:26:50 PM PDT 24
Finished Mar 26 03:26:51 PM PDT 24
Peak memory 215276 kb
Host smart-5e9e322c-a3e8-43fa-b730-e27a7972772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103794464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2103794464
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3069796001
Short name T711
Test name
Test status
Simulation time 553306599 ps
CPU time 5.3 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 215272 kb
Host smart-81e781bb-25da-4fdf-a49b-8aa2e7b74dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069796001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3069796001
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3452425834
Short name T181
Test name
Test status
Simulation time 14320048236 ps
CPU time 362.17 seconds
Started Mar 26 03:27:03 PM PDT 24
Finished Mar 26 03:33:05 PM PDT 24
Peak memory 217424 kb
Host smart-5bbcc5d0-f051-4c61-a4e0-eaedc86a7311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452425834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3452425834
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.514730158
Short name T702
Test name
Test status
Simulation time 39128391 ps
CPU time 1.43 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:10 PM PDT 24
Peak memory 218548 kb
Host smart-91853fc8-3987-4b7e-a2b8-44da8e00acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514730158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.514730158
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4098180780
Short name T251
Test name
Test status
Simulation time 46809258 ps
CPU time 1.8 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 217780 kb
Host smart-b33a17d4-ee19-4a34-8ece-96319804a53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098180780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4098180780
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2347349179
Short name T352
Test name
Test status
Simulation time 80940116 ps
CPU time 1.34 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 217980 kb
Host smart-1e59c6ca-bd9f-427c-8228-76018c6af4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347349179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2347349179
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1275593576
Short name T736
Test name
Test status
Simulation time 56351762 ps
CPU time 1.88 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:18 PM PDT 24
Peak memory 217852 kb
Host smart-bc620180-a8f1-4810-8e82-4ca95d963354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275593576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1275593576
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.646103731
Short name T570
Test name
Test status
Simulation time 61376332 ps
CPU time 1.33 seconds
Started Mar 26 03:28:24 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 216648 kb
Host smart-a7a35f5c-3bef-4230-84b9-009468a7474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646103731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.646103731
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1010538067
Short name T527
Test name
Test status
Simulation time 113958449 ps
CPU time 2.36 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 218496 kb
Host smart-dbe814e1-5ffa-43e7-8fa2-abc734371bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010538067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1010538067
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3655810160
Short name T136
Test name
Test status
Simulation time 36257658 ps
CPU time 1.31 seconds
Started Mar 26 03:28:02 PM PDT 24
Finished Mar 26 03:28:03 PM PDT 24
Peak memory 216468 kb
Host smart-3bea9e81-1533-4ca0-b9e8-fa42396dc977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655810160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3655810160
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1644716174
Short name T200
Test name
Test status
Simulation time 24295184 ps
CPU time 1.16 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 216816 kb
Host smart-4aab2e2c-e985-4702-b77c-b02d332709ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644716174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1644716174
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2168376016
Short name T827
Test name
Test status
Simulation time 38916309 ps
CPU time 1.54 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 217684 kb
Host smart-b3c57a7e-d1cc-47e0-8c1b-2cea96044bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168376016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2168376016
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1070167681
Short name T392
Test name
Test status
Simulation time 44390747 ps
CPU time 1.03 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 216468 kb
Host smart-8dd5e255-9db8-4ebe-9011-df562e634f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070167681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1070167681
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2376350577
Short name T93
Test name
Test status
Simulation time 82257953 ps
CPU time 1.13 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 215620 kb
Host smart-c2675d19-ac3d-479b-bb11-8d6487990a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376350577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2376350577
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3180925586
Short name T816
Test name
Test status
Simulation time 46120202 ps
CPU time 0.83 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 205740 kb
Host smart-64fc6760-d350-49f0-88fb-e581b372f15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180925586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3180925586
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_err.103879046
Short name T705
Test name
Test status
Simulation time 40732957 ps
CPU time 0.91 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 231060 kb
Host smart-7a59d0d4-a847-4803-8ba7-40018c9cca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103879046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.103879046
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3786494408
Short name T430
Test name
Test status
Simulation time 48598208 ps
CPU time 1.13 seconds
Started Mar 26 03:26:44 PM PDT 24
Finished Mar 26 03:26:45 PM PDT 24
Peak memory 217512 kb
Host smart-bb366c1f-98f1-42e1-a0b3-a166cbc8ea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786494408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3786494408
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4181393211
Short name T762
Test name
Test status
Simulation time 21004033 ps
CPU time 1.05 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 215636 kb
Host smart-0772ff51-4a48-4008-8000-7fefb7fad6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181393211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4181393211
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2380195897
Short name T735
Test name
Test status
Simulation time 38262890 ps
CPU time 0.89 seconds
Started Mar 26 03:26:55 PM PDT 24
Finished Mar 26 03:26:56 PM PDT 24
Peak memory 215180 kb
Host smart-0428378b-94ba-4663-bd5d-df1b7295d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380195897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2380195897
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3411431926
Short name T541
Test name
Test status
Simulation time 22818418 ps
CPU time 1.07 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215164 kb
Host smart-327fdf28-92bf-418f-ab0e-f38a4f23d438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411431926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3411431926
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2870453945
Short name T182
Test name
Test status
Simulation time 148248455076 ps
CPU time 357.81 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:33:04 PM PDT 24
Peak memory 218560 kb
Host smart-7c02c0f6-a7e6-462b-a816-fcc27b0101d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870453945 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2870453945
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.4045954895
Short name T516
Test name
Test status
Simulation time 36659670 ps
CPU time 1.07 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 216916 kb
Host smart-f8519372-7d31-45e7-8c87-4d1a98e2e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045954895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4045954895
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.556959427
Short name T283
Test name
Test status
Simulation time 19013031 ps
CPU time 1.09 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 216416 kb
Host smart-b43d3de8-387d-4fda-9cb4-98394694d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556959427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.556959427
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2336372813
Short name T138
Test name
Test status
Simulation time 89601112 ps
CPU time 1.24 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 216660 kb
Host smart-fc0d8973-59b0-4718-a9b6-c1e3e1176ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336372813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2336372813
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.8828573
Short name T520
Test name
Test status
Simulation time 80966938 ps
CPU time 1.56 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 219276 kb
Host smart-b29f076f-b490-42a5-8515-b478c4b168f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8828573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.8828573
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1188788551
Short name T832
Test name
Test status
Simulation time 75836801 ps
CPU time 1.44 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 215352 kb
Host smart-a22fe427-e930-4357-82e3-99f5f10c94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188788551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1188788551
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2946402223
Short name T596
Test name
Test status
Simulation time 243028077 ps
CPU time 3.02 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:10 PM PDT 24
Peak memory 218928 kb
Host smart-5ae5a9ba-763a-43a8-998e-dbc932df7830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946402223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2946402223
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.474041961
Short name T168
Test name
Test status
Simulation time 35910451 ps
CPU time 1.38 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:06 PM PDT 24
Peak memory 217708 kb
Host smart-ac713a0a-5da0-4eb6-9df6-06c8cfbe8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474041961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.474041961
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.614500988
Short name T386
Test name
Test status
Simulation time 78464289 ps
CPU time 1.14 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 216248 kb
Host smart-ac71d277-e3f6-4144-a50e-a0e577f12b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614500988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.614500988
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.238158726
Short name T20
Test name
Test status
Simulation time 101537984 ps
CPU time 1.39 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 218492 kb
Host smart-556d0d5b-f251-459d-ad79-2bdf3ef21bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238158726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.238158726
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1779074508
Short name T264
Test name
Test status
Simulation time 138227664 ps
CPU time 2.98 seconds
Started Mar 26 03:28:27 PM PDT 24
Finished Mar 26 03:28:31 PM PDT 24
Peak memory 216920 kb
Host smart-3566d185-8caa-434e-8ab1-cd97432916f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779074508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1779074508
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1984029573
Short name T754
Test name
Test status
Simulation time 73022675 ps
CPU time 1.13 seconds
Started Mar 26 03:27:02 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 215588 kb
Host smart-af62e4b9-ff95-4b0b-bb36-903feabd6aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984029573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1984029573
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1439925635
Short name T492
Test name
Test status
Simulation time 13172489 ps
CPU time 0.89 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 205832 kb
Host smart-515ea2aa-47c6-4507-98f4-007bdc756815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439925635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1439925635
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3185631288
Short name T509
Test name
Test status
Simulation time 19617326 ps
CPU time 0.88 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215384 kb
Host smart-c1444670-d1bf-4df6-93b7-6254ffcfc096
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185631288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3185631288
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.502667715
Short name T384
Test name
Test status
Simulation time 52080279 ps
CPU time 1.11 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 216588 kb
Host smart-63f1428e-6fd5-4daa-be90-55e695472910
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502667715 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.502667715
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.4185747799
Short name T158
Test name
Test status
Simulation time 28320916 ps
CPU time 0.92 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 218048 kb
Host smart-43283d4b-a346-4a8f-ae17-d582911e89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185747799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.4185747799
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3812758092
Short name T252
Test name
Test status
Simulation time 76926178 ps
CPU time 1.14 seconds
Started Mar 26 03:26:54 PM PDT 24
Finished Mar 26 03:26:55 PM PDT 24
Peak memory 216540 kb
Host smart-5f2662e0-b916-4372-994b-3bcb3af3cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812758092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3812758092
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4148089223
Short name T539
Test name
Test status
Simulation time 58364362 ps
CPU time 0.9 seconds
Started Mar 26 03:27:08 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 215268 kb
Host smart-5a501cb9-ff60-4efa-9ce2-28d1176e7fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148089223 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4148089223
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1808038640
Short name T290
Test name
Test status
Simulation time 16503430 ps
CPU time 0.93 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215276 kb
Host smart-4d9ba435-6149-4c47-bec9-92b22b84c9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808038640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1808038640
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1849636814
Short name T1
Test name
Test status
Simulation time 573549503 ps
CPU time 2.72 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 215168 kb
Host smart-a59852b2-1fd4-4c93-a900-ce5589bd9320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849636814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1849636814
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3047433227
Short name T489
Test name
Test status
Simulation time 23654135589 ps
CPU time 308.59 seconds
Started Mar 26 03:27:01 PM PDT 24
Finished Mar 26 03:32:10 PM PDT 24
Peak memory 219584 kb
Host smart-ad288bef-89f1-4f04-81d5-5f99cc8cfb2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047433227 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3047433227
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3157067719
Short name T833
Test name
Test status
Simulation time 32877680 ps
CPU time 1.02 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 216692 kb
Host smart-f8643d87-91e5-4677-899f-88173e812d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157067719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3157067719
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1187618965
Short name T613
Test name
Test status
Simulation time 32311780 ps
CPU time 1.29 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 216636 kb
Host smart-c77f0f5e-c933-4111-bd29-189364eababa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187618965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1187618965
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2379441759
Short name T314
Test name
Test status
Simulation time 45149386 ps
CPU time 1.5 seconds
Started Mar 26 03:28:11 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 217632 kb
Host smart-49a4d4be-27e3-48eb-a8a1-c48b6e77fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379441759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2379441759
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2372912285
Short name T383
Test name
Test status
Simulation time 26376035 ps
CPU time 1.16 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:10 PM PDT 24
Peak memory 216596 kb
Host smart-a9300654-ee11-4039-a463-7525d33ae54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372912285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2372912285
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4198623583
Short name T8
Test name
Test status
Simulation time 139634881 ps
CPU time 1.47 seconds
Started Mar 26 03:28:14 PM PDT 24
Finished Mar 26 03:28:16 PM PDT 24
Peak memory 219120 kb
Host smart-5bcb720a-06c9-442a-9803-5371460bd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198623583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4198623583
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2091714376
Short name T831
Test name
Test status
Simulation time 82605458 ps
CPU time 1.21 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 215324 kb
Host smart-7516e80a-0948-484e-a095-3aeb2028cd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091714376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2091714376
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2757749733
Short name T710
Test name
Test status
Simulation time 341973362 ps
CPU time 3.18 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 218632 kb
Host smart-e031c72b-ae5a-4db6-8db7-7db3d710eeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757749733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2757749733
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2535040440
Short name T363
Test name
Test status
Simulation time 122277219 ps
CPU time 1.28 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:08 PM PDT 24
Peak memory 216512 kb
Host smart-5c2dddc8-48d1-4626-9ddf-72d53645dc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535040440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2535040440
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2215297901
Short name T300
Test name
Test status
Simulation time 198795408 ps
CPU time 1.02 seconds
Started Mar 26 03:28:14 PM PDT 24
Finished Mar 26 03:28:15 PM PDT 24
Peak memory 216612 kb
Host smart-e0064fc0-127a-41dc-971d-68050bd0ea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215297901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2215297901
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1384086114
Short name T135
Test name
Test status
Simulation time 76544865 ps
CPU time 1.42 seconds
Started Mar 26 03:28:11 PM PDT 24
Finished Mar 26 03:28:13 PM PDT 24
Peak memory 218180 kb
Host smart-37857eec-9ae8-44d0-813a-9a64449bee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384086114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1384086114
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3703682720
Short name T600
Test name
Test status
Simulation time 90634428 ps
CPU time 1.18 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 215568 kb
Host smart-ea93b6c1-fd12-418f-9ebb-cd3ae7156339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703682720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3703682720
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2396678941
Short name T598
Test name
Test status
Simulation time 16165374 ps
CPU time 0.91 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 206764 kb
Host smart-c0ae882e-83f1-4a77-bd1c-737d121113f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396678941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2396678941
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4265267024
Short name T593
Test name
Test status
Simulation time 49074788 ps
CPU time 0.84 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:21 PM PDT 24
Peak memory 215640 kb
Host smart-41d419f8-64a7-4b73-a1e0-2b2004c0af19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265267024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4265267024
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.2577250546
Short name T68
Test name
Test status
Simulation time 48171897 ps
CPU time 0.94 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 219196 kb
Host smart-d638f92d-4348-4abe-8c83-eec9d6a6d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577250546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2577250546
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2208703396
Short name T798
Test name
Test status
Simulation time 266238022 ps
CPU time 1.27 seconds
Started Mar 26 03:26:23 PM PDT 24
Finished Mar 26 03:26:25 PM PDT 24
Peak memory 216736 kb
Host smart-5b1b22ed-143e-41d1-8f44-0580a80f9fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208703396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2208703396
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1457698188
Short name T682
Test name
Test status
Simulation time 35441419 ps
CPU time 0.88 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215532 kb
Host smart-fedb5464-a740-4fcf-8676-5dcbe6812ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457698188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1457698188
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1371036505
Short name T246
Test name
Test status
Simulation time 63186430 ps
CPU time 0.91 seconds
Started Mar 26 03:26:24 PM PDT 24
Finished Mar 26 03:26:25 PM PDT 24
Peak memory 207084 kb
Host smart-1ce5254c-85ec-48ae-a17b-f631ab774b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371036505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1371036505
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1707517594
Short name T425
Test name
Test status
Simulation time 19464509 ps
CPU time 1 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 207060 kb
Host smart-6ec54e07-99b2-4190-95e6-9201b0910fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707517594 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1707517594
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.914954112
Short name T661
Test name
Test status
Simulation time 402319315 ps
CPU time 2.62 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 216648 kb
Host smart-7fcc31db-f4a0-4dd9-a365-01af2899554c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914954112 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.914954112
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3759441301
Short name T694
Test name
Test status
Simulation time 28968301839 ps
CPU time 393.82 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:32:56 PM PDT 24
Peak memory 217752 kb
Host smart-2c9e0cf2-0be3-4788-9020-9b16ea312ed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759441301 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3759441301
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.4030263793
Short name T15
Test name
Test status
Simulation time 49514711 ps
CPU time 1.21 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 215580 kb
Host smart-41e68347-3147-4838-a80e-b2d67ff02cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030263793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4030263793
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2241619942
Short name T495
Test name
Test status
Simulation time 16448652 ps
CPU time 0.98 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:27:00 PM PDT 24
Peak memory 206544 kb
Host smart-bf74eeb5-1bc2-4a84-a218-9c950b32c8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241619942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2241619942
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4040779139
Short name T150
Test name
Test status
Simulation time 22429133 ps
CPU time 0.91 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215916 kb
Host smart-470522f7-b714-4095-a679-4324b324b118
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040779139 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4040779139
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.3274808638
Short name T292
Test name
Test status
Simulation time 19745917 ps
CPU time 1.07 seconds
Started Mar 26 03:26:55 PM PDT 24
Finished Mar 26 03:26:57 PM PDT 24
Peak memory 217584 kb
Host smart-2e88d30f-910c-46d5-bde0-f8dbcb83f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274808638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3274808638
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.402716090
Short name T116
Test name
Test status
Simulation time 121072453 ps
CPU time 1.25 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 219500 kb
Host smart-5dd07d44-2e9f-48a4-8948-7bd4d86fd2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402716090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.402716090
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2833115070
Short name T503
Test name
Test status
Simulation time 22431832 ps
CPU time 1.23 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 224132 kb
Host smart-9c787eba-3956-4784-8b6e-ab87b64e85b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833115070 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2833115070
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1265546824
Short name T622
Test name
Test status
Simulation time 16815579 ps
CPU time 0.98 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215280 kb
Host smart-3596ce02-d5e9-4aeb-b4b5-6710c37d2158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265546824 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1265546824
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3528424067
Short name T502
Test name
Test status
Simulation time 38889695 ps
CPU time 1.05 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:27:05 PM PDT 24
Peak memory 215264 kb
Host smart-e106c03a-d016-48f8-8714-98598d8ab19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528424067 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3528424067
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2430500746
Short name T749
Test name
Test status
Simulation time 124762486271 ps
CPU time 735.85 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:39:13 PM PDT 24
Peak memory 220944 kb
Host smart-a003c300-53e3-4bda-a3f5-3deffd90d231
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430500746 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2430500746
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.4191885461
Short name T418
Test name
Test status
Simulation time 23654769 ps
CPU time 0.95 seconds
Started Mar 26 03:26:55 PM PDT 24
Finished Mar 26 03:26:56 PM PDT 24
Peak memory 205956 kb
Host smart-78dc1558-8905-4f88-b320-9a267ae27ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191885461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4191885461
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.860262234
Short name T829
Test name
Test status
Simulation time 21095756 ps
CPU time 0.9 seconds
Started Mar 26 03:27:02 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 215384 kb
Host smart-448d4d74-a690-444c-950c-b6837ba84fd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860262234 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.860262234
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4218785793
Short name T524
Test name
Test status
Simulation time 57487105 ps
CPU time 1.12 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 216224 kb
Host smart-ab57062b-acd6-42e4-91b4-f44e09c6da50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218785793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4218785793
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2586960205
Short name T293
Test name
Test status
Simulation time 18045971 ps
CPU time 1.05 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:27:10 PM PDT 24
Peak memory 217884 kb
Host smart-e2dc3d2f-6aa9-40a1-b9e3-67010c13adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586960205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2586960205
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2885313662
Short name T464
Test name
Test status
Simulation time 35288680 ps
CPU time 1.14 seconds
Started Mar 26 03:27:01 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 216704 kb
Host smart-65682005-fdf1-4f74-8dcd-c47665ab1e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885313662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2885313662
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3423741468
Short name T814
Test name
Test status
Simulation time 21062478 ps
CPU time 1.18 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 224060 kb
Host smart-96a9dd6f-6ec8-4b6c-8185-d91b3ca34998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423741468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3423741468
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3283336444
Short name T295
Test name
Test status
Simulation time 15903532 ps
CPU time 1.01 seconds
Started Mar 26 03:27:13 PM PDT 24
Finished Mar 26 03:27:14 PM PDT 24
Peak memory 215336 kb
Host smart-e05eb659-6eb9-4a04-b21f-03f5297245cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283336444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3283336444
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2426082790
Short name T660
Test name
Test status
Simulation time 75625727 ps
CPU time 1.47 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 215288 kb
Host smart-fd693011-60c3-487e-8c43-0b1b91a8756f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426082790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2426082790
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.788408249
Short name T190
Test name
Test status
Simulation time 27605078812 ps
CPU time 635.86 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:37:41 PM PDT 24
Peak memory 218464 kb
Host smart-510ebaac-93ce-4da6-a069-a679a8984a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788408249 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.788408249
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.433615944
Short name T131
Test name
Test status
Simulation time 211480914 ps
CPU time 1.21 seconds
Started Mar 26 03:27:08 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 215596 kb
Host smart-908c8795-6b37-4d6a-97f5-68831a986e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433615944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.433615944
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2236659448
Short name T303
Test name
Test status
Simulation time 68855571 ps
CPU time 0.92 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 205940 kb
Host smart-11881662-10ad-442a-a527-be8933d8929b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236659448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2236659448
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1640906167
Short name T784
Test name
Test status
Simulation time 35188523 ps
CPU time 0.82 seconds
Started Mar 26 03:27:08 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 215796 kb
Host smart-89606a7e-52e9-4fea-ba4a-d30b72674dfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640906167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1640906167
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4146929599
Short name T449
Test name
Test status
Simulation time 34380024 ps
CPU time 1.1 seconds
Started Mar 26 03:26:54 PM PDT 24
Finished Mar 26 03:26:55 PM PDT 24
Peak memory 217728 kb
Host smart-a45a6098-06b4-42ca-bf1d-236c4ea4c11d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146929599 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4146929599
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.592624151
Short name T445
Test name
Test status
Simulation time 36166311 ps
CPU time 1.3 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:03 PM PDT 24
Peak memory 229832 kb
Host smart-32e75f3a-cdb6-44ac-b92a-cb87710b3ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592624151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.592624151
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1978529891
Short name T319
Test name
Test status
Simulation time 88754476 ps
CPU time 1.29 seconds
Started Mar 26 03:27:02 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 219132 kb
Host smart-8dbd8521-db8e-40dd-bf49-785d4814f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978529891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1978529891
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1729841594
Short name T123
Test name
Test status
Simulation time 20646229 ps
CPU time 1.07 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:10 PM PDT 24
Peak memory 216640 kb
Host smart-2987e4a1-70dd-4292-9cb2-199d62b8749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729841594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1729841594
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4013671708
Short name T619
Test name
Test status
Simulation time 15626383 ps
CPU time 0.96 seconds
Started Mar 26 03:26:58 PM PDT 24
Finished Mar 26 03:26:59 PM PDT 24
Peak memory 215200 kb
Host smart-38eb6736-2cec-4414-bf73-59b52603281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013671708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4013671708
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3932779188
Short name T341
Test name
Test status
Simulation time 192908371 ps
CPU time 1.42 seconds
Started Mar 26 03:26:59 PM PDT 24
Finished Mar 26 03:27:01 PM PDT 24
Peak memory 216656 kb
Host smart-091d836e-258a-4093-9209-def3c679e39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932779188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3932779188
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert_test.547144897
Short name T794
Test name
Test status
Simulation time 47777856 ps
CPU time 0.87 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 206784 kb
Host smart-992cc4af-b349-49c6-8feb-257ce0e1d2a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547144897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.547144897
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2118560732
Short name T100
Test name
Test status
Simulation time 14515440 ps
CPU time 0.97 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 215980 kb
Host smart-6c04917c-9ab3-4b36-ab51-58bce081a4a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118560732 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2118560732
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.3060461092
Short name T548
Test name
Test status
Simulation time 19184611 ps
CPU time 1.09 seconds
Started Mar 26 03:27:02 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 218228 kb
Host smart-c64cf014-2dcf-4c6b-b30f-a2737dedd737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060461092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3060461092
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1267575900
Short name T269
Test name
Test status
Simulation time 88412275 ps
CPU time 1.22 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 219360 kb
Host smart-9a051dbd-1794-4396-ae9b-25dd59e64247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267575900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1267575900
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2868421648
Short name T388
Test name
Test status
Simulation time 32019471 ps
CPU time 0.95 seconds
Started Mar 26 03:26:59 PM PDT 24
Finished Mar 26 03:27:00 PM PDT 24
Peak memory 224112 kb
Host smart-5d174065-cedf-47e6-ae72-7ec12e7fc5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868421648 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2868421648
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3308068814
Short name T322
Test name
Test status
Simulation time 35208863 ps
CPU time 0.9 seconds
Started Mar 26 03:27:01 PM PDT 24
Finished Mar 26 03:27:02 PM PDT 24
Peak memory 215272 kb
Host smart-b0a03aa0-804d-432b-8d71-aeeb835b1655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308068814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3308068814
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3552039544
Short name T127
Test name
Test status
Simulation time 223977214 ps
CPU time 4.33 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:15 PM PDT 24
Peak memory 216432 kb
Host smart-c5523d1a-48ba-49b3-957c-70e7f7f3af86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552039544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3552039544
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2361870910
Short name T497
Test name
Test status
Simulation time 73548083491 ps
CPU time 473.2 seconds
Started Mar 26 03:27:04 PM PDT 24
Finished Mar 26 03:34:58 PM PDT 24
Peak memory 218008 kb
Host smart-90c1ced2-7388-41b5-a4b8-f69bb3970533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361870910 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2361870910
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3946556128
Short name T129
Test name
Test status
Simulation time 28567329 ps
CPU time 1.3 seconds
Started Mar 26 03:27:02 PM PDT 24
Finished Mar 26 03:27:04 PM PDT 24
Peak memory 215620 kb
Host smart-3ad4d4c0-7335-41ce-87d5-a0cde9139aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946556128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3946556128
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.934027740
Short name T586
Test name
Test status
Simulation time 21277629 ps
CPU time 1.02 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 206508 kb
Host smart-accb6665-8017-401e-b010-481f0bf1ad24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934027740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.934027740
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2147387167
Short name T423
Test name
Test status
Simulation time 15093001 ps
CPU time 0.89 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 215612 kb
Host smart-c8535558-9e90-4469-aca2-d996941ef0b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147387167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2147387167
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3022427840
Short name T626
Test name
Test status
Simulation time 29946383 ps
CPU time 1.09 seconds
Started Mar 26 03:27:13 PM PDT 24
Finished Mar 26 03:27:14 PM PDT 24
Peak memory 216324 kb
Host smart-c3e57c21-f7fb-450d-90bf-8fb2ac9979cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022427840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3022427840
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4033965784
Short name T478
Test name
Test status
Simulation time 26092094 ps
CPU time 0.89 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 217784 kb
Host smart-45def6df-dc66-4189-b895-b4bb78816b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033965784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4033965784
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.241194621
Short name T799
Test name
Test status
Simulation time 58213535 ps
CPU time 1.27 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 217620 kb
Host smart-28f471fd-30aa-4480-a2d6-5f38fe9f52d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241194621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.241194621
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3181730988
Short name T635
Test name
Test status
Simulation time 25307220 ps
CPU time 0.97 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215460 kb
Host smart-84d5034c-c3d5-4418-91e1-36a40d8b3cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181730988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3181730988
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2319490383
Short name T362
Test name
Test status
Simulation time 50170277 ps
CPU time 0.92 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215272 kb
Host smart-f46b3fb0-82c8-4d0e-9946-d35e92b87b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319490383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2319490383
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2855741352
Short name T685
Test name
Test status
Simulation time 226416403 ps
CPU time 5.26 seconds
Started Mar 26 03:27:03 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 216508 kb
Host smart-87e1fe08-c85b-4860-8506-d44ccbed0fff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855741352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2855741352
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3589317961
Short name T185
Test name
Test status
Simulation time 121554908053 ps
CPU time 1495.59 seconds
Started Mar 26 03:27:00 PM PDT 24
Finished Mar 26 03:51:56 PM PDT 24
Peak memory 223400 kb
Host smart-c35136a2-0cc8-4349-8ab4-4d45f8c84b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589317961 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3589317961
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3272471077
Short name T89
Test name
Test status
Simulation time 57959929 ps
CPU time 1.22 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 215592 kb
Host smart-7d7ffe21-c328-4b28-988b-0297999ea81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272471077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3272471077
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2286209169
Short name T342
Test name
Test status
Simulation time 12476334 ps
CPU time 0.88 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 205816 kb
Host smart-1d426d28-8786-41ca-8eb1-c6c99b8e2a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286209169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2286209169
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3048579536
Short name T337
Test name
Test status
Simulation time 12211793 ps
CPU time 0.9 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215788 kb
Host smart-01b0eea5-840e-4f45-b603-14ed4ce60cb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048579536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3048579536
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.626753835
Short name T455
Test name
Test status
Simulation time 21606903 ps
CPU time 1.05 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 218124 kb
Host smart-d6cbf7fa-79fb-47a5-acac-ac4348744645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626753835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.626753835
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3414153274
Short name T825
Test name
Test status
Simulation time 282599124 ps
CPU time 3.79 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 219548 kb
Host smart-81614d06-76cf-4220-867c-4aba62add6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414153274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3414153274
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1647906048
Short name T111
Test name
Test status
Simulation time 21188038 ps
CPU time 1 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215660 kb
Host smart-c4f7baab-40df-4eec-8eaf-019cedca1a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647906048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1647906048
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3119635180
Short name T783
Test name
Test status
Simulation time 89142636 ps
CPU time 0.87 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 215276 kb
Host smart-f0a89090-a112-49d1-a791-21911b4e0784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119635180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3119635180
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2882900747
Short name T517
Test name
Test status
Simulation time 848309850 ps
CPU time 5.11 seconds
Started Mar 26 03:27:11 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215284 kb
Host smart-a9f389e4-836b-4b7d-976f-04e25d84a622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882900747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2882900747
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1863440696
Short name T184
Test name
Test status
Simulation time 68518829195 ps
CPU time 1700.35 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:55:32 PM PDT 24
Peak memory 223276 kb
Host smart-c0c6d5b4-c277-44c8-b72f-e1b7cfea400f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863440696 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1863440696
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3363929545
Short name T132
Test name
Test status
Simulation time 48215851 ps
CPU time 1.18 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215600 kb
Host smart-5c63d97b-5934-4906-b970-3f14127cfaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363929545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3363929545
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3528695083
Short name T470
Test name
Test status
Simulation time 33821267 ps
CPU time 0.96 seconds
Started Mar 26 03:27:13 PM PDT 24
Finished Mar 26 03:27:15 PM PDT 24
Peak memory 206048 kb
Host smart-4f8e8a5d-4468-4d09-9685-f4bb7d7e7a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528695083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3528695083
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1198149305
Short name T28
Test name
Test status
Simulation time 37362379 ps
CPU time 0.86 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 215524 kb
Host smart-9c7c07fb-3ab1-421f-9e6f-752dc4468c25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198149305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1198149305
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2811181613
Short name T522
Test name
Test status
Simulation time 32949968 ps
CPU time 1.12 seconds
Started Mar 26 03:27:08 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 216356 kb
Host smart-2da76e9e-ffe3-4cfe-9bef-cd53d18f83cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811181613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2811181613
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1549129283
Short name T62
Test name
Test status
Simulation time 31178610 ps
CPU time 1.01 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:10 PM PDT 24
Peak memory 219268 kb
Host smart-0113c465-88e3-4ddd-886b-68b309f87015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549129283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1549129283
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4185783582
Short name T553
Test name
Test status
Simulation time 45395172 ps
CPU time 1.64 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:12 PM PDT 24
Peak memory 216628 kb
Host smart-aab04f9f-b5fc-4423-8663-abfa5f5d8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185783582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4185783582
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.854726888
Short name T689
Test name
Test status
Simulation time 21107805 ps
CPU time 1.2 seconds
Started Mar 26 03:27:13 PM PDT 24
Finished Mar 26 03:27:14 PM PDT 24
Peak memory 224244 kb
Host smart-65d9a94e-86f6-44eb-a172-b81140261af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854726888 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.854726888
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3361522875
Short name T285
Test name
Test status
Simulation time 45108648 ps
CPU time 0.9 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 215260 kb
Host smart-3d8575b6-d231-474d-bafa-d55ea6523522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361522875 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3361522875
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1638780022
Short name T369
Test name
Test status
Simulation time 263434249 ps
CPU time 5.47 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 216292 kb
Host smart-7bdf3b2e-b2a0-45e3-869c-fab3691a73f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638780022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1638780022
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1222860100
Short name T340
Test name
Test status
Simulation time 21710793510 ps
CPU time 478.84 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:35:09 PM PDT 24
Peak memory 223624 kb
Host smart-b0909b2e-c773-4728-b9ab-439df5f10cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222860100 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1222860100
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3105008684
Short name T617
Test name
Test status
Simulation time 55312701 ps
CPU time 1.25 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:27:13 PM PDT 24
Peak memory 215608 kb
Host smart-b4fc7162-899e-4755-bae9-b7e9e790ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105008684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3105008684
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2787445538
Short name T542
Test name
Test status
Simulation time 58661984 ps
CPU time 0.77 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:27:13 PM PDT 24
Peak memory 206612 kb
Host smart-3bc896bd-48b7-4db0-8276-92732c578f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787445538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2787445538
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4137101701
Short name T149
Test name
Test status
Simulation time 23909392 ps
CPU time 0.87 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215896 kb
Host smart-10feae75-bd9e-47c1-a8b0-f066cdfd1963
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137101701 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4137101701
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3822495404
Short name T169
Test name
Test status
Simulation time 89338788 ps
CPU time 1.19 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 216700 kb
Host smart-d83416b4-7b15-414d-a605-2f9969d1e111
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822495404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3822495404
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1205708294
Short name T104
Test name
Test status
Simulation time 31637395 ps
CPU time 1.03 seconds
Started Mar 26 03:27:22 PM PDT 24
Finished Mar 26 03:27:23 PM PDT 24
Peak memory 232656 kb
Host smart-1433fedf-7228-4e3e-8b13-71019b0299f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205708294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1205708294
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.882442349
Short name T555
Test name
Test status
Simulation time 44915097 ps
CPU time 1.46 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 217836 kb
Host smart-a516393d-b307-498d-a8e4-747b046ab9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882442349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.882442349
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2203521042
Short name T46
Test name
Test status
Simulation time 30533123 ps
CPU time 1 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:27:13 PM PDT 24
Peak memory 224044 kb
Host smart-b60e817e-2a3c-4373-88d4-f2e73bc816d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203521042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2203521042
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3368502579
Short name T318
Test name
Test status
Simulation time 23335926 ps
CPU time 0.92 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 215352 kb
Host smart-f081d06b-ee0c-44b3-af13-63a1483fd6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368502579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3368502579
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2497163489
Short name T443
Test name
Test status
Simulation time 508420776 ps
CPU time 3.15 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:13 PM PDT 24
Peak memory 216372 kb
Host smart-730811bb-4865-4adf-8225-e089221eac53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497163489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2497163489
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1245579408
Short name T650
Test name
Test status
Simulation time 25022962179 ps
CPU time 561.62 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:36:38 PM PDT 24
Peak memory 218464 kb
Host smart-af2bbab4-c6bb-4efc-8a14-78d63007dde0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245579408 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1245579408
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2371394495
Short name T653
Test name
Test status
Simulation time 48299645 ps
CPU time 1.19 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:10 PM PDT 24
Peak memory 215568 kb
Host smart-1c8a39cb-2b55-4435-805c-6212ee93093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371394495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2371394495
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3921172974
Short name T556
Test name
Test status
Simulation time 19612576 ps
CPU time 1 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:10 PM PDT 24
Peak memory 206008 kb
Host smart-885824cf-2559-4d04-9103-faecb440c320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921172974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3921172974
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1203607879
Short name T84
Test name
Test status
Simulation time 43474629 ps
CPU time 0.9 seconds
Started Mar 26 03:27:11 PM PDT 24
Finished Mar 26 03:27:12 PM PDT 24
Peak memory 215440 kb
Host smart-a8c4342b-3a22-4162-a77c-ada3254f964b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203607879 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1203607879
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.4220581786
Short name T148
Test name
Test status
Simulation time 26453885 ps
CPU time 0.96 seconds
Started Mar 26 03:27:21 PM PDT 24
Finished Mar 26 03:27:22 PM PDT 24
Peak memory 217988 kb
Host smart-4e29b5d9-deb2-4d29-a90c-a4c8edc7b58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220581786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4220581786
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_intr.1991511422
Short name T690
Test name
Test status
Simulation time 22627398 ps
CPU time 1.1 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 215388 kb
Host smart-da030c8a-e099-4ec2-bbd7-1b43c6896a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991511422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1991511422
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1065184992
Short name T670
Test name
Test status
Simulation time 18797103 ps
CPU time 1.03 seconds
Started Mar 26 03:27:08 PM PDT 24
Finished Mar 26 03:27:09 PM PDT 24
Peak memory 215256 kb
Host smart-4934e65f-cc00-4b02-86b6-4054d9b68d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065184992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1065184992
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1652679604
Short name T695
Test name
Test status
Simulation time 949619573 ps
CPU time 3.04 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:20 PM PDT 24
Peak memory 216728 kb
Host smart-ed86355c-ed59-49a0-a532-7d771bde5818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652679604 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1652679604
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1619945374
Short name T678
Test name
Test status
Simulation time 422018499576 ps
CPU time 883.54 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:41:58 PM PDT 24
Peak memory 220780 kb
Host smart-b2d692d0-3056-4514-a712-03e0a6c04c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619945374 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1619945374
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.450755152
Short name T572
Test name
Test status
Simulation time 36473253 ps
CPU time 1.2 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 215604 kb
Host smart-169e8da5-2883-4e15-a4f1-44d784c75e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450755152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.450755152
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.628088930
Short name T376
Test name
Test status
Simulation time 21758103 ps
CPU time 1 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:27:13 PM PDT 24
Peak memory 206044 kb
Host smart-1206a4ed-4788-416a-8f05-f2fdf2ac091d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628088930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.628088930
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.886511028
Short name T167
Test name
Test status
Simulation time 52520485 ps
CPU time 0.85 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 214736 kb
Host smart-8a9511b8-6e93-4982-8b1b-bd9a5d7d26f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886511028 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.886511028
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2522376919
Short name T538
Test name
Test status
Simulation time 50680687 ps
CPU time 1.11 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 216464 kb
Host smart-0a28132b-ad25-418a-bf6a-8fd0d7dfe590
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522376919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2522376919
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3010924610
Short name T557
Test name
Test status
Simulation time 19397365 ps
CPU time 1.07 seconds
Started Mar 26 03:27:09 PM PDT 24
Finished Mar 26 03:27:10 PM PDT 24
Peak memory 217928 kb
Host smart-8a6f3bd6-b037-4ce8-a987-6e3aea1bdb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010924610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3010924610
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.240062202
Short name T436
Test name
Test status
Simulation time 127406140 ps
CPU time 1.23 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:11 PM PDT 24
Peak memory 216744 kb
Host smart-61e36730-9e2b-4e44-8682-411f7a155a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240062202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.240062202
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3570255427
Short name T125
Test name
Test status
Simulation time 19803561 ps
CPU time 1.04 seconds
Started Mar 26 03:27:13 PM PDT 24
Finished Mar 26 03:27:14 PM PDT 24
Peak memory 215772 kb
Host smart-36dedc13-f1c3-4b67-9034-6f2cc5c1c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570255427 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3570255427
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.671612196
Short name T380
Test name
Test status
Simulation time 47786274 ps
CPU time 0.95 seconds
Started Mar 26 03:27:06 PM PDT 24
Finished Mar 26 03:27:07 PM PDT 24
Peak memory 215308 kb
Host smart-2310c873-2bc0-4f08-99aa-92f80e7071ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671612196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.671612196
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1350192459
Short name T633
Test name
Test status
Simulation time 617758315 ps
CPU time 5.1 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:23 PM PDT 24
Peak memory 216792 kb
Host smart-dbec2a7f-cc63-4746-a014-23c1b877e5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350192459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1350192459
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.2035570890
Short name T248
Test name
Test status
Simulation time 44843033 ps
CPU time 1.19 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 215620 kb
Host smart-b1d456f4-b707-4c24-a0a7-596d967cc34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035570890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2035570890
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2690877749
Short name T714
Test name
Test status
Simulation time 62151087 ps
CPU time 1.2 seconds
Started Mar 26 03:26:24 PM PDT 24
Finished Mar 26 03:26:25 PM PDT 24
Peak memory 206448 kb
Host smart-43064784-e9b7-4ee6-ab06-5c7b86413c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690877749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2690877749
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1936043334
Short name T639
Test name
Test status
Simulation time 15937132 ps
CPU time 0.79 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215868 kb
Host smart-bc4cefb2-02ac-444c-8dce-beaa5b9f52e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936043334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1936043334
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.636814491
Short name T409
Test name
Test status
Simulation time 122328675 ps
CPU time 1.24 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:26:22 PM PDT 24
Peak memory 216648 kb
Host smart-b197624f-d4e7-474c-b208-f6b21741949a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636814491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.636814491
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1563245405
Short name T54
Test name
Test status
Simulation time 21076416 ps
CPU time 1.2 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:26:22 PM PDT 24
Peak memory 219368 kb
Host smart-725e41cf-8caf-4ba3-a4c8-d52ac02b0218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563245405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1563245405
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3441905319
Short name T680
Test name
Test status
Simulation time 129524867 ps
CPU time 1.4 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 218128 kb
Host smart-85a888f6-6b1d-441a-9526-3d7189f99beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441905319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3441905319
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.19997598
Short name T115
Test name
Test status
Simulation time 21639447 ps
CPU time 1.08 seconds
Started Mar 26 03:26:54 PM PDT 24
Finished Mar 26 03:26:56 PM PDT 24
Peak memory 215756 kb
Host smart-52592b62-9bbb-4ff9-99fb-446a175ac26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19997598 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.19997598
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.567848224
Short name T49
Test name
Test status
Simulation time 350685415 ps
CPU time 6.02 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 237108 kb
Host smart-84a79ec6-e097-4375-a5cb-b133d4d4dfec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567848224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.567848224
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3682256530
Short name T750
Test name
Test status
Simulation time 38346449 ps
CPU time 0.87 seconds
Started Mar 26 03:26:23 PM PDT 24
Finished Mar 26 03:26:24 PM PDT 24
Peak memory 215104 kb
Host smart-df98370a-4530-4b34-9a85-e481de3e636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682256530 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3682256530
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.471726699
Short name T483
Test name
Test status
Simulation time 66665836 ps
CPU time 1.9 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 217884 kb
Host smart-692a9707-b01f-49ae-95af-70c53e8c4a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471726699 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.471726699
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3308883652
Short name T176
Test name
Test status
Simulation time 84485578579 ps
CPU time 527.65 seconds
Started Mar 26 03:26:23 PM PDT 24
Finished Mar 26 03:35:11 PM PDT 24
Peak memory 219088 kb
Host smart-0bf0968f-59b3-445b-9108-65a3d8dabc6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308883652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3308883652
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2545065334
Short name T237
Test name
Test status
Simulation time 48968572 ps
CPU time 1.17 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:27:13 PM PDT 24
Peak memory 215636 kb
Host smart-138890fb-dff5-4cf1-b6c0-5460373981a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545065334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2545065334
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2259636441
Short name T406
Test name
Test status
Simulation time 18803525 ps
CPU time 0.78 seconds
Started Mar 26 03:27:21 PM PDT 24
Finished Mar 26 03:27:22 PM PDT 24
Peak memory 205252 kb
Host smart-0a55b033-373d-43c2-9bc1-87cc30167fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259636441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2259636441
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2376664284
Short name T764
Test name
Test status
Simulation time 17666114 ps
CPU time 0.9 seconds
Started Mar 26 03:27:07 PM PDT 24
Finished Mar 26 03:27:08 PM PDT 24
Peak memory 215548 kb
Host smart-e4818e08-7a44-4d85-9436-edd5f4e84a64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376664284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2376664284
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.1712186241
Short name T306
Test name
Test status
Simulation time 19114943 ps
CPU time 1.09 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 218196 kb
Host smart-4a7866fc-984c-4b53-996e-ded4ad385ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712186241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1712186241
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1463620960
Short name T267
Test name
Test status
Simulation time 57775857 ps
CPU time 1.51 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 217828 kb
Host smart-b6486290-62db-4e54-82f3-7ba67514b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463620960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1463620960
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3394677001
Short name T402
Test name
Test status
Simulation time 29146909 ps
CPU time 0.99 seconds
Started Mar 26 03:27:05 PM PDT 24
Finished Mar 26 03:27:06 PM PDT 24
Peak memory 215476 kb
Host smart-95c302aa-047b-4f9c-a1e4-f920582341b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394677001 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3394677001
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.418970779
Short name T602
Test name
Test status
Simulation time 18193777 ps
CPU time 1.02 seconds
Started Mar 26 03:27:11 PM PDT 24
Finished Mar 26 03:27:12 PM PDT 24
Peak memory 215252 kb
Host smart-cacdcefe-6cbd-4d4a-b7b0-86dc6cfa7c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418970779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.418970779
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2403109271
Short name T448
Test name
Test status
Simulation time 46892046 ps
CPU time 1.52 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 217636 kb
Host smart-70706096-e217-4da2-a0c3-b670af0b7cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403109271 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2403109271
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.749561486
Short name T197
Test name
Test status
Simulation time 80328663292 ps
CPU time 389.97 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:33:46 PM PDT 24
Peak memory 218196 kb
Host smart-2bb8eaf6-de2c-4993-8f47-31b423a9d1f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749561486 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.749561486
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.3167939971
Short name T551
Test name
Test status
Simulation time 68183582 ps
CPU time 0.8 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 206348 kb
Host smart-8d4797ed-1e10-4be7-907b-fec81fdde87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167939971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3167939971
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2026935902
Short name T313
Test name
Test status
Simulation time 12809579 ps
CPU time 0.95 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215876 kb
Host smart-98e488c4-fd7b-4afb-b798-51298afd2dab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026935902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2026935902
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.176763213
Short name T145
Test name
Test status
Simulation time 52551259 ps
CPU time 1.91 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 216484 kb
Host smart-430873cc-3e57-4e75-8b05-f88fbd12f72e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176763213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.176763213
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2721928977
Short name T385
Test name
Test status
Simulation time 22490803 ps
CPU time 0.91 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 217972 kb
Host smart-46261b1f-b2d1-46d0-9b16-052515fcf12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721928977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2721928977
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2257631545
Short name T531
Test name
Test status
Simulation time 36148970 ps
CPU time 1.4 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 217780 kb
Host smart-e5710038-efaf-4220-9042-36fe5098d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257631545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2257631545
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1224585320
Short name T364
Test name
Test status
Simulation time 28518299 ps
CPU time 0.97 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 215564 kb
Host smart-91382b17-c910-4c7a-b13a-ae8d7279da82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224585320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1224585320
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.520715919
Short name T394
Test name
Test status
Simulation time 28698000 ps
CPU time 1.01 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 214652 kb
Host smart-a53b4f47-797c-4140-9ae4-542e5d0b3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520715919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.520715919
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.336068494
Short name T834
Test name
Test status
Simulation time 221933605 ps
CPU time 1.71 seconds
Started Mar 26 03:27:10 PM PDT 24
Finished Mar 26 03:27:12 PM PDT 24
Peak memory 215276 kb
Host smart-cbcdf39e-fa11-441c-b618-a0e43abaa79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336068494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.336068494
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.988771248
Short name T515
Test name
Test status
Simulation time 252697847382 ps
CPU time 1546.48 seconds
Started Mar 26 03:27:12 PM PDT 24
Finished Mar 26 03:53:00 PM PDT 24
Peak memory 223732 kb
Host smart-05cb6690-ccf5-4556-b64e-60b4800bf76d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988771248 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.988771248
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2507465363
Short name T247
Test name
Test status
Simulation time 95843395 ps
CPU time 1.24 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 215564 kb
Host smart-28df3b7b-59cb-4bcc-b231-3a92fef7cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507465363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2507465363
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2910260693
Short name T334
Test name
Test status
Simulation time 54401386 ps
CPU time 0.84 seconds
Started Mar 26 03:27:23 PM PDT 24
Finished Mar 26 03:27:24 PM PDT 24
Peak memory 206772 kb
Host smart-24bd472e-03b2-4ec7-aea7-a65f08ea6fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910260693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2910260693
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.294893559
Short name T160
Test name
Test status
Simulation time 11795164 ps
CPU time 0.87 seconds
Started Mar 26 03:27:23 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 215792 kb
Host smart-2998c38b-f68e-48d3-b1d1-be87e5221037
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294893559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.294893559
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.356766706
Short name T715
Test name
Test status
Simulation time 330469967 ps
CPU time 1.06 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:22 PM PDT 24
Peak memory 216420 kb
Host smart-d42b4629-5ca0-4357-ada1-4a8e3ea63c76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356766706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.356766706
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.70749624
Short name T769
Test name
Test status
Simulation time 30796370 ps
CPU time 1.2 seconds
Started Mar 26 03:27:19 PM PDT 24
Finished Mar 26 03:27:21 PM PDT 24
Peak memory 219204 kb
Host smart-3311edc0-3eb2-4169-bd43-f619d59766d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70749624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.70749624
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3932175167
Short name T576
Test name
Test status
Simulation time 38920229 ps
CPU time 1.35 seconds
Started Mar 26 03:27:34 PM PDT 24
Finished Mar 26 03:27:36 PM PDT 24
Peak memory 216856 kb
Host smart-6790049c-8dca-43ea-9a5d-f58c05fada1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932175167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3932175167
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2403637104
Short name T766
Test name
Test status
Simulation time 41702770 ps
CPU time 0.87 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215432 kb
Host smart-62461669-ab7f-4847-960e-45f2fa0cbc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403637104 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2403637104
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1502074396
Short name T657
Test name
Test status
Simulation time 138670609 ps
CPU time 0.96 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215280 kb
Host smart-935cf5bf-456f-4fbd-bd54-8a9244e53552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502074396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1502074396
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.622422886
Short name T805
Test name
Test status
Simulation time 86434923 ps
CPU time 2.25 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:27 PM PDT 24
Peak memory 216508 kb
Host smart-49987a62-8cba-43a4-b8d5-73d9f1d5afef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622422886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.622422886
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2020153725
Short name T658
Test name
Test status
Simulation time 83612052603 ps
CPU time 800.59 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:40:49 PM PDT 24
Peak memory 221784 kb
Host smart-c05eba50-d819-4f10-b074-458e2f8294fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020153725 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2020153725
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.4122484025
Short name T801
Test name
Test status
Simulation time 26415380 ps
CPU time 1.16 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 215632 kb
Host smart-a084d1ab-6e09-4ee9-869d-ef1596e42eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122484025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4122484025
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2076865518
Short name T725
Test name
Test status
Simulation time 33241017 ps
CPU time 0.79 seconds
Started Mar 26 03:27:19 PM PDT 24
Finished Mar 26 03:27:20 PM PDT 24
Peak memory 205564 kb
Host smart-a0ce4f75-29d6-4a0f-8179-a5ec33c00eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076865518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2076865518
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2112218939
Short name T147
Test name
Test status
Simulation time 27552311 ps
CPU time 0.83 seconds
Started Mar 26 03:27:23 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 215856 kb
Host smart-e581344c-81d0-4484-af07-02a908c5cbc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112218939 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2112218939
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.808048691
Short name T793
Test name
Test status
Simulation time 73946905 ps
CPU time 1.07 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 216608 kb
Host smart-33c648be-f687-4bed-a5a8-f69c6b9fe3c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808048691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.808048691
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.339679965
Short name T781
Test name
Test status
Simulation time 30933906 ps
CPU time 1.23 seconds
Started Mar 26 03:27:20 PM PDT 24
Finished Mar 26 03:27:22 PM PDT 24
Peak memory 219088 kb
Host smart-d7ceb723-5c34-461b-9ca9-cb186458401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339679965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.339679965
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1403545617
Short name T354
Test name
Test status
Simulation time 78885108 ps
CPU time 1.42 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 218304 kb
Host smart-19136ace-887f-4cc8-a971-640171e60d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403545617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1403545617
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2193340304
Short name T606
Test name
Test status
Simulation time 24256511 ps
CPU time 0.95 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 215476 kb
Host smart-4cb42e22-b57d-45c4-b25c-d5b02a79c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193340304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2193340304
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2387961065
Short name T305
Test name
Test status
Simulation time 20656641 ps
CPU time 0.91 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215276 kb
Host smart-f982e7af-9aaa-4c2e-a6b0-503cbc19b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387961065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2387961065
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3945433216
Short name T760
Test name
Test status
Simulation time 261936277 ps
CPU time 5.4 seconds
Started Mar 26 03:27:11 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 216484 kb
Host smart-db53626c-f0ef-40e3-b27f-903ed2b6808c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945433216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3945433216
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.573301167
Short name T648
Test name
Test status
Simulation time 56564912658 ps
CPU time 1505.6 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:52:25 PM PDT 24
Peak memory 220976 kb
Host smart-6f396752-a904-4b4a-a0bf-bc74a0c569bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573301167 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.573301167
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.149758887
Short name T238
Test name
Test status
Simulation time 31391381 ps
CPU time 1.29 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 215600 kb
Host smart-d1d1a6bf-857e-4867-b04f-095fdaf4047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149758887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.149758887
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1274762742
Short name T41
Test name
Test status
Simulation time 27452647 ps
CPU time 1.08 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 205996 kb
Host smart-38425a2f-711e-4532-95ab-77bb00933e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274762742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1274762742
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3663130725
Short name T174
Test name
Test status
Simulation time 57172307 ps
CPU time 0.86 seconds
Started Mar 26 03:27:20 PM PDT 24
Finished Mar 26 03:27:21 PM PDT 24
Peak memory 215396 kb
Host smart-01521372-bbfd-402e-9036-20ae39982ad2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663130725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3663130725
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3298909322
Short name T740
Test name
Test status
Simulation time 80389458 ps
CPU time 1.01 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 217436 kb
Host smart-f8f365d4-4298-4c8a-9e30-31b7cd74a35b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298909322 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3298909322
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2861234263
Short name T377
Test name
Test status
Simulation time 82013781 ps
CPU time 1.01 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 220284 kb
Host smart-7d6a5089-a531-4bb1-9706-59d456a574e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861234263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2861234263
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.798404425
Short name T566
Test name
Test status
Simulation time 123272043 ps
CPU time 1.16 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 216592 kb
Host smart-987bbdab-a934-45d4-8846-2bc975a78831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798404425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.798404425
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.531807582
Short name T137
Test name
Test status
Simulation time 127650338 ps
CPU time 0.87 seconds
Started Mar 26 03:27:23 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 215228 kb
Host smart-fd245fd2-8b72-41b5-853a-7741e2d2f4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531807582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.531807582
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.382337675
Short name T456
Test name
Test status
Simulation time 40058029 ps
CPU time 0.89 seconds
Started Mar 26 03:27:40 PM PDT 24
Finished Mar 26 03:27:41 PM PDT 24
Peak memory 215144 kb
Host smart-3f8808b4-0c3c-4278-934e-8946ab06843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382337675 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.382337675
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.965784652
Short name T372
Test name
Test status
Simulation time 156226317 ps
CPU time 1.97 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:20 PM PDT 24
Peak memory 216404 kb
Host smart-16491eac-e7e6-43b5-8555-b3f2d94ef564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965784652 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.965784652
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.11388127
Short name T128
Test name
Test status
Simulation time 63352599303 ps
CPU time 1509.3 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:52:25 PM PDT 24
Peak memory 224148 kb
Host smart-cdeaf0ef-9dc0-4550-b1af-7221384f24ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11388127 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.11388127
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2383343990
Short name T166
Test name
Test status
Simulation time 176291473 ps
CPU time 1.32 seconds
Started Mar 26 03:27:14 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215656 kb
Host smart-224cf343-7b6a-4533-aef7-96fe5712dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383343990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2383343990
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3300809415
Short name T795
Test name
Test status
Simulation time 18552781 ps
CPU time 0.96 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:25 PM PDT 24
Peak memory 205964 kb
Host smart-a8a64f04-3af9-4c4b-aeaf-b46079475e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300809415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3300809415
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3996808140
Short name T719
Test name
Test status
Simulation time 15827189 ps
CPU time 0.91 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 216036 kb
Host smart-72f53fff-7a4a-43a9-8cff-427f87f60133
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996808140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3996808140
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.277732092
Short name T61
Test name
Test status
Simulation time 47766871 ps
CPU time 1.46 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 216484 kb
Host smart-7bdd44df-3d26-4f0e-9ac7-93fa1887e1eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277732092 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.277732092
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1229516525
Short name T652
Test name
Test status
Simulation time 23709027 ps
CPU time 1.16 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 220228 kb
Host smart-2dfcac33-8154-444e-acd9-1940d1bb4edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229516525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1229516525
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3215245966
Short name T262
Test name
Test status
Simulation time 124459076 ps
CPU time 2.51 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 219536 kb
Host smart-5e940d1a-dca1-470b-9c26-6f689fa9ac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215245966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3215245966
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2789418839
Short name T327
Test name
Test status
Simulation time 31399075 ps
CPU time 0.86 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 215224 kb
Host smart-6ff39f37-7e13-4166-8c3d-3517faf7c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789418839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2789418839
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2144615755
Short name T395
Test name
Test status
Simulation time 17548381 ps
CPU time 0.97 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215256 kb
Host smart-5e9fac39-5f19-41ec-a1fd-5d16a940940c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144615755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2144615755
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1675961985
Short name T329
Test name
Test status
Simulation time 32066003 ps
CPU time 1.22 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:27 PM PDT 24
Peak memory 215272 kb
Host smart-e9409b5c-1489-4783-ae4f-1fff2e261e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675961985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1675961985
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3991870410
Short name T589
Test name
Test status
Simulation time 60105905057 ps
CPU time 1378.44 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:50:15 PM PDT 24
Peak memory 220932 kb
Host smart-f8292844-f120-4a0a-a95c-f0bc2a134bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991870410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3991870410
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1339342896
Short name T501
Test name
Test status
Simulation time 31916614 ps
CPU time 1.36 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215612 kb
Host smart-13c4d906-7742-43c0-b8f6-2d43ff91f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339342896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1339342896
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4144476534
Short name T659
Test name
Test status
Simulation time 13643704 ps
CPU time 0.88 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 205816 kb
Host smart-1b66fba2-9628-4d5c-bf46-afa4edee4038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144476534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4144476534
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.631437217
Short name T155
Test name
Test status
Simulation time 22102059 ps
CPU time 0.92 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215816 kb
Host smart-bf724946-f62f-4cb1-acf3-e4e7e88b7504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631437217 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.631437217
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3475847984
Short name T75
Test name
Test status
Simulation time 58621998 ps
CPU time 1.15 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 216512 kb
Host smart-bf75f0b4-6936-4dab-ab96-c24c2cd0153b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475847984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3475847984
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1522120180
Short name T161
Test name
Test status
Simulation time 30050098 ps
CPU time 1.29 seconds
Started Mar 26 03:27:37 PM PDT 24
Finished Mar 26 03:27:39 PM PDT 24
Peak memory 219072 kb
Host smart-9a5614ef-5cc3-40c5-a795-974a4562f0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522120180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1522120180
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3611472085
Short name T487
Test name
Test status
Simulation time 55093219 ps
CPU time 1.22 seconds
Started Mar 26 03:27:20 PM PDT 24
Finished Mar 26 03:27:22 PM PDT 24
Peak memory 216728 kb
Host smart-e54167e0-c3a4-4a55-9fe4-e460f4e51d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611472085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3611472085
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.222914075
Short name T114
Test name
Test status
Simulation time 21689852 ps
CPU time 1.07 seconds
Started Mar 26 03:27:22 PM PDT 24
Finished Mar 26 03:27:23 PM PDT 24
Peak memory 215624 kb
Host smart-380192aa-5ef9-4c9d-bcbe-4d5c62e1c66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222914075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.222914075
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.826403787
Short name T163
Test name
Test status
Simulation time 20759365 ps
CPU time 0.92 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215284 kb
Host smart-309bc0b6-bc61-4096-9223-238351bc29d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826403787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.826403787
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3402280003
Short name T381
Test name
Test status
Simulation time 125859111 ps
CPU time 1.3 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 216392 kb
Host smart-7542791c-4a02-4ddc-ab3b-a3f62542e74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402280003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3402280003
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3898222177
Short name T178
Test name
Test status
Simulation time 75364007011 ps
CPU time 1004.82 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:44:11 PM PDT 24
Peak memory 223712 kb
Host smart-24bf8ff5-dd70-48d7-8a3a-8679418dce25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898222177 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3898222177
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1035191652
Short name T804
Test name
Test status
Simulation time 48175699 ps
CPU time 1.19 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 215568 kb
Host smart-e8abf3e7-0f9d-4b69-b738-2294e1e91ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035191652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1035191652
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1238148127
Short name T529
Test name
Test status
Simulation time 25125972 ps
CPU time 0.86 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 205924 kb
Host smart-f348c708-3017-4ae1-9e90-75bea1ff7fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238148127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1238148127
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3828252165
Short name T85
Test name
Test status
Simulation time 12171091 ps
CPU time 0.86 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 215528 kb
Host smart-b6d0ab66-3501-4ba1-9ff6-1aebfe5241db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828252165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3828252165
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2238173879
Short name T609
Test name
Test status
Simulation time 20430663 ps
CPU time 0.95 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 217496 kb
Host smart-cb72956d-dcba-4fb6-9eeb-b7fb61e68f59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238173879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2238173879
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1159864813
Short name T580
Test name
Test status
Simulation time 52625344 ps
CPU time 0.97 seconds
Started Mar 26 03:27:22 PM PDT 24
Finished Mar 26 03:27:23 PM PDT 24
Peak memory 219268 kb
Host smart-701024ee-38b6-49bf-9a85-c0aa8c5a2e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159864813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1159864813
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1758661306
Short name T638
Test name
Test status
Simulation time 70557378 ps
CPU time 1.04 seconds
Started Mar 26 03:27:20 PM PDT 24
Finished Mar 26 03:27:21 PM PDT 24
Peak memory 216480 kb
Host smart-ae3302a1-585d-464b-ac64-33a81c6a57d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758661306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1758661306
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2573169917
Short name T43
Test name
Test status
Simulation time 30204079 ps
CPU time 1.1 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 224104 kb
Host smart-b8ff7a15-3b20-4c42-96a5-b74f4323de08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573169917 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2573169917
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.4270147715
Short name T286
Test name
Test status
Simulation time 86482964 ps
CPU time 0.85 seconds
Started Mar 26 03:27:15 PM PDT 24
Finished Mar 26 03:27:16 PM PDT 24
Peak memory 215288 kb
Host smart-023e252f-72dd-45e9-bb0e-1448d05c95e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270147715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.4270147715
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1270958813
Short name T802
Test name
Test status
Simulation time 671296412 ps
CPU time 3.69 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 216716 kb
Host smart-95d94a51-024f-4948-84c6-035fcaa6da99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270958813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1270958813
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.352232533
Short name T479
Test name
Test status
Simulation time 111726627357 ps
CPU time 1560.45 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:53:27 PM PDT 24
Peak memory 225948 kb
Host smart-d9d6739f-2a96-40b6-b027-83390adb3fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352232533 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.352232533
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1607820148
Short name T133
Test name
Test status
Simulation time 27378715 ps
CPU time 1.23 seconds
Started Mar 26 03:27:19 PM PDT 24
Finished Mar 26 03:27:21 PM PDT 24
Peak memory 215600 kb
Host smart-6f0671fa-5e7f-49d5-90cd-f2fc766f22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607820148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1607820148
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.4166141911
Short name T437
Test name
Test status
Simulation time 21840970 ps
CPU time 0.82 seconds
Started Mar 26 03:27:24 PM PDT 24
Finished Mar 26 03:27:26 PM PDT 24
Peak memory 205744 kb
Host smart-56ad978e-7b8e-4bb0-815c-5da591064fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166141911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4166141911
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.4284737240
Short name T432
Test name
Test status
Simulation time 11174849 ps
CPU time 0.85 seconds
Started Mar 26 03:27:39 PM PDT 24
Finished Mar 26 03:27:40 PM PDT 24
Peak memory 215484 kb
Host smart-313356cb-c155-407b-915f-25c0ba5e2236
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284737240 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4284737240
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2276205711
Short name T12
Test name
Test status
Simulation time 29566540 ps
CPU time 1.14 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:27:18 PM PDT 24
Peak memory 217536 kb
Host smart-539b988c-acda-4a0f-bbc2-da0a35d32cd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276205711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2276205711
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3988561112
Short name T102
Test name
Test status
Simulation time 22735320 ps
CPU time 0.95 seconds
Started Mar 26 03:27:22 PM PDT 24
Finished Mar 26 03:27:23 PM PDT 24
Peak memory 218044 kb
Host smart-23ebe7e9-880d-4287-a73f-21f8c36f3775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988561112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3988561112
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2562094397
Short name T276
Test name
Test status
Simulation time 40647673 ps
CPU time 1.64 seconds
Started Mar 26 03:27:19 PM PDT 24
Finished Mar 26 03:27:21 PM PDT 24
Peak memory 217860 kb
Host smart-6ba6b204-ad3e-4242-89a8-0c74d1397188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562094397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2562094397
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1447453271
Short name T112
Test name
Test status
Simulation time 35834687 ps
CPU time 0.89 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:17 PM PDT 24
Peak memory 215492 kb
Host smart-ed44188d-2ef4-404a-a492-05d5817c655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447453271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1447453271
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1209969370
Short name T201
Test name
Test status
Simulation time 227014487 ps
CPU time 0.9 seconds
Started Mar 26 03:27:18 PM PDT 24
Finished Mar 26 03:27:19 PM PDT 24
Peak memory 207072 kb
Host smart-26c551ca-c26e-4a95-8685-e0091ca9c476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209969370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1209969370
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1886179951
Short name T533
Test name
Test status
Simulation time 436282402 ps
CPU time 4.8 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 216336 kb
Host smart-50060c5a-9e65-446b-bc67-c3fb0a993630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886179951 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1886179951
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2608037028
Short name T625
Test name
Test status
Simulation time 41789226127 ps
CPU time 724.99 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:39:33 PM PDT 24
Peak memory 218176 kb
Host smart-0e42eabb-440d-4ddd-b8b5-57ae365181be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608037028 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2608037028
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2325873915
Short name T90
Test name
Test status
Simulation time 29040770 ps
CPU time 1.23 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 215632 kb
Host smart-78037a21-e15a-4656-9de6-420c9d35b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325873915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2325873915
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.25017575
Short name T299
Test name
Test status
Simulation time 23689797 ps
CPU time 0.96 seconds
Started Mar 26 03:27:32 PM PDT 24
Finished Mar 26 03:27:33 PM PDT 24
Peak memory 206696 kb
Host smart-04273d33-59be-4f0a-91a4-505eeeb8321e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.25017575
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2072959099
Short name T720
Test name
Test status
Simulation time 21723398 ps
CPU time 0.9 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 215616 kb
Host smart-50e05625-656b-4444-b840-bcaed9462b30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072959099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2072959099
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.435977097
Short name T320
Test name
Test status
Simulation time 68730820 ps
CPU time 0.99 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 216480 kb
Host smart-fcef8929-17c3-4b8b-9226-2beb2ae08314
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435977097 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.435977097
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.597451058
Short name T374
Test name
Test status
Simulation time 33605135 ps
CPU time 1.26 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 218940 kb
Host smart-92a79c43-ef73-43ab-821d-5c50152bb08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597451058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.597451058
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2524995657
Short name T366
Test name
Test status
Simulation time 88967003 ps
CPU time 1.71 seconds
Started Mar 26 03:27:22 PM PDT 24
Finished Mar 26 03:27:24 PM PDT 24
Peak memory 217984 kb
Host smart-1cc155a9-01b1-42ed-b389-873ad4327d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524995657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2524995657
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.53516146
Short name T474
Test name
Test status
Simulation time 38940500 ps
CPU time 0.96 seconds
Started Mar 26 03:27:25 PM PDT 24
Finished Mar 26 03:27:27 PM PDT 24
Peak memory 223060 kb
Host smart-10d380be-758f-449b-a1c7-d9e900467b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53516146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.53516146
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.463436340
Short name T506
Test name
Test status
Simulation time 29137159 ps
CPU time 0.99 seconds
Started Mar 26 03:27:20 PM PDT 24
Finished Mar 26 03:27:21 PM PDT 24
Peak memory 215288 kb
Host smart-a8820d99-ab36-4789-abd8-2f5773ab2e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463436340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.463436340
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.172861106
Short name T758
Test name
Test status
Simulation time 511905628 ps
CPU time 3.33 seconds
Started Mar 26 03:27:16 PM PDT 24
Finished Mar 26 03:27:20 PM PDT 24
Peak memory 219056 kb
Host smart-01382709-a7fa-424b-abb4-0ad73a67d37b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172861106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.172861106
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1049196220
Short name T507
Test name
Test status
Simulation time 212398891657 ps
CPU time 836.41 seconds
Started Mar 26 03:27:17 PM PDT 24
Finished Mar 26 03:41:14 PM PDT 24
Peak memory 220772 kb
Host smart-ff01a06c-0101-42de-973f-d4dbac6f16be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049196220 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1049196220
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2264730109
Short name T828
Test name
Test status
Simulation time 51565223 ps
CPU time 1.16 seconds
Started Mar 26 03:26:22 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 215620 kb
Host smart-4fd5c512-ceb1-4556-a861-6ada4f267db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264730109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2264730109
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2462017217
Short name T438
Test name
Test status
Simulation time 39719430 ps
CPU time 0.93 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 205960 kb
Host smart-f939e2b0-58b4-4f81-a1fe-8b6ce15fb612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462017217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2462017217
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2099440858
Short name T700
Test name
Test status
Simulation time 88324189 ps
CPU time 0.86 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 215484 kb
Host smart-8d9d447b-985a-4a3c-aa9e-8e4c801e4bef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099440858 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2099440858
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3306594383
Short name T309
Test name
Test status
Simulation time 47969872 ps
CPU time 1.05 seconds
Started Mar 26 03:26:24 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 216276 kb
Host smart-3ae0f68d-50ee-4283-8e21-5735e3d79f7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306594383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3306594383
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3508447189
Short name T641
Test name
Test status
Simulation time 18667480 ps
CPU time 1.02 seconds
Started Mar 26 03:26:15 PM PDT 24
Finished Mar 26 03:26:16 PM PDT 24
Peak memory 217764 kb
Host smart-b26d849c-420f-4f45-8a4e-b3847445edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508447189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3508447189
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4293783921
Short name T809
Test name
Test status
Simulation time 33397986 ps
CPU time 1.36 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 217788 kb
Host smart-3f880eb6-0fd0-4205-b615-2e256ad0988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293783921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4293783921
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2596353683
Short name T540
Test name
Test status
Simulation time 21502337 ps
CPU time 1.15 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 215404 kb
Host smart-667fef8a-6a0d-4324-8282-d41d439d3d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596353683 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2596353683
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.502700000
Short name T244
Test name
Test status
Simulation time 27516263 ps
CPU time 0.94 seconds
Started Mar 26 03:26:24 PM PDT 24
Finished Mar 26 03:26:25 PM PDT 24
Peak memory 207080 kb
Host smart-2c31a2e3-4960-41c5-bd80-f8db4255003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502700000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.502700000
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1623323249
Short name T683
Test name
Test status
Simulation time 15628141 ps
CPU time 0.99 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 207088 kb
Host smart-e81cae4e-8b39-49a4-b5f4-c25455a7d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623323249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1623323249
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2369072945
Short name T767
Test name
Test status
Simulation time 642686416 ps
CPU time 3.68 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 216612 kb
Host smart-07105d0c-d44f-4298-a8a6-8edf67bea421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369072945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2369072945
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2993946991
Short name T462
Test name
Test status
Simulation time 119365967827 ps
CPU time 555.77 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:35:37 PM PDT 24
Peak memory 219320 kb
Host smart-d5d316a0-cf0e-4580-a64c-a0bd76e098a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993946991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2993946991
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1624358966
Short name T7
Test name
Test status
Simulation time 30291128 ps
CPU time 0.98 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 219076 kb
Host smart-5614cabd-5890-4a1e-b86e-e9430c9dcb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624358966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1624358966
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2181559044
Short name T338
Test name
Test status
Simulation time 193729427 ps
CPU time 1.01 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 216412 kb
Host smart-74c76974-4ccc-47c6-b1a8-02cfb8237b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181559044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2181559044
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1602675325
Short name T390
Test name
Test status
Simulation time 20699761 ps
CPU time 0.96 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 217984 kb
Host smart-ec184e9f-baf5-40ad-8db3-44df1fd56620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602675325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1602675325
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1972168517
Short name T255
Test name
Test status
Simulation time 200015488 ps
CPU time 1.53 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 218376 kb
Host smart-0f2dfa08-048b-4c79-83e2-c40dac7ecb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972168517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1972168517
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2770303596
Short name T441
Test name
Test status
Simulation time 18912728 ps
CPU time 1.08 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:46 PM PDT 24
Peak memory 218008 kb
Host smart-6405a514-46c9-4906-9d40-017907280461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770303596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2770303596
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.764710521
Short name T400
Test name
Test status
Simulation time 46527533 ps
CPU time 1.71 seconds
Started Mar 26 03:27:32 PM PDT 24
Finished Mar 26 03:27:34 PM PDT 24
Peak memory 217848 kb
Host smart-967aff6a-74de-483d-ad9f-e3f385af067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764710521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.764710521
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.291788398
Short name T48
Test name
Test status
Simulation time 30590578 ps
CPU time 0.95 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 222860 kb
Host smart-ef0886f0-7bad-4867-8411-b991528a6327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291788398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.291788398
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2797602326
Short name T172
Test name
Test status
Simulation time 231151700 ps
CPU time 1.46 seconds
Started Mar 26 03:27:30 PM PDT 24
Finished Mar 26 03:27:32 PM PDT 24
Peak memory 217984 kb
Host smart-6d806891-b57d-489d-8b38-822a28ce16e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797602326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2797602326
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.319525598
Short name T103
Test name
Test status
Simulation time 24141709 ps
CPU time 0.99 seconds
Started Mar 26 03:27:53 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 218120 kb
Host smart-bcb62321-987b-4ed0-8926-e2d43fd55668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319525598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.319525598
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1877600845
Short name T763
Test name
Test status
Simulation time 71924189 ps
CPU time 1.12 seconds
Started Mar 26 03:27:30 PM PDT 24
Finished Mar 26 03:27:32 PM PDT 24
Peak memory 216696 kb
Host smart-48a0c7ab-f224-4db0-a5b6-b6bba6f81717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877600845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1877600845
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2441768653
Short name T792
Test name
Test status
Simulation time 63190452 ps
CPU time 1.07 seconds
Started Mar 26 03:27:57 PM PDT 24
Finished Mar 26 03:27:58 PM PDT 24
Peak memory 218068 kb
Host smart-ed35d2da-98b7-4619-ae71-245e5e791fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441768653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2441768653
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1560146659
Short name T761
Test name
Test status
Simulation time 47817201 ps
CPU time 1.52 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 217976 kb
Host smart-31dda63a-8011-42e4-9b65-e946f9e3cfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560146659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1560146659
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3694891893
Short name T718
Test name
Test status
Simulation time 32973070 ps
CPU time 1.43 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:43 PM PDT 24
Peak memory 233564 kb
Host smart-11305a6b-05c7-4dc9-8d83-ea7abd024693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694891893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3694891893
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2595259341
Short name T500
Test name
Test status
Simulation time 39304308 ps
CPU time 1.31 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 216640 kb
Host smart-bf7ac455-30bf-4f2f-9c40-3e5cb9e83151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595259341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2595259341
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3739995531
Short name T78
Test name
Test status
Simulation time 49192518 ps
CPU time 1.03 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 220160 kb
Host smart-2ce3b4d8-f91a-4202-bd43-de0841b50cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739995531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3739995531
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2432489732
Short name T325
Test name
Test status
Simulation time 27328597 ps
CPU time 1.35 seconds
Started Mar 26 03:27:32 PM PDT 24
Finished Mar 26 03:27:33 PM PDT 24
Peak memory 217776 kb
Host smart-fc23743f-de75-4261-a2ca-c6ee9cf81a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432489732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2432489732
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2344143710
Short name T296
Test name
Test status
Simulation time 51164886 ps
CPU time 0.97 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 218128 kb
Host smart-6224be79-9fa2-4ee6-9697-4c11da982a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344143710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2344143710
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2250135250
Short name T378
Test name
Test status
Simulation time 239524466 ps
CPU time 1.11 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 219132 kb
Host smart-cd2dd417-21a7-4a8c-b60d-7b1a44c51be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250135250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2250135250
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1042406394
Short name T484
Test name
Test status
Simulation time 20107956 ps
CPU time 1.08 seconds
Started Mar 26 03:27:34 PM PDT 24
Finished Mar 26 03:27:36 PM PDT 24
Peak memory 218124 kb
Host smart-4e642e1d-ef28-4c73-93c3-fa9d8b3b2863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042406394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1042406394
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3179889897
Short name T490
Test name
Test status
Simulation time 45708788 ps
CPU time 1.11 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 218056 kb
Host smart-e0eb3b6a-3c6e-48f8-9bf8-2159f7571410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179889897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3179889897
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2621598427
Short name T228
Test name
Test status
Simulation time 83366096 ps
CPU time 1.12 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 215656 kb
Host smart-76866f83-b0aa-469f-b0b7-582b14651b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621598427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2621598427
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3533188403
Short name T743
Test name
Test status
Simulation time 27116097 ps
CPU time 0.92 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:21 PM PDT 24
Peak memory 206512 kb
Host smart-ea6fe08c-aea9-4a2b-ae79-5191e5afd646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533188403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3533188403
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1382687785
Short name T64
Test name
Test status
Simulation time 94699843 ps
CPU time 1.14 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 216348 kb
Host smart-207f6d47-444e-49a3-882b-30219724d908
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382687785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1382687785
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2537607139
Short name T312
Test name
Test status
Simulation time 26747410 ps
CPU time 0.86 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:33 PM PDT 24
Peak memory 217520 kb
Host smart-2d2e6daa-398d-4ca4-88db-32d608894778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537607139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2537607139
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.620449425
Short name T282
Test name
Test status
Simulation time 97869350 ps
CPU time 1.3 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:26:23 PM PDT 24
Peak memory 218708 kb
Host smart-593eb7de-df45-4226-9d14-aac47c05c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620449425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.620449425
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1384208133
Short name T791
Test name
Test status
Simulation time 33300291 ps
CPU time 0.87 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215544 kb
Host smart-84ae877b-e999-49cc-81d1-1447b3b6a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384208133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1384208133
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.766335000
Short name T616
Test name
Test status
Simulation time 22063652 ps
CPU time 0.95 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 207120 kb
Host smart-38f39a50-dfdf-472a-a6f2-ff6a3976f900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766335000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.766335000
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.941946177
Short name T737
Test name
Test status
Simulation time 45201286 ps
CPU time 0.91 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 215308 kb
Host smart-5f222cb1-c365-4fe4-af99-049efa0abea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941946177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.941946177
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1641233683
Short name T731
Test name
Test status
Simulation time 178490357 ps
CPU time 1.87 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215312 kb
Host smart-8f520824-df24-4800-bc6c-7cf67bb4d039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641233683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1641233683
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3853074388
Short name T179
Test name
Test status
Simulation time 38206452651 ps
CPU time 490.37 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:34:41 PM PDT 24
Peak memory 218492 kb
Host smart-fa853771-809b-464e-8dbb-30188954c735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853074388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3853074388
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.4206842827
Short name T5
Test name
Test status
Simulation time 33476226 ps
CPU time 1.43 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 233644 kb
Host smart-c85cc894-d808-4cdd-8cb9-62420c2c6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206842827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.4206842827
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2373344932
Short name T373
Test name
Test status
Simulation time 47514120 ps
CPU time 1.67 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 218016 kb
Host smart-37c33873-7911-4303-9e75-aa84d635855e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373344932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2373344932
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2979662140
Short name T134
Test name
Test status
Simulation time 34806585 ps
CPU time 0.88 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 217744 kb
Host smart-f4c97159-bc99-4b33-8308-3e7f650de0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979662140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2979662140
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.3202910155
Short name T646
Test name
Test status
Simulation time 27851236 ps
CPU time 0.81 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 217500 kb
Host smart-55b977c9-180d-4701-b077-36f47ec0700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202910155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3202910155
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1817195777
Short name T547
Test name
Test status
Simulation time 51968121 ps
CPU time 1.38 seconds
Started Mar 26 03:27:34 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 217832 kb
Host smart-7b2913e9-aceb-4908-a085-1781ba8cbb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817195777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1817195777
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1461389469
Short name T157
Test name
Test status
Simulation time 21057006 ps
CPU time 1.19 seconds
Started Mar 26 03:27:31 PM PDT 24
Finished Mar 26 03:27:32 PM PDT 24
Peak memory 229728 kb
Host smart-5bd43903-2f47-4b40-ab8d-a24dfb1fdf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461389469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1461389469
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1209225991
Short name T202
Test name
Test status
Simulation time 36441607 ps
CPU time 1.3 seconds
Started Mar 26 03:27:34 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 217988 kb
Host smart-466d0053-c3ad-4132-adf1-3d0f3cf4a810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209225991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1209225991
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3426421292
Short name T298
Test name
Test status
Simulation time 19628457 ps
CPU time 1.05 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 218204 kb
Host smart-1d969f29-f93c-4b04-9ead-7b5a7630bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426421292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3426421292
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.951805281
Short name T467
Test name
Test status
Simulation time 56922188 ps
CPU time 1.37 seconds
Started Mar 26 03:27:31 PM PDT 24
Finished Mar 26 03:27:33 PM PDT 24
Peak memory 217756 kb
Host smart-d74bf60a-3573-4681-9d98-57e8b506b9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951805281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.951805281
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4128149896
Short name T675
Test name
Test status
Simulation time 26110463 ps
CPU time 0.92 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:43 PM PDT 24
Peak memory 218132 kb
Host smart-bf7959a5-856e-4c3f-9384-1a9b464476c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128149896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4128149896
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1097488652
Short name T562
Test name
Test status
Simulation time 54021065 ps
CPU time 1.2 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 218100 kb
Host smart-86eeff3f-b2fb-4c96-8d4b-8634a646d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097488652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1097488652
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3924443343
Short name T77
Test name
Test status
Simulation time 33744240 ps
CPU time 1.04 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 229768 kb
Host smart-2bb276c2-fe11-4ec5-86f3-6adc244f661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924443343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3924443343
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3738779978
Short name T258
Test name
Test status
Simulation time 65821721 ps
CPU time 1.36 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 218108 kb
Host smart-06be7994-4b06-4078-b640-4045c0a845ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738779978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3738779978
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.805851718
Short name T92
Test name
Test status
Simulation time 29326768 ps
CPU time 0.92 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:27:59 PM PDT 24
Peak memory 218032 kb
Host smart-bea74a38-9da0-47d6-af66-69c279fd2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805851718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.805851718
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.935623215
Short name T401
Test name
Test status
Simulation time 50057341 ps
CPU time 1.29 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 217640 kb
Host smart-bf68af79-5cf6-4706-b2ce-7d5fb4854457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935623215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.935623215
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.658477393
Short name T370
Test name
Test status
Simulation time 22390497 ps
CPU time 0.96 seconds
Started Mar 26 03:27:55 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 218160 kb
Host smart-3571f2c1-82c3-49e4-a269-b3e1888170d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658477393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.658477393
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.625994657
Short name T665
Test name
Test status
Simulation time 48702600 ps
CPU time 1.53 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 217824 kb
Host smart-c5a7bc38-c30f-4567-b5b8-27a2582d721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625994657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.625994657
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.476784967
Short name T291
Test name
Test status
Simulation time 30293861 ps
CPU time 0.86 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 217800 kb
Host smart-faab9e2c-5bc3-4b65-a53b-7c05f31786bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476784967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.476784967
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2963025967
Short name T779
Test name
Test status
Simulation time 50270051 ps
CPU time 1.33 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 218280 kb
Host smart-30525c7c-b5ab-49b0-a636-f09ed7edef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963025967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2963025967
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2754962313
Short name T170
Test name
Test status
Simulation time 135632743 ps
CPU time 1.33 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215572 kb
Host smart-385356e4-6007-47ee-bb03-56b9495c5449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754962313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2754962313
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3780575564
Short name T348
Test name
Test status
Simulation time 61200704 ps
CPU time 0.81 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:26:32 PM PDT 24
Peak memory 206584 kb
Host smart-f246c2a9-fd48-46ca-a67b-c061752c945b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780575564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3780575564
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3958904235
Short name T800
Test name
Test status
Simulation time 11232082 ps
CPU time 0.88 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215608 kb
Host smart-1f304ded-d5bc-4d20-bb6a-63cb8def7ff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958904235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3958904235
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2434481610
Short name T752
Test name
Test status
Simulation time 19134168 ps
CPU time 1.18 seconds
Started Mar 26 03:26:38 PM PDT 24
Finished Mar 26 03:26:40 PM PDT 24
Peak memory 232392 kb
Host smart-4a3c6116-a2ad-4e1b-b82e-8684cb75b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434481610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2434481610
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1463727563
Short name T310
Test name
Test status
Simulation time 53497567 ps
CPU time 1.43 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 218936 kb
Host smart-b9b3cad6-49c9-4fd9-930d-7b46d4a0140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463727563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1463727563
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1403636775
Short name T819
Test name
Test status
Simulation time 19796887 ps
CPU time 1.08 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 215736 kb
Host smart-3e85ef9f-e958-4093-b3b6-2a00ede02eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403636775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1403636775
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.2966291381
Short name T416
Test name
Test status
Simulation time 30244378 ps
CPU time 0.92 seconds
Started Mar 26 03:26:33 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 215276 kb
Host smart-1b48138c-e9b5-4f53-b3f6-58450fd74b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966291381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2966291381
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4293850942
Short name T414
Test name
Test status
Simulation time 538773078 ps
CPU time 6.15 seconds
Started Mar 26 03:26:20 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 215372 kb
Host smart-ffdab545-c495-456c-9c6e-528248882c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293850942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4293850942
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1565113819
Short name T356
Test name
Test status
Simulation time 253099589061 ps
CPU time 1872.08 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:57:38 PM PDT 24
Peak memory 227180 kb
Host smart-a90a3e60-862d-4e48-963b-b5bb5773303c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565113819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1565113819
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3044419304
Short name T582
Test name
Test status
Simulation time 18922095 ps
CPU time 1.04 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 217988 kb
Host smart-e8594dfa-eef1-4ff1-a806-89d4939b4bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044419304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3044419304
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4069494765
Short name T666
Test name
Test status
Simulation time 54508167 ps
CPU time 1.35 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:45 PM PDT 24
Peak memory 218108 kb
Host smart-70fafbec-7022-4d5e-945b-e9e5c30ce154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069494765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4069494765
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3209412640
Short name T404
Test name
Test status
Simulation time 19431366 ps
CPU time 1.02 seconds
Started Mar 26 03:27:44 PM PDT 24
Finished Mar 26 03:27:45 PM PDT 24
Peak memory 217972 kb
Host smart-db3b7286-1ae4-4695-ab32-6e00dc409b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209412640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3209412640
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1443331753
Short name T164
Test name
Test status
Simulation time 90350346 ps
CPU time 1.11 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:43 PM PDT 24
Peak memory 217652 kb
Host smart-a5bbec4f-e01a-4173-a02d-164d8f37f24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443331753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1443331753
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3526484984
Short name T481
Test name
Test status
Simulation time 20347839 ps
CPU time 1.09 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 219548 kb
Host smart-7c1ddc9f-b7ba-4fb3-a32e-dc6568727244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526484984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3526484984
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1065412719
Short name T260
Test name
Test status
Simulation time 36699859 ps
CPU time 1.28 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 216512 kb
Host smart-88a757ae-83b6-411b-a4f3-fcae0a24282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065412719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1065412719
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2334019878
Short name T97
Test name
Test status
Simulation time 34150549 ps
CPU time 0.99 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 232400 kb
Host smart-fccf22a8-f413-49ce-9d83-16486d124dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334019878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2334019878
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1714738245
Short name T316
Test name
Test status
Simulation time 46142261 ps
CPU time 1.23 seconds
Started Mar 26 03:27:26 PM PDT 24
Finished Mar 26 03:27:28 PM PDT 24
Peak memory 217920 kb
Host smart-8a052e54-587b-477a-870e-7c7168b31be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714738245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1714738245
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2172956179
Short name T101
Test name
Test status
Simulation time 20816948 ps
CPU time 0.9 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 218024 kb
Host smart-56894d60-21c9-4c12-aa1b-6b7df5f2bc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172956179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2172956179
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1738083338
Short name T198
Test name
Test status
Simulation time 74198935 ps
CPU time 1.47 seconds
Started Mar 26 03:27:53 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 217984 kb
Host smart-f5f36115-17bc-4079-a3f1-4e85298ac000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738083338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1738083338
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3497464065
Short name T66
Test name
Test status
Simulation time 39371868 ps
CPU time 1.11 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 216752 kb
Host smart-a40dba68-b509-4806-bf1c-b151ae48bc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497464065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3497464065
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2140740998
Short name T330
Test name
Test status
Simulation time 48918295 ps
CPU time 1.48 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:45 PM PDT 24
Peak memory 219104 kb
Host smart-c68565b3-34b9-41c7-b4b0-ae4af455b799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140740998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2140740998
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3790969352
Short name T590
Test name
Test status
Simulation time 34672544 ps
CPU time 0.95 seconds
Started Mar 26 03:27:41 PM PDT 24
Finished Mar 26 03:27:42 PM PDT 24
Peak memory 222940 kb
Host smart-e4e6b3e1-c308-4e44-9dbf-ffd7e7d69f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790969352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3790969352
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3403068148
Short name T532
Test name
Test status
Simulation time 60873642 ps
CPU time 1.2 seconds
Started Mar 26 03:27:47 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 215272 kb
Host smart-a4efef31-c5b4-495e-820a-98e758286008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403068148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3403068148
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.9275641
Short name T326
Test name
Test status
Simulation time 31958748 ps
CPU time 0.84 seconds
Started Mar 26 03:27:35 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 217740 kb
Host smart-fa3e5228-f500-4fd4-a24f-d396facc8e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9275641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.9275641
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2113823729
Short name T536
Test name
Test status
Simulation time 36686696 ps
CPU time 1.49 seconds
Started Mar 26 03:27:35 PM PDT 24
Finished Mar 26 03:27:37 PM PDT 24
Peak memory 218188 kb
Host smart-9d3f762e-6078-43e6-a898-3881a1988786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113823729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2113823729
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.641661118
Short name T712
Test name
Test status
Simulation time 28664660 ps
CPU time 0.84 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 217600 kb
Host smart-0acfc154-1d72-4fef-8cc9-26dd030cd61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641661118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.641661118
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2958264332
Short name T567
Test name
Test status
Simulation time 53020082 ps
CPU time 1.43 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 217736 kb
Host smart-7e5e3a23-9cd1-4b40-8e61-9179a9f3436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958264332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2958264332
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2419533901
Short name T144
Test name
Test status
Simulation time 23554475 ps
CPU time 0.98 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 218308 kb
Host smart-87f53a45-1167-409d-9061-102086511140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419533901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2419533901
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2940223133
Short name T389
Test name
Test status
Simulation time 279621717 ps
CPU time 1.04 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 216592 kb
Host smart-1f0f1e17-7a53-457c-989f-8e71117adad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940223133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2940223133
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1990607600
Short name T521
Test name
Test status
Simulation time 220847032 ps
CPU time 1.32 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 215636 kb
Host smart-996e6e09-3104-4c50-8568-6308bfa1fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990607600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1990607600
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3622966728
Short name T367
Test name
Test status
Simulation time 38442423 ps
CPU time 0.83 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 206332 kb
Host smart-4510ba41-2691-4f3a-909e-2f406d88552f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622966728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3622966728
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2467458161
Short name T315
Test name
Test status
Simulation time 31185970 ps
CPU time 0.86 seconds
Started Mar 26 03:26:57 PM PDT 24
Finished Mar 26 03:26:58 PM PDT 24
Peak memory 215476 kb
Host smart-5ce49960-328a-45a8-b964-bf67a4d2b0eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467458161 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2467458161
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.855713220
Short name T65
Test name
Test status
Simulation time 98179930 ps
CPU time 1.08 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 216424 kb
Host smart-8cc458d3-124f-4e35-a427-4364ea6ebdef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855713220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.855713220
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.690253605
Short name T351
Test name
Test status
Simulation time 34184539 ps
CPU time 0.98 seconds
Started Mar 26 03:26:33 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 218240 kb
Host smart-a468dc47-d415-4619-91d4-d153be2b4d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690253605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.690253605
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1358768485
Short name T396
Test name
Test status
Simulation time 50245096 ps
CPU time 1.65 seconds
Started Mar 26 03:26:32 PM PDT 24
Finished Mar 26 03:26:34 PM PDT 24
Peak memory 217760 kb
Host smart-3dbb66c0-ea14-4805-8ae9-23c7a36ee88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358768485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1358768485
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1619025412
Short name T546
Test name
Test status
Simulation time 22182455 ps
CPU time 0.92 seconds
Started Mar 26 03:26:27 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 215636 kb
Host smart-fef9c4a2-86f2-453d-bf7d-2a6b373ab495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619025412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1619025412
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.923727476
Short name T119
Test name
Test status
Simulation time 16873572 ps
CPU time 0.93 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 207068 kb
Host smart-4878ecfa-a290-4aa7-ba5f-9109119c2c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923727476 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.923727476
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1453797542
Short name T345
Test name
Test status
Simulation time 25073586 ps
CPU time 0.97 seconds
Started Mar 26 03:26:21 PM PDT 24
Finished Mar 26 03:26:22 PM PDT 24
Peak memory 215252 kb
Host smart-93a63f64-03a0-4e5e-930a-5753c70100c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453797542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1453797542
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.214448788
Short name T194
Test name
Test status
Simulation time 361422150 ps
CPU time 6.81 seconds
Started Mar 26 03:26:23 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 215272 kb
Host smart-ba784c29-0d84-4028-a15a-7c3f47485e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214448788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.214448788
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3923901051
Short name T549
Test name
Test status
Simulation time 101491615650 ps
CPU time 2756.62 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 04:12:27 PM PDT 24
Peak memory 232240 kb
Host smart-b3e9a05a-32ee-4552-b82b-ebe7297319ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923901051 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3923901051
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2062096800
Short name T59
Test name
Test status
Simulation time 38095321 ps
CPU time 1.11 seconds
Started Mar 26 03:27:50 PM PDT 24
Finished Mar 26 03:27:51 PM PDT 24
Peak memory 219260 kb
Host smart-4157eb38-f3a0-479e-a345-60543e1fd761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062096800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2062096800
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.396207685
Short name T199
Test name
Test status
Simulation time 62864979 ps
CPU time 1.32 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 219232 kb
Host smart-b6bdad60-0a85-4ea0-bff9-81c2aa735e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396207685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.396207685
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.908010546
Short name T746
Test name
Test status
Simulation time 18227197 ps
CPU time 1.09 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 217920 kb
Host smart-1c0f4de0-525d-42b2-9dea-37d6f2148234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908010546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.908010546
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.798589388
Short name T663
Test name
Test status
Simulation time 90425254 ps
CPU time 1.45 seconds
Started Mar 26 03:27:38 PM PDT 24
Finished Mar 26 03:27:39 PM PDT 24
Peak memory 218156 kb
Host smart-8e22b589-3212-4409-b53d-306a37e8bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798589388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.798589388
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3690877614
Short name T71
Test name
Test status
Simulation time 19173164 ps
CPU time 1.11 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 218088 kb
Host smart-14880def-014d-4c52-af78-c26dd3cb326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690877614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3690877614
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1827000833
Short name T36
Test name
Test status
Simulation time 53959675 ps
CPU time 1.67 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 217792 kb
Host smart-2861b23d-35bf-439a-80a0-0a89d4c598a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827000833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1827000833
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.140033973
Short name T393
Test name
Test status
Simulation time 48171067 ps
CPU time 0.96 seconds
Started Mar 26 03:27:42 PM PDT 24
Finished Mar 26 03:27:43 PM PDT 24
Peak memory 218104 kb
Host smart-8d63a74f-e3f2-4c69-9aed-48bbfc2e3efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140033973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.140033973
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1837803727
Short name T594
Test name
Test status
Simulation time 66337117 ps
CPU time 1.59 seconds
Started Mar 26 03:27:33 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 218220 kb
Host smart-aedb8ebd-6204-4ed0-b5d9-f5691d7efec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837803727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1837803727
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1851282745
Short name T349
Test name
Test status
Simulation time 18716367 ps
CPU time 1.06 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 217808 kb
Host smart-5c6b6b39-ae53-43cc-b88b-ecf9cda14fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851282745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1851282745
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.517097107
Short name T491
Test name
Test status
Simulation time 67869558 ps
CPU time 1.1 seconds
Started Mar 26 03:27:43 PM PDT 24
Finished Mar 26 03:27:45 PM PDT 24
Peak memory 216548 kb
Host smart-fba5da9e-271b-4f80-ad89-c5d7a65d792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517097107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.517097107
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1332060610
Short name T411
Test name
Test status
Simulation time 31310631 ps
CPU time 1.02 seconds
Started Mar 26 03:27:30 PM PDT 24
Finished Mar 26 03:27:32 PM PDT 24
Peak memory 219380 kb
Host smart-dcb1f22f-3d87-4037-a693-3949e5624f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332060610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1332060610
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2751518976
Short name T256
Test name
Test status
Simulation time 72932385 ps
CPU time 1.17 seconds
Started Mar 26 03:27:52 PM PDT 24
Finished Mar 26 03:27:54 PM PDT 24
Peak memory 217904 kb
Host smart-896f3e86-e131-40ed-be47-c86bf0711787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751518976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2751518976
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1168726630
Short name T51
Test name
Test status
Simulation time 40164573 ps
CPU time 0.83 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:52 PM PDT 24
Peak memory 217996 kb
Host smart-c440f612-3a4d-4457-adf5-33ef5775884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168726630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1168726630
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.958617610
Short name T647
Test name
Test status
Simulation time 108868844 ps
CPU time 1.34 seconds
Started Mar 26 03:27:34 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 218272 kb
Host smart-27d07b8f-a4b3-4762-a3fc-940b25dc7e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958617610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.958617610
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1641035336
Short name T76
Test name
Test status
Simulation time 31230453 ps
CPU time 1.16 seconds
Started Mar 26 03:27:55 PM PDT 24
Finished Mar 26 03:27:56 PM PDT 24
Peak memory 229768 kb
Host smart-6df85574-16ff-465d-bb4b-9243f05b62d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641035336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1641035336
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2179678924
Short name T577
Test name
Test status
Simulation time 45092569 ps
CPU time 1.49 seconds
Started Mar 26 03:27:49 PM PDT 24
Finished Mar 26 03:27:50 PM PDT 24
Peak memory 217852 kb
Host smart-62f6c94c-8b39-4851-8e8f-889818ae7632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179678924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2179678924
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_genbits.977373179
Short name T787
Test name
Test status
Simulation time 43631761 ps
CPU time 1.35 seconds
Started Mar 26 03:27:51 PM PDT 24
Finished Mar 26 03:27:53 PM PDT 24
Peak memory 218004 kb
Host smart-fc5793d2-4b7b-49cc-92f4-9e1f2ccaaf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977373179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.977373179
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2345299731
Short name T162
Test name
Test status
Simulation time 29921211 ps
CPU time 0.93 seconds
Started Mar 26 03:27:46 PM PDT 24
Finished Mar 26 03:27:47 PM PDT 24
Peak memory 216852 kb
Host smart-5bec08f8-37a0-46c4-9aeb-e47c6714b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345299731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2345299731
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2143597259
Short name T24
Test name
Test status
Simulation time 73608660 ps
CPU time 1.14 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:35 PM PDT 24
Peak memory 217972 kb
Host smart-32a5391e-b5dc-45e6-b83e-fd5f5085dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143597259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2143597259
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1442500632
Short name T708
Test name
Test status
Simulation time 251573357 ps
CPU time 1.32 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215640 kb
Host smart-97646b6f-7cd1-456c-8662-a34ae80dc89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442500632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1442500632
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2546280997
Short name T672
Test name
Test status
Simulation time 14942646 ps
CPU time 0.9 seconds
Started Mar 26 03:26:29 PM PDT 24
Finished Mar 26 03:26:30 PM PDT 24
Peak memory 205928 kb
Host smart-acd755b8-1332-4cfe-aafa-e223ddb2097f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546280997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2546280997
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.469034421
Short name T584
Test name
Test status
Simulation time 106122439 ps
CPU time 0.78 seconds
Started Mar 26 03:26:26 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 215524 kb
Host smart-57fd3a7d-eab8-4480-8d7b-6becdad5047f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469034421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.469034421
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1089990521
Short name T69
Test name
Test status
Simulation time 27685395 ps
CPU time 0.98 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 217692 kb
Host smart-111d1ed7-34a8-4880-bcf8-cb926443a79c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089990521 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1089990521
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_genbits.1517052913
Short name T671
Test name
Test status
Simulation time 36110913 ps
CPU time 1.3 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:27 PM PDT 24
Peak memory 219208 kb
Host smart-5a155e0f-5606-4720-9461-5e14564de682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517052913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1517052913
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2038216187
Short name T612
Test name
Test status
Simulation time 35446417 ps
CPU time 0.87 seconds
Started Mar 26 03:26:30 PM PDT 24
Finished Mar 26 03:26:31 PM PDT 24
Peak memory 215476 kb
Host smart-c9164c25-30d0-413b-90e1-d571757cd355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038216187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2038216187
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2911271773
Short name T121
Test name
Test status
Simulation time 55828415 ps
CPU time 0.96 seconds
Started Mar 26 03:26:28 PM PDT 24
Finished Mar 26 03:26:29 PM PDT 24
Peak memory 207044 kb
Host smart-c2f33477-9572-4a06-b83f-dbd2141c37cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911271773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2911271773
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.228176294
Short name T523
Test name
Test status
Simulation time 16469885 ps
CPU time 0.97 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:26 PM PDT 24
Peak memory 215252 kb
Host smart-cb782a8a-16f4-4034-8e41-01af8f94d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228176294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.228176294
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1402953577
Short name T270
Test name
Test status
Simulation time 715198122 ps
CPU time 2.33 seconds
Started Mar 26 03:26:25 PM PDT 24
Finished Mar 26 03:26:28 PM PDT 24
Peak memory 216712 kb
Host smart-981235c4-57ad-4289-a276-828e6b7c6385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402953577 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1402953577
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4145717560
Short name T428
Test name
Test status
Simulation time 34417953692 ps
CPU time 799.73 seconds
Started Mar 26 03:26:31 PM PDT 24
Finished Mar 26 03:39:51 PM PDT 24
Peak memory 217912 kb
Host smart-426b24ae-7136-4da8-bc68-5fae86b7943b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145717560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4145717560
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1521017030
Short name T597
Test name
Test status
Simulation time 58824012 ps
CPU time 1.03 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 220308 kb
Host smart-534c17ee-d90f-45ee-a4cf-5da14fbcb65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521017030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1521017030
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3640692654
Short name T307
Test name
Test status
Simulation time 287623712 ps
CPU time 2.37 seconds
Started Mar 26 03:27:27 PM PDT 24
Finished Mar 26 03:27:30 PM PDT 24
Peak memory 219192 kb
Host smart-e9818c0e-e471-4eaa-affe-57f7e34e50f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640692654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3640692654
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.61866735
Short name T611
Test name
Test status
Simulation time 32719137 ps
CPU time 1.2 seconds
Started Mar 26 03:27:56 PM PDT 24
Finished Mar 26 03:27:57 PM PDT 24
Peak memory 218980 kb
Host smart-c4c493c1-49db-4655-b001-3a6e571bb288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61866735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.61866735
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3178071861
Short name T419
Test name
Test status
Simulation time 66755052 ps
CPU time 1.32 seconds
Started Mar 26 03:27:48 PM PDT 24
Finished Mar 26 03:27:49 PM PDT 24
Peak memory 216452 kb
Host smart-286c5458-e5e0-4a6c-afd4-fab1618fa8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178071861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3178071861
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2472832035
Short name T14
Test name
Test status
Simulation time 17962216 ps
CPU time 1.17 seconds
Started Mar 26 03:28:00 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 223076 kb
Host smart-95696900-ac72-4bdf-ac26-a4289c272380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472832035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2472832035
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.776055039
Short name T640
Test name
Test status
Simulation time 70556782 ps
CPU time 1.05 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 216716 kb
Host smart-372738b6-a7dd-4847-b78d-68209f7430d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776055039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.776055039
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.488130520
Short name T153
Test name
Test status
Simulation time 20635438 ps
CPU time 1.02 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 231280 kb
Host smart-d8d79700-8b00-4878-a348-5137e959f6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488130520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.488130520
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.586761726
Short name T498
Test name
Test status
Simulation time 117491850 ps
CPU time 1.69 seconds
Started Mar 26 03:27:29 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 218628 kb
Host smart-c83eb763-8c20-486c-a07c-a6a0d16e1069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586761726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.586761726
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2837529940
Short name T812
Test name
Test status
Simulation time 24349981 ps
CPU time 1.15 seconds
Started Mar 26 03:27:54 PM PDT 24
Finished Mar 26 03:27:55 PM PDT 24
Peak memory 218052 kb
Host smart-e93ba62a-e1e4-4209-a1eb-6845d7389261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837529940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2837529940
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.542527826
Short name T471
Test name
Test status
Simulation time 244206746 ps
CPU time 1.12 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:00 PM PDT 24
Peak memory 216560 kb
Host smart-2a2e58a1-cb08-4c9a-9950-d843b0f0e7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542527826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.542527826
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2138430412
Short name T644
Test name
Test status
Simulation time 51656264 ps
CPU time 1.11 seconds
Started Mar 26 03:27:35 PM PDT 24
Finished Mar 26 03:27:36 PM PDT 24
Peak memory 231360 kb
Host smart-564fd90f-9752-476d-888d-bde5c442d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138430412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2138430412
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2540394728
Short name T707
Test name
Test status
Simulation time 30067547 ps
CPU time 1.44 seconds
Started Mar 26 03:27:45 PM PDT 24
Finished Mar 26 03:27:46 PM PDT 24
Peak memory 216788 kb
Host smart-568818e4-6da6-42da-bbf0-2939939b3a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540394728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2540394728
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1986137169
Short name T67
Test name
Test status
Simulation time 21111565 ps
CPU time 1.08 seconds
Started Mar 26 03:27:31 PM PDT 24
Finished Mar 26 03:27:32 PM PDT 24
Peak memory 219460 kb
Host smart-9f36c642-e322-476d-b1c6-2782e5672a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986137169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1986137169
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3022886933
Short name T614
Test name
Test status
Simulation time 38556403 ps
CPU time 1.69 seconds
Started Mar 26 03:27:59 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 217872 kb
Host smart-bdbf40b2-7194-4f4c-ab92-404da79cda09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022886933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3022886933
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.603642215
Short name T835
Test name
Test status
Simulation time 33355229 ps
CPU time 0.93 seconds
Started Mar 26 03:27:35 PM PDT 24
Finished Mar 26 03:27:36 PM PDT 24
Peak memory 219520 kb
Host smart-39934f3e-7bfa-401c-ba64-670c65d56921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603642215 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.603642215
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2500867695
Short name T53
Test name
Test status
Simulation time 137045451 ps
CPU time 2.81 seconds
Started Mar 26 03:27:58 PM PDT 24
Finished Mar 26 03:28:01 PM PDT 24
Peak memory 217768 kb
Host smart-b1132d2b-78b0-4772-99ad-a760e1873191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500867695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2500867695
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.190056090
Short name T42
Test name
Test status
Simulation time 32375572 ps
CPU time 0.94 seconds
Started Mar 26 03:27:30 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 231096 kb
Host smart-57930275-e0ad-4e4c-aae5-f7ca93ee8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190056090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.190056090
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1097371451
Short name T465
Test name
Test status
Simulation time 873834629 ps
CPU time 7.54 seconds
Started Mar 26 03:27:36 PM PDT 24
Finished Mar 26 03:27:44 PM PDT 24
Peak memory 218144 kb
Host smart-43a4821d-dbe7-4ae2-a43f-6ac527ea423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097371451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1097371451
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1839601091
Short name T6
Test name
Test status
Simulation time 25318128 ps
CPU time 1.01 seconds
Started Mar 26 03:27:30 PM PDT 24
Finished Mar 26 03:27:31 PM PDT 24
Peak memory 219168 kb
Host smart-13b5a5e7-d50c-4660-855b-dc8997c512cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839601091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1839601091
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2319311737
Short name T535
Test name
Test status
Simulation time 34341063 ps
CPU time 1.21 seconds
Started Mar 26 03:27:28 PM PDT 24
Finished Mar 26 03:27:29 PM PDT 24
Peak memory 218856 kb
Host smart-95e14e0e-6168-4303-bba9-c4ffc592571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319311737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2319311737
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%