Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.88 98.27 93.64 96.79 82.08 96.87 96.58 92.95


Total test records in report: 973
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T784 /workspace/coverage/default/49.edn_alert.3023529829 Mar 28 01:31:45 PM PDT 24 Mar 28 01:31:47 PM PDT 24 64158579 ps
T785 /workspace/coverage/default/9.edn_intr.272778463 Mar 28 01:30:17 PM PDT 24 Mar 28 01:30:18 PM PDT 24 32088525 ps
T786 /workspace/coverage/default/28.edn_genbits.2782724391 Mar 28 01:30:55 PM PDT 24 Mar 28 01:30:58 PM PDT 24 66256559 ps
T787 /workspace/coverage/default/294.edn_genbits.3278977283 Mar 28 01:32:28 PM PDT 24 Mar 28 01:32:29 PM PDT 24 32183477 ps
T788 /workspace/coverage/default/39.edn_err.2274473774 Mar 28 01:31:10 PM PDT 24 Mar 28 01:31:11 PM PDT 24 30274926 ps
T163 /workspace/coverage/default/71.edn_err.1548180004 Mar 28 01:31:41 PM PDT 24 Mar 28 01:31:42 PM PDT 24 31212378 ps
T789 /workspace/coverage/default/5.edn_genbits.1568145429 Mar 28 01:30:13 PM PDT 24 Mar 28 01:30:15 PM PDT 24 30175119 ps
T790 /workspace/coverage/default/18.edn_stress_all.1573839295 Mar 28 01:30:40 PM PDT 24 Mar 28 01:30:43 PM PDT 24 1240830458 ps
T791 /workspace/coverage/default/124.edn_genbits.2985812507 Mar 28 01:32:02 PM PDT 24 Mar 28 01:32:04 PM PDT 24 41882766 ps
T792 /workspace/coverage/default/68.edn_genbits.4159394931 Mar 28 01:31:42 PM PDT 24 Mar 28 01:31:43 PM PDT 24 38283788 ps
T793 /workspace/coverage/default/133.edn_genbits.3454496143 Mar 28 01:31:57 PM PDT 24 Mar 28 01:31:59 PM PDT 24 56692680 ps
T794 /workspace/coverage/default/12.edn_alert_test.3451124378 Mar 28 01:30:34 PM PDT 24 Mar 28 01:30:35 PM PDT 24 35238859 ps
T795 /workspace/coverage/default/32.edn_intr.652191162 Mar 28 01:30:54 PM PDT 24 Mar 28 01:30:55 PM PDT 24 69594193 ps
T796 /workspace/coverage/default/54.edn_err.415808359 Mar 28 01:31:43 PM PDT 24 Mar 28 01:31:44 PM PDT 24 27914382 ps
T797 /workspace/coverage/default/63.edn_genbits.971449836 Mar 28 01:31:49 PM PDT 24 Mar 28 01:31:51 PM PDT 24 57597239 ps
T798 /workspace/coverage/default/66.edn_err.3820663999 Mar 28 01:31:41 PM PDT 24 Mar 28 01:31:42 PM PDT 24 25889920 ps
T799 /workspace/coverage/default/125.edn_genbits.4133396449 Mar 28 01:32:01 PM PDT 24 Mar 28 01:32:02 PM PDT 24 50526081 ps
T800 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.659743442 Mar 28 01:30:54 PM PDT 24 Mar 28 01:42:57 PM PDT 24 46394404214 ps
T801 /workspace/coverage/default/83.edn_err.1047768438 Mar 28 01:31:46 PM PDT 24 Mar 28 01:31:47 PM PDT 24 37590173 ps
T802 /workspace/coverage/default/154.edn_genbits.1080013887 Mar 28 01:32:05 PM PDT 24 Mar 28 01:32:07 PM PDT 24 278891946 ps
T803 /workspace/coverage/default/13.edn_intr.1394567994 Mar 28 01:30:34 PM PDT 24 Mar 28 01:30:35 PM PDT 24 41189125 ps
T804 /workspace/coverage/default/3.edn_stress_all.730891140 Mar 28 01:30:01 PM PDT 24 Mar 28 01:30:02 PM PDT 24 164260284 ps
T805 /workspace/coverage/default/78.edn_err.2386774269 Mar 28 01:31:46 PM PDT 24 Mar 28 01:31:47 PM PDT 24 60172640 ps
T806 /workspace/coverage/default/10.edn_alert_test.3338236310 Mar 28 01:30:37 PM PDT 24 Mar 28 01:30:38 PM PDT 24 47494215 ps
T807 /workspace/coverage/default/9.edn_genbits.717792849 Mar 28 01:30:18 PM PDT 24 Mar 28 01:30:21 PM PDT 24 197643475 ps
T808 /workspace/coverage/default/286.edn_genbits.3252761944 Mar 28 01:32:17 PM PDT 24 Mar 28 01:32:19 PM PDT 24 63003090 ps
T809 /workspace/coverage/default/195.edn_genbits.2226666015 Mar 28 01:32:05 PM PDT 24 Mar 28 01:32:07 PM PDT 24 78949471 ps
T810 /workspace/coverage/default/32.edn_genbits.1877579628 Mar 28 01:30:54 PM PDT 24 Mar 28 01:30:56 PM PDT 24 50237505 ps
T811 /workspace/coverage/default/36.edn_stress_all.2945388912 Mar 28 01:31:06 PM PDT 24 Mar 28 01:31:12 PM PDT 24 285080812 ps
T812 /workspace/coverage/default/42.edn_alert.858005113 Mar 28 01:31:17 PM PDT 24 Mar 28 01:31:18 PM PDT 24 71504826 ps
T813 /workspace/coverage/default/25.edn_disable.4267765446 Mar 28 01:30:58 PM PDT 24 Mar 28 01:30:59 PM PDT 24 20531008 ps
T814 /workspace/coverage/default/298.edn_genbits.1300387231 Mar 28 01:32:17 PM PDT 24 Mar 28 01:32:18 PM PDT 24 27604026 ps
T815 /workspace/coverage/default/254.edn_genbits.2780830226 Mar 28 01:32:08 PM PDT 24 Mar 28 01:32:10 PM PDT 24 83861785 ps
T816 /workspace/coverage/default/99.edn_err.4159941841 Mar 28 01:32:01 PM PDT 24 Mar 28 01:32:02 PM PDT 24 30654147 ps
T817 /workspace/coverage/default/163.edn_genbits.2628522749 Mar 28 01:32:06 PM PDT 24 Mar 28 01:32:08 PM PDT 24 42863964 ps
T818 /workspace/coverage/default/35.edn_stress_all.344504085 Mar 28 01:30:53 PM PDT 24 Mar 28 01:30:58 PM PDT 24 653128135 ps
T819 /workspace/coverage/default/29.edn_genbits.1051215589 Mar 28 01:30:54 PM PDT 24 Mar 28 01:30:56 PM PDT 24 55783942 ps
T820 /workspace/coverage/default/278.edn_genbits.1411923729 Mar 28 01:32:18 PM PDT 24 Mar 28 01:32:20 PM PDT 24 83122667 ps
T821 /workspace/coverage/default/33.edn_disable_auto_req_mode.2417408404 Mar 28 01:30:55 PM PDT 24 Mar 28 01:30:56 PM PDT 24 120271685 ps
T822 /workspace/coverage/default/19.edn_stress_all.707131359 Mar 28 01:30:39 PM PDT 24 Mar 28 01:30:41 PM PDT 24 127986523 ps
T823 /workspace/coverage/default/234.edn_genbits.2750605639 Mar 28 01:32:06 PM PDT 24 Mar 28 01:32:08 PM PDT 24 51187630 ps
T824 /workspace/coverage/default/36.edn_alert.621631840 Mar 28 01:31:09 PM PDT 24 Mar 28 01:31:10 PM PDT 24 137649534 ps
T825 /workspace/coverage/default/33.edn_genbits.1865932931 Mar 28 01:30:53 PM PDT 24 Mar 28 01:30:55 PM PDT 24 55713874 ps
T826 /workspace/coverage/default/78.edn_genbits.1308719295 Mar 28 01:31:50 PM PDT 24 Mar 28 01:31:52 PM PDT 24 92213898 ps
T827 /workspace/coverage/default/14.edn_err.419040234 Mar 28 01:30:38 PM PDT 24 Mar 28 01:30:40 PM PDT 24 45184807 ps
T828 /workspace/coverage/default/16.edn_err.126766813 Mar 28 01:30:38 PM PDT 24 Mar 28 01:30:39 PM PDT 24 67059999 ps
T829 /workspace/coverage/default/265.edn_genbits.183820890 Mar 28 01:32:15 PM PDT 24 Mar 28 01:32:16 PM PDT 24 48005336 ps
T830 /workspace/coverage/default/237.edn_genbits.999561393 Mar 28 01:32:14 PM PDT 24 Mar 28 01:32:16 PM PDT 24 49056113 ps
T831 /workspace/coverage/default/18.edn_disable.679715039 Mar 28 01:30:39 PM PDT 24 Mar 28 01:30:41 PM PDT 24 10893820 ps
T45 /workspace/coverage/default/4.edn_sec_cm.2420612965 Mar 28 01:30:12 PM PDT 24 Mar 28 01:30:18 PM PDT 24 1216291783 ps
T832 /workspace/coverage/default/52.edn_genbits.3234536162 Mar 28 01:31:44 PM PDT 24 Mar 28 01:31:45 PM PDT 24 25650229 ps
T833 /workspace/coverage/default/134.edn_genbits.385752159 Mar 28 01:32:03 PM PDT 24 Mar 28 01:32:06 PM PDT 24 44237498 ps
T834 /workspace/coverage/default/31.edn_smoke.999867065 Mar 28 01:30:59 PM PDT 24 Mar 28 01:31:01 PM PDT 24 18482996 ps
T835 /workspace/coverage/default/44.edn_alert_test.4163085328 Mar 28 01:31:07 PM PDT 24 Mar 28 01:31:08 PM PDT 24 11647699 ps
T836 /workspace/coverage/default/245.edn_genbits.298571389 Mar 28 01:32:15 PM PDT 24 Mar 28 01:32:16 PM PDT 24 38992807 ps
T837 /workspace/coverage/default/8.edn_disable_auto_req_mode.631246581 Mar 28 01:30:16 PM PDT 24 Mar 28 01:30:17 PM PDT 24 28341767 ps
T838 /workspace/coverage/default/12.edn_err.637937310 Mar 28 01:30:39 PM PDT 24 Mar 28 01:30:41 PM PDT 24 20811281 ps
T839 /workspace/coverage/default/238.edn_genbits.3842595232 Mar 28 01:32:05 PM PDT 24 Mar 28 01:32:10 PM PDT 24 325881708 ps
T840 /workspace/coverage/cover_reg_top/29.edn_intr_test.956877417 Mar 28 12:41:52 PM PDT 24 Mar 28 12:41:55 PM PDT 24 23034819 ps
T201 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2848153012 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:46 PM PDT 24 43466814 ps
T841 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1872558576 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:48 PM PDT 24 33092803 ps
T202 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3078383038 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 17070965 ps
T842 /workspace/coverage/cover_reg_top/34.edn_intr_test.936959291 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:49 PM PDT 24 13757835 ps
T843 /workspace/coverage/cover_reg_top/39.edn_intr_test.3574817926 Mar 28 12:41:49 PM PDT 24 Mar 28 12:41:50 PM PDT 24 12019537 ps
T203 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2326336622 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:42 PM PDT 24 45596750 ps
T204 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1461217524 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:47 PM PDT 24 17620780 ps
T844 /workspace/coverage/cover_reg_top/16.edn_intr_test.2827998870 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 63278726 ps
T224 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3453317768 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:49 PM PDT 24 473160401 ps
T225 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2860704904 Mar 28 12:41:32 PM PDT 24 Mar 28 12:41:36 PM PDT 24 337667855 ps
T845 /workspace/coverage/cover_reg_top/1.edn_intr_test.1536849 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:38 PM PDT 24 17376244 ps
T846 /workspace/coverage/cover_reg_top/12.edn_tl_errors.747520146 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:47 PM PDT 24 42425056 ps
T847 /workspace/coverage/cover_reg_top/25.edn_intr_test.2095617297 Mar 28 12:41:51 PM PDT 24 Mar 28 12:41:55 PM PDT 24 31775742 ps
T221 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2932798576 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:46 PM PDT 24 30807545 ps
T848 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1222118593 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 84797122 ps
T226 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2863864265 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 194164175 ps
T849 /workspace/coverage/cover_reg_top/27.edn_intr_test.3161237719 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:47 PM PDT 24 13232283 ps
T234 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2891904064 Mar 28 12:41:33 PM PDT 24 Mar 28 12:41:34 PM PDT 24 78949494 ps
T850 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2046180074 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 78436304 ps
T851 /workspace/coverage/cover_reg_top/14.edn_tl_errors.672877580 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:49 PM PDT 24 45427418 ps
T235 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2575918468 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:43 PM PDT 24 453289630 ps
T852 /workspace/coverage/cover_reg_top/9.edn_intr_test.3142481027 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 13234331 ps
T853 /workspace/coverage/cover_reg_top/37.edn_intr_test.4098914709 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:47 PM PDT 24 12387108 ps
T236 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2550094727 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:48 PM PDT 24 75605415 ps
T854 /workspace/coverage/cover_reg_top/48.edn_intr_test.1205582291 Mar 28 12:42:04 PM PDT 24 Mar 28 12:42:05 PM PDT 24 15634794 ps
T237 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.619613935 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 587509989 ps
T855 /workspace/coverage/cover_reg_top/40.edn_intr_test.868675524 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:48 PM PDT 24 36846143 ps
T856 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2002260553 Mar 28 12:41:23 PM PDT 24 Mar 28 12:41:24 PM PDT 24 44922913 ps
T222 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4108021115 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:43 PM PDT 24 121038806 ps
T205 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2362445919 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 26830302 ps
T206 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2250323503 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 12567478 ps
T857 /workspace/coverage/cover_reg_top/4.edn_intr_test.253074249 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 20466642 ps
T858 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2598088266 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:45 PM PDT 24 134139888 ps
T859 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1551583172 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 91135577 ps
T860 /workspace/coverage/cover_reg_top/28.edn_intr_test.3074056096 Mar 28 12:42:07 PM PDT 24 Mar 28 12:42:09 PM PDT 24 28091619 ps
T861 /workspace/coverage/cover_reg_top/7.edn_intr_test.270202945 Mar 28 12:41:39 PM PDT 24 Mar 28 12:41:40 PM PDT 24 21318388 ps
T862 /workspace/coverage/cover_reg_top/6.edn_tl_errors.4174384070 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:45 PM PDT 24 554421545 ps
T863 /workspace/coverage/cover_reg_top/43.edn_intr_test.3993125021 Mar 28 12:41:53 PM PDT 24 Mar 28 12:41:57 PM PDT 24 16604899 ps
T207 /workspace/coverage/cover_reg_top/7.edn_csr_rw.423701668 Mar 28 12:41:31 PM PDT 24 Mar 28 12:41:32 PM PDT 24 13900055 ps
T864 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3983800144 Mar 28 12:41:55 PM PDT 24 Mar 28 12:41:57 PM PDT 24 85244665 ps
T865 /workspace/coverage/cover_reg_top/35.edn_intr_test.1287875066 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:48 PM PDT 24 14450502 ps
T208 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2227691267 Mar 28 12:41:39 PM PDT 24 Mar 28 12:41:41 PM PDT 24 36024784 ps
T866 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2655850097 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:43 PM PDT 24 215517264 ps
T867 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3983785047 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:43 PM PDT 24 25028262 ps
T209 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3241877350 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:46 PM PDT 24 13589024 ps
T868 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1573866267 Mar 28 12:41:31 PM PDT 24 Mar 28 12:41:32 PM PDT 24 31432343 ps
T869 /workspace/coverage/cover_reg_top/13.edn_intr_test.2982767708 Mar 28 12:41:57 PM PDT 24 Mar 28 12:41:58 PM PDT 24 17549436 ps
T870 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.316969260 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:43 PM PDT 24 171177592 ps
T871 /workspace/coverage/cover_reg_top/0.edn_tl_errors.509642958 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:53 PM PDT 24 1163394956 ps
T872 /workspace/coverage/cover_reg_top/17.edn_csr_rw.949474694 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 50555960 ps
T873 /workspace/coverage/cover_reg_top/19.edn_intr_test.3368392720 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:49 PM PDT 24 109412303 ps
T874 /workspace/coverage/cover_reg_top/3.edn_intr_test.1547853342 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 41689599 ps
T875 /workspace/coverage/cover_reg_top/2.edn_tl_errors.684297118 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:41 PM PDT 24 76405676 ps
T210 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2696699677 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:48 PM PDT 24 250437824 ps
T876 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2408672847 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:50 PM PDT 24 90174271 ps
T223 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4280006476 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:47 PM PDT 24 31307653 ps
T877 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.67528075 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:43 PM PDT 24 38273670 ps
T878 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2918013242 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 20564904 ps
T879 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1884715396 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:45 PM PDT 24 147687869 ps
T211 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3997632197 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 96843894 ps
T238 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.655526296 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:48 PM PDT 24 245434062 ps
T880 /workspace/coverage/cover_reg_top/26.edn_intr_test.3958399659 Mar 28 12:42:08 PM PDT 24 Mar 28 12:42:09 PM PDT 24 23529960 ps
T881 /workspace/coverage/cover_reg_top/42.edn_intr_test.367255851 Mar 28 12:42:09 PM PDT 24 Mar 28 12:42:10 PM PDT 24 12198627 ps
T882 /workspace/coverage/cover_reg_top/23.edn_intr_test.527717898 Mar 28 12:42:07 PM PDT 24 Mar 28 12:42:08 PM PDT 24 15233670 ps
T883 /workspace/coverage/cover_reg_top/9.edn_tl_errors.4070021563 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:44 PM PDT 24 81692586 ps
T884 /workspace/coverage/cover_reg_top/17.edn_intr_test.1317724020 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 14463663 ps
T885 /workspace/coverage/cover_reg_top/10.edn_intr_test.4256014192 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:43 PM PDT 24 17671702 ps
T886 /workspace/coverage/cover_reg_top/12.edn_intr_test.1020495347 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 38446724 ps
T212 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1111651423 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:48 PM PDT 24 45498862 ps
T887 /workspace/coverage/cover_reg_top/15.edn_intr_test.1448939216 Mar 28 12:41:36 PM PDT 24 Mar 28 12:41:37 PM PDT 24 20922656 ps
T888 /workspace/coverage/cover_reg_top/32.edn_intr_test.4237501674 Mar 28 12:41:51 PM PDT 24 Mar 28 12:41:55 PM PDT 24 13022571 ps
T889 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1780508581 Mar 28 12:42:02 PM PDT 24 Mar 28 12:42:04 PM PDT 24 166660079 ps
T890 /workspace/coverage/cover_reg_top/18.edn_intr_test.2170359901 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 36817421 ps
T891 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3160436677 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 42663430 ps
T892 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4007998053 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:48 PM PDT 24 474372441 ps
T893 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1426488247 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:49 PM PDT 24 364414113 ps
T894 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2209040000 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:43 PM PDT 24 38112603 ps
T895 /workspace/coverage/cover_reg_top/33.edn_intr_test.2191893526 Mar 28 12:41:49 PM PDT 24 Mar 28 12:41:50 PM PDT 24 33201634 ps
T896 /workspace/coverage/cover_reg_top/36.edn_intr_test.3008167785 Mar 28 12:41:49 PM PDT 24 Mar 28 12:41:50 PM PDT 24 22251966 ps
T897 /workspace/coverage/cover_reg_top/14.edn_intr_test.3526644958 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:48 PM PDT 24 18795937 ps
T898 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3767263565 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 24797467 ps
T899 /workspace/coverage/cover_reg_top/22.edn_intr_test.843039919 Mar 28 12:41:49 PM PDT 24 Mar 28 12:41:50 PM PDT 24 56848047 ps
T213 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.328064462 Mar 28 12:41:35 PM PDT 24 Mar 28 12:41:36 PM PDT 24 37452326 ps
T900 /workspace/coverage/cover_reg_top/44.edn_intr_test.2515379536 Mar 28 12:42:03 PM PDT 24 Mar 28 12:42:04 PM PDT 24 14116105 ps
T901 /workspace/coverage/cover_reg_top/3.edn_csr_rw.777112983 Mar 28 12:41:30 PM PDT 24 Mar 28 12:41:31 PM PDT 24 19014018 ps
T902 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.549783793 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:45 PM PDT 24 44594394 ps
T903 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3602874390 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 97138605 ps
T904 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2863850312 Mar 28 12:41:50 PM PDT 24 Mar 28 12:41:51 PM PDT 24 33206229 ps
T905 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2642329301 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:48 PM PDT 24 29074731 ps
T906 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4048637154 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:46 PM PDT 24 37990453 ps
T907 /workspace/coverage/cover_reg_top/47.edn_intr_test.3586793949 Mar 28 12:41:50 PM PDT 24 Mar 28 12:41:51 PM PDT 24 44271282 ps
T908 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2235487420 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:43 PM PDT 24 61078494 ps
T909 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2368850985 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:46 PM PDT 24 359441533 ps
T910 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1317514655 Mar 28 12:41:35 PM PDT 24 Mar 28 12:41:38 PM PDT 24 101981381 ps
T911 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.342192109 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:45 PM PDT 24 48040416 ps
T912 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3398305546 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:50 PM PDT 24 604042490 ps
T913 /workspace/coverage/cover_reg_top/45.edn_intr_test.1024333815 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:49 PM PDT 24 13151608 ps
T214 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4226963349 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:48 PM PDT 24 44468069 ps
T914 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1484712580 Mar 28 12:41:38 PM PDT 24 Mar 28 12:41:39 PM PDT 24 29441491 ps
T915 /workspace/coverage/cover_reg_top/11.edn_intr_test.277849909 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:46 PM PDT 24 13510575 ps
T916 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.95483470 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:46 PM PDT 24 16107251 ps
T917 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1901384878 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:42 PM PDT 24 51869767 ps
T918 /workspace/coverage/cover_reg_top/1.edn_tl_errors.85974462 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:43 PM PDT 24 68846820 ps
T919 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1402485859 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 34421788 ps
T920 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3604418489 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:47 PM PDT 24 37627564 ps
T921 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.195412141 Mar 28 12:41:50 PM PDT 24 Mar 28 12:41:52 PM PDT 24 138520057 ps
T922 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3216522957 Mar 28 12:41:39 PM PDT 24 Mar 28 12:41:41 PM PDT 24 103262463 ps
T219 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4114861586 Mar 28 12:41:55 PM PDT 24 Mar 28 12:41:59 PM PDT 24 129405191 ps
T923 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4188467647 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:46 PM PDT 24 22683599 ps
T924 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1106607302 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 35425754 ps
T925 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2757816571 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 100063714 ps
T926 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1135650078 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:51 PM PDT 24 123954341 ps
T927 /workspace/coverage/cover_reg_top/9.edn_csr_rw.846896420 Mar 28 12:41:30 PM PDT 24 Mar 28 12:41:31 PM PDT 24 38334086 ps
T928 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3810461658 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:45 PM PDT 24 72089945 ps
T929 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2917223089 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:44 PM PDT 24 248919282 ps
T930 /workspace/coverage/cover_reg_top/10.edn_tl_errors.687166874 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:46 PM PDT 24 163533475 ps
T931 /workspace/coverage/cover_reg_top/46.edn_intr_test.1099765193 Mar 28 12:42:00 PM PDT 24 Mar 28 12:42:01 PM PDT 24 193919311 ps
T932 /workspace/coverage/cover_reg_top/31.edn_intr_test.1329281606 Mar 28 12:41:54 PM PDT 24 Mar 28 12:41:57 PM PDT 24 22107523 ps
T933 /workspace/coverage/cover_reg_top/12.edn_csr_rw.974549849 Mar 28 12:41:55 PM PDT 24 Mar 28 12:41:57 PM PDT 24 22278855 ps
T934 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1800553656 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 29969838 ps
T935 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1482887889 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 18301634 ps
T936 /workspace/coverage/cover_reg_top/6.edn_intr_test.32911757 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 22637556 ps
T937 /workspace/coverage/cover_reg_top/19.edn_csr_rw.715945521 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:48 PM PDT 24 29766147 ps
T215 /workspace/coverage/cover_reg_top/14.edn_csr_rw.164357532 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:44 PM PDT 24 28370593 ps
T216 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1281602424 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:44 PM PDT 24 111809962 ps
T938 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3998247851 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:47 PM PDT 24 70581843 ps
T939 /workspace/coverage/cover_reg_top/41.edn_intr_test.2164706652 Mar 28 12:41:50 PM PDT 24 Mar 28 12:41:51 PM PDT 24 34090176 ps
T940 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2925120495 Mar 28 12:41:38 PM PDT 24 Mar 28 12:41:39 PM PDT 24 81593600 ps
T941 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.361114872 Mar 28 12:41:38 PM PDT 24 Mar 28 12:41:40 PM PDT 24 43869724 ps
T942 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2365818850 Mar 28 12:41:38 PM PDT 24 Mar 28 12:41:39 PM PDT 24 19339651 ps
T943 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3102931914 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:47 PM PDT 24 50933281 ps
T944 /workspace/coverage/cover_reg_top/4.edn_tl_errors.44430273 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:47 PM PDT 24 35784998 ps
T220 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1935089360 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:48 PM PDT 24 72064545 ps
T945 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2958840854 Mar 28 12:41:41 PM PDT 24 Mar 28 12:41:42 PM PDT 24 12583298 ps
T217 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3667085312 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:45 PM PDT 24 29992516 ps
T946 /workspace/coverage/cover_reg_top/49.edn_intr_test.2032613979 Mar 28 12:42:04 PM PDT 24 Mar 28 12:42:05 PM PDT 24 17540228 ps
T947 /workspace/coverage/cover_reg_top/11.edn_csr_rw.268972005 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:46 PM PDT 24 22321283 ps
T948 /workspace/coverage/cover_reg_top/30.edn_intr_test.1161666057 Mar 28 12:41:49 PM PDT 24 Mar 28 12:41:50 PM PDT 24 14761054 ps
T949 /workspace/coverage/cover_reg_top/21.edn_intr_test.329177379 Mar 28 12:42:08 PM PDT 24 Mar 28 12:42:09 PM PDT 24 34953259 ps
T950 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3050913879 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:46 PM PDT 24 106731993 ps
T951 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2655403394 Mar 28 12:41:39 PM PDT 24 Mar 28 12:41:40 PM PDT 24 20021808 ps
T952 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.365531450 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:45 PM PDT 24 31878412 ps
T953 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2010221359 Mar 28 12:41:36 PM PDT 24 Mar 28 12:41:38 PM PDT 24 440747622 ps
T954 /workspace/coverage/cover_reg_top/0.edn_intr_test.1267984071 Mar 28 12:41:33 PM PDT 24 Mar 28 12:41:34 PM PDT 24 11583561 ps
T955 /workspace/coverage/cover_reg_top/8.edn_intr_test.1598485914 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:42 PM PDT 24 14125451 ps
T956 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3343162681 Mar 28 12:41:40 PM PDT 24 Mar 28 12:41:43 PM PDT 24 36754641 ps
T957 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2456355372 Mar 28 12:41:39 PM PDT 24 Mar 28 12:41:41 PM PDT 24 211217394 ps
T958 /workspace/coverage/cover_reg_top/24.edn_intr_test.3788423990 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:48 PM PDT 24 37395015 ps
T959 /workspace/coverage/cover_reg_top/2.edn_intr_test.3210698317 Mar 28 12:41:33 PM PDT 24 Mar 28 12:41:34 PM PDT 24 24922058 ps
T218 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1166129433 Mar 28 12:41:42 PM PDT 24 Mar 28 12:41:45 PM PDT 24 94080664 ps
T960 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.135577000 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:45 PM PDT 24 41633311 ps
T961 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.181572746 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:46 PM PDT 24 53449874 ps
T962 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.874932379 Mar 28 12:41:46 PM PDT 24 Mar 28 12:41:47 PM PDT 24 120669665 ps
T963 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4070521002 Mar 28 12:41:52 PM PDT 24 Mar 28 12:41:56 PM PDT 24 22481851 ps
T964 /workspace/coverage/cover_reg_top/6.edn_csr_rw.737334941 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:49 PM PDT 24 14457933 ps
T965 /workspace/coverage/cover_reg_top/8.edn_tl_errors.638274609 Mar 28 12:41:37 PM PDT 24 Mar 28 12:41:39 PM PDT 24 79769517 ps
T966 /workspace/coverage/cover_reg_top/38.edn_intr_test.3801409638 Mar 28 12:41:53 PM PDT 24 Mar 28 12:41:57 PM PDT 24 14962833 ps
T967 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2898107350 Mar 28 12:41:43 PM PDT 24 Mar 28 12:41:47 PM PDT 24 46952342 ps
T968 /workspace/coverage/cover_reg_top/20.edn_intr_test.3975778091 Mar 28 12:41:48 PM PDT 24 Mar 28 12:41:49 PM PDT 24 24791733 ps
T969 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.101672224 Mar 28 12:41:33 PM PDT 24 Mar 28 12:41:34 PM PDT 24 21187180 ps
T970 /workspace/coverage/cover_reg_top/5.edn_intr_test.1820315664 Mar 28 12:41:47 PM PDT 24 Mar 28 12:41:48 PM PDT 24 24448063 ps
T971 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2613576711 Mar 28 12:41:35 PM PDT 24 Mar 28 12:41:37 PM PDT 24 36776472 ps
T972 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3823446568 Mar 28 12:41:44 PM PDT 24 Mar 28 12:41:47 PM PDT 24 321826617 ps
T973 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2504240452 Mar 28 12:41:45 PM PDT 24 Mar 28 12:41:46 PM PDT 24 22726318 ps

Test location /workspace/coverage/default/235.edn_genbits.1126925827
Short name T1
Test name
Test status
Simulation time 87379695 ps
CPU time 1.65 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 217880 kb
Host smart-e12fb506-11ae-4749-9879-21570826beba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126925827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1126925827
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2238486084
Short name T31
Test name
Test status
Simulation time 72754328 ps
CPU time 1.25 seconds
Started Mar 28 01:30:33 PM PDT 24
Finished Mar 28 01:30:35 PM PDT 24
Peak memory 216404 kb
Host smart-d46a3e2c-13b6-4b9d-948e-f8abfd4074de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238486084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2238486084
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2617162105
Short name T23
Test name
Test status
Simulation time 264013376205 ps
CPU time 1235.13 seconds
Started Mar 28 01:31:26 PM PDT 24
Finished Mar 28 01:52:01 PM PDT 24
Peak memory 221388 kb
Host smart-f3714876-599a-4512-bbe9-b60c4540d4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617162105 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2617162105
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1041161379
Short name T3
Test name
Test status
Simulation time 167527041 ps
CPU time 3.38 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 236072 kb
Host smart-ddf4301c-594c-4e7c-87f9-65e53c2871bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041161379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1041161379
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/14.edn_alert.179205873
Short name T18
Test name
Test status
Simulation time 79758511 ps
CPU time 1.18 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 215604 kb
Host smart-452080bf-26f8-4788-b235-1dc403694467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179205873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.179205873
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1065559736
Short name T20
Test name
Test status
Simulation time 788672215 ps
CPU time 6.8 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:10 PM PDT 24
Peak memory 235716 kb
Host smart-93dc96af-c56c-4a0b-affb-19cd94fe543d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065559736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1065559736
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2126743879
Short name T148
Test name
Test status
Simulation time 90143224 ps
CPU time 1.17 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 217824 kb
Host smart-9e32465e-819c-4e51-8c35-86bf1ea84e25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126743879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2126743879
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3047917822
Short name T36
Test name
Test status
Simulation time 33434036 ps
CPU time 0.99 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 231096 kb
Host smart-8de8638d-a0e3-46d1-b892-802256077dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047917822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3047917822
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.4252448360
Short name T49
Test name
Test status
Simulation time 24530408 ps
CPU time 1.27 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 215584 kb
Host smart-dd413bb2-5008-40d9-be24-e93d57b65fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252448360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4252448360
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2811940765
Short name T12
Test name
Test status
Simulation time 31319935 ps
CPU time 1.24 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 219220 kb
Host smart-aad9c7e2-99b3-4d4b-97ed-ea2e2d73bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811940765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2811940765
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3861981425
Short name T110
Test name
Test status
Simulation time 27408986 ps
CPU time 0.95 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215628 kb
Host smart-7f74e973-0f61-4c1c-ab68-a28b4b73f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861981425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3861981425
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.878139244
Short name T121
Test name
Test status
Simulation time 40346186 ps
CPU time 0.95 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 207092 kb
Host smart-2c93543f-ee78-42d7-a099-f0e1d0eef7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878139244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.878139244
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_alert.3166687958
Short name T17
Test name
Test status
Simulation time 40079616 ps
CPU time 1.22 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:38 PM PDT 24
Peak memory 215576 kb
Host smart-4f9209a5-d796-4043-b4ed-445036e442d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166687958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3166687958
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.423701668
Short name T207
Test name
Test status
Simulation time 13900055 ps
CPU time 0.94 seconds
Started Mar 28 12:41:31 PM PDT 24
Finished Mar 28 12:41:32 PM PDT 24
Peak memory 206188 kb
Host smart-4f559b8a-4480-49dd-a5f2-53f23d759b67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423701668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.423701668
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3649498118
Short name T70
Test name
Test status
Simulation time 141197068 ps
CPU time 1.27 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 216516 kb
Host smart-7af946d4-cc3c-4045-9b41-2e9def170e87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649498118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3649498118
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.619613935
Short name T237
Test name
Test status
Simulation time 587509989 ps
CPU time 2.12 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 206332 kb
Host smart-cabd5523-c310-47de-8065-9f3fd0c9724c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619613935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.619613935
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/default/48.edn_disable.3123644934
Short name T81
Test name
Test status
Simulation time 14355208 ps
CPU time 0.94 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:31:26 PM PDT 24
Peak memory 215948 kb
Host smart-47466f2d-7488-4b11-bbb4-c4dd1338d534
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123644934 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3123644934
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable.1407991883
Short name T147
Test name
Test status
Simulation time 46998236 ps
CPU time 0.86 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215864 kb
Host smart-88a7e10b-cc76-4ca7-ab74-a355f5584a37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407991883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1407991883
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2984509998
Short name T135
Test name
Test status
Simulation time 133389932340 ps
CPU time 1576.8 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:57:33 PM PDT 24
Peak memory 226496 kb
Host smart-9fccc51d-da8b-4157-8bbb-96600ce1178e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984509998 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2984509998
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert.2962820457
Short name T88
Test name
Test status
Simulation time 32091000 ps
CPU time 1.22 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215672 kb
Host smart-f8f2eadd-c5cb-4499-ba3d-cc268258ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962820457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2962820457
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2763909651
Short name T54
Test name
Test status
Simulation time 32027706 ps
CPU time 1.15 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 216348 kb
Host smart-2bbe377c-2533-4bcc-9f42-2fc7bc768829
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763909651 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2763909651
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_disable.1218376031
Short name T776
Test name
Test status
Simulation time 14211529 ps
CPU time 0.9 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:57 PM PDT 24
Peak memory 215988 kb
Host smart-07e8420b-edc1-42e3-b6f9-ad669038399c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218376031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1218376031
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/14.edn_intr.3702501687
Short name T111
Test name
Test status
Simulation time 30120525 ps
CPU time 0.9 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215500 kb
Host smart-c47eda84-a861-4b2b-9cde-f33a9900e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702501687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3702501687
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/153.edn_genbits.4083471060
Short name T22
Test name
Test status
Simulation time 55050516 ps
CPU time 1.12 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 216544 kb
Host smart-229ed327-8426-4f5e-b3d5-cf7e7131d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083471060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4083471060
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2708386905
Short name T64
Test name
Test status
Simulation time 25794728 ps
CPU time 1 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 217996 kb
Host smart-7d21f2ef-0be2-4f53-818f-04a222c2a840
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708386905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2708386905
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_genbits.943777468
Short name T239
Test name
Test status
Simulation time 30221162 ps
CPU time 1.26 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 218208 kb
Host smart-476b5477-1936-4e23-a49b-b43d4d7a1d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943777468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.943777468
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3086008700
Short name T227
Test name
Test status
Simulation time 43703659 ps
CPU time 1.44 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 216608 kb
Host smart-133e1346-038b-48aa-937b-3a68248fb12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086008700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3086008700
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_disable.1564776955
Short name T80
Test name
Test status
Simulation time 39482336 ps
CPU time 0.87 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215396 kb
Host smart-a54ef1e4-3e7e-4e84-8445-54e55c6bbb3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564776955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1564776955
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.1977475668
Short name T571
Test name
Test status
Simulation time 11879535 ps
CPU time 0.9 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 215808 kb
Host smart-0f83c682-e94b-4cce-bbac-728c3b2edc3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977475668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1977475668
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.249430560
Short name T41
Test name
Test status
Simulation time 26375023 ps
CPU time 1.11 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 231324 kb
Host smart-541a8e31-f9e8-45fd-baa4-8da3a7531b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249430560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.249430560
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/2.edn_disable.1173206555
Short name T169
Test name
Test status
Simulation time 28748570 ps
CPU time 0.82 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 215716 kb
Host smart-ab34ebb5-a07e-48b9-8110-2d16187ad845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173206555 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1173206555
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1049807242
Short name T71
Test name
Test status
Simulation time 59469301 ps
CPU time 1.05 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216376 kb
Host smart-016147ba-250a-4b09-a479-0ed0fb7af107
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049807242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1049807242
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.522247315
Short name T104
Test name
Test status
Simulation time 10741580 ps
CPU time 0.92 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 215796 kb
Host smart-1213e731-b4de-4c9e-a63b-c2fe15b2397f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522247315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.522247315
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.3720529468
Short name T151
Test name
Test status
Simulation time 11200235 ps
CPU time 0.88 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 215812 kb
Host smart-3c58fb96-9d70-42d9-9e09-c1e9ceb53145
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720529468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3720529468
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.52111110
Short name T55
Test name
Test status
Simulation time 63204776 ps
CPU time 1.26 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 216468 kb
Host smart-9d1ea908-cadc-4e8a-a29a-7252d533c5c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52111110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disa
ble_auto_req_mode.52111110
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/194.edn_genbits.1259244475
Short name T174
Test name
Test status
Simulation time 70159150 ps
CPU time 1.07 seconds
Started Mar 28 01:32:11 PM PDT 24
Finished Mar 28 01:32:13 PM PDT 24
Peak memory 216708 kb
Host smart-ec91e267-e0ee-49df-802a-56499f9f45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259244475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1259244475
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.2993682288
Short name T195
Test name
Test status
Simulation time 35474007 ps
CPU time 0.96 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 207032 kb
Host smart-b2697914-eecf-495e-9d7d-88a4809547cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993682288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2993682288
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/67.edn_genbits.3157752471
Short name T233
Test name
Test status
Simulation time 46846658 ps
CPU time 1.48 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218888 kb
Host smart-c06526c0-23d0-480d-8c09-6a7e5eaf234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157752471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3157752471
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.122256493
Short name T298
Test name
Test status
Simulation time 13908978 ps
CPU time 0.93 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 205992 kb
Host smart-65aa7159-c971-4b7a-aa6b-d70e9a248064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122256493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.122256493
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/148.edn_genbits.2393177753
Short name T277
Test name
Test status
Simulation time 59604969 ps
CPU time 1.5 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218848 kb
Host smart-823b51d0-74c1-4f98-adc2-2ff4f110778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393177753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2393177753
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.4285900084
Short name T122
Test name
Test status
Simulation time 44191899 ps
CPU time 0.94 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 207104 kb
Host smart-fe07a8ad-63df-4704-8be8-4e93239d5d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285900084 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.4285900084
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_alert.960504056
Short name T48
Test name
Test status
Simulation time 49119853 ps
CPU time 1.33 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215596 kb
Host smart-38c09244-9edd-47a2-a045-c4fafed8f609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960504056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.960504056
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/230.edn_genbits.1456379351
Short name T116
Test name
Test status
Simulation time 64923974 ps
CPU time 1.15 seconds
Started Mar 28 01:32:10 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 219232 kb
Host smart-197544b2-e202-47fd-9fed-59d43bf73741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456379351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1456379351
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.821250621
Short name T128
Test name
Test status
Simulation time 19700439 ps
CPU time 1.22 seconds
Started Mar 28 01:31:22 PM PDT 24
Finished Mar 28 01:31:23 PM PDT 24
Peak memory 215812 kb
Host smart-bb122cef-c9d8-4b59-9551-7b071b763204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821250621 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.821250621
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/10.edn_alert.3658182863
Short name T246
Test name
Test status
Simulation time 81617323 ps
CPU time 1.06 seconds
Started Mar 28 01:30:22 PM PDT 24
Finished Mar 28 01:30:23 PM PDT 24
Peak memory 215608 kb
Host smart-a27ec855-7c41-4797-b5a7-ac8613e42f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658182863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3658182863
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.1394190318
Short name T270
Test name
Test status
Simulation time 53313147 ps
CPU time 1.08 seconds
Started Mar 28 01:32:00 PM PDT 24
Finished Mar 28 01:32:02 PM PDT 24
Peak memory 216476 kb
Host smart-28e36236-9f65-47de-bbd9-ea9b71fec321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394190318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1394190318
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.665912893
Short name T257
Test name
Test status
Simulation time 65030622 ps
CPU time 1.07 seconds
Started Mar 28 01:32:00 PM PDT 24
Finished Mar 28 01:32:01 PM PDT 24
Peak memory 216716 kb
Host smart-26dff49c-5e97-49fa-a47d-7bf932019d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665912893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.665912893
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.750107920
Short name T253
Test name
Test status
Simulation time 26810019 ps
CPU time 1.31 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215576 kb
Host smart-1402d5ea-2e03-42e1-8d64-6bf45605f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750107920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.750107920
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all.3103855166
Short name T198
Test name
Test status
Simulation time 252450007 ps
CPU time 5.13 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 215268 kb
Host smart-d6edcdd3-2d19-4ca6-bb72-e4324d880bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103855166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3103855166
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.887430847
Short name T276
Test name
Test status
Simulation time 86784903 ps
CPU time 1.35 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 217924 kb
Host smart-32b8cbe3-e116-4ecd-b9c4-111fbb822818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887430847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.887430847
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1015570294
Short name T262
Test name
Test status
Simulation time 106080690 ps
CPU time 1.3 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 219376 kb
Host smart-9bc66e39-0ca8-44fa-ae3a-4bf51380ef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015570294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1015570294
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4288321792
Short name T575
Test name
Test status
Simulation time 53441185 ps
CPU time 1.15 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 218200 kb
Host smart-83422f40-2e4e-4eef-9cf4-41e123205718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288321792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4288321792
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1463622389
Short name T272
Test name
Test status
Simulation time 78150613 ps
CPU time 3.02 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:18 PM PDT 24
Peak memory 216912 kb
Host smart-c22af69c-2a85-4102-946c-1002d624755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463622389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1463622389
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2988508924
Short name T230
Test name
Test status
Simulation time 57656582 ps
CPU time 1.57 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217584 kb
Host smart-b7aec298-7914-46ce-b62d-f731bf77d6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988508924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2988508924
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4009260256
Short name T717
Test name
Test status
Simulation time 43419180 ps
CPU time 1.27 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217908 kb
Host smart-7a30ab29-e0e7-4be3-8aa7-670e3b475c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009260256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4009260256
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2029021725
Short name T250
Test name
Test status
Simulation time 24106579 ps
CPU time 1.22 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 215648 kb
Host smart-31570812-6e17-4708-b549-49c91be9f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029021725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2029021725
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/17.edn_intr.1599894695
Short name T118
Test name
Test status
Simulation time 21626373 ps
CPU time 1.13 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215704 kb
Host smart-a273f0ee-9189-421b-8c6c-0fd179e2b65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599894695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1599894695
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/18.edn_disable.679715039
Short name T831
Test name
Test status
Simulation time 10893820 ps
CPU time 0.92 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215724 kb
Host smart-35ddbbdc-f44f-4aa6-9432-ec5eb9bcb66d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679715039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.679715039
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.4050920214
Short name T43
Test name
Test status
Simulation time 11945079 ps
CPU time 0.92 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215608 kb
Host smart-d496219c-274e-4bbb-bf2b-e7e807028cde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050920214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4050920214
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/162.edn_genbits.1549852143
Short name T457
Test name
Test status
Simulation time 47634536 ps
CPU time 1.63 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218112 kb
Host smart-0b1cfb9e-e7dc-435f-93c3-3421473cf9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549852143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1549852143
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_err.2135449923
Short name T7
Test name
Test status
Simulation time 51003862 ps
CPU time 1.03 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 217960 kb
Host smart-db52c33b-6d03-45aa-ad42-45fd0b810420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135449923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2135449923
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2655850097
Short name T866
Test name
Test status
Simulation time 215517264 ps
CPU time 1.44 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206200 kb
Host smart-abb01295-78fc-43f5-9ac9-c011db2b896e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655850097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2655850097
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2696699677
Short name T210
Test name
Test status
Simulation time 250437824 ps
CPU time 5.75 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206236 kb
Host smart-c66777ea-cf86-4021-9c11-d159b6f91310
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696699677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2696699677
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.328064462
Short name T213
Test name
Test status
Simulation time 37452326 ps
CPU time 0.82 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 206276 kb
Host smart-9a781401-461e-4c84-a296-0d4a28f003f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328064462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.328064462
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1800553656
Short name T934
Test name
Test status
Simulation time 29969838 ps
CPU time 0.96 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206432 kb
Host smart-37580ef4-72e0-440f-9e6b-5cb73282a6a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800553656 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1800553656
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2504240452
Short name T973
Test name
Test status
Simulation time 22726318 ps
CPU time 0.84 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 206216 kb
Host smart-8d0fc2f7-9cbb-431e-a9ad-89e0578b542e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504240452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2504240452
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1267984071
Short name T954
Test name
Test status
Simulation time 11583561 ps
CPU time 0.85 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:41:34 PM PDT 24
Peak memory 206248 kb
Host smart-6d76a5bb-15f6-4c0b-9348-ef97bcaa1d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267984071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1267984071
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.67528075
Short name T877
Test name
Test status
Simulation time 38273670 ps
CPU time 1.55 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206200 kb
Host smart-621dc98d-fe86-4198-9718-8645b986e585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67528075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs
tanding.67528075
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.509642958
Short name T871
Test name
Test status
Simulation time 1163394956 ps
CPU time 5.02 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:53 PM PDT 24
Peak memory 214644 kb
Host smart-0f20aa2d-e20d-4330-bc73-f03432bb81a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509642958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.509642958
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2010221359
Short name T953
Test name
Test status
Simulation time 440747622 ps
CPU time 2.26 seconds
Started Mar 28 12:41:36 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 206348 kb
Host smart-e162cffd-19e5-43d7-9e92-b78f13680979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010221359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2010221359
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4188467647
Short name T923
Test name
Test status
Simulation time 22683599 ps
CPU time 1.06 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 206220 kb
Host smart-0d66dd43-d828-4817-ba6b-df45cdb3dbbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188467647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4188467647
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2917223089
Short name T929
Test name
Test status
Simulation time 248919282 ps
CPU time 3.6 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206324 kb
Host smart-50c2fd27-072b-48a1-a012-f609a9ae988e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917223089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2917223089
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1281602424
Short name T216
Test name
Test status
Simulation time 111809962 ps
CPU time 0.98 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206196 kb
Host smart-9372a9ab-9355-48e2-a28c-c5476692e3f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281602424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1281602424
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1402485859
Short name T919
Test name
Test status
Simulation time 34421788 ps
CPU time 1.04 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 214584 kb
Host smart-2fec66c0-7fd5-4f63-94a9-2a9fcfe16507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402485859 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1402485859
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2250323503
Short name T206
Test name
Test status
Simulation time 12567478 ps
CPU time 0.88 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206204 kb
Host smart-b3ae5a4d-e9f7-4a2e-b14e-375f6b6e54b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250323503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2250323503
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1536849
Short name T845
Test name
Test status
Simulation time 17376244 ps
CPU time 0.83 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 206232 kb
Host smart-38bba081-6ac9-4690-8d8e-07e32dfabe43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1536849
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2227691267
Short name T208
Test name
Test status
Simulation time 36024784 ps
CPU time 1.41 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 206424 kb
Host smart-023827a0-3b34-43a2-87b1-750e1096071d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227691267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2227691267
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.85974462
Short name T918
Test name
Test status
Simulation time 68846820 ps
CPU time 2.67 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 214692 kb
Host smart-039765e3-a187-4a5f-8009-f14320054fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85974462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.85974462
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.316969260
Short name T870
Test name
Test status
Simulation time 171177592 ps
CPU time 1.65 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206380 kb
Host smart-8ef6d9cf-9249-4968-8c17-90fd3cdf4975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316969260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.316969260
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.365531450
Short name T952
Test name
Test status
Simulation time 31878412 ps
CPU time 1.46 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 214668 kb
Host smart-6c503fc0-db09-4147-93d4-c73a5b0d8b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365531450 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.365531450
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3078383038
Short name T202
Test name
Test status
Simulation time 17070965 ps
CPU time 0.79 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206008 kb
Host smart-ec7e6fb5-541c-4a18-874f-b3ac2fa140c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078383038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3078383038
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.4256014192
Short name T885
Test name
Test status
Simulation time 17671702 ps
CPU time 0.76 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206092 kb
Host smart-9f6d043b-ab4a-4ab9-9acc-e9e184de97b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256014192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4256014192
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3998247851
Short name T938
Test name
Test status
Simulation time 70581843 ps
CPU time 1.11 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206308 kb
Host smart-afdcc961-4935-4487-b6a2-82a6818ae0a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998247851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3998247851
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.687166874
Short name T930
Test name
Test status
Simulation time 163533475 ps
CPU time 1.92 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 214580 kb
Host smart-d3f8f9c7-2099-4815-bd65-29882ceb2750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687166874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.687166874
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3823446568
Short name T972
Test name
Test status
Simulation time 321826617 ps
CPU time 2.23 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206316 kb
Host smart-f8a9680a-e723-4c2d-9c66-1a394d693b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823446568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3823446568
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1222118593
Short name T848
Test name
Test status
Simulation time 84797122 ps
CPU time 1.35 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206360 kb
Host smart-63516f8d-b02b-402d-807e-b833bfa9467c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222118593 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1222118593
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.268972005
Short name T947
Test name
Test status
Simulation time 22321283 ps
CPU time 0.85 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 204832 kb
Host smart-eb90e23e-1eed-45c8-8e17-457b11be8f7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268972005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.268972005
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.277849909
Short name T915
Test name
Test status
Simulation time 13510575 ps
CPU time 0.82 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 205164 kb
Host smart-4f31f182-bf9c-4fe2-a56c-51f295e5bbc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277849909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.277849909
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2235487420
Short name T908
Test name
Test status
Simulation time 61078494 ps
CPU time 1.02 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206344 kb
Host smart-da17b64b-3a2a-435c-8170-38a95140a394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235487420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2235487420
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2368850985
Short name T909
Test name
Test status
Simulation time 359441533 ps
CPU time 3.26 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 214564 kb
Host smart-396c6d5a-f311-486a-be0a-0b6cdbcdd33b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368850985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2368850985
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2550094727
Short name T236
Test name
Test status
Simulation time 75605415 ps
CPU time 1.46 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206136 kb
Host smart-b2d16d0b-1b37-44a2-a33d-cc3028544ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550094727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2550094727
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.101672224
Short name T969
Test name
Test status
Simulation time 21187180 ps
CPU time 1.27 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:41:34 PM PDT 24
Peak memory 214564 kb
Host smart-3ab3f286-bab2-4a59-8e34-0bce7f55f8fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101672224 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.101672224
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.974549849
Short name T933
Test name
Test status
Simulation time 22278855 ps
CPU time 0.84 seconds
Started Mar 28 12:41:55 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 206156 kb
Host smart-89c89c6a-b09f-4ee6-b30a-a963014c8e8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974549849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.974549849
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1020495347
Short name T886
Test name
Test status
Simulation time 38446724 ps
CPU time 0.82 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206080 kb
Host smart-5279870d-1eba-4082-bfcd-d8d4f7f80fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020495347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1020495347
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3241877350
Short name T209
Test name
Test status
Simulation time 13589024 ps
CPU time 0.96 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 205052 kb
Host smart-8be66025-b57f-43eb-b6d2-fca778c902b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241877350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3241877350
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.747520146
Short name T846
Test name
Test status
Simulation time 42425056 ps
CPU time 2.9 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 214584 kb
Host smart-0be152fc-c03a-4cd8-9621-5119e58eb2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747520146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.747520146
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3453317768
Short name T224
Test name
Test status
Simulation time 473160401 ps
CPU time 2.83 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206076 kb
Host smart-9f94298b-3bd9-4367-baf9-fc6ff689998c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453317768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3453317768
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.874932379
Short name T962
Test name
Test status
Simulation time 120669665 ps
CPU time 1.47 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 214604 kb
Host smart-ef70a48d-d72e-4033-a52b-c2bd25ddf6a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874932379 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.874932379
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3604418489
Short name T920
Test name
Test status
Simulation time 37627564 ps
CPU time 0.82 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206036 kb
Host smart-a6356fc7-3ede-4fca-91d0-9e273f5bde90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604418489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3604418489
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2982767708
Short name T869
Test name
Test status
Simulation time 17549436 ps
CPU time 0.92 seconds
Started Mar 28 12:41:57 PM PDT 24
Finished Mar 28 12:41:58 PM PDT 24
Peak memory 206228 kb
Host smart-9b093173-a5b7-44ba-a212-158393c828d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982767708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2982767708
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2932798576
Short name T221
Test name
Test status
Simulation time 30807545 ps
CPU time 1.12 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 206444 kb
Host smart-2482d725-bd63-443b-9276-24bd96946d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932798576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2932798576
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1135650078
Short name T926
Test name
Test status
Simulation time 123954341 ps
CPU time 4.33 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:51 PM PDT 24
Peak memory 214700 kb
Host smart-2f09bd7d-e512-4659-962a-bcc88b51162c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135650078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1135650078
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3398305546
Short name T912
Test name
Test status
Simulation time 604042490 ps
CPU time 2.19 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206388 kb
Host smart-fa4576a0-1f02-4091-8c32-508e43a9be32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398305546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3398305546
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2002260553
Short name T856
Test name
Test status
Simulation time 44922913 ps
CPU time 1.2 seconds
Started Mar 28 12:41:23 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 214684 kb
Host smart-863873fc-4ad9-49a8-89e4-105b3289f777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002260553 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2002260553
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.164357532
Short name T215
Test name
Test status
Simulation time 28370593 ps
CPU time 0.88 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206232 kb
Host smart-7d8f7e68-b1d3-4ed2-be7d-d6d54f84f43a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164357532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.164357532
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3526644958
Short name T897
Test name
Test status
Simulation time 18795937 ps
CPU time 0.9 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206216 kb
Host smart-11233ac8-df5c-4459-8161-bff521570ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526644958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3526644958
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4108021115
Short name T222
Test name
Test status
Simulation time 121038806 ps
CPU time 1.36 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206244 kb
Host smart-4608e0a7-88c2-4600-bf1b-7bae987f1439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108021115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4108021115
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.672877580
Short name T851
Test name
Test status
Simulation time 45427418 ps
CPU time 2.77 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 214644 kb
Host smart-490ca32e-8307-4a0f-a12a-0bede3577dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672877580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.672877580
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2891904064
Short name T234
Test name
Test status
Simulation time 78949494 ps
CPU time 1.51 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:41:34 PM PDT 24
Peak memory 206340 kb
Host smart-ec9bec4b-beb5-4fdd-8f8f-07b6a93ebecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891904064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2891904064
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2918013242
Short name T878
Test name
Test status
Simulation time 20564904 ps
CPU time 1.2 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 214592 kb
Host smart-a6a37d7f-af86-4cb7-a4e3-20e3c077f8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918013242 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2918013242
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2958840854
Short name T945
Test name
Test status
Simulation time 12583298 ps
CPU time 0.89 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 206020 kb
Host smart-e679ea9e-c6a4-4c58-aa53-3689dbf5b41a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958840854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2958840854
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1448939216
Short name T887
Test name
Test status
Simulation time 20922656 ps
CPU time 0.85 seconds
Started Mar 28 12:41:36 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 206260 kb
Host smart-72c25d61-8c1c-4064-ae11-145ec2c3eb0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448939216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1448939216
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2925120495
Short name T940
Test name
Test status
Simulation time 81593600 ps
CPU time 1.07 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 206328 kb
Host smart-283ccbea-1907-4159-855b-ff1ddbbaa9ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925120495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2925120495
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2898107350
Short name T967
Test name
Test status
Simulation time 46952342 ps
CPU time 3.31 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 214620 kb
Host smart-eaec5bf9-4364-44c6-b1d4-d7d105147678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898107350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2898107350
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1317514655
Short name T910
Test name
Test status
Simulation time 101981381 ps
CPU time 2.58 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 206304 kb
Host smart-45ed956a-33c0-4796-8ec8-7db9e5b1fa2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317514655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1317514655
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2046180074
Short name T850
Test name
Test status
Simulation time 78436304 ps
CPU time 0.98 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206388 kb
Host smart-1d696de1-ae59-4870-8c08-21e3d62eb5cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046180074 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2046180074
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1901384878
Short name T917
Test name
Test status
Simulation time 51869767 ps
CPU time 0.84 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 206248 kb
Host smart-ee10b377-e973-4932-bb9b-8f5336e7a1c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901384878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1901384878
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2827998870
Short name T844
Test name
Test status
Simulation time 63278726 ps
CPU time 0.89 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206192 kb
Host smart-ac18ec5d-df60-40da-b54c-970beb74d582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827998870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2827998870
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2655403394
Short name T951
Test name
Test status
Simulation time 20021808 ps
CPU time 1.16 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 206420 kb
Host smart-166a8978-f643-447b-bee0-20a26d015ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655403394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2655403394
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3343162681
Short name T956
Test name
Test status
Simulation time 36754641 ps
CPU time 1.65 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 217044 kb
Host smart-2ebc9417-c5dd-453a-9584-0a2567395561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343162681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3343162681
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2575918468
Short name T235
Test name
Test status
Simulation time 453289630 ps
CPU time 2.19 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206368 kb
Host smart-c3af973f-e862-4b58-9399-18a969ba801a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575918468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2575918468
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3050913879
Short name T950
Test name
Test status
Simulation time 106731993 ps
CPU time 1.57 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 214616 kb
Host smart-163a43b5-5d49-4051-b04b-d8f4a34ac602
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050913879 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3050913879
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.949474694
Short name T872
Test name
Test status
Simulation time 50555960 ps
CPU time 0.89 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206192 kb
Host smart-82a07e96-293d-4f3e-93f3-e519ce3daf88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949474694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.949474694
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1317724020
Short name T884
Test name
Test status
Simulation time 14463663 ps
CPU time 0.95 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206200 kb
Host smart-d92b7a9d-2583-497f-aa29-e306e3a6f1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317724020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1317724020
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.95483470
Short name T916
Test name
Test status
Simulation time 16107251 ps
CPU time 1.07 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 206376 kb
Host smart-ecb1cf02-6f69-4728-b561-7da39a1966e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95483470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_out
standing.95483470
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1884715396
Short name T879
Test name
Test status
Simulation time 147687869 ps
CPU time 1.67 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 214780 kb
Host smart-dbfe5012-efb5-4f9c-b832-2d2586054d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884715396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1884715396
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.361114872
Short name T941
Test name
Test status
Simulation time 43869724 ps
CPU time 1.55 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 206420 kb
Host smart-f13856f8-0045-4114-8436-8e21e0aff53b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361114872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.361114872
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3983785047
Short name T867
Test name
Test status
Simulation time 25028262 ps
CPU time 1.19 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 214656 kb
Host smart-784b5e89-1b9c-4447-bf31-b391e744a65b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983785047 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3983785047
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3667085312
Short name T217
Test name
Test status
Simulation time 29992516 ps
CPU time 0.96 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206008 kb
Host smart-0046b777-ddc4-40a2-89c3-01863997f197
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667085312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3667085312
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2170359901
Short name T890
Test name
Test status
Simulation time 36817421 ps
CPU time 0.82 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 205964 kb
Host smart-3fb2a95e-e400-43ea-b4d8-75cbe525333e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170359901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2170359901
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2209040000
Short name T894
Test name
Test status
Simulation time 38112603 ps
CPU time 1.07 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 206416 kb
Host smart-f2264217-3685-4a1b-89fe-a1f7a2cb73aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209040000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2209040000
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1106607302
Short name T924
Test name
Test status
Simulation time 35425754 ps
CPU time 2.47 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 214780 kb
Host smart-eaa12ec5-7d5f-4ad0-adb2-378b19383fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106607302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1106607302
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3102931914
Short name T943
Test name
Test status
Simulation time 50933281 ps
CPU time 1.75 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206324 kb
Host smart-20faaa29-6bd3-43b8-b902-d9f6badd98aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102931914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3102931914
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2863850312
Short name T904
Test name
Test status
Simulation time 33206229 ps
CPU time 1.46 seconds
Started Mar 28 12:41:50 PM PDT 24
Finished Mar 28 12:41:51 PM PDT 24
Peak memory 217292 kb
Host smart-62123045-3adf-40fe-9dd6-6c68fc25a3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863850312 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2863850312
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.715945521
Short name T937
Test name
Test status
Simulation time 29766147 ps
CPU time 0.81 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206104 kb
Host smart-96dc1eb9-ac7b-4790-bd70-a37e1aa3489c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715945521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.715945521
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3368392720
Short name T873
Test name
Test status
Simulation time 109412303 ps
CPU time 0.84 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206096 kb
Host smart-4f87fc80-4373-43e4-b2ab-aa1cbb9430de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368392720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3368392720
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.195412141
Short name T921
Test name
Test status
Simulation time 138520057 ps
CPU time 1.44 seconds
Started Mar 28 12:41:50 PM PDT 24
Finished Mar 28 12:41:52 PM PDT 24
Peak memory 206436 kb
Host smart-69e9eaa1-5eb4-426c-9728-8ba022bb8968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195412141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.195412141
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1872558576
Short name T841
Test name
Test status
Simulation time 33092803 ps
CPU time 1.16 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 214672 kb
Host smart-5b604217-317c-449e-bed5-5f57fbef16f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872558576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1872558576
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1780508581
Short name T889
Test name
Test status
Simulation time 166660079 ps
CPU time 1.61 seconds
Started Mar 28 12:42:02 PM PDT 24
Finished Mar 28 12:42:04 PM PDT 24
Peak memory 206372 kb
Host smart-9d0b5fe5-e607-4bbb-8989-a50f0c642084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780508581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1780508581
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4226963349
Short name T214
Test name
Test status
Simulation time 44468069 ps
CPU time 1.21 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206232 kb
Host smart-41d2d73a-9c95-400c-95cf-e3f4c7938f60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226963349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4226963349
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1935089360
Short name T220
Test name
Test status
Simulation time 72064545 ps
CPU time 3.09 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206268 kb
Host smart-580a3370-9f2d-420e-b253-ef20e0526cda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935089360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1935089360
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1573866267
Short name T868
Test name
Test status
Simulation time 31432343 ps
CPU time 0.94 seconds
Started Mar 28 12:41:31 PM PDT 24
Finished Mar 28 12:41:32 PM PDT 24
Peak memory 206148 kb
Host smart-49738cca-5481-4f12-828f-111736dfeb0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573866267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1573866267
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.549783793
Short name T902
Test name
Test status
Simulation time 44594394 ps
CPU time 1.23 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 214692 kb
Host smart-b8ff642e-72ec-4c60-9e92-8f8d0eda2d87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549783793 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.549783793
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1484712580
Short name T914
Test name
Test status
Simulation time 29441491 ps
CPU time 0.94 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 206192 kb
Host smart-53bdb93f-0a41-4e29-b6fa-20c490d3a9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484712580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1484712580
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3210698317
Short name T959
Test name
Test status
Simulation time 24922058 ps
CPU time 0.85 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:41:34 PM PDT 24
Peak memory 206308 kb
Host smart-8df81c13-2bb9-4684-81d6-60b6408367e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210698317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3210698317
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2362445919
Short name T205
Test name
Test status
Simulation time 26830302 ps
CPU time 1.08 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206476 kb
Host smart-bdc32590-5000-43b7-aaac-fe9e8a7bb64d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362445919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2362445919
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.684297118
Short name T875
Test name
Test status
Simulation time 76405676 ps
CPU time 1.57 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 218108 kb
Host smart-4f1598ae-7425-4186-95e6-d2ccbd69c9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684297118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.684297118
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2456355372
Short name T957
Test name
Test status
Simulation time 211217394 ps
CPU time 1.69 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 206324 kb
Host smart-88ede1ac-fcfc-4ed3-b60b-adff2c51c67c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456355372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2456355372
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3975778091
Short name T968
Test name
Test status
Simulation time 24791733 ps
CPU time 0.91 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206304 kb
Host smart-e3f006a4-3d5b-4a6f-85b5-83d0fe4076d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975778091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3975778091
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.329177379
Short name T949
Test name
Test status
Simulation time 34953259 ps
CPU time 0.96 seconds
Started Mar 28 12:42:08 PM PDT 24
Finished Mar 28 12:42:09 PM PDT 24
Peak memory 206176 kb
Host smart-6d817afb-cd65-4e39-a274-464a072a6bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329177379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.329177379
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.843039919
Short name T899
Test name
Test status
Simulation time 56848047 ps
CPU time 0.93 seconds
Started Mar 28 12:41:49 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206208 kb
Host smart-c76cf063-7cd4-44e1-9b21-529747e4a4ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843039919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.843039919
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.527717898
Short name T882
Test name
Test status
Simulation time 15233670 ps
CPU time 0.91 seconds
Started Mar 28 12:42:07 PM PDT 24
Finished Mar 28 12:42:08 PM PDT 24
Peak memory 206176 kb
Host smart-cd925f1a-d69e-4b73-9479-2ceb96ef5309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527717898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.527717898
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3788423990
Short name T958
Test name
Test status
Simulation time 37395015 ps
CPU time 0.81 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206016 kb
Host smart-1e72931c-c176-43e9-af4c-ecc23d3a1459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788423990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3788423990
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2095617297
Short name T847
Test name
Test status
Simulation time 31775742 ps
CPU time 0.85 seconds
Started Mar 28 12:41:51 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 206228 kb
Host smart-eccd2f24-2040-446d-8c69-58f7ee983334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095617297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2095617297
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3958399659
Short name T880
Test name
Test status
Simulation time 23529960 ps
CPU time 0.82 seconds
Started Mar 28 12:42:08 PM PDT 24
Finished Mar 28 12:42:09 PM PDT 24
Peak memory 206200 kb
Host smart-45c8b86c-d1b6-4c80-ae8c-e2c52fd1dc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958399659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3958399659
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3161237719
Short name T849
Test name
Test status
Simulation time 13232283 ps
CPU time 0.79 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206248 kb
Host smart-2906a641-91b2-404a-a9ab-1349ff2f804a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161237719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3161237719
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3074056096
Short name T860
Test name
Test status
Simulation time 28091619 ps
CPU time 0.81 seconds
Started Mar 28 12:42:07 PM PDT 24
Finished Mar 28 12:42:09 PM PDT 24
Peak memory 205996 kb
Host smart-da41e1dd-c6c7-4a46-ab57-bc4cb048bb97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074056096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3074056096
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.956877417
Short name T840
Test name
Test status
Simulation time 23034819 ps
CPU time 0.83 seconds
Started Mar 28 12:41:52 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 206196 kb
Host smart-6879e47e-dcdc-46ba-bc44-8ec681ad5130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956877417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.956877417
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1166129433
Short name T218
Test name
Test status
Simulation time 94080664 ps
CPU time 1.59 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206172 kb
Host smart-0c00bab9-4d47-4f43-8d9a-2253101dddf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166129433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1166129433
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4007998053
Short name T892
Test name
Test status
Simulation time 474372441 ps
CPU time 3.27 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206192 kb
Host smart-566870f9-8097-4ab9-a731-f2ffd028f28f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007998053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4007998053
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3160436677
Short name T891
Test name
Test status
Simulation time 42663430 ps
CPU time 0.9 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206016 kb
Host smart-b7b8e553-04ea-4c6e-a016-52aa7a39500b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160436677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3160436677
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3983800144
Short name T864
Test name
Test status
Simulation time 85244665 ps
CPU time 1.33 seconds
Started Mar 28 12:41:55 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 214716 kb
Host smart-585c650f-5052-4144-b94d-dd5b729ea20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983800144 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3983800144
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.777112983
Short name T901
Test name
Test status
Simulation time 19014018 ps
CPU time 0.82 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:41:31 PM PDT 24
Peak memory 206036 kb
Host smart-5382f9f8-4391-4e9b-a2fb-ec177d42077c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777112983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.777112983
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1547853342
Short name T874
Test name
Test status
Simulation time 41689599 ps
CPU time 0.87 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206172 kb
Host smart-9faa4c2c-0e75-4b65-bd5e-c4680235ec3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547853342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1547853342
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.135577000
Short name T960
Test name
Test status
Simulation time 41633311 ps
CPU time 1.6 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206324 kb
Host smart-4b51c9a3-e927-4110-9277-a5233bcc3b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135577000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.135577000
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3810461658
Short name T928
Test name
Test status
Simulation time 72089945 ps
CPU time 2.81 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 217488 kb
Host smart-78482002-0a3f-47b4-bea1-8e7630d72e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810461658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3810461658
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.181572746
Short name T961
Test name
Test status
Simulation time 53449874 ps
CPU time 1.74 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 206104 kb
Host smart-7b675cec-9675-4af9-9bdb-36794d953949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181572746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.181572746
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1161666057
Short name T948
Test name
Test status
Simulation time 14761054 ps
CPU time 0.88 seconds
Started Mar 28 12:41:49 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206120 kb
Host smart-db42ae50-82be-4fc3-96eb-4b5c15340f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161666057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1161666057
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1329281606
Short name T932
Test name
Test status
Simulation time 22107523 ps
CPU time 0.85 seconds
Started Mar 28 12:41:54 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 206260 kb
Host smart-5749f247-bedd-4ce5-b210-180148750e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329281606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1329281606
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.4237501674
Short name T888
Test name
Test status
Simulation time 13022571 ps
CPU time 0.84 seconds
Started Mar 28 12:41:51 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 206196 kb
Host smart-a5392c37-5327-4e5f-a1b5-cc25fa17b627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237501674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4237501674
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2191893526
Short name T895
Test name
Test status
Simulation time 33201634 ps
CPU time 0.85 seconds
Started Mar 28 12:41:49 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206108 kb
Host smart-16b41a2a-0b36-43dc-8672-adb35b15d6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191893526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2191893526
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.936959291
Short name T842
Test name
Test status
Simulation time 13757835 ps
CPU time 0.88 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206124 kb
Host smart-1c026d1e-3667-4fd5-9a03-8734b9054ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936959291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.936959291
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1287875066
Short name T865
Test name
Test status
Simulation time 14450502 ps
CPU time 0.85 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206304 kb
Host smart-4f18fe19-73a6-42c7-ac94-c0b455a617b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287875066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1287875066
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3008167785
Short name T896
Test name
Test status
Simulation time 22251966 ps
CPU time 0.84 seconds
Started Mar 28 12:41:49 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206300 kb
Host smart-1cad2a1f-92bd-497d-bf16-c5f0ef03a5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008167785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3008167785
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4098914709
Short name T853
Test name
Test status
Simulation time 12387108 ps
CPU time 0.79 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206196 kb
Host smart-682dab4c-0549-478f-abaa-0cb6bc9a4525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098914709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4098914709
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3801409638
Short name T966
Test name
Test status
Simulation time 14962833 ps
CPU time 0.86 seconds
Started Mar 28 12:41:53 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 206284 kb
Host smart-babd62c8-680f-42d3-a1e1-c81a55ac3b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801409638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3801409638
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3574817926
Short name T843
Test name
Test status
Simulation time 12019537 ps
CPU time 0.85 seconds
Started Mar 28 12:41:49 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206208 kb
Host smart-0a4bea75-c0fc-42f8-9780-f7807ff59382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574817926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3574817926
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3997632197
Short name T211
Test name
Test status
Simulation time 96843894 ps
CPU time 1.16 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206256 kb
Host smart-b04919c5-22ec-4d1b-b6fa-62e8ff021c6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997632197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3997632197
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4114861586
Short name T219
Test name
Test status
Simulation time 129405191 ps
CPU time 3.25 seconds
Started Mar 28 12:41:55 PM PDT 24
Finished Mar 28 12:41:59 PM PDT 24
Peak memory 206240 kb
Host smart-d6f56053-22c8-423f-826c-6723cf5da3c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114861586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4114861586
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.342192109
Short name T911
Test name
Test status
Simulation time 48040416 ps
CPU time 0.95 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206176 kb
Host smart-a6e2b262-5d87-4bae-8503-7f2452c15234
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342192109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.342192109
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4070521002
Short name T963
Test name
Test status
Simulation time 22481851 ps
CPU time 1.49 seconds
Started Mar 28 12:41:52 PM PDT 24
Finished Mar 28 12:41:56 PM PDT 24
Peak memory 214604 kb
Host smart-12142bc6-b630-423e-821d-d88898a93700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070521002 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4070521002
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2848153012
Short name T201
Test name
Test status
Simulation time 43466814 ps
CPU time 0.94 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 204576 kb
Host smart-9e65706c-a722-4931-a1ba-15cd5aa71b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848153012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2848153012
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.253074249
Short name T857
Test name
Test status
Simulation time 20466642 ps
CPU time 0.81 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 206080 kb
Host smart-359c90d3-a1ae-472e-a501-22f3cde6ca8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253074249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.253074249
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4280006476
Short name T223
Test name
Test status
Simulation time 31307653 ps
CPU time 1.31 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206412 kb
Host smart-39644376-d312-4e43-a563-c358296e6bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280006476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4280006476
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.44430273
Short name T944
Test name
Test status
Simulation time 35784998 ps
CPU time 2.38 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 212892 kb
Host smart-398af721-863b-4a3e-9be8-b1cd99c80d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44430273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.44430273
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.655526296
Short name T238
Test name
Test status
Simulation time 245434062 ps
CPU time 2.81 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 205836 kb
Host smart-3cbd4a3b-74e1-4486-a94c-6aba6364dfbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655526296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.655526296
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.868675524
Short name T855
Test name
Test status
Simulation time 36846143 ps
CPU time 0.85 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206284 kb
Host smart-83cf8324-dd29-4ecd-bcd7-3605eab8f4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868675524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.868675524
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2164706652
Short name T939
Test name
Test status
Simulation time 34090176 ps
CPU time 0.79 seconds
Started Mar 28 12:41:50 PM PDT 24
Finished Mar 28 12:41:51 PM PDT 24
Peak memory 206016 kb
Host smart-8b71d9cc-b043-44cf-8981-373cc2529a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164706652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2164706652
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.367255851
Short name T881
Test name
Test status
Simulation time 12198627 ps
CPU time 0.82 seconds
Started Mar 28 12:42:09 PM PDT 24
Finished Mar 28 12:42:10 PM PDT 24
Peak memory 206020 kb
Host smart-f88c3efc-91cc-4222-9159-e12632c8e17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367255851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.367255851
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3993125021
Short name T863
Test name
Test status
Simulation time 16604899 ps
CPU time 0.87 seconds
Started Mar 28 12:41:53 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 206120 kb
Host smart-e6cd796e-b85a-4f7c-8556-4d6bfff169ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993125021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3993125021
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2515379536
Short name T900
Test name
Test status
Simulation time 14116105 ps
CPU time 0.86 seconds
Started Mar 28 12:42:03 PM PDT 24
Finished Mar 28 12:42:04 PM PDT 24
Peak memory 206200 kb
Host smart-fec6e37c-f4c3-4c78-b1de-56626481e85a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515379536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2515379536
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1024333815
Short name T913
Test name
Test status
Simulation time 13151608 ps
CPU time 0.88 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206220 kb
Host smart-14489533-d411-4534-b778-e85e5adf81ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024333815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1024333815
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1099765193
Short name T931
Test name
Test status
Simulation time 193919311 ps
CPU time 0.86 seconds
Started Mar 28 12:42:00 PM PDT 24
Finished Mar 28 12:42:01 PM PDT 24
Peak memory 206176 kb
Host smart-15af3635-5f7d-46d0-8099-5d69bc9c1f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099765193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1099765193
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3586793949
Short name T907
Test name
Test status
Simulation time 44271282 ps
CPU time 0.83 seconds
Started Mar 28 12:41:50 PM PDT 24
Finished Mar 28 12:41:51 PM PDT 24
Peak memory 206016 kb
Host smart-960636f9-006f-4b28-ad6c-0b6939d57279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586793949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3586793949
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1205582291
Short name T854
Test name
Test status
Simulation time 15634794 ps
CPU time 0.89 seconds
Started Mar 28 12:42:04 PM PDT 24
Finished Mar 28 12:42:05 PM PDT 24
Peak memory 206176 kb
Host smart-f57c3c94-0429-430d-9094-4b24237d52a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205582291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1205582291
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2032613979
Short name T946
Test name
Test status
Simulation time 17540228 ps
CPU time 0.79 seconds
Started Mar 28 12:42:04 PM PDT 24
Finished Mar 28 12:42:05 PM PDT 24
Peak memory 205976 kb
Host smart-3ccce1c3-8e01-4244-8bcb-f875ed7f69f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032613979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2032613979
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1551583172
Short name T859
Test name
Test status
Simulation time 91135577 ps
CPU time 1.58 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 214596 kb
Host smart-514498fd-88b3-4d7f-b92c-6d3e94d88b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551583172 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1551583172
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1111651423
Short name T212
Test name
Test status
Simulation time 45498862 ps
CPU time 0.86 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206220 kb
Host smart-a06eb126-efae-48a0-b0b5-8ce5fb82baed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111651423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1111651423
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1820315664
Short name T970
Test name
Test status
Simulation time 24448063 ps
CPU time 0.9 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 206216 kb
Host smart-b75bc8f1-acf5-493f-a330-af7cc20ef1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820315664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1820315664
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1461217524
Short name T204
Test name
Test status
Simulation time 17620780 ps
CPU time 1.02 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 206460 kb
Host smart-7fdafff4-cb31-496b-9f8f-6dacc8876846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461217524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1461217524
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3602874390
Short name T903
Test name
Test status
Simulation time 97138605 ps
CPU time 2.07 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 214900 kb
Host smart-981423cf-15b1-43cb-8bc3-dba2e7c70339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602874390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3602874390
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2408672847
Short name T876
Test name
Test status
Simulation time 90174271 ps
CPU time 1.51 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 206344 kb
Host smart-17a12459-cd7a-4561-8112-1cee8197e1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408672847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2408672847
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2598088266
Short name T858
Test name
Test status
Simulation time 134139888 ps
CPU time 1.34 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 217576 kb
Host smart-bef9e8a9-a9b8-41ae-ab78-1c16ca9e2b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598088266 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2598088266
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.737334941
Short name T964
Test name
Test status
Simulation time 14457933 ps
CPU time 0.95 seconds
Started Mar 28 12:41:48 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206216 kb
Host smart-99612534-fad3-403a-a4cc-0dd843251f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737334941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.737334941
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.32911757
Short name T936
Test name
Test status
Simulation time 22637556 ps
CPU time 0.81 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206228 kb
Host smart-3929bb8d-4cb6-4e89-b0ab-8bfee570063b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32911757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.32911757
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2757816571
Short name T925
Test name
Test status
Simulation time 100063714 ps
CPU time 1.15 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 206328 kb
Host smart-ba4e3be0-aa0a-479b-a6fe-937a88e969d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757816571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2757816571
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4174384070
Short name T862
Test name
Test status
Simulation time 554421545 ps
CPU time 3.84 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 214716 kb
Host smart-de815bb6-38d9-4f57-8c5f-982238c348b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174384070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4174384070
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1426488247
Short name T893
Test name
Test status
Simulation time 364414113 ps
CPU time 1.78 seconds
Started Mar 28 12:41:47 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 206344 kb
Host smart-1f5f1c4a-9dea-4634-b36b-6e3c6659dc4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426488247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1426488247
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1482887889
Short name T935
Test name
Test status
Simulation time 18301634 ps
CPU time 1.04 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206396 kb
Host smart-cf09faf7-6450-4efc-aef7-4c3160f518fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482887889 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1482887889
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.270202945
Short name T861
Test name
Test status
Simulation time 21318388 ps
CPU time 0.83 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 206028 kb
Host smart-1f6a97f0-f5f6-4b9b-a788-e86d387ab068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270202945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.270202945
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2365818850
Short name T942
Test name
Test status
Simulation time 19339651 ps
CPU time 1.15 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 206316 kb
Host smart-bf2bae66-fd48-481b-86ca-777a1946d004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365818850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2365818850
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2613576711
Short name T971
Test name
Test status
Simulation time 36776472 ps
CPU time 2.22 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 214584 kb
Host smart-0492a964-9f03-49d1-944e-821e1d1f74b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613576711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2613576711
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2863864265
Short name T226
Test name
Test status
Simulation time 194164175 ps
CPU time 2.52 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 206348 kb
Host smart-35c4841d-8cf0-443e-93a2-a012c09f02a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863864265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2863864265
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3216522957
Short name T922
Test name
Test status
Simulation time 103262463 ps
CPU time 1.54 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 214680 kb
Host smart-5cccedfa-7b62-4175-ac7a-b197a3b0d8af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216522957 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3216522957
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2326336622
Short name T203
Test name
Test status
Simulation time 45596750 ps
CPU time 0.85 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 206248 kb
Host smart-3545e68b-cca4-4107-bfee-bfa8a96722de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326336622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2326336622
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1598485914
Short name T955
Test name
Test status
Simulation time 14125451 ps
CPU time 0.84 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 206260 kb
Host smart-fcdb7f70-d037-49f8-88f8-0622ff650576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598485914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1598485914
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3767263565
Short name T898
Test name
Test status
Simulation time 24797467 ps
CPU time 1.17 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206336 kb
Host smart-9e4dae72-930c-4ad1-abec-92e21adcebbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767263565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3767263565
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.638274609
Short name T965
Test name
Test status
Simulation time 79769517 ps
CPU time 1.61 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 214616 kb
Host smart-7ac12faa-2e86-4e17-a55f-26866b1aca8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638274609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.638274609
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2642329301
Short name T905
Test name
Test status
Simulation time 29074731 ps
CPU time 1.78 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 214656 kb
Host smart-5a753ba0-ce9e-4d78-8a85-15395e2f0d5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642329301 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2642329301
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.846896420
Short name T927
Test name
Test status
Simulation time 38334086 ps
CPU time 0.86 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:41:31 PM PDT 24
Peak memory 206028 kb
Host smart-b69c9800-9280-4e12-a580-d3f5a65b1f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846896420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.846896420
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3142481027
Short name T852
Test name
Test status
Simulation time 13234331 ps
CPU time 0.86 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 206260 kb
Host smart-de6fa291-4c08-44eb-93bf-3f29f0569b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142481027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3142481027
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4048637154
Short name T906
Test name
Test status
Simulation time 37990453 ps
CPU time 1.47 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 206284 kb
Host smart-1d12b886-2c1c-4e4f-b935-9e50e52aca0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048637154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4048637154
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4070021563
Short name T883
Test name
Test status
Simulation time 81692586 ps
CPU time 2.88 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 214656 kb
Host smart-8deec45d-ebfc-41a6-8f38-dfe51aeced03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070021563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4070021563
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2860704904
Short name T225
Test name
Test status
Simulation time 337667855 ps
CPU time 4 seconds
Started Mar 28 12:41:32 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 206444 kb
Host smart-10489ed7-38cd-4df0-a3c5-2a6fd1d3685f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860704904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2860704904
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1523848542
Short name T632
Test name
Test status
Simulation time 91680969 ps
CPU time 1.22 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 215640 kb
Host smart-75f8000d-74e3-4eb4-9f0e-ea939ecccd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523848542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1523848542
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.949823134
Short name T342
Test name
Test status
Simulation time 54258395 ps
CPU time 0.92 seconds
Started Mar 28 01:30:04 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 206556 kb
Host smart-da1ea7be-a342-48d9-8958-94732c4cd73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949823134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.949823134
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.824982436
Short name T178
Test name
Test status
Simulation time 160852790 ps
CPU time 0.86 seconds
Started Mar 28 01:30:04 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 215400 kb
Host smart-52626285-9e5b-415d-aba7-39b52d79173a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824982436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.824982436
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1817953165
Short name T57
Test name
Test status
Simulation time 33306942 ps
CPU time 1.05 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 229776 kb
Host smart-87154bd5-b033-44ee-a35e-fea4b6401c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817953165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1817953165
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3252256298
Short name T606
Test name
Test status
Simulation time 34040090 ps
CPU time 1.39 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 216516 kb
Host smart-f1ec175c-f449-4bfc-839c-2f9255cec07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252256298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3252256298
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1021806963
Short name T698
Test name
Test status
Simulation time 64012559 ps
CPU time 0.95 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 223904 kb
Host smart-ae5a2ba7-9f50-4c99-8514-ff6bd8ce6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021806963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1021806963
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.400240520
Short name T440
Test name
Test status
Simulation time 21323342 ps
CPU time 0.96 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 215344 kb
Host smart-5355a634-d947-4f68-b512-bc279014ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400240520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.400240520
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.25739677
Short name T446
Test name
Test status
Simulation time 420935054 ps
CPU time 4.6 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:06 PM PDT 24
Peak memory 216484 kb
Host smart-c3f8982c-daf0-48ff-b44a-22b9003af980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.25739677
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2344572723
Short name T186
Test name
Test status
Simulation time 36983829583 ps
CPU time 806.9 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:43:31 PM PDT 24
Peak memory 220900 kb
Host smart-8dcbf383-bcfc-4707-aba6-1190fe322d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344572723 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2344572723
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1707201775
Short name T141
Test name
Test status
Simulation time 46967387 ps
CPU time 1.27 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 215596 kb
Host smart-8470622f-953b-41c6-a388-6497595531e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707201775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1707201775
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1872563252
Short name T470
Test name
Test status
Simulation time 44215013 ps
CPU time 0.85 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 205972 kb
Host smart-5edf9958-11a4-4f4d-a73f-8d88caf19963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872563252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1872563252
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1669083881
Short name T53
Test name
Test status
Simulation time 42845995 ps
CPU time 1.34 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 216424 kb
Host smart-a7f8ee95-4dcc-46b6-ab92-faf50c6a8119
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669083881 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1669083881
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1952456343
Short name T50
Test name
Test status
Simulation time 47862168 ps
CPU time 1.01 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:29:58 PM PDT 24
Peak memory 219116 kb
Host smart-e30fb22e-824f-4602-b325-bdd0bb8ec8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952456343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1952456343
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2591905997
Short name T324
Test name
Test status
Simulation time 70702910 ps
CPU time 1.42 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:29:58 PM PDT 24
Peak memory 218420 kb
Host smart-44011373-98b8-4b85-8f7c-9390b13f4974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591905997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2591905997
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.780363456
Short name T767
Test name
Test status
Simulation time 23300390 ps
CPU time 1.06 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 215544 kb
Host smart-fb3e1b87-5827-4078-aca4-f84cfb97313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780363456 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.780363456
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3461012450
Short name T21
Test name
Test status
Simulation time 207306662 ps
CPU time 3.83 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 234800 kb
Host smart-bde3bb40-1219-4c0a-9e17-1bbce0980113
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461012450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3461012450
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2141012239
Short name T332
Test name
Test status
Simulation time 16287196 ps
CPU time 0.95 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 215292 kb
Host smart-92ce69e5-c2fc-4035-ac2d-172ea459115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141012239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2141012239
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3530926511
Short name T596
Test name
Test status
Simulation time 218030853 ps
CPU time 2.76 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 215316 kb
Host smart-07b8995d-27f3-483e-afcc-f49a0cd665a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530926511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3530926511
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4234957023
Short name T187
Test name
Test status
Simulation time 231977271135 ps
CPU time 2646.19 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 02:14:07 PM PDT 24
Peak memory 228536 kb
Host smart-54be887f-75f1-4aa4-b5af-bc3a5c5480d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234957023 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4234957023
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3338236310
Short name T806
Test name
Test status
Simulation time 47494215 ps
CPU time 0.96 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:38 PM PDT 24
Peak memory 206008 kb
Host smart-caca4cfb-e751-4e5f-845e-598c2a3a4f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338236310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3338236310
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.4190546855
Short name T94
Test name
Test status
Simulation time 16151816 ps
CPU time 0.9 seconds
Started Mar 28 01:30:15 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 215984 kb
Host smart-40dcb89e-7e41-41eb-b87c-e01979d459cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190546855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4190546855
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.3609623854
Short name T91
Test name
Test status
Simulation time 23656185 ps
CPU time 1.08 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 231332 kb
Host smart-2824fe66-e320-4c84-8e59-8b3b41dc3aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609623854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3609623854
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4018435768
Short name T480
Test name
Test status
Simulation time 49930764 ps
CPU time 1.61 seconds
Started Mar 28 01:30:23 PM PDT 24
Finished Mar 28 01:30:25 PM PDT 24
Peak memory 219052 kb
Host smart-2b760358-daaf-4a2e-8943-1002b9fc755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018435768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4018435768
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3338726028
Short name T678
Test name
Test status
Simulation time 70631088 ps
CPU time 0.84 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 215504 kb
Host smart-97c7cb0c-a1d8-45dc-88bf-3d39f381f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338726028 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3338726028
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2344024799
Short name T723
Test name
Test status
Simulation time 16047763 ps
CPU time 0.93 seconds
Started Mar 28 01:30:21 PM PDT 24
Finished Mar 28 01:30:22 PM PDT 24
Peak memory 215300 kb
Host smart-d3e12382-c1e6-4e32-a7e5-32a83db2eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344024799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2344024799
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2553597293
Short name T199
Test name
Test status
Simulation time 254611437 ps
CPU time 2.64 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:17 PM PDT 24
Peak memory 216480 kb
Host smart-5e7c2eab-4cb8-47e7-9d9a-68adc8963c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553597293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2553597293
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3132086513
Short name T192
Test name
Test status
Simulation time 1382638786854 ps
CPU time 1672.56 seconds
Started Mar 28 01:30:23 PM PDT 24
Finished Mar 28 01:58:16 PM PDT 24
Peak memory 223068 kb
Host smart-29f2077e-8dd0-4263-ae65-c3071f6f2faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132086513 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3132086513
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.4151935711
Short name T654
Test name
Test status
Simulation time 350782457 ps
CPU time 4.37 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:13 PM PDT 24
Peak memory 216800 kb
Host smart-e23afa2d-ea8e-42e9-bc48-9d6dd0d81a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151935711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4151935711
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1012158535
Short name T523
Test name
Test status
Simulation time 51636806 ps
CPU time 1.29 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 219276 kb
Host smart-37fe2c04-5842-467d-a6a5-485f1a32cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012158535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1012158535
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3228941131
Short name T765
Test name
Test status
Simulation time 74295566 ps
CPU time 1.42 seconds
Started Mar 28 01:31:59 PM PDT 24
Finished Mar 28 01:32:00 PM PDT 24
Peak memory 217996 kb
Host smart-b7350fd0-a03c-4500-aa0c-bb6881bb7018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228941131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3228941131
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2088618369
Short name T368
Test name
Test status
Simulation time 196747443 ps
CPU time 1.36 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216612 kb
Host smart-5559534a-8055-45f3-88e6-28daf32a2229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088618369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2088618369
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3743442298
Short name T409
Test name
Test status
Simulation time 69696592 ps
CPU time 1.02 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216584 kb
Host smart-c137e778-df31-4e92-99a9-b6cafdb28482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743442298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3743442298
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1713746934
Short name T590
Test name
Test status
Simulation time 60865467 ps
CPU time 1.43 seconds
Started Mar 28 01:32:04 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217908 kb
Host smart-22362880-a79f-4227-a21e-d5fb079cd1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713746934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1713746934
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1027375305
Short name T377
Test name
Test status
Simulation time 134981293 ps
CPU time 1.32 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216812 kb
Host smart-fce49fc3-9045-46f3-962b-ec7282117502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027375305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1027375305
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2719628681
Short name T460
Test name
Test status
Simulation time 133512868 ps
CPU time 1.91 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 219176 kb
Host smart-d24f62c1-bb42-474c-9305-b5771be4d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719628681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2719628681
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2784927676
Short name T517
Test name
Test status
Simulation time 46249944 ps
CPU time 1.14 seconds
Started Mar 28 01:32:04 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216664 kb
Host smart-2a636266-30f3-49b6-bb5a-1001dc4c1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784927676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2784927676
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.813474086
Short name T500
Test name
Test status
Simulation time 17183962 ps
CPU time 1.04 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:38 PM PDT 24
Peak memory 205968 kb
Host smart-8096b7a2-a06a-4639-8548-342fc36f403a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813474086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.813474086
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3743167270
Short name T100
Test name
Test status
Simulation time 14211237 ps
CPU time 0.96 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215988 kb
Host smart-e36cef4a-71cb-43b3-b776-e23446117f6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743167270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3743167270
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2900910449
Short name T74
Test name
Test status
Simulation time 66741118 ps
CPU time 1.04 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 229784 kb
Host smart-dde806f6-9205-4c9b-bf27-c4aa5f469b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900910449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2900910449
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2685304370
Short name T631
Test name
Test status
Simulation time 53781359 ps
CPU time 1.08 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 216656 kb
Host smart-1853aa41-f47a-4264-bb46-11923fddab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685304370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2685304370
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3365055485
Short name T293
Test name
Test status
Simulation time 25534665 ps
CPU time 1 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:40 PM PDT 24
Peak memory 215688 kb
Host smart-eee9e13e-bf56-4b8c-b8ed-3cd9f55b55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365055485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3365055485
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3291298494
Short name T337
Test name
Test status
Simulation time 18369821 ps
CPU time 1.04 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 215292 kb
Host smart-f9d603dd-9177-4202-aa93-ad48ad787ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291298494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3291298494
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1590089092
Short name T563
Test name
Test status
Simulation time 1179206827 ps
CPU time 3.83 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:43 PM PDT 24
Peak memory 215296 kb
Host smart-a38012c8-3990-489c-8182-e39b1bf3218f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590089092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1590089092
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1439497936
Short name T775
Test name
Test status
Simulation time 279990702908 ps
CPU time 1152.72 seconds
Started Mar 28 01:30:33 PM PDT 24
Finished Mar 28 01:49:46 PM PDT 24
Peak memory 222332 kb
Host smart-dc0665bd-d0e6-49f8-b818-19cf71450ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439497936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1439497936
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.2699353372
Short name T506
Test name
Test status
Simulation time 60109892 ps
CPU time 1.14 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 216552 kb
Host smart-a5acb4af-be0b-441a-a254-41d655523862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699353372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2699353372
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3134842024
Short name T737
Test name
Test status
Simulation time 65721365 ps
CPU time 1.01 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 218064 kb
Host smart-e3f64437-187b-4824-ac6e-0117e5751e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134842024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3134842024
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3068311393
Short name T548
Test name
Test status
Simulation time 78693018 ps
CPU time 1.21 seconds
Started Mar 28 01:31:59 PM PDT 24
Finished Mar 28 01:32:00 PM PDT 24
Peak memory 217884 kb
Host smart-c05c11d1-e65b-4489-ab8e-cc1e16ad7440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068311393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3068311393
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1976431821
Short name T258
Test name
Test status
Simulation time 61776189 ps
CPU time 2.34 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217840 kb
Host smart-7af5ff75-c44a-4cde-b324-7afbc82b06b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976431821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1976431821
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3364758487
Short name T289
Test name
Test status
Simulation time 43964696 ps
CPU time 1.74 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 217660 kb
Host smart-d73ffa68-15ed-4dd7-8e74-9483f698581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364758487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3364758487
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.944931249
Short name T561
Test name
Test status
Simulation time 50819465 ps
CPU time 1.11 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 217684 kb
Host smart-5c0b35c1-7b0a-4a2c-9df8-5463fb71c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944931249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.944931249
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1767826205
Short name T449
Test name
Test status
Simulation time 44266450 ps
CPU time 1.49 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 217716 kb
Host smart-b6989bf9-1bcb-4158-85a7-3334eb20ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767826205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1767826205
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.462758769
Short name T437
Test name
Test status
Simulation time 79184077 ps
CPU time 1.45 seconds
Started Mar 28 01:31:58 PM PDT 24
Finished Mar 28 01:31:59 PM PDT 24
Peak memory 218924 kb
Host smart-4b98df31-38a5-4f8e-a55a-fc17bf62a0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462758769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.462758769
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1479526709
Short name T9
Test name
Test status
Simulation time 47908102 ps
CPU time 1.78 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 217820 kb
Host smart-c2bc3dbd-f0ea-4895-8b20-0f8a268511d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479526709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1479526709
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1154487165
Short name T455
Test name
Test status
Simulation time 93535907 ps
CPU time 1.3 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215612 kb
Host smart-dbfd9db3-26fd-4529-9ebb-2dbd9ae87526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154487165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1154487165
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3451124378
Short name T794
Test name
Test status
Simulation time 35238859 ps
CPU time 1.12 seconds
Started Mar 28 01:30:34 PM PDT 24
Finished Mar 28 01:30:35 PM PDT 24
Peak memory 206780 kb
Host smart-d68469c2-ae0c-45fe-b71f-05a560105e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451124378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3451124378
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.647071590
Short name T634
Test name
Test status
Simulation time 11675892 ps
CPU time 0.99 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:38 PM PDT 24
Peak memory 215980 kb
Host smart-73de7236-f8d0-4b66-a93b-82e7f3711e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647071590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.647071590
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.541097126
Short name T618
Test name
Test status
Simulation time 39767293 ps
CPU time 1.28 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 216556 kb
Host smart-a9c078f6-8e64-4f80-9436-9375c4d70eb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541097126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.541097126
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.637937310
Short name T838
Test name
Test status
Simulation time 20811281 ps
CPU time 1.17 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 218112 kb
Host smart-32df1968-68e3-494c-aa3a-7e50553549b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637937310 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.637937310
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3782876703
Short name T452
Test name
Test status
Simulation time 52115191 ps
CPU time 2.01 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 218036 kb
Host smart-d4cc9864-fd7b-4324-96cf-a84dbbf85887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782876703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3782876703
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3608971480
Short name T627
Test name
Test status
Simulation time 27301147 ps
CPU time 1.01 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215412 kb
Host smart-d32a3b94-5d25-41b8-9f2a-92268fdca160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608971480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3608971480
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2192970296
Short name T294
Test name
Test status
Simulation time 58730964 ps
CPU time 0.98 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 215296 kb
Host smart-c32510aa-d409-46c7-827d-a715e0f0db68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192970296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2192970296
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3190436784
Short name T366
Test name
Test status
Simulation time 224120070 ps
CPU time 4.74 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:43 PM PDT 24
Peak memory 219120 kb
Host smart-e6fdeb5a-b9ad-4cb1-a34e-93bfa2048b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190436784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3190436784
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2346700395
Short name T622
Test name
Test status
Simulation time 132677546434 ps
CPU time 1045 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:48:02 PM PDT 24
Peak memory 222592 kb
Host smart-56d07325-e13e-40b1-ad93-e74e0e9786d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346700395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2346700395
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1315690908
Short name T580
Test name
Test status
Simulation time 36915830 ps
CPU time 1.65 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 217820 kb
Host smart-38f9c00e-80c4-4a33-b19f-e90f49239f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315690908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1315690908
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3690586412
Short name T304
Test name
Test status
Simulation time 50995242 ps
CPU time 1.72 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 217796 kb
Host smart-b29f37c6-4e0f-496d-afe2-8f75677c7c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690586412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3690586412
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.489481428
Short name T713
Test name
Test status
Simulation time 34767872 ps
CPU time 1.47 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217844 kb
Host smart-2b74c0b9-561c-4d49-85a0-5b159f649268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489481428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.489481428
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2066111311
Short name T579
Test name
Test status
Simulation time 48865884 ps
CPU time 1.39 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:02 PM PDT 24
Peak memory 218068 kb
Host smart-85ee9138-8db7-4c48-97db-8f9bc4f50779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066111311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2066111311
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2985812507
Short name T791
Test name
Test status
Simulation time 41882766 ps
CPU time 1.12 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 217920 kb
Host smart-5d9ad3a1-bd5e-4ee5-a4e8-ce14ff7f8356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985812507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2985812507
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.4133396449
Short name T799
Test name
Test status
Simulation time 50526081 ps
CPU time 1.41 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:02 PM PDT 24
Peak memory 216820 kb
Host smart-ea5a94ad-dc53-4f0b-84b8-61e0b5401e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133396449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4133396449
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3596402003
Short name T314
Test name
Test status
Simulation time 114669223 ps
CPU time 1.17 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 218092 kb
Host smart-01554701-a93a-4a95-88f1-4ac95fc2346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596402003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3596402003
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.202253070
Short name T30
Test name
Test status
Simulation time 69155211 ps
CPU time 1.85 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 217720 kb
Host smart-a2246f9e-cb49-453c-b656-526480dcf140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202253070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.202253070
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1226709172
Short name T326
Test name
Test status
Simulation time 2293054753 ps
CPU time 73.77 seconds
Started Mar 28 01:31:57 PM PDT 24
Finished Mar 28 01:33:11 PM PDT 24
Peak memory 218736 kb
Host smart-b67f9be5-e6fb-4583-a5e3-840617a3843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226709172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1226709172
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1408159931
Short name T491
Test name
Test status
Simulation time 48791398 ps
CPU time 1.42 seconds
Started Mar 28 01:32:04 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216656 kb
Host smart-ecb1c266-d9fd-4297-99df-790e17748527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408159931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1408159931
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1946048720
Short name T492
Test name
Test status
Simulation time 32222493 ps
CPU time 1.14 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 206120 kb
Host smart-4351032d-5d09-4cd2-8010-1c64ee40c3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946048720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1946048720
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.95614774
Short name T103
Test name
Test status
Simulation time 30567509 ps
CPU time 0.84 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215816 kb
Host smart-81151370-ef08-4d06-9fe4-2ffd5484d5a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95614774 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.95614774
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1296893830
Short name T354
Test name
Test status
Simulation time 175735793 ps
CPU time 1.15 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 217732 kb
Host smart-ebb0e38e-fabf-4b56-ad92-238e259bb363
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296893830 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1296893830
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.114646294
Short name T331
Test name
Test status
Simulation time 29040059 ps
CPU time 0.89 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:38 PM PDT 24
Peak memory 217608 kb
Host smart-f546e1e3-c3ce-4cbb-a7e0-42225e7e63a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114646294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.114646294
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.909567586
Short name T488
Test name
Test status
Simulation time 88909557 ps
CPU time 1.58 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 218252 kb
Host smart-e5212d9c-709e-4d02-acce-93d748a4e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909567586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.909567586
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1394567994
Short name T803
Test name
Test status
Simulation time 41189125 ps
CPU time 0.87 seconds
Started Mar 28 01:30:34 PM PDT 24
Finished Mar 28 01:30:35 PM PDT 24
Peak memory 215360 kb
Host smart-56c3aad0-bc89-4fab-8ab9-e90e55298567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394567994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1394567994
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4145454473
Short name T747
Test name
Test status
Simulation time 163778582 ps
CPU time 0.92 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215084 kb
Host smart-2412d029-7318-414a-987a-830fd988ec57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145454473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4145454473
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3796335603
Short name T181
Test name
Test status
Simulation time 94791522530 ps
CPU time 1155.73 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:49:54 PM PDT 24
Peak memory 223672 kb
Host smart-0bd07126-eaba-4331-be61-11d7e43863b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796335603 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3796335603
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1701686723
Short name T418
Test name
Test status
Simulation time 54544451 ps
CPU time 1.26 seconds
Started Mar 28 01:32:00 PM PDT 24
Finished Mar 28 01:32:02 PM PDT 24
Peak memory 216624 kb
Host smart-1cb5c54f-a3d1-47bd-86ab-1e881414f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701686723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1701686723
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2964932089
Short name T684
Test name
Test status
Simulation time 92349971 ps
CPU time 1.24 seconds
Started Mar 28 01:31:58 PM PDT 24
Finished Mar 28 01:32:00 PM PDT 24
Peak memory 217968 kb
Host smart-145f0ac4-a78d-420e-98ca-6d56a0d78b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964932089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2964932089
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3279339701
Short name T621
Test name
Test status
Simulation time 47560512 ps
CPU time 1.43 seconds
Started Mar 28 01:32:04 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217960 kb
Host smart-5e6f5bb8-e454-4af6-96ad-dca8792e899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279339701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3279339701
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3454496143
Short name T793
Test name
Test status
Simulation time 56692680 ps
CPU time 1.31 seconds
Started Mar 28 01:31:57 PM PDT 24
Finished Mar 28 01:31:59 PM PDT 24
Peak memory 219116 kb
Host smart-4b47a6fe-e25f-4d93-851a-ce34b0b92bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454496143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3454496143
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.385752159
Short name T833
Test name
Test status
Simulation time 44237498 ps
CPU time 1.41 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217828 kb
Host smart-299367a4-0ab2-4622-b042-f3d3b924405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385752159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.385752159
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.37369599
Short name T714
Test name
Test status
Simulation time 157932134 ps
CPU time 1.6 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 218084 kb
Host smart-791d4faf-bfb7-4360-91ea-9ad83ff59907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37369599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.37369599
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1226625472
Short name T641
Test name
Test status
Simulation time 30260047 ps
CPU time 1.37 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 216556 kb
Host smart-a36bd9df-3771-4ccf-ac0e-03f678e4ccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226625472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1226625472
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3467652599
Short name T489
Test name
Test status
Simulation time 64271272 ps
CPU time 1.3 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 216576 kb
Host smart-0e7ad413-6a6e-4d33-8790-8141095b3ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467652599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3467652599
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.456327044
Short name T339
Test name
Test status
Simulation time 451914213 ps
CPU time 1.3 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 216656 kb
Host smart-3e42371f-2559-41b7-8633-c2a4915dbf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456327044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.456327044
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3291969776
Short name T309
Test name
Test status
Simulation time 236706368 ps
CPU time 2.56 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217864 kb
Host smart-ea8076a2-ff7b-48a1-a92a-fc1e637d1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291969776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3291969776
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.3466421897
Short name T387
Test name
Test status
Simulation time 48077631 ps
CPU time 1.07 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 206088 kb
Host smart-2b8cbfbb-3dfe-4eeb-a347-83696b624b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466421897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3466421897
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.733297895
Short name T322
Test name
Test status
Simulation time 19281247 ps
CPU time 0.89 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 215692 kb
Host smart-36636a35-988c-4c9d-b2b4-3e56e5dc7834
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733297895 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.733297895
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.142742790
Short name T72
Test name
Test status
Simulation time 65678652 ps
CPU time 1.34 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 216272 kb
Host smart-8557fe55-468f-49e4-9134-e7f29b79254a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142742790 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.142742790
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.419040234
Short name T827
Test name
Test status
Simulation time 45184807 ps
CPU time 1.2 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:40 PM PDT 24
Peak memory 219100 kb
Host smart-0f183c9b-2e54-4105-8870-31faf1105d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419040234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.419040234
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.684617050
Short name T283
Test name
Test status
Simulation time 91754489 ps
CPU time 1.29 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 218524 kb
Host smart-83236cec-cbdc-4e80-888c-3bd2b8572b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684617050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.684617050
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.1864485961
Short name T773
Test name
Test status
Simulation time 158850715 ps
CPU time 0.92 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 215332 kb
Host smart-da8f5a10-d33e-476a-87f7-2df86eb06798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864485961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1864485961
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1274999408
Short name T35
Test name
Test status
Simulation time 525943313 ps
CPU time 3.28 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:43 PM PDT 24
Peak memory 216328 kb
Host smart-bf3ec981-8835-4da2-a016-95143c220d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274999408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1274999408
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1040971943
Short name T185
Test name
Test status
Simulation time 6527767745 ps
CPU time 35.06 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:31:15 PM PDT 24
Peak memory 216628 kb
Host smart-6324da7c-a77b-4f7f-a765-43dd6bfd9acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040971943 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1040971943
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1012861943
Short name T557
Test name
Test status
Simulation time 522307155 ps
CPU time 3.96 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 219464 kb
Host smart-d7a096bd-8599-402e-b9bb-f7d80a379227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012861943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1012861943
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.4000198338
Short name T511
Test name
Test status
Simulation time 40110235 ps
CPU time 1.42 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 216688 kb
Host smart-7155e894-c5f2-4bca-9dfb-fd0bb558eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000198338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4000198338
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2784962164
Short name T572
Test name
Test status
Simulation time 75905414 ps
CPU time 1.19 seconds
Started Mar 28 01:32:00 PM PDT 24
Finished Mar 28 01:32:01 PM PDT 24
Peak memory 216680 kb
Host smart-127e6216-0fdd-47e1-b4c3-36b854c4fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784962164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2784962164
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.815518907
Short name T193
Test name
Test status
Simulation time 123169159 ps
CPU time 1.12 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 215388 kb
Host smart-3a9219c3-b5e5-47b3-bf45-cc1f3cd54361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815518907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.815518907
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2371307832
Short name T536
Test name
Test status
Simulation time 64504717 ps
CPU time 1.07 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 218944 kb
Host smart-d127709e-daa4-43c1-88dd-59c2739d8220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371307832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2371307832
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.421720483
Short name T672
Test name
Test status
Simulation time 67540377 ps
CPU time 1.56 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 217956 kb
Host smart-e83d0579-7791-4277-a078-0fb91f980b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421720483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.421720483
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3769074916
Short name T697
Test name
Test status
Simulation time 338910223 ps
CPU time 2.18 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218104 kb
Host smart-c7341d4c-2403-4b5d-a303-037546277456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769074916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3769074916
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3165464847
Short name T570
Test name
Test status
Simulation time 67883895 ps
CPU time 1.16 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 215320 kb
Host smart-541b0e9a-148a-4ab2-90f9-e67522dd7f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165464847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3165464847
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2338294907
Short name T543
Test name
Test status
Simulation time 86572564 ps
CPU time 1.21 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215592 kb
Host smart-06725da9-0b88-45fa-8d13-6b273b0784bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338294907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2338294907
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.4142494030
Short name T98
Test name
Test status
Simulation time 11138149 ps
CPU time 0.88 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 215788 kb
Host smart-edfa92cb-9961-40e5-b729-77a3537b59f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142494030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4142494030
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2140883968
Short name T689
Test name
Test status
Simulation time 90900085 ps
CPU time 1.07 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 216564 kb
Host smart-a1c053fb-c68f-45b5-b921-eaf371592811
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140883968 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2140883968
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1965447697
Short name T168
Test name
Test status
Simulation time 34651757 ps
CPU time 0.98 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 219472 kb
Host smart-810211fb-07ab-4904-978d-75eff4186c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965447697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1965447697
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3239137626
Short name T268
Test name
Test status
Simulation time 34423517 ps
CPU time 1.47 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 217952 kb
Host smart-88232061-5553-494d-bdfb-eb4182c944e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239137626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3239137626
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2839870215
Short name T422
Test name
Test status
Simulation time 33415609 ps
CPU time 0.89 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 215328 kb
Host smart-60fe7007-04e6-48cc-ab52-f1a75a72e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839870215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2839870215
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2909152447
Short name T566
Test name
Test status
Simulation time 26535287 ps
CPU time 0.95 seconds
Started Mar 28 01:30:34 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 215320 kb
Host smart-fa876a2a-bcbe-4929-b45d-99f969b02c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909152447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2909152447
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3847160607
Short name T708
Test name
Test status
Simulation time 170363282 ps
CPU time 2.29 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:40 PM PDT 24
Peak memory 216500 kb
Host smart-4fe2184d-7001-4dcc-9e2b-4dd8429461e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847160607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3847160607
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1976364593
Short name T534
Test name
Test status
Simulation time 42997484779 ps
CPU time 1013.46 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:47:30 PM PDT 24
Peak memory 219104 kb
Host smart-229c9d7a-da72-41c5-a3d3-100a05dd3e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976364593 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1976364593
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.edn_genbits.480257978
Short name T282
Test name
Test status
Simulation time 508995520 ps
CPU time 2.93 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 216772 kb
Host smart-eb22d20d-b44c-42b4-8ecf-adcff2644a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480257978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.480257978
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3260073214
Short name T721
Test name
Test status
Simulation time 64324784 ps
CPU time 1.38 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 216548 kb
Host smart-ef225b62-a7f2-420a-9476-667cd2a9b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260073214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3260073214
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1080013887
Short name T802
Test name
Test status
Simulation time 278891946 ps
CPU time 1.45 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 218032 kb
Host smart-91d7e394-407c-4119-b49d-3a615422c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080013887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1080013887
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2358011287
Short name T424
Test name
Test status
Simulation time 90637468 ps
CPU time 1.23 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 217840 kb
Host smart-1690627a-efbf-4592-a651-e7695c99bfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358011287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2358011287
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2942736196
Short name T564
Test name
Test status
Simulation time 34842752 ps
CPU time 1.58 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 219436 kb
Host smart-d2bb51b0-bc47-478f-9a6c-ee00a8d6bc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942736196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2942736196
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2381292908
Short name T529
Test name
Test status
Simulation time 39008036 ps
CPU time 1.4 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 216784 kb
Host smart-66790374-4ea6-4950-931c-0920ab67f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381292908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2381292908
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1072900624
Short name T447
Test name
Test status
Simulation time 125309240 ps
CPU time 1.59 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 218140 kb
Host smart-67c8ed3b-616b-46c8-aadd-dd4da2768ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072900624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1072900624
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.2949213969
Short name T396
Test name
Test status
Simulation time 16399736 ps
CPU time 1 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 206796 kb
Host smart-c0409a6d-5c20-4d42-bd03-bc6e051f62ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949213969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2949213969
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.468141811
Short name T760
Test name
Test status
Simulation time 22317934 ps
CPU time 0.85 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215472 kb
Host smart-7fe887d2-2c9f-4bcb-8c5d-4e11eb03ca16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468141811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.468141811
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.126766813
Short name T828
Test name
Test status
Simulation time 67059999 ps
CPU time 0.97 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 219136 kb
Host smart-771eb7b0-0d29-4806-b02c-c8aeb13307ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126766813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.126766813
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2610545098
Short name T27
Test name
Test status
Simulation time 69381429 ps
CPU time 1.28 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 218064 kb
Host smart-11057b4f-760c-4084-851f-4e4db50facf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610545098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2610545098
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3162452174
Short name T29
Test name
Test status
Simulation time 25864001 ps
CPU time 1.02 seconds
Started Mar 28 01:30:34 PM PDT 24
Finished Mar 28 01:30:35 PM PDT 24
Peak memory 215740 kb
Host smart-3e82eec7-28dc-4064-9924-85c85ad32e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162452174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3162452174
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.640070056
Short name T544
Test name
Test status
Simulation time 29176475 ps
CPU time 0.99 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 215324 kb
Host smart-01b44779-1c2b-47c5-b53a-92ba7aadbc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640070056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.640070056
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4218827943
Short name T502
Test name
Test status
Simulation time 3113733967 ps
CPU time 3.85 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:43 PM PDT 24
Peak memory 216720 kb
Host smart-70662a19-718d-489c-98e2-3bf9156aba9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218827943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4218827943
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3769062609
Short name T604
Test name
Test status
Simulation time 190433532325 ps
CPU time 1260.54 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:51:38 PM PDT 24
Peak memory 224328 kb
Host smart-148b7840-eb59-4f70-a79e-cca379a6b5ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769062609 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3769062609
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1135439995
Short name T642
Test name
Test status
Simulation time 67646690 ps
CPU time 1.09 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 216692 kb
Host smart-7afab27d-f607-4988-9c8a-3261c2cbeef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135439995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1135439995
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4065460071
Short name T540
Test name
Test status
Simulation time 34801242 ps
CPU time 1.71 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217908 kb
Host smart-7ef0746e-1d04-41bb-b608-b66b20feb3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065460071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4065460071
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2628522749
Short name T817
Test name
Test status
Simulation time 42863964 ps
CPU time 1.19 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 216764 kb
Host smart-07d1c4b6-eb48-4ce6-839b-e5adebc6488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628522749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2628522749
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3777492766
Short name T59
Test name
Test status
Simulation time 328265879 ps
CPU time 3.93 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:18 PM PDT 24
Peak memory 219256 kb
Host smart-2dbca26d-fb6f-499d-95e7-265ccd6fe191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777492766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3777492766
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.1324964988
Short name T400
Test name
Test status
Simulation time 196961704 ps
CPU time 2.84 seconds
Started Mar 28 01:32:11 PM PDT 24
Finished Mar 28 01:32:14 PM PDT 24
Peak memory 219076 kb
Host smart-71f69f95-b5fd-4853-85e0-26255c1c86e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324964988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1324964988
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3462700031
Short name T328
Test name
Test status
Simulation time 48302987 ps
CPU time 1.28 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217952 kb
Host smart-cab45be1-4319-4886-a6f6-1b761bf76a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462700031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3462700031
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1041125759
Short name T730
Test name
Test status
Simulation time 56204099 ps
CPU time 1.22 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 216656 kb
Host smart-5fb627b7-9dc0-4100-81f4-f65df8a5dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041125759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1041125759
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2490197601
Short name T303
Test name
Test status
Simulation time 87526897 ps
CPU time 1.33 seconds
Started Mar 28 01:32:10 PM PDT 24
Finished Mar 28 01:32:12 PM PDT 24
Peak memory 216760 kb
Host smart-f2f8966f-d7f5-43a7-b377-4ec9d7f23bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490197601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2490197601
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.2645634141
Short name T476
Test name
Test status
Simulation time 45372429 ps
CPU time 0.87 seconds
Started Mar 28 01:30:35 PM PDT 24
Finished Mar 28 01:30:36 PM PDT 24
Peak memory 205768 kb
Host smart-d65613e9-d0bd-4972-b424-ba934da00bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645634141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2645634141
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.4076515170
Short name T146
Test name
Test status
Simulation time 65896790 ps
CPU time 0.83 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215824 kb
Host smart-74f3f29d-61cd-4a40-9134-c650027cb298
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076515170 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4076515170
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1053985964
Short name T699
Test name
Test status
Simulation time 76898321 ps
CPU time 1.1 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 216432 kb
Host smart-97166967-bd0f-4dfc-b25e-61a8510b40f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053985964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1053985964
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.2577374900
Short name T278
Test name
Test status
Simulation time 70148885 ps
CPU time 2.42 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 219004 kb
Host smart-a8c2aff4-8202-4f87-9e29-e1fd2c94d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577374900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2577374900
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.408444214
Short name T388
Test name
Test status
Simulation time 18919681 ps
CPU time 1.04 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215316 kb
Host smart-07b8900a-fb83-4cdd-8a70-621b3bd13beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408444214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.408444214
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2130010682
Short name T464
Test name
Test status
Simulation time 538744888 ps
CPU time 3.47 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215292 kb
Host smart-00a364bd-ad5f-4776-a859-31f49a64ea08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130010682 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2130010682
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1951897240
Short name T611
Test name
Test status
Simulation time 393836402138 ps
CPU time 2306.69 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 02:09:07 PM PDT 24
Peak memory 230324 kb
Host smart-ce743d38-87fa-4e5b-b9db-5009eb2d803f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951897240 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1951897240
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3000141944
Short name T371
Test name
Test status
Simulation time 102726879 ps
CPU time 1.73 seconds
Started Mar 28 01:32:10 PM PDT 24
Finished Mar 28 01:32:12 PM PDT 24
Peak memory 218252 kb
Host smart-4f5a99b4-107e-40b9-a307-112e5e6a3094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000141944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3000141944
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.12175833
Short name T599
Test name
Test status
Simulation time 206660578 ps
CPU time 3.3 seconds
Started Mar 28 01:32:00 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 218272 kb
Host smart-72446f28-a946-4261-bbc7-7320c5fabc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12175833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.12175833
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2770508428
Short name T231
Test name
Test status
Simulation time 95955620 ps
CPU time 1.37 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217952 kb
Host smart-580ceadc-7f32-46ff-8482-01a90d68a628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770508428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2770508428
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2459354116
Short name T266
Test name
Test status
Simulation time 103094400 ps
CPU time 1.66 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 218208 kb
Host smart-4b633b0a-2324-415c-98a7-9919c64edf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459354116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2459354116
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2865318902
Short name T700
Test name
Test status
Simulation time 43814418 ps
CPU time 1.48 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 215264 kb
Host smart-26f48e46-7b84-47e5-b579-5b349d02deea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865318902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2865318902
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1129106632
Short name T138
Test name
Test status
Simulation time 52468113 ps
CPU time 1.31 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 217856 kb
Host smart-8e7b9d89-446b-4b16-a63f-cadb88ce4fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129106632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1129106632
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.454181503
Short name T259
Test name
Test status
Simulation time 73396969 ps
CPU time 1.36 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 218172 kb
Host smart-c919d194-6a29-4ddb-911e-f0c8d2f0add7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454181503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.454181503
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2260347452
Short name T274
Test name
Test status
Simulation time 75632167 ps
CPU time 1.15 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 216632 kb
Host smart-a0c40289-5148-4cf3-ad53-1f9139a61b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260347452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2260347452
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3209845231
Short name T542
Test name
Test status
Simulation time 52106950 ps
CPU time 1.71 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 217624 kb
Host smart-d412f74a-2d68-4eb7-a7fa-41a66fc50812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209845231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3209845231
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1715226199
Short name T228
Test name
Test status
Simulation time 199771297 ps
CPU time 1.3 seconds
Started Mar 28 01:30:42 PM PDT 24
Finished Mar 28 01:30:44 PM PDT 24
Peak memory 215464 kb
Host smart-9b97adf3-2ded-49a4-8987-67fd06614a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715226199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1715226199
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3678841128
Short name T288
Test name
Test status
Simulation time 22076004 ps
CPU time 0.89 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 206400 kb
Host smart-0ea029d2-e993-4363-8868-ecbe3405bbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678841128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3678841128
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4289070131
Short name T171
Test name
Test status
Simulation time 24518241 ps
CPU time 1.06 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 216568 kb
Host smart-b4c1c7cb-f5e7-4466-bf43-e00e47c8603a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289070131 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4289070131
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.3555646937
Short name T355
Test name
Test status
Simulation time 65724455 ps
CPU time 1.38 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:38 PM PDT 24
Peak memory 216696 kb
Host smart-71591889-25e6-4123-a0c9-778e5ec5f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555646937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3555646937
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1581789610
Short name T725
Test name
Test status
Simulation time 30094919 ps
CPU time 0.91 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:40 PM PDT 24
Peak memory 215484 kb
Host smart-df75ccc5-f019-491c-8ad1-bb67216f77b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581789610 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1581789610
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3336166801
Short name T439
Test name
Test status
Simulation time 49708178 ps
CPU time 1.01 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215344 kb
Host smart-e83b8c38-6c2b-468a-98f0-549ce012d517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336166801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3336166801
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1573839295
Short name T790
Test name
Test status
Simulation time 1240830458 ps
CPU time 3.42 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:43 PM PDT 24
Peak memory 216192 kb
Host smart-c1032f7b-2990-46b7-a123-c82a67dc4d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573839295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1573839295
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1695820910
Short name T335
Test name
Test status
Simulation time 100500198346 ps
CPU time 2228.51 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 02:07:48 PM PDT 24
Peak memory 227352 kb
Host smart-5a4434a4-f28b-4054-9ffa-6a9ab1ab01f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695820910 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1695820910
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.142708956
Short name T538
Test name
Test status
Simulation time 286432578 ps
CPU time 3.89 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 217796 kb
Host smart-f168f40a-8136-4e7c-8db4-a15b1a5458c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142708956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.142708956
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3910528709
Short name T351
Test name
Test status
Simulation time 43556966 ps
CPU time 1.82 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217896 kb
Host smart-a79a45c6-8990-4b07-be34-14db895d58f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910528709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3910528709
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.81785372
Short name T423
Test name
Test status
Simulation time 135879557 ps
CPU time 1.47 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217944 kb
Host smart-6dbe4e91-7666-4c74-b9bc-f1774c1afa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81785372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.81785372
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.905773926
Short name T392
Test name
Test status
Simulation time 47345759 ps
CPU time 1.87 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217764 kb
Host smart-ec43c216-958f-4b39-9562-3e608364b244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905773926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.905773926
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3786598040
Short name T13
Test name
Test status
Simulation time 27821509 ps
CPU time 1.16 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 217940 kb
Host smart-5bfafa0a-759f-4bff-ab24-1795d6897bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786598040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3786598040
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1029946843
Short name T312
Test name
Test status
Simulation time 98964207 ps
CPU time 1.71 seconds
Started Mar 28 01:32:04 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 218132 kb
Host smart-534afe20-3ea6-4909-838c-6a45d7a6f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029946843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1029946843
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2763868981
Short name T646
Test name
Test status
Simulation time 36695468 ps
CPU time 1.47 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217780 kb
Host smart-a7fccb13-7d63-419a-a9d9-6cf8b44f214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763868981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2763868981
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2323189797
Short name T768
Test name
Test status
Simulation time 54258488 ps
CPU time 1.8 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217604 kb
Host smart-659838ff-75af-4dab-9135-88bcdf6fce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323189797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2323189797
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2456898661
Short name T361
Test name
Test status
Simulation time 101653118 ps
CPU time 1.23 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 216632 kb
Host smart-253b00c9-c71e-471e-9087-3aa33616363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456898661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2456898661
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.536246605
Short name T84
Test name
Test status
Simulation time 31966594 ps
CPU time 1.24 seconds
Started Mar 28 01:30:40 PM PDT 24
Finished Mar 28 01:30:42 PM PDT 24
Peak memory 215608 kb
Host smart-c289535f-53ae-4622-b2ba-9f9782c8feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536246605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.536246605
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1306348917
Short name T688
Test name
Test status
Simulation time 45412962 ps
CPU time 0.85 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 205916 kb
Host smart-c59bb010-04e3-41b9-bb12-608d809dfed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306348917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1306348917
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.994937063
Short name T172
Test name
Test status
Simulation time 10969291 ps
CPU time 0.88 seconds
Started Mar 28 01:30:36 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 215976 kb
Host smart-36f24c83-85c6-47f2-a5b5-f5eafb2f912c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994937063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.994937063
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.3207295368
Short name T733
Test name
Test status
Simulation time 64326442 ps
CPU time 1.13 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 220100 kb
Host smart-acf987f8-4849-49ff-b1ab-bc44111a37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207295368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3207295368
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2090345068
Short name T494
Test name
Test status
Simulation time 107521123 ps
CPU time 1.38 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 219252 kb
Host smart-76220fa4-9c74-4a39-9054-0c7a20c77968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090345068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2090345068
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3963525660
Short name T119
Test name
Test status
Simulation time 30500545 ps
CPU time 0.89 seconds
Started Mar 28 01:30:37 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215496 kb
Host smart-80e39d0e-7096-4e51-b3a3-255e9c88fb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963525660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3963525660
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3262573725
Short name T568
Test name
Test status
Simulation time 166323011 ps
CPU time 0.94 seconds
Started Mar 28 01:30:38 PM PDT 24
Finished Mar 28 01:30:39 PM PDT 24
Peak memory 215284 kb
Host smart-defb8241-7c4a-437e-8ee1-4077894773f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262573725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3262573725
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.707131359
Short name T822
Test name
Test status
Simulation time 127986523 ps
CPU time 1.31 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 215180 kb
Host smart-8c60b5f0-4e54-4ffe-ae24-7888648d015b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707131359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.707131359
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.751388977
Short name T727
Test name
Test status
Simulation time 104013686562 ps
CPU time 539.59 seconds
Started Mar 28 01:30:39 PM PDT 24
Finished Mar 28 01:39:39 PM PDT 24
Peak memory 219328 kb
Host smart-1690b769-2228-42d8-8f0e-216f47cdb89b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751388977 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.751388977
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.edn_genbits.1706536370
Short name T330
Test name
Test status
Simulation time 43130741 ps
CPU time 1.71 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 216608 kb
Host smart-c25bf5a6-c0ef-41c3-b861-5c223aab5334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706536370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1706536370
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3731361636
Short name T14
Test name
Test status
Simulation time 28910648 ps
CPU time 1.26 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 218972 kb
Host smart-7e3ad609-13a0-4b37-9fe0-4148d084d915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731361636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3731361636
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3700466639
Short name T133
Test name
Test status
Simulation time 58234590 ps
CPU time 1.29 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 217780 kb
Host smart-40963708-4328-4a6d-ba36-1ebfaf89c6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700466639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3700466639
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2226666015
Short name T809
Test name
Test status
Simulation time 78949471 ps
CPU time 1.46 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 218260 kb
Host smart-e31b2e93-9ab4-4b7a-b847-6f3b4964e4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226666015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2226666015
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2553677074
Short name T306
Test name
Test status
Simulation time 64517107 ps
CPU time 1.71 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 217560 kb
Host smart-2b9f6c31-1017-492f-a41e-aa31c8ef59ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553677074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2553677074
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.586986392
Short name T435
Test name
Test status
Simulation time 40871934 ps
CPU time 1.82 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 216812 kb
Host smart-0dc98c69-0f5d-42a3-87c9-44544cb0dc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586986392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.586986392
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.330163040
Short name T359
Test name
Test status
Simulation time 84182208 ps
CPU time 1 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216652 kb
Host smart-ce0f2a46-af29-49ce-a029-1affbabb8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330163040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.330163040
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3677854362
Short name T508
Test name
Test status
Simulation time 89849757 ps
CPU time 3.39 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 219420 kb
Host smart-8d92b6e1-447f-4dd3-9fca-94322f4deae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677854362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3677854362
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3198549817
Short name T255
Test name
Test status
Simulation time 46538466 ps
CPU time 1.28 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 215512 kb
Host smart-22c2295a-04fe-499b-a477-03960e20cf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198549817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3198549817
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2049963782
Short name T323
Test name
Test status
Simulation time 24452627 ps
CPU time 0.94 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 206800 kb
Host smart-d10e25f9-7719-45e0-9c3f-205f364a5a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049963782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2049963782
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_err.991852864
Short name T66
Test name
Test status
Simulation time 57768473 ps
CPU time 0.99 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 218080 kb
Host smart-7c58e7ed-a053-4a3b-8a7d-968e176ab1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991852864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.991852864
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4156970477
Short name T129
Test name
Test status
Simulation time 39850997 ps
CPU time 1.45 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 217992 kb
Host smart-311e8f8e-5966-4c9b-a60c-85faf561ca79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156970477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4156970477
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.426675835
Short name T704
Test name
Test status
Simulation time 22158680 ps
CPU time 1.06 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 215428 kb
Host smart-82da69c3-e169-4bf2-9cf9-67be0baaa4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426675835 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.426675835
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2448242622
Short name T629
Test name
Test status
Simulation time 25427941 ps
CPU time 0.97 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 207144 kb
Host smart-6de8ecb2-f625-4d17-a7df-36bea1b3e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448242622 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2448242622
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.3929641801
Short name T350
Test name
Test status
Simulation time 23127923 ps
CPU time 0.9 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 215320 kb
Host smart-485b59d8-a16b-44b9-9e71-91c313aa1bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929641801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3929641801
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2295185414
Short name T668
Test name
Test status
Simulation time 765556545 ps
CPU time 2.34 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 216796 kb
Host smart-24a4bfb5-47f7-4b23-9f45-a1ca9c512a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295185414 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2295185414
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3923294821
Short name T279
Test name
Test status
Simulation time 41475308942 ps
CPU time 544.11 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:39:04 PM PDT 24
Peak memory 219152 kb
Host smart-69e79b9c-156d-424a-ae77-2960ffd7e7e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923294821 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3923294821
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1830503333
Short name T682
Test name
Test status
Simulation time 21927205 ps
CPU time 1.16 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 215648 kb
Host smart-3a5a9a50-b0c8-4f13-b879-ef5069f4b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830503333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1830503333
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.504252
Short name T592
Test name
Test status
Simulation time 43509247 ps
CPU time 0.89 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 205944 kb
Host smart-a621bea1-3906-4e52-a6ba-611dba1d77e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.504252
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2779027467
Short name T82
Test name
Test status
Simulation time 17508115 ps
CPU time 0.97 seconds
Started Mar 28 01:30:49 PM PDT 24
Finished Mar 28 01:30:50 PM PDT 24
Peak memory 216040 kb
Host smart-815b1117-d40d-4814-9288-be4b5fa31c0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779027467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2779027467
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.700122864
Short name T39
Test name
Test status
Simulation time 57307184 ps
CPU time 1.12 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 231316 kb
Host smart-36b9600f-1028-4d61-bef4-61f201561193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700122864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.700122864
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2099531995
Short name T443
Test name
Test status
Simulation time 41961435 ps
CPU time 1.55 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216772 kb
Host smart-e455bab8-6006-48a1-9389-d08a02ab5061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099531995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2099531995
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1868786509
Short name T746
Test name
Test status
Simulation time 19543568 ps
CPU time 1.06 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215668 kb
Host smart-4cc5e818-3267-42d3-8b2e-39fdf7098c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868786509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1868786509
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1006212714
Short name T427
Test name
Test status
Simulation time 19827918 ps
CPU time 1.01 seconds
Started Mar 28 01:30:50 PM PDT 24
Finished Mar 28 01:30:51 PM PDT 24
Peak memory 215432 kb
Host smart-82876121-ee6c-45c3-8d14-f1fd35a4db64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006212714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1006212714
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2183700195
Short name T197
Test name
Test status
Simulation time 162526726 ps
CPU time 3.62 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216544 kb
Host smart-1a88171c-9161-412e-b43f-494bb35e82dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183700195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2183700195
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3125654846
Short name T189
Test name
Test status
Simulation time 152664833733 ps
CPU time 889.16 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:45:42 PM PDT 24
Peak memory 223592 kb
Host smart-e22b5e05-73c5-4940-8f86-c4db78fe742b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125654846 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3125654846
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.326994658
Short name T115
Test name
Test status
Simulation time 56019470 ps
CPU time 1.23 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218104 kb
Host smart-d008874d-744a-4215-a96e-8d7c0e684cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326994658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.326994658
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3017921200
Short name T616
Test name
Test status
Simulation time 66465404 ps
CPU time 1.34 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 218096 kb
Host smart-ded6be75-f87c-44b4-9e31-58f3f73ea69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017921200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3017921200
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1284022345
Short name T635
Test name
Test status
Simulation time 44944383 ps
CPU time 1.18 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 216512 kb
Host smart-83493e0e-57d5-4e3a-9291-0357d28bfb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284022345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1284022345
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4209342228
Short name T453
Test name
Test status
Simulation time 50628016 ps
CPU time 1.46 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 217600 kb
Host smart-ff648cb4-002c-4f74-9908-136732eaa2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209342228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4209342228
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4280361327
Short name T531
Test name
Test status
Simulation time 123520021 ps
CPU time 1.33 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218020 kb
Host smart-b6e5c7ab-814a-411f-b83c-7b1afe56c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280361327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4280361327
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3714718849
Short name T301
Test name
Test status
Simulation time 70618959 ps
CPU time 1.16 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 217980 kb
Host smart-dc94484f-cb49-4fe6-9135-155b059ba426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714718849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3714718849
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1219562574
Short name T664
Test name
Test status
Simulation time 118125537 ps
CPU time 1.09 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 216644 kb
Host smart-46a01446-7639-4c53-97fb-97c6cfb15bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219562574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1219562574
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3692118206
Short name T608
Test name
Test status
Simulation time 116540430 ps
CPU time 1.55 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218192 kb
Host smart-cf0691aa-27f7-4ed2-9b38-aabd9474d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692118206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3692118206
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3524890349
Short name T751
Test name
Test status
Simulation time 61840209 ps
CPU time 1.48 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 217788 kb
Host smart-1c6927ee-83e4-49e6-b5e7-acd33a789166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524890349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3524890349
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4103099715
Short name T706
Test name
Test status
Simulation time 150537572 ps
CPU time 1.65 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218152 kb
Host smart-2cc79a2a-4c41-465e-89b0-6e5b9c21b123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103099715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4103099715
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.322460146
Short name T474
Test name
Test status
Simulation time 64343216 ps
CPU time 1.26 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215656 kb
Host smart-2a3c90d5-c869-4fbd-b6d0-2a435a3dfdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322460146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.322460146
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3952923580
Short name T718
Test name
Test status
Simulation time 14729798 ps
CPU time 0.87 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 205864 kb
Host smart-99ce4682-5f2c-4572-a825-ad6e3fe073d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952923580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3952923580
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.259267556
Short name T154
Test name
Test status
Simulation time 14314992 ps
CPU time 0.94 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 216168 kb
Host smart-718907e0-441d-4318-a4ea-216d8f3f8aad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259267556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.259267556
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1681963347
Short name T65
Test name
Test status
Simulation time 34214905 ps
CPU time 1.16 seconds
Started Mar 28 01:30:49 PM PDT 24
Finished Mar 28 01:30:50 PM PDT 24
Peak memory 217756 kb
Host smart-52405311-8ba8-4951-8fb9-2975d704f2c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681963347 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1681963347
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.294053345
Short name T719
Test name
Test status
Simulation time 72902564 ps
CPU time 1.14 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 219132 kb
Host smart-c16f5af3-0d3d-48d6-b577-047130fcb52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294053345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.294053345
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3622072627
Short name T345
Test name
Test status
Simulation time 54733892 ps
CPU time 1.25 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 217856 kb
Host smart-533440af-6249-4ac9-964e-0e83fcc66b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622072627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3622072627
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2894471638
Short name T107
Test name
Test status
Simulation time 21358260 ps
CPU time 1.09 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215568 kb
Host smart-eca92155-dd74-4d9f-b60e-9bc4abaac06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894471638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2894471638
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3897436792
Short name T321
Test name
Test status
Simulation time 16287841 ps
CPU time 0.96 seconds
Started Mar 28 01:30:50 PM PDT 24
Finished Mar 28 01:30:51 PM PDT 24
Peak memory 215320 kb
Host smart-7b6bb394-9015-44f3-b7e4-43a2a1008393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897436792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3897436792
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1789263968
Short name T610
Test name
Test status
Simulation time 509076850 ps
CPU time 5.33 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 216600 kb
Host smart-aee57a87-b0ec-4e20-961d-6e1f65831819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789263968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1789263968
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.671373523
Short name T724
Test name
Test status
Simulation time 2640482757093 ps
CPU time 4398.77 seconds
Started Mar 28 01:30:49 PM PDT 24
Finished Mar 28 02:44:08 PM PDT 24
Peak memory 237552 kb
Host smart-8601b68d-090d-4b68-91e8-a35831f83e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671373523 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.671373523
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.9302537
Short name T614
Test name
Test status
Simulation time 82314527 ps
CPU time 1.11 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216632 kb
Host smart-636965a2-ef47-45ff-9ec2-4df33a9b91fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9302537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.9302537
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.952331536
Short name T384
Test name
Test status
Simulation time 135549240 ps
CPU time 2.95 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:17 PM PDT 24
Peak memory 219312 kb
Host smart-9bebcbac-6fc0-49bc-8132-dc049e8c2ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952331536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.952331536
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1176898265
Short name T624
Test name
Test status
Simulation time 64019240 ps
CPU time 1.21 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 218000 kb
Host smart-d197c977-901e-4c27-a89d-983858e44960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176898265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1176898265
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.698849088
Short name T512
Test name
Test status
Simulation time 31682622 ps
CPU time 1.07 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216400 kb
Host smart-bc136730-39cf-4a3e-b440-c884d7fe0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698849088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.698849088
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3453191956
Short name T412
Test name
Test status
Simulation time 70044388 ps
CPU time 1.09 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217876 kb
Host smart-0b588346-b804-4661-920f-5fc8f7bb9a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453191956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3453191956
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.540079757
Short name T681
Test name
Test status
Simulation time 45461389 ps
CPU time 1.63 seconds
Started Mar 28 01:32:13 PM PDT 24
Finished Mar 28 01:32:14 PM PDT 24
Peak memory 216548 kb
Host smart-d7a6b7fb-a932-4bb4-b636-e5ba5f6a2870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540079757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.540079757
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4098754875
Short name T636
Test name
Test status
Simulation time 44712726 ps
CPU time 1.65 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 217976 kb
Host smart-222f87bc-4ec7-4efd-8257-d74af5f98345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098754875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4098754875
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.227314375
Short name T603
Test name
Test status
Simulation time 43340916 ps
CPU time 1.85 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217972 kb
Host smart-bb689f6d-7826-4696-a269-ab3e41949ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227314375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.227314375
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1160562602
Short name T469
Test name
Test status
Simulation time 34947482 ps
CPU time 1.21 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 217840 kb
Host smart-87929f21-ab5f-41ca-b65f-18ca0b3567c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160562602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1160562602
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.4055756884
Short name T686
Test name
Test status
Simulation time 61013722 ps
CPU time 1.16 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215468 kb
Host smart-62aad37b-c928-428e-98c6-c50fd4ee02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055756884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4055756884
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2207356781
Short name T144
Test name
Test status
Simulation time 14400075 ps
CPU time 0.9 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 206496 kb
Host smart-08d4e860-cd93-4a25-abd6-0256e57cb13e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207356781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2207356781
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3106583798
Short name T114
Test name
Test status
Simulation time 45642857 ps
CPU time 1.19 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216540 kb
Host smart-66014ea9-973b-49f0-bf09-5153ff01bfca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106583798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3106583798
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.414731964
Short name T356
Test name
Test status
Simulation time 33555367 ps
CPU time 1.56 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 233420 kb
Host smart-08e99ec5-e7a4-47ab-9fe2-52535304e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414731964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.414731964
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2572759376
Short name T265
Test name
Test status
Simulation time 27777792 ps
CPU time 1.23 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 216508 kb
Host smart-7a6ce042-7091-45dd-88e5-f350832f5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572759376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2572759376
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3061606496
Short name T5
Test name
Test status
Simulation time 19655261 ps
CPU time 1.06 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215668 kb
Host smart-6a48a297-7ab3-4f8b-9597-342f8b952cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061606496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3061606496
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3038201609
Short name T390
Test name
Test status
Simulation time 19527283 ps
CPU time 0.96 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215356 kb
Host smart-5ec8b5d4-82bc-4a3b-bb2e-7308696701de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038201609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3038201609
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1501375429
Short name T755
Test name
Test status
Simulation time 411495272 ps
CPU time 1.61 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215332 kb
Host smart-1ec1140c-c2ff-4eda-acab-e88b74e32585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501375429 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1501375429
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.448002471
Short name T707
Test name
Test status
Simulation time 65432388854 ps
CPU time 782.15 seconds
Started Mar 28 01:30:50 PM PDT 24
Finished Mar 28 01:43:52 PM PDT 24
Peak memory 219516 kb
Host smart-791e674e-99a0-4a9a-acfc-71f8146612c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448002471 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.448002471
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.4002398733
Short name T434
Test name
Test status
Simulation time 77406922 ps
CPU time 1.16 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 218236 kb
Host smart-d9820172-fc62-49c9-8458-5304bb0c398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002398733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4002398733
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3547838565
Short name T560
Test name
Test status
Simulation time 45644291 ps
CPU time 1.43 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 215260 kb
Host smart-b5b0eae7-bcaf-4aad-bac0-3119ecedfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547838565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3547838565
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.611936360
Short name T313
Test name
Test status
Simulation time 67007220 ps
CPU time 1.21 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 218236 kb
Host smart-591b7a3a-d874-4859-aa9b-e04ea7b9f09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611936360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.611936360
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3465978422
Short name T408
Test name
Test status
Simulation time 68466486 ps
CPU time 1.74 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 218028 kb
Host smart-74f87684-f57f-4bbb-a66d-371648a91439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465978422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3465978422
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4120662677
Short name T752
Test name
Test status
Simulation time 38374436 ps
CPU time 1.37 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 218876 kb
Host smart-ba8af86e-04c7-43ae-b635-0dabb5c52e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120662677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4120662677
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1861354962
Short name T405
Test name
Test status
Simulation time 41757103 ps
CPU time 1.73 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 216636 kb
Host smart-6817ec22-adf5-4b06-bea9-f93a1cc08431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861354962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1861354962
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2703637133
Short name T137
Test name
Test status
Simulation time 87984551 ps
CPU time 1.71 seconds
Started Mar 28 01:32:11 PM PDT 24
Finished Mar 28 01:32:13 PM PDT 24
Peak memory 218028 kb
Host smart-bcad14b4-0866-4912-9930-169da691496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703637133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2703637133
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.913078075
Short name T722
Test name
Test status
Simulation time 61513264 ps
CPU time 1.63 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 218056 kb
Host smart-2ee9c797-0e82-4c6a-8d8f-67a0c5380946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913078075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.913078075
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1259263522
Short name T414
Test name
Test status
Simulation time 46304189 ps
CPU time 1.25 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 216464 kb
Host smart-3b904390-37a8-43b7-986c-5d94e25bd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259263522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1259263522
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1315485534
Short name T357
Test name
Test status
Simulation time 25771968 ps
CPU time 1.08 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 216808 kb
Host smart-ad3ed84b-c90c-4cfb-a401-f76f8467105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315485534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1315485534
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1797746989
Short name T558
Test name
Test status
Simulation time 73424573 ps
CPU time 1.1 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215580 kb
Host smart-4779b630-718b-465f-be9d-e90e2d5925de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797746989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1797746989
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3547376003
Short name T307
Test name
Test status
Simulation time 13671962 ps
CPU time 0.9 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 206528 kb
Host smart-b313647c-d428-4ae8-8f7d-859989a9e43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547376003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3547376003
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3375745492
Short name T748
Test name
Test status
Simulation time 39561588 ps
CPU time 0.81 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215916 kb
Host smart-9ebd2cb4-ca40-4d43-9065-bf0b8485bce1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375745492 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3375745492
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.493964345
Short name T164
Test name
Test status
Simulation time 156493997 ps
CPU time 1.17 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216308 kb
Host smart-88ef4036-316d-4d61-b827-c77012a6dc73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493964345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.493964345
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1978217202
Short name T364
Test name
Test status
Simulation time 19017400 ps
CPU time 1.1 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 218304 kb
Host smart-c348482f-895d-4c3e-9f93-3b7e7bddd044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978217202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1978217202
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2337936028
Short name T273
Test name
Test status
Simulation time 122895579 ps
CPU time 1.28 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 218772 kb
Host smart-60801007-15a2-4805-89b3-7a039cdab2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337936028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2337936028
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1055645153
Short name T112
Test name
Test status
Simulation time 33926048 ps
CPU time 0.9 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215468 kb
Host smart-5b334561-2cd9-4d0d-b87c-9b9180e7d8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055645153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1055645153
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3255533871
Short name T743
Test name
Test status
Simulation time 20012035 ps
CPU time 0.91 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215284 kb
Host smart-45f0b912-1c9d-476b-994a-737d8eb30518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255533871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3255533871
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1728750099
Short name T362
Test name
Test status
Simulation time 429122458 ps
CPU time 2.6 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216644 kb
Host smart-ed60b189-b334-492d-ae11-967efce31aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728750099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1728750099
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3882873252
Short name T348
Test name
Test status
Simulation time 11277242432 ps
CPU time 245.54 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:34:56 PM PDT 24
Peak memory 218924 kb
Host smart-eef364ae-28de-45ba-acd2-a8f0d8efa943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882873252 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3882873252
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/231.edn_genbits.1792661110
Short name T382
Test name
Test status
Simulation time 42497034 ps
CPU time 1.53 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:07 PM PDT 24
Peak memory 217972 kb
Host smart-0e07e353-8211-4eb6-aff6-4d78f7d1eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792661110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1792661110
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2876600040
Short name T360
Test name
Test status
Simulation time 324763127 ps
CPU time 2.89 seconds
Started Mar 28 01:32:04 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 216760 kb
Host smart-6a9d8575-f797-44cc-8737-7a5f1588ea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876600040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2876600040
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.615565690
Short name T602
Test name
Test status
Simulation time 41508044 ps
CPU time 1.6 seconds
Started Mar 28 01:32:10 PM PDT 24
Finished Mar 28 01:32:12 PM PDT 24
Peak memory 216756 kb
Host smart-ea8e7e26-7c90-4115-b5d8-458549576c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615565690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.615565690
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2750605639
Short name T823
Test name
Test status
Simulation time 51187630 ps
CPU time 1.18 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 217836 kb
Host smart-3f78d87a-5ead-4875-8188-0e468a5474b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750605639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2750605639
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.874199326
Short name T626
Test name
Test status
Simulation time 70711257 ps
CPU time 2.54 seconds
Started Mar 28 01:32:06 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 219524 kb
Host smart-dc017830-549c-496d-ad61-3de419c564b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874199326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.874199326
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.999561393
Short name T830
Test name
Test status
Simulation time 49056113 ps
CPU time 1.23 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 217648 kb
Host smart-9d510b71-2b71-4328-b81b-5b25c4f847ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999561393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.999561393
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3842595232
Short name T839
Test name
Test status
Simulation time 325881708 ps
CPU time 4 seconds
Started Mar 28 01:32:05 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 216988 kb
Host smart-e0aa0f62-67e6-4e97-bd5b-036292891dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842595232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3842595232
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.72627276
Short name T702
Test name
Test status
Simulation time 151840365 ps
CPU time 1.13 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 216664 kb
Host smart-132d8390-7cfd-44b3-b3ae-91dda43b0fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72627276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.72627276
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4255377566
Short name T83
Test name
Test status
Simulation time 41173965 ps
CPU time 1.12 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215620 kb
Host smart-675c0587-665f-4c62-a763-1f3569a7a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255377566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4255377566
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.866138171
Short name T569
Test name
Test status
Simulation time 120946937 ps
CPU time 0.77 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:00 PM PDT 24
Peak memory 206592 kb
Host smart-9ed7247d-a727-446c-8716-f831dc8f41bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866138171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.866138171
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3295495595
Short name T573
Test name
Test status
Simulation time 12810783 ps
CPU time 0.9 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215852 kb
Host smart-eed88826-72ec-4a02-8edb-d3e2d0312814
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295495595 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3295495595
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.557340481
Short name T10
Test name
Test status
Simulation time 26857549 ps
CPU time 1.13 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 217456 kb
Host smart-732fdd91-d016-49dc-868e-ac4af0f08539
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557340481 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.557340481
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3089909073
Short name T241
Test name
Test status
Simulation time 21600165 ps
CPU time 0.94 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 218384 kb
Host smart-6bcbabf9-651e-4325-9605-9007fc9d8bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089909073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3089909073
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2283044871
Short name T537
Test name
Test status
Simulation time 205307039 ps
CPU time 2.34 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:57 PM PDT 24
Peak memory 219036 kb
Host smart-d58ca459-22d9-474a-807f-e9f1425d4c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283044871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2283044871
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.151235770
Short name T415
Test name
Test status
Simulation time 38032906 ps
CPU time 0.89 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215564 kb
Host smart-72ea364f-c6b6-411d-bc01-f8f78fe2b319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151235770 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.151235770
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4145429222
Short name T341
Test name
Test status
Simulation time 28084435 ps
CPU time 0.97 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 215288 kb
Host smart-4e8c808b-3373-4555-ac30-f2b0c79e39ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145429222 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4145429222
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2422357647
Short name T194
Test name
Test status
Simulation time 352389814 ps
CPU time 6.5 seconds
Started Mar 28 01:30:52 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 215280 kb
Host smart-cb60e758-cb11-4fa4-92af-8dbbaa699b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422357647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2422357647
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.837850472
Short name T136
Test name
Test status
Simulation time 241985194759 ps
CPU time 1368.05 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:53:44 PM PDT 24
Peak memory 222480 kb
Host smart-f92f564d-420d-4350-88cb-2eed9d5790bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837850472 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.837850472
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1871340358
Short name T524
Test name
Test status
Simulation time 35836036 ps
CPU time 1.44 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 218656 kb
Host smart-10ebd491-97e7-468b-bc0c-d1f62e7d0d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871340358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1871340358
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1198748524
Short name T263
Test name
Test status
Simulation time 53049282 ps
CPU time 1.96 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 219304 kb
Host smart-8faf05e6-bda4-4ee2-801d-dc5f1ae8c619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198748524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1198748524
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1338797860
Short name T229
Test name
Test status
Simulation time 51624552 ps
CPU time 1.15 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:15 PM PDT 24
Peak memory 216516 kb
Host smart-8151a100-c00d-493b-b3ed-3256e19ad45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338797860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1338797860
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3712217709
Short name T607
Test name
Test status
Simulation time 28648139 ps
CPU time 1.33 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 218016 kb
Host smart-d28edf23-9bf7-4bf2-a36e-a3f0456a108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712217709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3712217709
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2121573051
Short name T240
Test name
Test status
Simulation time 53799317 ps
CPU time 1.36 seconds
Started Mar 28 01:32:09 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 218180 kb
Host smart-3bdcfdd4-6573-41a5-bf8d-ea99b75ee680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121573051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2121573051
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.298571389
Short name T836
Test name
Test status
Simulation time 38992807 ps
CPU time 1.67 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 216716 kb
Host smart-b50270b9-10cd-43f9-a75c-63320000a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298571389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.298571389
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2648938166
Short name T432
Test name
Test status
Simulation time 72803273 ps
CPU time 1.87 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:11 PM PDT 24
Peak memory 218208 kb
Host smart-0e59737a-831e-4c1e-95cc-445222c70876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648938166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2648938166
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3764391114
Short name T317
Test name
Test status
Simulation time 66530476 ps
CPU time 1.1 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 216788 kb
Host smart-77f32f65-e3d2-494e-b00a-85d28be7f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764391114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3764391114
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3178363657
Short name T441
Test name
Test status
Simulation time 30935597 ps
CPU time 1.29 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:15 PM PDT 24
Peak memory 218080 kb
Host smart-93a85fbe-de35-4821-9f72-87e84e2892ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178363657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3178363657
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1182431002
Short name T340
Test name
Test status
Simulation time 290095893 ps
CPU time 1.15 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 216564 kb
Host smart-74ed6a61-5fb8-4f2b-9c38-e8ab852461bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182431002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1182431002
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3420559100
Short name T139
Test name
Test status
Simulation time 115046407 ps
CPU time 1.17 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215648 kb
Host smart-0b79aa57-392f-433c-843a-9f52acac8f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420559100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3420559100
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.450472120
Short name T505
Test name
Test status
Simulation time 41814660 ps
CPU time 1.29 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 206176 kb
Host smart-22c8bad2-cd18-4c84-a22d-2fe91d5fad2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450472120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.450472120
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.4267765446
Short name T813
Test name
Test status
Simulation time 20531008 ps
CPU time 0.89 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 215508 kb
Host smart-a9b23e0b-5fbd-4253-9ee6-0f0a00253b92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267765446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4267765446
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.4146090117
Short name T655
Test name
Test status
Simulation time 28116270 ps
CPU time 1.29 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 216896 kb
Host smart-222acb91-5ed9-4dd2-8d17-3ab839c861d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146090117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4146090117
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1187785802
Short name T290
Test name
Test status
Simulation time 41129156 ps
CPU time 1.49 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216544 kb
Host smart-81db8eaf-ada7-4436-a7b8-361309e7cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187785802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1187785802
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2687092648
Short name T113
Test name
Test status
Simulation time 38495228 ps
CPU time 0.85 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215500 kb
Host smart-bda232c1-db35-4f6a-8233-07222f1dddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687092648 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2687092648
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2576356549
Short name T338
Test name
Test status
Simulation time 113453413 ps
CPU time 1 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 215340 kb
Host smart-32e7a24e-3942-4876-93a4-7354b173ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576356549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2576356549
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2111429682
Short name T417
Test name
Test status
Simulation time 1098491004 ps
CPU time 5.12 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:31:02 PM PDT 24
Peak memory 216696 kb
Host smart-2a37f7f1-eeee-49d3-8b12-2ed9e683aabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111429682 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2111429682
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3304710953
Short name T184
Test name
Test status
Simulation time 85434535396 ps
CPU time 644.74 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:41:42 PM PDT 24
Peak memory 218788 kb
Host smart-b5960689-2e86-4830-be0d-26f9d37fcda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304710953 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3304710953
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.680567609
Short name T782
Test name
Test status
Simulation time 45495231 ps
CPU time 1.55 seconds
Started Mar 28 01:32:10 PM PDT 24
Finished Mar 28 01:32:12 PM PDT 24
Peak memory 217932 kb
Host smart-a63844b9-f18b-4b49-81f7-152eacd9b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680567609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.680567609
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2213460824
Short name T471
Test name
Test status
Simulation time 55808065 ps
CPU time 1.48 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217976 kb
Host smart-91218281-ec1f-419d-a2b2-01b74f9b1b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213460824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2213460824
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3158423474
Short name T659
Test name
Test status
Simulation time 70320696 ps
CPU time 1.97 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 219608 kb
Host smart-9a64eb65-7ac0-419b-bb90-df40b2407d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158423474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3158423474
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3385434054
Short name T716
Test name
Test status
Simulation time 46796391 ps
CPU time 1.66 seconds
Started Mar 28 01:32:07 PM PDT 24
Finished Mar 28 01:32:09 PM PDT 24
Peak memory 217652 kb
Host smart-1df39e2a-20f3-43f6-a699-70ac74633943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385434054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3385434054
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2780830226
Short name T815
Test name
Test status
Simulation time 83861785 ps
CPU time 1.79 seconds
Started Mar 28 01:32:08 PM PDT 24
Finished Mar 28 01:32:10 PM PDT 24
Peak memory 218296 kb
Host smart-c7b2ba7b-6c15-40bf-b5a1-4fe044c061cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780830226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2780830226
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.319010918
Short name T652
Test name
Test status
Simulation time 76466129 ps
CPU time 1.35 seconds
Started Mar 28 01:32:16 PM PDT 24
Finished Mar 28 01:32:18 PM PDT 24
Peak memory 217632 kb
Host smart-f512fa75-c956-4d23-bbe1-64bd8e3fdea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319010918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.319010918
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2573216544
Short name T329
Test name
Test status
Simulation time 64907454 ps
CPU time 1.72 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:32:17 PM PDT 24
Peak memory 217708 kb
Host smart-4cf94e86-d006-413a-9636-e1c671a9fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573216544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2573216544
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1141988438
Short name T676
Test name
Test status
Simulation time 37968424 ps
CPU time 1.31 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:28 PM PDT 24
Peak memory 216484 kb
Host smart-9decb9eb-e1a2-446e-9e3d-f42f6170cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141988438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1141988438
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.970046000
Short name T431
Test name
Test status
Simulation time 235005949 ps
CPU time 2.94 seconds
Started Mar 28 01:32:22 PM PDT 24
Finished Mar 28 01:32:26 PM PDT 24
Peak memory 219212 kb
Host smart-91d53156-66d9-44e2-be28-68f8e26c4e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970046000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.970046000
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.404685580
Short name T456
Test name
Test status
Simulation time 69042323 ps
CPU time 1.26 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 218752 kb
Host smart-514d2455-1b3d-40d9-b5cf-80d82506f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404685580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.404685580
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1680713051
Short name T254
Test name
Test status
Simulation time 191556625 ps
CPU time 1.29 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215600 kb
Host smart-2df454ea-2b2b-4e3b-b169-021393b66b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680713051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1680713051
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.534342860
Short name T475
Test name
Test status
Simulation time 15153667 ps
CPU time 0.9 seconds
Started Mar 28 01:31:01 PM PDT 24
Finished Mar 28 01:31:03 PM PDT 24
Peak memory 205920 kb
Host smart-8f908e61-e89f-4a95-b76b-5395614500bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534342860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.534342860
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1883699432
Short name T176
Test name
Test status
Simulation time 16627418 ps
CPU time 0.84 seconds
Started Mar 28 01:31:01 PM PDT 24
Finished Mar 28 01:31:02 PM PDT 24
Peak memory 215804 kb
Host smart-ffc0fb61-3ed6-49f1-80a0-b279d85ea939
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883699432 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1883699432
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1201043833
Short name T157
Test name
Test status
Simulation time 274880804 ps
CPU time 1.2 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 216432 kb
Host smart-e509c00f-c57d-4980-ad39-6d093baf2122
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201043833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1201043833
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2471013110
Short name T47
Test name
Test status
Simulation time 36222725 ps
CPU time 1.18 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 229720 kb
Host smart-45fdb99a-a815-4e71-844e-4c045aa69889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471013110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2471013110
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_intr.907013977
Short name T305
Test name
Test status
Simulation time 26374773 ps
CPU time 0.98 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215520 kb
Host smart-63b129b6-e169-4f18-bd24-8e79906999d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907013977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.907013977
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.713762211
Short name T528
Test name
Test status
Simulation time 35817936 ps
CPU time 0.87 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 215344 kb
Host smart-90384dc4-fc04-4dd8-865a-25510be57957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713762211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.713762211
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2283102533
Short name T479
Test name
Test status
Simulation time 1322390437 ps
CPU time 4.73 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216220 kb
Host smart-198b4305-c67b-43bf-b78d-b50ad3c7d51b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283102533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2283102533
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.808216186
Short name T781
Test name
Test status
Simulation time 29971960314 ps
CPU time 387.29 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:37:27 PM PDT 24
Peak memory 223624 kb
Host smart-96989373-2399-49ad-b735-e9ac1ec5e1d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808216186 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.808216186
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1693719479
Short name T685
Test name
Test status
Simulation time 51906957 ps
CPU time 1.6 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:21 PM PDT 24
Peak memory 217692 kb
Host smart-6fbf188b-4116-45a4-aa55-8b6391ec771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693719479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1693719479
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3700857677
Short name T381
Test name
Test status
Simulation time 73830916 ps
CPU time 1.11 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 216564 kb
Host smart-be9f8ae0-4d31-4910-94f8-e400c07e5aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700857677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3700857677
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3026848138
Short name T281
Test name
Test status
Simulation time 87922240 ps
CPU time 1.41 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:20 PM PDT 24
Peak memory 218268 kb
Host smart-d87c7a5b-409d-4f8e-99e1-a189ea3dd722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026848138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3026848138
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1041927380
Short name T770
Test name
Test status
Simulation time 51551236 ps
CPU time 1.19 seconds
Started Mar 28 01:32:17 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 216436 kb
Host smart-296ca63b-2275-464a-9364-6903ccad123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041927380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1041927380
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3376966548
Short name T461
Test name
Test status
Simulation time 20594276 ps
CPU time 1.04 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 216380 kb
Host smart-dcde5218-565b-43e5-a182-9b9044e5e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376966548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3376966548
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.183820890
Short name T829
Test name
Test status
Simulation time 48005336 ps
CPU time 1.02 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 217932 kb
Host smart-63bdfab9-5285-4532-b6a0-a407f1839a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183820890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.183820890
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3769234337
Short name T720
Test name
Test status
Simulation time 57750265 ps
CPU time 1.36 seconds
Started Mar 28 01:32:22 PM PDT 24
Finished Mar 28 01:32:23 PM PDT 24
Peak memory 217968 kb
Host smart-7d6e77ff-9aaf-41a7-9f66-7ced2eee7558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769234337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3769234337
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2959084230
Short name T117
Test name
Test status
Simulation time 72925296 ps
CPU time 1.62 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:20 PM PDT 24
Peak memory 218256 kb
Host smart-5ba06a9b-cf73-4134-82c2-6881ab6d4331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959084230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2959084230
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.672864415
Short name T267
Test name
Test status
Simulation time 41666395 ps
CPU time 1.27 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 217828 kb
Host smart-e3aac5a0-7ae8-4fbd-9703-132ed6643fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672864415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.672864415
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.838039322
Short name T429
Test name
Test status
Simulation time 404465041 ps
CPU time 4.12 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 219692 kb
Host smart-881d9d05-7235-4b4c-a9e2-9f3aba1bbff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838039322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.838039322
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.3448448226
Short name T325
Test name
Test status
Simulation time 57529751 ps
CPU time 0.84 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 205652 kb
Host smart-cb91b5ce-7c2b-43b3-bf1d-42eaf77dcc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448448226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3448448226
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.384858244
Short name T498
Test name
Test status
Simulation time 13900882 ps
CPU time 0.96 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 215596 kb
Host smart-cf5f1711-c50e-49f1-9cea-3cf906fc33a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384858244 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.384858244
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1610289288
Short name T11
Test name
Test status
Simulation time 91660529 ps
CPU time 1.05 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216480 kb
Host smart-23005774-244b-4d87-85a1-6f0ba325ccc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610289288 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1610289288
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2662113755
Short name T514
Test name
Test status
Simulation time 102520233 ps
CPU time 1.35 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 232376 kb
Host smart-e3e0bf59-dfea-4077-9cf6-1678ff82ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662113755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2662113755
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.424400816
Short name T771
Test name
Test status
Simulation time 26958502 ps
CPU time 1.21 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 216540 kb
Host smart-345fb69f-01e5-40fc-9ff5-b66ba10d9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424400816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.424400816
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2942375344
Short name T302
Test name
Test status
Simulation time 21879735 ps
CPU time 1.06 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215580 kb
Host smart-a5aa29c7-d22f-4263-b2a2-e20b0a510fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942375344 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2942375344
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3487315857
Short name T315
Test name
Test status
Simulation time 119648852 ps
CPU time 0.98 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 215272 kb
Host smart-09833d83-ef54-4aa3-afd4-309888c01947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487315857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3487315857
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2132116698
Short name T334
Test name
Test status
Simulation time 107636623 ps
CPU time 2.66 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 216516 kb
Host smart-10e12aba-0511-40aa-809f-00e0de51f96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132116698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2132116698
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1512871944
Short name T645
Test name
Test status
Simulation time 65606393757 ps
CPU time 875.76 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:45:30 PM PDT 24
Peak memory 221064 kb
Host smart-2816f80a-4386-40a9-b346-aa1f23ff9bf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512871944 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1512871944
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1852014039
Short name T541
Test name
Test status
Simulation time 35853025 ps
CPU time 1.45 seconds
Started Mar 28 01:32:21 PM PDT 24
Finished Mar 28 01:32:23 PM PDT 24
Peak memory 217796 kb
Host smart-b6610e45-7b51-4219-ac18-a08cc7e85787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852014039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1852014039
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2749942739
Short name T170
Test name
Test status
Simulation time 56308317 ps
CPU time 1.48 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:21 PM PDT 24
Peak memory 216716 kb
Host smart-3eb9eec5-5986-452e-9fec-d98d83ddf52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749942739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2749942739
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.841906507
Short name T690
Test name
Test status
Simulation time 33433680 ps
CPU time 1.3 seconds
Started Mar 28 01:32:26 PM PDT 24
Finished Mar 28 01:32:28 PM PDT 24
Peak memory 217732 kb
Host smart-21f9592c-da02-4896-af6a-30d8f8a1ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841906507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.841906507
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4007964768
Short name T380
Test name
Test status
Simulation time 74178266 ps
CPU time 1.16 seconds
Started Mar 28 01:32:16 PM PDT 24
Finished Mar 28 01:32:17 PM PDT 24
Peak memory 216480 kb
Host smart-8d89b852-8c52-4f1b-a81d-68c5de8a82f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007964768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4007964768
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1786407571
Short name T658
Test name
Test status
Simulation time 21854581 ps
CPU time 1.13 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:20 PM PDT 24
Peak memory 216572 kb
Host smart-5b804b42-b58f-4e5e-b958-d53d59c05f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786407571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1786407571
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2090490882
Short name T269
Test name
Test status
Simulation time 44521652 ps
CPU time 1.04 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:28 PM PDT 24
Peak memory 217636 kb
Host smart-8f79e66c-818f-4109-8c04-3953e7f7a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090490882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2090490882
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.331781943
Short name T468
Test name
Test status
Simulation time 49023669 ps
CPU time 1.37 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 217876 kb
Host smart-a90b90f7-a5fd-4b36-9974-3c1303dda880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331781943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.331781943
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.852561968
Short name T271
Test name
Test status
Simulation time 66589614 ps
CPU time 1.37 seconds
Started Mar 28 01:32:15 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 217996 kb
Host smart-7c4059d6-99d3-4166-966b-5ab6be9f81a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852561968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.852561968
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1411923729
Short name T820
Test name
Test status
Simulation time 83122667 ps
CPU time 1.07 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:20 PM PDT 24
Peak memory 216388 kb
Host smart-628e40e0-327c-4b7c-af31-0b6a0721b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411923729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1411923729
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.856047464
Short name T442
Test name
Test status
Simulation time 61228724 ps
CPU time 1.3 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 217588 kb
Host smart-92a9b8c9-130c-45ee-ac60-058376073db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856047464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.856047464
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3958580672
Short name T445
Test name
Test status
Simulation time 50673112 ps
CPU time 1.24 seconds
Started Mar 28 01:30:50 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 215624 kb
Host smart-24fbe427-790e-4ba8-a9df-a4bccbea2621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958580672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3958580672
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1828515796
Short name T300
Test name
Test status
Simulation time 19321885 ps
CPU time 0.93 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 205944 kb
Host smart-edb1b8a7-c583-4048-883b-ffb7831cf1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828515796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1828515796
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2976263717
Short name T75
Test name
Test status
Simulation time 69144601 ps
CPU time 1.41 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 217676 kb
Host smart-4d193db4-3306-4ef2-a2a8-ffcf1cc2ada6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976263717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2976263717
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2891784056
Short name T694
Test name
Test status
Simulation time 24479540 ps
CPU time 1.14 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 219436 kb
Host smart-68a09d72-e53a-4fb5-8590-2a098e0e6bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891784056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2891784056
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2782724391
Short name T786
Test name
Test status
Simulation time 66256559 ps
CPU time 2.44 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 219096 kb
Host smart-13c952ec-b6fd-4d83-b12f-7e2a056b6c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782724391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2782724391
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3059012199
Short name T4
Test name
Test status
Simulation time 40572980 ps
CPU time 0.79 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215508 kb
Host smart-df6fe30c-0b76-480e-9c83-304e1e1dc670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059012199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3059012199
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2311048203
Short name T619
Test name
Test status
Simulation time 25386839 ps
CPU time 1.01 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215304 kb
Host smart-4fa3c026-fb6d-481a-9cc5-ba4ab5a965a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311048203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2311048203
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2400095678
Short name T679
Test name
Test status
Simulation time 370530087 ps
CPU time 7.26 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 216448 kb
Host smart-e8da7baf-2b3d-4948-9aa9-b3c1011cf549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400095678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2400095678
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1373322328
Short name T25
Test name
Test status
Simulation time 907649783493 ps
CPU time 1711.3 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:59:25 PM PDT 24
Peak memory 231132 kb
Host smart-825bc196-9653-4737-aba6-2132b84d597e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373322328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1373322328
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3309576690
Short name T26
Test name
Test status
Simulation time 106443708 ps
CPU time 1.6 seconds
Started Mar 28 01:32:18 PM PDT 24
Finished Mar 28 01:32:20 PM PDT 24
Peak memory 216716 kb
Host smart-766e2ea3-2f83-408f-aedc-2c6ac539f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309576690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3309576690
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2102059426
Short name T666
Test name
Test status
Simulation time 47277317 ps
CPU time 1.48 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 215260 kb
Host smart-a08969c2-8b2c-4e3a-8359-812a623b2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102059426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2102059426
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.4016910645
Short name T296
Test name
Test status
Simulation time 55293472 ps
CPU time 1.13 seconds
Started Mar 28 01:32:22 PM PDT 24
Finished Mar 28 01:32:23 PM PDT 24
Peak memory 216668 kb
Host smart-e485e771-7d56-4f0d-9d56-c25d0068caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016910645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.4016910645
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1497494640
Short name T490
Test name
Test status
Simulation time 46318296 ps
CPU time 1.54 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 217768 kb
Host smart-d7954021-80bf-4b84-ae29-2ba1bf69a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497494640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1497494640
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2059993433
Short name T416
Test name
Test status
Simulation time 34073888 ps
CPU time 1.25 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:28 PM PDT 24
Peak memory 216552 kb
Host smart-88fde446-c38f-43d8-9d98-01ae2d502c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059993433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2059993433
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1269846630
Short name T275
Test name
Test status
Simulation time 58905975 ps
CPU time 1.3 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 216860 kb
Host smart-d835982f-c555-44af-becc-0c27aec7f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269846630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1269846630
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3252761944
Short name T808
Test name
Test status
Simulation time 63003090 ps
CPU time 2.44 seconds
Started Mar 28 01:32:17 PM PDT 24
Finished Mar 28 01:32:19 PM PDT 24
Peak memory 216848 kb
Host smart-482d5293-ca3e-422b-9c27-8a361c2916e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252761944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3252761944
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3453545337
Short name T260
Test name
Test status
Simulation time 104399269 ps
CPU time 1.58 seconds
Started Mar 28 01:32:16 PM PDT 24
Finished Mar 28 01:32:18 PM PDT 24
Peak memory 218388 kb
Host smart-52f1edd3-61de-47c2-9a59-df38230a3816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453545337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3453545337
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.118449951
Short name T383
Test name
Test status
Simulation time 62458069 ps
CPU time 1.33 seconds
Started Mar 28 01:32:16 PM PDT 24
Finished Mar 28 01:32:18 PM PDT 24
Peak memory 216708 kb
Host smart-af050e51-704e-4566-9ad7-6d81c4d583aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118449951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.118449951
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1461403244
Short name T299
Test name
Test status
Simulation time 42655149 ps
CPU time 1.63 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 217680 kb
Host smart-35d8b035-654a-462e-801a-49ac3a7ca225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461403244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1461403244
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1387448122
Short name T248
Test name
Test status
Simulation time 31129584 ps
CPU time 1.28 seconds
Started Mar 28 01:31:04 PM PDT 24
Finished Mar 28 01:31:05 PM PDT 24
Peak memory 215600 kb
Host smart-4651a21b-f211-4e17-b782-0672d4035b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387448122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1387448122
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1082631966
Short name T336
Test name
Test status
Simulation time 30405519 ps
CPU time 0.88 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 206900 kb
Host smart-3fafaec3-db4e-4c7a-9a4d-ed6f82f96ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082631966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1082631966
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.853899487
Short name T161
Test name
Test status
Simulation time 190820808 ps
CPU time 1.05 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216492 kb
Host smart-0107a773-1f0c-4797-8ce2-bb910249ae4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853899487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.853899487
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3638375294
Short name T42
Test name
Test status
Simulation time 34069056 ps
CPU time 1.01 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:57 PM PDT 24
Peak memory 231020 kb
Host smart-a47a09cf-8c5f-44ff-895e-31489bcaf092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638375294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3638375294
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1051215589
Short name T819
Test name
Test status
Simulation time 55783942 ps
CPU time 1.48 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215392 kb
Host smart-631518e5-ea4c-43fa-acde-1439121b6f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051215589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1051215589
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3739076911
Short name T127
Test name
Test status
Simulation time 20783542 ps
CPU time 1.08 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 215772 kb
Host smart-68159b1e-02c5-423b-b883-95ffea5b86b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739076911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3739076911
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.241830284
Short name T397
Test name
Test status
Simulation time 22335758 ps
CPU time 1.06 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215288 kb
Host smart-a3f20912-bfb9-4f6f-a1bf-e43e2e31addf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241830284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.241830284
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.42678540
Short name T744
Test name
Test status
Simulation time 196959471 ps
CPU time 4.17 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:03 PM PDT 24
Peak memory 215300 kb
Host smart-236802f0-9101-4215-a66d-2354662116d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42678540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.42678540
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1756130932
Short name T547
Test name
Test status
Simulation time 45491387089 ps
CPU time 599.41 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:40:56 PM PDT 24
Peak memory 218928 kb
Host smart-6517929f-b044-4171-9e32-e6c1e228cd07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756130932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1756130932
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.842966567
Short name T333
Test name
Test status
Simulation time 98875921 ps
CPU time 1.25 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:21 PM PDT 24
Peak memory 216632 kb
Host smart-ea7e4a93-a917-449c-836c-2a62cf84ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842966567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.842966567
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.458188088
Short name T496
Test name
Test status
Simulation time 55577333 ps
CPU time 1 seconds
Started Mar 28 01:32:19 PM PDT 24
Finished Mar 28 01:32:21 PM PDT 24
Peak memory 216544 kb
Host smart-f8af6f11-5f55-4d1e-b577-9ae78fb7ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458188088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.458188088
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3639667600
Short name T352
Test name
Test status
Simulation time 79810969 ps
CPU time 1.63 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 217628 kb
Host smart-dddf1f7a-86d3-4fa6-a485-93db28c91934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639667600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3639667600
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2802210238
Short name T513
Test name
Test status
Simulation time 112893953 ps
CPU time 1.28 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 219196 kb
Host smart-cf63215c-3000-4b8f-a0ac-161bcc961725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802210238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2802210238
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3278977283
Short name T787
Test name
Test status
Simulation time 32183477 ps
CPU time 1.35 seconds
Started Mar 28 01:32:28 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 219248 kb
Host smart-c1d430dd-050e-484f-8aa3-a71609352b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278977283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3278977283
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1482531845
Short name T33
Test name
Test status
Simulation time 94951667 ps
CPU time 1.11 seconds
Started Mar 28 01:32:14 PM PDT 24
Finished Mar 28 01:32:16 PM PDT 24
Peak memory 216544 kb
Host smart-b332ffba-805c-45f3-bf4b-3c6899af5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482531845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1482531845
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2514864830
Short name T484
Test name
Test status
Simulation time 82719973 ps
CPU time 2.8 seconds
Started Mar 28 01:32:17 PM PDT 24
Finished Mar 28 01:32:20 PM PDT 24
Peak memory 216840 kb
Host smart-8650a043-dba2-43e8-8ece-fa9a50003d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514864830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2514864830
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3226432162
Short name T179
Test name
Test status
Simulation time 86424694 ps
CPU time 1.1 seconds
Started Mar 28 01:32:16 PM PDT 24
Finished Mar 28 01:32:17 PM PDT 24
Peak memory 216552 kb
Host smart-9ea49fd9-7931-47b3-9db8-e9f6d7e43165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226432162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3226432162
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1300387231
Short name T814
Test name
Test status
Simulation time 27604026 ps
CPU time 1.29 seconds
Started Mar 28 01:32:17 PM PDT 24
Finished Mar 28 01:32:18 PM PDT 24
Peak memory 216676 kb
Host smart-044416ee-1fb8-4be2-aada-22656ab4b9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300387231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1300387231
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3174012000
Short name T615
Test name
Test status
Simulation time 54585869 ps
CPU time 1.56 seconds
Started Mar 28 01:32:27 PM PDT 24
Finished Mar 28 01:32:29 PM PDT 24
Peak memory 218196 kb
Host smart-567b0260-e263-4867-9c06-e7fb1d26e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174012000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3174012000
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.461028348
Short name T647
Test name
Test status
Simulation time 44000105 ps
CPU time 1.21 seconds
Started Mar 28 01:30:10 PM PDT 24
Finished Mar 28 01:30:11 PM PDT 24
Peak memory 215616 kb
Host smart-b338a788-64ad-4b56-a4ba-e53a2de9af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461028348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.461028348
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1126607493
Short name T583
Test name
Test status
Simulation time 18819871 ps
CPU time 1.04 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 206540 kb
Host smart-f6be7e21-9f26-4c04-9ef3-9596e1d76096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126607493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1126607493
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.673685650
Short name T407
Test name
Test status
Simulation time 11245404 ps
CPU time 0.87 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 215408 kb
Host smart-3682f66c-0395-41b9-a133-503854ee72ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673685650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.673685650
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1017170724
Short name T153
Test name
Test status
Simulation time 83704299 ps
CPU time 1.07 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 216532 kb
Host smart-e9dad1a4-8f42-4045-968c-8f6e10610c80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017170724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1017170724
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1363502519
Short name T683
Test name
Test status
Simulation time 26754650 ps
CPU time 1.23 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 218048 kb
Host smart-e4091b6e-6f72-4332-9da0-99ebcfdfff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363502519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1363502519
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3894761022
Short name T401
Test name
Test status
Simulation time 30403055 ps
CPU time 1.43 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 216764 kb
Host smart-82b73227-e533-4785-b7b3-6aaa9a26d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894761022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3894761022
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3210412000
Short name T120
Test name
Test status
Simulation time 26789897 ps
CPU time 0.94 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 215712 kb
Host smart-3f55f1b5-e75c-431c-bb3d-49545d65970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210412000 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3210412000
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.69398819
Short name T535
Test name
Test status
Simulation time 36223362 ps
CPU time 0.95 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 207068 kb
Host smart-2b2e8a67-fc90-4cb4-ac42-4eccaa2c0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69398819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.69398819
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2594287001
Short name T44
Test name
Test status
Simulation time 476453966 ps
CPU time 7.3 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 236692 kb
Host smart-5b885491-1200-4401-ad6a-d0ad4d59dc7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594287001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2594287001
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3238981544
Short name T286
Test name
Test status
Simulation time 30161992 ps
CPU time 1.01 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 215292 kb
Host smart-4c641532-ff0a-4012-a748-4be7d9abf21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238981544 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3238981544
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.730891140
Short name T804
Test name
Test status
Simulation time 164260284 ps
CPU time 1.47 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 207084 kb
Host smart-858f8cbc-2b70-4de1-b1b6-047cddbd14e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730891140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.730891140
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2226724547
Short name T24
Test name
Test status
Simulation time 50568400613 ps
CPU time 1113.39 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:48:47 PM PDT 24
Peak memory 221860 kb
Host smart-053086e0-cbbd-4725-8d2c-8afc98501d04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226724547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2226724547
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1743027139
Short name T656
Test name
Test status
Simulation time 26440814 ps
CPU time 1.26 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 215544 kb
Host smart-c0978895-0802-499f-a440-16c6d5f6e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743027139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1743027139
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2766277360
Short name T472
Test name
Test status
Simulation time 17243831 ps
CPU time 0.96 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:00 PM PDT 24
Peak memory 206512 kb
Host smart-fc8f112f-f4b1-4489-b288-3c83b0722afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766277360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2766277360
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1376608808
Short name T102
Test name
Test status
Simulation time 20209089 ps
CPU time 0.88 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:00 PM PDT 24
Peak memory 215876 kb
Host smart-cb920dfd-c5c3-42b9-9a7a-3b55eb6f25b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376608808 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1376608808
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_genbits.1672055567
Short name T28
Test name
Test status
Simulation time 68658884 ps
CPU time 1.32 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216828 kb
Host smart-cfd7df01-0bb1-4911-8bb9-dea9607dcf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672055567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1672055567
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2949321177
Short name T15
Test name
Test status
Simulation time 34173217 ps
CPU time 1.04 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 232500 kb
Host smart-80649db1-3405-4782-b658-37da5b845af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949321177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2949321177
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.796333078
Short name T145
Test name
Test status
Simulation time 17442874 ps
CPU time 1 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 215324 kb
Host smart-9ca0a705-e710-4b3c-a8b1-fdb9fb041837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796333078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.796333078
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4128804208
Short name T327
Test name
Test status
Simulation time 1375567596 ps
CPU time 2.18 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 216696 kb
Host smart-1bdbefec-3571-4e46-a188-4a3b9f571a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128804208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4128804208
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1946346130
Short name T499
Test name
Test status
Simulation time 182053855850 ps
CPU time 1042.53 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:48:20 PM PDT 24
Peak memory 222224 kb
Host smart-cda47745-9870-4c4e-8380-edbbca84b62e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946346130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1946346130
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1486150926
Short name T459
Test name
Test status
Simulation time 26006112 ps
CPU time 1.27 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 215600 kb
Host smart-861dcd0f-2b78-49ec-8f93-589d426b740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486150926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1486150926
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2704513420
Short name T349
Test name
Test status
Simulation time 13529582 ps
CPU time 0.88 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 205936 kb
Host smart-873cb254-8953-4542-bb94-c2297553f2e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704513420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2704513420
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2680345022
Short name T92
Test name
Test status
Simulation time 88249187 ps
CPU time 0.82 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 215804 kb
Host smart-739b586a-8ca5-4a7c-a0f1-20383b2451bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680345022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2680345022
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2628173560
Short name T52
Test name
Test status
Simulation time 111469793 ps
CPU time 1.52 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 216392 kb
Host smart-1c0e5b90-e8c2-4583-ba67-dacde07bd439
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628173560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2628173560
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3063932806
Short name T486
Test name
Test status
Simulation time 27945307 ps
CPU time 1.26 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 232752 kb
Host smart-a8ab80b7-d572-4b2d-b3d5-b14be6b5c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063932806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3063932806
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1567008263
Short name T732
Test name
Test status
Simulation time 51640959 ps
CPU time 1.56 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 217780 kb
Host smart-b09b4caa-02d7-4b73-973d-6428b15d0659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567008263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1567008263
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.947439872
Short name T598
Test name
Test status
Simulation time 24554740 ps
CPU time 0.96 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:02 PM PDT 24
Peak memory 215680 kb
Host smart-61ee7103-be1e-4f1e-bba3-6feb820cbe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947439872 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.947439872
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.999867065
Short name T834
Test name
Test status
Simulation time 18482996 ps
CPU time 1.04 seconds
Started Mar 28 01:30:59 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 215256 kb
Host smart-75498178-3af3-4c76-82ea-37264ab24705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999867065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.999867065
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4139862932
Short name T200
Test name
Test status
Simulation time 1025908116 ps
CPU time 4.04 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 215320 kb
Host smart-4390814a-cf12-4bac-a25c-bc5fa5e34a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139862932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4139862932
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1508492072
Short name T183
Test name
Test status
Simulation time 91221415715 ps
CPU time 1179.78 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:50:34 PM PDT 24
Peak memory 224200 kb
Host smart-c0285873-407e-4c7d-8523-86fbb1340ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508492072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1508492072
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3510429419
Short name T106
Test name
Test status
Simulation time 27448126 ps
CPU time 1.26 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 215632 kb
Host smart-7269ac3e-e9d5-413a-a038-ee1115807c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510429419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3510429419
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1644130095
Short name T565
Test name
Test status
Simulation time 18204518 ps
CPU time 0.98 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:57 PM PDT 24
Peak memory 205988 kb
Host smart-cfe5b290-fa43-475d-ad5f-9f9e73479a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644130095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1644130095
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1423220265
Short name T99
Test name
Test status
Simulation time 13663800 ps
CPU time 0.91 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216032 kb
Host smart-df213422-6b59-4925-95ac-b18d332ded66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423220265 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1423220265
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.3478585631
Short name T374
Test name
Test status
Simulation time 20774566 ps
CPU time 1.18 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 219312 kb
Host smart-d179d75a-6cfc-4ee0-95d7-4f4d3a155db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478585631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3478585631
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1877579628
Short name T810
Test name
Test status
Simulation time 50237505 ps
CPU time 1.3 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 216692 kb
Host smart-089ca485-da06-4f1c-ae68-571984517e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877579628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1877579628
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.652191162
Short name T795
Test name
Test status
Simulation time 69594193 ps
CPU time 0.87 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215356 kb
Host smart-2d99ca2e-2692-431a-9d36-d27c828dbe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652191162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.652191162
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.742369280
Short name T421
Test name
Test status
Simulation time 29240432 ps
CPU time 0.98 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 215308 kb
Host smart-b61b4519-7ab6-40ef-9d70-402304c30b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742369280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.742369280
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1383321671
Short name T644
Test name
Test status
Simulation time 185831719 ps
CPU time 2.13 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:53 PM PDT 24
Peak memory 218648 kb
Host smart-e732056d-6eeb-449f-9b3a-1fea516a0628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383321671 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1383321671
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3952042301
Short name T487
Test name
Test status
Simulation time 542988821657 ps
CPU time 1379.82 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:53:56 PM PDT 24
Peak memory 222084 kb
Host smart-cb56e202-a4d4-448f-aedc-027e4dc8c566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952042301 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3952042301
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1913076566
Short name T640
Test name
Test status
Simulation time 23167833 ps
CPU time 1.14 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215656 kb
Host smart-a7f92c08-768b-41a0-9c82-495b41aa3c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913076566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1913076566
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2144963941
Short name T143
Test name
Test status
Simulation time 38523694 ps
CPU time 0.87 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 205800 kb
Host smart-6a06daba-10d8-4822-b012-b815ac26ccfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144963941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2144963941
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1167668264
Short name T173
Test name
Test status
Simulation time 12557220 ps
CPU time 0.9 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 216044 kb
Host smart-0fd821bb-f261-415a-819e-56d0aef927a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167668264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1167668264
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2417408404
Short name T821
Test name
Test status
Simulation time 120271685 ps
CPU time 1.21 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:30:56 PM PDT 24
Peak memory 216444 kb
Host smart-82aea135-4aea-44ab-a461-f473bae425fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417408404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2417408404
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3067010742
Short name T60
Test name
Test status
Simulation time 20473384 ps
CPU time 1.28 seconds
Started Mar 28 01:30:50 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 229740 kb
Host smart-56817d35-9e70-4dcc-baee-ac6bda96dc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067010742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3067010742
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1865932931
Short name T825
Test name
Test status
Simulation time 55713874 ps
CPU time 1.34 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215244 kb
Host smart-e6699b70-ffce-4818-a0ad-c1448629bcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865932931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1865932931
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3590001601
Short name T665
Test name
Test status
Simulation time 23108647 ps
CPU time 0.99 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:30:55 PM PDT 24
Peak memory 215680 kb
Host smart-f0a19022-2a10-41f0-ba55-ab7c87340c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590001601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3590001601
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1558173197
Short name T612
Test name
Test status
Simulation time 47093974 ps
CPU time 0.92 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 215292 kb
Host smart-814af3b0-a80c-470b-ac8f-22d2b06b8d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558173197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1558173197
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.417009453
Short name T562
Test name
Test status
Simulation time 326841147 ps
CPU time 6.95 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 215280 kb
Host smart-70cb8dea-8728-4b14-bc23-f163a9abad32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417009453 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.417009453
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1567027348
Short name T731
Test name
Test status
Simulation time 103070399962 ps
CPU time 1294.16 seconds
Started Mar 28 01:30:55 PM PDT 24
Finished Mar 28 01:52:29 PM PDT 24
Peak memory 223008 kb
Host smart-fd70f05e-a45b-4ea7-a0ee-01166d704b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567027348 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1567027348
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3426951013
Short name T663
Test name
Test status
Simulation time 25553808 ps
CPU time 1.28 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 215648 kb
Host smart-4bd48502-5207-41cd-9908-0b61363f84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426951013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3426951013
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3256536423
Short name T458
Test name
Test status
Simulation time 21774431 ps
CPU time 0.86 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 206520 kb
Host smart-158e1fc7-f278-4aba-bffe-f39a7c52021f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256536423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3256536423
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_err.3718817018
Short name T501
Test name
Test status
Simulation time 20409678 ps
CPU time 1.05 seconds
Started Mar 28 01:30:51 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 218108 kb
Host smart-9eaaf513-aa1c-432f-928d-eb55fffd039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718817018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3718817018
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1295361412
Short name T318
Test name
Test status
Simulation time 41862623 ps
CPU time 1.3 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 217780 kb
Host smart-13b16af7-0b9b-4c54-8c40-2e900ff55aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295361412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1295361412
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2432425783
Short name T40
Test name
Test status
Simulation time 28746674 ps
CPU time 1 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 224080 kb
Host smart-2c149211-f83c-4793-836a-814c902b76f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432425783 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2432425783
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.141212940
Short name T741
Test name
Test status
Simulation time 29933643 ps
CPU time 1.03 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 215280 kb
Host smart-f225fa82-d845-43bc-8cab-d12b7b354e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141212940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.141212940
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3472248641
Short name T516
Test name
Test status
Simulation time 288567610 ps
CPU time 5.64 seconds
Started Mar 28 01:30:56 PM PDT 24
Finished Mar 28 01:31:02 PM PDT 24
Peak memory 215332 kb
Host smart-8d7d6416-58af-4f69-8733-d54f2a36b8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472248641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3472248641
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.377505011
Short name T131
Test name
Test status
Simulation time 53022641999 ps
CPU time 599.13 seconds
Started Mar 28 01:30:57 PM PDT 24
Finished Mar 28 01:40:56 PM PDT 24
Peak memory 218056 kb
Host smart-07f2bef1-e909-47ec-87fa-bc8277001831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377505011 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.377505011
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.479372131
Short name T89
Test name
Test status
Simulation time 101870852 ps
CPU time 1.14 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 215612 kb
Host smart-114a409a-096c-4d46-a00a-a653c922ec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479372131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.479372131
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1736511456
Short name T650
Test name
Test status
Simulation time 71888818 ps
CPU time 0.85 seconds
Started Mar 28 01:31:05 PM PDT 24
Finished Mar 28 01:31:06 PM PDT 24
Peak memory 206760 kb
Host smart-1155fb69-79b4-4d7b-bfa3-c796372d8328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736511456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1736511456
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2151558807
Short name T79
Test name
Test status
Simulation time 20280487 ps
CPU time 0.79 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 215428 kb
Host smart-5525cfb6-5273-4f30-8ea9-5f31c495b4c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151558807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2151558807
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1980523016
Short name T696
Test name
Test status
Simulation time 44560993 ps
CPU time 1.48 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 216004 kb
Host smart-6cfcc34b-9ee9-48d2-bd69-b768dd59ce16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980523016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1980523016
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2196379005
Short name T108
Test name
Test status
Simulation time 31322971 ps
CPU time 0.87 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 217516 kb
Host smart-48364190-e918-47cc-a2f3-fb22aa4620ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196379005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2196379005
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1944095465
Short name T552
Test name
Test status
Simulation time 34537077 ps
CPU time 1.14 seconds
Started Mar 28 01:31:00 PM PDT 24
Finished Mar 28 01:31:01 PM PDT 24
Peak memory 216596 kb
Host smart-89a76609-611f-450f-b627-6f70d9f6c627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944095465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1944095465
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_smoke.1515006321
Short name T657
Test name
Test status
Simulation time 23875489 ps
CPU time 0.91 seconds
Started Mar 28 01:30:58 PM PDT 24
Finished Mar 28 01:30:59 PM PDT 24
Peak memory 215232 kb
Host smart-8104641b-1a41-44dd-9e20-999a85a59889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515006321 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1515006321
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.344504085
Short name T818
Test name
Test status
Simulation time 653128135 ps
CPU time 5.07 seconds
Started Mar 28 01:30:53 PM PDT 24
Finished Mar 28 01:30:58 PM PDT 24
Peak memory 216556 kb
Host smart-20895c57-6795-4b15-88d1-cf32ec7e8500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344504085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.344504085
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.659743442
Short name T800
Test name
Test status
Simulation time 46394404214 ps
CPU time 723.4 seconds
Started Mar 28 01:30:54 PM PDT 24
Finished Mar 28 01:42:57 PM PDT 24
Peak memory 218248 kb
Host smart-72dd10fe-ca87-4d2b-816f-4d2227775bcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659743442 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.659743442
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.621631840
Short name T824
Test name
Test status
Simulation time 137649534 ps
CPU time 1.18 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 215608 kb
Host smart-8543ae95-9603-4f56-9e5c-e820002a9559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621631840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.621631840
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2272511711
Short name T581
Test name
Test status
Simulation time 23295167 ps
CPU time 1.07 seconds
Started Mar 28 01:31:05 PM PDT 24
Finished Mar 28 01:31:07 PM PDT 24
Peak memory 206072 kb
Host smart-26b3aafb-d22e-44fe-95a3-48c14557cf55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272511711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2272511711
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2673060038
Short name T532
Test name
Test status
Simulation time 71662893 ps
CPU time 1.09 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 217800 kb
Host smart-5c9bd0e6-7054-425b-bbc6-aba32b239e11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673060038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2673060038
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1710863043
Short name T61
Test name
Test status
Simulation time 26289059 ps
CPU time 1.34 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:12 PM PDT 24
Peak memory 229836 kb
Host smart-49ee7e7a-27a7-4e91-b75c-a9829f7c2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710863043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1710863043
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1116205603
Short name T595
Test name
Test status
Simulation time 162814495 ps
CPU time 2.43 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 216888 kb
Host smart-29e60bca-bae8-4097-91fe-92e7ef7220c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116205603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1116205603
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2550283829
Short name T481
Test name
Test status
Simulation time 23046030 ps
CPU time 1.13 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 215492 kb
Host smart-eaf5bfc7-e037-4efa-9fe0-44c536b306a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550283829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2550283829
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1874862353
Short name T756
Test name
Test status
Simulation time 69961227 ps
CPU time 0.91 seconds
Started Mar 28 01:31:15 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 215420 kb
Host smart-a0d1d4b9-af03-4ed0-978a-51ca9c98dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874862353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1874862353
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2945388912
Short name T811
Test name
Test status
Simulation time 285080812 ps
CPU time 5.57 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:12 PM PDT 24
Peak memory 219544 kb
Host smart-6dbdf7dd-79b2-4567-b7ed-3c05e6d6b9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945388912 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2945388912
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.982998194
Short name T530
Test name
Test status
Simulation time 60726219519 ps
CPU time 823.45 seconds
Started Mar 28 01:31:05 PM PDT 24
Finished Mar 28 01:44:49 PM PDT 24
Peak memory 220656 kb
Host smart-bf3420f4-01c8-4123-a64c-dbdc82813031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982998194 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.982998194
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2308523367
Short name T245
Test name
Test status
Simulation time 67677598 ps
CPU time 1.12 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 215644 kb
Host smart-2323d03d-b8dd-4e55-84d6-c5cdf44614c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308523367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2308523367
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.912638921
Short name T680
Test name
Test status
Simulation time 151421398 ps
CPU time 0.86 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 205764 kb
Host smart-372dddcd-c128-4f57-a901-637e653b0096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912638921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.912638921
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.56474355
Short name T509
Test name
Test status
Simulation time 16118450 ps
CPU time 0.92 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 215620 kb
Host smart-ab946850-7fb4-4012-b20d-a251c64efafb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56474355 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.56474355
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1165324239
Short name T149
Test name
Test status
Simulation time 23217770 ps
CPU time 1.14 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 217504 kb
Host smart-d82c05aa-fd75-43bc-903e-8fbfbad3dce8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165324239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1165324239
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2523675866
Short name T85
Test name
Test status
Simulation time 27720663 ps
CPU time 0.88 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 217860 kb
Host smart-84f00f1f-c2e8-4eef-8e2f-5799c20eb214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523675866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2523675866
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3887382615
Short name T316
Test name
Test status
Simulation time 36097847 ps
CPU time 1.33 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 218716 kb
Host smart-a238ab2c-3f0c-4551-b7ae-40679f60f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887382615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3887382615
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2715692507
Short name T766
Test name
Test status
Simulation time 41298932 ps
CPU time 0.9 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215556 kb
Host smart-c765cef6-cf1c-46b8-ab2f-4df0fbfea2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715692507 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2715692507
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3237227593
Short name T413
Test name
Test status
Simulation time 14560914 ps
CPU time 1.01 seconds
Started Mar 28 01:31:05 PM PDT 24
Finished Mar 28 01:31:07 PM PDT 24
Peak memory 215296 kb
Host smart-37d24426-a858-400d-83b8-362da6ce2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237227593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3237227593
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2490596581
Short name T34
Test name
Test status
Simulation time 1239840045 ps
CPU time 5.01 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:13 PM PDT 24
Peak memory 219324 kb
Host smart-d1469345-ebe1-4ddf-8126-d1e2840c34c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490596581 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2490596581
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2751811445
Short name T617
Test name
Test status
Simulation time 72970959282 ps
CPU time 1145.74 seconds
Started Mar 28 01:31:13 PM PDT 24
Finished Mar 28 01:50:20 PM PDT 24
Peak memory 223224 kb
Host smart-2122f743-a207-4ebe-80cb-c828e0f7f01f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751811445 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2751811445
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3527342480
Short name T244
Test name
Test status
Simulation time 87894431 ps
CPU time 1.11 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215576 kb
Host smart-fcb8f5ae-100a-401a-8350-21e495023950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527342480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3527342480
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1787833699
Short name T295
Test name
Test status
Simulation time 14856808 ps
CPU time 0.86 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 206788 kb
Host smart-cb69ba51-1d45-4109-8a4a-14bec6274367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787833699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1787833699
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.906503031
Short name T715
Test name
Test status
Simulation time 14271494 ps
CPU time 0.95 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215684 kb
Host smart-a7e99ff8-0511-4b0a-9a66-8403a570eee3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906503031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.906503031
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3487895319
Short name T16
Test name
Test status
Simulation time 24995075 ps
CPU time 0.99 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 232656 kb
Host smart-64c9c4aa-e48f-4e15-b541-f89efd5a7a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487895319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3487895319
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3098159494
Short name T344
Test name
Test status
Simulation time 120231661 ps
CPU time 1.05 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 216644 kb
Host smart-445ec2f8-98f6-443b-b7f3-0c318871fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098159494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3098159494
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1380763420
Short name T358
Test name
Test status
Simulation time 36529418 ps
CPU time 0.99 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 232688 kb
Host smart-0dce2f36-e199-40c3-8734-d453c14c5fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380763420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1380763420
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1423026387
Short name T297
Test name
Test status
Simulation time 154442088 ps
CPU time 0.93 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215264 kb
Host smart-3b644586-b40e-4e09-b090-ff0fdcedb9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423026387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1423026387
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.787102388
Short name T745
Test name
Test status
Simulation time 345819653 ps
CPU time 1.86 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 216616 kb
Host smart-d26008b1-0789-46cd-96d7-e72de9bfb669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787102388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.787102388
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3138970218
Short name T370
Test name
Test status
Simulation time 598320893452 ps
CPU time 883.22 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:45:52 PM PDT 24
Peak memory 221224 kb
Host smart-74f0b0a6-06d2-4f60-b8cb-07d3e2838a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138970218 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3138970218
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4143095574
Short name T728
Test name
Test status
Simulation time 157389988 ps
CPU time 1.35 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 215656 kb
Host smart-7b2e12e2-a3b3-4c52-91a6-47d5bb8547eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143095574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4143095574
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3868154561
Short name T545
Test name
Test status
Simulation time 22878433 ps
CPU time 0.84 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 206360 kb
Host smart-2bcf948d-11ed-4eeb-989f-a1109736ba1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868154561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3868154561
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2343142256
Short name T473
Test name
Test status
Simulation time 23265795 ps
CPU time 0.82 seconds
Started Mar 28 01:31:05 PM PDT 24
Finished Mar 28 01:31:07 PM PDT 24
Peak memory 215404 kb
Host smart-8e7584f8-e103-47b9-9738-19658815562a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343142256 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2343142256
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2825927920
Short name T152
Test name
Test status
Simulation time 141560019 ps
CPU time 1.07 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 216348 kb
Host smart-1dd2fb1f-85da-4237-8f96-6ad040e19a97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825927920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2825927920
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2274473774
Short name T788
Test name
Test status
Simulation time 30274926 ps
CPU time 1.27 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 219024 kb
Host smart-cc675ef7-5c1b-4ee8-9d68-c0982beef03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274473774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2274473774
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.697915285
Short name T703
Test name
Test status
Simulation time 52565733 ps
CPU time 1.37 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 218172 kb
Host smart-2e5fb5e3-a90f-4d75-94d6-9dd7085924db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697915285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.697915285
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.462675304
Short name T125
Test name
Test status
Simulation time 21197942 ps
CPU time 0.92 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215560 kb
Host smart-84323f20-8779-40a9-bbc7-254034de504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462675304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.462675304
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.263831546
Short name T196
Test name
Test status
Simulation time 19331430 ps
CPU time 1.06 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 207148 kb
Host smart-36def11d-82a5-4779-aaf9-be7d0f2b60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263831546 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.263831546
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2676875560
Short name T777
Test name
Test status
Simulation time 1569972430 ps
CPU time 4.72 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:15 PM PDT 24
Peak memory 216448 kb
Host smart-e3193eec-e844-40ec-b9d1-c7c271e6785e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676875560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2676875560
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4239578606
Short name T188
Test name
Test status
Simulation time 76160337936 ps
CPU time 673.31 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:42:22 PM PDT 24
Peak memory 218252 kb
Host smart-eaf1cb11-ea74-4b51-897c-5a808ffae1a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239578606 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4239578606
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.103411948
Short name T712
Test name
Test status
Simulation time 53945949 ps
CPU time 1.16 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 215616 kb
Host smart-12120eb1-0f02-49e2-a385-50cbe48b0b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103411948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.103411948
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2280873467
Short name T749
Test name
Test status
Simulation time 142014092 ps
CPU time 0.84 seconds
Started Mar 28 01:30:16 PM PDT 24
Finished Mar 28 01:30:17 PM PDT 24
Peak memory 206372 kb
Host smart-604670d4-2f2d-4f9b-b8e8-0be4d66d899c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280873467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2280873467
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.606828500
Short name T763
Test name
Test status
Simulation time 37862557 ps
CPU time 0.89 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215772 kb
Host smart-239a17da-35ea-4e16-b2d9-c91bb6dba052
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606828500 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.606828500
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3908882298
Short name T462
Test name
Test status
Simulation time 38606492 ps
CPU time 1.38 seconds
Started Mar 28 01:30:10 PM PDT 24
Finished Mar 28 01:30:11 PM PDT 24
Peak memory 216264 kb
Host smart-b3e9f884-ee35-4fa2-8fce-2224740dda05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908882298 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3908882298
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.218473618
Short name T410
Test name
Test status
Simulation time 94004527 ps
CPU time 1.02 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 219292 kb
Host smart-e248780d-784f-4bba-ba7d-60e9c19baac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218473618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.218473618
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2319188509
Short name T710
Test name
Test status
Simulation time 56262895 ps
CPU time 1.92 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 217792 kb
Host smart-806ee770-a284-442e-b977-3f96371e45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319188509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2319188509
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.902080242
Short name T593
Test name
Test status
Simulation time 26169568 ps
CPU time 0.93 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 215572 kb
Host smart-3a2e18d4-637a-4f90-9bff-078409a27886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902080242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.902080242
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3064261778
Short name T256
Test name
Test status
Simulation time 36077113 ps
CPU time 0.9 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 206912 kb
Host smart-ddf3fcc2-0d46-4095-94d3-905152b5af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064261778 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3064261778
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2420612965
Short name T45
Test name
Test status
Simulation time 1216291783 ps
CPU time 5.4 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 235372 kb
Host smart-3f625ee4-e213-432c-b8f6-c190f507bf38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420612965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2420612965
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.4266199779
Short name T451
Test name
Test status
Simulation time 95166244 ps
CPU time 0.92 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215236 kb
Host smart-cdbc7c71-cca8-4dd8-a11d-889be895f608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266199779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4266199779
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3705784655
Short name T555
Test name
Test status
Simulation time 690587318 ps
CPU time 3.78 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 219572 kb
Host smart-67f1d5bf-757f-4f36-8647-d32e60666bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705784655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3705784655
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3981625993
Short name T605
Test name
Test status
Simulation time 60892775493 ps
CPU time 822.42 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:43:54 PM PDT 24
Peak memory 219400 kb
Host smart-ee3b5550-1554-466c-bb33-60017be5ffe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981625993 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3981625993
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.528056177
Short name T553
Test name
Test status
Simulation time 25144218 ps
CPU time 1.23 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 215216 kb
Host smart-5c20eed0-66f5-488d-a44c-d9850837b73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528056177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.528056177
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3147799444
Short name T343
Test name
Test status
Simulation time 41594950 ps
CPU time 0.87 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 206560 kb
Host smart-8548b92b-84a0-4d41-9abe-bf9704d7f43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147799444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3147799444
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1044430241
Short name T759
Test name
Test status
Simulation time 18603366 ps
CPU time 0.87 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 215804 kb
Host smart-29170863-f7b8-430c-9ab1-ca3b2c3ef4d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044430241 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1044430241
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2466678352
Short name T319
Test name
Test status
Simulation time 35565460 ps
CPU time 1.19 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 217696 kb
Host smart-ede9d492-9098-4d7b-b932-068ea278bb74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466678352 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2466678352
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3903546773
Short name T166
Test name
Test status
Simulation time 52036077 ps
CPU time 1.02 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 218056 kb
Host smart-eacceec0-e368-4290-b6b6-87a1ab82fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903546773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3903546773
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1828834382
Short name T586
Test name
Test status
Simulation time 49206308 ps
CPU time 1.19 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 219572 kb
Host smart-afe75225-8ad6-4aa6-a0c1-b9a58e01e633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828834382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1828834382
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.346531927
Short name T503
Test name
Test status
Simulation time 22842003 ps
CPU time 0.98 seconds
Started Mar 28 01:31:11 PM PDT 24
Finished Mar 28 01:31:12 PM PDT 24
Peak memory 215528 kb
Host smart-7aecd8ab-837f-4192-8aa1-b93a980345ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346531927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.346531927
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2413848294
Short name T588
Test name
Test status
Simulation time 45990415 ps
CPU time 1.07 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 215208 kb
Host smart-b9b983f5-9c22-4bc9-b50f-f028033370e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413848294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2413848294
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2655008935
Short name T769
Test name
Test status
Simulation time 250856344 ps
CPU time 5.4 seconds
Started Mar 28 01:31:13 PM PDT 24
Finished Mar 28 01:31:19 PM PDT 24
Peak memory 216528 kb
Host smart-7a0f7b64-e440-4d2d-ab52-384b26436d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655008935 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2655008935
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2375205106
Short name T369
Test name
Test status
Simulation time 149893867638 ps
CPU time 1693.85 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:59:24 PM PDT 24
Peak memory 225284 kb
Host smart-b0ebcaaf-6eaa-4dca-974c-cbfdabc0fbf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375205106 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2375205106
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2775064169
Short name T519
Test name
Test status
Simulation time 48887546 ps
CPU time 1.27 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 215608 kb
Host smart-e0626d28-96f3-4e8b-a1ba-c6974983c084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775064169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2775064169
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2277565569
Short name T520
Test name
Test status
Simulation time 45915399 ps
CPU time 0.92 seconds
Started Mar 28 01:31:17 PM PDT 24
Finished Mar 28 01:31:18 PM PDT 24
Peak memory 205988 kb
Host smart-4a6ffda8-3d1b-4c09-8b4a-4f0186d08217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277565569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2277565569
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3684317390
Short name T177
Test name
Test status
Simulation time 13890209 ps
CPU time 0.95 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 216028 kb
Host smart-9889181f-bf00-4497-a974-8077272e3fcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684317390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3684317390
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2195077480
Short name T430
Test name
Test status
Simulation time 48321104 ps
CPU time 1.13 seconds
Started Mar 28 01:31:17 PM PDT 24
Finished Mar 28 01:31:18 PM PDT 24
Peak memory 216540 kb
Host smart-c59ffd68-4e0d-42fe-a8dd-e346029aabf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195077480 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2195077480
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.259048178
Short name T648
Test name
Test status
Simulation time 26121159 ps
CPU time 1.18 seconds
Started Mar 28 01:31:13 PM PDT 24
Finished Mar 28 01:31:15 PM PDT 24
Peak memory 218192 kb
Host smart-9ad26b7c-d989-4c0d-b81e-8ec4478c45ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259048178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.259048178
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1256650057
Short name T425
Test name
Test status
Simulation time 77491425 ps
CPU time 1.46 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 218000 kb
Host smart-981aac89-aaa5-431e-b29b-82a0414eb5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256650057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1256650057
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1740800868
Short name T403
Test name
Test status
Simulation time 39775920 ps
CPU time 0.97 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 224116 kb
Host smart-ae65028a-5d49-4fad-ad80-cdba8e5b9770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740800868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1740800868
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2796682129
Short name T378
Test name
Test status
Simulation time 53211843 ps
CPU time 0.92 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 215328 kb
Host smart-783b08c5-28b6-4012-b830-04f3f03ad761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796682129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2796682129
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.794215151
Short name T660
Test name
Test status
Simulation time 424863229 ps
CPU time 3.53 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:10 PM PDT 24
Peak memory 216236 kb
Host smart-2d85abbe-b046-46a2-9481-fade35c6d004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794215151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.794215151
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.390330748
Short name T191
Test name
Test status
Simulation time 17552603775 ps
CPU time 385.01 seconds
Started Mar 28 01:31:09 PM PDT 24
Finished Mar 28 01:37:34 PM PDT 24
Peak memory 218484 kb
Host smart-5c229396-c3fc-43aa-a601-dbfb69e0f251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390330748 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.390330748
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.858005113
Short name T812
Test name
Test status
Simulation time 71504826 ps
CPU time 1.2 seconds
Started Mar 28 01:31:17 PM PDT 24
Finished Mar 28 01:31:18 PM PDT 24
Peak memory 215604 kb
Host smart-a8a22ff5-68c7-498a-b012-8e4f34d20124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858005113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.858005113
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3975859275
Short name T308
Test name
Test status
Simulation time 28981343 ps
CPU time 0.79 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 205544 kb
Host smart-83c6bc3b-bb5c-4a18-bb58-27f91a99e386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975859275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3975859275
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1422200595
Short name T156
Test name
Test status
Simulation time 16938221 ps
CPU time 0.88 seconds
Started Mar 28 01:31:12 PM PDT 24
Finished Mar 28 01:31:14 PM PDT 24
Peak memory 215808 kb
Host smart-524edcc4-c467-4916-8747-aa3ac06b90ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422200595 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1422200595
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.478931840
Short name T165
Test name
Test status
Simulation time 26911935 ps
CPU time 1.14 seconds
Started Mar 28 01:31:12 PM PDT 24
Finished Mar 28 01:31:13 PM PDT 24
Peak memory 216452 kb
Host smart-d4bdb31d-118c-4b5f-b01e-a24e679b0d93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478931840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.478931840
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1062672176
Short name T779
Test name
Test status
Simulation time 29668967 ps
CPU time 1 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:18 PM PDT 24
Peak memory 222840 kb
Host smart-23e78711-a25a-4d4b-a6f0-0536043ff1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062672176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1062672176
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4108806248
Short name T693
Test name
Test status
Simulation time 44789701 ps
CPU time 1.58 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 217872 kb
Host smart-044f8cea-880c-4a0a-91fa-8b05bc897dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108806248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4108806248
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1354731580
Short name T550
Test name
Test status
Simulation time 44155328 ps
CPU time 0.91 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 214984 kb
Host smart-27f96b66-b14d-406c-89cc-c69da8e6bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354731580 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1354731580
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3041692128
Short name T762
Test name
Test status
Simulation time 19568048 ps
CPU time 1.01 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 215264 kb
Host smart-04cad09f-d02b-4ca5-8455-078c9e56c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041692128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3041692128
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.483936442
Short name T576
Test name
Test status
Simulation time 231614319 ps
CPU time 4.6 seconds
Started Mar 28 01:31:18 PM PDT 24
Finished Mar 28 01:31:23 PM PDT 24
Peak memory 218988 kb
Host smart-4f3f42f2-d98f-441d-9b0a-ca2d455ee61d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483936442 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.483936442
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1432323397
Short name T190
Test name
Test status
Simulation time 132619511517 ps
CPU time 1348.93 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:53:45 PM PDT 24
Peak memory 221992 kb
Host smart-7d674e7d-0395-4f53-bdcc-444f015120a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432323397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1432323397
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.114856182
Short name T175
Test name
Test status
Simulation time 50515793 ps
CPU time 1.26 seconds
Started Mar 28 01:31:18 PM PDT 24
Finished Mar 28 01:31:20 PM PDT 24
Peak memory 215620 kb
Host smart-9ba0b153-a37a-467c-8c48-824a25f8faea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114856182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.114856182
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3630532380
Short name T142
Test name
Test status
Simulation time 70759506 ps
CPU time 0.93 seconds
Started Mar 28 01:31:17 PM PDT 24
Finished Mar 28 01:31:18 PM PDT 24
Peak memory 206552 kb
Host smart-6d75c07c-7f1d-429d-867d-bc5766f24285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630532380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3630532380
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2008949760
Short name T739
Test name
Test status
Simulation time 11662914 ps
CPU time 0.9 seconds
Started Mar 28 01:31:11 PM PDT 24
Finished Mar 28 01:31:12 PM PDT 24
Peak memory 215868 kb
Host smart-628dfbeb-0418-47c1-b075-47dcd06b7bc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008949760 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2008949760
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1330858861
Short name T158
Test name
Test status
Simulation time 40896414 ps
CPU time 1.42 seconds
Started Mar 28 01:31:15 PM PDT 24
Finished Mar 28 01:31:17 PM PDT 24
Peak memory 216500 kb
Host smart-e028deed-aa83-4d84-ae91-96db34510e08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330858861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1330858861
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3080423705
Short name T726
Test name
Test status
Simulation time 22454055 ps
CPU time 1.15 seconds
Started Mar 28 01:31:15 PM PDT 24
Finished Mar 28 01:31:16 PM PDT 24
Peak memory 218120 kb
Host smart-21735298-576b-4c03-907e-b454df3367d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080423705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3080423705
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1228938386
Short name T411
Test name
Test status
Simulation time 63608895 ps
CPU time 1.35 seconds
Started Mar 28 01:31:15 PM PDT 24
Finished Mar 28 01:31:16 PM PDT 24
Peak memory 218068 kb
Host smart-66435346-991a-4705-b3d0-8ae7756016f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228938386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1228938386
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2516025356
Short name T701
Test name
Test status
Simulation time 86807265 ps
CPU time 0.95 seconds
Started Mar 28 01:31:10 PM PDT 24
Finished Mar 28 01:31:11 PM PDT 24
Peak memory 223948 kb
Host smart-7c2372b2-f7e1-4d2e-b794-c9e09bb315d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516025356 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2516025356
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3799392421
Short name T674
Test name
Test status
Simulation time 22817726 ps
CPU time 0.92 seconds
Started Mar 28 01:31:15 PM PDT 24
Finished Mar 28 01:31:16 PM PDT 24
Peak memory 215336 kb
Host smart-04b7283e-12d1-4ab3-8db6-fc5aab2fc516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799392421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3799392421
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.371847668
Short name T467
Test name
Test status
Simulation time 304657050 ps
CPU time 2.11 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:19 PM PDT 24
Peak memory 219352 kb
Host smart-d7314039-c90b-48bf-9ee7-294ccf2e203e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371847668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.371847668
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.2535549408
Short name T90
Test name
Test status
Simulation time 58835495 ps
CPU time 1.14 seconds
Started Mar 28 01:32:20 PM PDT 24
Finished Mar 28 01:32:22 PM PDT 24
Peak memory 215672 kb
Host smart-4bd689fb-64f3-47af-81d0-e0375f28437e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535549408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2535549408
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.4163085328
Short name T835
Test name
Test status
Simulation time 11647699 ps
CPU time 0.81 seconds
Started Mar 28 01:31:07 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 205600 kb
Host smart-10080ec3-ef53-492f-afa7-be990c9a250f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163085328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4163085328
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1588082059
Short name T709
Test name
Test status
Simulation time 36044300 ps
CPU time 0.82 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 215864 kb
Host smart-4f001a7a-059b-4281-9c2f-f21865f11a92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588082059 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1588082059
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1043513223
Short name T395
Test name
Test status
Simulation time 34984153 ps
CPU time 1.15 seconds
Started Mar 28 01:31:12 PM PDT 24
Finished Mar 28 01:31:14 PM PDT 24
Peak memory 217740 kb
Host smart-497e660f-b65f-48e7-bfdb-38781033af77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043513223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1043513223
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3091910815
Short name T159
Test name
Test status
Simulation time 82229380 ps
CPU time 1.09 seconds
Started Mar 28 01:31:12 PM PDT 24
Finished Mar 28 01:31:14 PM PDT 24
Peak memory 219020 kb
Host smart-e3983104-02d2-4b8f-b0ec-e1ebac21f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091910815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3091910815
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1853941750
Short name T466
Test name
Test status
Simulation time 36864796 ps
CPU time 1.31 seconds
Started Mar 28 01:31:08 PM PDT 24
Finished Mar 28 01:31:09 PM PDT 24
Peak memory 218932 kb
Host smart-26186aff-bb7f-43ea-a61c-133526283002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853941750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1853941750
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2103353475
Short name T372
Test name
Test status
Simulation time 22084656 ps
CPU time 1.2 seconds
Started Mar 28 01:31:18 PM PDT 24
Finished Mar 28 01:31:19 PM PDT 24
Peak memory 224500 kb
Host smart-d7a940ba-548d-42f8-904e-f1656c8bc32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103353475 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2103353475
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2080198406
Short name T559
Test name
Test status
Simulation time 39036875 ps
CPU time 0.86 seconds
Started Mar 28 01:31:17 PM PDT 24
Finished Mar 28 01:31:18 PM PDT 24
Peak memory 215304 kb
Host smart-b7534a25-4afb-422f-b3f5-974d67e391bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080198406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2080198406
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1691522312
Short name T587
Test name
Test status
Simulation time 906940460 ps
CPU time 3.67 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:31:20 PM PDT 24
Peak memory 216504 kb
Host smart-4068665b-1592-4e03-bb62-a54e422f6714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691522312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1691522312
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1606538918
Short name T493
Test name
Test status
Simulation time 77956266115 ps
CPU time 981.22 seconds
Started Mar 28 01:31:16 PM PDT 24
Finished Mar 28 01:47:37 PM PDT 24
Peak memory 222572 kb
Host smart-b250edf1-480d-4839-92ce-d85e0437b032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606538918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1606538918
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2646208852
Short name T105
Test name
Test status
Simulation time 35285895 ps
CPU time 1.16 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 215648 kb
Host smart-489bac6d-28fd-438b-912c-a541250d51a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646208852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2646208852
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1312828482
Short name T310
Test name
Test status
Simulation time 43591167 ps
CPU time 1.16 seconds
Started Mar 28 01:31:22 PM PDT 24
Finished Mar 28 01:31:23 PM PDT 24
Peak memory 206092 kb
Host smart-8e235780-6252-4aa5-94c9-4d3293b1b9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312828482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1312828482
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.116100402
Short name T649
Test name
Test status
Simulation time 34922265 ps
CPU time 0.88 seconds
Started Mar 28 01:31:22 PM PDT 24
Finished Mar 28 01:31:23 PM PDT 24
Peak memory 215808 kb
Host smart-4ee73bb5-a19f-418f-b985-b63f3f612367
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116100402 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.116100402
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2863461654
Short name T577
Test name
Test status
Simulation time 149554767 ps
CPU time 1.29 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:26 PM PDT 24
Peak memory 216488 kb
Host smart-9bdc239c-9b18-45e9-9523-948f0efc8c22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863461654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2863461654
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1821628023
Short name T38
Test name
Test status
Simulation time 21620869 ps
CPU time 1 seconds
Started Mar 28 01:31:26 PM PDT 24
Finished Mar 28 01:31:27 PM PDT 24
Peak memory 222860 kb
Host smart-2f72c783-0301-4bb7-a0d3-2f5750bbe018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821628023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1821628023
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3338725173
Short name T232
Test name
Test status
Simulation time 48262165 ps
CPU time 1.49 seconds
Started Mar 28 01:31:06 PM PDT 24
Finished Mar 28 01:31:08 PM PDT 24
Peak memory 217848 kb
Host smart-a6010903-f739-458c-8d49-458e666e9670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338725173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3338725173
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.567000219
Short name T522
Test name
Test status
Simulation time 22100801 ps
CPU time 1.13 seconds
Started Mar 28 01:31:27 PM PDT 24
Finished Mar 28 01:31:28 PM PDT 24
Peak memory 215440 kb
Host smart-7617b0e0-fc0e-4d8e-83e2-5e8524d41982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567000219 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.567000219
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1030290806
Short name T780
Test name
Test status
Simulation time 26945870 ps
CPU time 0.89 seconds
Started Mar 28 01:31:11 PM PDT 24
Finished Mar 28 01:31:12 PM PDT 24
Peak memory 215272 kb
Host smart-2f1ba643-8194-4613-8599-bdae463822c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030290806 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1030290806
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3028270950
Short name T264
Test name
Test status
Simulation time 159949290 ps
CPU time 3.46 seconds
Started Mar 28 01:31:11 PM PDT 24
Finished Mar 28 01:31:15 PM PDT 24
Peak memory 217752 kb
Host smart-37e8e379-9b11-49f0-964b-caf0b428a8ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028270950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3028270950
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.600935486
Short name T243
Test name
Test status
Simulation time 86280118 ps
CPU time 1.19 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 215636 kb
Host smart-ac969a65-6e98-44f7-bfa9-05229a50b03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600935486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.600935486
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2855191483
Short name T673
Test name
Test status
Simulation time 40382148 ps
CPU time 0.91 seconds
Started Mar 28 01:31:23 PM PDT 24
Finished Mar 28 01:31:24 PM PDT 24
Peak memory 206492 kb
Host smart-4251e726-3bc9-4c2f-9425-719ff3efd53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855191483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2855191483
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2694918850
Short name T692
Test name
Test status
Simulation time 12116660 ps
CPU time 0.9 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 215548 kb
Host smart-864b4c97-f3b9-41e6-8087-9687e70268c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694918850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2694918850
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.185896566
Short name T533
Test name
Test status
Simulation time 27950660 ps
CPU time 1.07 seconds
Started Mar 28 01:31:29 PM PDT 24
Finished Mar 28 01:31:30 PM PDT 24
Peak memory 218004 kb
Host smart-af711c5c-4747-40a6-ac6f-5105a9d59dd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185896566 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.185896566
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.47362800
Short name T160
Test name
Test status
Simulation time 57331331 ps
CPU time 0.86 seconds
Started Mar 28 01:31:23 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 217812 kb
Host smart-65a04cee-0bfc-4ba4-9998-0a13f6d55003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47362800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.47362800
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.315839242
Short name T394
Test name
Test status
Simulation time 132366538 ps
CPU time 1.37 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:31:27 PM PDT 24
Peak memory 218532 kb
Host smart-45c69257-580e-461c-87e3-bfb67db077ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315839242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.315839242
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_smoke.2015164688
Short name T109
Test name
Test status
Simulation time 45966567 ps
CPU time 0.92 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:31:27 PM PDT 24
Peak memory 215344 kb
Host smart-5a645e1a-1a25-4c49-94dc-6b29796d7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015164688 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2015164688
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1303191539
Short name T574
Test name
Test status
Simulation time 471438493 ps
CPU time 5.67 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:31:32 PM PDT 24
Peak memory 215328 kb
Host smart-521366cf-943c-4818-9744-5582543a2727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303191539 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1303191539
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.837425697
Short name T753
Test name
Test status
Simulation time 182025561602 ps
CPU time 1065.5 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:49:09 PM PDT 24
Peak memory 223664 kb
Host smart-a43772d0-b009-470b-9ec3-09cc213b615a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837425697 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.837425697
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.591972756
Short name T252
Test name
Test status
Simulation time 42188898 ps
CPU time 1.16 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 215612 kb
Host smart-1dd0858c-433a-4f2a-ba7f-3405844c5eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591972756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.591972756
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3517198727
Short name T398
Test name
Test status
Simulation time 24266489 ps
CPU time 0.9 seconds
Started Mar 28 01:31:27 PM PDT 24
Finished Mar 28 01:31:28 PM PDT 24
Peak memory 205972 kb
Host smart-c7bbfd54-db36-4070-a1ab-544b6ee06932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517198727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3517198727
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3804792839
Short name T735
Test name
Test status
Simulation time 11488616 ps
CPU time 0.85 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:31:26 PM PDT 24
Peak memory 215792 kb
Host smart-41a4a34d-c974-4889-9407-7881c1548df5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804792839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3804792839
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4005609617
Short name T63
Test name
Test status
Simulation time 48206624 ps
CPU time 1.11 seconds
Started Mar 28 01:31:23 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 216460 kb
Host smart-9f97ac54-16bb-4894-b209-a788ce64b654
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005609617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4005609617
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1762092251
Short name T643
Test name
Test status
Simulation time 31193318 ps
CPU time 1.04 seconds
Started Mar 28 01:31:23 PM PDT 24
Finished Mar 28 01:31:24 PM PDT 24
Peak memory 232456 kb
Host smart-f9504faf-92a3-4f6a-87b1-8f567ed056e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762092251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1762092251
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2278111815
Short name T729
Test name
Test status
Simulation time 69735496 ps
CPU time 1.15 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 216932 kb
Host smart-c800b6bd-498a-4268-a439-dfda68c3169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278111815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2278111815
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.4171943100
Short name T478
Test name
Test status
Simulation time 19593454 ps
CPU time 1.09 seconds
Started Mar 28 01:31:21 PM PDT 24
Finished Mar 28 01:31:23 PM PDT 24
Peak memory 215716 kb
Host smart-096aa753-0526-4bce-b72e-dea0a2ff5d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171943100 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4171943100
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1668515661
Short name T287
Test name
Test status
Simulation time 66588649 ps
CPU time 0.89 seconds
Started Mar 28 01:31:29 PM PDT 24
Finished Mar 28 01:31:30 PM PDT 24
Peak memory 215120 kb
Host smart-f215e865-6d71-4a9d-ba20-fb3fc907d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668515661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1668515661
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.931630843
Short name T463
Test name
Test status
Simulation time 214817104 ps
CPU time 2.87 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:27 PM PDT 24
Peak memory 216504 kb
Host smart-bf1cc404-528e-4894-99a8-17ee0e418712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931630843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.931630843
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1916769197
Short name T182
Test name
Test status
Simulation time 65962881477 ps
CPU time 775.9 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:44:22 PM PDT 24
Peak memory 219460 kb
Host smart-33673e39-c4db-4038-aae0-03e5125f7fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916769197 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1916769197
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1289915541
Short name T19
Test name
Test status
Simulation time 58836975 ps
CPU time 1.37 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:26 PM PDT 24
Peak memory 215636 kb
Host smart-8612ead7-2e11-44bf-af55-2b40976fcb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289915541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1289915541
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.969831289
Short name T628
Test name
Test status
Simulation time 22763479 ps
CPU time 0.92 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 205960 kb
Host smart-60537a27-e450-4b11-a555-d9d3147007b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969831289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.969831289
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2995473903
Short name T653
Test name
Test status
Simulation time 223105137 ps
CPU time 1.09 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:26 PM PDT 24
Peak memory 216492 kb
Host smart-30c0447c-f3f1-4458-beb0-8c3a670b691b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995473903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2995473903
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2267663789
Short name T73
Test name
Test status
Simulation time 34738113 ps
CPU time 0.9 seconds
Started Mar 28 01:31:25 PM PDT 24
Finished Mar 28 01:31:27 PM PDT 24
Peak memory 219364 kb
Host smart-2408940b-2371-4e1a-a987-22424b7fd7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267663789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2267663789
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1431662386
Short name T578
Test name
Test status
Simulation time 42211102 ps
CPU time 1.4 seconds
Started Mar 28 01:31:34 PM PDT 24
Finished Mar 28 01:31:35 PM PDT 24
Peak memory 216584 kb
Host smart-2e09f77f-ad52-4b9c-a6b9-85e3921950a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431662386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1431662386
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4294250494
Short name T124
Test name
Test status
Simulation time 28086389 ps
CPU time 0.91 seconds
Started Mar 28 01:31:23 PM PDT 24
Finished Mar 28 01:31:24 PM PDT 24
Peak memory 215660 kb
Host smart-3fc321f9-b8a6-4c26-a746-12c758858a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294250494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4294250494
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4029226877
Short name T454
Test name
Test status
Simulation time 81921790 ps
CPU time 0.92 seconds
Started Mar 28 01:31:23 PM PDT 24
Finished Mar 28 01:31:24 PM PDT 24
Peak memory 215344 kb
Host smart-db74e0e0-f367-4377-91d7-25c8636291ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029226877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4029226877
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3388164191
Short name T764
Test name
Test status
Simulation time 280713947 ps
CPU time 5.68 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:30 PM PDT 24
Peak memory 219168 kb
Host smart-98e834a7-958f-49ce-a9fb-7bf0ed4eaacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388164191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3388164191
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3712216277
Short name T510
Test name
Test status
Simulation time 64134213870 ps
CPU time 758.44 seconds
Started Mar 28 01:31:22 PM PDT 24
Finished Mar 28 01:44:01 PM PDT 24
Peak memory 223672 kb
Host smart-a610eb1c-c0dc-45d3-8e6c-0d6c471d0f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712216277 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3712216277
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3023529829
Short name T784
Test name
Test status
Simulation time 64158579 ps
CPU time 1.12 seconds
Started Mar 28 01:31:45 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 215576 kb
Host smart-e227d2c8-3012-43c1-a1ef-f405bdd337b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023529829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3023529829
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1130860921
Short name T695
Test name
Test status
Simulation time 17981494 ps
CPU time 1 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 205912 kb
Host smart-9b950852-8d78-443f-acce-12c1174850c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130860921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1130860921
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.597448851
Short name T150
Test name
Test status
Simulation time 12606992 ps
CPU time 0.87 seconds
Started Mar 28 01:31:41 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 215856 kb
Host smart-82a91463-2fb5-474a-b3ed-f9a71fd2cd0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597448851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.597448851
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3350498197
Short name T778
Test name
Test status
Simulation time 56640946 ps
CPU time 1.18 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 216464 kb
Host smart-1e5f7cad-24f9-4f69-ba14-5ec1a87227d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350498197 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3350498197
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1776278277
Short name T758
Test name
Test status
Simulation time 29610650 ps
CPU time 0.87 seconds
Started Mar 28 01:31:53 PM PDT 24
Finished Mar 28 01:31:54 PM PDT 24
Peak memory 217692 kb
Host smart-cae708e5-bc0f-49db-8c6c-b904282f7b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776278277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1776278277
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1139263587
Short name T651
Test name
Test status
Simulation time 30721587 ps
CPU time 1.36 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 219284 kb
Host smart-fa7ca976-605b-4315-8643-e5a7e68fd776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139263587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1139263587
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3744259847
Short name T711
Test name
Test status
Simulation time 21273756 ps
CPU time 1.21 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 224068 kb
Host smart-89da23d4-0d51-42f6-a4ca-b2041e37095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744259847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3744259847
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1862411999
Short name T597
Test name
Test status
Simulation time 49769549 ps
CPU time 0.94 seconds
Started Mar 28 01:31:24 PM PDT 24
Finished Mar 28 01:31:25 PM PDT 24
Peak memory 215248 kb
Host smart-80628ca2-e547-46b3-aa88-6c27a1d839a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862411999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1862411999
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2512459435
Short name T667
Test name
Test status
Simulation time 704903642 ps
CPU time 4.58 seconds
Started Mar 28 01:31:53 PM PDT 24
Finished Mar 28 01:31:57 PM PDT 24
Peak memory 216452 kb
Host smart-99dd902c-48e1-433d-8c42-58b8cf782641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512459435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2512459435
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3577907636
Short name T373
Test name
Test status
Simulation time 571420314004 ps
CPU time 1546.03 seconds
Started Mar 28 01:31:44 PM PDT 24
Finished Mar 28 01:57:30 PM PDT 24
Peak memory 226272 kb
Host smart-a7a19374-4786-4ea6-8131-086817af4e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577907636 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3577907636
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.437374164
Short name T247
Test name
Test status
Simulation time 29131324 ps
CPU time 1.29 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215656 kb
Host smart-6ee2af58-d935-4a60-92b7-a18a93a1a725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437374164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.437374164
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1151656245
Short name T391
Test name
Test status
Simulation time 22176884 ps
CPU time 0.95 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 206600 kb
Host smart-f6d2f0f9-fe44-4101-a5c8-95d36f925123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151656245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1151656245
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2656109275
Short name T609
Test name
Test status
Simulation time 12223956 ps
CPU time 0.91 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 216048 kb
Host smart-0ced1ec9-5749-433a-8528-567faee398f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656109275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2656109275
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.2500101658
Short name T46
Test name
Test status
Simulation time 43167666 ps
CPU time 1.02 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 217964 kb
Host smart-ed4ab019-9b23-49ac-82fc-f4617acaaf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500101658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2500101658
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1568145429
Short name T789
Test name
Test status
Simulation time 30175119 ps
CPU time 1.54 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 216984 kb
Host smart-ddfcefe4-fcc6-4c83-ac5c-17ac7a442397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568145429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1568145429
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2315719198
Short name T546
Test name
Test status
Simulation time 35500572 ps
CPU time 0.83 seconds
Started Mar 28 01:30:10 PM PDT 24
Finished Mar 28 01:30:11 PM PDT 24
Peak memory 215536 kb
Host smart-5c9a2581-da51-47b3-9c22-3ec049511c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315719198 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2315719198
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.3030675067
Short name T389
Test name
Test status
Simulation time 27488580 ps
CPU time 0.99 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 207092 kb
Host smart-4687b288-7ba3-4af9-a89c-00c1f508fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030675067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3030675067
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.364958284
Short name T613
Test name
Test status
Simulation time 275748974 ps
CPU time 6.11 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 215332 kb
Host smart-527294f2-a02c-4c71-8497-9a9de89e9012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364958284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.364958284
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.506966161
Short name T130
Test name
Test status
Simulation time 98649084374 ps
CPU time 609.05 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:40:24 PM PDT 24
Peak memory 223700 kb
Host smart-229fce6d-d6b7-41e4-8189-42504370ecc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506966161 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.506966161
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3421185898
Short name T497
Test name
Test status
Simulation time 19135463 ps
CPU time 1.08 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 215468 kb
Host smart-96c94486-b2e3-4667-b395-e0e85e06b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421185898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3421185898
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2026670121
Short name T444
Test name
Test status
Simulation time 43813543 ps
CPU time 1.31 seconds
Started Mar 28 01:31:53 PM PDT 24
Finished Mar 28 01:31:54 PM PDT 24
Peak memory 217724 kb
Host smart-9e855dd8-0031-4524-9a6e-9449fe5df553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026670121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2026670121
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2642992646
Short name T86
Test name
Test status
Simulation time 34168027 ps
CPU time 0.91 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:44 PM PDT 24
Peak memory 217700 kb
Host smart-a41eaeab-b679-4b81-84df-16ee28153a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642992646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2642992646
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.335967827
Short name T280
Test name
Test status
Simulation time 97097927 ps
CPU time 1.72 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218128 kb
Host smart-769fb86e-bac7-42e3-a7e9-6d574e517615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335967827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.335967827
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2284412076
Short name T404
Test name
Test status
Simulation time 37631228 ps
CPU time 1.08 seconds
Started Mar 28 01:31:53 PM PDT 24
Finished Mar 28 01:31:54 PM PDT 24
Peak memory 217844 kb
Host smart-4a6e8d1e-ee48-4fc0-90f9-6d7fed2183ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284412076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2284412076
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3234536162
Short name T832
Test name
Test status
Simulation time 25650229 ps
CPU time 1.24 seconds
Started Mar 28 01:31:44 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 216820 kb
Host smart-92a47ead-26cf-424d-894b-47de234427bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234536162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3234536162
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3164378060
Short name T6
Test name
Test status
Simulation time 40319607 ps
CPU time 1.02 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 219280 kb
Host smart-ac59a639-8e7f-4ceb-887c-4eb546727d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164378060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3164378060
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1091274227
Short name T662
Test name
Test status
Simulation time 39799222 ps
CPU time 1.56 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 217720 kb
Host smart-69cff954-ff92-42a5-916a-f096c8adbdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091274227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1091274227
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.415808359
Short name T796
Test name
Test status
Simulation time 27914382 ps
CPU time 1.35 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:44 PM PDT 24
Peak memory 232312 kb
Host smart-7fd1dc06-5587-4ff3-83c2-d21f0ae37456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415808359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.415808359
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.882792386
Short name T320
Test name
Test status
Simulation time 98684938 ps
CPU time 1.1 seconds
Started Mar 28 01:31:39 PM PDT 24
Finished Mar 28 01:31:40 PM PDT 24
Peak memory 217988 kb
Host smart-4d8baa83-7da3-42d3-8927-359ceff5dc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882792386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.882792386
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1375769848
Short name T637
Test name
Test status
Simulation time 20870224 ps
CPU time 1.05 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 231268 kb
Host smart-c28acdc1-0c2d-4222-8b25-5ac8d30d6fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375769848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1375769848
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2066016580
Short name T465
Test name
Test status
Simulation time 34041215 ps
CPU time 1.52 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 218028 kb
Host smart-26e836cb-7345-4ea5-abfe-e523aadc21b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066016580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2066016580
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2843115501
Short name T162
Test name
Test status
Simulation time 34545894 ps
CPU time 1.25 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 224288 kb
Host smart-0dc1b002-c8b7-4254-a62d-3aeaed064aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843115501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2843115501
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3842078419
Short name T736
Test name
Test status
Simulation time 59825508 ps
CPU time 1.27 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 217804 kb
Host smart-81f05c26-b833-4fc8-bd8c-df5dbc4b5455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842078419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3842078419
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2186276416
Short name T551
Test name
Test status
Simulation time 21388249 ps
CPU time 0.95 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 218124 kb
Host smart-d5a805ab-0db8-42e0-ae41-f6776e880b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186276416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2186276416
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.843596692
Short name T261
Test name
Test status
Simulation time 48540926 ps
CPU time 1.49 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218020 kb
Host smart-3c98e8fc-a867-4ba7-931b-9a50004091c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843596692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.843596692
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1518053476
Short name T95
Test name
Test status
Simulation time 21997098 ps
CPU time 0.89 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 217676 kb
Host smart-1034946f-5eaf-4fca-a774-dbc66e95d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518053476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1518053476
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2731618168
Short name T585
Test name
Test status
Simulation time 102364951 ps
CPU time 2.43 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 218032 kb
Host smart-57e7fc12-90c4-4c2a-80b6-6f0e2c80f8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731618168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2731618168
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1474727872
Short name T761
Test name
Test status
Simulation time 20080431 ps
CPU time 1.36 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 229880 kb
Host smart-d4e59ac8-f346-41fd-a026-380403faad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474727872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1474727872
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.64230151
Short name T589
Test name
Test status
Simulation time 48773138 ps
CPU time 1.67 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 217792 kb
Host smart-ae5b18a0-75f9-45fa-9401-045d88ae6cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64230151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.64230151
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.2070022428
Short name T311
Test name
Test status
Simulation time 20401315 ps
CPU time 0.83 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 205524 kb
Host smart-e9c3abb7-d415-4d2b-b0da-bc5651754613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070022428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2070022428
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2144104612
Short name T754
Test name
Test status
Simulation time 20912026 ps
CPU time 0.87 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 215388 kb
Host smart-2f1d1a83-2150-4e44-b03b-d3d7a1518fad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144104612 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2144104612
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.357532023
Short name T705
Test name
Test status
Simulation time 49574317 ps
CPU time 1.14 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 216484 kb
Host smart-7f1b0f43-4e04-4459-9779-4b2636ae2039
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357532023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.357532023
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.453648850
Short name T772
Test name
Test status
Simulation time 63960905 ps
CPU time 0.81 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 217592 kb
Host smart-1ce2d773-da0b-4059-85c3-167492f6ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453648850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.453648850
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1661582401
Short name T32
Test name
Test status
Simulation time 38925401 ps
CPU time 1.54 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 217816 kb
Host smart-01727955-bc9e-4a88-9ece-8a1d10bed2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661582401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1661582401
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1109838473
Short name T485
Test name
Test status
Simulation time 31303621 ps
CPU time 1.05 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 224108 kb
Host smart-612b706f-36a9-48d9-8b7d-698ec2833dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109838473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1109838473
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3179974496
Short name T591
Test name
Test status
Simulation time 40687279 ps
CPU time 0.98 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 207072 kb
Host smart-fa880df0-c438-47b8-b6cf-6dea2db3c393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179974496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3179974496
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1039518626
Short name T630
Test name
Test status
Simulation time 35214250 ps
CPU time 0.88 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215144 kb
Host smart-dd7c97ab-1615-4e04-8baa-a1f04ab42c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039518626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1039518626
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.350968416
Short name T393
Test name
Test status
Simulation time 257880360 ps
CPU time 1.92 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215312 kb
Host smart-92e9c674-8844-415e-823a-af2fd02085f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350968416 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.350968416
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1526572063
Short name T482
Test name
Test status
Simulation time 21183490841 ps
CPU time 359.48 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:36:10 PM PDT 24
Peak memory 216548 kb
Host smart-54722a89-1a37-4553-b08c-9c07ede9923a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526572063 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1526572063
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2207784825
Short name T37
Test name
Test status
Simulation time 26680767 ps
CPU time 0.93 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 222936 kb
Host smart-a4a97534-6e57-4a06-862c-efc5b671aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207784825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2207784825
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2647688769
Short name T750
Test name
Test status
Simulation time 69002982 ps
CPU time 1.7 seconds
Started Mar 28 01:31:42 PM PDT 24
Finished Mar 28 01:31:44 PM PDT 24
Peak memory 217892 kb
Host smart-0e7fe5f6-5f50-4ff8-bc6a-cafaea27992e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647688769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2647688769
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3816967115
Short name T155
Test name
Test status
Simulation time 24321906 ps
CPU time 0.9 seconds
Started Mar 28 01:31:41 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 217808 kb
Host smart-1517b402-a9bd-4fe9-9cd8-d72ae2be8a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816967115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3816967115
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1965622452
Short name T363
Test name
Test status
Simulation time 43649020 ps
CPU time 1.74 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 217948 kb
Host smart-20d2bb9e-6dc9-4208-bf2a-75d5c235c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965622452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1965622452
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.60075892
Short name T549
Test name
Test status
Simulation time 30741551 ps
CPU time 1.01 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 229792 kb
Host smart-f6f1f6db-2628-478f-9761-c178be33495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60075892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.60075892
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1619011892
Short name T677
Test name
Test status
Simulation time 51161734 ps
CPU time 1.61 seconds
Started Mar 28 01:31:41 PM PDT 24
Finished Mar 28 01:31:43 PM PDT 24
Peak memory 218112 kb
Host smart-5ab4d9db-5684-4dd2-8bd3-645ab67ed622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619011892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1619011892
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.656411450
Short name T51
Test name
Test status
Simulation time 30201327 ps
CPU time 1.27 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 220112 kb
Host smart-1e73cf68-43e1-4074-b6ee-bbe61c43952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656411450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.656411450
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.971449836
Short name T797
Test name
Test status
Simulation time 57597239 ps
CPU time 1.17 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 216648 kb
Host smart-f1b71778-7932-49ac-bb19-f6fc2158cc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971449836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.971449836
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4000271760
Short name T101
Test name
Test status
Simulation time 27348693 ps
CPU time 1.11 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 232556 kb
Host smart-90f7f087-ed27-4724-8329-0d4322bbf513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000271760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4000271760
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.185874447
Short name T691
Test name
Test status
Simulation time 53437845 ps
CPU time 1.68 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 216724 kb
Host smart-c1e12537-e1d6-4db2-bed2-368678a2538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185874447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.185874447
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.911546871
Short name T8
Test name
Test status
Simulation time 32012061 ps
CPU time 0.9 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 218236 kb
Host smart-3ef76d93-969f-4c68-b0d3-3c56b7a36eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911546871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.911546871
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2011335937
Short name T675
Test name
Test status
Simulation time 139145863 ps
CPU time 1.36 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218400 kb
Host smart-463bb420-3436-4497-843a-011e8a787f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011335937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2011335937
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3820663999
Short name T798
Test name
Test status
Simulation time 25889920 ps
CPU time 1.01 seconds
Started Mar 28 01:31:41 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 216832 kb
Host smart-3276a90b-cbbd-4db6-a74c-b80ffe1161c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820663999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3820663999
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3671143620
Short name T521
Test name
Test status
Simulation time 95039105 ps
CPU time 1.23 seconds
Started Mar 28 01:31:42 PM PDT 24
Finished Mar 28 01:31:43 PM PDT 24
Peak memory 216588 kb
Host smart-3e3b5a33-047c-471c-a861-1c63252c6f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671143620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3671143620
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1271579761
Short name T68
Test name
Test status
Simulation time 25937031 ps
CPU time 1.01 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 219084 kb
Host smart-0ef20ad7-8afd-4a72-a23c-cc304386c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271579761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1271579761
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.1959217846
Short name T661
Test name
Test status
Simulation time 25549329 ps
CPU time 1.1 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 229728 kb
Host smart-aa2032cf-e2a1-4038-8f3b-28b8d38977fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959217846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1959217846
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.4159394931
Short name T792
Test name
Test status
Simulation time 38283788 ps
CPU time 1.42 seconds
Started Mar 28 01:31:42 PM PDT 24
Finished Mar 28 01:31:43 PM PDT 24
Peak memory 217632 kb
Host smart-50db2c97-72ee-45ba-8a5c-821a29b20fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159394931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4159394931
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2613298425
Short name T567
Test name
Test status
Simulation time 18942564 ps
CPU time 1.03 seconds
Started Mar 28 01:31:40 PM PDT 24
Finished Mar 28 01:31:41 PM PDT 24
Peak memory 218176 kb
Host smart-19c88f42-9955-4d4b-a741-85d86b4ca22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613298425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2613298425
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2673199533
Short name T132
Test name
Test status
Simulation time 83265280 ps
CPU time 1.49 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218440 kb
Host smart-77488ba0-0d16-4709-a321-4b8cedc0509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673199533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2673199533
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2015234915
Short name T140
Test name
Test status
Simulation time 30112926 ps
CPU time 1.19 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215656 kb
Host smart-870c669b-59e9-4c09-831b-c41abe3f7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015234915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2015234915
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1733614804
Short name T346
Test name
Test status
Simulation time 219596962 ps
CPU time 1.02 seconds
Started Mar 28 01:30:20 PM PDT 24
Finished Mar 28 01:30:21 PM PDT 24
Peak memory 206756 kb
Host smart-f9c20b7c-fe01-45d7-894a-5ca346276df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733614804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1733614804
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2034583847
Short name T180
Test name
Test status
Simulation time 12818274 ps
CPU time 0.9 seconds
Started Mar 28 01:30:15 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 215560 kb
Host smart-64bbfb32-52b1-4d4f-b93e-d1f38b218778
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034583847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2034583847
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.608091644
Short name T450
Test name
Test status
Simulation time 26270916 ps
CPU time 0.95 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 218208 kb
Host smart-a191ec42-2cca-40ed-9e99-200e57c4c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608091644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.608091644
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1500666924
Short name T428
Test name
Test status
Simulation time 36414691 ps
CPU time 1.36 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 216636 kb
Host smart-defc6368-86b1-4e1c-b932-3b847dc1c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500666924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1500666924
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1545609214
Short name T126
Test name
Test status
Simulation time 20365288 ps
CPU time 1.04 seconds
Started Mar 28 01:30:13 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215712 kb
Host smart-b0934261-6a3a-40ba-8adc-1c5f3476c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545609214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1545609214
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3840520330
Short name T123
Test name
Test status
Simulation time 43736907 ps
CPU time 0.9 seconds
Started Mar 28 01:30:11 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 207124 kb
Host smart-a3e19eef-6106-40ac-9494-41156368707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840520330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3840520330
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.651161741
Short name T554
Test name
Test status
Simulation time 26582781 ps
CPU time 0.94 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 215308 kb
Host smart-996ba8de-d669-40bf-a6f3-a21d44251852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651161741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.651161741
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4071854001
Short name T740
Test name
Test status
Simulation time 1142884082 ps
CPU time 5.85 seconds
Started Mar 28 01:30:12 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 216504 kb
Host smart-77cbf954-c21c-4d82-830d-13d65b4c7918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071854001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4071854001
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3243550738
Short name T582
Test name
Test status
Simulation time 264451836274 ps
CPU time 1767.94 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:59:42 PM PDT 24
Peak memory 227056 kb
Host smart-172b16f1-4d77-4f13-9c65-ea283def2303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243550738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3243550738
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2993971088
Short name T87
Test name
Test status
Simulation time 22979814 ps
CPU time 0.92 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218000 kb
Host smart-a91694b0-69cb-4808-852e-0071a030cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993971088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2993971088
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1649436227
Short name T504
Test name
Test status
Simulation time 111518486 ps
CPU time 1.62 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:48 PM PDT 24
Peak memory 219464 kb
Host smart-2296677d-9870-4d9b-af79-08d3b0e39698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649436227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1649436227
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1548180004
Short name T163
Test name
Test status
Simulation time 31212378 ps
CPU time 0.88 seconds
Started Mar 28 01:31:41 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 217900 kb
Host smart-c5424a79-8f92-4de0-903f-029c462d082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548180004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1548180004
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3118784130
Short name T671
Test name
Test status
Simulation time 95737530 ps
CPU time 1.53 seconds
Started Mar 28 01:31:40 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 218028 kb
Host smart-f4339b91-ef6f-447a-982c-d1a05d11a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118784130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3118784130
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3613868606
Short name T167
Test name
Test status
Simulation time 102858091 ps
CPU time 1.18 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 219312 kb
Host smart-a75d9fc3-bda1-49cb-a1ab-40d3808adaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613868606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3613868606
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4070401223
Short name T539
Test name
Test status
Simulation time 54972026 ps
CPU time 1.26 seconds
Started Mar 28 01:31:42 PM PDT 24
Finished Mar 28 01:31:43 PM PDT 24
Peak memory 216692 kb
Host smart-945b52e5-46a4-47f5-aa69-6152bd4a60a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070401223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4070401223
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.769493128
Short name T600
Test name
Test status
Simulation time 20164715 ps
CPU time 1.29 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 232688 kb
Host smart-a147e2c1-af76-4c85-b3b9-6dfe47c71d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769493128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.769493128
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1146590083
Short name T783
Test name
Test status
Simulation time 42794586 ps
CPU time 1.48 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 217916 kb
Host smart-75b79302-e292-47a9-95d5-ea1f0cdabc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146590083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1146590083
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4279332254
Short name T426
Test name
Test status
Simulation time 34706428 ps
CPU time 1.05 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:44 PM PDT 24
Peak memory 219368 kb
Host smart-f01b5df2-dc54-452e-8be2-cbe67e79f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279332254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4279332254
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2017770316
Short name T134
Test name
Test status
Simulation time 88430089 ps
CPU time 1.26 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218216 kb
Host smart-80d6b044-a62f-448f-ae78-b2e781310e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017770316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2017770316
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1827572731
Short name T507
Test name
Test status
Simulation time 44009268 ps
CPU time 0.96 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 231148 kb
Host smart-3cb6454f-27f1-4222-afc3-165ced4fe8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827572731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1827572731
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.55382921
Short name T376
Test name
Test status
Simulation time 102893712 ps
CPU time 1.29 seconds
Started Mar 28 01:31:41 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 216704 kb
Host smart-86f4955d-e20c-4e26-8fd7-d556d0ef9ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55382921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.55382921
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3669133724
Short name T399
Test name
Test status
Simulation time 25002136 ps
CPU time 1.2 seconds
Started Mar 28 01:31:44 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 218160 kb
Host smart-edfaaa21-8bd4-44b9-a11b-3a4be4c37863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669133724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3669133724
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1196366474
Short name T477
Test name
Test status
Simulation time 60302607 ps
CPU time 1.47 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 217976 kb
Host smart-075adb20-379e-4f80-92ff-b96844053c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196366474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1196366474
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2909040682
Short name T774
Test name
Test status
Simulation time 25716270 ps
CPU time 1.22 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 220112 kb
Host smart-e11dcb94-3585-4e97-b7e4-3243f50ddcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909040682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2909040682
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.156795859
Short name T367
Test name
Test status
Simulation time 70008750 ps
CPU time 1.2 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218488 kb
Host smart-fe3a8c1b-9879-4073-ac79-642f64106676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156795859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.156795859
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2386774269
Short name T805
Test name
Test status
Simulation time 60172640 ps
CPU time 1.13 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 219156 kb
Host smart-1c58dc88-de2d-4f79-b2cd-5501e8f3aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386774269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2386774269
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1308719295
Short name T826
Test name
Test status
Simulation time 92213898 ps
CPU time 1.44 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 218088 kb
Host smart-8e615a59-bece-4cec-94f4-1d3f7c0f7238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308719295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1308719295
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1613665174
Short name T353
Test name
Test status
Simulation time 20053391 ps
CPU time 1.14 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 218196 kb
Host smart-f2592ae0-8cfa-4ffd-b1ca-15d7615f8505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613665174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1613665174
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.704493914
Short name T365
Test name
Test status
Simulation time 77375352 ps
CPU time 1.22 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 218924 kb
Host smart-1ba6e1ef-2a7e-4444-a765-23dc095a3e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704493914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.704493914
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3639595491
Short name T249
Test name
Test status
Simulation time 26086281 ps
CPU time 1.2 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 215608 kb
Host smart-cd00769b-c6a4-420c-a709-d8371c3de2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639595491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3639595491
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.4016880737
Short name T623
Test name
Test status
Simulation time 20561585 ps
CPU time 0.93 seconds
Started Mar 28 01:30:20 PM PDT 24
Finished Mar 28 01:30:21 PM PDT 24
Peak memory 206020 kb
Host smart-28c684bf-a829-4805-9a28-5eaec2db4e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016880737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.4016880737
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.631246581
Short name T837
Test name
Test status
Simulation time 28341767 ps
CPU time 1.13 seconds
Started Mar 28 01:30:16 PM PDT 24
Finished Mar 28 01:30:17 PM PDT 24
Peak memory 217816 kb
Host smart-3dbfd044-c50a-4f3a-a211-d0d1d0408bff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631246581 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.631246581
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2388545926
Short name T515
Test name
Test status
Simulation time 27025835 ps
CPU time 0.94 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 215564 kb
Host smart-49abd7f0-b30d-429f-9bae-ede644881346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388545926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2388545926
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.646381985
Short name T420
Test name
Test status
Simulation time 54590769 ps
CPU time 1.12 seconds
Started Mar 28 01:30:20 PM PDT 24
Finished Mar 28 01:30:21 PM PDT 24
Peak memory 218052 kb
Host smart-2aaaabab-7d75-4ae6-95b9-d5059514c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646381985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.646381985
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2272586622
Short name T639
Test name
Test status
Simulation time 24393657 ps
CPU time 1 seconds
Started Mar 28 01:30:20 PM PDT 24
Finished Mar 28 01:30:21 PM PDT 24
Peak memory 215552 kb
Host smart-16d9b29d-1030-4232-b1dd-36c847c30df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272586622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2272586622
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1924866356
Short name T242
Test name
Test status
Simulation time 52164275 ps
CPU time 0.92 seconds
Started Mar 28 01:30:16 PM PDT 24
Finished Mar 28 01:30:17 PM PDT 24
Peak memory 207096 kb
Host smart-64545a7b-81a9-43f2-b5ab-97fc378467bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924866356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1924866356
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2064476914
Short name T625
Test name
Test status
Simulation time 29815508 ps
CPU time 0.92 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 215292 kb
Host smart-45395f2d-95cb-4cfc-a2d1-0de9183332c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064476914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2064476914
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3092713071
Short name T757
Test name
Test status
Simulation time 87327789 ps
CPU time 1.31 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 216564 kb
Host smart-5c439333-3abe-4c54-89aa-fc09373f9c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092713071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3092713071
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1552616099
Short name T406
Test name
Test status
Simulation time 71993277350 ps
CPU time 438.83 seconds
Started Mar 28 01:30:15 PM PDT 24
Finished Mar 28 01:37:34 PM PDT 24
Peak memory 218364 kb
Host smart-5587ff25-94ce-4fcc-a831-c0da663ca898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552616099 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1552616099
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2409700345
Short name T67
Test name
Test status
Simulation time 151972041 ps
CPU time 1.21 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:44 PM PDT 24
Peak memory 229828 kb
Host smart-2a9d1bb4-65cd-4df4-a6af-4b8889eabca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409700345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2409700345
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4060843858
Short name T291
Test name
Test status
Simulation time 32890284 ps
CPU time 1.28 seconds
Started Mar 28 01:31:44 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 216544 kb
Host smart-9a01478f-0819-40c5-8e32-006361ae8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060843858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4060843858
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3907558386
Short name T56
Test name
Test status
Simulation time 26885100 ps
CPU time 1.06 seconds
Started Mar 28 01:31:44 PM PDT 24
Finished Mar 28 01:31:45 PM PDT 24
Peak memory 219092 kb
Host smart-2ed5fa0e-7c66-499c-84ae-ac03a45b73d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907558386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3907558386
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.157077245
Short name T556
Test name
Test status
Simulation time 83648134 ps
CPU time 1.25 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 217032 kb
Host smart-a84d3bdc-6329-4f68-8933-a33f309463e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157077245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.157077245
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2831943403
Short name T96
Test name
Test status
Simulation time 29050549 ps
CPU time 0.93 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 222908 kb
Host smart-8dce29fd-ef0c-4e3a-944b-33ea9e71e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831943403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2831943403
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1660044330
Short name T438
Test name
Test status
Simulation time 28102668 ps
CPU time 1.3 seconds
Started Mar 28 01:31:42 PM PDT 24
Finished Mar 28 01:31:43 PM PDT 24
Peak memory 216672 kb
Host smart-8576d145-2bb1-4cd3-a298-c4fdddc7208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660044330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1660044330
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1047768438
Short name T801
Test name
Test status
Simulation time 37590173 ps
CPU time 0.91 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 219292 kb
Host smart-9676a9f8-f992-45fd-aaef-5eb1148e36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047768438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1047768438
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3578522394
Short name T2
Test name
Test status
Simulation time 55897766 ps
CPU time 2.18 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 217984 kb
Host smart-bef31e5f-93df-4ba3-b80e-6af304abd069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578522394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3578522394
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1081677183
Short name T402
Test name
Test status
Simulation time 30613626 ps
CPU time 1.04 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 218024 kb
Host smart-058474cc-7c59-491c-8368-e046d6fe8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081677183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1081677183
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1231937537
Short name T633
Test name
Test status
Simulation time 423831166 ps
CPU time 4.85 seconds
Started Mar 28 01:31:43 PM PDT 24
Finished Mar 28 01:31:48 PM PDT 24
Peak memory 219440 kb
Host smart-45d6f915-7032-4cf9-8ba2-6556a22dbbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231937537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1231937537
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3866557460
Short name T738
Test name
Test status
Simulation time 49614164 ps
CPU time 0.82 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:47 PM PDT 24
Peak memory 217608 kb
Host smart-7f0cc97e-ca9b-4a59-816d-809c8c30c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866557460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3866557460
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1695523547
Short name T386
Test name
Test status
Simulation time 125676081 ps
CPU time 1.1 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:48 PM PDT 24
Peak memory 216664 kb
Host smart-4375afd0-d62d-4377-9bf9-3602caf76693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695523547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1695523547
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3526269917
Short name T62
Test name
Test status
Simulation time 27708727 ps
CPU time 0.96 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 219364 kb
Host smart-9179c2de-bb76-4700-aaf8-8382f9c8704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526269917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3526269917
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2360672073
Short name T670
Test name
Test status
Simulation time 204517529 ps
CPU time 1.53 seconds
Started Mar 28 01:31:46 PM PDT 24
Finished Mar 28 01:31:48 PM PDT 24
Peak memory 218204 kb
Host smart-b6555698-819f-4a5a-90d0-ed679ba0f9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360672073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2360672073
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3070599967
Short name T69
Test name
Test status
Simulation time 59924621 ps
CPU time 1.2 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 229468 kb
Host smart-89934304-0114-4dad-8cc2-eabcede4eaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070599967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3070599967
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2351402824
Short name T284
Test name
Test status
Simulation time 34662958 ps
CPU time 1.08 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 219304 kb
Host smart-f74b6ea1-5fbc-491a-abc9-c17841e25bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351402824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2351402824
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1174889279
Short name T385
Test name
Test status
Simulation time 33161257 ps
CPU time 0.89 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:51 PM PDT 24
Peak memory 217972 kb
Host smart-b105993e-5285-4dcc-abe8-16bafc73ca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174889279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1174889279
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1360506405
Short name T448
Test name
Test status
Simulation time 128980548 ps
CPU time 3.03 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:53 PM PDT 24
Peak memory 216736 kb
Host smart-030f8434-4e26-42fe-b77b-caa373cc2b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360506405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1360506405
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.587109554
Short name T97
Test name
Test status
Simulation time 28392493 ps
CPU time 0.85 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 217620 kb
Host smart-1f6eb337-96a1-4d2d-9e27-37d266545ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587109554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.587109554
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4020765612
Short name T525
Test name
Test status
Simulation time 80485161 ps
CPU time 1.31 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 219552 kb
Host smart-10c4464f-d9f3-415e-97b3-f552212617b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020765612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4020765612
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1141255923
Short name T687
Test name
Test status
Simulation time 25470906 ps
CPU time 1.16 seconds
Started Mar 28 01:30:17 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 215560 kb
Host smart-b6ccf402-ae63-47b2-bfc7-2eef7cec9dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141255923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1141255923
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1389854646
Short name T669
Test name
Test status
Simulation time 60606579 ps
CPU time 0.88 seconds
Started Mar 28 01:30:17 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 206272 kb
Host smart-c998cb52-b417-4433-96a9-860b4f393931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389854646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1389854646
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1390074275
Short name T93
Test name
Test status
Simulation time 27785707 ps
CPU time 0.84 seconds
Started Mar 28 01:30:21 PM PDT 24
Finished Mar 28 01:30:22 PM PDT 24
Peak memory 215820 kb
Host smart-ae15f43c-17ca-43f4-812c-20a236f7d48f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390074275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1390074275
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2862828041
Short name T483
Test name
Test status
Simulation time 208554760 ps
CPU time 1.16 seconds
Started Mar 28 01:30:14 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 216540 kb
Host smart-fb06b37a-0be0-463b-b2cf-fe042bad8a61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862828041 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2862828041
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1248758121
Short name T78
Test name
Test status
Simulation time 39223460 ps
CPU time 0.99 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 232312 kb
Host smart-a3f378b6-15c8-4986-929c-ee80655b91c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248758121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1248758121
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.717792849
Short name T807
Test name
Test status
Simulation time 197643475 ps
CPU time 2.62 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:21 PM PDT 24
Peak memory 218176 kb
Host smart-7b2f83bb-9bea-489a-a9df-ddf189b0ad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717792849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.717792849
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.272778463
Short name T785
Test name
Test status
Simulation time 32088525 ps
CPU time 0.89 seconds
Started Mar 28 01:30:17 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 215412 kb
Host smart-5976d2f8-4a99-4a55-92ec-3592626fbdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272778463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.272778463
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2864695337
Short name T251
Test name
Test status
Simulation time 69599534 ps
CPU time 0.87 seconds
Started Mar 28 01:30:15 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 206604 kb
Host smart-ae1eb070-3f67-4de3-b8fb-7e32bdb2a0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864695337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2864695337
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4033332464
Short name T292
Test name
Test status
Simulation time 78266505 ps
CPU time 0.89 seconds
Started Mar 28 01:30:15 PM PDT 24
Finished Mar 28 01:30:16 PM PDT 24
Peak memory 214728 kb
Host smart-30392925-5b7c-4972-adca-5f2f1ee93eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033332464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4033332464
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2285989343
Short name T620
Test name
Test status
Simulation time 110673381 ps
CPU time 2.64 seconds
Started Mar 28 01:30:18 PM PDT 24
Finished Mar 28 01:30:21 PM PDT 24
Peak memory 216520 kb
Host smart-c897b7b0-cbc0-4568-bf73-71c488715ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285989343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2285989343
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.548044932
Short name T347
Test name
Test status
Simulation time 656280615975 ps
CPU time 1745.82 seconds
Started Mar 28 01:30:23 PM PDT 24
Finished Mar 28 01:59:29 PM PDT 24
Peak memory 222808 kb
Host smart-75e5e678-0603-4171-8b60-f3b95a227d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548044932 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.548044932
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.4020273818
Short name T742
Test name
Test status
Simulation time 30957215 ps
CPU time 0.92 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 217904 kb
Host smart-df5badbd-b26f-4cf2-aef1-a4160b0991f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020273818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4020273818
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2233304706
Short name T375
Test name
Test status
Simulation time 232966623 ps
CPU time 1.23 seconds
Started Mar 28 01:31:51 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 216964 kb
Host smart-08252fda-3b28-4a08-a9f9-4cdcf408382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233304706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2233304706
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2641378529
Short name T495
Test name
Test status
Simulation time 20522500 ps
CPU time 1.05 seconds
Started Mar 28 01:31:50 PM PDT 24
Finished Mar 28 01:31:52 PM PDT 24
Peak memory 217848 kb
Host smart-1a9ecc6b-9d62-4558-a533-190483a26462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641378529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2641378529
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3084400488
Short name T526
Test name
Test status
Simulation time 97244486 ps
CPU time 1.05 seconds
Started Mar 28 01:31:49 PM PDT 24
Finished Mar 28 01:31:50 PM PDT 24
Peak memory 216736 kb
Host smart-5f66992a-0365-4c9f-a654-6afc50793aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084400488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3084400488
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3505525153
Short name T527
Test name
Test status
Simulation time 26760393 ps
CPU time 1.29 seconds
Started Mar 28 01:31:47 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 231324 kb
Host smart-07ba68a1-e0bc-434f-956a-e5ac6ed87cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505525153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3505525153
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3807580806
Short name T379
Test name
Test status
Simulation time 67186012 ps
CPU time 1.11 seconds
Started Mar 28 01:31:48 PM PDT 24
Finished Mar 28 01:31:49 PM PDT 24
Peak memory 218960 kb
Host smart-54f2c6ab-41e3-45d7-af7a-815a4335eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807580806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3807580806
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2287224615
Short name T77
Test name
Test status
Simulation time 73422266 ps
CPU time 1.16 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 233372 kb
Host smart-f2c88775-5776-411e-a07d-316feff4a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287224615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2287224615
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1952201755
Short name T433
Test name
Test status
Simulation time 38421660 ps
CPU time 1.71 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 216656 kb
Host smart-410c98ab-47b8-48f3-872e-aa9901bba42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952201755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1952201755
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1911414703
Short name T601
Test name
Test status
Simulation time 31341052 ps
CPU time 0.88 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 217624 kb
Host smart-171fd317-5726-4120-bd3a-f3a79de291b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911414703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1911414703
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1933231124
Short name T518
Test name
Test status
Simulation time 75083376 ps
CPU time 1.48 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 217796 kb
Host smart-68842328-d66e-4339-b7ab-773cb8083183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933231124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1933231124
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3268544181
Short name T419
Test name
Test status
Simulation time 127713776 ps
CPU time 0.96 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 218152 kb
Host smart-2bd33bd8-d8f9-4dd8-9c4c-75642d532cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268544181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3268544181
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1231964188
Short name T638
Test name
Test status
Simulation time 76325229 ps
CPU time 1.29 seconds
Started Mar 28 01:31:58 PM PDT 24
Finished Mar 28 01:31:59 PM PDT 24
Peak memory 216572 kb
Host smart-c3569af7-8381-45b1-bc3b-ffb4b52d6b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231964188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1231964188
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1443814120
Short name T584
Test name
Test status
Simulation time 29590586 ps
CPU time 1.25 seconds
Started Mar 28 01:32:02 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 219216 kb
Host smart-0e70495e-786f-4968-96c5-74425065f2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443814120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1443814120
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3711190021
Short name T594
Test name
Test status
Simulation time 145280703 ps
CPU time 3.35 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:08 PM PDT 24
Peak memory 219436 kb
Host smart-13e99755-9ee6-475c-9f20-17740d8be29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711190021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3711190021
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1235905762
Short name T76
Test name
Test status
Simulation time 28745053 ps
CPU time 1.02 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 232352 kb
Host smart-1343410c-bbda-45d1-bc6a-5d5230d6d76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235905762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1235905762
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2406014506
Short name T734
Test name
Test status
Simulation time 31103940 ps
CPU time 1.27 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:02 PM PDT 24
Peak memory 219216 kb
Host smart-4b219b96-885f-4556-a22f-a9104f7f1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406014506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2406014506
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2930500694
Short name T58
Test name
Test status
Simulation time 21036042 ps
CPU time 1.2 seconds
Started Mar 28 01:32:03 PM PDT 24
Finished Mar 28 01:32:06 PM PDT 24
Peak memory 219316 kb
Host smart-d01df447-0caa-43b9-aacb-c7a0e2b67e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930500694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2930500694
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4122580198
Short name T285
Test name
Test status
Simulation time 84986445 ps
CPU time 2.88 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:04 PM PDT 24
Peak memory 218144 kb
Host smart-cf34aa57-c847-45bc-8df8-c41e5a36b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122580198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4122580198
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.4159941841
Short name T816
Test name
Test status
Simulation time 30654147 ps
CPU time 0.93 seconds
Started Mar 28 01:32:01 PM PDT 24
Finished Mar 28 01:32:02 PM PDT 24
Peak memory 217968 kb
Host smart-368475c7-cbcf-413e-8cc6-5b9bc483c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159941841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.4159941841
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1931332581
Short name T436
Test name
Test status
Simulation time 41012460 ps
CPU time 1.14 seconds
Started Mar 28 01:31:59 PM PDT 24
Finished Mar 28 01:32:01 PM PDT 24
Peak memory 217004 kb
Host smart-fa96067f-dc25-4e6b-b92d-0b2e4bfd8534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931332581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1931332581
Directory /workspace/99.edn_genbits/latest
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