Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.75 98.27 93.64 96.84 80.92 96.87 96.58 93.15


Total test records in report: 965
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T787 /workspace/coverage/default/207.edn_genbits.1133000974 Mar 31 01:13:11 PM PDT 24 Mar 31 01:13:13 PM PDT 24 39846635 ps
T788 /workspace/coverage/default/30.edn_alert.2499322347 Mar 31 01:11:37 PM PDT 24 Mar 31 01:11:39 PM PDT 24 43661746 ps
T789 /workspace/coverage/default/46.edn_smoke.3710867915 Mar 31 01:12:12 PM PDT 24 Mar 31 01:12:13 PM PDT 24 108135783 ps
T790 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3813155527 Mar 31 01:10:55 PM PDT 24 Mar 31 01:50:28 PM PDT 24 106124672915 ps
T791 /workspace/coverage/default/17.edn_stress_all.4082304473 Mar 31 01:11:15 PM PDT 24 Mar 31 01:11:17 PM PDT 24 118829777 ps
T792 /workspace/coverage/default/239.edn_genbits.2726948748 Mar 31 01:13:06 PM PDT 24 Mar 31 01:13:08 PM PDT 24 26167920 ps
T793 /workspace/coverage/default/23.edn_smoke.735041792 Mar 31 01:11:24 PM PDT 24 Mar 31 01:11:25 PM PDT 24 16112378 ps
T794 /workspace/coverage/default/14.edn_disable.1732232501 Mar 31 01:11:05 PM PDT 24 Mar 31 01:11:06 PM PDT 24 15498252 ps
T795 /workspace/coverage/default/18.edn_genbits.2241244711 Mar 31 01:11:13 PM PDT 24 Mar 31 01:11:15 PM PDT 24 114522845 ps
T796 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2363180378 Mar 31 01:11:53 PM PDT 24 Mar 31 01:24:02 PM PDT 24 122754935823 ps
T797 /workspace/coverage/default/298.edn_genbits.478909277 Mar 31 01:13:10 PM PDT 24 Mar 31 01:13:12 PM PDT 24 185928703 ps
T798 /workspace/coverage/default/131.edn_genbits.2237047552 Mar 31 01:12:57 PM PDT 24 Mar 31 01:12:58 PM PDT 24 86917211 ps
T799 /workspace/coverage/default/268.edn_genbits.1848127913 Mar 31 01:13:15 PM PDT 24 Mar 31 01:13:16 PM PDT 24 71839725 ps
T800 /workspace/coverage/default/10.edn_disable_auto_req_mode.401193548 Mar 31 01:10:49 PM PDT 24 Mar 31 01:10:51 PM PDT 24 30439256 ps
T801 /workspace/coverage/default/16.edn_intr.2842457200 Mar 31 01:11:07 PM PDT 24 Mar 31 01:11:09 PM PDT 24 30754461 ps
T802 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3464620396 Mar 31 01:11:20 PM PDT 24 Mar 31 01:28:02 PM PDT 24 173314047524 ps
T803 /workspace/coverage/default/1.edn_regwen.3091109842 Mar 31 01:10:11 PM PDT 24 Mar 31 01:10:12 PM PDT 24 56204499 ps
T804 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.221257410 Mar 31 01:11:48 PM PDT 24 Mar 31 01:30:44 PM PDT 24 155177947962 ps
T805 /workspace/coverage/default/106.edn_genbits.3861433565 Mar 31 01:12:55 PM PDT 24 Mar 31 01:12:56 PM PDT 24 47566562 ps
T806 /workspace/coverage/default/266.edn_genbits.1041743843 Mar 31 01:13:09 PM PDT 24 Mar 31 01:13:11 PM PDT 24 73087091 ps
T807 /workspace/coverage/default/59.edn_err.2298343131 Mar 31 01:12:27 PM PDT 24 Mar 31 01:12:29 PM PDT 24 19471236 ps
T808 /workspace/coverage/default/45.edn_genbits.371834359 Mar 31 01:12:10 PM PDT 24 Mar 31 01:12:11 PM PDT 24 118950630 ps
T809 /workspace/coverage/default/24.edn_alert_test.3615396444 Mar 31 01:11:29 PM PDT 24 Mar 31 01:11:30 PM PDT 24 52223315 ps
T810 /workspace/coverage/default/238.edn_genbits.3492914366 Mar 31 01:13:14 PM PDT 24 Mar 31 01:13:16 PM PDT 24 51971521 ps
T811 /workspace/coverage/default/41.edn_alert.376570595 Mar 31 01:12:01 PM PDT 24 Mar 31 01:12:03 PM PDT 24 52103558 ps
T812 /workspace/coverage/default/203.edn_genbits.1987187622 Mar 31 01:13:03 PM PDT 24 Mar 31 01:13:05 PM PDT 24 67804264 ps
T813 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.713806366 Mar 31 01:11:34 PM PDT 24 Mar 31 01:32:38 PM PDT 24 51451477406 ps
T814 /workspace/coverage/default/18.edn_stress_all.1883862340 Mar 31 01:11:11 PM PDT 24 Mar 31 01:11:13 PM PDT 24 274918135 ps
T815 /workspace/coverage/default/24.edn_disable_auto_req_mode.2326595536 Mar 31 01:11:30 PM PDT 24 Mar 31 01:11:31 PM PDT 24 268965329 ps
T161 /workspace/coverage/default/26.edn_disable.1047972601 Mar 31 01:11:35 PM PDT 24 Mar 31 01:11:36 PM PDT 24 31432250 ps
T816 /workspace/coverage/default/29.edn_intr.778823732 Mar 31 01:11:35 PM PDT 24 Mar 31 01:11:36 PM PDT 24 40070553 ps
T817 /workspace/coverage/default/9.edn_err.3967721970 Mar 31 01:10:51 PM PDT 24 Mar 31 01:10:52 PM PDT 24 42122345 ps
T54 /workspace/coverage/default/1.edn_sec_cm.344810044 Mar 31 01:10:17 PM PDT 24 Mar 31 01:10:22 PM PDT 24 2497403350 ps
T818 /workspace/coverage/default/36.edn_smoke.2136667385 Mar 31 01:12:02 PM PDT 24 Mar 31 01:12:03 PM PDT 24 24725771 ps
T819 /workspace/coverage/default/22.edn_stress_all.2207612189 Mar 31 01:11:22 PM PDT 24 Mar 31 01:11:24 PM PDT 24 198731040 ps
T820 /workspace/coverage/default/32.edn_genbits.1295422884 Mar 31 01:11:48 PM PDT 24 Mar 31 01:11:50 PM PDT 24 96004349 ps
T821 /workspace/coverage/default/39.edn_disable.3760325346 Mar 31 01:11:56 PM PDT 24 Mar 31 01:11:57 PM PDT 24 21173072 ps
T822 /workspace/coverage/default/103.edn_genbits.3376908779 Mar 31 01:13:01 PM PDT 24 Mar 31 01:13:03 PM PDT 24 165193249 ps
T823 /workspace/coverage/default/170.edn_genbits.4066615169 Mar 31 01:12:59 PM PDT 24 Mar 31 01:13:00 PM PDT 24 100844616 ps
T824 /workspace/coverage/default/227.edn_genbits.415546755 Mar 31 01:13:08 PM PDT 24 Mar 31 01:13:09 PM PDT 24 89991682 ps
T825 /workspace/coverage/default/11.edn_alert_test.552676714 Mar 31 01:10:57 PM PDT 24 Mar 31 01:10:59 PM PDT 24 43730527 ps
T826 /workspace/coverage/default/145.edn_genbits.1804886669 Mar 31 01:12:59 PM PDT 24 Mar 31 01:13:00 PM PDT 24 43870648 ps
T827 /workspace/coverage/default/15.edn_genbits.1947270276 Mar 31 01:11:05 PM PDT 24 Mar 31 01:11:06 PM PDT 24 51364543 ps
T828 /workspace/coverage/default/102.edn_genbits.2487074094 Mar 31 01:12:58 PM PDT 24 Mar 31 01:13:00 PM PDT 24 74382493 ps
T829 /workspace/coverage/default/31.edn_genbits.361524132 Mar 31 01:11:47 PM PDT 24 Mar 31 01:11:48 PM PDT 24 91765168 ps
T830 /workspace/coverage/default/247.edn_genbits.1633213283 Mar 31 01:13:06 PM PDT 24 Mar 31 01:13:07 PM PDT 24 38754017 ps
T831 /workspace/coverage/default/37.edn_disable_auto_req_mode.1985175945 Mar 31 01:11:53 PM PDT 24 Mar 31 01:11:55 PM PDT 24 27086001 ps
T832 /workspace/coverage/default/113.edn_genbits.3339954179 Mar 31 01:12:55 PM PDT 24 Mar 31 01:12:58 PM PDT 24 137672523 ps
T833 /workspace/coverage/default/28.edn_intr.827548714 Mar 31 01:11:37 PM PDT 24 Mar 31 01:11:38 PM PDT 24 23166548 ps
T834 /workspace/coverage/default/23.edn_disable.2172798269 Mar 31 01:11:21 PM PDT 24 Mar 31 01:11:22 PM PDT 24 35592020 ps
T225 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2826112428 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:03 PM PDT 24 188821991 ps
T835 /workspace/coverage/cover_reg_top/26.edn_intr_test.2061121465 Mar 31 12:26:38 PM PDT 24 Mar 31 12:26:39 PM PDT 24 14267985 ps
T226 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1597071060 Mar 31 12:26:24 PM PDT 24 Mar 31 12:26:27 PM PDT 24 92655155 ps
T199 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3491166741 Mar 31 12:26:10 PM PDT 24 Mar 31 12:26:11 PM PDT 24 22624985 ps
T200 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3731247450 Mar 31 12:28:24 PM PDT 24 Mar 31 12:28:25 PM PDT 24 61613755 ps
T836 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2939212046 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:06 PM PDT 24 23993106 ps
T837 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.246172452 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:10 PM PDT 24 181915798 ps
T838 /workspace/coverage/cover_reg_top/42.edn_intr_test.217740662 Mar 31 12:28:33 PM PDT 24 Mar 31 12:28:34 PM PDT 24 24837963 ps
T839 /workspace/coverage/cover_reg_top/47.edn_intr_test.1236123407 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:09 PM PDT 24 46966859 ps
T840 /workspace/coverage/cover_reg_top/23.edn_intr_test.3890038866 Mar 31 12:26:09 PM PDT 24 Mar 31 12:26:10 PM PDT 24 78214228 ps
T201 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1763036090 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:08 PM PDT 24 91804502 ps
T202 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1660781444 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 13900540 ps
T227 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2436635931 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:07 PM PDT 24 133136619 ps
T841 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1873285786 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:56 PM PDT 24 209311681 ps
T842 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2417222821 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:52 PM PDT 24 86072844 ps
T237 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.680945862 Mar 31 12:25:58 PM PDT 24 Mar 31 12:26:00 PM PDT 24 162308913 ps
T843 /workspace/coverage/cover_reg_top/0.edn_intr_test.3971720468 Mar 31 12:25:49 PM PDT 24 Mar 31 12:25:50 PM PDT 24 89673167 ps
T844 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1621108246 Mar 31 12:26:09 PM PDT 24 Mar 31 12:26:17 PM PDT 24 486948294 ps
T845 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1335149236 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:04 PM PDT 24 199191741 ps
T203 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3153713126 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:03 PM PDT 24 29400336 ps
T846 /workspace/coverage/cover_reg_top/7.edn_tl_errors.905547564 Mar 31 12:26:19 PM PDT 24 Mar 31 12:26:22 PM PDT 24 79080498 ps
T218 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2724049794 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:01 PM PDT 24 37795389 ps
T847 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1106961260 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:51 PM PDT 24 324997366 ps
T848 /workspace/coverage/cover_reg_top/16.edn_intr_test.624332714 Mar 31 12:26:31 PM PDT 24 Mar 31 12:26:32 PM PDT 24 23836606 ps
T849 /workspace/coverage/cover_reg_top/6.edn_intr_test.285767664 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:10 PM PDT 24 14931379 ps
T850 /workspace/coverage/cover_reg_top/27.edn_intr_test.1602367120 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:09 PM PDT 24 16362805 ps
T204 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1568811647 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:17 PM PDT 24 73380531 ps
T851 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2619539661 Mar 31 12:25:52 PM PDT 24 Mar 31 12:25:56 PM PDT 24 210376802 ps
T852 /workspace/coverage/cover_reg_top/38.edn_intr_test.4208405003 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:07 PM PDT 24 13502489 ps
T205 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4273555902 Mar 31 12:25:54 PM PDT 24 Mar 31 12:25:56 PM PDT 24 70625533 ps
T240 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2490695272 Mar 31 12:26:10 PM PDT 24 Mar 31 12:26:13 PM PDT 24 141183989 ps
T853 /workspace/coverage/cover_reg_top/16.edn_tl_errors.40491601 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:09 PM PDT 24 443844892 ps
T854 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1390927427 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:02 PM PDT 24 135239002 ps
T224 /workspace/coverage/cover_reg_top/17.edn_csr_rw.956648832 Mar 31 12:25:58 PM PDT 24 Mar 31 12:25:59 PM PDT 24 35646008 ps
T855 /workspace/coverage/cover_reg_top/25.edn_intr_test.1256336814 Mar 31 12:26:24 PM PDT 24 Mar 31 12:26:25 PM PDT 24 14772625 ps
T856 /workspace/coverage/cover_reg_top/9.edn_intr_test.2777757824 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:07 PM PDT 24 16559293 ps
T219 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4194091892 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:02 PM PDT 24 123465391 ps
T238 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3284046209 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:11 PM PDT 24 84890458 ps
T857 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3221275550 Mar 31 12:28:53 PM PDT 24 Mar 31 12:29:07 PM PDT 24 390932334 ps
T241 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2393086630 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:09 PM PDT 24 183128509 ps
T858 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3678497393 Mar 31 12:25:56 PM PDT 24 Mar 31 12:25:58 PM PDT 24 283088855 ps
T859 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4139042712 Mar 31 12:25:53 PM PDT 24 Mar 31 12:25:54 PM PDT 24 30561976 ps
T860 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3034446506 Mar 31 12:26:22 PM PDT 24 Mar 31 12:26:25 PM PDT 24 102798378 ps
T861 /workspace/coverage/cover_reg_top/4.edn_intr_test.3185771333 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:07 PM PDT 24 34475454 ps
T220 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.40233471 Mar 31 12:28:25 PM PDT 24 Mar 31 12:28:26 PM PDT 24 33668628 ps
T221 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2691455840 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:06 PM PDT 24 164617076 ps
T222 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2777280936 Mar 31 12:26:11 PM PDT 24 Mar 31 12:26:13 PM PDT 24 37181965 ps
T206 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1759758506 Mar 31 12:25:56 PM PDT 24 Mar 31 12:25:57 PM PDT 24 19075873 ps
T862 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.956956193 Mar 31 12:25:59 PM PDT 24 Mar 31 12:26:00 PM PDT 24 54802195 ps
T207 /workspace/coverage/cover_reg_top/3.edn_csr_rw.680492287 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:05 PM PDT 24 18766180 ps
T863 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1039920301 Mar 31 12:28:27 PM PDT 24 Mar 31 12:28:29 PM PDT 24 38548340 ps
T208 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1403250977 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 28828510 ps
T239 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3395679754 Mar 31 12:26:37 PM PDT 24 Mar 31 12:26:40 PM PDT 24 852422883 ps
T864 /workspace/coverage/cover_reg_top/29.edn_intr_test.352889048 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 38005148 ps
T865 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2051886409 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 30410195 ps
T209 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2235208542 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:17 PM PDT 24 27648034 ps
T866 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3170164897 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:06 PM PDT 24 243429577 ps
T867 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2763072095 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 873194151 ps
T223 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.975508615 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:07 PM PDT 24 30814759 ps
T868 /workspace/coverage/cover_reg_top/40.edn_intr_test.1688531882 Mar 31 12:26:09 PM PDT 24 Mar 31 12:26:10 PM PDT 24 21733205 ps
T869 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3784664959 Mar 31 12:26:13 PM PDT 24 Mar 31 12:26:15 PM PDT 24 213384899 ps
T870 /workspace/coverage/cover_reg_top/22.edn_intr_test.3160139622 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:05 PM PDT 24 40100271 ps
T871 /workspace/coverage/cover_reg_top/19.edn_tl_errors.237412996 Mar 31 12:28:48 PM PDT 24 Mar 31 12:28:50 PM PDT 24 156453891 ps
T872 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4279761046 Mar 31 12:28:48 PM PDT 24 Mar 31 12:28:49 PM PDT 24 135028783 ps
T210 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1626178480 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:06 PM PDT 24 24199571 ps
T873 /workspace/coverage/cover_reg_top/20.edn_intr_test.1370047142 Mar 31 12:26:20 PM PDT 24 Mar 31 12:26:21 PM PDT 24 11245828 ps
T874 /workspace/coverage/cover_reg_top/28.edn_intr_test.2901585646 Mar 31 12:26:31 PM PDT 24 Mar 31 12:26:32 PM PDT 24 25388946 ps
T875 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1204795072 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:09 PM PDT 24 56529389 ps
T876 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2806529327 Mar 31 12:26:11 PM PDT 24 Mar 31 12:26:17 PM PDT 24 165281930 ps
T877 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1342864511 Mar 31 12:28:26 PM PDT 24 Mar 31 12:28:27 PM PDT 24 42791549 ps
T878 /workspace/coverage/cover_reg_top/0.edn_csr_rw.453318086 Mar 31 12:25:56 PM PDT 24 Mar 31 12:25:57 PM PDT 24 30471277 ps
T879 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3828533029 Mar 31 12:26:41 PM PDT 24 Mar 31 12:26:42 PM PDT 24 17468064 ps
T880 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3078160126 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:03 PM PDT 24 144440122 ps
T881 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1587269806 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:12 PM PDT 24 53700081 ps
T882 /workspace/coverage/cover_reg_top/36.edn_intr_test.1046377596 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:03 PM PDT 24 34849283 ps
T883 /workspace/coverage/cover_reg_top/2.edn_intr_test.4009549371 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:07 PM PDT 24 61348049 ps
T884 /workspace/coverage/cover_reg_top/11.edn_intr_test.381625560 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:07 PM PDT 24 45741331 ps
T885 /workspace/coverage/cover_reg_top/8.edn_intr_test.1982678656 Mar 31 12:28:36 PM PDT 24 Mar 31 12:28:38 PM PDT 24 31051403 ps
T886 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3605271926 Mar 31 12:25:58 PM PDT 24 Mar 31 12:26:00 PM PDT 24 51715947 ps
T211 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2610243377 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:04 PM PDT 24 26005809 ps
T887 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.886673807 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:04 PM PDT 24 71023524 ps
T888 /workspace/coverage/cover_reg_top/5.edn_intr_test.3932708240 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 16189693 ps
T889 /workspace/coverage/cover_reg_top/13.edn_intr_test.4279338299 Mar 31 12:26:44 PM PDT 24 Mar 31 12:26:45 PM PDT 24 23733436 ps
T890 /workspace/coverage/cover_reg_top/24.edn_intr_test.1308095246 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:06 PM PDT 24 47496497 ps
T891 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1304450483 Mar 31 12:26:14 PM PDT 24 Mar 31 12:26:15 PM PDT 24 16687983 ps
T212 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1592999957 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 15661185 ps
T892 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.362618533 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 102592098 ps
T893 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1774276734 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:02 PM PDT 24 40572911 ps
T894 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1425128852 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:07 PM PDT 24 137275101 ps
T895 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2542313970 Mar 31 12:26:09 PM PDT 24 Mar 31 12:26:11 PM PDT 24 108220244 ps
T896 /workspace/coverage/cover_reg_top/37.edn_intr_test.669002163 Mar 31 12:26:39 PM PDT 24 Mar 31 12:26:40 PM PDT 24 27033527 ps
T897 /workspace/coverage/cover_reg_top/15.edn_csr_rw.514505306 Mar 31 12:26:48 PM PDT 24 Mar 31 12:26:49 PM PDT 24 12478599 ps
T898 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2714796345 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:04 PM PDT 24 63976456 ps
T899 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1687199398 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:07 PM PDT 24 42496494 ps
T900 /workspace/coverage/cover_reg_top/1.edn_intr_test.3916903736 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:04 PM PDT 24 16862443 ps
T901 /workspace/coverage/cover_reg_top/17.edn_intr_test.3171644682 Mar 31 12:26:43 PM PDT 24 Mar 31 12:26:44 PM PDT 24 25181008 ps
T902 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1439454503 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:05 PM PDT 24 16494227 ps
T903 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.307812335 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 54545249 ps
T904 /workspace/coverage/cover_reg_top/10.edn_intr_test.1132039404 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:51 PM PDT 24 54677328 ps
T905 /workspace/coverage/cover_reg_top/30.edn_intr_test.2360556965 Mar 31 12:26:11 PM PDT 24 Mar 31 12:26:15 PM PDT 24 14184830 ps
T906 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3827892297 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:12 PM PDT 24 59605138 ps
T907 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3725397552 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:01 PM PDT 24 227398542 ps
T908 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1042173859 Mar 31 12:26:11 PM PDT 24 Mar 31 12:26:12 PM PDT 24 17973358 ps
T909 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1097181206 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:09 PM PDT 24 202792028 ps
T910 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1325091497 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 138831793 ps
T911 /workspace/coverage/cover_reg_top/49.edn_intr_test.1327123485 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:11 PM PDT 24 20842598 ps
T912 /workspace/coverage/cover_reg_top/18.edn_intr_test.2751105802 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:02 PM PDT 24 21627617 ps
T913 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1414056297 Mar 31 12:26:12 PM PDT 24 Mar 31 12:26:16 PM PDT 24 48848774 ps
T914 /workspace/coverage/cover_reg_top/41.edn_intr_test.1782301290 Mar 31 12:26:10 PM PDT 24 Mar 31 12:26:12 PM PDT 24 12730634 ps
T915 /workspace/coverage/cover_reg_top/43.edn_intr_test.2561131909 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:09 PM PDT 24 48599449 ps
T916 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.940997944 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:02 PM PDT 24 477579501 ps
T917 /workspace/coverage/cover_reg_top/13.edn_csr_rw.499121213 Mar 31 12:25:57 PM PDT 24 Mar 31 12:25:58 PM PDT 24 43308138 ps
T918 /workspace/coverage/cover_reg_top/3.edn_intr_test.744282113 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:05 PM PDT 24 26199888 ps
T919 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.180355470 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:08 PM PDT 24 59939152 ps
T920 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1870719145 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:06 PM PDT 24 156651276 ps
T921 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3635119314 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:06 PM PDT 24 84034330 ps
T922 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2539176426 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:01 PM PDT 24 27944413 ps
T923 /workspace/coverage/cover_reg_top/14.edn_intr_test.3671741279 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:52 PM PDT 24 15007195 ps
T924 /workspace/coverage/cover_reg_top/19.edn_intr_test.3888637335 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:03 PM PDT 24 14032305 ps
T925 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.298867575 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:07 PM PDT 24 18070379 ps
T926 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1149225130 Mar 31 12:26:39 PM PDT 24 Mar 31 12:26:46 PM PDT 24 128179650 ps
T927 /workspace/coverage/cover_reg_top/12.edn_intr_test.2201431090 Mar 31 12:26:09 PM PDT 24 Mar 31 12:26:11 PM PDT 24 41228571 ps
T928 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.888191619 Mar 31 12:28:31 PM PDT 24 Mar 31 12:28:33 PM PDT 24 81289351 ps
T929 /workspace/coverage/cover_reg_top/46.edn_intr_test.867462177 Mar 31 12:26:11 PM PDT 24 Mar 31 12:26:12 PM PDT 24 14190139 ps
T930 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3983304522 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:10 PM PDT 24 34164616 ps
T931 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1959579911 Mar 31 12:26:29 PM PDT 24 Mar 31 12:26:32 PM PDT 24 202752848 ps
T932 /workspace/coverage/cover_reg_top/32.edn_intr_test.2780334441 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:08 PM PDT 24 116634527 ps
T933 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3559887735 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:09 PM PDT 24 14456580 ps
T934 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2067042358 Mar 31 12:26:09 PM PDT 24 Mar 31 12:26:12 PM PDT 24 376365682 ps
T935 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1974174006 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 70512540 ps
T936 /workspace/coverage/cover_reg_top/48.edn_intr_test.2421286881 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:06 PM PDT 24 28865740 ps
T937 /workspace/coverage/cover_reg_top/44.edn_intr_test.843697238 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 15024478 ps
T938 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4142303814 Mar 31 12:26:30 PM PDT 24 Mar 31 12:26:32 PM PDT 24 96629469 ps
T939 /workspace/coverage/cover_reg_top/31.edn_intr_test.1676620737 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:10 PM PDT 24 33955731 ps
T940 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1829086802 Mar 31 12:26:00 PM PDT 24 Mar 31 12:26:07 PM PDT 24 84246068 ps
T941 /workspace/coverage/cover_reg_top/21.edn_intr_test.1251940168 Mar 31 12:26:14 PM PDT 24 Mar 31 12:26:15 PM PDT 24 133673996 ps
T213 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.328965243 Mar 31 12:26:03 PM PDT 24 Mar 31 12:26:04 PM PDT 24 152181996 ps
T942 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2353846469 Mar 31 12:25:47 PM PDT 24 Mar 31 12:25:48 PM PDT 24 166711031 ps
T216 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.591364366 Mar 31 12:26:10 PM PDT 24 Mar 31 12:26:15 PM PDT 24 15737012 ps
T943 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1048185445 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:07 PM PDT 24 15129921 ps
T944 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3302569037 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:12 PM PDT 24 253310477 ps
T945 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3193389792 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:13 PM PDT 24 38614661 ps
T946 /workspace/coverage/cover_reg_top/39.edn_intr_test.3996133647 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:05 PM PDT 24 22730596 ps
T947 /workspace/coverage/cover_reg_top/7.edn_intr_test.3451802247 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:03 PM PDT 24 14844681 ps
T948 /workspace/coverage/cover_reg_top/45.edn_intr_test.181190044 Mar 31 12:26:13 PM PDT 24 Mar 31 12:26:14 PM PDT 24 41325448 ps
T949 /workspace/coverage/cover_reg_top/34.edn_intr_test.1078526357 Mar 31 12:28:37 PM PDT 24 Mar 31 12:28:38 PM PDT 24 25409526 ps
T950 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1569680976 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:04 PM PDT 24 46224159 ps
T951 /workspace/coverage/cover_reg_top/33.edn_intr_test.3166203105 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:10 PM PDT 24 11936657 ps
T952 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2379065169 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:04 PM PDT 24 148344296 ps
T953 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.572270438 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 58401451 ps
T954 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.98342531 Mar 31 12:26:08 PM PDT 24 Mar 31 12:26:11 PM PDT 24 304315074 ps
T955 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1796515295 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:54 PM PDT 24 31064053 ps
T217 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2574644294 Mar 31 12:26:07 PM PDT 24 Mar 31 12:26:08 PM PDT 24 42023916 ps
T956 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4160543065 Mar 31 12:26:02 PM PDT 24 Mar 31 12:26:06 PM PDT 24 189704092 ps
T957 /workspace/coverage/cover_reg_top/35.edn_intr_test.3472791708 Mar 31 12:26:11 PM PDT 24 Mar 31 12:26:13 PM PDT 24 13371288 ps
T958 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2933744202 Mar 31 12:25:58 PM PDT 24 Mar 31 12:26:05 PM PDT 24 251344906 ps
T959 /workspace/coverage/cover_reg_top/8.edn_tl_errors.412190198 Mar 31 12:26:06 PM PDT 24 Mar 31 12:26:08 PM PDT 24 104826457 ps
T214 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2522878259 Mar 31 12:26:01 PM PDT 24 Mar 31 12:26:02 PM PDT 24 18192423 ps
T960 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3417730819 Mar 31 12:26:10 PM PDT 24 Mar 31 12:26:15 PM PDT 24 87043600 ps
T215 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2177293319 Mar 31 12:26:30 PM PDT 24 Mar 31 12:26:30 PM PDT 24 110672766 ps
T961 /workspace/coverage/cover_reg_top/15.edn_intr_test.1819929008 Mar 31 12:26:20 PM PDT 24 Mar 31 12:26:21 PM PDT 24 39910952 ps
T962 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2174101852 Mar 31 12:26:37 PM PDT 24 Mar 31 12:26:39 PM PDT 24 27473669 ps
T963 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2029816168 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:07 PM PDT 24 84060271 ps
T964 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2940194067 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:52 PM PDT 24 117831536 ps
T965 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1899857577 Mar 31 12:26:10 PM PDT 24 Mar 31 12:26:12 PM PDT 24 47552965 ps

Test location /workspace/coverage/default/55.edn_genbits.3249702370
Short name T10
Test name
Test status
Simulation time 98983987 ps
CPU time 2.46 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:19 PM PDT 24
Peak memory 216924 kb
Host smart-14637bb8-b028-4849-9ac3-2240155b8fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249702370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3249702370
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2287780420
Short name T23
Test name
Test status
Simulation time 12767634133 ps
CPU time 291.82 seconds
Started Mar 31 01:11:09 PM PDT 24
Finished Mar 31 01:16:01 PM PDT 24
Peak memory 218132 kb
Host smart-66e29555-9d24-4056-9cec-5cb3e93aa48e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287780420 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2287780420
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_err.2165506712
Short name T64
Test name
Test status
Simulation time 29766231 ps
CPU time 0.93 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 218216 kb
Host smart-68aad906-1bf8-4c31-af76-fedcf298313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165506712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2165506712
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/14.edn_alert.3157529082
Short name T17
Test name
Test status
Simulation time 33878409 ps
CPU time 1.1 seconds
Started Mar 31 01:11:04 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 215668 kb
Host smart-ee62a0b6-e5de-479e-871a-f2a0de96f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157529082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3157529082
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1549681251
Short name T19
Test name
Test status
Simulation time 220181104 ps
CPU time 3.8 seconds
Started Mar 31 01:10:26 PM PDT 24
Finished Mar 31 01:10:30 PM PDT 24
Peak memory 234372 kb
Host smart-9bf24172-045d-491d-ab7d-eb0a78dc2ad5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549681251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1549681251
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2129004039
Short name T9
Test name
Test status
Simulation time 122989209 ps
CPU time 1.05 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 216336 kb
Host smart-9b5c385b-cf05-474f-8bee-d1e7a92deeda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129004039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2129004039
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.344810044
Short name T54
Test name
Test status
Simulation time 2497403350 ps
CPU time 5.13 seconds
Started Mar 31 01:10:17 PM PDT 24
Finished Mar 31 01:10:22 PM PDT 24
Peak memory 236240 kb
Host smart-482ace84-5667-41d6-9496-ae5bbffc6da4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344810044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.344810044
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1171648121
Short name T49
Test name
Test status
Simulation time 51075696 ps
CPU time 0.99 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 217528 kb
Host smart-8de1afc4-ead2-43b7-ba56-770a5e44d58e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171648121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1171648121
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1043354381
Short name T184
Test name
Test status
Simulation time 103447711427 ps
CPU time 1332.49 seconds
Started Mar 31 01:11:05 PM PDT 24
Finished Mar 31 01:33:18 PM PDT 24
Peak memory 225148 kb
Host smart-1894572f-537c-40c8-ba8e-91e53842cb42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043354381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1043354381
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.edn_genbits.872382349
Short name T32
Test name
Test status
Simulation time 32259863 ps
CPU time 1.32 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 218020 kb
Host smart-308b50b4-45cc-4eda-abce-dadd2abd42fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872382349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.872382349
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3475909829
Short name T5
Test name
Test status
Simulation time 21430266 ps
CPU time 1.08 seconds
Started Mar 31 01:10:18 PM PDT 24
Finished Mar 31 01:10:19 PM PDT 24
Peak memory 215580 kb
Host smart-0526b72e-d481-49b0-a52b-abcf78e40607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475909829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3475909829
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/12.edn_alert.1051801985
Short name T278
Test name
Test status
Simulation time 87124542 ps
CPU time 1.23 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 215604 kb
Host smart-d51520a1-8b5c-46e9-b40f-8641f334c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051801985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1051801985
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.979349876
Short name T133
Test name
Test status
Simulation time 74856479 ps
CPU time 0.91 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:10:20 PM PDT 24
Peak memory 207080 kb
Host smart-3ccfdc8d-f37e-4b92-b0c3-be2bf7516307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979349876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.979349876
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2523466795
Short name T88
Test name
Test status
Simulation time 46231761 ps
CPU time 1.33 seconds
Started Mar 31 01:11:56 PM PDT 24
Finished Mar 31 01:11:57 PM PDT 24
Peak memory 216356 kb
Host smart-e5fb292c-460e-44a5-a7e2-6a4b1c8d8ee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523466795 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2523466795
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.680945862
Short name T237
Test name
Test status
Simulation time 162308913 ps
CPU time 2.26 seconds
Started Mar 31 12:25:58 PM PDT 24
Finished Mar 31 12:26:00 PM PDT 24
Peak memory 206256 kb
Host smart-ec8f7c55-2ba4-47ff-83be-7de890cfba19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680945862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.680945862
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_alert.1556674239
Short name T120
Test name
Test status
Simulation time 82126585 ps
CPU time 1.22 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:10:20 PM PDT 24
Peak memory 215640 kb
Host smart-11e72628-353e-4859-9b44-a9ed9a38b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556674239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1556674239
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3153713126
Short name T203
Test name
Test status
Simulation time 29400336 ps
CPU time 0.78 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:03 PM PDT 24
Peak memory 205964 kb
Host smart-8e775845-fd86-4d71-b587-1b356158b4b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153713126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3153713126
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/default/21.edn_alert.2122740040
Short name T145
Test name
Test status
Simulation time 31565556 ps
CPU time 1.26 seconds
Started Mar 31 01:11:17 PM PDT 24
Finished Mar 31 01:11:18 PM PDT 24
Peak memory 215600 kb
Host smart-e4c5b1d8-5f3d-41f2-9433-ba6b8382f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122740040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2122740040
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.861445949
Short name T76
Test name
Test status
Simulation time 58983980 ps
CPU time 1.13 seconds
Started Mar 31 01:10:25 PM PDT 24
Finished Mar 31 01:10:26 PM PDT 24
Peak memory 216440 kb
Host smart-39c3ff46-7cf2-4f89-b751-d40da33e7f5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861445949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.861445949
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable.1286267587
Short name T576
Test name
Test status
Simulation time 30578043 ps
CPU time 0.85 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:12 PM PDT 24
Peak memory 215836 kb
Host smart-a80256af-3b05-4283-8c85-daabfe637aa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286267587 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1286267587
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.812441368
Short name T117
Test name
Test status
Simulation time 11896085 ps
CPU time 0.89 seconds
Started Mar 31 01:11:38 PM PDT 24
Finished Mar 31 01:11:39 PM PDT 24
Peak memory 215952 kb
Host smart-7fb2eb9b-e60e-4c64-ba88-c076e9d4ac7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812441368 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.812441368
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.2873144755
Short name T108
Test name
Test status
Simulation time 22470707 ps
CPU time 0.82 seconds
Started Mar 31 01:11:19 PM PDT 24
Finished Mar 31 01:11:20 PM PDT 24
Peak memory 215776 kb
Host smart-a403b1e5-291f-4087-9d7d-f0be91dfd8af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873144755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2873144755
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/11.edn_intr.1390250489
Short name T125
Test name
Test status
Simulation time 37916783 ps
CPU time 0.87 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 215688 kb
Host smart-4303a714-2827-4e23-bd4b-6a8cdde6ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390250489 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1390250489
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/44.edn_disable.3013966367
Short name T95
Test name
Test status
Simulation time 22700767 ps
CPU time 0.89 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 215388 kb
Host smart-9aaaa4ca-3792-41a9-8ac4-72427ec8ddbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013966367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3013966367
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/111.edn_genbits.2769093276
Short name T286
Test name
Test status
Simulation time 33819430 ps
CPU time 1.29 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:56 PM PDT 24
Peak memory 219404 kb
Host smart-04001af1-e84a-4af1-8fb7-256f083d8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769093276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2769093276
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.18369767
Short name T7
Test name
Test status
Simulation time 168419171 ps
CPU time 1.07 seconds
Started Mar 31 01:12:25 PM PDT 24
Finished Mar 31 01:12:26 PM PDT 24
Peak memory 219352 kb
Host smart-474bb5f8-ae44-4810-896f-58740b7bca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18369767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.18369767
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/30.edn_disable.832443724
Short name T51
Test name
Test status
Simulation time 10332742 ps
CPU time 0.87 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 215796 kb
Host smart-b5bbddc5-783a-44e1-91cd-686fb5fd3d17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832443724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.832443724
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/16.edn_alert.3409672671
Short name T270
Test name
Test status
Simulation time 74365134 ps
CPU time 1.2 seconds
Started Mar 31 01:11:06 PM PDT 24
Finished Mar 31 01:11:08 PM PDT 24
Peak memory 215620 kb
Host smart-6d379b4f-06c7-435a-a44c-5247efc857f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409672671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3409672671
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/272.edn_genbits.3224938816
Short name T255
Test name
Test status
Simulation time 77797882 ps
CPU time 1.73 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 217872 kb
Host smart-7d6b1070-4496-4882-a59e-e77c16dfe537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224938816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3224938816
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.53036604
Short name T545
Test name
Test status
Simulation time 13659161 ps
CPU time 0.88 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:10:20 PM PDT 24
Peak memory 215964 kb
Host smart-3950a7a5-6b47-44f5-915f-18f2b5c7d01b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53036604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.53036604
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.771947419
Short name T156
Test name
Test status
Simulation time 65814805 ps
CPU time 1.44 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 216420 kb
Host smart-eeed66b1-7cb5-43b3-ad6d-e29a297d4c57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771947419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.771947419
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_disable.1374443451
Short name T101
Test name
Test status
Simulation time 71982832 ps
CPU time 0.83 seconds
Started Mar 31 01:10:33 PM PDT 24
Finished Mar 31 01:10:34 PM PDT 24
Peak memory 215376 kb
Host smart-adf5e349-7d24-42d2-bd21-76d98fd00d08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374443451 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1374443451
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2826796016
Short name T79
Test name
Test status
Simulation time 49820962 ps
CPU time 1.14 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 216336 kb
Host smart-a22a79de-a81a-42c8-9113-0fa10e965291
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826796016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2826796016
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2103257305
Short name T92
Test name
Test status
Simulation time 142245112 ps
CPU time 1.16 seconds
Started Mar 31 01:10:37 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 216320 kb
Host smart-ce0eb8f0-53d7-46e1-8fb8-b81b56cd0437
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103257305 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2103257305
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_alert_test.1939076265
Short name T316
Test name
Test status
Simulation time 24637711 ps
CPU time 0.9 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:04 PM PDT 24
Peak memory 206580 kb
Host smart-fc1f9b0d-ecbf-4ad8-8b5b-ce8ff874d667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939076265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1939076265
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/54.edn_err.2108416195
Short name T81
Test name
Test status
Simulation time 20103694 ps
CPU time 1.07 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:20 PM PDT 24
Peak memory 219172 kb
Host smart-0dccde9f-2aa6-44a0-912f-b0e61ed34bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108416195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2108416195
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/116.edn_genbits.4265892923
Short name T247
Test name
Test status
Simulation time 164263417 ps
CPU time 2.42 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 216848 kb
Host smart-bcdc54f0-8ca2-4f0b-a385-2feb3d7f985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265892923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4265892923
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3668560968
Short name T27
Test name
Test status
Simulation time 91722271 ps
CPU time 1.25 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 216612 kb
Host smart-f3fce1f5-b7f6-4e66-bbcc-a8dad2e0ae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668560968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3668560968
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3953348160
Short name T261
Test name
Test status
Simulation time 42189204 ps
CPU time 1.63 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 217872 kb
Host smart-c344972d-93d3-4d04-95f8-967f07b3c195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953348160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3953348160
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1524865032
Short name T147
Test name
Test status
Simulation time 24750915 ps
CPU time 1.18 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 215636 kb
Host smart-ecceff93-bb09-491a-b5b1-fa0412117f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524865032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1524865032
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/5.edn_regwen.1214042708
Short name T267
Test name
Test status
Simulation time 145959948 ps
CPU time 0.93 seconds
Started Mar 31 01:10:33 PM PDT 24
Finished Mar 31 01:10:34 PM PDT 24
Peak memory 207084 kb
Host smart-a7f58a46-8807-452c-9722-0281db8baabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214042708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1214042708
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_regwen.1963083904
Short name T273
Test name
Test status
Simulation time 18806006 ps
CPU time 0.97 seconds
Started Mar 31 01:10:37 PM PDT 24
Finished Mar 31 01:10:38 PM PDT 24
Peak memory 207104 kb
Host smart-44c6af82-972f-42b0-97b1-b42046adf736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963083904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1963083904
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/13.edn_genbits.2186167636
Short name T37
Test name
Test status
Simulation time 96771009 ps
CPU time 1.37 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 217844 kb
Host smart-5cf78fc0-22f7-4412-902c-ebe7358f0b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186167636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2186167636
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_err.2220738408
Short name T45
Test name
Test status
Simulation time 35288322 ps
CPU time 1.49 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 233496 kb
Host smart-19f23056-eb90-4ae0-9b2a-5415601254b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220738408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2220738408
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/246.edn_genbits.3983406925
Short name T264
Test name
Test status
Simulation time 84231372 ps
CPU time 1.39 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 219324 kb
Host smart-50c42fb9-c39b-4d8b-ac95-da2ec444b80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983406925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3983406925
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_genbits.3477179846
Short name T11
Test name
Test status
Simulation time 57017563 ps
CPU time 1.34 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 219320 kb
Host smart-a942bc03-9cdc-4ee9-b9fb-b6eac96baf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477179846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3477179846
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3532717141
Short name T140
Test name
Test status
Simulation time 20013237 ps
CPU time 1.1 seconds
Started Mar 31 01:11:40 PM PDT 24
Finished Mar 31 01:11:41 PM PDT 24
Peak memory 215636 kb
Host smart-5ee276ef-b763-406f-a3c4-a4a9331c49b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532717141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3532717141
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2522878259
Short name T214
Test name
Test status
Simulation time 18192423 ps
CPU time 0.95 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206176 kb
Host smart-cdcfa9f5-5af6-4f1f-a329-13540fa05cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522878259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2522878259
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_genbits.3448010257
Short name T1
Test name
Test status
Simulation time 25542145 ps
CPU time 1.1 seconds
Started Mar 31 01:10:11 PM PDT 24
Finished Mar 31 01:10:12 PM PDT 24
Peak memory 216640 kb
Host smart-c3db74d8-b68e-4fab-b0d8-af17b475889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448010257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3448010257
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2698721514
Short name T25
Test name
Test status
Simulation time 1008601566770 ps
CPU time 1876.57 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:41:36 PM PDT 24
Peak memory 224652 kb
Host smart-9de60e69-0430-4c8e-be59-4381d7e67287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698721514 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2698721514
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_genbits.2692175776
Short name T292
Test name
Test status
Simulation time 37118097 ps
CPU time 1.42 seconds
Started Mar 31 01:11:00 PM PDT 24
Finished Mar 31 01:11:03 PM PDT 24
Peak memory 216644 kb
Host smart-b3bd18ac-8182-4cf6-95dc-9bcfb3c742fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692175776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2692175776
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1475589896
Short name T743
Test name
Test status
Simulation time 130560932 ps
CPU time 1.15 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 216356 kb
Host smart-77191ec3-33bd-4100-93ed-55426aace7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475589896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1475589896
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3164682987
Short name T50
Test name
Test status
Simulation time 73869802 ps
CPU time 1.53 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 218112 kb
Host smart-b0bdb961-a9e7-4bc9-8858-686acb52dce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164682987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3164682987
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4137311185
Short name T337
Test name
Test status
Simulation time 36627419 ps
CPU time 1.08 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 216476 kb
Host smart-d2c63d39-4b48-4566-a616-6d966d3a16db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137311185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4137311185
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1013375437
Short name T119
Test name
Test status
Simulation time 27810216 ps
CPU time 1.26 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:30 PM PDT 24
Peak memory 215648 kb
Host smart-2a9230d3-707c-437b-991d-2e84ea585998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013375437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1013375437
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.49503458
Short name T766
Test name
Test status
Simulation time 22617972 ps
CPU time 1.17 seconds
Started Mar 31 01:11:38 PM PDT 24
Finished Mar 31 01:11:39 PM PDT 24
Peak memory 215640 kb
Host smart-4bba3d5d-0360-4e7a-bea9-fedfe19adf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49503458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.49503458
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/281.edn_genbits.2481969216
Short name T251
Test name
Test status
Simulation time 31133889 ps
CPU time 1.4 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 216780 kb
Host smart-7a429da5-92cd-4fc8-a713-7a951596399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481969216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2481969216
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_genbits.2074969144
Short name T253
Test name
Test status
Simulation time 39381960 ps
CPU time 1.61 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 217876 kb
Host smart-215a3042-4b9b-4d5e-a50c-7306678b12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074969144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2074969144
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_genbits.2168990718
Short name T246
Test name
Test status
Simulation time 48900362 ps
CPU time 1.8 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217720 kb
Host smart-091617b0-6acb-4c63-afb0-c966c8c33a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168990718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2168990718
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1964552340
Short name T129
Test name
Test status
Simulation time 22049519 ps
CPU time 1.05 seconds
Started Mar 31 01:11:58 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 215720 kb
Host smart-4b73ae19-dea9-4d9f-bed7-bb3175f3623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964552340 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1964552340
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/11.edn_alert.2990517503
Short name T103
Test name
Test status
Simulation time 255030844 ps
CPU time 1.38 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 215548 kb
Host smart-08d1673a-6908-4fc5-945c-e60300441c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990517503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2990517503
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/31.edn_disable.474802549
Short name T175
Test name
Test status
Simulation time 11797484 ps
CPU time 0.91 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 215380 kb
Host smart-0da506d8-86ce-4ff3-bbfe-d09caa48576d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474802549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.474802549
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/212.edn_genbits.4180595342
Short name T489
Test name
Test status
Simulation time 66794576 ps
CPU time 1.95 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 218016 kb
Host smart-3b0ae2d1-74de-477c-b4e9-edae1573d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180595342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4180595342
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1425128852
Short name T894
Test name
Test status
Simulation time 137275101 ps
CPU time 1.49 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206168 kb
Host smart-2c887856-943f-4998-9937-93cbff242159
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425128852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1425128852
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.180355470
Short name T919
Test name
Test status
Simulation time 59939152 ps
CPU time 3.17 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:08 PM PDT 24
Peak memory 206168 kb
Host smart-f8360cd1-f2ea-438b-a050-804a2a56c55a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180355470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.180355470
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2353846469
Short name T942
Test name
Test status
Simulation time 166711031 ps
CPU time 0.88 seconds
Started Mar 31 12:25:47 PM PDT 24
Finished Mar 31 12:25:48 PM PDT 24
Peak memory 206248 kb
Host smart-b14be43e-de79-4ce5-8ae0-154b24221a93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353846469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2353846469
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4139042712
Short name T859
Test name
Test status
Simulation time 30561976 ps
CPU time 1.16 seconds
Started Mar 31 12:25:53 PM PDT 24
Finished Mar 31 12:25:54 PM PDT 24
Peak memory 214636 kb
Host smart-72ca4759-a51d-4049-9baf-d7421da1cbd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139042712 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4139042712
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.453318086
Short name T878
Test name
Test status
Simulation time 30471277 ps
CPU time 0.77 seconds
Started Mar 31 12:25:56 PM PDT 24
Finished Mar 31 12:25:57 PM PDT 24
Peak memory 205988 kb
Host smart-d9c89a56-2650-4513-b92a-a24d436a200f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453318086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.453318086
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3971720468
Short name T843
Test name
Test status
Simulation time 89673167 ps
CPU time 0.93 seconds
Started Mar 31 12:25:49 PM PDT 24
Finished Mar 31 12:25:50 PM PDT 24
Peak memory 206168 kb
Host smart-c40e8aad-fad0-4083-be1c-d319c4a43bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971720468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3971720468
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.975508615
Short name T223
Test name
Test status
Simulation time 30814759 ps
CPU time 1.27 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206364 kb
Host smart-39d793c4-2b5f-4f52-a817-69ce20ce4888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975508615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.975508615
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2619539661
Short name T851
Test name
Test status
Simulation time 210376802 ps
CPU time 3.85 seconds
Started Mar 31 12:25:52 PM PDT 24
Finished Mar 31 12:25:56 PM PDT 24
Peak memory 214620 kb
Host smart-4e3d329f-f305-438b-955d-340d2c1805b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619539661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2619539661
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4273555902
Short name T205
Test name
Test status
Simulation time 70625533 ps
CPU time 1.47 seconds
Started Mar 31 12:25:54 PM PDT 24
Finished Mar 31 12:25:56 PM PDT 24
Peak memory 206148 kb
Host smart-c7463ccb-329f-4e53-abd4-031035b1d467
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273555902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4273555902
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2933744202
Short name T958
Test name
Test status
Simulation time 251344906 ps
CPU time 5.96 seconds
Started Mar 31 12:25:58 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 206156 kb
Host smart-fb943bc2-1eba-4198-b660-9818bd1146a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933744202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2933744202
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.591364366
Short name T216
Test name
Test status
Simulation time 15737012 ps
CPU time 0.93 seconds
Started Mar 31 12:26:10 PM PDT 24
Finished Mar 31 12:26:15 PM PDT 24
Peak memory 206068 kb
Host smart-aca311c6-d320-4c3e-9de9-1ca2a47af3f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591364366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.591364366
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3827892297
Short name T906
Test name
Test status
Simulation time 59605138 ps
CPU time 1.4 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 214212 kb
Host smart-18fafb75-eb3c-4d8c-a44a-e355044fc9ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827892297 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3827892297
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2574644294
Short name T217
Test name
Test status
Simulation time 42023916 ps
CPU time 0.84 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:08 PM PDT 24
Peak memory 206136 kb
Host smart-9512af0e-4c2b-4204-ba13-eca6750c774e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574644294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2574644294
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3916903736
Short name T900
Test name
Test status
Simulation time 16862443 ps
CPU time 0.82 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 205940 kb
Host smart-b36d48a3-e85c-484f-b7b7-6eb42123550f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916903736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3916903736
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.886673807
Short name T887
Test name
Test status
Simulation time 71023524 ps
CPU time 1.04 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206304 kb
Host smart-0699bf3c-f81a-4d4e-86aa-ef018fa16aac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886673807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.886673807
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2379065169
Short name T952
Test name
Test status
Simulation time 148344296 ps
CPU time 2.73 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 214596 kb
Host smart-222e1f91-db59-4a78-a96a-170f4d53e11f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379065169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2379065169
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3078160126
Short name T880
Test name
Test status
Simulation time 144440122 ps
CPU time 2.25 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:03 PM PDT 24
Peak memory 206340 kb
Host smart-39ad03aa-23da-43b3-901d-741966dfa8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078160126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3078160126
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.956956193
Short name T862
Test name
Test status
Simulation time 54802195 ps
CPU time 1.13 seconds
Started Mar 31 12:25:59 PM PDT 24
Finished Mar 31 12:26:00 PM PDT 24
Peak memory 214640 kb
Host smart-0ec5b4d2-ed95-48b2-b335-1f679763defb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956956193 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.956956193
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2610243377
Short name T211
Test name
Test status
Simulation time 26005809 ps
CPU time 0.98 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206164 kb
Host smart-48fd7993-2278-4a35-8aa6-1be5353529b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610243377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2610243377
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1132039404
Short name T904
Test name
Test status
Simulation time 54677328 ps
CPU time 0.86 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:51 PM PDT 24
Peak memory 206148 kb
Host smart-5ee2e3e0-eb3e-4835-9bce-0406dfbf4f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132039404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1132039404
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.362618533
Short name T892
Test name
Test status
Simulation time 102592098 ps
CPU time 1.29 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 206408 kb
Host smart-6ab75d7f-0f93-4937-8ac5-2b6f09a6c228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362618533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.362618533
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3221275550
Short name T857
Test name
Test status
Simulation time 390932334 ps
CPU time 3.69 seconds
Started Mar 31 12:28:53 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 214704 kb
Host smart-d66282d3-8ad2-4314-bbcf-08c026beff7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221275550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3221275550
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2393086630
Short name T241
Test name
Test status
Simulation time 183128509 ps
CPU time 3.69 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206328 kb
Host smart-e9c59a71-2f82-4782-82fa-a28dbd802305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393086630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2393086630
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1039920301
Short name T863
Test name
Test status
Simulation time 38548340 ps
CPU time 1.16 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 12:28:29 PM PDT 24
Peak memory 214588 kb
Host smart-8f9be5ec-5bd6-4599-b428-e2e1348bb21e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039920301 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1039920301
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1304450483
Short name T891
Test name
Test status
Simulation time 16687983 ps
CPU time 0.9 seconds
Started Mar 31 12:26:14 PM PDT 24
Finished Mar 31 12:26:15 PM PDT 24
Peak memory 206136 kb
Host smart-e0eeb1cc-3252-4f3f-bf87-ef2b36c75fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304450483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1304450483
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.381625560
Short name T884
Test name
Test status
Simulation time 45741331 ps
CPU time 0.82 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206152 kb
Host smart-397ec03b-fcd3-422e-a05c-5e18a49bfc37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381625560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.381625560
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2691455840
Short name T221
Test name
Test status
Simulation time 164617076 ps
CPU time 1.22 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 206260 kb
Host smart-76bc6bd8-67f0-47a5-85fe-c3305c7494e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691455840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2691455840
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3635119314
Short name T921
Test name
Test status
Simulation time 84034330 ps
CPU time 2.84 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 214640 kb
Host smart-252a556c-e434-4730-a0b5-7b14521a6f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635119314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3635119314
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3678497393
Short name T858
Test name
Test status
Simulation time 283088855 ps
CPU time 2.23 seconds
Started Mar 31 12:25:56 PM PDT 24
Finished Mar 31 12:25:58 PM PDT 24
Peak memory 206316 kb
Host smart-105258ba-38c2-4ac1-bd29-ea7b114b6ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678497393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3678497393
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1796515295
Short name T955
Test name
Test status
Simulation time 31064053 ps
CPU time 1.25 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 214564 kb
Host smart-5ed8b283-58c5-469e-9cf6-a34c179481c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796515295 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1796515295
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1687199398
Short name T899
Test name
Test status
Simulation time 42496494 ps
CPU time 0.87 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206128 kb
Host smart-370d24a3-96b0-40eb-b8e6-5720f33f0f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687199398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1687199398
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2201431090
Short name T927
Test name
Test status
Simulation time 41228571 ps
CPU time 0.77 seconds
Started Mar 31 12:26:09 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 206020 kb
Host smart-fc8d7f8d-862b-4528-aeef-d5f73b8edfbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201431090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2201431090
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1097181206
Short name T909
Test name
Test status
Simulation time 202792028 ps
CPU time 1.38 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206400 kb
Host smart-9a7230ed-bdad-42f3-a1d4-a31cda55610c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097181206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1097181206
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1829086802
Short name T940
Test name
Test status
Simulation time 84246068 ps
CPU time 1.93 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 214500 kb
Host smart-9ca52335-b45f-4c26-b5df-4c95db3e480b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829086802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1829086802
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3302569037
Short name T944
Test name
Test status
Simulation time 253310477 ps
CPU time 2.24 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 206288 kb
Host smart-b1558e20-2e0c-45be-b1a7-ffac28a75139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302569037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3302569037
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1390927427
Short name T854
Test name
Test status
Simulation time 135239002 ps
CPU time 1.54 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 214568 kb
Host smart-c603fe09-90a0-4e12-b95a-112ee12bafa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390927427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1390927427
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.499121213
Short name T917
Test name
Test status
Simulation time 43308138 ps
CPU time 0.83 seconds
Started Mar 31 12:25:57 PM PDT 24
Finished Mar 31 12:25:58 PM PDT 24
Peak memory 206124 kb
Host smart-de4e0ee3-f9fd-4401-b22f-01ee480230ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499121213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.499121213
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4279338299
Short name T889
Test name
Test status
Simulation time 23733436 ps
CPU time 0.87 seconds
Started Mar 31 12:26:44 PM PDT 24
Finished Mar 31 12:26:45 PM PDT 24
Peak memory 206192 kb
Host smart-3bacb9c4-8b10-4ff7-aad2-0a6ff1fca16e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279338299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4279338299
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3828533029
Short name T879
Test name
Test status
Simulation time 17468064 ps
CPU time 1.11 seconds
Started Mar 31 12:26:41 PM PDT 24
Finished Mar 31 12:26:42 PM PDT 24
Peak memory 206320 kb
Host smart-1fa6c504-5d9a-4aff-bd2d-b57e3837d811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828533029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3828533029
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1959579911
Short name T931
Test name
Test status
Simulation time 202752848 ps
CPU time 3.68 seconds
Started Mar 31 12:26:29 PM PDT 24
Finished Mar 31 12:26:32 PM PDT 24
Peak memory 214688 kb
Host smart-291504e8-2450-4faa-85e2-263b4ca82fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959579911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1959579911
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1325091497
Short name T910
Test name
Test status
Simulation time 138831793 ps
CPU time 2.09 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206348 kb
Host smart-a60deb6f-cd7e-4e4a-a67b-d86b55d8296d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325091497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1325091497
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1106961260
Short name T847
Test name
Test status
Simulation time 324997366 ps
CPU time 1.3 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:51 PM PDT 24
Peak memory 214596 kb
Host smart-d1307801-a2d5-4678-ba08-469e93e4d9fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106961260 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1106961260
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3671741279
Short name T923
Test name
Test status
Simulation time 15007195 ps
CPU time 0.84 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 206192 kb
Host smart-9bd1178a-8dcc-455c-8235-78e94fb666a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671741279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3671741279
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2724049794
Short name T218
Test name
Test status
Simulation time 37795389 ps
CPU time 1.02 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:01 PM PDT 24
Peak memory 206384 kb
Host smart-edb7a8e7-21c0-4dbd-9e71-4d2e465ddbf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724049794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2724049794
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2940194067
Short name T964
Test name
Test status
Simulation time 117831536 ps
CPU time 2.43 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 214636 kb
Host smart-d2bf9cb2-ad85-463b-b188-b68d8a187f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940194067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2940194067
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.307812335
Short name T903
Test name
Test status
Simulation time 54545249 ps
CPU time 1.72 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206344 kb
Host smart-78a13c7e-404b-4c6f-b6c2-068098602ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307812335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.307812335
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2417222821
Short name T842
Test name
Test status
Simulation time 86072844 ps
CPU time 1.49 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 214672 kb
Host smart-0d4a9228-a078-4542-a0d6-ce57c30b67c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417222821 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2417222821
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.514505306
Short name T897
Test name
Test status
Simulation time 12478599 ps
CPU time 0.88 seconds
Started Mar 31 12:26:48 PM PDT 24
Finished Mar 31 12:26:49 PM PDT 24
Peak memory 206192 kb
Host smart-fbcd5d26-a997-4f95-b6df-1f5958d74d1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514505306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.514505306
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1819929008
Short name T961
Test name
Test status
Simulation time 39910952 ps
CPU time 0.85 seconds
Started Mar 31 12:26:20 PM PDT 24
Finished Mar 31 12:26:21 PM PDT 24
Peak memory 206152 kb
Host smart-32cec7ea-d934-4937-9e8f-0cad9933d2ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819929008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1819929008
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4279761046
Short name T872
Test name
Test status
Simulation time 135028783 ps
CPU time 1.37 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 206404 kb
Host smart-12de20ab-3951-457d-914b-18fbd569ded5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279761046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4279761046
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1873285786
Short name T841
Test name
Test status
Simulation time 209311681 ps
CPU time 2.22 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 214656 kb
Host smart-43c3385c-27fe-4381-877e-e40a9392ddd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873285786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1873285786
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3284046209
Short name T238
Test name
Test status
Simulation time 84890458 ps
CPU time 1.51 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 206428 kb
Host smart-93804db3-a479-4c4c-af78-e3c18210b9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284046209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3284046209
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3725397552
Short name T907
Test name
Test status
Simulation time 227398542 ps
CPU time 1.04 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 214620 kb
Host smart-ac10eba7-a6f0-431f-937d-7197900c6a53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725397552 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3725397552
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1403250977
Short name T208
Test name
Test status
Simulation time 28828510 ps
CPU time 0.91 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206164 kb
Host smart-0260817f-09f1-45e3-a1e5-3c91d8597fbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403250977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1403250977
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.624332714
Short name T848
Test name
Test status
Simulation time 23836606 ps
CPU time 0.85 seconds
Started Mar 31 12:26:31 PM PDT 24
Finished Mar 31 12:26:32 PM PDT 24
Peak memory 206132 kb
Host smart-cf15c6ef-4a9d-4090-924f-bd59486144ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624332714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.624332714
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4194091892
Short name T219
Test name
Test status
Simulation time 123465391 ps
CPU time 1.44 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206420 kb
Host smart-4b358ff8-056e-4bff-a5af-f2e8bc184ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194091892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4194091892
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.40491601
Short name T853
Test name
Test status
Simulation time 443844892 ps
CPU time 3.86 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 214808 kb
Host smart-b119374d-4b38-4301-9b52-9e6e515b03d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.40491601
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3605271926
Short name T886
Test name
Test status
Simulation time 51715947 ps
CPU time 1.56 seconds
Started Mar 31 12:25:58 PM PDT 24
Finished Mar 31 12:26:00 PM PDT 24
Peak memory 206320 kb
Host smart-1e62fadf-b968-45db-b41f-5801777fb650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605271926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3605271926
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4142303814
Short name T938
Test name
Test status
Simulation time 96629469 ps
CPU time 1.12 seconds
Started Mar 31 12:26:30 PM PDT 24
Finished Mar 31 12:26:32 PM PDT 24
Peak memory 214636 kb
Host smart-a9073b59-3025-4204-bd72-a363549fc52a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142303814 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4142303814
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.956648832
Short name T224
Test name
Test status
Simulation time 35646008 ps
CPU time 0.81 seconds
Started Mar 31 12:25:58 PM PDT 24
Finished Mar 31 12:25:59 PM PDT 24
Peak memory 205980 kb
Host smart-0beba1f4-356b-439a-95d1-7c720281a4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956648832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.956648832
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3171644682
Short name T901
Test name
Test status
Simulation time 25181008 ps
CPU time 0.87 seconds
Started Mar 31 12:26:43 PM PDT 24
Finished Mar 31 12:26:44 PM PDT 24
Peak memory 206188 kb
Host smart-b509f1c0-8c7d-453e-98bd-9f9df1759986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171644682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3171644682
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.40233471
Short name T220
Test name
Test status
Simulation time 33668628 ps
CPU time 1.35 seconds
Started Mar 31 12:28:25 PM PDT 24
Finished Mar 31 12:28:26 PM PDT 24
Peak memory 206344 kb
Host smart-295630bb-feea-4122-81b0-539c4d6a00db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40233471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_out
standing.40233471
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2714796345
Short name T898
Test name
Test status
Simulation time 63976456 ps
CPU time 2.36 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 214600 kb
Host smart-7cd9ffe6-b2d4-4667-8b66-18d515a7e7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714796345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2714796345
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3784664959
Short name T869
Test name
Test status
Simulation time 213384899 ps
CPU time 2.61 seconds
Started Mar 31 12:26:13 PM PDT 24
Finished Mar 31 12:26:15 PM PDT 24
Peak memory 206296 kb
Host smart-cdbf2d48-8cb3-437d-bc2b-6b844fb90cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784664959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3784664959
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2051886409
Short name T865
Test name
Test status
Simulation time 30410195 ps
CPU time 0.99 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206340 kb
Host smart-4e76661d-6c60-4961-9371-8c96f5617922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051886409 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2051886409
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1974174006
Short name T935
Test name
Test status
Simulation time 70512540 ps
CPU time 0.87 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206136 kb
Host smart-64093606-f52a-4f48-a6d1-7633fdf798b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974174006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1974174006
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2751105802
Short name T912
Test name
Test status
Simulation time 21627617 ps
CPU time 0.84 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206252 kb
Host smart-5a547e99-4dec-4f82-8f9f-cc4a63908ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751105802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2751105802
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1763036090
Short name T201
Test name
Test status
Simulation time 91804502 ps
CPU time 0.99 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:08 PM PDT 24
Peak memory 206288 kb
Host smart-c1cf0742-2fbd-4a01-9d1d-9ee7240db8ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763036090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1763036090
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3034446506
Short name T860
Test name
Test status
Simulation time 102798378 ps
CPU time 3.2 seconds
Started Mar 31 12:26:22 PM PDT 24
Finished Mar 31 12:26:25 PM PDT 24
Peak memory 214532 kb
Host smart-4aee149d-b92a-4770-8293-c2f08ae7c8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034446506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3034446506
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3395679754
Short name T239
Test name
Test status
Simulation time 852422883 ps
CPU time 2.37 seconds
Started Mar 31 12:26:37 PM PDT 24
Finished Mar 31 12:26:40 PM PDT 24
Peak memory 206548 kb
Host smart-935cc2d0-3ea6-4d82-a2a6-05fa330607f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395679754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3395679754
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2174101852
Short name T962
Test name
Test status
Simulation time 27473669 ps
CPU time 1.87 seconds
Started Mar 31 12:26:37 PM PDT 24
Finished Mar 31 12:26:39 PM PDT 24
Peak memory 214620 kb
Host smart-57d0e4c3-d580-4b26-809a-8276fb62e964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174101852 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2174101852
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2177293319
Short name T215
Test name
Test status
Simulation time 110672766 ps
CPU time 0.81 seconds
Started Mar 31 12:26:30 PM PDT 24
Finished Mar 31 12:26:30 PM PDT 24
Peak memory 206168 kb
Host smart-4e5a869e-dec1-4ef3-9351-f9eb280c60bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177293319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2177293319
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3888637335
Short name T924
Test name
Test status
Simulation time 14032305 ps
CPU time 0.86 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:03 PM PDT 24
Peak memory 206168 kb
Host smart-6bfc4353-068d-4f55-8a81-7b68763edad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888637335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3888637335
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2777280936
Short name T222
Test name
Test status
Simulation time 37181965 ps
CPU time 0.98 seconds
Started Mar 31 12:26:11 PM PDT 24
Finished Mar 31 12:26:13 PM PDT 24
Peak memory 206412 kb
Host smart-2a636453-1c7f-49ed-99fa-a3762f9f4e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777280936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2777280936
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.237412996
Short name T871
Test name
Test status
Simulation time 156453891 ps
CPU time 2.7 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 214752 kb
Host smart-06033cd7-d86e-44de-8b8d-c9a61091d8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237412996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.237412996
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1569680976
Short name T950
Test name
Test status
Simulation time 46224159 ps
CPU time 1.53 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206316 kb
Host smart-0594b439-936d-4bb0-8f29-9f4f762be89d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569680976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1569680976
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1626178480
Short name T210
Test name
Test status
Simulation time 24199571 ps
CPU time 1.04 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 206204 kb
Host smart-4553f417-ed4b-4a52-be34-7d18f0058bea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626178480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1626178480
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1621108246
Short name T844
Test name
Test status
Simulation time 486948294 ps
CPU time 3.32 seconds
Started Mar 31 12:26:09 PM PDT 24
Finished Mar 31 12:26:17 PM PDT 24
Peak memory 206196 kb
Host smart-b7deca2b-22db-46ea-af6b-251c52b59296
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621108246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1621108246
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1204795072
Short name T875
Test name
Test status
Simulation time 56529389 ps
CPU time 0.9 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206164 kb
Host smart-891f93a1-7831-4dd6-91aa-a96c1fa1d7c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204795072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1204795072
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2939212046
Short name T836
Test name
Test status
Simulation time 23993106 ps
CPU time 1.08 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 215776 kb
Host smart-b4792bd9-538b-42c2-978b-9666fcf55c37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939212046 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2939212046
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2539176426
Short name T922
Test name
Test status
Simulation time 27944413 ps
CPU time 0.88 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:01 PM PDT 24
Peak memory 206176 kb
Host smart-ac306252-baa8-4e5c-851b-0b350bc2b445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539176426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2539176426
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4009549371
Short name T883
Test name
Test status
Simulation time 61348049 ps
CPU time 0.94 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206148 kb
Host smart-ea0509eb-253e-460b-b548-b69001e9c51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009549371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4009549371
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.298867575
Short name T925
Test name
Test status
Simulation time 18070379 ps
CPU time 1.01 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206292 kb
Host smart-616c31ba-6219-4c00-8749-7e91ff1e1422
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298867575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.298867575
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1870719145
Short name T920
Test name
Test status
Simulation time 156651276 ps
CPU time 2.82 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 214580 kb
Host smart-b4985961-ff71-40dc-b4dc-bfcdfa9f3ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870719145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1870719145
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2490695272
Short name T240
Test name
Test status
Simulation time 141183989 ps
CPU time 2.06 seconds
Started Mar 31 12:26:10 PM PDT 24
Finished Mar 31 12:26:13 PM PDT 24
Peak memory 206312 kb
Host smart-31152b18-2404-48b6-a9ca-eaa01bd9cca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490695272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2490695272
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1370047142
Short name T873
Test name
Test status
Simulation time 11245828 ps
CPU time 0.82 seconds
Started Mar 31 12:26:20 PM PDT 24
Finished Mar 31 12:26:21 PM PDT 24
Peak memory 206420 kb
Host smart-84cbba2c-0838-4e98-b0ac-b28a98035d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370047142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1370047142
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1251940168
Short name T941
Test name
Test status
Simulation time 133673996 ps
CPU time 0.76 seconds
Started Mar 31 12:26:14 PM PDT 24
Finished Mar 31 12:26:15 PM PDT 24
Peak memory 205992 kb
Host smart-4ff1cb2e-626b-464a-ac9d-d01d98bc5ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251940168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1251940168
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3160139622
Short name T870
Test name
Test status
Simulation time 40100271 ps
CPU time 0.82 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 206424 kb
Host smart-0b131c30-9381-401d-ae80-2e3d8bdb6fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160139622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3160139622
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3890038866
Short name T840
Test name
Test status
Simulation time 78214228 ps
CPU time 0.82 seconds
Started Mar 31 12:26:09 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 206172 kb
Host smart-176d6bfb-1fe8-47fb-855d-120410ee40f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890038866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3890038866
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1308095246
Short name T890
Test name
Test status
Simulation time 47496497 ps
CPU time 0.82 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 206196 kb
Host smart-5b3beaa6-4b44-4279-93a1-a0fb32fcbec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308095246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1308095246
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1256336814
Short name T855
Test name
Test status
Simulation time 14772625 ps
CPU time 0.87 seconds
Started Mar 31 12:26:24 PM PDT 24
Finished Mar 31 12:26:25 PM PDT 24
Peak memory 206152 kb
Host smart-8624e7d9-9a04-4da6-93b4-bfa0be0fc609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256336814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1256336814
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2061121465
Short name T835
Test name
Test status
Simulation time 14267985 ps
CPU time 0.91 seconds
Started Mar 31 12:26:38 PM PDT 24
Finished Mar 31 12:26:39 PM PDT 24
Peak memory 206204 kb
Host smart-9376f273-0dc2-48f4-8374-9cb5f81f3dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061121465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2061121465
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1602367120
Short name T850
Test name
Test status
Simulation time 16362805 ps
CPU time 0.88 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206152 kb
Host smart-762797e1-958d-4a62-a68b-60b4c8371309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602367120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1602367120
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2901585646
Short name T874
Test name
Test status
Simulation time 25388946 ps
CPU time 0.82 seconds
Started Mar 31 12:26:31 PM PDT 24
Finished Mar 31 12:26:32 PM PDT 24
Peak memory 206168 kb
Host smart-d55615c1-a084-45a1-9ebd-e64f67c45665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901585646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2901585646
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.352889048
Short name T864
Test name
Test status
Simulation time 38005148 ps
CPU time 0.88 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206168 kb
Host smart-2a373f15-96ff-4ae4-9ba4-e67f46b424cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352889048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.352889048
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3491166741
Short name T199
Test name
Test status
Simulation time 22624985 ps
CPU time 1.27 seconds
Started Mar 31 12:26:10 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 206224 kb
Host smart-9a571313-6441-4f14-b9e9-29e55d4be42a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491166741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3491166741
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.246172452
Short name T837
Test name
Test status
Simulation time 181915798 ps
CPU time 2.97 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 206268 kb
Host smart-daddd245-b06f-4548-adf5-aed9f73baad0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246172452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.246172452
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1439454503
Short name T902
Test name
Test status
Simulation time 16494227 ps
CPU time 0.9 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 206172 kb
Host smart-226bf9bb-30ed-4b0c-ac27-2cc93eeec3f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439454503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1439454503
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3193389792
Short name T945
Test name
Test status
Simulation time 38614661 ps
CPU time 1.64 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:13 PM PDT 24
Peak memory 214576 kb
Host smart-afb0be57-8872-4441-ad69-53cc5d676a25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193389792 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3193389792
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.680492287
Short name T207
Test name
Test status
Simulation time 18766180 ps
CPU time 0.87 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 206168 kb
Host smart-e1e88e98-c9bd-4151-bb35-1c34c012a87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680492287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.680492287
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.744282113
Short name T918
Test name
Test status
Simulation time 26199888 ps
CPU time 0.83 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 206172 kb
Host smart-354b49fc-0806-4bdf-996b-7c91b680d275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744282113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.744282113
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1899857577
Short name T965
Test name
Test status
Simulation time 47552965 ps
CPU time 0.98 seconds
Started Mar 31 12:26:10 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 206312 kb
Host smart-d7bab326-f9f3-4d9a-9d9b-891d1e6df8e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899857577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1899857577
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1587269806
Short name T881
Test name
Test status
Simulation time 53700081 ps
CPU time 1.41 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 214308 kb
Host smart-027c5c6c-6af8-4972-ad81-346fdf63b96d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587269806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1587269806
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4160543065
Short name T956
Test name
Test status
Simulation time 189704092 ps
CPU time 3.96 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 206352 kb
Host smart-bafcb5ee-754f-4256-b5fb-791a5b3f3b60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160543065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4160543065
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2360556965
Short name T905
Test name
Test status
Simulation time 14184830 ps
CPU time 0.88 seconds
Started Mar 31 12:26:11 PM PDT 24
Finished Mar 31 12:26:15 PM PDT 24
Peak memory 206308 kb
Host smart-101c21c1-b608-4a60-ae04-236cdc9f9cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360556965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2360556965
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1676620737
Short name T939
Test name
Test status
Simulation time 33955731 ps
CPU time 0.87 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 206168 kb
Host smart-e48862f4-8725-48be-8dcb-bf73ecfb5c77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676620737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1676620737
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2780334441
Short name T932
Test name
Test status
Simulation time 116634527 ps
CPU time 0.79 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:08 PM PDT 24
Peak memory 206016 kb
Host smart-6f69a2ef-0582-4989-8f46-3b2449d657bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780334441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2780334441
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3166203105
Short name T951
Test name
Test status
Simulation time 11936657 ps
CPU time 0.81 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 206172 kb
Host smart-e50735e8-81f0-4e76-86dc-ec11ddb3a0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166203105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3166203105
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1078526357
Short name T949
Test name
Test status
Simulation time 25409526 ps
CPU time 0.85 seconds
Started Mar 31 12:28:37 PM PDT 24
Finished Mar 31 12:28:38 PM PDT 24
Peak memory 206172 kb
Host smart-5102028c-e212-4b87-bf69-908484db40be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078526357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1078526357
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3472791708
Short name T957
Test name
Test status
Simulation time 13371288 ps
CPU time 0.82 seconds
Started Mar 31 12:26:11 PM PDT 24
Finished Mar 31 12:26:13 PM PDT 24
Peak memory 206140 kb
Host smart-4b9dcff9-1ec7-4e14-a941-70cb9ac2287e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472791708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3472791708
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1046377596
Short name T882
Test name
Test status
Simulation time 34849283 ps
CPU time 0.79 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:03 PM PDT 24
Peak memory 205984 kb
Host smart-7a454a54-a685-447e-ae37-84727c987afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046377596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1046377596
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.669002163
Short name T896
Test name
Test status
Simulation time 27033527 ps
CPU time 0.9 seconds
Started Mar 31 12:26:39 PM PDT 24
Finished Mar 31 12:26:40 PM PDT 24
Peak memory 206116 kb
Host smart-72b25d6a-7f45-4cd4-8041-1c23a6be6db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669002163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.669002163
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4208405003
Short name T852
Test name
Test status
Simulation time 13502489 ps
CPU time 0.87 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206212 kb
Host smart-cb6d05b0-0d0e-4d8a-9c26-d41da945babb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208405003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4208405003
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3996133647
Short name T946
Test name
Test status
Simulation time 22730596 ps
CPU time 0.82 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 206132 kb
Host smart-e607031f-972e-479d-8244-4bfa9f5293dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996133647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3996133647
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.328965243
Short name T213
Test name
Test status
Simulation time 152181996 ps
CPU time 1.56 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206148 kb
Host smart-5569c30a-f66e-4a27-8e63-0bc389907c24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328965243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.328965243
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2067042358
Short name T934
Test name
Test status
Simulation time 376365682 ps
CPU time 2.92 seconds
Started Mar 31 12:26:09 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 206184 kb
Host smart-ee06a7e2-d719-486b-a10b-95b1d0306c11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067042358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2067042358
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.572270438
Short name T953
Test name
Test status
Simulation time 58401451 ps
CPU time 0.79 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 205992 kb
Host smart-0077cd1e-e095-4f12-9554-079f1d541a3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572270438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.572270438
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1774276734
Short name T893
Test name
Test status
Simulation time 40572911 ps
CPU time 1.1 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 216224 kb
Host smart-56ad6dfe-3dd1-4ef4-9eb3-17f427346881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774276734 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1774276734
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1759758506
Short name T206
Test name
Test status
Simulation time 19075873 ps
CPU time 0.79 seconds
Started Mar 31 12:25:56 PM PDT 24
Finished Mar 31 12:25:57 PM PDT 24
Peak memory 205996 kb
Host smart-29619a20-bebf-4b5c-9334-465c3f7636fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759758506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1759758506
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3185771333
Short name T861
Test name
Test status
Simulation time 34475454 ps
CPU time 0.75 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 205964 kb
Host smart-5e8e404f-5c1c-46bd-8b7b-bdcff01e2876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185771333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3185771333
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3417730819
Short name T960
Test name
Test status
Simulation time 87043600 ps
CPU time 0.86 seconds
Started Mar 31 12:26:10 PM PDT 24
Finished Mar 31 12:26:15 PM PDT 24
Peak memory 206348 kb
Host smart-6de9e20c-e3f5-460b-bdb7-32bd384af6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417730819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3417730819
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1414056297
Short name T913
Test name
Test status
Simulation time 48848774 ps
CPU time 1.66 seconds
Started Mar 31 12:26:12 PM PDT 24
Finished Mar 31 12:26:16 PM PDT 24
Peak memory 214512 kb
Host smart-6a74079c-e112-47f4-b800-5b966db736fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414056297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1414056297
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.98342531
Short name T954
Test name
Test status
Simulation time 304315074 ps
CPU time 2.34 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 206180 kb
Host smart-d0cf7711-2a20-4302-8348-5b69a8f4db82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98342531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.98342531
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1688531882
Short name T868
Test name
Test status
Simulation time 21733205 ps
CPU time 0.81 seconds
Started Mar 31 12:26:09 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 206168 kb
Host smart-dbacd6d1-b7bb-46ef-aa84-d9ee4d748967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688531882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1688531882
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1782301290
Short name T914
Test name
Test status
Simulation time 12730634 ps
CPU time 0.82 seconds
Started Mar 31 12:26:10 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 206064 kb
Host smart-d6bb1f2d-8564-4e36-875c-d213b94d14ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782301290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1782301290
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.217740662
Short name T838
Test name
Test status
Simulation time 24837963 ps
CPU time 0.85 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:34 PM PDT 24
Peak memory 206196 kb
Host smart-eb197a79-bbef-40a0-ae76-a8d5ac5d5773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217740662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.217740662
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2561131909
Short name T915
Test name
Test status
Simulation time 48599449 ps
CPU time 0.84 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206164 kb
Host smart-6fad0eaf-d392-408b-a7bf-91c87f7869fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561131909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2561131909
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.843697238
Short name T937
Test name
Test status
Simulation time 15024478 ps
CPU time 0.91 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206140 kb
Host smart-a1a60173-254e-4cb4-9f3a-a5ac89438d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843697238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.843697238
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.181190044
Short name T948
Test name
Test status
Simulation time 41325448 ps
CPU time 0.81 seconds
Started Mar 31 12:26:13 PM PDT 24
Finished Mar 31 12:26:14 PM PDT 24
Peak memory 205960 kb
Host smart-b4811e40-c44f-4ee0-8ef0-aa65e5669768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181190044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.181190044
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.867462177
Short name T929
Test name
Test status
Simulation time 14190139 ps
CPU time 0.86 seconds
Started Mar 31 12:26:11 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 206260 kb
Host smart-982a7b58-7e8c-4ecc-b36d-d49e08f228f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867462177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.867462177
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1236123407
Short name T839
Test name
Test status
Simulation time 46966859 ps
CPU time 0.86 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206140 kb
Host smart-71c358f1-d1ee-4f89-a725-8cb8171973b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236123407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1236123407
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2421286881
Short name T936
Test name
Test status
Simulation time 28865740 ps
CPU time 0.74 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 205940 kb
Host smart-8aa68843-decf-43d8-9906-1df4c6e0e72b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421286881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2421286881
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1327123485
Short name T911
Test name
Test status
Simulation time 20842598 ps
CPU time 0.79 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 205984 kb
Host smart-4b64c48f-c61d-42ca-98c5-f516ff115cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327123485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1327123485
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3983304522
Short name T930
Test name
Test status
Simulation time 34164616 ps
CPU time 1.26 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 214596 kb
Host smart-964808c6-ec81-4dd3-97ab-14f7a392d533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983304522 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3983304522
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2235208542
Short name T209
Test name
Test status
Simulation time 27648034 ps
CPU time 0.76 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:17 PM PDT 24
Peak memory 205980 kb
Host smart-ddf8a4ab-058d-43bb-9ad1-22da58c7b278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235208542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2235208542
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3932708240
Short name T888
Test name
Test status
Simulation time 16189693 ps
CPU time 0.79 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 206176 kb
Host smart-a864cf59-0636-471b-b5b6-9936aa668ea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932708240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3932708240
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1568811647
Short name T204
Test name
Test status
Simulation time 73380531 ps
CPU time 1.41 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:17 PM PDT 24
Peak memory 206276 kb
Host smart-3ae5de5b-b3e6-497b-94aa-baa7cb5dbe73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568811647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1568811647
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2763072095
Short name T867
Test name
Test status
Simulation time 873194151 ps
CPU time 1.85 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 214520 kb
Host smart-0889b4a6-9887-43ec-a13b-17926f986433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763072095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2763072095
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2436635931
Short name T227
Test name
Test status
Simulation time 133136619 ps
CPU time 1.32 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206328 kb
Host smart-77132c9f-6796-4a2f-a5f7-700038ecc91c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436635931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2436635931
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1335149236
Short name T845
Test name
Test status
Simulation time 199191741 ps
CPU time 1.26 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 214564 kb
Host smart-21feb93b-5c79-49d4-91de-db7ffdfdd84e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335149236 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1335149236
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1660781444
Short name T202
Test name
Test status
Simulation time 13900540 ps
CPU time 0.91 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206140 kb
Host smart-1021afc3-8a30-481e-ab3a-d6ffed96a651
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660781444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1660781444
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.285767664
Short name T849
Test name
Test status
Simulation time 14931379 ps
CPU time 0.84 seconds
Started Mar 31 12:26:08 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 206200 kb
Host smart-3005b8ee-fcf3-424c-97f2-fc90f023f9a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285767664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.285767664
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.940997944
Short name T916
Test name
Test status
Simulation time 477579501 ps
CPU time 1.4 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206344 kb
Host smart-9f0eb37b-3aa7-4e85-b47e-0a53c03c99e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940997944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.940997944
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2806529327
Short name T876
Test name
Test status
Simulation time 165281930 ps
CPU time 3.18 seconds
Started Mar 31 12:26:11 PM PDT 24
Finished Mar 31 12:26:17 PM PDT 24
Peak memory 214636 kb
Host smart-e9b0cb3a-630f-417f-bffb-559525fc05b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806529327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2806529327
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2826112428
Short name T225
Test name
Test status
Simulation time 188821991 ps
CPU time 2.43 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:03 PM PDT 24
Peak memory 206308 kb
Host smart-7896c36d-b9d6-4b27-8bc2-af027f58bd2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826112428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2826112428
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.888191619
Short name T928
Test name
Test status
Simulation time 81289351 ps
CPU time 1.16 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 214560 kb
Host smart-f2287fc5-2c2b-4ea8-a574-3152f9aa65cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888191619 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.888191619
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3559887735
Short name T933
Test name
Test status
Simulation time 14456580 ps
CPU time 0.91 seconds
Started Mar 31 12:26:07 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 206068 kb
Host smart-87d2297c-1ba8-42cc-960a-6503bb8473cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559887735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3559887735
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3451802247
Short name T947
Test name
Test status
Simulation time 14844681 ps
CPU time 0.87 seconds
Started Mar 31 12:26:02 PM PDT 24
Finished Mar 31 12:26:03 PM PDT 24
Peak memory 206168 kb
Host smart-c0142f4d-4190-4267-b9c0-f5dd1783b26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451802247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3451802247
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1048185445
Short name T943
Test name
Test status
Simulation time 15129921 ps
CPU time 0.97 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206372 kb
Host smart-912360de-783d-40c3-af10-44faecfe2d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048185445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1048185445
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.905547564
Short name T846
Test name
Test status
Simulation time 79080498 ps
CPU time 2.43 seconds
Started Mar 31 12:26:19 PM PDT 24
Finished Mar 31 12:26:22 PM PDT 24
Peak memory 214576 kb
Host smart-84172e59-915c-4329-9fd8-417ca5f7886c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905547564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.905547564
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2029816168
Short name T963
Test name
Test status
Simulation time 84060271 ps
CPU time 1.43 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206296 kb
Host smart-05561924-7fa3-42a6-be34-c309de9c4441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029816168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2029816168
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2542313970
Short name T895
Test name
Test status
Simulation time 108220244 ps
CPU time 1.93 seconds
Started Mar 31 12:26:09 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 214644 kb
Host smart-fcea7736-1fa0-46d1-802c-8c79bc5950a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542313970 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2542313970
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1592999957
Short name T212
Test name
Test status
Simulation time 15661185 ps
CPU time 0.96 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 206168 kb
Host smart-a4a80129-fbfa-4ebf-95c4-e873e579ea03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592999957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1592999957
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1982678656
Short name T885
Test name
Test status
Simulation time 31051403 ps
CPU time 0.76 seconds
Started Mar 31 12:28:36 PM PDT 24
Finished Mar 31 12:28:38 PM PDT 24
Peak memory 206016 kb
Host smart-434213fd-976e-4c9c-acc0-369e7bfd97fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982678656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1982678656
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1342864511
Short name T877
Test name
Test status
Simulation time 42791549 ps
CPU time 1.05 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:27 PM PDT 24
Peak memory 206416 kb
Host smart-81e41b37-9ce7-475c-a146-7df8e1d1ffa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342864511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1342864511
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.412190198
Short name T959
Test name
Test status
Simulation time 104826457 ps
CPU time 1.63 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:08 PM PDT 24
Peak memory 222668 kb
Host smart-0b7eed8f-cf36-46d3-95df-26cae76750aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412190198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.412190198
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3170164897
Short name T866
Test name
Test status
Simulation time 243429577 ps
CPU time 1.53 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:06 PM PDT 24
Peak memory 206304 kb
Host smart-cb0d9fd1-a330-46f8-8d8c-aaf0920d113d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170164897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3170164897
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1042173859
Short name T908
Test name
Test status
Simulation time 17973358 ps
CPU time 1 seconds
Started Mar 31 12:26:11 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 214548 kb
Host smart-54cde56b-e8af-46b2-827a-2807e6b4e951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042173859 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1042173859
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2777757824
Short name T856
Test name
Test status
Simulation time 16559293 ps
CPU time 0.9 seconds
Started Mar 31 12:26:06 PM PDT 24
Finished Mar 31 12:26:07 PM PDT 24
Peak memory 206152 kb
Host smart-819ffbd8-9a37-45ed-8649-c8483e9ed0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777757824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2777757824
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3731247450
Short name T200
Test name
Test status
Simulation time 61613755 ps
CPU time 0.87 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:25 PM PDT 24
Peak memory 206440 kb
Host smart-85b285cb-03e5-440c-afc9-da668d352f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731247450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3731247450
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1149225130
Short name T926
Test name
Test status
Simulation time 128179650 ps
CPU time 2.46 seconds
Started Mar 31 12:26:39 PM PDT 24
Finished Mar 31 12:26:46 PM PDT 24
Peak memory 214572 kb
Host smart-45d45519-d98d-4dbe-a93c-8af988f8b1c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149225130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1149225130
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1597071060
Short name T226
Test name
Test status
Simulation time 92655155 ps
CPU time 2.46 seconds
Started Mar 31 12:26:24 PM PDT 24
Finished Mar 31 12:26:27 PM PDT 24
Peak memory 206352 kb
Host smart-3b5b40f6-7568-491c-85f7-b447c7d4bca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597071060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1597071060
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3347942814
Short name T506
Test name
Test status
Simulation time 36079541 ps
CPU time 1.37 seconds
Started Mar 31 01:10:14 PM PDT 24
Finished Mar 31 01:10:15 PM PDT 24
Peak memory 215612 kb
Host smart-7a8b982e-aeed-4813-ab1a-c805fec9b69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347942814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3347942814
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.4242624634
Short name T329
Test name
Test status
Simulation time 23765944 ps
CPU time 0.78 seconds
Started Mar 31 01:10:10 PM PDT 24
Finished Mar 31 01:10:10 PM PDT 24
Peak memory 205668 kb
Host smart-2962d1eb-1d0e-4b71-9532-331778614e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242624634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4242624634
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3571904172
Short name T116
Test name
Test status
Simulation time 36192027 ps
CPU time 0.87 seconds
Started Mar 31 01:10:13 PM PDT 24
Finished Mar 31 01:10:14 PM PDT 24
Peak memory 215900 kb
Host smart-a59e90a8-bc4f-4ee8-a6f5-e7f2575c431d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571904172 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3571904172
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3393968187
Short name T528
Test name
Test status
Simulation time 22951453 ps
CPU time 0.97 seconds
Started Mar 31 01:10:12 PM PDT 24
Finished Mar 31 01:10:13 PM PDT 24
Peak memory 217992 kb
Host smart-d6d37234-fb85-4c01-b3fb-9fc363d4db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393968187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3393968187
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.3884952901
Short name T771
Test name
Test status
Simulation time 59410189 ps
CPU time 0.87 seconds
Started Mar 31 01:10:12 PM PDT 24
Finished Mar 31 01:10:13 PM PDT 24
Peak memory 215372 kb
Host smart-42eebf74-d014-404c-b6cb-af9bb9ebc829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884952901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3884952901
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.62991623
Short name T650
Test name
Test status
Simulation time 68661805 ps
CPU time 0.97 seconds
Started Mar 31 01:10:12 PM PDT 24
Finished Mar 31 01:10:13 PM PDT 24
Peak memory 207084 kb
Host smart-a78e03ba-2e02-433d-b7b4-2b50b4af7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62991623 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.62991623
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3557900672
Short name T20
Test name
Test status
Simulation time 233584073 ps
CPU time 4.03 seconds
Started Mar 31 01:10:11 PM PDT 24
Finished Mar 31 01:10:15 PM PDT 24
Peak memory 234488 kb
Host smart-a7c3844a-5603-4d60-9453-9c296af41402
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557900672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3557900672
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3070256494
Short name T656
Test name
Test status
Simulation time 31144151 ps
CPU time 0.98 seconds
Started Mar 31 01:10:11 PM PDT 24
Finished Mar 31 01:10:12 PM PDT 24
Peak memory 215288 kb
Host smart-4ae0bc58-829c-4ced-a11e-ee93fa6fe355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070256494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3070256494
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2128300786
Short name T586
Test name
Test status
Simulation time 22728001 ps
CPU time 1.1 seconds
Started Mar 31 01:10:13 PM PDT 24
Finished Mar 31 01:10:14 PM PDT 24
Peak memory 215260 kb
Host smart-0f0e8c8c-3565-4702-a25d-cdc26188dde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128300786 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2128300786
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1666498430
Short name T381
Test name
Test status
Simulation time 165313058235 ps
CPU time 1017.86 seconds
Started Mar 31 01:10:12 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 223840 kb
Host smart-804ea080-4aa7-49a5-80c2-c04dfba54471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666498430 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1666498430
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1207999157
Short name T735
Test name
Test status
Simulation time 29372672 ps
CPU time 0.94 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:10:20 PM PDT 24
Peak memory 206032 kb
Host smart-53f3df88-6e14-4141-953e-c1b0c8b6cb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207999157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1207999157
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.576649639
Short name T685
Test name
Test status
Simulation time 54210891 ps
CPU time 1.19 seconds
Started Mar 31 01:10:17 PM PDT 24
Finished Mar 31 01:10:19 PM PDT 24
Peak memory 216548 kb
Host smart-29b5100b-edb0-40c7-9b0d-5d33529c0e60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576649639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.576649639
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.748199627
Short name T678
Test name
Test status
Simulation time 24414896 ps
CPU time 1.24 seconds
Started Mar 31 01:10:17 PM PDT 24
Finished Mar 31 01:10:19 PM PDT 24
Peak memory 229744 kb
Host smart-359c0212-c24a-435d-9692-d0ceb4365106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748199627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.748199627
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2941371315
Short name T589
Test name
Test status
Simulation time 42923843 ps
CPU time 1.64 seconds
Started Mar 31 01:10:14 PM PDT 24
Finished Mar 31 01:10:15 PM PDT 24
Peak memory 216628 kb
Host smart-39f15c2b-f666-4374-b568-f9a10aea5c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941371315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2941371315
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3091109842
Short name T803
Test name
Test status
Simulation time 56204499 ps
CPU time 0.97 seconds
Started Mar 31 01:10:11 PM PDT 24
Finished Mar 31 01:10:12 PM PDT 24
Peak memory 207124 kb
Host smart-5adef051-8e74-4768-8045-1e9758d515fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091109842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3091109842
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3267624737
Short name T376
Test name
Test status
Simulation time 46655036 ps
CPU time 0.93 seconds
Started Mar 31 01:10:10 PM PDT 24
Finished Mar 31 01:10:11 PM PDT 24
Peak memory 215200 kb
Host smart-e54de55b-80d1-46dd-b0dd-69e69ce391ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267624737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3267624737
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1381206878
Short name T485
Test name
Test status
Simulation time 1695456482 ps
CPU time 2.45 seconds
Started Mar 31 01:10:12 PM PDT 24
Finished Mar 31 01:10:14 PM PDT 24
Peak memory 216568 kb
Host smart-981cd876-111e-47e0-a031-dbf47448a5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381206878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1381206878
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.795277865
Short name T121
Test name
Test status
Simulation time 40221717 ps
CPU time 1.12 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 215600 kb
Host smart-a456f9f2-20ee-4dc4-b51c-1a4b86144242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795277865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.795277865
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2039557402
Short name T462
Test name
Test status
Simulation time 42030775 ps
CPU time 0.85 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 206460 kb
Host smart-f6ec1629-1a97-45d8-a700-82c9ba107154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039557402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2039557402
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1676572678
Short name T112
Test name
Test status
Simulation time 21444552 ps
CPU time 0.84 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 215856 kb
Host smart-80380df4-844b-463b-b206-6dd828f33592
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676572678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1676572678
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.401193548
Short name T800
Test name
Test status
Simulation time 30439256 ps
CPU time 1.18 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 216488 kb
Host smart-a45f5245-f43e-4a2e-8344-408b991ca111
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401193548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.401193548
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2851251202
Short name T44
Test name
Test status
Simulation time 21637958 ps
CPU time 0.99 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 223116 kb
Host smart-6698eb5b-1f06-4a23-8e04-fb58b047b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851251202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2851251202
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1495570339
Short name T641
Test name
Test status
Simulation time 28673433 ps
CPU time 1.25 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:50 PM PDT 24
Peak memory 218068 kb
Host smart-13b610f5-c340-49fc-9926-5c1854426b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495570339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1495570339
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2062539239
Short name T657
Test name
Test status
Simulation time 21180841 ps
CPU time 0.93 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:50 PM PDT 24
Peak memory 215672 kb
Host smart-352f8fd3-4511-4891-bb07-65c836730afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062539239 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2062539239
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2518918565
Short name T463
Test name
Test status
Simulation time 23876827 ps
CPU time 0.93 seconds
Started Mar 31 01:10:55 PM PDT 24
Finished Mar 31 01:10:56 PM PDT 24
Peak memory 215316 kb
Host smart-fcb5f1ff-51a5-4c55-a09f-7565587b3628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518918565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2518918565
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1302226905
Short name T418
Test name
Test status
Simulation time 301937062 ps
CPU time 6.01 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:56 PM PDT 24
Peak memory 217740 kb
Host smart-095ce3ba-6ac2-4303-a9d9-373b1415c5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302226905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1302226905
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1565630633
Short name T352
Test name
Test status
Simulation time 25177544899 ps
CPU time 634.49 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:21:25 PM PDT 24
Peak memory 216824 kb
Host smart-4efebd67-aeae-405e-b33b-f2e0790488f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565630633 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1565630633
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2814460291
Short name T505
Test name
Test status
Simulation time 75262077 ps
CPU time 1.13 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 218888 kb
Host smart-95dde6e9-c73f-4dc8-a6b7-1774606f9678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814460291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2814460291
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.4013546172
Short name T741
Test name
Test status
Simulation time 47649680 ps
CPU time 1.46 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 217876 kb
Host smart-c44a401a-bd37-42b9-bf4e-5a57bb73de88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013546172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4013546172
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2487074094
Short name T828
Test name
Test status
Simulation time 74382493 ps
CPU time 1.37 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217892 kb
Host smart-d4a45c54-2455-4c90-b537-6a19f862229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487074094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2487074094
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3376908779
Short name T822
Test name
Test status
Simulation time 165193249 ps
CPU time 2.27 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 217144 kb
Host smart-e4a2ceb8-0f72-4d71-a861-856e4b137a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376908779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3376908779
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2118601265
Short name T510
Test name
Test status
Simulation time 45830050 ps
CPU time 1.71 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 217688 kb
Host smart-6da87dd1-94d6-46af-bc41-f17fb3950f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118601265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2118601265
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1399689373
Short name T456
Test name
Test status
Simulation time 43374410 ps
CPU time 1.18 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 218000 kb
Host smart-d93c3d27-42d2-44b0-8c19-1530e546ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399689373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1399689373
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3861433565
Short name T805
Test name
Test status
Simulation time 47566562 ps
CPU time 1.16 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:56 PM PDT 24
Peak memory 218032 kb
Host smart-45da6555-dbf5-4125-be8b-f4baf7ada91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861433565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3861433565
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1807587115
Short name T350
Test name
Test status
Simulation time 64445224 ps
CPU time 1.05 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 216584 kb
Host smart-c47f88e1-311a-42b8-b838-fab3d3831a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807587115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1807587115
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1131545147
Short name T33
Test name
Test status
Simulation time 26808882 ps
CPU time 1.23 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 216480 kb
Host smart-df6c8e1c-dd4e-4c0b-a58e-0e0294defa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131545147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1131545147
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3936031463
Short name T258
Test name
Test status
Simulation time 58552700 ps
CPU time 1.93 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 217864 kb
Host smart-a124f25c-8cc5-46b8-a1c0-096c31906661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936031463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3936031463
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.552676714
Short name T825
Test name
Test status
Simulation time 43730527 ps
CPU time 0.87 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 206844 kb
Host smart-a6293971-ad58-4ae9-b37a-bb2e6a9c4510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552676714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.552676714
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2343131138
Short name T612
Test name
Test status
Simulation time 13564026 ps
CPU time 0.91 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:10:57 PM PDT 24
Peak memory 216036 kb
Host smart-9451c997-257e-4224-838f-d2c4d2c90713
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343131138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2343131138
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1369493157
Short name T388
Test name
Test status
Simulation time 31419188 ps
CPU time 1.12 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 218976 kb
Host smart-60383852-302f-44aa-b831-c2460360979c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369493157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1369493157
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.4115908764
Short name T772
Test name
Test status
Simulation time 24202838 ps
CPU time 0.94 seconds
Started Mar 31 01:10:55 PM PDT 24
Finished Mar 31 01:10:57 PM PDT 24
Peak memory 217888 kb
Host smart-6ef4f954-72d5-4b28-afdd-be6b69868cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115908764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4115908764
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3877470705
Short name T516
Test name
Test status
Simulation time 193223613 ps
CPU time 3.13 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:11:01 PM PDT 24
Peak memory 219368 kb
Host smart-160cabf1-c732-4d70-8a81-4fa0c692ddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877470705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3877470705
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.2431344568
Short name T306
Test name
Test status
Simulation time 23672769 ps
CPU time 0.94 seconds
Started Mar 31 01:11:00 PM PDT 24
Finished Mar 31 01:11:01 PM PDT 24
Peak memory 215284 kb
Host smart-1a44144c-0a8b-4a0a-90cd-59ffc4c9ffbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431344568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2431344568
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1017176029
Short name T747
Test name
Test status
Simulation time 115740919 ps
CPU time 2.23 seconds
Started Mar 31 01:10:58 PM PDT 24
Finished Mar 31 01:11:00 PM PDT 24
Peak memory 216776 kb
Host smart-cda38dd3-2808-4ab8-9f11-a5f4246f6180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017176029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1017176029
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3813155527
Short name T790
Test name
Test status
Simulation time 106124672915 ps
CPU time 2372.62 seconds
Started Mar 31 01:10:55 PM PDT 24
Finished Mar 31 01:50:28 PM PDT 24
Peak memory 227772 kb
Host smart-26900273-cc74-4d1b-a013-08e4905b6ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813155527 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3813155527
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.83265683
Short name T34
Test name
Test status
Simulation time 76580013 ps
CPU time 1.36 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 218152 kb
Host smart-c478eb47-bd67-4fc8-acf8-2d2fc35064b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83265683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.83265683
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2582114123
Short name T297
Test name
Test status
Simulation time 101608242 ps
CPU time 1.03 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 216836 kb
Host smart-28ed9416-027e-4fb3-90e0-79f04e7b00a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582114123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2582114123
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3339954179
Short name T832
Test name
Test status
Simulation time 137672523 ps
CPU time 3.27 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218384 kb
Host smart-598eb81e-b7c9-43bd-a9fa-f50abda03bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339954179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3339954179
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2669533345
Short name T625
Test name
Test status
Simulation time 59427152 ps
CPU time 1.37 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:56 PM PDT 24
Peak memory 216672 kb
Host smart-ececef2d-4377-4c48-9cbe-9f555178115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669533345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2669533345
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3116018718
Short name T754
Test name
Test status
Simulation time 38694962 ps
CPU time 1.44 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 217704 kb
Host smart-2907b581-f084-4b3e-a6c4-8ac68d646453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116018718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3116018718
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.607049156
Short name T573
Test name
Test status
Simulation time 63847914 ps
CPU time 1.13 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 218304 kb
Host smart-7ea5075e-aab5-4b83-8215-e07db1178874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607049156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.607049156
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3870886842
Short name T715
Test name
Test status
Simulation time 84634522 ps
CPU time 1.17 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:56 PM PDT 24
Peak memory 216632 kb
Host smart-79c4fc26-0470-4f0f-bcc1-5b947eea332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870886842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3870886842
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1242166631
Short name T379
Test name
Test status
Simulation time 37821064 ps
CPU time 1.35 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 216756 kb
Host smart-02865bfe-fa8a-463d-8c75-4804e40e1e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242166631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1242166631
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.1698221648
Short name T665
Test name
Test status
Simulation time 72423441 ps
CPU time 0.83 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:10:57 PM PDT 24
Peak memory 206676 kb
Host smart-8ac810b3-aa54-41bf-a75c-a99eb7e13727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698221648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1698221648
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2583974569
Short name T466
Test name
Test status
Simulation time 12421012 ps
CPU time 0.9 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 215644 kb
Host smart-9b058bd8-cb2c-4d7b-b5e2-35246cbf0c57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583974569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2583974569
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.3820161222
Short name T93
Test name
Test status
Simulation time 18831293 ps
CPU time 1.05 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 217892 kb
Host smart-f45a5a61-ca15-4f90-b46c-85ce1e511ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820161222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3820161222
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.4249441310
Short name T718
Test name
Test status
Simulation time 37098955 ps
CPU time 0.96 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 232348 kb
Host smart-9491c564-da5c-4baf-8e5c-466f058118c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249441310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4249441310
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2138456576
Short name T568
Test name
Test status
Simulation time 18681376 ps
CPU time 1.04 seconds
Started Mar 31 01:10:58 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 215304 kb
Host smart-0f7d612e-d591-4ca9-b800-7229edbac74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138456576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2138456576
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3560980506
Short name T491
Test name
Test status
Simulation time 216245734 ps
CPU time 1.5 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 216696 kb
Host smart-9b573b64-8195-4bc8-aebb-a2f47efc0670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560980506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3560980506
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.794703064
Short name T753
Test name
Test status
Simulation time 163491526451 ps
CPU time 587.42 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:20:44 PM PDT 24
Peak memory 223552 kb
Host smart-01ae37c9-ddd6-479f-8993-e0c6be728667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794703064 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.794703064
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.23419637
Short name T637
Test name
Test status
Simulation time 54496828 ps
CPU time 1.24 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 217724 kb
Host smart-cae77ec3-9a6e-4842-ae4d-3cc5b23d37d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23419637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.23419637
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3626182577
Short name T564
Test name
Test status
Simulation time 85984615 ps
CPU time 1.44 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 217724 kb
Host smart-dd7d3339-7257-4f61-93b8-45e396a526d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626182577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3626182577
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3968143554
Short name T762
Test name
Test status
Simulation time 64864210 ps
CPU time 1.42 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218060 kb
Host smart-74d3c8de-4bb9-4bc4-ad66-4a9bf6b74bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968143554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3968143554
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2344602325
Short name T327
Test name
Test status
Simulation time 38836375 ps
CPU time 1.5 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 217936 kb
Host smart-0fb790b6-0dd5-4fb0-8afa-534c0efc6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344602325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2344602325
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1664770217
Short name T497
Test name
Test status
Simulation time 72910272 ps
CPU time 1.38 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218100 kb
Host smart-f197d779-f7ff-416f-bf43-11e836198b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664770217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1664770217
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.665400304
Short name T374
Test name
Test status
Simulation time 136368810 ps
CPU time 2.73 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217944 kb
Host smart-dc199d5f-f58b-4ab6-ac75-5aef0ecf5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665400304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.665400304
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.4206323547
Short name T348
Test name
Test status
Simulation time 78913150 ps
CPU time 1.22 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218508 kb
Host smart-fea53941-ce87-4d18-a817-ba3b1236a810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206323547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4206323547
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2196504012
Short name T424
Test name
Test status
Simulation time 43163750 ps
CPU time 1.2 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 219096 kb
Host smart-c7b6b2d8-fa28-4e2e-abe4-34897bc28b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196504012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2196504012
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.167049238
Short name T571
Test name
Test status
Simulation time 55453620 ps
CPU time 1.47 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 219152 kb
Host smart-91bd8584-bbbe-4872-8d13-73295c825bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167049238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.167049238
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3790219084
Short name T392
Test name
Test status
Simulation time 63323391 ps
CPU time 1.53 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217824 kb
Host smart-faf18a4c-1506-489b-a49e-14efbdbafe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790219084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3790219084
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2876798872
Short name T228
Test name
Test status
Simulation time 69965045 ps
CPU time 1.18 seconds
Started Mar 31 01:10:58 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 215628 kb
Host smart-9456099a-fa5c-4830-8e73-491ffb466638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876798872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2876798872
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1329032443
Short name T786
Test name
Test status
Simulation time 42046601 ps
CPU time 0.76 seconds
Started Mar 31 01:10:55 PM PDT 24
Finished Mar 31 01:10:56 PM PDT 24
Peak memory 205552 kb
Host smart-36332059-bcac-424a-a44e-52087d13a579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329032443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1329032443
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3714589929
Short name T460
Test name
Test status
Simulation time 12884279 ps
CPU time 0.92 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 215908 kb
Host smart-4c19eaaa-2136-46f7-92d8-0e6f6b629dea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714589929 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3714589929
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2592840728
Short name T412
Test name
Test status
Simulation time 19023540 ps
CPU time 1.06 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:58 PM PDT 24
Peak memory 217676 kb
Host smart-23b2a972-f172-4c53-9ad3-359c5139c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592840728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2592840728
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.4165696253
Short name T22
Test name
Test status
Simulation time 26503929 ps
CPU time 0.96 seconds
Started Mar 31 01:10:54 PM PDT 24
Finished Mar 31 01:10:55 PM PDT 24
Peak memory 215716 kb
Host smart-8af3f6c7-e958-4d5d-966a-d654ec52b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165696253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4165696253
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.606486614
Short name T475
Test name
Test status
Simulation time 18658628 ps
CPU time 1.05 seconds
Started Mar 31 01:11:00 PM PDT 24
Finished Mar 31 01:11:01 PM PDT 24
Peak memory 215292 kb
Host smart-a14834f2-7037-4c56-a962-7e2a76588b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606486614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.606486614
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1687069494
Short name T315
Test name
Test status
Simulation time 39876305 ps
CPU time 1.07 seconds
Started Mar 31 01:10:57 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 215200 kb
Host smart-453a25b3-b1bc-4fe4-9533-1b98d9e886b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687069494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1687069494
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3377800544
Short name T189
Test name
Test status
Simulation time 9157156621 ps
CPU time 223.82 seconds
Started Mar 31 01:10:56 PM PDT 24
Finished Mar 31 01:14:40 PM PDT 24
Peak memory 223728 kb
Host smart-5625cdb8-af3c-4949-9af7-925be14fc9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377800544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3377800544
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.637414652
Short name T628
Test name
Test status
Simulation time 81978116 ps
CPU time 1.41 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 217956 kb
Host smart-b7ea6c48-0fc7-4401-a260-ebe1d3b66342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637414652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.637414652
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2237047552
Short name T798
Test name
Test status
Simulation time 86917211 ps
CPU time 1.21 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 216988 kb
Host smart-01428092-a7fd-4455-846a-8a47ef2b0b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237047552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2237047552
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.899956669
Short name T409
Test name
Test status
Simulation time 24821810 ps
CPU time 1.18 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 216828 kb
Host smart-a22c55aa-9ec6-4bac-973b-2e1b17eb1e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899956669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.899956669
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3632107404
Short name T440
Test name
Test status
Simulation time 85329321 ps
CPU time 1.14 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 216596 kb
Host smart-3ebf96c4-3845-4b54-abaa-f9cf83a31e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632107404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3632107404
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3626881044
Short name T746
Test name
Test status
Simulation time 40333588 ps
CPU time 1.01 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 216800 kb
Host smart-8a8288ed-f648-4620-b0d5-9d201a4578af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626881044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3626881044
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.742161192
Short name T603
Test name
Test status
Simulation time 93794446 ps
CPU time 1.23 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 219376 kb
Host smart-5ef29bdd-c8d2-4230-9400-4530b605e21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742161192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.742161192
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.634521807
Short name T734
Test name
Test status
Simulation time 39979013 ps
CPU time 1.36 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218740 kb
Host smart-0635e1d0-cc4a-4c47-aeb5-fb99e7210e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634521807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.634521807
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2853163371
Short name T36
Test name
Test status
Simulation time 41048446 ps
CPU time 1.49 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218040 kb
Host smart-3afcfd76-241a-4678-9d7d-f2ff41f57790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853163371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2853163371
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1394591395
Short name T602
Test name
Test status
Simulation time 65113497 ps
CPU time 1.31 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 219160 kb
Host smart-bfb29c67-e9d5-4e0a-a9e8-de56ecd7c7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394591395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1394591395
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable.1732232501
Short name T794
Test name
Test status
Simulation time 15498252 ps
CPU time 0.87 seconds
Started Mar 31 01:11:05 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 215784 kb
Host smart-e9bda742-289d-43da-8b2d-fc365b8df660
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732232501 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1732232501
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1228006404
Short name T160
Test name
Test status
Simulation time 200183284 ps
CPU time 1.15 seconds
Started Mar 31 01:11:06 PM PDT 24
Finished Mar 31 01:11:08 PM PDT 24
Peak memory 216212 kb
Host smart-5ebc4165-cc17-4161-95e5-ad8e32dea421
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228006404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1228006404
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.584317233
Short name T785
Test name
Test status
Simulation time 19284619 ps
CPU time 1.1 seconds
Started Mar 31 01:11:02 PM PDT 24
Finished Mar 31 01:11:04 PM PDT 24
Peak memory 217828 kb
Host smart-6997748a-eb11-4b68-8203-2bc216dbfc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584317233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.584317233
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1780413473
Short name T638
Test name
Test status
Simulation time 281444586 ps
CPU time 1.18 seconds
Started Mar 31 01:11:04 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 215240 kb
Host smart-d2d28930-fbde-4cdf-af14-58a0f82adf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780413473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1780413473
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3774479227
Short name T410
Test name
Test status
Simulation time 28377928 ps
CPU time 0.97 seconds
Started Mar 31 01:11:04 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 215640 kb
Host smart-62270b45-9207-497c-a6dc-de41c1e709c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774479227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3774479227
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3734885113
Short name T298
Test name
Test status
Simulation time 20465947 ps
CPU time 1 seconds
Started Mar 31 01:11:04 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 215300 kb
Host smart-ed65f30b-b5c4-4a07-b2df-6d305f29c652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734885113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3734885113
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2678986829
Short name T39
Test name
Test status
Simulation time 112756437 ps
CPU time 2.64 seconds
Started Mar 31 01:11:09 PM PDT 24
Finished Mar 31 01:11:11 PM PDT 24
Peak memory 215352 kb
Host smart-f1a9fc43-7db0-45d2-b962-d866100cf441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678986829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2678986829
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_genbits.4271165789
Short name T727
Test name
Test status
Simulation time 69705617 ps
CPU time 1.34 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218056 kb
Host smart-a33c6963-9294-4be1-83b2-a2846b2f359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271165789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4271165789
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2832784305
Short name T335
Test name
Test status
Simulation time 102947855 ps
CPU time 0.88 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 216460 kb
Host smart-36bee819-b4e3-4b47-8e68-72e075b92f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832784305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2832784305
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1436424921
Short name T681
Test name
Test status
Simulation time 24379879959 ps
CPU time 230.22 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:16:51 PM PDT 24
Peak memory 217988 kb
Host smart-fbb94e30-0a2b-4447-ad4a-0e84a19da165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436424921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1436424921
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3739269192
Short name T302
Test name
Test status
Simulation time 67490565 ps
CPU time 1.1 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 217916 kb
Host smart-d6b80835-5b8e-4c48-93bf-e3f5b9809273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739269192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3739269192
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1804886669
Short name T826
Test name
Test status
Simulation time 43870648 ps
CPU time 1.45 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217880 kb
Host smart-483153e3-321e-40af-a670-80413ee1b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804886669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1804886669
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.735847431
Short name T290
Test name
Test status
Simulation time 80271764 ps
CPU time 1.25 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 218112 kb
Host smart-2841df0f-5e41-409a-bf22-a2f4d584ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735847431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.735847431
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1928912289
Short name T639
Test name
Test status
Simulation time 91516000 ps
CPU time 1.19 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 218660 kb
Host smart-63f8d447-39b1-4af9-9019-37577c6b3172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928912289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1928912289
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3610805726
Short name T372
Test name
Test status
Simulation time 49151425 ps
CPU time 1.73 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 217752 kb
Host smart-93855d2f-83cf-4dc5-b3a8-d274fe7401ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610805726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3610805726
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1757949945
Short name T569
Test name
Test status
Simulation time 240262791 ps
CPU time 1.06 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 216520 kb
Host smart-63bcee87-cbe9-4e8e-912b-c358c8455c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757949945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1757949945
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1014544188
Short name T230
Test name
Test status
Simulation time 42730159 ps
CPU time 1.15 seconds
Started Mar 31 01:11:06 PM PDT 24
Finished Mar 31 01:11:08 PM PDT 24
Peak memory 215612 kb
Host smart-a279a861-7f8f-44d7-9d79-7ba6f4d580e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014544188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1014544188
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3187476634
Short name T655
Test name
Test status
Simulation time 15301978 ps
CPU time 0.97 seconds
Started Mar 31 01:11:04 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 205908 kb
Host smart-db502a25-b422-4b9a-9300-203e529a086c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187476634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3187476634
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2567426405
Short name T154
Test name
Test status
Simulation time 14812334 ps
CPU time 0.97 seconds
Started Mar 31 01:11:05 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 216032 kb
Host smart-bcf41eab-7920-4381-948e-349b8cbc0d0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567426405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2567426405
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4014004077
Short name T57
Test name
Test status
Simulation time 44936227 ps
CPU time 1.39 seconds
Started Mar 31 01:11:02 PM PDT 24
Finished Mar 31 01:11:04 PM PDT 24
Peak memory 216520 kb
Host smart-1509ad15-6729-4b3a-aaf3-71cc5670d578
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014004077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4014004077
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.395433111
Short name T566
Test name
Test status
Simulation time 54040380 ps
CPU time 1.03 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:04 PM PDT 24
Peak memory 220112 kb
Host smart-a443a639-146a-4ff6-85bc-d4f7ddc3ad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395433111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.395433111
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1947270276
Short name T827
Test name
Test status
Simulation time 51364543 ps
CPU time 1.56 seconds
Started Mar 31 01:11:05 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 216556 kb
Host smart-5eab5453-ae6e-43fa-9162-6fbd88c32bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947270276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1947270276
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3402319792
Short name T65
Test name
Test status
Simulation time 27275578 ps
CPU time 0.96 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:04 PM PDT 24
Peak memory 215408 kb
Host smart-1f074a61-3d13-4e4a-9810-88dee8a62f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402319792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3402319792
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3669015336
Short name T52
Test name
Test status
Simulation time 17238345 ps
CPU time 1.03 seconds
Started Mar 31 01:11:05 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 215248 kb
Host smart-52a46c2c-fa04-4639-bf84-45dbfb98f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669015336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3669015336
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.35205221
Short name T196
Test name
Test status
Simulation time 236861995 ps
CPU time 4.81 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:08 PM PDT 24
Peak memory 216436 kb
Host smart-09588306-b266-441e-b853-2f949a8911d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35205221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.35205221
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2265566499
Short name T256
Test name
Test status
Simulation time 71211058773 ps
CPU time 480.94 seconds
Started Mar 31 01:11:02 PM PDT 24
Finished Mar 31 01:19:03 PM PDT 24
Peak memory 221376 kb
Host smart-7535d05e-d602-4fe6-90ca-876e51a65fdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265566499 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2265566499
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2328621804
Short name T444
Test name
Test status
Simulation time 73073676 ps
CPU time 1.54 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 218260 kb
Host smart-cd3519ff-8228-4ee8-a468-9555a11e3ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328621804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2328621804
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1538621219
Short name T694
Test name
Test status
Simulation time 97300558 ps
CPU time 2.22 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217872 kb
Host smart-f67e3ab7-387e-463e-b1ac-db6ea0d8a52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538621219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1538621219
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2474536890
Short name T519
Test name
Test status
Simulation time 33905772 ps
CPU time 1.41 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218836 kb
Host smart-63cf8232-1fd9-4d89-9c7b-c542a4f29dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474536890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2474536890
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3338488565
Short name T35
Test name
Test status
Simulation time 76103397 ps
CPU time 1.1 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 215360 kb
Host smart-b350c554-15d6-423a-b0c0-f5798164558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338488565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3338488565
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2054517026
Short name T594
Test name
Test status
Simulation time 85345412 ps
CPU time 1.07 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 218212 kb
Host smart-53525f20-b14d-446c-a16f-70b4e6a337c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054517026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2054517026
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.829527637
Short name T721
Test name
Test status
Simulation time 152353563 ps
CPU time 3.03 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 217900 kb
Host smart-8f1786a0-5a85-468c-a38c-387e013a2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829527637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.829527637
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3974083018
Short name T652
Test name
Test status
Simulation time 177678091 ps
CPU time 1.2 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 218916 kb
Host smart-080e3ea7-6609-4623-b03f-66dda9305d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974083018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3974083018
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3726698678
Short name T287
Test name
Test status
Simulation time 95003002 ps
CPU time 1.15 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 219536 kb
Host smart-00b697a6-1394-45b1-aab6-7d2dfd1bce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726698678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3726698678
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3607995920
Short name T768
Test name
Test status
Simulation time 44238440 ps
CPU time 1.18 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 216472 kb
Host smart-00b19258-70e7-4b63-b6e3-95bbbb8357a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607995920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3607995920
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2119184508
Short name T403
Test name
Test status
Simulation time 31765842 ps
CPU time 1.36 seconds
Started Mar 31 01:13:05 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 217824 kb
Host smart-be0d6a9d-171e-4181-b9ca-c59f9e01a52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119184508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2119184508
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.1479990262
Short name T669
Test name
Test status
Simulation time 18208440 ps
CPU time 0.95 seconds
Started Mar 31 01:11:09 PM PDT 24
Finished Mar 31 01:11:10 PM PDT 24
Peak memory 206540 kb
Host smart-0c76d6c1-bddd-4b76-9913-83351447a9bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479990262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1479990262
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.390079680
Short name T624
Test name
Test status
Simulation time 29670969 ps
CPU time 0.83 seconds
Started Mar 31 01:11:04 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 215788 kb
Host smart-d78071c0-6c35-4d3f-8311-c88dd3ac3329
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390079680 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.390079680
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.2645050308
Short name T74
Test name
Test status
Simulation time 24471678 ps
CPU time 1.4 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 229704 kb
Host smart-c0f64b2f-2aa3-4d5e-82f1-ff79c97cd12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645050308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2645050308
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3329276421
Short name T308
Test name
Test status
Simulation time 41850994 ps
CPU time 1.67 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 216900 kb
Host smart-7b77d3ce-15fb-4232-b720-a344f75998fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329276421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3329276421
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2842457200
Short name T801
Test name
Test status
Simulation time 30754461 ps
CPU time 0.91 seconds
Started Mar 31 01:11:07 PM PDT 24
Finished Mar 31 01:11:09 PM PDT 24
Peak memory 215492 kb
Host smart-53c86637-d938-4b4e-8c11-40d51b00154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842457200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2842457200
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.390238172
Short name T702
Test name
Test status
Simulation time 38206943 ps
CPU time 0.96 seconds
Started Mar 31 01:11:05 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 215156 kb
Host smart-32e12cb2-c322-4432-be78-149de8b2b596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390238172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.390238172
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.749131450
Short name T252
Test name
Test status
Simulation time 177912286 ps
CPU time 3.91 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:11:07 PM PDT 24
Peak memory 216824 kb
Host smart-a341ee15-fa21-4aad-8bd1-45045f5f2eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749131450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.749131450
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.648724106
Short name T779
Test name
Test status
Simulation time 43410340896 ps
CPU time 600.69 seconds
Started Mar 31 01:11:03 PM PDT 24
Finished Mar 31 01:21:04 PM PDT 24
Peak memory 217800 kb
Host smart-56dc6e07-48c3-49f8-8dd0-6f17fe806396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648724106 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.648724106
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3613548700
Short name T492
Test name
Test status
Simulation time 68126509 ps
CPU time 1.39 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 217584 kb
Host smart-e0d7d35d-43de-483c-95f9-53e7abb9e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613548700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3613548700
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.903185512
Short name T428
Test name
Test status
Simulation time 118880204 ps
CPU time 1.68 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 217036 kb
Host smart-62b03341-28eb-4507-9f7b-77a118c2a07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903185512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.903185512
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.4197440884
Short name T607
Test name
Test status
Simulation time 66416082 ps
CPU time 1.3 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217812 kb
Host smart-eae506f4-9249-40f5-9fe3-33fa18163b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197440884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4197440884
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.984340061
Short name T389
Test name
Test status
Simulation time 206941180 ps
CPU time 1.26 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 216752 kb
Host smart-1f7f3948-6c9f-4c9f-aaca-9dac9818fa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984340061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.984340061
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1412294513
Short name T490
Test name
Test status
Simulation time 107008910 ps
CPU time 1.15 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 219264 kb
Host smart-622bb3a8-1294-4073-b06f-f15f936daecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412294513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1412294513
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3989590118
Short name T719
Test name
Test status
Simulation time 36102386 ps
CPU time 1.54 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 216496 kb
Host smart-601203d9-87f1-41ea-ac1d-e788cdfa2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989590118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3989590118
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.1718305852
Short name T2
Test name
Test status
Simulation time 53726393 ps
CPU time 1.36 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 218088 kb
Host smart-2b4f22c5-2faa-45b0-b6e3-a17ed3e32ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718305852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1718305852
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3101758805
Short name T458
Test name
Test status
Simulation time 50285411 ps
CPU time 1.39 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 217656 kb
Host smart-15778356-7dc1-495a-9660-fe65e00ca289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101758805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3101758805
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1106649047
Short name T385
Test name
Test status
Simulation time 37550144 ps
CPU time 1.43 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 218752 kb
Host smart-c503391d-dc72-400a-b706-ac329ad6e868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106649047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1106649047
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3551464670
Short name T748
Test name
Test status
Simulation time 45861839 ps
CPU time 1.62 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 219580 kb
Host smart-4c9e6918-2ff9-4660-9182-cf1776d2f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551464670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3551464670
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3969785197
Short name T279
Test name
Test status
Simulation time 71534929 ps
CPU time 1.14 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:12 PM PDT 24
Peak memory 215584 kb
Host smart-48156fe2-0945-461b-8d4c-764addc22c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969785197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3969785197
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1055555876
Short name T324
Test name
Test status
Simulation time 20979742 ps
CPU time 1 seconds
Started Mar 31 01:11:13 PM PDT 24
Finished Mar 31 01:11:15 PM PDT 24
Peak memory 206076 kb
Host smart-0fdfd8f9-ed97-445d-a406-90d3be5119fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055555876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1055555876
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3639560915
Short name T769
Test name
Test status
Simulation time 16662784 ps
CPU time 0.83 seconds
Started Mar 31 01:11:10 PM PDT 24
Finished Mar 31 01:11:11 PM PDT 24
Peak memory 215376 kb
Host smart-08797602-7d62-44e5-b862-28ef09f04e78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639560915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3639560915
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3637950515
Short name T511
Test name
Test status
Simulation time 43438375 ps
CPU time 1.04 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:12 PM PDT 24
Peak memory 217884 kb
Host smart-cdad6f55-47fe-4789-9f45-90b2efc76312
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637950515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3637950515
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.370458155
Short name T60
Test name
Test status
Simulation time 32427598 ps
CPU time 0.86 seconds
Started Mar 31 01:11:15 PM PDT 24
Finished Mar 31 01:11:16 PM PDT 24
Peak memory 217676 kb
Host smart-0ae6fe77-d0c7-46a9-a39f-5a3e7f78d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370458155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.370458155
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3649443892
Short name T647
Test name
Test status
Simulation time 32517606 ps
CPU time 1.42 seconds
Started Mar 31 01:11:14 PM PDT 24
Finished Mar 31 01:11:16 PM PDT 24
Peak memory 216880 kb
Host smart-12eb1f9a-aba9-4c23-83f4-52352aa87b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649443892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3649443892
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1433687847
Short name T139
Test name
Test status
Simulation time 22474808 ps
CPU time 0.98 seconds
Started Mar 31 01:11:08 PM PDT 24
Finished Mar 31 01:11:09 PM PDT 24
Peak memory 215672 kb
Host smart-9ff0eb50-ca8b-499f-b3e4-1710b4ed7e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433687847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1433687847
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3119404810
Short name T436
Test name
Test status
Simulation time 19190841 ps
CPU time 1.03 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:12 PM PDT 24
Peak memory 215352 kb
Host smart-db81d22b-5845-449c-bd8f-b6dd2f846d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119404810 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3119404810
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4082304473
Short name T791
Test name
Test status
Simulation time 118829777 ps
CPU time 1.94 seconds
Started Mar 31 01:11:15 PM PDT 24
Finished Mar 31 01:11:17 PM PDT 24
Peak memory 216512 kb
Host smart-4ed78c90-acf2-434a-8de3-62af9cbd1eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082304473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4082304473
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.988472288
Short name T367
Test name
Test status
Simulation time 48165715328 ps
CPU time 721.32 seconds
Started Mar 31 01:11:14 PM PDT 24
Finished Mar 31 01:23:16 PM PDT 24
Peak memory 218888 kb
Host smart-0145e367-278c-481e-82b4-6cd9df2334fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988472288 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.988472288
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4066615169
Short name T823
Test name
Test status
Simulation time 100844616 ps
CPU time 1.22 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 216760 kb
Host smart-d58dedb8-b33c-49dd-aa38-8580d2b835af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066615169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4066615169
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2449151469
Short name T448
Test name
Test status
Simulation time 63049608 ps
CPU time 1.59 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 218356 kb
Host smart-122f2c21-96ec-441f-8687-e7fb6588b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449151469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2449151469
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2336955480
Short name T774
Test name
Test status
Simulation time 31156051 ps
CPU time 1.07 seconds
Started Mar 31 01:12:58 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217916 kb
Host smart-5f3e5ea3-4278-429a-8c7e-baa8fc8b80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336955480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2336955480
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.947530952
Short name T322
Test name
Test status
Simulation time 51701879 ps
CPU time 1.9 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 216740 kb
Host smart-809e96fc-1c1c-412c-9f3b-243c5c3b35d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947530952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.947530952
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1812615544
Short name T457
Test name
Test status
Simulation time 68387681 ps
CPU time 1.26 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 218036 kb
Host smart-1d0ce372-b104-476e-8545-539a2384d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812615544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1812615544
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1425196039
Short name T632
Test name
Test status
Simulation time 65617425 ps
CPU time 1.13 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 216612 kb
Host smart-70835f61-ecf8-4ab2-9668-cfc3011ae828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425196039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1425196039
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1666248333
Short name T427
Test name
Test status
Simulation time 48038694 ps
CPU time 1.65 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 218088 kb
Host smart-bbbf5a44-f023-4c71-baf0-a3130ff0ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666248333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1666248333
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1758005245
Short name T260
Test name
Test status
Simulation time 26738746 ps
CPU time 1.22 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 216952 kb
Host smart-8fe42917-7a1e-4db0-9780-4ecbc74987b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758005245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1758005245
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3676347032
Short name T398
Test name
Test status
Simulation time 81188136 ps
CPU time 1.51 seconds
Started Mar 31 01:13:05 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 216608 kb
Host smart-ceb780e4-61e8-4b30-b1d0-b69c4f5efb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676347032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3676347032
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1281360932
Short name T104
Test name
Test status
Simulation time 55219452 ps
CPU time 1.23 seconds
Started Mar 31 01:11:13 PM PDT 24
Finished Mar 31 01:11:15 PM PDT 24
Peak memory 215664 kb
Host smart-a8d40ff8-6177-4f87-a905-3626850c056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281360932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1281360932
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1208294492
Short name T621
Test name
Test status
Simulation time 15898988 ps
CPU time 0.9 seconds
Started Mar 31 01:11:15 PM PDT 24
Finished Mar 31 01:11:16 PM PDT 24
Peak memory 206760 kb
Host smart-dae10199-74bf-487c-81e3-7398ca633b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208294492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1208294492
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2752052934
Short name T38
Test name
Test status
Simulation time 117165568 ps
CPU time 1.14 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:14 PM PDT 24
Peak memory 217936 kb
Host smart-e0af4b39-0f3b-46e4-9152-102ab31d2b1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752052934 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2752052934
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2333964039
Short name T382
Test name
Test status
Simulation time 19933538 ps
CPU time 1.03 seconds
Started Mar 31 01:11:10 PM PDT 24
Finished Mar 31 01:11:11 PM PDT 24
Peak memory 217808 kb
Host smart-0698d996-97b3-4df4-ab90-f9e0ff1547d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333964039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2333964039
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2241244711
Short name T795
Test name
Test status
Simulation time 114522845 ps
CPU time 1.34 seconds
Started Mar 31 01:11:13 PM PDT 24
Finished Mar 31 01:11:15 PM PDT 24
Peak memory 219456 kb
Host smart-c82b47c9-1ab6-447d-87a4-3b6d884641bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241244711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2241244711
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.976421519
Short name T320
Test name
Test status
Simulation time 91972470 ps
CPU time 0.84 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:12 PM PDT 24
Peak memory 215348 kb
Host smart-c23befc0-6dbf-434e-8a67-30aef5cf0405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976421519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.976421519
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.314341399
Short name T574
Test name
Test status
Simulation time 26037533 ps
CPU time 1.02 seconds
Started Mar 31 01:11:12 PM PDT 24
Finished Mar 31 01:11:14 PM PDT 24
Peak memory 215260 kb
Host smart-c12f8b48-9683-46bf-99ae-2340ffe57f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314341399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.314341399
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1883862340
Short name T814
Test name
Test status
Simulation time 274918135 ps
CPU time 1.99 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:13 PM PDT 24
Peak memory 215264 kb
Host smart-808a4e0d-a3c0-4c5b-ab79-51e620c40f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883862340 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1883862340
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_genbits.2024026940
Short name T344
Test name
Test status
Simulation time 155215118 ps
CPU time 1.09 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 215364 kb
Host smart-f3d0a25d-a541-4e6d-8448-d4f1f0dae2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024026940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2024026940
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2582031491
Short name T311
Test name
Test status
Simulation time 91860355 ps
CPU time 1.55 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 217996 kb
Host smart-35c8a9d6-50b9-4813-beb6-a56d0cbeff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582031491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2582031491
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.4177378425
Short name T759
Test name
Test status
Simulation time 133771303 ps
CPU time 3.27 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 219376 kb
Host smart-a78ac02b-6ba5-4b3e-9d4b-3fbd312a401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177378425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.4177378425
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1417752372
Short name T404
Test name
Test status
Simulation time 91817069 ps
CPU time 1.55 seconds
Started Mar 31 01:12:59 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 217812 kb
Host smart-e5ed1ebb-6b55-4d01-afbd-94cb19c8b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417752372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1417752372
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1094911305
Short name T447
Test name
Test status
Simulation time 241601737 ps
CPU time 1.77 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 218288 kb
Host smart-f2e00769-6c1e-4d2b-b062-9daced2e4c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094911305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1094911305
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2775816200
Short name T636
Test name
Test status
Simulation time 162046410 ps
CPU time 1.29 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 216972 kb
Host smart-519279ff-4278-4c70-9723-e0e131013838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775816200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2775816200
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2825537336
Short name T454
Test name
Test status
Simulation time 40325045 ps
CPU time 1.54 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 217896 kb
Host smart-3c2fb5ea-4a3f-483a-bdcf-2b90975a8145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825537336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2825537336
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.205765007
Short name T559
Test name
Test status
Simulation time 121060685 ps
CPU time 1.61 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 219404 kb
Host smart-dc8ad8c4-2561-4565-94ec-3ae56e7e52bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205765007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.205765007
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.386547636
Short name T675
Test name
Test status
Simulation time 101518286 ps
CPU time 1.44 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 218900 kb
Host smart-10c70bfc-cbfd-4273-8551-b10a86c48ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386547636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.386547636
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.488381973
Short name T775
Test name
Test status
Simulation time 53001791 ps
CPU time 1.19 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 215596 kb
Host smart-85c144bb-9d7b-4357-814a-a28be264e564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488381973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.488381973
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2038213561
Short name T635
Test name
Test status
Simulation time 167242938 ps
CPU time 1.12 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 206012 kb
Host smart-9c5dca29-698d-4ccc-a9ac-f3b912333a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038213561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2038213561
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3768983822
Short name T336
Test name
Test status
Simulation time 11755414 ps
CPU time 0.85 seconds
Started Mar 31 01:11:15 PM PDT 24
Finished Mar 31 01:11:16 PM PDT 24
Peak memory 215468 kb
Host smart-f388be4c-dbbb-4769-9ce9-d7f42ea88a24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768983822 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3768983822
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2822793241
Short name T556
Test name
Test status
Simulation time 41577566 ps
CPU time 1.29 seconds
Started Mar 31 01:11:17 PM PDT 24
Finished Mar 31 01:11:18 PM PDT 24
Peak memory 217728 kb
Host smart-8f28e3fe-ca57-4318-8630-730fff290988
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822793241 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2822793241
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3753057652
Short name T155
Test name
Test status
Simulation time 18633360 ps
CPU time 1.06 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:11:17 PM PDT 24
Peak memory 218112 kb
Host smart-a88096b6-97e7-411f-a313-57a963c0a80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753057652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3753057652
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1814406628
Short name T174
Test name
Test status
Simulation time 31693593 ps
CPU time 1.28 seconds
Started Mar 31 01:11:10 PM PDT 24
Finished Mar 31 01:11:11 PM PDT 24
Peak memory 216588 kb
Host smart-e993ae90-79d3-4f84-afc0-627a6297c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814406628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1814406628
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3686437865
Short name T137
Test name
Test status
Simulation time 27057498 ps
CPU time 0.99 seconds
Started Mar 31 01:11:19 PM PDT 24
Finished Mar 31 01:11:20 PM PDT 24
Peak memory 215760 kb
Host smart-f0ea41dc-c27f-4538-b96b-8b5980739531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686437865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3686437865
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1206272334
Short name T541
Test name
Test status
Simulation time 18541559 ps
CPU time 1.03 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:11:12 PM PDT 24
Peak memory 207200 kb
Host smart-e1bcf7cb-ce45-4745-a7a6-bae1e0c30c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206272334 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1206272334
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.169974744
Short name T486
Test name
Test status
Simulation time 1117785897 ps
CPU time 5.74 seconds
Started Mar 31 01:11:10 PM PDT 24
Finished Mar 31 01:11:16 PM PDT 24
Peak memory 216660 kb
Host smart-1d7f6dde-53e6-4add-9bb0-a0bfd9e724af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169974744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.169974744
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2132265342
Short name T450
Test name
Test status
Simulation time 19998563336 ps
CPU time 529.17 seconds
Started Mar 31 01:11:11 PM PDT 24
Finished Mar 31 01:20:00 PM PDT 24
Peak memory 217448 kb
Host smart-698932a0-d19c-4f3f-b516-affeed8587ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132265342 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2132265342
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1406647943
Short name T477
Test name
Test status
Simulation time 35027064 ps
CPU time 1.3 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 217792 kb
Host smart-b6ed11b7-fc80-4243-ab5a-c50315fc61ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406647943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1406647943
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.4225838564
Short name T391
Test name
Test status
Simulation time 45335716 ps
CPU time 1.64 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 219184 kb
Host smart-67c5ee3f-6dc9-4210-9877-7b9a80756bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225838564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4225838564
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3365641003
Short name T31
Test name
Test status
Simulation time 99255607 ps
CPU time 1.23 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 216588 kb
Host smart-6392dd84-5aa2-4a5a-a59c-ff9ac8e7e081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365641003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3365641003
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2561481885
Short name T527
Test name
Test status
Simulation time 97354165 ps
CPU time 2.43 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 219352 kb
Host smart-6aa28524-9f17-4996-8e5a-8a6e81d2ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561481885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2561481885
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1619218030
Short name T360
Test name
Test status
Simulation time 67905841 ps
CPU time 1.27 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 217852 kb
Host smart-7edb3cd6-ef32-486b-a43c-6704d39c9b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619218030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1619218030
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.553765764
Short name T408
Test name
Test status
Simulation time 26346966 ps
CPU time 1.17 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 217704 kb
Host smart-bf07838b-b141-415a-8f52-045137f7bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553765764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.553765764
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3311090040
Short name T423
Test name
Test status
Simulation time 60462370 ps
CPU time 1.42 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 218952 kb
Host smart-786dc496-51c0-455b-9705-e5b3c136a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311090040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3311090040
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2000653887
Short name T378
Test name
Test status
Simulation time 49660943 ps
CPU time 2 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 216640 kb
Host smart-b55d5d72-134a-450b-94f4-35bd7b7bad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000653887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2000653887
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2501566544
Short name T386
Test name
Test status
Simulation time 69507976 ps
CPU time 1.38 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 215272 kb
Host smart-79302f9e-61d8-41d5-a7e6-1c2b12e941ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501566544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2501566544
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3691788606
Short name T499
Test name
Test status
Simulation time 46946169 ps
CPU time 1.82 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 217740 kb
Host smart-00ec655f-349e-453f-b88b-01a68fc39920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691788606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3691788606
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1127409629
Short name T269
Test name
Test status
Simulation time 44053220 ps
CPU time 1.15 seconds
Started Mar 31 01:10:18 PM PDT 24
Finished Mar 31 01:10:19 PM PDT 24
Peak memory 215636 kb
Host smart-81f02c60-ee38-4f5a-923d-a271a2c98f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127409629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1127409629
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2267758171
Short name T484
Test name
Test status
Simulation time 49280186 ps
CPU time 0.88 seconds
Started Mar 31 01:10:17 PM PDT 24
Finished Mar 31 01:10:18 PM PDT 24
Peak memory 206496 kb
Host smart-5fd1c260-443a-426c-b5ca-b5b8a93feede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267758171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2267758171
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1052444215
Short name T537
Test name
Test status
Simulation time 39349679 ps
CPU time 0.83 seconds
Started Mar 31 01:10:21 PM PDT 24
Finished Mar 31 01:10:22 PM PDT 24
Peak memory 215360 kb
Host smart-52d90594-3d7c-4c0c-b297-38c0b31942d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052444215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1052444215
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.1563656484
Short name T592
Test name
Test status
Simulation time 18216920 ps
CPU time 1.14 seconds
Started Mar 31 01:10:18 PM PDT 24
Finished Mar 31 01:10:20 PM PDT 24
Peak memory 223324 kb
Host smart-e2453a44-5bcd-47bc-a6fd-0f0fa095e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563656484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1563656484
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3685488771
Short name T340
Test name
Test status
Simulation time 26895595 ps
CPU time 1.29 seconds
Started Mar 31 01:10:18 PM PDT 24
Finished Mar 31 01:10:19 PM PDT 24
Peak memory 218000 kb
Host smart-700cbd38-5625-4f91-974b-ac185446b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685488771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3685488771
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1552134491
Short name T370
Test name
Test status
Simulation time 22854777 ps
CPU time 1.09 seconds
Started Mar 31 01:10:21 PM PDT 24
Finished Mar 31 01:10:22 PM PDT 24
Peak memory 215356 kb
Host smart-feebece4-d7e4-476d-bfab-c2206077d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552134491 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1552134491
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1439126819
Short name T53
Test name
Test status
Simulation time 724849095 ps
CPU time 5.72 seconds
Started Mar 31 01:10:18 PM PDT 24
Finished Mar 31 01:10:23 PM PDT 24
Peak memory 233432 kb
Host smart-55c86748-3290-424c-9b4e-b87286079bc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439126819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1439126819
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.60446902
Short name T614
Test name
Test status
Simulation time 20398122 ps
CPU time 1 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:10:20 PM PDT 24
Peak memory 215212 kb
Host smart-dbed1383-dd4f-4ffa-8c0f-da92b958222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60446902 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.60446902
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2267750628
Short name T432
Test name
Test status
Simulation time 581814431 ps
CPU time 5.96 seconds
Started Mar 31 01:10:19 PM PDT 24
Finished Mar 31 01:10:25 PM PDT 24
Peak memory 215280 kb
Host smart-5ffcf37b-02ab-4782-8fd4-0ae086eab5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267750628 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2267750628
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2786408827
Short name T192
Test name
Test status
Simulation time 94210367322 ps
CPU time 533.56 seconds
Started Mar 31 01:10:20 PM PDT 24
Finished Mar 31 01:19:13 PM PDT 24
Peak memory 218476 kb
Host smart-c567c5dc-024b-4b31-ba0c-e8d3bed7468e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786408827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2786408827
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4059011884
Short name T173
Test name
Test status
Simulation time 68256456 ps
CPU time 1.11 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:11:17 PM PDT 24
Peak memory 215632 kb
Host smart-d8ade4cc-55da-4995-a09d-0ca16c929b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059011884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4059011884
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.4004076228
Short name T349
Test name
Test status
Simulation time 22429350 ps
CPU time 0.87 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:11:17 PM PDT 24
Peak memory 205960 kb
Host smart-034b6bf4-6ef6-49f2-afa1-1cee5d9ecacb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004076228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4004076228
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_err.3599004603
Short name T784
Test name
Test status
Simulation time 35814079 ps
CPU time 0.86 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:11:18 PM PDT 24
Peak memory 217844 kb
Host smart-469bd758-67bb-409d-94ce-e02da516bc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599004603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3599004603
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.4172823381
Short name T570
Test name
Test status
Simulation time 57792862 ps
CPU time 1.71 seconds
Started Mar 31 01:11:20 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 217808 kb
Host smart-ed4a4140-eac3-4600-8ad4-12d1253e3ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172823381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.4172823381
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3914930590
Short name T194
Test name
Test status
Simulation time 62221330 ps
CPU time 0.89 seconds
Started Mar 31 01:11:17 PM PDT 24
Finished Mar 31 01:11:18 PM PDT 24
Peak memory 215396 kb
Host smart-e44ab87e-69c1-4fe5-82c6-e6ea38b391b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914930590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3914930590
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3425620547
Short name T532
Test name
Test status
Simulation time 76780878 ps
CPU time 0.94 seconds
Started Mar 31 01:11:20 PM PDT 24
Finished Mar 31 01:11:21 PM PDT 24
Peak memory 215276 kb
Host smart-f2ee673b-8a16-4659-ba45-3431010dc13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425620547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3425620547
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1038467620
Short name T338
Test name
Test status
Simulation time 178915996 ps
CPU time 4 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:11:20 PM PDT 24
Peak memory 216636 kb
Host smart-5dff0711-f99d-4920-a043-64d39686344f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038467620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1038467620
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3464620396
Short name T802
Test name
Test status
Simulation time 173314047524 ps
CPU time 1001.65 seconds
Started Mar 31 01:11:20 PM PDT 24
Finished Mar 31 01:28:02 PM PDT 24
Peak memory 223788 kb
Host smart-b58388c0-e007-47b1-a842-759e6a627e17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464620396 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3464620396
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3116433194
Short name T708
Test name
Test status
Simulation time 149716839 ps
CPU time 2.98 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 217872 kb
Host smart-fddd0ec4-6d31-4fa2-a862-811c4409b4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116433194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3116433194
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2567001781
Short name T627
Test name
Test status
Simulation time 21303919 ps
CPU time 1.1 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 216456 kb
Host smart-ac2fdf13-fd2a-4156-96bf-01a0358f2cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567001781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2567001781
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1606884707
Short name T58
Test name
Test status
Simulation time 62034517 ps
CPU time 1.25 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 217576 kb
Host smart-b6683a83-3b89-4816-80ef-93b8718f1916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606884707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1606884707
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1987187622
Short name T812
Test name
Test status
Simulation time 67804264 ps
CPU time 1.39 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 218812 kb
Host smart-62b09d78-58f7-4309-b5b5-25aa4d93a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987187622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1987187622
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.311565295
Short name T504
Test name
Test status
Simulation time 62086254 ps
CPU time 2.02 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 218480 kb
Host smart-a04b265f-1cf7-434a-9550-d81ff44f3c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311565295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.311565295
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3947944272
Short name T554
Test name
Test status
Simulation time 55676279 ps
CPU time 1.37 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 217836 kb
Host smart-f82fbbbc-ebbc-4444-bcd9-3a2e3106ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947944272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3947944272
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2100402538
Short name T660
Test name
Test status
Simulation time 164521788 ps
CPU time 1.34 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 219464 kb
Host smart-b46d0185-0bd5-47e9-acc8-e58979b6b430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100402538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2100402538
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1133000974
Short name T787
Test name
Test status
Simulation time 39846635 ps
CPU time 1.48 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 216520 kb
Host smart-8aa33824-4fd3-4d04-8406-d6d53fd5ebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133000974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1133000974
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4283970073
Short name T364
Test name
Test status
Simulation time 406413713 ps
CPU time 4.15 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 218968 kb
Host smart-a53a4c9f-d0b9-4937-90a1-558f0a6a6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283970073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4283970073
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1088580733
Short name T371
Test name
Test status
Simulation time 44358859 ps
CPU time 1.52 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 216476 kb
Host smart-a5a451ee-470b-4d91-8519-0767407c10f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088580733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1088580733
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.2201080809
Short name T755
Test name
Test status
Simulation time 13897510 ps
CPU time 0.93 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 206788 kb
Host smart-6aa3d328-bc5b-44b0-b84d-8d40526af724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201080809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2201080809
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4052808189
Short name T113
Test name
Test status
Simulation time 15968497 ps
CPU time 0.93 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:29 PM PDT 24
Peak memory 216056 kb
Host smart-60c083ff-b59a-40fe-a2c0-8910ec4c4e12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052808189 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4052808189
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3870509249
Short name T62
Test name
Test status
Simulation time 29193835 ps
CPU time 1.06 seconds
Started Mar 31 01:11:22 PM PDT 24
Finished Mar 31 01:11:23 PM PDT 24
Peak memory 217532 kb
Host smart-ecc669e5-2166-4d85-a3f4-e511dd194747
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870509249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3870509249
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1529849025
Short name T732
Test name
Test status
Simulation time 32076577 ps
CPU time 1.23 seconds
Started Mar 31 01:11:24 PM PDT 24
Finished Mar 31 01:11:26 PM PDT 24
Peak memory 229704 kb
Host smart-c36f9e8d-6c84-4a85-bffa-65c9e2d5bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529849025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1529849025
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.380678607
Short name T540
Test name
Test status
Simulation time 54017463 ps
CPU time 1.29 seconds
Started Mar 31 01:11:15 PM PDT 24
Finished Mar 31 01:11:17 PM PDT 24
Peak memory 217576 kb
Host smart-a90ea640-98b5-4e7c-bf5e-de2e6383985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380678607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.380678607
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.442414220
Short name T14
Test name
Test status
Simulation time 22786063 ps
CPU time 1.22 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:11:18 PM PDT 24
Peak memory 224148 kb
Host smart-2e4ef5f7-758a-4c07-99ec-08b695439f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442414220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.442414220
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2013201128
Short name T375
Test name
Test status
Simulation time 17724995 ps
CPU time 1 seconds
Started Mar 31 01:11:17 PM PDT 24
Finished Mar 31 01:11:18 PM PDT 24
Peak memory 215312 kb
Host smart-3f58f005-1bbf-4ee2-88aa-1e4ece3e1371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013201128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2013201128
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2729128064
Short name T580
Test name
Test status
Simulation time 875190574 ps
CPU time 3.34 seconds
Started Mar 31 01:11:20 PM PDT 24
Finished Mar 31 01:11:24 PM PDT 24
Peak memory 216460 kb
Host smart-909b0c45-c927-48ca-8be1-a143489f35db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729128064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2729128064
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4087917451
Short name T668
Test name
Test status
Simulation time 206479659120 ps
CPU time 1228.18 seconds
Started Mar 31 01:11:16 PM PDT 24
Finished Mar 31 01:31:45 PM PDT 24
Peak memory 222740 kb
Host smart-f2c4a3e3-5f97-4053-b44d-5167e12fb54e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087917451 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4087917451
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3337441925
Short name T548
Test name
Test status
Simulation time 79385045 ps
CPU time 1.61 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 218192 kb
Host smart-fca3a0eb-289b-49b5-adde-fc0f6b1f2f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337441925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3337441925
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1335381426
Short name T496
Test name
Test status
Simulation time 248429886 ps
CPU time 0.95 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 216492 kb
Host smart-0ef6a9c7-5b74-4af2-a90b-59f5abf4190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335381426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1335381426
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.69069556
Short name T407
Test name
Test status
Simulation time 48153943 ps
CPU time 1.2 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 217936 kb
Host smart-269ab935-2ac0-4a68-abd4-c7a2dbe9c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69069556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.69069556
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2432304171
Short name T605
Test name
Test status
Simulation time 47949875 ps
CPU time 1.29 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 216720 kb
Host smart-01a2e3e2-8566-49ce-adec-6f8190d5fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432304171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2432304171
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.205463676
Short name T683
Test name
Test status
Simulation time 26293020 ps
CPU time 1.33 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 217896 kb
Host smart-7272bcc0-dbda-46a9-bcb0-0ca037fcb31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205463676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.205463676
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.468608771
Short name T236
Test name
Test status
Simulation time 61820884 ps
CPU time 1.43 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 218448 kb
Host smart-141da0c9-f095-4326-9cd6-92d7976b026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468608771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.468608771
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2524616773
Short name T425
Test name
Test status
Simulation time 41527334 ps
CPU time 1.64 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 218040 kb
Host smart-a29f7333-bff0-4345-b160-500cc9b4094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524616773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2524616773
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.212142189
Short name T325
Test name
Test status
Simulation time 48296290 ps
CPU time 1.73 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 216820 kb
Host smart-54b04bb6-182e-445c-8ebc-18a146eb8c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212142189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.212142189
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.766800467
Short name T659
Test name
Test status
Simulation time 112757289 ps
CPU time 1.86 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 219604 kb
Host smart-8ae4f6d7-bcf4-4cad-ac16-b2a6fab55038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766800467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.766800467
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.940775228
Short name T283
Test name
Test status
Simulation time 36868608 ps
CPU time 1.08 seconds
Started Mar 31 01:11:25 PM PDT 24
Finished Mar 31 01:11:26 PM PDT 24
Peak memory 215592 kb
Host smart-bb85add1-7da9-484e-81ff-0e70fba96824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940775228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.940775228
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2883397396
Short name T443
Test name
Test status
Simulation time 16934526 ps
CPU time 0.96 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:29 PM PDT 24
Peak memory 205940 kb
Host smart-512c5a25-52fe-4261-b9f5-49f97f5ec758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883397396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2883397396
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.4210631663
Short name T167
Test name
Test status
Simulation time 12974392 ps
CPU time 0.93 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 215992 kb
Host smart-75500a2a-0a55-4368-a3db-a3b1059d9ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210631663 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4210631663
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.4248184924
Short name T72
Test name
Test status
Simulation time 108803340 ps
CPU time 0.93 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:29 PM PDT 24
Peak memory 219296 kb
Host smart-9e19265b-bae6-41ec-a8c7-2c627c6f2223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248184924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4248184924
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.594117377
Short name T782
Test name
Test status
Simulation time 54807301 ps
CPU time 1.22 seconds
Started Mar 31 01:11:23 PM PDT 24
Finished Mar 31 01:11:24 PM PDT 24
Peak memory 217656 kb
Host smart-a70fbf56-a477-49a5-9090-15c2fc7cafe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594117377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.594117377
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3134458039
Short name T313
Test name
Test status
Simulation time 41245922 ps
CPU time 0.91 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 215236 kb
Host smart-7f1e9843-3a89-445f-b5c2-d8f38f24e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134458039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3134458039
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3864919420
Short name T514
Test name
Test status
Simulation time 30593233 ps
CPU time 0.99 seconds
Started Mar 31 01:11:23 PM PDT 24
Finished Mar 31 01:11:24 PM PDT 24
Peak memory 215284 kb
Host smart-31b9cf12-a322-488a-b22c-a438ff2d2746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864919420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3864919420
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2207612189
Short name T819
Test name
Test status
Simulation time 198731040 ps
CPU time 2.21 seconds
Started Mar 31 01:11:22 PM PDT 24
Finished Mar 31 01:11:24 PM PDT 24
Peak memory 218768 kb
Host smart-c8d58d46-eb39-42b0-8b70-67a50e557aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207612189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2207612189
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3854609685
Short name T693
Test name
Test status
Simulation time 147609954804 ps
CPU time 577.92 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:20:59 PM PDT 24
Peak memory 221456 kb
Host smart-151850dd-02ab-4942-8a71-135e958355ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854609685 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3854609685
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2287585012
Short name T493
Test name
Test status
Simulation time 129866902 ps
CPU time 1.63 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 218468 kb
Host smart-480a1b97-7ab2-4f70-b27e-d913cd3d6ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287585012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2287585012
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3475160761
Short name T763
Test name
Test status
Simulation time 46475575 ps
CPU time 1.6 seconds
Started Mar 31 01:13:02 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 217728 kb
Host smart-5b5ce1b9-11bb-48ac-8624-e3f71d03ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475160761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3475160761
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.307743892
Short name T778
Test name
Test status
Simulation time 112261766 ps
CPU time 1.94 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 218300 kb
Host smart-c6015fe5-25c4-4b83-a4fc-64edf6b7ede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307743892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.307743892
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2175353479
Short name T695
Test name
Test status
Simulation time 42716427 ps
CPU time 1.16 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:12 PM PDT 24
Peak memory 217872 kb
Host smart-6cae348f-b87a-4923-855a-31f8ac61dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175353479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2175353479
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.783088825
Short name T55
Test name
Test status
Simulation time 87103569 ps
CPU time 1.47 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 218100 kb
Host smart-5e6f4828-fed4-4342-afc2-1dc766d8695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783088825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.783088825
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3860742703
Short name T262
Test name
Test status
Simulation time 89509422 ps
CPU time 3.4 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 219388 kb
Host smart-28f60149-ea6e-4b4b-8876-4b84437779ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860742703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3860742703
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3887045541
Short name T294
Test name
Test status
Simulation time 21764556 ps
CPU time 1.12 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 216616 kb
Host smart-ab2aa08e-8ddc-4f90-aa48-9a20f5fa148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887045541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3887045541
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.415546755
Short name T824
Test name
Test status
Simulation time 89991682 ps
CPU time 1.36 seconds
Started Mar 31 01:13:08 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 218480 kb
Host smart-82c8a0b6-989d-4d5b-b3cd-ccbc6186e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415546755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.415546755
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3404764397
Short name T610
Test name
Test status
Simulation time 38352545 ps
CPU time 1.12 seconds
Started Mar 31 01:13:05 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 216580 kb
Host smart-2d5674e6-82dc-4acf-9441-62006f4f9da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404764397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3404764397
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3723794277
Short name T728
Test name
Test status
Simulation time 45398979 ps
CPU time 1.16 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217904 kb
Host smart-6b4e3388-8c9a-4784-b5d5-ad8ba4c7fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723794277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3723794277
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2453382548
Short name T102
Test name
Test status
Simulation time 139769557 ps
CPU time 1.2 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:23 PM PDT 24
Peak memory 215540 kb
Host smart-2fd76699-9b00-4463-8ab8-ef7cb47ceac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453382548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2453382548
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1617689030
Short name T745
Test name
Test status
Simulation time 46994132 ps
CPU time 0.91 seconds
Started Mar 31 01:11:23 PM PDT 24
Finished Mar 31 01:11:24 PM PDT 24
Peak memory 206872 kb
Host smart-de5661f5-1df2-46c7-9d3d-ddc187711a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617689030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1617689030
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2172798269
Short name T834
Test name
Test status
Simulation time 35592020 ps
CPU time 0.88 seconds
Started Mar 31 01:11:21 PM PDT 24
Finished Mar 31 01:11:22 PM PDT 24
Peak memory 215516 kb
Host smart-80d3907a-eaa7-42b6-a44e-65ccbc3d99f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172798269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2172798269
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3954746536
Short name T696
Test name
Test status
Simulation time 50208201 ps
CPU time 1.09 seconds
Started Mar 31 01:11:24 PM PDT 24
Finished Mar 31 01:11:25 PM PDT 24
Peak memory 216292 kb
Host smart-07acab5b-3eb9-40e4-a3a1-6ce6107bb104
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954746536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3954746536
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3004111192
Short name T165
Test name
Test status
Simulation time 75479712 ps
CPU time 1.14 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:29 PM PDT 24
Peak memory 219240 kb
Host smart-67a8e6ee-e0fc-42f5-b4ae-854aed3bcf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004111192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3004111192
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2998831345
Short name T263
Test name
Test status
Simulation time 141512351 ps
CPU time 2.87 seconds
Started Mar 31 01:11:23 PM PDT 24
Finished Mar 31 01:11:26 PM PDT 24
Peak memory 217988 kb
Host smart-c732adf7-2de2-45a7-bb14-25b8feb6c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998831345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2998831345
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3673248132
Short name T351
Test name
Test status
Simulation time 38883758 ps
CPU time 0.94 seconds
Started Mar 31 01:11:25 PM PDT 24
Finished Mar 31 01:11:26 PM PDT 24
Peak memory 215380 kb
Host smart-b387116e-be0a-45c9-8c5b-69a1c725f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673248132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3673248132
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.735041792
Short name T793
Test name
Test status
Simulation time 16112378 ps
CPU time 0.94 seconds
Started Mar 31 01:11:24 PM PDT 24
Finished Mar 31 01:11:25 PM PDT 24
Peak memory 215276 kb
Host smart-4cf88641-c83b-4138-b7e5-d68cad33e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735041792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.735041792
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3850585469
Short name T557
Test name
Test status
Simulation time 2270551243 ps
CPU time 4.22 seconds
Started Mar 31 01:11:22 PM PDT 24
Finished Mar 31 01:11:27 PM PDT 24
Peak memory 216928 kb
Host smart-21eb0adb-826b-4b5a-b753-27cc78070fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850585469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3850585469
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4170216644
Short name T142
Test name
Test status
Simulation time 142236228484 ps
CPU time 851.11 seconds
Started Mar 31 01:11:22 PM PDT 24
Finished Mar 31 01:25:33 PM PDT 24
Peak memory 220576 kb
Host smart-370a12b0-9f79-40d0-a3bc-f5383519fa10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170216644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4170216644
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.979260045
Short name T591
Test name
Test status
Simulation time 33550556 ps
CPU time 1.22 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 217888 kb
Host smart-eb8d59bb-ba83-459b-b04e-f376e6e90761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979260045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.979260045
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2870919962
Short name T259
Test name
Test status
Simulation time 31684889 ps
CPU time 1.11 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:12 PM PDT 24
Peak memory 216480 kb
Host smart-936ae4f4-efe4-40f9-9cf6-72c1f1a777b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870919962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2870919962
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1532594367
Short name T13
Test name
Test status
Simulation time 41067243 ps
CPU time 1.19 seconds
Started Mar 31 01:13:08 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 219160 kb
Host smart-e4ecf3e3-1695-409d-8120-440c0433d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532594367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1532594367
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2495010558
Short name T644
Test name
Test status
Simulation time 215584689 ps
CPU time 1.32 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 216704 kb
Host smart-3db81bbc-bc2f-49af-9cd1-29fd098ce302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495010558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2495010558
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2189476108
Short name T46
Test name
Test status
Simulation time 29935068 ps
CPU time 1.4 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217756 kb
Host smart-a4f0aa3f-d886-4ffd-ac71-b665146de1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189476108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2189476108
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1606551628
Short name T248
Test name
Test status
Simulation time 66788131 ps
CPU time 1.44 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217904 kb
Host smart-66d4420c-1b1b-4ff6-b668-1241f0427d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606551628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1606551628
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.36167140
Short name T441
Test name
Test status
Simulation time 41619570 ps
CPU time 1.5 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217848 kb
Host smart-cdea02c3-0192-4832-8ec2-a837e829d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36167140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.36167140
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4027503911
Short name T684
Test name
Test status
Simulation time 43350368 ps
CPU time 1.54 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217800 kb
Host smart-3a49a075-accb-408a-8164-0c65b696f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027503911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4027503911
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3492914366
Short name T810
Test name
Test status
Simulation time 51971521 ps
CPU time 1.71 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:16 PM PDT 24
Peak memory 217616 kb
Host smart-70f5012b-e144-4b6f-b692-ebfabdac97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492914366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3492914366
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2726948748
Short name T792
Test name
Test status
Simulation time 26167920 ps
CPU time 1.13 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 219192 kb
Host smart-3a4509a2-0179-4bbc-a005-3b3396e24aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726948748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2726948748
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2809711446
Short name T513
Test name
Test status
Simulation time 46671824 ps
CPU time 1.22 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 215612 kb
Host smart-245ac592-c539-4891-996e-f05ba10cb542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809711446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2809711446
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3615396444
Short name T809
Test name
Test status
Simulation time 52223315 ps
CPU time 0.85 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:30 PM PDT 24
Peak memory 206632 kb
Host smart-3f4cc4f1-3b1b-4276-aa89-b2f780b937bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615396444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3615396444
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1771899611
Short name T662
Test name
Test status
Simulation time 24898004 ps
CPU time 0.84 seconds
Started Mar 31 01:11:30 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 215364 kb
Host smart-92938890-a9a8-4754-b2af-4a667baa2424
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771899611 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1771899611
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2326595536
Short name T815
Test name
Test status
Simulation time 268965329 ps
CPU time 1.19 seconds
Started Mar 31 01:11:30 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 216228 kb
Host smart-1b94d2b1-a4df-40f2-991c-aa41a7a77171
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326595536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2326595536
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.347854255
Short name T714
Test name
Test status
Simulation time 21775522 ps
CPU time 1.15 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 229692 kb
Host smart-df4ce899-e740-4158-a557-1198e5da4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347854255 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.347854255
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2821910487
Short name T295
Test name
Test status
Simulation time 28933797 ps
CPU time 1.18 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 216536 kb
Host smart-6086aaa9-d358-4b06-b76d-f51439e68d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821910487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2821910487
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.161797327
Short name T323
Test name
Test status
Simulation time 28990449 ps
CPU time 0.96 seconds
Started Mar 31 01:11:23 PM PDT 24
Finished Mar 31 01:11:24 PM PDT 24
Peak memory 215320 kb
Host smart-28a5c58d-e729-4d89-b502-42b3f16f4bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161797327 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.161797327
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4291029791
Short name T198
Test name
Test status
Simulation time 169424981 ps
CPU time 2.27 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 215292 kb
Host smart-babd5538-d987-4d2c-b4a7-0b3e09956ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291029791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4291029791
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.713806366
Short name T813
Test name
Test status
Simulation time 51451477406 ps
CPU time 1263.61 seconds
Started Mar 31 01:11:34 PM PDT 24
Finished Mar 31 01:32:38 PM PDT 24
Peak memory 222436 kb
Host smart-6189a94e-88ea-40b7-8d35-83758378e018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713806366 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.713806366
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.965529686
Short name T285
Test name
Test status
Simulation time 86992964 ps
CPU time 1.21 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 219240 kb
Host smart-eee0d674-c438-4919-adb4-7fef955a9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965529686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.965529686
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1213029067
Short name T235
Test name
Test status
Simulation time 302173575 ps
CPU time 2.13 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 216948 kb
Host smart-450d19d2-f802-4867-9540-b84c9fcb0751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213029067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1213029067
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2902417174
Short name T401
Test name
Test status
Simulation time 26372228 ps
CPU time 1.23 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 216944 kb
Host smart-4dfb24db-5c80-4c8b-a482-3ba78cce5b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902417174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2902417174
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1783096099
Short name T26
Test name
Test status
Simulation time 125602970 ps
CPU time 1.39 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 218064 kb
Host smart-6ffc8119-5e4b-479c-8db3-3f93aaccfe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783096099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1783096099
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2430632243
Short name T563
Test name
Test status
Simulation time 53745148 ps
CPU time 1.16 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 218000 kb
Host smart-aca8c1f5-7cbd-4a4b-9da7-599236102f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430632243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2430632243
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2058477764
Short name T266
Test name
Test status
Simulation time 118905678 ps
CPU time 1.27 seconds
Started Mar 31 01:13:08 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 218024 kb
Host smart-1574e8bd-33b5-43b2-94f0-94fbb8c93fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058477764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2058477764
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1633213283
Short name T830
Test name
Test status
Simulation time 38754017 ps
CPU time 1.75 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 217804 kb
Host smart-356039b3-044c-4f89-8df4-eaa9f79b1c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633213283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1633213283
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3912654244
Short name T666
Test name
Test status
Simulation time 40119324 ps
CPU time 1.33 seconds
Started Mar 31 01:13:10 PM PDT 24
Finished Mar 31 01:13:11 PM PDT 24
Peak memory 217832 kb
Host smart-db6853ea-8b3b-410b-9d9b-2fe385e36cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912654244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3912654244
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1242515864
Short name T751
Test name
Test status
Simulation time 27817259 ps
CPU time 1.22 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 218016 kb
Host smart-bd15f6df-4186-411c-99d3-3b95c4aac809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242515864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1242515864
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.2297661905
Short name T531
Test name
Test status
Simulation time 17081866 ps
CPU time 0.82 seconds
Started Mar 31 01:11:31 PM PDT 24
Finished Mar 31 01:11:32 PM PDT 24
Peak memory 205732 kb
Host smart-c4d07f12-b8e1-490f-8002-742e3ae03ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297661905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2297661905
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2028466511
Short name T761
Test name
Test status
Simulation time 12364451 ps
CPU time 0.91 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:30 PM PDT 24
Peak memory 216012 kb
Host smart-4b7fd45c-917e-4d04-b36e-1b7e340aeba6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028466511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2028466511
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.609643778
Short name T110
Test name
Test status
Simulation time 75194551 ps
CPU time 0.83 seconds
Started Mar 31 01:11:30 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 215084 kb
Host smart-43b0c1c5-dd79-4427-97e7-9384d680f5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609643778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.609643778
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3885635927
Short name T179
Test name
Test status
Simulation time 41777852 ps
CPU time 1.5 seconds
Started Mar 31 01:11:26 PM PDT 24
Finished Mar 31 01:11:28 PM PDT 24
Peak memory 216480 kb
Host smart-3601736f-52a4-4e21-81bf-4e0a002d39a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885635927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3885635927
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3027570736
Short name T478
Test name
Test status
Simulation time 22188799 ps
CPU time 1.1 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 215676 kb
Host smart-03737157-357c-448a-916f-b99f48790b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027570736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3027570736
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.989177816
Short name T672
Test name
Test status
Simulation time 27243756 ps
CPU time 0.93 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:29 PM PDT 24
Peak memory 215292 kb
Host smart-825dfd39-06cd-4172-80ec-613092948a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989177816 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.989177816
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1673089905
Short name T709
Test name
Test status
Simulation time 84447617 ps
CPU time 2.18 seconds
Started Mar 31 01:11:31 PM PDT 24
Finished Mar 31 01:11:33 PM PDT 24
Peak memory 216680 kb
Host smart-4d9a973c-a059-4770-b3d0-eb7fbeae5b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673089905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1673089905
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.264424418
Short name T342
Test name
Test status
Simulation time 90667955272 ps
CPU time 2160.33 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:47:30 PM PDT 24
Peak memory 226984 kb
Host smart-c548231f-c11c-4047-b16f-4e5dd667a355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264424418 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.264424418
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1352568551
Short name T730
Test name
Test status
Simulation time 73863547 ps
CPU time 1.15 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:12 PM PDT 24
Peak memory 219380 kb
Host smart-4581e8ca-de34-4ae4-97c2-d6f4ea534e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352568551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1352568551
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2384586275
Short name T575
Test name
Test status
Simulation time 44390186 ps
CPU time 1.49 seconds
Started Mar 31 01:13:04 PM PDT 24
Finished Mar 31 01:13:06 PM PDT 24
Peak memory 216652 kb
Host smart-15764faa-61ae-43af-8210-c14be75d80f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384586275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2384586275
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.409615894
Short name T303
Test name
Test status
Simulation time 49878623 ps
CPU time 1.83 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:11 PM PDT 24
Peak memory 217872 kb
Host smart-9e00e1da-f8db-455a-b40c-673f163f095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409615894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.409615894
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1224957991
Short name T690
Test name
Test status
Simulation time 488781952 ps
CPU time 2.3 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:11 PM PDT 24
Peak memory 218228 kb
Host smart-34327491-94c3-4250-b6a9-d11fd6f8c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224957991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1224957991
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3716355753
Short name T243
Test name
Test status
Simulation time 72596126 ps
CPU time 1.07 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:12 PM PDT 24
Peak memory 218580 kb
Host smart-3a2fda54-2ed8-4537-ad64-e65b6c99e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716355753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3716355753
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2316978082
Short name T502
Test name
Test status
Simulation time 45319677 ps
CPU time 1.53 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 217776 kb
Host smart-90230efb-031c-4e59-9259-a9f821d22349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316978082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2316978082
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1634827484
Short name T629
Test name
Test status
Simulation time 68281956 ps
CPU time 1 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 216660 kb
Host smart-5adfaba7-33c8-4833-a70c-3ed2eade8604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634827484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1634827484
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1673971023
Short name T671
Test name
Test status
Simulation time 101561641 ps
CPU time 1.38 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 218172 kb
Host smart-977dc743-c298-45b7-af74-c637817e923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673971023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1673971023
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.755494403
Short name T549
Test name
Test status
Simulation time 153316006 ps
CPU time 1.19 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 219576 kb
Host smart-755a6054-2744-4829-956b-4a4ef1a9c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755494403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.755494403
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.512683153
Short name T617
Test name
Test status
Simulation time 147770511 ps
CPU time 3.18 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 218688 kb
Host smart-67e1d9c7-f767-45d8-bc31-6f4e40a644aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512683153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.512683153
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.1390645210
Short name T347
Test name
Test status
Simulation time 11159244 ps
CPU time 0.86 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:36 PM PDT 24
Peak memory 205604 kb
Host smart-aefb9f08-e2ff-4c97-a961-a8ce4085e9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390645210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1390645210
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1047972601
Short name T161
Test name
Test status
Simulation time 31432250 ps
CPU time 0.86 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:36 PM PDT 24
Peak memory 215800 kb
Host smart-40f05219-a81a-4189-bc8e-468abf6be735
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047972601 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1047972601
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1281587987
Short name T470
Test name
Test status
Simulation time 19596048 ps
CPU time 1.05 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 217804 kb
Host smart-d2aa2329-1fe1-4d5b-9621-5f5acdefac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281587987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1281587987
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3465203263
Short name T544
Test name
Test status
Simulation time 128605320 ps
CPU time 1.55 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 218352 kb
Host smart-c949e868-8d78-4293-8dab-373c90eba4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465203263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3465203263
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1453715425
Short name T515
Test name
Test status
Simulation time 23821508 ps
CPU time 1.12 seconds
Started Mar 31 01:11:29 PM PDT 24
Finished Mar 31 01:11:30 PM PDT 24
Peak memory 215524 kb
Host smart-8f63b830-dca2-4891-ac0a-339ea0d79553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453715425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1453715425
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.152282852
Short name T661
Test name
Test status
Simulation time 48608625 ps
CPU time 1 seconds
Started Mar 31 01:11:31 PM PDT 24
Finished Mar 31 01:11:32 PM PDT 24
Peak memory 215320 kb
Host smart-37eb4a0e-42f0-40b8-9db3-b0695b6b476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152282852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.152282852
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.773395046
Short name T739
Test name
Test status
Simulation time 200580513 ps
CPU time 2.21 seconds
Started Mar 31 01:11:28 PM PDT 24
Finished Mar 31 01:11:30 PM PDT 24
Peak memory 215288 kb
Host smart-0baa2211-81aa-4fe9-9315-73d3d2f78e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773395046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.773395046
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2181257494
Short name T595
Test name
Test status
Simulation time 342707384039 ps
CPU time 1949.1 seconds
Started Mar 31 01:11:27 PM PDT 24
Finished Mar 31 01:43:56 PM PDT 24
Peak memory 224888 kb
Host smart-211f8d76-0f85-4bc5-9b90-a39d1161c15a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181257494 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2181257494
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3878492757
Short name T355
Test name
Test status
Simulation time 45493793 ps
CPU time 1.46 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:11 PM PDT 24
Peak memory 217960 kb
Host smart-a33ee503-a403-484b-8059-4593b4f93543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878492757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3878492757
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1296601400
Short name T565
Test name
Test status
Simulation time 215776007 ps
CPU time 2.81 seconds
Started Mar 31 01:13:05 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217904 kb
Host smart-e86d14ae-6c8c-4556-8665-9f88ab2144be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296601400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1296601400
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.272605318
Short name T232
Test name
Test status
Simulation time 43468016 ps
CPU time 1.41 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:08 PM PDT 24
Peak memory 217956 kb
Host smart-d979b7e4-ee32-40b9-a5dd-c02c6da49de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272605318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.272605318
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1431568373
Short name T61
Test name
Test status
Simulation time 84295043 ps
CPU time 1.03 seconds
Started Mar 31 01:13:08 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 218736 kb
Host smart-108be8ed-576f-4c77-a6b1-5dd4063b4a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431568373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1431568373
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.761128187
Short name T543
Test name
Test status
Simulation time 55652314 ps
CPU time 1.03 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 216680 kb
Host smart-5993eb2b-c07e-4069-aa8f-24dbe0716082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761128187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.761128187
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3890782530
Short name T296
Test name
Test status
Simulation time 34607371 ps
CPU time 1.41 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 217664 kb
Host smart-dd155397-33a7-41e2-a4d0-0b73df5eb46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890782530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3890782530
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1041743843
Short name T806
Test name
Test status
Simulation time 73087091 ps
CPU time 2.5 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:11 PM PDT 24
Peak memory 218032 kb
Host smart-a30bcd61-4ee5-4c4e-ac5f-aea2b8f4c5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041743843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1041743843
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.261526487
Short name T615
Test name
Test status
Simulation time 81661483 ps
CPU time 1.22 seconds
Started Mar 31 01:13:11 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 219236 kb
Host smart-9b723846-1390-4fbf-ab42-dcc30531b39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261526487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.261526487
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1848127913
Short name T799
Test name
Test status
Simulation time 71839725 ps
CPU time 1.11 seconds
Started Mar 31 01:13:15 PM PDT 24
Finished Mar 31 01:13:16 PM PDT 24
Peak memory 216552 kb
Host smart-b8d5932d-275f-459d-a8bb-27d549c8703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848127913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1848127913
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2847438811
Short name T420
Test name
Test status
Simulation time 205608521 ps
CPU time 2.72 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 217764 kb
Host smart-14d7280e-6f33-4eea-b2f2-0220a01290a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847438811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2847438811
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2688676216
Short name T275
Test name
Test status
Simulation time 38307694 ps
CPU time 1.13 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:36 PM PDT 24
Peak memory 215640 kb
Host smart-d8b80bb0-21f9-4c09-beae-8e0835b36afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688676216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2688676216
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3874243491
Short name T711
Test name
Test status
Simulation time 15002479 ps
CPU time 0.86 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 205580 kb
Host smart-e6e7bc6e-0d7f-4a3d-ac39-2e6d3994a99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874243491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3874243491
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1783283824
Short name T126
Test name
Test status
Simulation time 96651748 ps
CPU time 1.45 seconds
Started Mar 31 01:11:46 PM PDT 24
Finished Mar 31 01:11:47 PM PDT 24
Peak memory 216476 kb
Host smart-c5678f8a-c02d-4dc7-9359-a9b06f5fd814
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783283824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1783283824
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1024477726
Short name T63
Test name
Test status
Simulation time 24133001 ps
CPU time 1.01 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 217952 kb
Host smart-960c159e-df92-4d3a-90e8-0aad1a4969d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024477726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1024477726
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.105473173
Short name T365
Test name
Test status
Simulation time 146725942 ps
CPU time 2.18 seconds
Started Mar 31 01:11:39 PM PDT 24
Finished Mar 31 01:11:42 PM PDT 24
Peak memory 216772 kb
Host smart-04342b8d-9e82-4514-ae1c-5362bb434d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105473173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.105473173
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1986421967
Short name T452
Test name
Test status
Simulation time 26859184 ps
CPU time 1.18 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 215404 kb
Host smart-76bb2a0b-a95d-4e25-972b-139cbbf09b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986421967 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1986421967
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.289674682
Short name T459
Test name
Test status
Simulation time 48455587 ps
CPU time 0.96 seconds
Started Mar 31 01:11:41 PM PDT 24
Finished Mar 31 01:11:42 PM PDT 24
Peak memory 215224 kb
Host smart-995797fb-0603-4caa-8fe2-bcdacacc9cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289674682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.289674682
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3679900066
Short name T426
Test name
Test status
Simulation time 1403563680 ps
CPU time 4.48 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:40 PM PDT 24
Peak memory 216312 kb
Host smart-87d0fa59-504f-426d-b715-143833153809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679900066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3679900066
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2881420932
Short name T185
Test name
Test status
Simulation time 50512532629 ps
CPU time 1342.34 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:33:59 PM PDT 24
Peak memory 222412 kb
Host smart-d4f670a2-8530-4e74-bb88-244eaed9a860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881420932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2881420932
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2878549505
Short name T451
Test name
Test status
Simulation time 84930228 ps
CPU time 1.88 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 217792 kb
Host smart-e6c62821-890a-4377-9592-9361013c730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878549505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2878549505
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3620212495
Short name T59
Test name
Test status
Simulation time 20449473 ps
CPU time 1.08 seconds
Started Mar 31 01:13:06 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 216444 kb
Host smart-e9338835-164e-461d-96e3-6562804c241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620212495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3620212495
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.809428808
Short name T587
Test name
Test status
Simulation time 34806073 ps
CPU time 1.27 seconds
Started Mar 31 01:13:07 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 218944 kb
Host smart-be967247-c1c8-4139-87b9-d5314795f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809428808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.809428808
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2867578287
Short name T733
Test name
Test status
Simulation time 116000014 ps
CPU time 1.75 seconds
Started Mar 31 01:13:09 PM PDT 24
Finished Mar 31 01:13:11 PM PDT 24
Peak memory 217904 kb
Host smart-556d588d-fb44-4126-a779-8ff8192b9e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867578287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2867578287
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3695002752
Short name T339
Test name
Test status
Simulation time 32850682 ps
CPU time 1.31 seconds
Started Mar 31 01:13:08 PM PDT 24
Finished Mar 31 01:13:10 PM PDT 24
Peak memory 217788 kb
Host smart-43a92a8d-18c9-4799-a1b3-76f30b175816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695002752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3695002752
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.494818380
Short name T433
Test name
Test status
Simulation time 84135173 ps
CPU time 1.27 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:16 PM PDT 24
Peak memory 218832 kb
Host smart-3f9b1802-485e-4b31-b3e9-2fb876533390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494818380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.494818380
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2911381622
Short name T431
Test name
Test status
Simulation time 85818216 ps
CPU time 2.93 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 218000 kb
Host smart-c48dc32a-b434-4ad5-98ea-7fc281fdf11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911381622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2911381622
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3748564356
Short name T193
Test name
Test status
Simulation time 41559316 ps
CPU time 1.38 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 215272 kb
Host smart-db9450db-4190-4e1e-b1f4-71df0f68b9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748564356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3748564356
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.4156047967
Short name T307
Test name
Test status
Simulation time 80867787 ps
CPU time 0.91 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 206784 kb
Host smart-d48332f4-9ac2-4e0f-b69f-9b88a110342c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156047967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4156047967
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.202357728
Short name T723
Test name
Test status
Simulation time 31418664 ps
CPU time 0.85 seconds
Started Mar 31 01:11:46 PM PDT 24
Finished Mar 31 01:11:46 PM PDT 24
Peak memory 215592 kb
Host smart-f403c0f9-5842-4bd6-a012-04e4581e05ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202357728 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.202357728
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.882474351
Short name T195
Test name
Test status
Simulation time 75666420 ps
CPU time 1.31 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 216588 kb
Host smart-18cb7f16-aaca-4144-ad40-976d1953ff89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882474351 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.882474351
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.659847300
Short name T69
Test name
Test status
Simulation time 26095883 ps
CPU time 1.27 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 219312 kb
Host smart-91d3bf09-a952-4c7a-813b-339793544ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659847300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.659847300
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4281710336
Short name T476
Test name
Test status
Simulation time 254480488 ps
CPU time 3.58 seconds
Started Mar 31 01:11:45 PM PDT 24
Finished Mar 31 01:11:49 PM PDT 24
Peak memory 216872 kb
Host smart-fdf7566a-734e-4312-909a-db8458aa559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281710336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4281710336
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.827548714
Short name T833
Test name
Test status
Simulation time 23166548 ps
CPU time 1.11 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 215424 kb
Host smart-553b6dec-3d48-41f6-b470-51613dead2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827548714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.827548714
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.19275995
Short name T664
Test name
Test status
Simulation time 26157045 ps
CPU time 0.97 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 215288 kb
Host smart-a197f075-d08f-48ea-b76b-9fc1eee07eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19275995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.19275995
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2555854024
Short name T242
Test name
Test status
Simulation time 93809510 ps
CPU time 2.27 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:39 PM PDT 24
Peak memory 216348 kb
Host smart-3b1f74e0-6d47-4725-a3f3-6619713387b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555854024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2555854024
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.852789375
Short name T331
Test name
Test status
Simulation time 134228678675 ps
CPU time 990.39 seconds
Started Mar 31 01:11:38 PM PDT 24
Finished Mar 31 01:28:08 PM PDT 24
Peak memory 221300 kb
Host smart-9dade7ad-40d0-426e-bb7d-51d9076d73bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852789375 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.852789375
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1382379247
Short name T152
Test name
Test status
Simulation time 48956345 ps
CPU time 1.54 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:16 PM PDT 24
Peak memory 218756 kb
Host smart-35d6dcbd-d621-4ce7-bc85-fb9531216374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382379247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1382379247
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2001446605
Short name T645
Test name
Test status
Simulation time 31899685 ps
CPU time 1.45 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 218192 kb
Host smart-07e49627-0ae7-4d81-829c-1aae390a74bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001446605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2001446605
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2416879936
Short name T677
Test name
Test status
Simulation time 146503080 ps
CPU time 1.05 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 216856 kb
Host smart-fa424b33-e450-4f1a-ac43-6a93c90b8ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416879936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2416879936
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.4123420392
Short name T29
Test name
Test status
Simulation time 60871475 ps
CPU time 1.68 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:16 PM PDT 24
Peak memory 216636 kb
Host smart-d265798d-205d-4b58-9a80-9e48c9c3bd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123420392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.4123420392
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2461545984
Short name T312
Test name
Test status
Simulation time 42454445 ps
CPU time 1.59 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 216744 kb
Host smart-5c443c6f-804b-429c-8795-5cf28f064edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461545984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2461545984
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1316482298
Short name T373
Test name
Test status
Simulation time 63174659 ps
CPU time 1.11 seconds
Started Mar 31 01:13:14 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 219340 kb
Host smart-0f225ccf-fd1b-4cbd-8f28-39aeec633a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316482298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1316482298
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2587718599
Short name T555
Test name
Test status
Simulation time 203510267 ps
CPU time 1.59 seconds
Started Mar 31 01:13:17 PM PDT 24
Finished Mar 31 01:13:19 PM PDT 24
Peak memory 219608 kb
Host smart-b02c6777-f60b-46f4-8b48-51076874a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587718599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2587718599
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1369409989
Short name T584
Test name
Test status
Simulation time 44321919 ps
CPU time 1.47 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 218628 kb
Host smart-6da2109a-ce52-46b1-983d-a4753c80db83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369409989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1369409989
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1592664005
Short name T646
Test name
Test status
Simulation time 70267169 ps
CPU time 1.4 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 218020 kb
Host smart-86142737-4df1-4285-b02f-80d6ea4398e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592664005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1592664005
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2440993514
Short name T171
Test name
Test status
Simulation time 30174836 ps
CPU time 1.19 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 215596 kb
Host smart-bb543285-87e3-4ec6-8ec3-0b8b3bcb275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440993514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2440993514
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4193830896
Short name T524
Test name
Test status
Simulation time 15092292 ps
CPU time 0.84 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:36 PM PDT 24
Peak memory 206776 kb
Host smart-1d592973-ec51-4607-b47a-0a7ca864363b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193830896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4193830896
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1111238237
Short name T67
Test name
Test status
Simulation time 17147621 ps
CPU time 0.95 seconds
Started Mar 31 01:11:46 PM PDT 24
Finished Mar 31 01:11:47 PM PDT 24
Peak memory 215744 kb
Host smart-9f9c2d6d-72ad-4ef0-bad9-28dfcd65b2e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111238237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1111238237
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.3077631476
Short name T654
Test name
Test status
Simulation time 23032130 ps
CPU time 1.21 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 231400 kb
Host smart-e6b33a8a-043b-4a2b-9a1f-a5bec984a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077631476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3077631476
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3254471790
Short name T670
Test name
Test status
Simulation time 140550602 ps
CPU time 1.6 seconds
Started Mar 31 01:11:33 PM PDT 24
Finished Mar 31 01:11:35 PM PDT 24
Peak memory 217844 kb
Host smart-f6972987-aeec-4e6d-8c28-c29d759e8360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254471790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3254471790
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.778823732
Short name T816
Test name
Test status
Simulation time 40070553 ps
CPU time 0.98 seconds
Started Mar 31 01:11:35 PM PDT 24
Finished Mar 31 01:11:36 PM PDT 24
Peak memory 232380 kb
Host smart-d57a7f45-26c1-4719-b834-d1762c4c15fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778823732 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.778823732
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4224852447
Short name T413
Test name
Test status
Simulation time 43783786 ps
CPU time 0.87 seconds
Started Mar 31 01:11:38 PM PDT 24
Finished Mar 31 01:11:39 PM PDT 24
Peak memory 207092 kb
Host smart-cacd6248-2b14-4e4d-8926-ff8bedf6685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224852447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4224852447
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3081081247
Short name T560
Test name
Test status
Simulation time 503417699 ps
CPU time 5.45 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:41 PM PDT 24
Peak memory 215276 kb
Host smart-e7fe82e5-399d-402d-a7a8-dd2f24ff442f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081081247 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3081081247
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2424292470
Short name T182
Test name
Test status
Simulation time 526177561391 ps
CPU time 1026.49 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:28:43 PM PDT 24
Peak memory 223108 kb
Host smart-f145691e-0dfd-4e48-b54b-98ed4dcc7892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424292470 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2424292470
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1176385718
Short name T318
Test name
Test status
Simulation time 233212876 ps
CPU time 1.45 seconds
Started Mar 31 01:13:15 PM PDT 24
Finished Mar 31 01:13:17 PM PDT 24
Peak memory 217952 kb
Host smart-d7f55b77-7c87-4af6-815b-0f64e17dc159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176385718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1176385718
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.129585130
Short name T705
Test name
Test status
Simulation time 39990842 ps
CPU time 1.09 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 218048 kb
Host smart-d55e321a-255f-4238-bc0a-6626343fc51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129585130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.129585130
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2895185702
Short name T534
Test name
Test status
Simulation time 40791880 ps
CPU time 1.59 seconds
Started Mar 31 01:13:03 PM PDT 24
Finished Mar 31 01:13:04 PM PDT 24
Peak memory 217692 kb
Host smart-218b5b73-515a-4b73-a12d-e12e6d874c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895185702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2895185702
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2749426646
Short name T653
Test name
Test status
Simulation time 103003787 ps
CPU time 1.17 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:14 PM PDT 24
Peak memory 215280 kb
Host smart-5e692eab-b98f-459d-ab4c-02b900b09a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749426646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2749426646
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4135145973
Short name T619
Test name
Test status
Simulation time 145208399 ps
CPU time 1.83 seconds
Started Mar 31 01:13:13 PM PDT 24
Finished Mar 31 01:13:15 PM PDT 24
Peak memory 219252 kb
Host smart-4bdd667c-20c0-409e-b016-2690a4d63d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135145973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4135145973
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.818533103
Short name T257
Test name
Test status
Simulation time 114130843 ps
CPU time 1.67 seconds
Started Mar 31 01:13:15 PM PDT 24
Finished Mar 31 01:13:17 PM PDT 24
Peak memory 218224 kb
Host smart-ff72343f-5822-4dbe-a2c3-605d4f7f4d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818533103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.818533103
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.842675277
Short name T507
Test name
Test status
Simulation time 22680774 ps
CPU time 1.16 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 219184 kb
Host smart-2988e0b9-a7ee-4e41-99b2-558e928a3069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842675277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.842675277
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1810989321
Short name T551
Test name
Test status
Simulation time 59039849 ps
CPU time 1.03 seconds
Started Mar 31 01:13:12 PM PDT 24
Finished Mar 31 01:13:13 PM PDT 24
Peak memory 216544 kb
Host smart-8b9c3fe1-7bf8-49ae-8b03-caa5ca3549a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810989321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1810989321
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.478909277
Short name T797
Test name
Test status
Simulation time 185928703 ps
CPU time 2.7 seconds
Started Mar 31 01:13:10 PM PDT 24
Finished Mar 31 01:13:12 PM PDT 24
Peak memory 217804 kb
Host smart-ae64f87f-fb54-490d-9cc5-c87e38acecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478909277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.478909277
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2063657458
Short name T725
Test name
Test status
Simulation time 75725897 ps
CPU time 1.28 seconds
Started Mar 31 01:13:16 PM PDT 24
Finished Mar 31 01:13:18 PM PDT 24
Peak memory 218268 kb
Host smart-ab6e256f-e286-4137-a5cc-6f6fdd374059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063657458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2063657458
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3588551483
Short name T231
Test name
Test status
Simulation time 50824416 ps
CPU time 1.11 seconds
Started Mar 31 01:10:23 PM PDT 24
Finished Mar 31 01:10:24 PM PDT 24
Peak memory 215636 kb
Host smart-f096d498-cef0-416a-b2cc-bcc0af78a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588551483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3588551483
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.232860017
Short name T317
Test name
Test status
Simulation time 37382707 ps
CPU time 0.83 seconds
Started Mar 31 01:10:26 PM PDT 24
Finished Mar 31 01:10:26 PM PDT 24
Peak memory 205756 kb
Host smart-cb65d2c1-cb22-4ab2-9b0b-c33bf4fac603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232860017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.232860017
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_err.3570417989
Short name T73
Test name
Test status
Simulation time 42868371 ps
CPU time 1.09 seconds
Started Mar 31 01:10:24 PM PDT 24
Finished Mar 31 01:10:25 PM PDT 24
Peak memory 216728 kb
Host smart-9e6a0e77-3e09-449a-87f3-5d8c29f933c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570417989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3570417989
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1031400691
Short name T658
Test name
Test status
Simulation time 40588439 ps
CPU time 1.51 seconds
Started Mar 31 01:10:23 PM PDT 24
Finished Mar 31 01:10:25 PM PDT 24
Peak memory 215304 kb
Host smart-b649e1ae-2b75-46bf-ab32-0fd39b13cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031400691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1031400691
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1328529399
Short name T438
Test name
Test status
Simulation time 43319924 ps
CPU time 0.98 seconds
Started Mar 31 01:10:26 PM PDT 24
Finished Mar 31 01:10:27 PM PDT 24
Peak memory 224020 kb
Host smart-3d569e54-adea-423b-8b8c-b87a79b4e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328529399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1328529399
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2730930894
Short name T282
Test name
Test status
Simulation time 45104832 ps
CPU time 0.93 seconds
Started Mar 31 01:10:24 PM PDT 24
Finished Mar 31 01:10:25 PM PDT 24
Peak memory 207068 kb
Host smart-72548d9f-c3e3-4022-b462-7c7191e43c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730930894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2730930894
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2475363982
Short name T738
Test name
Test status
Simulation time 55586952 ps
CPU time 0.87 seconds
Started Mar 31 01:10:21 PM PDT 24
Finished Mar 31 01:10:22 PM PDT 24
Peak memory 215224 kb
Host smart-2ff9c00d-ac7d-43fd-bc81-82fc0738a81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475363982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2475363982
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2570484656
Short name T6
Test name
Test status
Simulation time 428777400 ps
CPU time 3.02 seconds
Started Mar 31 01:10:24 PM PDT 24
Finished Mar 31 01:10:27 PM PDT 24
Peak memory 216536 kb
Host smart-bcbb6189-73cf-48e3-9f60-3b39ef9e922f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570484656 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2570484656
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2366012005
Short name T186
Test name
Test status
Simulation time 29452307018 ps
CPU time 741.48 seconds
Started Mar 31 01:10:23 PM PDT 24
Finished Mar 31 01:22:45 PM PDT 24
Peak memory 217732 kb
Host smart-f8433183-6ef8-4b19-adcb-f2a4f1e29de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366012005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2366012005
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2499322347
Short name T788
Test name
Test status
Simulation time 43661746 ps
CPU time 1.22 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:39 PM PDT 24
Peak memory 215544 kb
Host smart-25d875e0-45a3-4ecf-b3f1-79e718e5e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499322347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2499322347
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3111639884
Short name T406
Test name
Test status
Simulation time 40098269 ps
CPU time 1.07 seconds
Started Mar 31 01:11:36 PM PDT 24
Finished Mar 31 01:11:37 PM PDT 24
Peak memory 205968 kb
Host smart-89e7104d-f3ae-487e-8bd9-c015d579eac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111639884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3111639884
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.3793665785
Short name T535
Test name
Test status
Simulation time 38075039 ps
CPU time 0.93 seconds
Started Mar 31 01:11:40 PM PDT 24
Finished Mar 31 01:11:41 PM PDT 24
Peak memory 219476 kb
Host smart-84355c22-811f-452b-9b01-de4babe0933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793665785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3793665785
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.99473823
Short name T178
Test name
Test status
Simulation time 80172040 ps
CPU time 1.32 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:11:38 PM PDT 24
Peak memory 216468 kb
Host smart-07d6c333-89b4-4fec-9271-3791fdb7a313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99473823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.99473823
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2433927684
Short name T699
Test name
Test status
Simulation time 25464743 ps
CPU time 0.98 seconds
Started Mar 31 01:11:40 PM PDT 24
Finished Mar 31 01:11:41 PM PDT 24
Peak memory 215528 kb
Host smart-7e0be8aa-f03f-4a2d-bd90-aa05b0d0e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433927684 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2433927684
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1486878760
Short name T437
Test name
Test status
Simulation time 28483958 ps
CPU time 0.96 seconds
Started Mar 31 01:11:39 PM PDT 24
Finished Mar 31 01:11:40 PM PDT 24
Peak memory 215216 kb
Host smart-448b73f7-7f96-440f-af64-ef9af3ac3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486878760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1486878760
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.944785094
Short name T749
Test name
Test status
Simulation time 44383929 ps
CPU time 1.07 seconds
Started Mar 31 01:11:46 PM PDT 24
Finished Mar 31 01:11:47 PM PDT 24
Peak memory 205724 kb
Host smart-5a6f9507-7565-40a6-a508-c933ff61f68b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944785094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.944785094
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3158516344
Short name T613
Test name
Test status
Simulation time 120225132291 ps
CPU time 1768.82 seconds
Started Mar 31 01:11:37 PM PDT 24
Finished Mar 31 01:41:07 PM PDT 24
Peak memory 225480 kb
Host smart-46006256-54db-4159-b8fb-e63d6cf245c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158516344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3158516344
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3450718926
Short name T146
Test name
Test status
Simulation time 82990334 ps
CPU time 1.19 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 215628 kb
Host smart-0ce9e23b-003f-4b96-8219-1f1ed3d592e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450718926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3450718926
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4119336962
Short name T150
Test name
Test status
Simulation time 51983533 ps
CPU time 0.93 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:49 PM PDT 24
Peak memory 205940 kb
Host smart-cdfb41de-f064-4589-8e35-b4af3a50f8fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119336962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4119336962
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_err.430869787
Short name T151
Test name
Test status
Simulation time 28449225 ps
CPU time 0.85 seconds
Started Mar 31 01:11:51 PM PDT 24
Finished Mar 31 01:11:52 PM PDT 24
Peak memory 218004 kb
Host smart-c7cdf991-53b4-46d6-9767-5a2c8966a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430869787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.430869787
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.361524132
Short name T829
Test name
Test status
Simulation time 91765168 ps
CPU time 1.19 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 216516 kb
Host smart-b68c6926-9368-4d7a-ac6f-881187d42452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361524132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.361524132
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.371240419
Short name T124
Test name
Test status
Simulation time 22977266 ps
CPU time 1.08 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:51 PM PDT 24
Peak memory 215660 kb
Host smart-92d1fc9d-7c3b-4a07-b8c9-67926a6b1dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371240419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.371240419
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2182234786
Short name T291
Test name
Test status
Simulation time 77009289 ps
CPU time 0.92 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 215216 kb
Host smart-fa53fca6-0c5d-4692-8b98-1e0faa9711c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182234786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2182234786
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.430935356
Short name T395
Test name
Test status
Simulation time 162645084 ps
CPU time 2.2 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 215320 kb
Host smart-94c58a58-2b1d-4c24-8629-fa1679ba19a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430935356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.430935356
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3709492362
Short name T518
Test name
Test status
Simulation time 133048160039 ps
CPU time 631.57 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:22:18 PM PDT 24
Peak memory 219584 kb
Host smart-08e582aa-c2c3-4cb0-b0d0-d11a713120a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709492362 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3709492362
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.94006922
Short name T550
Test name
Test status
Simulation time 36904270 ps
CPU time 1.19 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 215608 kb
Host smart-b42c77c6-c07f-444d-adbb-2e16124937e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94006922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.94006922
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2583062259
Short name T362
Test name
Test status
Simulation time 19889081 ps
CPU time 0.99 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 206792 kb
Host smart-7c472c19-914e-41de-b46d-ac899d4c60e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583062259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2583062259
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1684669921
Short name T770
Test name
Test status
Simulation time 13775936 ps
CPU time 0.89 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 216048 kb
Host smart-23d1ddc2-1f9a-49cf-8b4b-64dee1b09eba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684669921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1684669921
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.4154395802
Short name T651
Test name
Test status
Simulation time 24008353 ps
CPU time 1.01 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:51 PM PDT 24
Peak memory 219244 kb
Host smart-1ced574b-251d-4335-bbf0-e07142c7dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154395802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4154395802
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1295422884
Short name T820
Test name
Test status
Simulation time 96004349 ps
CPU time 1.58 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 218064 kb
Host smart-0422b85f-73ec-45ef-b6cc-3528f4ee8564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295422884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1295422884
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3338998397
Short name T572
Test name
Test status
Simulation time 22407050 ps
CPU time 1.08 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 215488 kb
Host smart-d46e0b69-52ab-423b-92a9-1664f1fd45e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338998397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3338998397
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1732453621
Short name T742
Test name
Test status
Simulation time 20572664 ps
CPU time 0.92 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 215332 kb
Host smart-455f9299-6047-4abd-9208-ed40cb14d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732453621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1732453621
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4021964965
Short name T599
Test name
Test status
Simulation time 697769675 ps
CPU time 5.87 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 215224 kb
Host smart-89ca093b-8a2c-4925-bc36-dfda8aa8404c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021964965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4021964965
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.844040219
Short name T567
Test name
Test status
Simulation time 86449508384 ps
CPU time 2177.28 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:48:05 PM PDT 24
Peak memory 230068 kb
Host smart-86dc78a9-966e-45bc-95d9-a6f1266f5543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844040219 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.844040219
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3159023018
Short name T144
Test name
Test status
Simulation time 25163999 ps
CPU time 1.25 seconds
Started Mar 31 01:11:53 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 215640 kb
Host smart-d3a4de0c-f750-42a4-a6b3-6436499b5809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159023018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3159023018
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3895641455
Short name T358
Test name
Test status
Simulation time 25060307 ps
CPU time 0.9 seconds
Started Mar 31 01:11:51 PM PDT 24
Finished Mar 31 01:11:52 PM PDT 24
Peak memory 205980 kb
Host smart-21b2da8c-092c-4518-9e06-a5896cf156bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895641455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3895641455
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3973941291
Short name T482
Test name
Test status
Simulation time 11272117 ps
CPU time 0.9 seconds
Started Mar 31 01:11:51 PM PDT 24
Finished Mar 31 01:11:52 PM PDT 24
Peak memory 215840 kb
Host smart-4da5fd73-ad49-4987-8df8-cf1d5d4839e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973941291 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3973941291
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1475326208
Short name T159
Test name
Test status
Simulation time 40158074 ps
CPU time 1.29 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 216376 kb
Host smart-f81b62b2-5040-43c6-a61a-29fae5a09541
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475326208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1475326208
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2854687930
Short name T43
Test name
Test status
Simulation time 73385851 ps
CPU time 1.22 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:51 PM PDT 24
Peak memory 224304 kb
Host smart-f600ab13-97e2-40ab-bea5-038b00c1895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854687930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2854687930
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4266725375
Short name T439
Test name
Test status
Simulation time 270551009 ps
CPU time 4.09 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:53 PM PDT 24
Peak memory 218316 kb
Host smart-d243b6b6-b6c7-4d84-978c-b00e274b4b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266725375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4266725375
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.671811336
Short name T127
Test name
Test status
Simulation time 29852547 ps
CPU time 0.89 seconds
Started Mar 31 01:11:47 PM PDT 24
Finished Mar 31 01:11:48 PM PDT 24
Peak memory 215640 kb
Host smart-c2ba9f29-b509-4aa1-ba4b-581d14a697c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671811336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.671811336
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3427560868
Short name T48
Test name
Test status
Simulation time 52990039 ps
CPU time 0.95 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 215316 kb
Host smart-fdfbba07-4d75-42a5-b918-40b9336f4aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427560868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3427560868
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1629454360
Short name T359
Test name
Test status
Simulation time 384801321 ps
CPU time 6.47 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 215312 kb
Host smart-66825f18-6a19-4d9e-ae44-7c0bee5cdc71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629454360 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1629454360
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2841215283
Short name T453
Test name
Test status
Simulation time 71752657503 ps
CPU time 1589.72 seconds
Started Mar 31 01:11:51 PM PDT 24
Finished Mar 31 01:38:21 PM PDT 24
Peak memory 223364 kb
Host smart-3ce49398-9124-48f0-8a1a-fa12ea4a7270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841215283 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2841215283
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.910291133
Short name T276
Test name
Test status
Simulation time 30491281 ps
CPU time 1.26 seconds
Started Mar 31 01:11:51 PM PDT 24
Finished Mar 31 01:11:52 PM PDT 24
Peak memory 215604 kb
Host smart-350d77d6-f7a2-466e-8408-33801ee19ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910291133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.910291133
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2529247057
Short name T474
Test name
Test status
Simulation time 26963845 ps
CPU time 0.9 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:51 PM PDT 24
Peak memory 205896 kb
Host smart-24345609-b3b9-496e-ac2b-19133d97eb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529247057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2529247057
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1166972833
Short name T164
Test name
Test status
Simulation time 58938065 ps
CPU time 0.87 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 215928 kb
Host smart-392c1a31-7c07-4aec-891b-ebba3d6851cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166972833 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1166972833
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.2566674098
Short name T114
Test name
Test status
Simulation time 83436069 ps
CPU time 0.81 seconds
Started Mar 31 01:11:54 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 217804 kb
Host smart-bcdef1d6-6122-4340-8391-5bf03291f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566674098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2566674098
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2743507368
Short name T56
Test name
Test status
Simulation time 250574186 ps
CPU time 3.65 seconds
Started Mar 31 01:11:46 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 217888 kb
Host smart-c606c4a4-2ded-405e-ac2d-6d82bd8784be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743507368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2743507368
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1890451122
Short name T481
Test name
Test status
Simulation time 21996343 ps
CPU time 1.07 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:49 PM PDT 24
Peak memory 215400 kb
Host smart-5eb2124c-bf87-4f5f-84f8-1a3fab7b9205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890451122 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1890451122
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.32338984
Short name T578
Test name
Test status
Simulation time 21328991 ps
CPU time 0.92 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:49 PM PDT 24
Peak memory 215264 kb
Host smart-6376a350-dc08-44f6-9871-9dde35586345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32338984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.32338984
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2732604157
Short name T326
Test name
Test status
Simulation time 169109136 ps
CPU time 3.14 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 216736 kb
Host smart-817982d1-360a-44c5-9839-cb7dec126b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732604157 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2732604157
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1932739515
Short name T767
Test name
Test status
Simulation time 41474080788 ps
CPU time 963.09 seconds
Started Mar 31 01:11:54 PM PDT 24
Finished Mar 31 01:27:57 PM PDT 24
Peak memory 220272 kb
Host smart-f4220ce7-de68-42ea-ae1f-d5a5a9d0307a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932739515 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1932739515
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2934492550
Short name T177
Test name
Test status
Simulation time 67848968 ps
CPU time 1.17 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 215736 kb
Host smart-ed71fdff-f52a-4f1b-8e2d-5eec0d81ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934492550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2934492550
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1381697852
Short name T446
Test name
Test status
Simulation time 26575125 ps
CPU time 1.03 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:51 PM PDT 24
Peak memory 206764 kb
Host smart-aeff0e71-a28c-45ce-ab72-a62b76fe32c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381697852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1381697852
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1850292561
Short name T166
Test name
Test status
Simulation time 11758647 ps
CPU time 0.97 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:50 PM PDT 24
Peak memory 215824 kb
Host smart-59375511-6db6-4cbf-9223-d9c72fdb0ee2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850292561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1850292561
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.507212855
Short name T703
Test name
Test status
Simulation time 66397940 ps
CPU time 0.98 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 216360 kb
Host smart-cb005a65-17ac-476f-92e1-3557a20549b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507212855 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.507212855
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3502873939
Short name T542
Test name
Test status
Simulation time 34939010 ps
CPU time 0.94 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 218112 kb
Host smart-00f9cbbe-ab72-4f7a-9f43-ecc53ef47abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502873939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3502873939
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.262699625
Short name T464
Test name
Test status
Simulation time 66537946 ps
CPU time 2.07 seconds
Started Mar 31 01:11:49 PM PDT 24
Finished Mar 31 01:11:51 PM PDT 24
Peak memory 218612 kb
Host smart-9b228b4d-afb0-42ab-b85e-ba7ffbd1043d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262699625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.262699625
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.790385693
Short name T384
Test name
Test status
Simulation time 21059075 ps
CPU time 1.08 seconds
Started Mar 31 01:11:56 PM PDT 24
Finished Mar 31 01:11:57 PM PDT 24
Peak memory 215556 kb
Host smart-16c98327-f97b-4ab0-a2e3-8ed634e9d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790385693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.790385693
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2836457199
Short name T357
Test name
Test status
Simulation time 27517013 ps
CPU time 0.93 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:11:49 PM PDT 24
Peak memory 215288 kb
Host smart-afad2853-5e37-4665-8eca-10bbd78f5dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836457199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2836457199
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3006100572
Short name T597
Test name
Test status
Simulation time 141440643 ps
CPU time 3.16 seconds
Started Mar 31 01:11:52 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 216484 kb
Host smart-db719ba6-2020-41d9-afa4-0089e4728d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006100572 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3006100572
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2363180378
Short name T796
Test name
Test status
Simulation time 122754935823 ps
CPU time 729.22 seconds
Started Mar 31 01:11:53 PM PDT 24
Finished Mar 31 01:24:02 PM PDT 24
Peak memory 221764 kb
Host smart-f8da186a-56dc-4bc5-94db-274d422b4a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363180378 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2363180378
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.377805120
Short name T455
Test name
Test status
Simulation time 90759276 ps
CPU time 1.25 seconds
Started Mar 31 01:11:50 PM PDT 24
Finished Mar 31 01:11:52 PM PDT 24
Peak memory 215636 kb
Host smart-7461861b-3bd4-4e57-8dfc-d7d3612f42b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377805120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.377805120
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3636613549
Short name T149
Test name
Test status
Simulation time 29786800 ps
CPU time 0.79 seconds
Started Mar 31 01:11:54 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 205516 kb
Host smart-dcbc9f3f-56f5-4f40-9f70-212aa52a970b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636613549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3636613549
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3262547513
Short name T697
Test name
Test status
Simulation time 48416447 ps
CPU time 0.89 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:11:58 PM PDT 24
Peak memory 215512 kb
Host smart-dc257b21-9b7e-46ca-9ca7-5d3e066e0223
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262547513 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3262547513
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.2609522173
Short name T47
Test name
Test status
Simulation time 20029469 ps
CPU time 1.12 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:11:58 PM PDT 24
Peak memory 218184 kb
Host smart-0ab649eb-307a-44f9-a139-9cc3b3460b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609522173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2609522173
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.350311280
Short name T706
Test name
Test status
Simulation time 37427630 ps
CPU time 1.58 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 217716 kb
Host smart-a2a09748-b267-44ee-83ca-d055cc117fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350311280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.350311280
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1576784816
Short name T141
Test name
Test status
Simulation time 22118461 ps
CPU time 0.95 seconds
Started Mar 31 01:11:52 PM PDT 24
Finished Mar 31 01:11:53 PM PDT 24
Peak memory 215804 kb
Host smart-121aa807-78c1-41f9-8a4e-1e0985b2b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576784816 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1576784816
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2136667385
Short name T818
Test name
Test status
Simulation time 24725771 ps
CPU time 0.98 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 215424 kb
Host smart-6b61574b-942f-4642-a081-c008bf0e5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136667385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2136667385
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2047638958
Short name T419
Test name
Test status
Simulation time 383196001 ps
CPU time 2.15 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:05 PM PDT 24
Peak memory 215440 kb
Host smart-15735d9b-0156-4e24-8e97-804872ecadc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047638958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2047638958
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.221257410
Short name T804
Test name
Test status
Simulation time 155177947962 ps
CPU time 1135.14 seconds
Started Mar 31 01:11:48 PM PDT 24
Finished Mar 31 01:30:44 PM PDT 24
Peak memory 223676 kb
Host smart-623a1c39-b8f1-4e98-a2f5-726ecea1e7b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221257410 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.221257410
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1362503204
Short name T70
Test name
Test status
Simulation time 41940599 ps
CPU time 1.22 seconds
Started Mar 31 01:11:54 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 215624 kb
Host smart-25453860-5f54-4913-a4f4-71e8b8e6ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362503204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1362503204
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3329527720
Short name T469
Test name
Test status
Simulation time 15109013 ps
CPU time 0.93 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:11:58 PM PDT 24
Peak memory 206792 kb
Host smart-9dd5cecc-9da2-4eba-a618-da4f3d7e796c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329527720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3329527720
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.832623557
Short name T626
Test name
Test status
Simulation time 22789129 ps
CPU time 0.83 seconds
Started Mar 31 01:11:52 PM PDT 24
Finished Mar 31 01:11:53 PM PDT 24
Peak memory 215404 kb
Host smart-9c44c6d8-e21c-432a-9c8d-0f17bc9dd8ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832623557 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.832623557
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1985175945
Short name T831
Test name
Test status
Simulation time 27086001 ps
CPU time 1.03 seconds
Started Mar 31 01:11:53 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 216316 kb
Host smart-4964ea46-ec65-4bc0-82f2-06b1de5e2a19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985175945 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1985175945
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_genbits.1340156306
Short name T744
Test name
Test status
Simulation time 117700208 ps
CPU time 1.41 seconds
Started Mar 31 01:11:53 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 218004 kb
Host smart-7db8012b-69cc-488a-8c73-c6ac5b0dd22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340156306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1340156306
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.531323332
Short name T304
Test name
Test status
Simulation time 55220577 ps
CPU time 0.9 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 215416 kb
Host smart-4c80d338-97c6-4de5-985f-5dcc883223e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531323332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.531323332
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2642585081
Short name T346
Test name
Test status
Simulation time 259906662 ps
CPU time 5.7 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:12:00 PM PDT 24
Peak memory 215388 kb
Host smart-1e870225-57df-4602-a939-96dd625197f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642585081 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2642585081
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.466195426
Short name T530
Test name
Test status
Simulation time 136389944580 ps
CPU time 656.07 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:22:53 PM PDT 24
Peak memory 223708 kb
Host smart-0697dfd9-5d0c-4498-8c3a-462eb5fadfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466195426 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.466195426
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3420629563
Short name T674
Test name
Test status
Simulation time 27465264 ps
CPU time 1.34 seconds
Started Mar 31 01:11:53 PM PDT 24
Finished Mar 31 01:11:54 PM PDT 24
Peak memory 215608 kb
Host smart-5be388fb-00fa-4134-94af-8182d40204a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420629563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3420629563
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1585913395
Short name T368
Test name
Test status
Simulation time 20040150 ps
CPU time 0.84 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 205644 kb
Host smart-f8ed1062-5fd3-4f8c-8ac5-41c2aefc129b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585913395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1585913395
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3619314657
Short name T118
Test name
Test status
Simulation time 13410013 ps
CPU time 0.95 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 216008 kb
Host smart-571bb945-c74a-4c39-9ec3-2d17ae86f5f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619314657 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3619314657
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3102658199
Short name T777
Test name
Test status
Simulation time 27816208 ps
CPU time 1.12 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 217644 kb
Host smart-e8c2c31c-3716-4235-99dc-98370417a62a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102658199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3102658199
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3553164217
Short name T82
Test name
Test status
Simulation time 75983242 ps
CPU time 1.1 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 229728 kb
Host smart-cc73b2b0-33ee-4fe1-a1ca-24711b959964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553164217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3553164217
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4183878110
Short name T265
Test name
Test status
Simulation time 49859011 ps
CPU time 1.51 seconds
Started Mar 31 01:11:59 PM PDT 24
Finished Mar 31 01:12:01 PM PDT 24
Peak memory 217896 kb
Host smart-65f3a13c-aa55-4ea5-96df-ce37e87af8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183878110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4183878110
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.614812696
Short name T472
Test name
Test status
Simulation time 40561551 ps
CPU time 0.98 seconds
Started Mar 31 01:11:54 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 224040 kb
Host smart-2c5ea37e-bedf-4c2b-85b2-1409dd1b780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614812696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.614812696
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1473360268
Short name T508
Test name
Test status
Simulation time 37617542 ps
CPU time 0.9 seconds
Started Mar 31 01:11:59 PM PDT 24
Finished Mar 31 01:12:00 PM PDT 24
Peak memory 215324 kb
Host smart-3e2def0c-a04f-4036-a75e-30ab0dc41331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473360268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1473360268
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2087519766
Short name T449
Test name
Test status
Simulation time 405049311 ps
CPU time 4.48 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 216448 kb
Host smart-0453dd83-bb33-4126-bf10-d4ec91b2decf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087519766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2087519766
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3945468906
Short name T503
Test name
Test status
Simulation time 71407758975 ps
CPU time 1646.86 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:39:24 PM PDT 24
Peak memory 223808 kb
Host smart-c0e04ee4-a35a-4ff6-91bd-b47ec65d01f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945468906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3945468906
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2407577782
Short name T106
Test name
Test status
Simulation time 25968137 ps
CPU time 1.24 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 215664 kb
Host smart-1a0f0503-3bee-4446-a8c3-df329c5015d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407577782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2407577782
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3027695228
Short name T649
Test name
Test status
Simulation time 26933120 ps
CPU time 0.89 seconds
Started Mar 31 01:11:59 PM PDT 24
Finished Mar 31 01:12:00 PM PDT 24
Peak memory 206016 kb
Host smart-2170a8db-12e7-417c-80fc-8a01e3a40364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027695228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3027695228
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3760325346
Short name T821
Test name
Test status
Simulation time 21173072 ps
CPU time 0.88 seconds
Started Mar 31 01:11:56 PM PDT 24
Finished Mar 31 01:11:57 PM PDT 24
Peak memory 215540 kb
Host smart-3338716c-8cfc-4e3e-8a77-9b7b38df819c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760325346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3760325346
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.1053371060
Short name T86
Test name
Test status
Simulation time 46210169 ps
CPU time 1.03 seconds
Started Mar 31 01:11:58 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 219392 kb
Host smart-9d2b1cc2-16d4-4218-b480-aafef7b73df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053371060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1053371060
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2665902967
Short name T501
Test name
Test status
Simulation time 59830232 ps
CPU time 2.25 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 217900 kb
Host smart-41ea9420-a885-4969-84c3-448939d8b3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665902967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2665902967
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1348429701
Short name T135
Test name
Test status
Simulation time 35740673 ps
CPU time 0.87 seconds
Started Mar 31 01:12:11 PM PDT 24
Finished Mar 31 01:12:12 PM PDT 24
Peak memory 215628 kb
Host smart-d8cb525d-f54a-48c4-b31d-718b6ed704bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348429701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1348429701
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1346315739
Short name T756
Test name
Test status
Simulation time 44942779 ps
CPU time 0.86 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:11:58 PM PDT 24
Peak memory 215336 kb
Host smart-b60a5203-d49b-4a04-845a-df30ec5567a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346315739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1346315739
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.4049482885
Short name T197
Test name
Test status
Simulation time 253633215 ps
CPU time 2.91 seconds
Started Mar 31 01:11:57 PM PDT 24
Finished Mar 31 01:12:00 PM PDT 24
Peak memory 216336 kb
Host smart-a32022a4-c827-4170-b556-33c58c053c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049482885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.4049482885
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1881948272
Short name T183
Test name
Test status
Simulation time 13424191923 ps
CPU time 290.93 seconds
Started Mar 31 01:11:59 PM PDT 24
Finished Mar 31 01:16:50 PM PDT 24
Peak memory 218440 kb
Host smart-198d7abf-976d-4a10-ba09-f680132b7578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881948272 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1881948272
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3741999644
Short name T704
Test name
Test status
Simulation time 38323149 ps
CPU time 1.32 seconds
Started Mar 31 01:10:32 PM PDT 24
Finished Mar 31 01:10:33 PM PDT 24
Peak memory 215580 kb
Host smart-cabf1b4e-b665-451f-bbdb-b1e9a598fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741999644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3741999644
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1593949727
Short name T737
Test name
Test status
Simulation time 135222975 ps
CPU time 0.87 seconds
Started Mar 31 01:10:31 PM PDT 24
Finished Mar 31 01:10:32 PM PDT 24
Peak memory 205520 kb
Host smart-e26f437c-6f8c-49d9-ac4a-135ddeb5348c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593949727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1593949727
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.138937194
Short name T180
Test name
Test status
Simulation time 21864272 ps
CPU time 0.88 seconds
Started Mar 31 01:10:32 PM PDT 24
Finished Mar 31 01:10:33 PM PDT 24
Peak memory 215940 kb
Host smart-cf5b1803-feab-417e-9fe8-867f953b306a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138937194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.138937194
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2958215870
Short name T701
Test name
Test status
Simulation time 56866980 ps
CPU time 1.23 seconds
Started Mar 31 01:10:30 PM PDT 24
Finished Mar 31 01:10:32 PM PDT 24
Peak memory 218712 kb
Host smart-c7bf411d-256e-4870-9bbf-23ea89e6e04f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958215870 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2958215870
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3983338698
Short name T15
Test name
Test status
Simulation time 76254083 ps
CPU time 1.18 seconds
Started Mar 31 01:10:34 PM PDT 24
Finished Mar 31 01:10:36 PM PDT 24
Peak memory 224164 kb
Host smart-d86d1b06-c4d5-478d-9915-a4b5c74f994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983338698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3983338698
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2837006790
Short name T577
Test name
Test status
Simulation time 63878639 ps
CPU time 1.25 seconds
Started Mar 31 01:10:33 PM PDT 24
Finished Mar 31 01:10:34 PM PDT 24
Peak memory 217704 kb
Host smart-a0b5602f-d8d6-4118-a11c-71b7d9aae532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837006790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2837006790
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3625338429
Short name T416
Test name
Test status
Simulation time 22169866 ps
CPU time 1.15 seconds
Started Mar 31 01:10:30 PM PDT 24
Finished Mar 31 01:10:31 PM PDT 24
Peak memory 224148 kb
Host smart-dbb195a3-ad26-4cb4-9d2b-cc88f11c1c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625338429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3625338429
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.136504243
Short name T132
Test name
Test status
Simulation time 27950056 ps
CPU time 1.02 seconds
Started Mar 31 01:10:24 PM PDT 24
Finished Mar 31 01:10:25 PM PDT 24
Peak memory 207060 kb
Host smart-d56b0d09-ea79-49ee-9295-fc97d3e07cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136504243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.136504243
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3082313797
Short name T21
Test name
Test status
Simulation time 712404179 ps
CPU time 5.87 seconds
Started Mar 31 01:10:34 PM PDT 24
Finished Mar 31 01:10:40 PM PDT 24
Peak memory 234380 kb
Host smart-a4781717-c0b3-4466-b674-4e6aa8c48519
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082313797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3082313797
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.577100803
Short name T546
Test name
Test status
Simulation time 19252930 ps
CPU time 0.96 seconds
Started Mar 31 01:10:25 PM PDT 24
Finished Mar 31 01:10:26 PM PDT 24
Peak memory 215264 kb
Host smart-e372b239-c60d-40cc-8a7a-a0c3d305d161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577100803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.577100803
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4224486149
Short name T442
Test name
Test status
Simulation time 38639589 ps
CPU time 1.29 seconds
Started Mar 31 01:10:30 PM PDT 24
Finished Mar 31 01:10:32 PM PDT 24
Peak memory 215524 kb
Host smart-aa717b11-2b27-4c62-bdba-340dbafd3b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224486149 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4224486149
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1352263212
Short name T191
Test name
Test status
Simulation time 82507268183 ps
CPU time 1834.23 seconds
Started Mar 31 01:10:33 PM PDT 24
Finished Mar 31 01:41:07 PM PDT 24
Peak memory 224964 kb
Host smart-0d9caa42-e32c-4ea2-bbfe-aef2a4736155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352263212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1352263212
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1296711968
Short name T277
Test name
Test status
Simulation time 24357630 ps
CPU time 1.32 seconds
Started Mar 31 01:11:56 PM PDT 24
Finished Mar 31 01:11:57 PM PDT 24
Peak memory 215640 kb
Host smart-da474140-8d40-46a3-89b3-0cf26c4099a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296711968 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1296711968
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1993607752
Short name T461
Test name
Test status
Simulation time 20562547 ps
CPU time 1.01 seconds
Started Mar 31 01:11:58 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 206108 kb
Host smart-e7fd35e2-8465-432e-963f-2e0d07f5ba57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993607752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1993607752
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.559463847
Short name T169
Test name
Test status
Simulation time 27720781 ps
CPU time 0.8 seconds
Started Mar 31 01:11:58 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 216008 kb
Host smart-88ce46d5-c5c6-488d-a972-8bd59bf0ce7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559463847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.559463847
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4038809388
Short name T387
Test name
Test status
Simulation time 44587873 ps
CPU time 1.39 seconds
Started Mar 31 01:11:59 PM PDT 24
Finished Mar 31 01:12:01 PM PDT 24
Peak memory 218716 kb
Host smart-852629ee-55a7-4486-975f-cf931545a07d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038809388 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4038809388
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3928964936
Short name T445
Test name
Test status
Simulation time 28406516 ps
CPU time 0.89 seconds
Started Mar 31 01:11:58 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 217784 kb
Host smart-9ceac9e5-e09c-4e3e-bc8a-a4ae32e1c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928964936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3928964936
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.131644338
Short name T529
Test name
Test status
Simulation time 22392030 ps
CPU time 1.19 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 224080 kb
Host smart-1f140b71-fbd3-406a-ad42-36c2d76fc67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131644338 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.131644338
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1520774989
Short name T731
Test name
Test status
Simulation time 29251606 ps
CPU time 0.94 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:11:56 PM PDT 24
Peak memory 215264 kb
Host smart-ed4fb6fb-d971-4358-9bb9-53c002024001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520774989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1520774989
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2897626345
Short name T310
Test name
Test status
Simulation time 72983243 ps
CPU time 0.99 seconds
Started Mar 31 01:11:58 PM PDT 24
Finished Mar 31 01:11:59 PM PDT 24
Peak memory 215248 kb
Host smart-472892f4-9301-4e1a-91fe-44922de99759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897626345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2897626345
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2202844712
Short name T467
Test name
Test status
Simulation time 55695477096 ps
CPU time 624.8 seconds
Started Mar 31 01:11:55 PM PDT 24
Finished Mar 31 01:22:20 PM PDT 24
Peak memory 217956 kb
Host smart-93abd942-5fb0-454c-93f2-fcb682c4cf25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202844712 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2202844712
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.376570595
Short name T811
Test name
Test status
Simulation time 52103558 ps
CPU time 1.31 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 215620 kb
Host smart-750ecbf6-fddc-45b5-830b-3c38caa41fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376570595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.376570595
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1870458794
Short name T663
Test name
Test status
Simulation time 199843267 ps
CPU time 1.04 seconds
Started Mar 31 01:12:05 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 205952 kb
Host smart-942f2294-6324-4e3b-b518-926a3819f416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870458794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1870458794
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2732117270
Short name T334
Test name
Test status
Simulation time 31404243 ps
CPU time 0.84 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:05 PM PDT 24
Peak memory 215504 kb
Host smart-4bf3a872-7568-41d9-98e0-607560bd12d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732117270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2732117270
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.908822388
Short name T75
Test name
Test status
Simulation time 44198040 ps
CPU time 1.14 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 216452 kb
Host smart-e55698af-fa7c-4f9c-b70c-ad03a202c971
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908822388 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.908822388
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.995148227
Short name T356
Test name
Test status
Simulation time 19083183 ps
CPU time 1.12 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 215356 kb
Host smart-d0ccbcd6-c0af-47fb-ba19-5682b1d457b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995148227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.995148227
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.4074082313
Short name T582
Test name
Test status
Simulation time 42985206 ps
CPU time 1.72 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 217756 kb
Host smart-99061014-9354-4bc5-bc6b-c3855929a897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074082313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4074082313
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3284078667
Short name T134
Test name
Test status
Simulation time 24230656 ps
CPU time 0.97 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 215656 kb
Host smart-dbc652c2-6780-452b-9c6f-f0051c8d8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284078667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3284078667
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3523188020
Short name T245
Test name
Test status
Simulation time 32977252 ps
CPU time 0.93 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 215216 kb
Host smart-2207bab1-bc7b-4ff7-a791-3f88d369f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523188020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3523188020
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4041056691
Short name T643
Test name
Test status
Simulation time 483295226 ps
CPU time 2.71 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 215324 kb
Host smart-b247e9fb-f805-44a0-995a-09032ed54795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041056691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4041056691
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2249200905
Short name T353
Test name
Test status
Simulation time 73418207719 ps
CPU time 1826.42 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:42:29 PM PDT 24
Peak memory 227280 kb
Host smart-23f585be-c7a2-4c89-bc9b-6025448742c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249200905 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2249200905
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1417499433
Short name T579
Test name
Test status
Simulation time 25845212 ps
CPU time 1.25 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 215580 kb
Host smart-1a47bd36-7548-4613-92ba-260c16721129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417499433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1417499433
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3993650645
Short name T422
Test name
Test status
Simulation time 24990291 ps
CPU time 1.01 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 205948 kb
Host smart-8bd4d23d-beef-412d-a4ec-634489ea68d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993650645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3993650645
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3478612377
Short name T321
Test name
Test status
Simulation time 29699669 ps
CPU time 0.88 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:05 PM PDT 24
Peak memory 215484 kb
Host smart-8d303a82-2a02-43e9-b7e6-3fac429005ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478612377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3478612377
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_genbits.570399171
Short name T377
Test name
Test status
Simulation time 72259676 ps
CPU time 1.65 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 219588 kb
Host smart-989c581f-2541-4eb8-823d-90fe0baa021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570399171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.570399171
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.285746143
Short name T523
Test name
Test status
Simulation time 35559203 ps
CPU time 1.06 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 224032 kb
Host smart-6e3d34a8-afd3-4a87-9ca5-02b9766df9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285746143 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.285746143
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3549591351
Short name T622
Test name
Test status
Simulation time 115596902 ps
CPU time 0.94 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 215256 kb
Host smart-5c9d5f77-f5d1-45d9-80eb-dd86bf1e9f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549591351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3549591351
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2786597923
Short name T608
Test name
Test status
Simulation time 1129752720 ps
CPU time 4.46 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:09 PM PDT 24
Peak memory 215340 kb
Host smart-d7ce95ed-e0c9-4338-a46b-3f1d5d2d4aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786597923 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2786597923
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.865190145
Short name T780
Test name
Test status
Simulation time 37504119479 ps
CPU time 934.26 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 223632 kb
Host smart-f1be76dd-97b6-4a4b-a1b1-eaa535c666d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865190145 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.865190145
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2233332055
Short name T281
Test name
Test status
Simulation time 79129790 ps
CPU time 1.35 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 215640 kb
Host smart-621fa265-153f-4e09-8ca6-b0d025d07700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233332055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2233332055
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1169825501
Short name T411
Test name
Test status
Simulation time 16217147 ps
CPU time 0.98 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 206820 kb
Host smart-ba36a9f3-c951-4666-9ae9-4100d58e390d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169825501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1169825501
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2620153024
Short name T97
Test name
Test status
Simulation time 11788292 ps
CPU time 0.89 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:05 PM PDT 24
Peak memory 215356 kb
Host smart-fe7fe8c2-ae19-4896-bc9d-02b0aa98fe28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620153024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2620153024
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4247131647
Short name T498
Test name
Test status
Simulation time 29580561 ps
CPU time 0.92 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 216540 kb
Host smart-de6a3f23-e9b3-4ebb-a959-ef637871b0f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247131647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4247131647
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2260084407
Short name T752
Test name
Test status
Simulation time 23125932 ps
CPU time 1.08 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:05 PM PDT 24
Peak memory 231336 kb
Host smart-eda830c5-5ade-4c05-99c9-7cd84c9536d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260084407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2260084407
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2431031671
Short name T522
Test name
Test status
Simulation time 43464469 ps
CPU time 1.67 seconds
Started Mar 31 01:12:02 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 217760 kb
Host smart-1e24a4c9-10a3-4a0a-8379-386944913d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431031671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2431031671
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3761702424
Short name T138
Test name
Test status
Simulation time 20334147 ps
CPU time 1.08 seconds
Started Mar 31 01:12:01 PM PDT 24
Finished Mar 31 01:12:02 PM PDT 24
Peak memory 215580 kb
Host smart-76027100-f1aa-4219-95ae-75fbd08436bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761702424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3761702424
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3002671492
Short name T314
Test name
Test status
Simulation time 24939962 ps
CPU time 0.94 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 215268 kb
Host smart-7d87075f-52f8-4e6b-a0be-0e89f5e5b91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002671492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3002671492
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1769435938
Short name T633
Test name
Test status
Simulation time 40263563 ps
CPU time 1.41 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:12:05 PM PDT 24
Peak memory 215244 kb
Host smart-5db7edb8-7e84-4838-af88-67299d1c5f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769435938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1769435938
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3288759642
Short name T190
Test name
Test status
Simulation time 13388060994 ps
CPU time 305.15 seconds
Started Mar 31 01:12:04 PM PDT 24
Finished Mar 31 01:17:09 PM PDT 24
Peak memory 223740 kb
Host smart-7bf555ea-a5cf-402a-9cc3-73a627ae4adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288759642 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3288759642
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1553400231
Short name T676
Test name
Test status
Simulation time 80772165 ps
CPU time 1.24 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 215572 kb
Host smart-03a2087c-d290-465f-a8d4-157989684ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553400231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1553400231
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.4202470995
Short name T611
Test name
Test status
Simulation time 15919759 ps
CPU time 0.87 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:15 PM PDT 24
Peak memory 205972 kb
Host smart-e49cedc6-fea5-4f19-b2a7-838483deb36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202470995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4202470995
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2794312064
Short name T80
Test name
Test status
Simulation time 43844562 ps
CPU time 1.41 seconds
Started Mar 31 01:12:11 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 216440 kb
Host smart-32716820-9952-494f-91c5-ad94c7adcc99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794312064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2794312064
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3010408295
Short name T115
Test name
Test status
Simulation time 32167135 ps
CPU time 1.02 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 232436 kb
Host smart-07110814-322d-4606-b2c5-0b9ddb034eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010408295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3010408295
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3664690948
Short name T520
Test name
Test status
Simulation time 53055342 ps
CPU time 1.31 seconds
Started Mar 31 01:12:10 PM PDT 24
Finished Mar 31 01:12:11 PM PDT 24
Peak memory 216812 kb
Host smart-6a64dd46-6f42-4aee-ac28-616c084bf318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664690948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3664690948
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2938039620
Short name T383
Test name
Test status
Simulation time 30466230 ps
CPU time 0.93 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:15 PM PDT 24
Peak memory 223880 kb
Host smart-998e865d-70d5-4211-8306-7be154d3a6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938039620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2938039620
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3412208820
Short name T764
Test name
Test status
Simulation time 51849585 ps
CPU time 0.99 seconds
Started Mar 31 01:12:03 PM PDT 24
Finished Mar 31 01:12:04 PM PDT 24
Peak memory 215280 kb
Host smart-57e6c1ee-883f-4f53-81be-a0e5de45a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412208820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3412208820
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3994263629
Short name T400
Test name
Test status
Simulation time 1205770394 ps
CPU time 4.1 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 216536 kb
Host smart-c314e38f-4bf4-4e17-9384-be4ee4493502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994263629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3994263629
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2952125866
Short name T781
Test name
Test status
Simulation time 70577233574 ps
CPU time 1625.04 seconds
Started Mar 31 01:12:13 PM PDT 24
Finished Mar 31 01:39:18 PM PDT 24
Peak memory 223620 kb
Host smart-b6046ca5-56be-4ec2-b5eb-27cd5141ebd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952125866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2952125866
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2920941666
Short name T18
Test name
Test status
Simulation time 26239378 ps
CPU time 1.26 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 215604 kb
Host smart-acdaaee5-642a-4bc8-9543-2fccc10419a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920941666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2920941666
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.572768822
Short name T435
Test name
Test status
Simulation time 187912017 ps
CPU time 0.99 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 205976 kb
Host smart-2ed5b3ca-7ff9-4679-87f6-d2efff98a370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572768822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.572768822
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1778356908
Short name T111
Test name
Test status
Simulation time 72764268 ps
CPU time 0.84 seconds
Started Mar 31 01:12:08 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 215836 kb
Host smart-67523150-54f3-4aa1-9285-afa638c821a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778356908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1778356908
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2419088492
Short name T89
Test name
Test status
Simulation time 86555328 ps
CPU time 1.24 seconds
Started Mar 31 01:12:10 PM PDT 24
Finished Mar 31 01:12:11 PM PDT 24
Peak memory 216332 kb
Host smart-11fd1895-19dd-4f7f-8f63-b822fbef3c55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419088492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2419088492
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2620535322
Short name T758
Test name
Test status
Simulation time 19641063 ps
CPU time 0.98 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 218012 kb
Host smart-42fcdf90-c357-456f-a284-986935426c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620535322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2620535322
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.371834359
Short name T808
Test name
Test status
Simulation time 118950630 ps
CPU time 1.18 seconds
Started Mar 31 01:12:10 PM PDT 24
Finished Mar 31 01:12:11 PM PDT 24
Peak memory 216680 kb
Host smart-44074300-fbf5-4376-92b4-cab556264688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371834359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.371834359
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4043126708
Short name T122
Test name
Test status
Simulation time 52963787 ps
CPU time 0.88 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 215288 kb
Host smart-b84a2324-fb26-498e-9ad8-8a1dc84a03a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043126708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4043126708
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1411838374
Short name T547
Test name
Test status
Simulation time 49119105 ps
CPU time 0.87 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:15 PM PDT 24
Peak memory 215292 kb
Host smart-1e7fa555-7ee2-4290-bc01-e6ec4a74dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411838374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1411838374
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3247258749
Short name T328
Test name
Test status
Simulation time 403708364 ps
CPU time 4.37 seconds
Started Mar 31 01:12:11 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 216768 kb
Host smart-b1edd606-bd47-4df9-892c-b4ba2b4b986f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247258749 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3247258749
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3485067463
Short name T585
Test name
Test status
Simulation time 49121533270 ps
CPU time 1277.91 seconds
Started Mar 31 01:12:10 PM PDT 24
Finished Mar 31 01:33:28 PM PDT 24
Peak memory 223744 kb
Host smart-d8be6ad4-a512-45e3-9ed1-53da6ff65867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485067463 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3485067463
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3027597104
Short name T268
Test name
Test status
Simulation time 26309104 ps
CPU time 1.19 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:11 PM PDT 24
Peak memory 215640 kb
Host smart-9603e119-06d4-43e9-aae9-5bd77d57bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027597104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3027597104
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3661641855
Short name T757
Test name
Test status
Simulation time 17462087 ps
CPU time 0.92 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 205928 kb
Host smart-45e105b0-121d-4507-a429-250f6b0e0e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661641855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3661641855
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.321066609
Short name T109
Test name
Test status
Simulation time 13527832 ps
CPU time 0.88 seconds
Started Mar 31 01:12:11 PM PDT 24
Finished Mar 31 01:12:12 PM PDT 24
Peak memory 215836 kb
Host smart-814af9d0-a609-45bd-a721-0a2c350b1823
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321066609 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.321066609
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.885070092
Short name T415
Test name
Test status
Simulation time 126594408 ps
CPU time 1.36 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 217552 kb
Host smart-fe34afb6-470f-48fb-973b-5a8f6a34c42b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885070092 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.885070092
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.398978487
Short name T616
Test name
Test status
Simulation time 31203971 ps
CPU time 0.85 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 217980 kb
Host smart-f819aa9f-956e-4f26-9cac-cc27f6b5ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398978487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.398978487
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3245642176
Short name T525
Test name
Test status
Simulation time 470523762 ps
CPU time 3.63 seconds
Started Mar 31 01:12:08 PM PDT 24
Finished Mar 31 01:12:12 PM PDT 24
Peak memory 217024 kb
Host smart-6c95aafc-7786-4359-a518-e3d24bf531ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245642176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3245642176
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2360042638
Short name T123
Test name
Test status
Simulation time 24220853 ps
CPU time 1 seconds
Started Mar 31 01:12:07 PM PDT 24
Finished Mar 31 01:12:08 PM PDT 24
Peak memory 215636 kb
Host smart-2bd18896-3445-4aa8-9093-d4b5db92f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360042638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2360042638
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3710867915
Short name T789
Test name
Test status
Simulation time 108135783 ps
CPU time 0.89 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 215104 kb
Host smart-cd38a35a-f540-4896-b274-223c6fcea835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710867915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3710867915
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2812984324
Short name T494
Test name
Test status
Simulation time 231861212 ps
CPU time 5 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 216484 kb
Host smart-8b701758-7c93-47f9-8bd2-f3b12ce0c1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812984324 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2812984324
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3659385174
Short name T526
Test name
Test status
Simulation time 31346637547 ps
CPU time 727.77 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:24:22 PM PDT 24
Peak memory 221704 kb
Host smart-d84ab695-3238-477e-afeb-6d88a5565830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659385174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3659385174
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2430814754
Short name T272
Test name
Test status
Simulation time 26800968 ps
CPU time 1.19 seconds
Started Mar 31 01:12:07 PM PDT 24
Finished Mar 31 01:12:08 PM PDT 24
Peak memory 215620 kb
Host smart-1c16e1ec-e786-499a-8ffc-16986b42b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430814754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2430814754
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1999029744
Short name T538
Test name
Test status
Simulation time 49367480 ps
CPU time 0.91 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 206740 kb
Host smart-f961b0bb-1a8e-43ef-a010-9c1253ab2d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999029744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1999029744
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1154457028
Short name T648
Test name
Test status
Simulation time 15250367 ps
CPU time 0.87 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 215832 kb
Host smart-f2750c27-a83d-4393-9247-4da600cc2e8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154457028 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1154457028
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4160188115
Short name T488
Test name
Test status
Simulation time 32458549 ps
CPU time 1.2 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 216300 kb
Host smart-a47005e3-770c-4d89-9190-49461d8d76c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160188115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4160188115
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3379990632
Short name T729
Test name
Test status
Simulation time 22973639 ps
CPU time 1.28 seconds
Started Mar 31 01:12:10 PM PDT 24
Finished Mar 31 01:12:11 PM PDT 24
Peak memory 232624 kb
Host smart-1eaf89c1-b26d-4bd3-a74f-1eb5c679cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379990632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3379990632
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2378152195
Short name T539
Test name
Test status
Simulation time 71582913 ps
CPU time 1.35 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:14 PM PDT 24
Peak memory 216456 kb
Host smart-3e894354-0302-47f8-a18a-bf3de32b6a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378152195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2378152195
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2635216312
Short name T136
Test name
Test status
Simulation time 35498727 ps
CPU time 0.89 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:13 PM PDT 24
Peak memory 215492 kb
Host smart-74cfb964-4e36-4877-80e0-b74150a1a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635216312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2635216312
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1886501931
Short name T288
Test name
Test status
Simulation time 187322853 ps
CPU time 0.85 seconds
Started Mar 31 01:12:09 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 215288 kb
Host smart-d33e20f9-2eaa-4a86-bc37-74d60d72dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886501931 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1886501931
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.353507327
Short name T710
Test name
Test status
Simulation time 225822348 ps
CPU time 4.46 seconds
Started Mar 31 01:12:12 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 216568 kb
Host smart-8c7c2d75-9d10-48ef-b86a-69bfad41e1b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353507327 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.353507327
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.301107039
Short name T583
Test name
Test status
Simulation time 73108894261 ps
CPU time 915.14 seconds
Started Mar 31 01:12:13 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 221944 kb
Host smart-0b63f4a7-1ada-424a-84c4-7746d327025a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301107039 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.301107039
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.825647143
Short name T71
Test name
Test status
Simulation time 75790439 ps
CPU time 1.21 seconds
Started Mar 31 01:12:18 PM PDT 24
Finished Mar 31 01:12:19 PM PDT 24
Peak memory 215600 kb
Host smart-9905897f-7cc5-4f0c-8acb-60a97214a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825647143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.825647143
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1217330953
Short name T333
Test name
Test status
Simulation time 52594293 ps
CPU time 0.88 seconds
Started Mar 31 01:12:18 PM PDT 24
Finished Mar 31 01:12:19 PM PDT 24
Peak memory 205912 kb
Host smart-eea80bb3-334c-4bc7-92d2-5476f23e195b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217330953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1217330953
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.4046838453
Short name T96
Test name
Test status
Simulation time 12681279 ps
CPU time 0.92 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:20 PM PDT 24
Peak memory 215612 kb
Host smart-38e18f35-b712-4337-b16b-7643b4ded43f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046838453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4046838453
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.741685844
Short name T405
Test name
Test status
Simulation time 281774987 ps
CPU time 1.01 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 219280 kb
Host smart-f33b2111-4382-448e-952a-bf7c25d05e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741685844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.741685844
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4071988201
Short name T760
Test name
Test status
Simulation time 80851350 ps
CPU time 1.58 seconds
Started Mar 31 01:12:18 PM PDT 24
Finished Mar 31 01:12:19 PM PDT 24
Peak memory 218124 kb
Host smart-3bb07969-9ba0-4bcb-a6ee-8f9b100f6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071988201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4071988201
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3869919676
Short name T500
Test name
Test status
Simulation time 20394819 ps
CPU time 1.21 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 224060 kb
Host smart-14c8dc95-e30f-4157-96b1-fec9cc8375f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869919676 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3869919676
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1841960703
Short name T143
Test name
Test status
Simulation time 51707971 ps
CPU time 0.96 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:18 PM PDT 24
Peak memory 215272 kb
Host smart-455acfb7-3b02-46bb-acf3-f1d5e7d44641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841960703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1841960703
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1353098064
Short name T736
Test name
Test status
Simulation time 390962516 ps
CPU time 7.93 seconds
Started Mar 31 01:12:17 PM PDT 24
Finished Mar 31 01:12:25 PM PDT 24
Peak memory 217940 kb
Host smart-50019388-8606-4044-a98f-91bdfbb2607a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353098064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1353098064
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.942871768
Short name T380
Test name
Test status
Simulation time 288034830444 ps
CPU time 611.48 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:22:28 PM PDT 24
Peak memory 218632 kb
Host smart-566a57b4-a2be-4cce-9464-2336eec3a835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942871768 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.942871768
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.863055320
Short name T16
Test name
Test status
Simulation time 50518042 ps
CPU time 1.15 seconds
Started Mar 31 01:12:18 PM PDT 24
Finished Mar 31 01:12:20 PM PDT 24
Peak memory 215648 kb
Host smart-bbf191b0-d6a2-4d8a-b5ef-5eab1a7e8173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863055320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.863055320
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1319231525
Short name T390
Test name
Test status
Simulation time 17355340 ps
CPU time 0.95 seconds
Started Mar 31 01:12:17 PM PDT 24
Finished Mar 31 01:12:18 PM PDT 24
Peak memory 205944 kb
Host smart-757a72a0-da74-4cd5-a0e1-eb7c4b7fa65e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319231525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1319231525
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3708640606
Short name T471
Test name
Test status
Simulation time 18708708 ps
CPU time 0.83 seconds
Started Mar 31 01:12:17 PM PDT 24
Finished Mar 31 01:12:18 PM PDT 24
Peak memory 215808 kb
Host smart-62711c7e-1311-4204-b518-35fed7a5e306
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708640606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3708640606
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.1577347456
Short name T91
Test name
Test status
Simulation time 27076162 ps
CPU time 1.3 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 217040 kb
Host smart-906f1a8d-fce3-49df-acec-d333e178c0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577347456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1577347456
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2355938309
Short name T250
Test name
Test status
Simulation time 42754830 ps
CPU time 1.47 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 217848 kb
Host smart-b3231d8f-d4ad-4ed6-8413-85867de7b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355938309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2355938309
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1739834071
Short name T686
Test name
Test status
Simulation time 26931274 ps
CPU time 0.96 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 215424 kb
Host smart-9e6d9981-4d52-4af8-bba6-d2e7b8067a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739834071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1739834071
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1887675153
Short name T598
Test name
Test status
Simulation time 26699168 ps
CPU time 0.95 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 215216 kb
Host smart-7139aa1f-b17b-4d3e-8c16-357dd8141c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887675153 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1887675153
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3365571253
Short name T153
Test name
Test status
Simulation time 137099442 ps
CPU time 1.29 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:18 PM PDT 24
Peak memory 217764 kb
Host smart-c29dcd58-b4cd-4fdb-a94f-935e07a9686e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365571253 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3365571253
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3756356
Short name T620
Test name
Test status
Simulation time 38476078738 ps
CPU time 983.09 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:28:38 PM PDT 24
Peak memory 219772 kb
Host smart-5e52d915-0b7d-4065-8327-41f0a12d1869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756356 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3756356
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3814574231
Short name T170
Test name
Test status
Simulation time 44710566 ps
CPU time 1.25 seconds
Started Mar 31 01:10:38 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 215532 kb
Host smart-dad06735-272f-46b5-a088-71380db54d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814574231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3814574231
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.474421193
Short name T536
Test name
Test status
Simulation time 15929937 ps
CPU time 0.99 seconds
Started Mar 31 01:10:38 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 206768 kb
Host smart-212758e7-da12-4cb6-bc1e-7bd72348ab00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474421193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.474421193
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1061402207
Short name T100
Test name
Test status
Simulation time 31214736 ps
CPU time 0.82 seconds
Started Mar 31 01:10:38 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 215976 kb
Host smart-3e481aa4-4ffa-467f-a642-8d9aa4419150
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061402207 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1061402207
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.3849462289
Short name T596
Test name
Test status
Simulation time 32417450 ps
CPU time 0.91 seconds
Started Mar 31 01:10:38 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 217732 kb
Host smart-8697d087-a4a1-4881-9856-e21e2e526e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849462289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3849462289
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3013701964
Short name T487
Test name
Test status
Simulation time 39310944 ps
CPU time 1.37 seconds
Started Mar 31 01:10:28 PM PDT 24
Finished Mar 31 01:10:30 PM PDT 24
Peak memory 216704 kb
Host smart-047351cd-5840-4163-ac88-fdca4765e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013701964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3013701964
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1697820940
Short name T773
Test name
Test status
Simulation time 23297392 ps
CPU time 0.93 seconds
Started Mar 31 01:10:31 PM PDT 24
Finished Mar 31 01:10:32 PM PDT 24
Peak memory 215672 kb
Host smart-e7fbc11a-7718-4227-9fac-6d9af4f184b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697820940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1697820940
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.3004363255
Short name T562
Test name
Test status
Simulation time 17339625 ps
CPU time 1.04 seconds
Started Mar 31 01:10:34 PM PDT 24
Finished Mar 31 01:10:35 PM PDT 24
Peak memory 215228 kb
Host smart-57c9b769-0c6f-423e-b582-ea5a5d0226d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004363255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3004363255
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.21527029
Short name T630
Test name
Test status
Simulation time 375457997 ps
CPU time 2.89 seconds
Started Mar 31 01:10:29 PM PDT 24
Finished Mar 31 01:10:32 PM PDT 24
Peak memory 216484 kb
Host smart-fe4e2f39-e27d-47c8-8c87-e6e855ea164c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21527029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.21527029
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3010608280
Short name T24
Test name
Test status
Simulation time 123390316952 ps
CPU time 1372.13 seconds
Started Mar 31 01:10:32 PM PDT 24
Finished Mar 31 01:33:25 PM PDT 24
Peak memory 223100 kb
Host smart-1233b577-2ea8-4b59-b710-e09da221f56d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010608280 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3010608280
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3244793772
Short name T157
Test name
Test status
Simulation time 95453010 ps
CPU time 1.11 seconds
Started Mar 31 01:12:20 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 219064 kb
Host smart-2ebc386d-844e-43df-8ad8-62bfbe2bd715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244793772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3244793772
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1476646003
Short name T640
Test name
Test status
Simulation time 53739331 ps
CPU time 1.55 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 217712 kb
Host smart-29517f35-dddb-41c5-998e-2694023ce011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476646003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1476646003
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2667202163
Short name T85
Test name
Test status
Simulation time 25051432 ps
CPU time 1.16 seconds
Started Mar 31 01:12:20 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 219268 kb
Host smart-4b01ad5e-3b1d-472a-b475-1f502500df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667202163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2667202163
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.3920135455
Short name T299
Test name
Test status
Simulation time 41030702 ps
CPU time 0.82 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:15 PM PDT 24
Peak memory 217600 kb
Host smart-4bf50527-f532-48fb-ad01-ad98e45faba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920135455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3920135455
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3328814748
Short name T698
Test name
Test status
Simulation time 181169865 ps
CPU time 1 seconds
Started Mar 31 01:12:15 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 216464 kb
Host smart-4f036b99-d39d-4294-a851-8b898d59d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328814748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3328814748
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3187362640
Short name T682
Test name
Test status
Simulation time 45252408 ps
CPU time 0.99 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 219344 kb
Host smart-ed5bd3bf-27ca-4ba5-8407-affaa4226114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187362640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3187362640
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1602680846
Short name T724
Test name
Test status
Simulation time 47342065 ps
CPU time 1.22 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:20 PM PDT 24
Peak memory 216600 kb
Host smart-e9a21585-3131-4e19-b12a-d8a4115ef7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602680846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1602680846
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_genbits.2241070411
Short name T345
Test name
Test status
Simulation time 37603958 ps
CPU time 1.08 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 219160 kb
Host smart-6a1d0a8c-d67a-46ad-b731-4515a8687fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241070411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2241070411
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.313598994
Short name T41
Test name
Test status
Simulation time 39930751 ps
CPU time 0.98 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 222908 kb
Host smart-51b68692-3b60-49df-a8d3-c524a10e3c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313598994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.313598994
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.2974346477
Short name T421
Test name
Test status
Simulation time 21432448 ps
CPU time 0.96 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 215476 kb
Host smart-ee90fc07-133c-4d44-9852-5d66fc869676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974346477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2974346477
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2281405978
Short name T3
Test name
Test status
Simulation time 47069073 ps
CPU time 1.6 seconds
Started Mar 31 01:12:18 PM PDT 24
Finished Mar 31 01:12:20 PM PDT 24
Peak memory 217856 kb
Host smart-542ee9a6-8e61-412a-b330-6710a51162e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281405978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2281405978
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.897517959
Short name T600
Test name
Test status
Simulation time 20208350 ps
CPU time 1.27 seconds
Started Mar 31 01:12:19 PM PDT 24
Finished Mar 31 01:12:20 PM PDT 24
Peak memory 229800 kb
Host smart-c5dd395a-176e-4ec7-8008-d667aeb91848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897517959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.897517959
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1433999328
Short name T634
Test name
Test status
Simulation time 76656906 ps
CPU time 1.16 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 219144 kb
Host smart-e93c46b3-2b04-4075-9d87-82f12fcbe817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433999328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1433999328
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.4271630991
Short name T84
Test name
Test status
Simulation time 20278694 ps
CPU time 1.23 seconds
Started Mar 31 01:12:16 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 229732 kb
Host smart-e605ebbf-5320-40f0-bfe6-d6dccc4e0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271630991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4271630991
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1133856705
Short name T28
Test name
Test status
Simulation time 95407148 ps
CPU time 1.18 seconds
Started Mar 31 01:12:17 PM PDT 24
Finished Mar 31 01:12:18 PM PDT 24
Peak memory 216680 kb
Host smart-49d3b64d-166b-4fb4-b434-faa747a9d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133856705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1133856705
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2298343131
Short name T807
Test name
Test status
Simulation time 19471236 ps
CPU time 1.09 seconds
Started Mar 31 01:12:27 PM PDT 24
Finished Mar 31 01:12:29 PM PDT 24
Peak memory 218156 kb
Host smart-998f736a-a593-41d6-9cc6-979d15af5e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298343131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2298343131
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2590067894
Short name T332
Test name
Test status
Simulation time 45479656 ps
CPU time 1.6 seconds
Started Mar 31 01:12:14 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 216668 kb
Host smart-8a1b2d51-b0b2-4e90-b8a4-4969bf34741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590067894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2590067894
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4189582167
Short name T274
Test name
Test status
Simulation time 63799722 ps
CPU time 1.13 seconds
Started Mar 31 01:10:37 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 215624 kb
Host smart-1251ccf6-a5ca-4253-bb53-ea25ce9ea194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189582167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4189582167
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1256937579
Short name T601
Test name
Test status
Simulation time 42771617 ps
CPU time 0.91 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 205964 kb
Host smart-c860e1ec-63bc-411a-b770-97fe2a498cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256937579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1256937579
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3101473213
Short name T692
Test name
Test status
Simulation time 43219076 ps
CPU time 0.85 seconds
Started Mar 31 01:10:40 PM PDT 24
Finished Mar 31 01:10:41 PM PDT 24
Peak memory 215804 kb
Host smart-bdc963e9-7033-4496-a6c3-cc2de8e9fc7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101473213 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3101473213
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.255442570
Short name T229
Test name
Test status
Simulation time 50345690 ps
CPU time 1.34 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:45 PM PDT 24
Peak memory 216352 kb
Host smart-f48dc4f2-bbbf-4595-a0af-f7d0516bdd93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255442570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.255442570
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1092612502
Short name T765
Test name
Test status
Simulation time 22446291 ps
CPU time 1.18 seconds
Started Mar 31 01:10:39 PM PDT 24
Finished Mar 31 01:10:40 PM PDT 24
Peak memory 231356 kb
Host smart-10e2b53e-2876-45c7-8725-4bb7c62523c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092612502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1092612502
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1897029268
Short name T687
Test name
Test status
Simulation time 78082993 ps
CPU time 1.51 seconds
Started Mar 31 01:10:38 PM PDT 24
Finished Mar 31 01:10:40 PM PDT 24
Peak memory 218212 kb
Host smart-294f8601-5ec6-4341-94e8-cfa442729ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897029268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1897029268
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4125988457
Short name T495
Test name
Test status
Simulation time 39809653 ps
CPU time 0.92 seconds
Started Mar 31 01:10:37 PM PDT 24
Finished Mar 31 01:10:38 PM PDT 24
Peak memory 215344 kb
Host smart-502c897d-6cc7-430a-ae2e-8c4eb232edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125988457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4125988457
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3380281986
Short name T722
Test name
Test status
Simulation time 107156840 ps
CPU time 0.88 seconds
Started Mar 31 01:10:36 PM PDT 24
Finished Mar 31 01:10:37 PM PDT 24
Peak memory 215092 kb
Host smart-57b68ae8-f063-49e4-b024-75ca01a228c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380281986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3380281986
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2386933529
Short name T561
Test name
Test status
Simulation time 398181553 ps
CPU time 4.22 seconds
Started Mar 31 01:10:37 PM PDT 24
Finished Mar 31 01:10:42 PM PDT 24
Peak memory 216640 kb
Host smart-0596ded8-d245-4d17-92d7-f277cff03b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386933529 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2386933529
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1491086645
Short name T188
Test name
Test status
Simulation time 667733973146 ps
CPU time 1002.11 seconds
Started Mar 31 01:10:38 PM PDT 24
Finished Mar 31 01:27:20 PM PDT 24
Peak memory 223632 kb
Host smart-3d8c6d97-93a7-4adf-ad2f-87e3b3cd55cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491086645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1491086645
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.561268019
Short name T700
Test name
Test status
Simulation time 72357194 ps
CPU time 1.07 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 220224 kb
Host smart-5b4bc862-99d9-43c6-ae05-cf6caaeaa658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561268019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.561268019
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3934299280
Short name T512
Test name
Test status
Simulation time 178828018 ps
CPU time 0.97 seconds
Started Mar 31 01:12:25 PM PDT 24
Finished Mar 31 01:12:26 PM PDT 24
Peak memory 216572 kb
Host smart-8f14c4e2-a3cd-4cb7-9b37-3328b00b1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934299280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3934299280
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.435422983
Short name T623
Test name
Test status
Simulation time 36396275 ps
CPU time 1.19 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:30 PM PDT 24
Peak memory 232572 kb
Host smart-4167d9a2-4406-465d-ae9f-c06f30857be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435422983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.435422983
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1510230819
Short name T293
Test name
Test status
Simulation time 38725279 ps
CPU time 1.38 seconds
Started Mar 31 01:12:27 PM PDT 24
Finished Mar 31 01:12:29 PM PDT 24
Peak memory 217676 kb
Host smart-8e4da2d7-efda-4a70-b2d9-63ef1761da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510230819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1510230819
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_genbits.386258948
Short name T604
Test name
Test status
Simulation time 49137020 ps
CPU time 1.52 seconds
Started Mar 31 01:12:26 PM PDT 24
Finished Mar 31 01:12:28 PM PDT 24
Peak memory 217640 kb
Host smart-17e9303b-bcfd-44b7-9252-455356eb9832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386258948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.386258948
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3792952113
Short name T553
Test name
Test status
Simulation time 69022700 ps
CPU time 1.22 seconds
Started Mar 31 01:12:26 PM PDT 24
Finished Mar 31 01:12:27 PM PDT 24
Peak memory 224272 kb
Host smart-c1956f36-ce9d-4754-ac7b-693bca45ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792952113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3792952113
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3208528130
Short name T667
Test name
Test status
Simulation time 125724718 ps
CPU time 1.86 seconds
Started Mar 31 01:12:27 PM PDT 24
Finished Mar 31 01:12:29 PM PDT 24
Peak memory 218108 kb
Host smart-dd7530d1-4150-4ea5-bfdd-e2ee9dd0e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208528130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3208528130
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3705835798
Short name T588
Test name
Test status
Simulation time 29711507 ps
CPU time 1 seconds
Started Mar 31 01:12:26 PM PDT 24
Finished Mar 31 01:12:27 PM PDT 24
Peak memory 231060 kb
Host smart-8b8c6da9-3bee-448e-bbfd-fe4f7ceb5c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705835798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3705835798
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1546726981
Short name T720
Test name
Test status
Simulation time 49679848 ps
CPU time 1.64 seconds
Started Mar 31 01:12:26 PM PDT 24
Finished Mar 31 01:12:28 PM PDT 24
Peak memory 216820 kb
Host smart-18dbafe7-a9ee-49f6-877e-4f32c415032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546726981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1546726981
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3348821150
Short name T42
Test name
Test status
Simulation time 34313078 ps
CPU time 1.03 seconds
Started Mar 31 01:12:25 PM PDT 24
Finished Mar 31 01:12:26 PM PDT 24
Peak memory 231280 kb
Host smart-29c5f2f3-22eb-47cd-965d-23c1e586fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348821150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3348821150
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1348769404
Short name T581
Test name
Test status
Simulation time 45380635 ps
CPU time 1.7 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 217796 kb
Host smart-05763e6e-470d-4af7-a1fd-7771acba7891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348769404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1348769404
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2565954201
Short name T90
Test name
Test status
Simulation time 36849966 ps
CPU time 0.97 seconds
Started Mar 31 01:12:27 PM PDT 24
Finished Mar 31 01:12:28 PM PDT 24
Peak memory 219296 kb
Host smart-77c28732-3767-4fec-bd85-cd2e24df74c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565954201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2565954201
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4221594845
Short name T673
Test name
Test status
Simulation time 60025582 ps
CPU time 1.13 seconds
Started Mar 31 01:12:25 PM PDT 24
Finished Mar 31 01:12:26 PM PDT 24
Peak memory 216720 kb
Host smart-7206fc56-19e4-4841-8e3b-354c4120e038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221594845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4221594845
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1455157872
Short name T558
Test name
Test status
Simulation time 19817126 ps
CPU time 1.07 seconds
Started Mar 31 01:12:25 PM PDT 24
Finished Mar 31 01:12:26 PM PDT 24
Peak memory 232708 kb
Host smart-7ed25c3e-51de-41ff-a2d5-8728689950ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455157872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1455157872
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1608296991
Short name T713
Test name
Test status
Simulation time 156030732 ps
CPU time 1.13 seconds
Started Mar 31 01:12:28 PM PDT 24
Finished Mar 31 01:12:30 PM PDT 24
Peak memory 217860 kb
Host smart-34a2d8a5-4881-4786-8f29-1fc7e72c7207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608296991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1608296991
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1107349844
Short name T8
Test name
Test status
Simulation time 33854174 ps
CPU time 1.13 seconds
Started Mar 31 01:12:26 PM PDT 24
Finished Mar 31 01:12:27 PM PDT 24
Peak memory 232504 kb
Host smart-70567bfc-b21d-4748-a0f4-3f6c9e80c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107349844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1107349844
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3297485842
Short name T343
Test name
Test status
Simulation time 42495147 ps
CPU time 1.1 seconds
Started Mar 31 01:12:26 PM PDT 24
Finished Mar 31 01:12:28 PM PDT 24
Peak memory 216456 kb
Host smart-db835d3a-1803-4579-8bda-60b1ab90cc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297485842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3297485842
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2712043854
Short name T40
Test name
Test status
Simulation time 22368993 ps
CPU time 1.05 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 223112 kb
Host smart-c46173a5-0e53-4173-a06c-9c6538475deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712043854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2712043854
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.495596052
Short name T249
Test name
Test status
Simulation time 32198279 ps
CPU time 1.35 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:30 PM PDT 24
Peak memory 217644 kb
Host smart-ab96ebf6-685a-4cce-86ce-5062c4cf83ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495596052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.495596052
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3899591383
Short name T176
Test name
Test status
Simulation time 52540085 ps
CPU time 1.27 seconds
Started Mar 31 01:10:45 PM PDT 24
Finished Mar 31 01:10:46 PM PDT 24
Peak memory 215616 kb
Host smart-a8133583-9c08-49f6-a0b3-9e528a8eda78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899591383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3899591383
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3220173616
Short name T148
Test name
Test status
Simulation time 15939839 ps
CPU time 0.95 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:44 PM PDT 24
Peak memory 205944 kb
Host smart-c62d7395-624b-4831-ad16-ca207558ee02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220173616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3220173616
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.417247037
Short name T163
Test name
Test status
Simulation time 43571162 ps
CPU time 0.84 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:44 PM PDT 24
Peak memory 215788 kb
Host smart-015ae902-7837-4c8e-b031-9a766337a63a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417247037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.417247037
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.1007639703
Short name T66
Test name
Test status
Simulation time 19193410 ps
CPU time 1.05 seconds
Started Mar 31 01:10:44 PM PDT 24
Finished Mar 31 01:10:45 PM PDT 24
Peak memory 217864 kb
Host smart-52b10823-9a5b-4b5e-a2ee-f4a97b6679cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007639703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1007639703
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.70525458
Short name T396
Test name
Test status
Simulation time 95461093 ps
CPU time 1.25 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:45 PM PDT 24
Peak memory 216612 kb
Host smart-d976b3a8-519d-474c-9130-30c7c4a7c4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70525458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.70525458
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2398923229
Short name T509
Test name
Test status
Simulation time 38768795 ps
CPU time 0.98 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:44 PM PDT 24
Peak memory 223824 kb
Host smart-855e80c3-dfc3-45a8-b4f5-d9a79bbc69db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398923229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2398923229
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2069402475
Short name T707
Test name
Test status
Simulation time 29909146 ps
CPU time 0.93 seconds
Started Mar 31 01:10:45 PM PDT 24
Finished Mar 31 01:10:46 PM PDT 24
Peak memory 206536 kb
Host smart-d656a3a4-cb63-4c14-8c6c-56cfedeb5e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069402475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2069402475
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2265229157
Short name T300
Test name
Test status
Simulation time 27075091 ps
CPU time 0.97 seconds
Started Mar 31 01:10:45 PM PDT 24
Finished Mar 31 01:10:46 PM PDT 24
Peak memory 215304 kb
Host smart-898863e8-fb78-4aa1-98e4-96b88e10073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265229157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2265229157
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3774135010
Short name T593
Test name
Test status
Simulation time 291604995 ps
CPU time 5.13 seconds
Started Mar 31 01:10:44 PM PDT 24
Finished Mar 31 01:10:50 PM PDT 24
Peak memory 215304 kb
Host smart-495dc460-af90-4981-8db5-d861eb35efa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774135010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3774135010
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3654199000
Short name T181
Test name
Test status
Simulation time 75231646296 ps
CPU time 1776.7 seconds
Started Mar 31 01:10:42 PM PDT 24
Finished Mar 31 01:40:19 PM PDT 24
Peak memory 223880 kb
Host smart-91a82869-e931-47bd-bfb6-4fb20cc5f279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654199000 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3654199000
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.4265508188
Short name T105
Test name
Test status
Simulation time 308831456 ps
CPU time 1.12 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 218972 kb
Host smart-a2dd5416-9380-4e95-a240-4bae7f973477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265508188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.4265508188
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2972667917
Short name T301
Test name
Test status
Simulation time 93998189 ps
CPU time 1.2 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 219244 kb
Host smart-a3c6d666-b69d-45a5-ad62-32080a5f087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972667917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2972667917
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1128745855
Short name T94
Test name
Test status
Simulation time 61699374 ps
CPU time 1.16 seconds
Started Mar 31 01:12:28 PM PDT 24
Finished Mar 31 01:12:30 PM PDT 24
Peak memory 224424 kb
Host smart-4205a653-17f9-4f11-b51f-a66bdb139c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128745855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1128745855
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.949550208
Short name T233
Test name
Test status
Simulation time 49829814 ps
CPU time 1.29 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 217824 kb
Host smart-a15ba448-866f-4a75-9ff6-bc1c453a9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949550208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.949550208
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2606430048
Short name T679
Test name
Test status
Simulation time 28832606 ps
CPU time 0.89 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 217948 kb
Host smart-ab992010-e51c-4930-8db5-d9bc0054a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606430048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2606430048
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1844228811
Short name T533
Test name
Test status
Simulation time 40521467 ps
CPU time 1.67 seconds
Started Mar 31 01:12:28 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 217584 kb
Host smart-ef75808a-1e0f-47aa-bdcb-84c5cfb415a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844228811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1844228811
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1202305027
Short name T78
Test name
Test status
Simulation time 31281468 ps
CPU time 1.07 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:33 PM PDT 24
Peak memory 219244 kb
Host smart-26326927-7833-4b7d-baf6-6445d905a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202305027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1202305027
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2646864695
Short name T363
Test name
Test status
Simulation time 114957166 ps
CPU time 2.45 seconds
Started Mar 31 01:12:28 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 218092 kb
Host smart-34cefd07-1efe-4eb2-893f-830511b61114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646864695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2646864695
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3401461650
Short name T717
Test name
Test status
Simulation time 18506875 ps
CPU time 1.08 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 217744 kb
Host smart-71105bf8-ab19-4124-8ed1-d77eba748098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401461650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3401461650
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.463244261
Short name T244
Test name
Test status
Simulation time 40211339 ps
CPU time 1.35 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 217716 kb
Host smart-4394ac2a-c242-4fdc-ad27-e4cb1f0092fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463244261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.463244261
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2239808797
Short name T162
Test name
Test status
Simulation time 24676259 ps
CPU time 0.98 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 218232 kb
Host smart-69f49fe0-57b0-4c8b-b562-48cf82696c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239808797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2239808797
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2116144324
Short name T465
Test name
Test status
Simulation time 37083867 ps
CPU time 1.45 seconds
Started Mar 31 01:12:36 PM PDT 24
Finished Mar 31 01:12:38 PM PDT 24
Peak memory 217804 kb
Host smart-487b9a5b-3763-4317-84a2-f103f0882893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116144324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2116144324
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.975911530
Short name T480
Test name
Test status
Simulation time 60438062 ps
CPU time 0.97 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 218036 kb
Host smart-1dd351d9-9a34-42b1-92e6-f4b341af8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975911530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.975911530
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.4067953583
Short name T369
Test name
Test status
Simulation time 57907685 ps
CPU time 1.31 seconds
Started Mar 31 01:12:34 PM PDT 24
Finished Mar 31 01:12:36 PM PDT 24
Peak memory 216596 kb
Host smart-dc2cbad8-ebc3-4bba-bf41-3f9e5af4fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067953583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.4067953583
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3698063007
Short name T402
Test name
Test status
Simulation time 19790483 ps
CPU time 1.14 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 223116 kb
Host smart-f2666732-1cd6-4bdd-8df9-fc5ffebc0307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698063007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3698063007
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2187167094
Short name T361
Test name
Test status
Simulation time 45847250 ps
CPU time 2.08 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 217764 kb
Host smart-18dfa4c9-acb3-46ba-86f0-2dfe7ec6764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187167094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2187167094
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.832550225
Short name T552
Test name
Test status
Simulation time 30952547 ps
CPU time 0.96 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 218000 kb
Host smart-095d5151-6e02-4b7a-838f-8eb2830e55a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832550225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.832550225
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3838534639
Short name T716
Test name
Test status
Simulation time 38700597 ps
CPU time 1.79 seconds
Started Mar 31 01:12:34 PM PDT 24
Finished Mar 31 01:12:36 PM PDT 24
Peak memory 217936 kb
Host smart-e34c846e-04fc-4493-a980-ec06a9b7956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838534639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3838534639
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3099934903
Short name T98
Test name
Test status
Simulation time 30681184 ps
CPU time 0.89 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:33 PM PDT 24
Peak memory 217720 kb
Host smart-1bf718a5-f29f-40bf-940e-2950aa997151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099934903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3099934903
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1833235689
Short name T618
Test name
Test status
Simulation time 54858916 ps
CPU time 1.37 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 218964 kb
Host smart-3108b6e5-9e35-4c8c-967d-2ca9a6ff2e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833235689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1833235689
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3448898940
Short name T280
Test name
Test status
Simulation time 62873594 ps
CPU time 1.24 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 215604 kb
Host smart-cf16a052-d6a4-4f75-afd8-aa876f555596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448898940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3448898940
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2203092059
Short name T468
Test name
Test status
Simulation time 22067675 ps
CPU time 1.08 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:52 PM PDT 24
Peak memory 205980 kb
Host smart-617fc8d3-c818-4092-9ea6-ac311bbf4fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203092059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2203092059
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2933651348
Short name T172
Test name
Test status
Simulation time 76551576 ps
CPU time 0.86 seconds
Started Mar 31 01:10:48 PM PDT 24
Finished Mar 31 01:10:49 PM PDT 24
Peak memory 215392 kb
Host smart-f29500f2-4d1b-486d-9834-26e55b1f2748
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933651348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2933651348
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.240671364
Short name T77
Test name
Test status
Simulation time 28389297 ps
CPU time 1.12 seconds
Started Mar 31 01:10:58 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 216588 kb
Host smart-108b0c3d-354d-4e8a-8241-1477b49673ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240671364 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.240671364
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3837394179
Short name T483
Test name
Test status
Simulation time 70989696 ps
CPU time 0.81 seconds
Started Mar 31 01:10:45 PM PDT 24
Finished Mar 31 01:10:46 PM PDT 24
Peak memory 217244 kb
Host smart-27c7ce6f-a657-47b2-b2b2-ed3ddea38c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837394179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3837394179
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3075388930
Short name T305
Test name
Test status
Simulation time 32517979 ps
CPU time 1.11 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:44 PM PDT 24
Peak memory 217656 kb
Host smart-65ac5967-d802-4b7e-965e-73c10be9d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075388930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3075388930
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4259472940
Short name T689
Test name
Test status
Simulation time 22118402 ps
CPU time 1.09 seconds
Started Mar 31 01:10:42 PM PDT 24
Finished Mar 31 01:10:43 PM PDT 24
Peak memory 215564 kb
Host smart-502d5f71-1e3e-4f36-97b2-faf7bb2c7d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259472940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4259472940
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2829088059
Short name T131
Test name
Test status
Simulation time 22324636 ps
CPU time 0.94 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 207084 kb
Host smart-78e52eda-3a3d-4e53-bf54-8ea91b3f0c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829088059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2829088059
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1735262252
Short name T289
Test name
Test status
Simulation time 18390803 ps
CPU time 0.98 seconds
Started Mar 31 01:10:43 PM PDT 24
Finished Mar 31 01:10:44 PM PDT 24
Peak memory 215288 kb
Host smart-018885b7-760f-4791-be88-e8dd402e1be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735262252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1735262252
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.57581686
Short name T680
Test name
Test status
Simulation time 161443471 ps
CPU time 1.99 seconds
Started Mar 31 01:10:42 PM PDT 24
Finished Mar 31 01:10:44 PM PDT 24
Peak memory 215164 kb
Host smart-65435212-3f53-4693-8596-97996b26dfb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57581686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.57581686
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1194414854
Short name T726
Test name
Test status
Simulation time 29496161210 ps
CPU time 746.24 seconds
Started Mar 31 01:10:45 PM PDT 24
Finished Mar 31 01:23:11 PM PDT 24
Peak memory 217636 kb
Host smart-b98491e7-33f2-4ae7-872a-2faa1b8bf0f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194414854 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1194414854
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.234736116
Short name T712
Test name
Test status
Simulation time 30316251 ps
CPU time 1.4 seconds
Started Mar 31 01:12:33 PM PDT 24
Finished Mar 31 01:12:35 PM PDT 24
Peak memory 224220 kb
Host smart-f0d04767-a038-4cfb-9ea3-639771d9133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234736116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.234736116
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3537277749
Short name T776
Test name
Test status
Simulation time 42816295 ps
CPU time 1.68 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:35 PM PDT 24
Peak memory 216744 kb
Host smart-900d9635-d913-4070-90d8-be4839e1299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537277749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3537277749
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2790393237
Short name T397
Test name
Test status
Simulation time 40561256 ps
CPU time 1.17 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 219224 kb
Host smart-bb12e220-116d-4309-95e0-44cdc607762d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790393237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2790393237
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3482043396
Short name T341
Test name
Test status
Simulation time 99720234 ps
CPU time 1.13 seconds
Started Mar 31 01:12:35 PM PDT 24
Finished Mar 31 01:12:36 PM PDT 24
Peak memory 216584 kb
Host smart-edc759c6-99bf-4bb5-a6c9-4046a662d955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482043396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3482043396
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2846232559
Short name T606
Test name
Test status
Simulation time 62935158 ps
CPU time 1.06 seconds
Started Mar 31 01:12:37 PM PDT 24
Finished Mar 31 01:12:38 PM PDT 24
Peak memory 220292 kb
Host smart-4a20089a-e301-4019-ab95-7707b6e8940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846232559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2846232559
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.457552113
Short name T609
Test name
Test status
Simulation time 31417118 ps
CPU time 1.28 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:30 PM PDT 24
Peak memory 217988 kb
Host smart-768b4769-e6cb-4c99-abe0-a6934db34eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457552113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.457552113
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4241225294
Short name T68
Test name
Test status
Simulation time 32693475 ps
CPU time 1.16 seconds
Started Mar 31 01:12:37 PM PDT 24
Finished Mar 31 01:12:38 PM PDT 24
Peak memory 229736 kb
Host smart-2d4b4744-c493-4111-9407-438d4e1683e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241225294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4241225294
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.2782400583
Short name T393
Test name
Test status
Simulation time 29339390 ps
CPU time 0.86 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 217628 kb
Host smart-9fbccbbb-ec97-4d04-9226-55abd58f90d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782400583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2782400583
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1659834005
Short name T521
Test name
Test status
Simulation time 26563446 ps
CPU time 1.22 seconds
Started Mar 31 01:12:38 PM PDT 24
Finished Mar 31 01:12:39 PM PDT 24
Peak memory 217516 kb
Host smart-b9d0adcf-edb0-4584-8156-15b2ef191928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659834005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1659834005
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2088506131
Short name T642
Test name
Test status
Simulation time 65386401 ps
CPU time 1.01 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 218060 kb
Host smart-49a4d070-2c45-4fcf-b706-2c15a839fbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088506131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2088506131
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1647507391
Short name T394
Test name
Test status
Simulation time 40426144 ps
CPU time 1.45 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:33 PM PDT 24
Peak memory 217648 kb
Host smart-5c90ab7f-2744-47a0-99a1-985b5514b0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647507391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1647507391
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2735787796
Short name T631
Test name
Test status
Simulation time 37925807 ps
CPU time 0.92 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 218096 kb
Host smart-3846b200-9c38-4265-8d1d-679350dddd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735787796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2735787796
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.754401166
Short name T30
Test name
Test status
Simulation time 51922138 ps
CPU time 1.26 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 219180 kb
Host smart-4d5a9880-c492-4c37-832c-93ccb8779457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754401166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.754401166
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.4011293069
Short name T688
Test name
Test status
Simulation time 34827090 ps
CPU time 0.82 seconds
Started Mar 31 01:12:39 PM PDT 24
Finished Mar 31 01:12:40 PM PDT 24
Peak memory 217616 kb
Host smart-e48faa59-3834-47cf-bf0c-6a2de72aff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011293069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4011293069
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.140340763
Short name T366
Test name
Test status
Simulation time 25965375 ps
CPU time 1.16 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 216664 kb
Host smart-5486556a-d1de-4f1c-8123-602259373ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140340763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.140340763
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2429586222
Short name T479
Test name
Test status
Simulation time 42164320 ps
CPU time 0.86 seconds
Started Mar 31 01:12:38 PM PDT 24
Finished Mar 31 01:12:39 PM PDT 24
Peak memory 217608 kb
Host smart-198f162f-a4f0-43df-85db-437685e40cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429586222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2429586222
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4280780554
Short name T783
Test name
Test status
Simulation time 48945051 ps
CPU time 1.84 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:33 PM PDT 24
Peak memory 217644 kb
Host smart-de9dffa2-0683-4944-a27a-b0febe564c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280780554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4280780554
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1346683057
Short name T99
Test name
Test status
Simulation time 18812214 ps
CPU time 1.17 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 231312 kb
Host smart-021571f7-2c95-4ff1-9e4f-d112bf82caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346683057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1346683057
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1392462524
Short name T354
Test name
Test status
Simulation time 43699693 ps
CPU time 1.64 seconds
Started Mar 31 01:12:30 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 219080 kb
Host smart-d9ee75c6-7a28-4c89-b772-670f08d2d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392462524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1392462524
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3103202262
Short name T750
Test name
Test status
Simulation time 64245720 ps
CPU time 1.1 seconds
Started Mar 31 01:10:48 PM PDT 24
Finished Mar 31 01:10:49 PM PDT 24
Peak memory 215640 kb
Host smart-20592cf4-3fc8-47c6-8e22-44b9cb490099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103202262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3103202262
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3421135626
Short name T430
Test name
Test status
Simulation time 12990389 ps
CPU time 0.88 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 206556 kb
Host smart-9335fc87-e61e-40dc-b5ca-45a141204334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421135626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3421135626
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3901314887
Short name T107
Test name
Test status
Simulation time 21986802 ps
CPU time 0.94 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:50 PM PDT 24
Peak memory 215768 kb
Host smart-fbb44e64-5dde-4423-a24f-a602e221a0d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901314887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3901314887
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3385270568
Short name T87
Test name
Test status
Simulation time 32172211 ps
CPU time 1.14 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:52 PM PDT 24
Peak memory 216376 kb
Host smart-c641e8d7-2a7a-4f4b-b655-494af5fc0835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385270568 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3385270568
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3967721970
Short name T817
Test name
Test status
Simulation time 42122345 ps
CPU time 1.15 seconds
Started Mar 31 01:10:51 PM PDT 24
Finished Mar 31 01:10:52 PM PDT 24
Peak memory 219256 kb
Host smart-08e39faf-b0bc-45b0-b827-fef89b933f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967721970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3967721970
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3853471565
Short name T319
Test name
Test status
Simulation time 85605845 ps
CPU time 2.84 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:53 PM PDT 24
Peak memory 218596 kb
Host smart-d0c94252-f511-4a4f-b22a-f1a8c7035495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853471565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3853471565
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2077125726
Short name T130
Test name
Test status
Simulation time 31456252 ps
CPU time 0.87 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:50 PM PDT 24
Peak memory 215416 kb
Host smart-905bc1c0-32bb-4eab-9767-ed766837bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077125726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2077125726
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.733151876
Short name T271
Test name
Test status
Simulation time 17857246 ps
CPU time 1.04 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:51 PM PDT 24
Peak memory 207080 kb
Host smart-2d182180-de2a-433e-b2a0-7c6186f7d8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733151876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.733151876
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.141856477
Short name T330
Test name
Test status
Simulation time 25837306 ps
CPU time 0.95 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:10:50 PM PDT 24
Peak memory 215228 kb
Host smart-9b9f1f75-f51a-474b-b6e6-accdc2c8cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141856477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.141856477
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2404852479
Short name T691
Test name
Test status
Simulation time 124677112 ps
CPU time 2.99 seconds
Started Mar 31 01:10:50 PM PDT 24
Finished Mar 31 01:10:53 PM PDT 24
Peak memory 216508 kb
Host smart-9ba83983-d7f1-4e5a-ac12-84b42f2099e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404852479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2404852479
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3023473315
Short name T187
Test name
Test status
Simulation time 29319092227 ps
CPU time 321.67 seconds
Started Mar 31 01:10:49 PM PDT 24
Finished Mar 31 01:16:11 PM PDT 24
Peak memory 216736 kb
Host smart-07d0923a-fee2-4f9c-bb93-97e9304b12cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023473315 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3023473315
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1928795322
Short name T158
Test name
Test status
Simulation time 23371923 ps
CPU time 1 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 218040 kb
Host smart-8ecdfc3f-8a99-44c2-aaae-245626f13761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928795322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1928795322
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2501421579
Short name T740
Test name
Test status
Simulation time 63198598 ps
CPU time 1.13 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:34 PM PDT 24
Peak memory 216544 kb
Host smart-6b782e16-0b85-4527-9172-87fd9d9ab71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501421579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2501421579
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3280792019
Short name T83
Test name
Test status
Simulation time 62507507 ps
CPU time 1.08 seconds
Started Mar 31 01:12:31 PM PDT 24
Finished Mar 31 01:12:32 PM PDT 24
Peak memory 219976 kb
Host smart-e1c52ca4-355a-4ab1-a3c5-1e8e467c9b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280792019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3280792019
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3194441116
Short name T234
Test name
Test status
Simulation time 98073284 ps
CPU time 1.6 seconds
Started Mar 31 01:12:37 PM PDT 24
Finished Mar 31 01:12:39 PM PDT 24
Peak memory 218376 kb
Host smart-73263e7f-6371-43a9-93d8-f67ae9b3f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194441116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3194441116
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.676112973
Short name T429
Test name
Test status
Simulation time 44226831 ps
CPU time 1.19 seconds
Started Mar 31 01:12:29 PM PDT 24
Finished Mar 31 01:12:31 PM PDT 24
Peak memory 219100 kb
Host smart-77652ee5-9408-4fcd-ad2b-d4b847953372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676112973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.676112973
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1802779924
Short name T417
Test name
Test status
Simulation time 65780495 ps
CPU time 1.69 seconds
Started Mar 31 01:12:32 PM PDT 24
Finished Mar 31 01:12:35 PM PDT 24
Peak memory 216732 kb
Host smart-4e419e4c-9461-4220-9e56-2dc83301f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802779924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1802779924
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1092722155
Short name T399
Test name
Test status
Simulation time 18115440 ps
CPU time 1.11 seconds
Started Mar 31 01:12:38 PM PDT 24
Finished Mar 31 01:12:39 PM PDT 24
Peak memory 223104 kb
Host smart-ec0344d2-dd73-4407-9404-fd68faa9a2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092722155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1092722155
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.641100639
Short name T254
Test name
Test status
Simulation time 97722155 ps
CPU time 1.5 seconds
Started Mar 31 01:12:37 PM PDT 24
Finished Mar 31 01:12:38 PM PDT 24
Peak memory 217948 kb
Host smart-9909dd68-c249-457a-b0a8-5d7a18f9ef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641100639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.641100639
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4219516535
Short name T517
Test name
Test status
Simulation time 28947850 ps
CPU time 1.39 seconds
Started Mar 31 01:12:54 PM PDT 24
Finished Mar 31 01:12:55 PM PDT 24
Peak memory 224200 kb
Host smart-e0a429a6-b402-4303-9815-c5bac00b1e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219516535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4219516535
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2865784536
Short name T284
Test name
Test status
Simulation time 244494227 ps
CPU time 4.02 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 218012 kb
Host smart-9bf97e82-4962-43b0-856c-896e6ca3a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865784536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2865784536
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4081620395
Short name T473
Test name
Test status
Simulation time 27748266 ps
CPU time 0.95 seconds
Started Mar 31 01:13:01 PM PDT 24
Finished Mar 31 01:13:02 PM PDT 24
Peak memory 231064 kb
Host smart-cae0725d-baf2-49d3-b2b5-eb64186a9ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081620395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4081620395
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1239951576
Short name T590
Test name
Test status
Simulation time 188346223 ps
CPU time 2.31 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:13:00 PM PDT 24
Peak memory 217088 kb
Host smart-6705471d-9ada-49cf-b4c2-36d294ee0400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239951576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1239951576
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2379297998
Short name T4
Test name
Test status
Simulation time 20522326 ps
CPU time 1.14 seconds
Started Mar 31 01:12:57 PM PDT 24
Finished Mar 31 01:12:59 PM PDT 24
Peak memory 219176 kb
Host smart-fe645430-52eb-4ed3-8a82-5708217c5d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379297998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2379297998
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3757568227
Short name T12
Test name
Test status
Simulation time 65954155 ps
CPU time 1.24 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 217852 kb
Host smart-8e036282-1cd3-4d14-a3f6-d5a165689b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757568227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3757568227
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.4073393261
Short name T434
Test name
Test status
Simulation time 19867080 ps
CPU time 1.12 seconds
Started Mar 31 01:12:53 PM PDT 24
Finished Mar 31 01:12:55 PM PDT 24
Peak memory 231264 kb
Host smart-66fba78c-8700-4ae7-9c29-5bfaf9175d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073393261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4073393261
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2068012622
Short name T414
Test name
Test status
Simulation time 93713096 ps
CPU time 1.1 seconds
Started Mar 31 01:12:54 PM PDT 24
Finished Mar 31 01:12:56 PM PDT 24
Peak memory 216524 kb
Host smart-267b407d-02d2-47cf-aad8-529ba393de85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068012622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2068012622
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.146347984
Short name T168
Test name
Test status
Simulation time 46319954 ps
CPU time 1 seconds
Started Mar 31 01:13:00 PM PDT 24
Finished Mar 31 01:13:01 PM PDT 24
Peak memory 219260 kb
Host smart-b25782a1-ee47-4887-9d6b-fa8e75dc2b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146347984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.146347984
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.3339888549
Short name T128
Test name
Test status
Simulation time 29979616 ps
CPU time 1.13 seconds
Started Mar 31 01:12:56 PM PDT 24
Finished Mar 31 01:12:57 PM PDT 24
Peak memory 218180 kb
Host smart-5e888a00-e5d5-417c-b7a1-45d57701efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339888549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3339888549
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2698284389
Short name T309
Test name
Test status
Simulation time 138688779 ps
CPU time 1.4 seconds
Started Mar 31 01:12:55 PM PDT 24
Finished Mar 31 01:12:58 PM PDT 24
Peak memory 218368 kb
Host smart-cf78c914-338e-4f54-8412-3d589337ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698284389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2698284389
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%