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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.94 98.27 93.71 96.74 82.08 96.87 96.58 93.35


Total test records in report: 968
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T791 /workspace/coverage/default/7.edn_stress_all_with_rand_reset.391538591 Apr 02 01:35:01 PM PDT 24 Apr 02 01:57:40 PM PDT 24 113507052158 ps
T792 /workspace/coverage/default/58.edn_genbits.1687567548 Apr 02 01:37:35 PM PDT 24 Apr 02 01:37:37 PM PDT 24 57855058 ps
T793 /workspace/coverage/default/28.edn_smoke.2348255535 Apr 02 01:36:19 PM PDT 24 Apr 02 01:36:20 PM PDT 24 113703740 ps
T794 /workspace/coverage/default/32.edn_stress_all.254499406 Apr 02 01:36:40 PM PDT 24 Apr 02 01:36:44 PM PDT 24 580189272 ps
T795 /workspace/coverage/default/101.edn_genbits.1779719416 Apr 02 01:38:04 PM PDT 24 Apr 02 01:38:06 PM PDT 24 46673373 ps
T796 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3125408177 Apr 02 01:36:27 PM PDT 24 Apr 02 01:55:51 PM PDT 24 50872412584 ps
T797 /workspace/coverage/default/25.edn_smoke.2296780865 Apr 02 01:36:16 PM PDT 24 Apr 02 01:36:17 PM PDT 24 44545538 ps
T146 /workspace/coverage/default/43.edn_disable.2231957174 Apr 02 01:37:15 PM PDT 24 Apr 02 01:37:16 PM PDT 24 28133777 ps
T798 /workspace/coverage/default/7.edn_disable_auto_req_mode.2520571952 Apr 02 01:35:05 PM PDT 24 Apr 02 01:35:07 PM PDT 24 53612225 ps
T799 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1128867723 Apr 02 01:37:31 PM PDT 24 Apr 02 01:43:54 PM PDT 24 15577444977 ps
T800 /workspace/coverage/default/2.edn_intr.2502111926 Apr 02 01:34:30 PM PDT 24 Apr 02 01:34:31 PM PDT 24 22674072 ps
T801 /workspace/coverage/default/23.edn_genbits.255438070 Apr 02 01:36:11 PM PDT 24 Apr 02 01:36:13 PM PDT 24 36423587 ps
T802 /workspace/coverage/default/125.edn_genbits.195210194 Apr 02 01:38:06 PM PDT 24 Apr 02 01:38:08 PM PDT 24 68602311 ps
T803 /workspace/coverage/default/264.edn_genbits.3101578078 Apr 02 01:38:40 PM PDT 24 Apr 02 01:38:42 PM PDT 24 46837376 ps
T804 /workspace/coverage/default/38.edn_genbits.3552937698 Apr 02 01:36:55 PM PDT 24 Apr 02 01:37:01 PM PDT 24 521401202 ps
T805 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1934612893 Apr 02 01:35:16 PM PDT 24 Apr 02 01:43:18 PM PDT 24 99245529470 ps
T806 /workspace/coverage/default/254.edn_genbits.2249263506 Apr 02 01:38:37 PM PDT 24 Apr 02 01:38:39 PM PDT 24 27842493 ps
T807 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.490261033 Apr 02 01:37:01 PM PDT 24 Apr 02 02:05:19 PM PDT 24 77029902838 ps
T808 /workspace/coverage/default/267.edn_genbits.3881311704 Apr 02 01:38:39 PM PDT 24 Apr 02 01:38:41 PM PDT 24 50856709 ps
T84 /workspace/coverage/default/37.edn_disable_auto_req_mode.1738407167 Apr 02 01:36:50 PM PDT 24 Apr 02 01:36:51 PM PDT 24 28425960 ps
T809 /workspace/coverage/default/2.edn_alert_test.1503703511 Apr 02 01:34:31 PM PDT 24 Apr 02 01:34:32 PM PDT 24 13339566 ps
T810 /workspace/coverage/default/17.edn_stress_all.2148888589 Apr 02 01:35:43 PM PDT 24 Apr 02 01:35:49 PM PDT 24 484598492 ps
T811 /workspace/coverage/default/14.edn_err.4170286120 Apr 02 01:35:35 PM PDT 24 Apr 02 01:35:37 PM PDT 24 19300442 ps
T812 /workspace/coverage/default/244.edn_genbits.3098979616 Apr 02 01:38:36 PM PDT 24 Apr 02 01:38:38 PM PDT 24 33437516 ps
T813 /workspace/coverage/default/19.edn_err.1583341012 Apr 02 01:35:57 PM PDT 24 Apr 02 01:35:59 PM PDT 24 27922098 ps
T814 /workspace/coverage/default/28.edn_alert_test.947918109 Apr 02 01:36:23 PM PDT 24 Apr 02 01:36:24 PM PDT 24 25743273 ps
T815 /workspace/coverage/default/28.edn_alert.746420526 Apr 02 01:36:23 PM PDT 24 Apr 02 01:36:26 PM PDT 24 41505916 ps
T816 /workspace/coverage/default/39.edn_stress_all.1198674274 Apr 02 01:36:54 PM PDT 24 Apr 02 01:36:57 PM PDT 24 95738329 ps
T817 /workspace/coverage/default/37.edn_err.1389038608 Apr 02 01:36:51 PM PDT 24 Apr 02 01:36:52 PM PDT 24 34347436 ps
T265 /workspace/coverage/default/21.edn_alert.3217159888 Apr 02 01:36:03 PM PDT 24 Apr 02 01:36:05 PM PDT 24 83198272 ps
T818 /workspace/coverage/default/56.edn_genbits.916970384 Apr 02 01:37:32 PM PDT 24 Apr 02 01:37:35 PM PDT 24 136495688 ps
T819 /workspace/coverage/default/113.edn_genbits.1918951415 Apr 02 01:38:06 PM PDT 24 Apr 02 01:38:07 PM PDT 24 71869107 ps
T820 /workspace/coverage/default/26.edn_stress_all.2151775127 Apr 02 01:36:20 PM PDT 24 Apr 02 01:36:24 PM PDT 24 326878005 ps
T821 /workspace/coverage/default/3.edn_disable_auto_req_mode.3175304219 Apr 02 01:34:42 PM PDT 24 Apr 02 01:34:44 PM PDT 24 154026868 ps
T822 /workspace/coverage/default/35.edn_alert_test.3544314911 Apr 02 01:36:49 PM PDT 24 Apr 02 01:36:50 PM PDT 24 60710646 ps
T823 /workspace/coverage/default/46.edn_disable_auto_req_mode.2845424908 Apr 02 01:37:25 PM PDT 24 Apr 02 01:37:26 PM PDT 24 178041580 ps
T824 /workspace/coverage/default/195.edn_genbits.783152976 Apr 02 01:38:25 PM PDT 24 Apr 02 01:38:27 PM PDT 24 95471289 ps
T825 /workspace/coverage/default/29.edn_err.1716835319 Apr 02 01:36:33 PM PDT 24 Apr 02 01:36:35 PM PDT 24 58262967 ps
T826 /workspace/coverage/default/3.edn_stress_all.771833552 Apr 02 01:34:34 PM PDT 24 Apr 02 01:34:40 PM PDT 24 292176125 ps
T827 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.931540880 Apr 02 01:36:32 PM PDT 24 Apr 02 01:46:15 PM PDT 24 22775067807 ps
T828 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2658961513 Apr 02 01:34:49 PM PDT 24 Apr 02 01:44:31 PM PDT 24 54130344222 ps
T829 /workspace/coverage/default/209.edn_genbits.1408937653 Apr 02 01:38:28 PM PDT 24 Apr 02 01:38:29 PM PDT 24 49750436 ps
T830 /workspace/coverage/default/2.edn_genbits.4104809671 Apr 02 01:34:27 PM PDT 24 Apr 02 01:34:29 PM PDT 24 32220560 ps
T831 /workspace/coverage/default/2.edn_stress_all.3073174882 Apr 02 01:34:28 PM PDT 24 Apr 02 01:34:34 PM PDT 24 392029071 ps
T106 /workspace/coverage/default/78.edn_err.3914417740 Apr 02 01:37:50 PM PDT 24 Apr 02 01:37:51 PM PDT 24 22696785 ps
T832 /workspace/coverage/default/291.edn_genbits.2040560707 Apr 02 01:38:46 PM PDT 24 Apr 02 01:38:48 PM PDT 24 70991359 ps
T833 /workspace/coverage/default/49.edn_disable_auto_req_mode.4137127536 Apr 02 01:37:40 PM PDT 24 Apr 02 01:37:41 PM PDT 24 30095546 ps
T834 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1898022647 Apr 02 01:36:56 PM PDT 24 Apr 02 02:04:24 PM PDT 24 249539803989 ps
T835 /workspace/coverage/default/82.edn_genbits.1630372092 Apr 02 01:37:54 PM PDT 24 Apr 02 01:37:55 PM PDT 24 50656069 ps
T836 /workspace/coverage/default/186.edn_genbits.4220320334 Apr 02 01:38:21 PM PDT 24 Apr 02 01:38:23 PM PDT 24 108464244 ps
T68 /workspace/coverage/default/99.edn_err.2224730639 Apr 02 01:38:01 PM PDT 24 Apr 02 01:38:02 PM PDT 24 25625412 ps
T837 /workspace/coverage/default/21.edn_smoke.3689383133 Apr 02 01:35:58 PM PDT 24 Apr 02 01:35:59 PM PDT 24 42408899 ps
T123 /workspace/coverage/default/32.edn_intr.397459867 Apr 02 01:36:37 PM PDT 24 Apr 02 01:36:39 PM PDT 24 28735870 ps
T838 /workspace/coverage/default/9.edn_regwen.1750291770 Apr 02 01:35:10 PM PDT 24 Apr 02 01:35:11 PM PDT 24 18200778 ps
T235 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3194729569 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:30 PM PDT 24 138838525 ps
T234 /workspace/coverage/cover_reg_top/8.edn_csr_rw.733986701 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:31 PM PDT 24 20327815 ps
T839 /workspace/coverage/cover_reg_top/36.edn_intr_test.3456475488 Apr 02 12:32:09 PM PDT 24 Apr 02 12:32:11 PM PDT 24 28222600 ps
T840 /workspace/coverage/cover_reg_top/26.edn_intr_test.3570099590 Apr 02 12:31:34 PM PDT 24 Apr 02 12:31:36 PM PDT 24 42220400 ps
T841 /workspace/coverage/cover_reg_top/4.edn_intr_test.3114316716 Apr 02 12:31:54 PM PDT 24 Apr 02 12:31:55 PM PDT 24 16625030 ps
T842 /workspace/coverage/cover_reg_top/11.edn_intr_test.1761372458 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:29 PM PDT 24 46474600 ps
T201 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2351785876 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:29 PM PDT 24 16002444 ps
T202 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3711280990 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:46 PM PDT 24 76264353 ps
T843 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3211205934 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:34 PM PDT 24 523256666 ps
T236 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4090797382 Apr 02 12:32:53 PM PDT 24 Apr 02 12:32:56 PM PDT 24 86429181 ps
T844 /workspace/coverage/cover_reg_top/6.edn_intr_test.2377961165 Apr 02 12:32:24 PM PDT 24 Apr 02 12:32:30 PM PDT 24 25528812 ps
T203 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.184348911 Apr 02 12:31:31 PM PDT 24 Apr 02 12:31:32 PM PDT 24 15532325 ps
T845 /workspace/coverage/cover_reg_top/28.edn_intr_test.2834523318 Apr 02 12:32:01 PM PDT 24 Apr 02 12:32:02 PM PDT 24 21669546 ps
T846 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.852064895 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:30 PM PDT 24 65573971 ps
T847 /workspace/coverage/cover_reg_top/46.edn_intr_test.1481059109 Apr 02 12:32:04 PM PDT 24 Apr 02 12:32:06 PM PDT 24 17464213 ps
T848 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.521915667 Apr 02 12:32:51 PM PDT 24 Apr 02 12:32:52 PM PDT 24 44351618 ps
T849 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3065560377 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:30 PM PDT 24 42467963 ps
T237 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1683932753 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:31 PM PDT 24 760205173 ps
T850 /workspace/coverage/cover_reg_top/11.edn_tl_errors.392058003 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:32 PM PDT 24 61804138 ps
T851 /workspace/coverage/cover_reg_top/1.edn_intr_test.3105165028 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 44042593 ps
T247 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3690267146 Apr 02 12:31:32 PM PDT 24 Apr 02 12:31:34 PM PDT 24 177673501 ps
T220 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3507255145 Apr 02 12:31:36 PM PDT 24 Apr 02 12:31:38 PM PDT 24 42051881 ps
T852 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4278305922 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:30 PM PDT 24 89238803 ps
T853 /workspace/coverage/cover_reg_top/18.edn_intr_test.1907987032 Apr 02 12:32:04 PM PDT 24 Apr 02 12:32:06 PM PDT 24 21327283 ps
T250 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3947235549 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:31 PM PDT 24 150452965 ps
T854 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1634504325 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:32 PM PDT 24 42345757 ps
T855 /workspace/coverage/cover_reg_top/16.edn_intr_test.2711400190 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:30 PM PDT 24 14134508 ps
T204 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1786847303 Apr 02 12:32:48 PM PDT 24 Apr 02 12:32:54 PM PDT 24 299495468 ps
T856 /workspace/coverage/cover_reg_top/43.edn_intr_test.992138174 Apr 02 12:31:50 PM PDT 24 Apr 02 12:31:51 PM PDT 24 19392933 ps
T857 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.719317965 Apr 02 12:31:32 PM PDT 24 Apr 02 12:31:35 PM PDT 24 49587788 ps
T858 /workspace/coverage/cover_reg_top/9.edn_tl_errors.92191336 Apr 02 12:32:04 PM PDT 24 Apr 02 12:32:07 PM PDT 24 90599189 ps
T205 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2125494554 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 62618538 ps
T206 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.772494835 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:31 PM PDT 24 25111400 ps
T207 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1185713161 Apr 02 12:31:33 PM PDT 24 Apr 02 12:31:40 PM PDT 24 29926728 ps
T221 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2128783680 Apr 02 12:32:49 PM PDT 24 Apr 02 12:32:51 PM PDT 24 16085404 ps
T859 /workspace/coverage/cover_reg_top/30.edn_intr_test.1649567576 Apr 02 12:32:03 PM PDT 24 Apr 02 12:32:05 PM PDT 24 14178041 ps
T860 /workspace/coverage/cover_reg_top/18.edn_tl_errors.4147183338 Apr 02 12:31:56 PM PDT 24 Apr 02 12:31:58 PM PDT 24 40861969 ps
T861 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1979383814 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:48 PM PDT 24 72585416 ps
T208 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2076589549 Apr 02 12:31:50 PM PDT 24 Apr 02 12:31:52 PM PDT 24 16203642 ps
T862 /workspace/coverage/cover_reg_top/23.edn_intr_test.779282026 Apr 02 12:32:03 PM PDT 24 Apr 02 12:32:05 PM PDT 24 12116124 ps
T251 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3738034497 Apr 02 12:32:55 PM PDT 24 Apr 02 12:32:57 PM PDT 24 58347355 ps
T222 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3663697902 Apr 02 12:32:09 PM PDT 24 Apr 02 12:32:11 PM PDT 24 14093216 ps
T209 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.718937444 Apr 02 12:32:45 PM PDT 24 Apr 02 12:32:46 PM PDT 24 22649319 ps
T863 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2853350529 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:32 PM PDT 24 294018156 ps
T210 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1355709390 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:30 PM PDT 24 16478319 ps
T864 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1074450804 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:32 PM PDT 24 64115946 ps
T865 /workspace/coverage/cover_reg_top/44.edn_intr_test.944700508 Apr 02 12:32:08 PM PDT 24 Apr 02 12:32:09 PM PDT 24 43537765 ps
T866 /workspace/coverage/cover_reg_top/0.edn_intr_test.2474754738 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 30294365 ps
T867 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3714792882 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:46 PM PDT 24 19209138 ps
T223 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2364309646 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 43400771 ps
T211 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.779189181 Apr 02 12:32:55 PM PDT 24 Apr 02 12:32:59 PM PDT 24 61023450 ps
T868 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3267564241 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:33 PM PDT 24 54758280 ps
T869 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1324568809 Apr 02 12:32:39 PM PDT 24 Apr 02 12:32:41 PM PDT 24 86946568 ps
T870 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.752932620 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:31 PM PDT 24 48518155 ps
T871 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1737393120 Apr 02 12:32:49 PM PDT 24 Apr 02 12:32:52 PM PDT 24 64080792 ps
T872 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2704605596 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 16995557 ps
T873 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.981993047 Apr 02 12:32:07 PM PDT 24 Apr 02 12:32:10 PM PDT 24 54208230 ps
T212 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.178204894 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 174953819 ps
T874 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4043071844 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:32 PM PDT 24 278698863 ps
T875 /workspace/coverage/cover_reg_top/34.edn_intr_test.2265282578 Apr 02 12:32:00 PM PDT 24 Apr 02 12:32:01 PM PDT 24 149368755 ps
T876 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4170943525 Apr 02 12:32:38 PM PDT 24 Apr 02 12:32:39 PM PDT 24 251893074 ps
T877 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.212333706 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 80699406 ps
T878 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.756006900 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:30 PM PDT 24 47657044 ps
T879 /workspace/coverage/cover_reg_top/49.edn_intr_test.488504631 Apr 02 12:31:56 PM PDT 24 Apr 02 12:31:57 PM PDT 24 14469141 ps
T880 /workspace/coverage/cover_reg_top/39.edn_intr_test.1720976892 Apr 02 12:31:56 PM PDT 24 Apr 02 12:31:57 PM PDT 24 22878910 ps
T881 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.838847638 Apr 02 12:32:02 PM PDT 24 Apr 02 12:32:04 PM PDT 24 39654523 ps
T882 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3278929151 Apr 02 12:32:59 PM PDT 24 Apr 02 12:33:00 PM PDT 24 23511090 ps
T883 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.527556032 Apr 02 12:31:26 PM PDT 24 Apr 02 12:31:27 PM PDT 24 37844162 ps
T884 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2066246250 Apr 02 12:31:44 PM PDT 24 Apr 02 12:31:47 PM PDT 24 42133793 ps
T885 /workspace/coverage/cover_reg_top/19.edn_csr_rw.311819179 Apr 02 12:31:40 PM PDT 24 Apr 02 12:31:41 PM PDT 24 14349599 ps
T886 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2659971395 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:33 PM PDT 24 180907094 ps
T248 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2691352780 Apr 02 12:32:50 PM PDT 24 Apr 02 12:32:53 PM PDT 24 379697547 ps
T887 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3028636069 Apr 02 12:32:48 PM PDT 24 Apr 02 12:32:49 PM PDT 24 161306827 ps
T888 /workspace/coverage/cover_reg_top/12.edn_intr_test.726236437 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:30 PM PDT 24 23830425 ps
T889 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2755678426 Apr 02 12:32:56 PM PDT 24 Apr 02 12:32:57 PM PDT 24 16975118 ps
T213 /workspace/coverage/cover_reg_top/15.edn_csr_rw.849891622 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:31 PM PDT 24 16026791 ps
T890 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2573007332 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:33 PM PDT 24 1106871332 ps
T891 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4205125668 Apr 02 12:32:24 PM PDT 24 Apr 02 12:32:27 PM PDT 24 38217403 ps
T219 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2695204777 Apr 02 12:32:54 PM PDT 24 Apr 02 12:33:00 PM PDT 24 261695565 ps
T892 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4191571459 Apr 02 12:32:53 PM PDT 24 Apr 02 12:32:55 PM PDT 24 17293145 ps
T214 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3332401356 Apr 02 12:31:35 PM PDT 24 Apr 02 12:31:38 PM PDT 24 43970138 ps
T893 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1282763408 Apr 02 12:32:59 PM PDT 24 Apr 02 12:33:00 PM PDT 24 47399585 ps
T894 /workspace/coverage/cover_reg_top/7.edn_intr_test.458776473 Apr 02 12:32:52 PM PDT 24 Apr 02 12:32:53 PM PDT 24 46800308 ps
T895 /workspace/coverage/cover_reg_top/27.edn_intr_test.1207375041 Apr 02 12:31:39 PM PDT 24 Apr 02 12:31:45 PM PDT 24 12798849 ps
T896 /workspace/coverage/cover_reg_top/24.edn_intr_test.4225763910 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:45 PM PDT 24 27927731 ps
T897 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4083568560 Apr 02 12:32:52 PM PDT 24 Apr 02 12:32:53 PM PDT 24 20445841 ps
T898 /workspace/coverage/cover_reg_top/42.edn_intr_test.1732870680 Apr 02 12:32:03 PM PDT 24 Apr 02 12:32:05 PM PDT 24 12477712 ps
T899 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1883865919 Apr 02 12:32:47 PM PDT 24 Apr 02 12:32:48 PM PDT 24 25455207 ps
T900 /workspace/coverage/cover_reg_top/10.edn_intr_test.1434612146 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:30 PM PDT 24 14701711 ps
T901 /workspace/coverage/cover_reg_top/13.edn_intr_test.2726666585 Apr 02 12:31:25 PM PDT 24 Apr 02 12:31:26 PM PDT 24 13908829 ps
T902 /workspace/coverage/cover_reg_top/2.edn_intr_test.2877816733 Apr 02 12:31:50 PM PDT 24 Apr 02 12:31:51 PM PDT 24 10875144 ps
T253 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2625452634 Apr 02 12:31:21 PM PDT 24 Apr 02 12:31:23 PM PDT 24 158251679 ps
T903 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2781523151 Apr 02 12:31:31 PM PDT 24 Apr 02 12:31:32 PM PDT 24 56840121 ps
T904 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2063984427 Apr 02 12:31:57 PM PDT 24 Apr 02 12:31:59 PM PDT 24 70614070 ps
T249 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4056722280 Apr 02 12:31:53 PM PDT 24 Apr 02 12:31:55 PM PDT 24 40677986 ps
T905 /workspace/coverage/cover_reg_top/19.edn_intr_test.3231751402 Apr 02 12:32:11 PM PDT 24 Apr 02 12:32:12 PM PDT 24 16153840 ps
T906 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1854768957 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:32 PM PDT 24 70275268 ps
T907 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1352547552 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:29 PM PDT 24 81558876 ps
T908 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3143795006 Apr 02 12:32:27 PM PDT 24 Apr 02 12:32:29 PM PDT 24 171671578 ps
T909 /workspace/coverage/cover_reg_top/8.edn_intr_test.1727145509 Apr 02 12:31:26 PM PDT 24 Apr 02 12:31:27 PM PDT 24 28860376 ps
T910 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2861763752 Apr 02 12:31:48 PM PDT 24 Apr 02 12:31:49 PM PDT 24 19793565 ps
T911 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4020945499 Apr 02 12:31:51 PM PDT 24 Apr 02 12:31:52 PM PDT 24 43629065 ps
T912 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2676432647 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:30 PM PDT 24 59716887 ps
T913 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1207674317 Apr 02 12:32:00 PM PDT 24 Apr 02 12:32:01 PM PDT 24 46581460 ps
T252 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1578945851 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:31 PM PDT 24 297010406 ps
T914 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1915877043 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:30 PM PDT 24 88841658 ps
T915 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.849308671 Apr 02 12:31:26 PM PDT 24 Apr 02 12:31:30 PM PDT 24 297225431 ps
T916 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1127276949 Apr 02 12:31:25 PM PDT 24 Apr 02 12:31:27 PM PDT 24 41932303 ps
T917 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.980204156 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:47 PM PDT 24 51989658 ps
T918 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4075914224 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:33 PM PDT 24 88102943 ps
T919 /workspace/coverage/cover_reg_top/40.edn_intr_test.1206935221 Apr 02 12:32:03 PM PDT 24 Apr 02 12:32:05 PM PDT 24 26424098 ps
T920 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2704738738 Apr 02 12:31:34 PM PDT 24 Apr 02 12:31:36 PM PDT 24 35283158 ps
T921 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3864261636 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:38 PM PDT 24 166323421 ps
T922 /workspace/coverage/cover_reg_top/7.edn_csr_rw.100545654 Apr 02 12:32:52 PM PDT 24 Apr 02 12:32:53 PM PDT 24 23933235 ps
T923 /workspace/coverage/cover_reg_top/37.edn_intr_test.778032766 Apr 02 12:32:00 PM PDT 24 Apr 02 12:32:01 PM PDT 24 16284731 ps
T924 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3148053654 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:33 PM PDT 24 371955971 ps
T925 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3768767426 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:46 PM PDT 24 48714157 ps
T926 /workspace/coverage/cover_reg_top/9.edn_intr_test.1281774307 Apr 02 12:31:27 PM PDT 24 Apr 02 12:31:34 PM PDT 24 37778579 ps
T927 /workspace/coverage/cover_reg_top/20.edn_intr_test.889685515 Apr 02 12:31:43 PM PDT 24 Apr 02 12:31:44 PM PDT 24 20075538 ps
T928 /workspace/coverage/cover_reg_top/48.edn_intr_test.2911646512 Apr 02 12:32:13 PM PDT 24 Apr 02 12:32:14 PM PDT 24 42297643 ps
T929 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4237038739 Apr 02 12:32:47 PM PDT 24 Apr 02 12:32:49 PM PDT 24 239968171 ps
T930 /workspace/coverage/cover_reg_top/38.edn_intr_test.3714498075 Apr 02 12:31:54 PM PDT 24 Apr 02 12:31:55 PM PDT 24 69813124 ps
T931 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.138731954 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:32 PM PDT 24 45569083 ps
T932 /workspace/coverage/cover_reg_top/31.edn_intr_test.3559553491 Apr 02 12:32:04 PM PDT 24 Apr 02 12:32:06 PM PDT 24 13090339 ps
T933 /workspace/coverage/cover_reg_top/15.edn_intr_test.1060149938 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:31 PM PDT 24 15768463 ps
T934 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3093017755 Apr 02 12:31:47 PM PDT 24 Apr 02 12:31:48 PM PDT 24 49139605 ps
T935 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.809283318 Apr 02 12:32:55 PM PDT 24 Apr 02 12:32:59 PM PDT 24 228544544 ps
T936 /workspace/coverage/cover_reg_top/33.edn_intr_test.1476989268 Apr 02 12:31:54 PM PDT 24 Apr 02 12:31:55 PM PDT 24 16024707 ps
T937 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2215492034 Apr 02 12:31:59 PM PDT 24 Apr 02 12:32:02 PM PDT 24 350835156 ps
T938 /workspace/coverage/cover_reg_top/22.edn_intr_test.1121220608 Apr 02 12:31:34 PM PDT 24 Apr 02 12:31:35 PM PDT 24 49550490 ps
T939 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1671841616 Apr 02 12:32:58 PM PDT 24 Apr 02 12:33:02 PM PDT 24 423373676 ps
T940 /workspace/coverage/cover_reg_top/25.edn_intr_test.2575165676 Apr 02 12:31:45 PM PDT 24 Apr 02 12:31:46 PM PDT 24 26847387 ps
T941 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2603302881 Apr 02 12:31:31 PM PDT 24 Apr 02 12:31:33 PM PDT 24 65452473 ps
T942 /workspace/coverage/cover_reg_top/41.edn_intr_test.3891849785 Apr 02 12:31:32 PM PDT 24 Apr 02 12:31:34 PM PDT 24 19537191 ps
T943 /workspace/coverage/cover_reg_top/14.edn_intr_test.4180546639 Apr 02 12:31:43 PM PDT 24 Apr 02 12:31:44 PM PDT 24 23868547 ps
T944 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2183730187 Apr 02 12:31:43 PM PDT 24 Apr 02 12:31:45 PM PDT 24 30461454 ps
T215 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3431416183 Apr 02 12:31:49 PM PDT 24 Apr 02 12:31:49 PM PDT 24 26550518 ps
T945 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1964015397 Apr 02 12:31:32 PM PDT 24 Apr 02 12:31:34 PM PDT 24 340159514 ps
T946 /workspace/coverage/cover_reg_top/17.edn_intr_test.2599035074 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:29 PM PDT 24 42588865 ps
T216 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2355860310 Apr 02 12:31:30 PM PDT 24 Apr 02 12:31:31 PM PDT 24 15394739 ps
T947 /workspace/coverage/cover_reg_top/21.edn_intr_test.2219208673 Apr 02 12:31:35 PM PDT 24 Apr 02 12:31:38 PM PDT 24 34798126 ps
T948 /workspace/coverage/cover_reg_top/17.edn_csr_rw.439838634 Apr 02 12:31:33 PM PDT 24 Apr 02 12:31:44 PM PDT 24 14820758 ps
T949 /workspace/coverage/cover_reg_top/3.edn_intr_test.2523794158 Apr 02 12:32:38 PM PDT 24 Apr 02 12:32:39 PM PDT 24 19802010 ps
T950 /workspace/coverage/cover_reg_top/32.edn_intr_test.2614814205 Apr 02 12:31:56 PM PDT 24 Apr 02 12:31:57 PM PDT 24 14538327 ps
T951 /workspace/coverage/cover_reg_top/29.edn_intr_test.1045670083 Apr 02 12:31:55 PM PDT 24 Apr 02 12:31:56 PM PDT 24 132354762 ps
T952 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.786722961 Apr 02 12:32:15 PM PDT 24 Apr 02 12:32:16 PM PDT 24 15085191 ps
T953 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4013670331 Apr 02 12:31:54 PM PDT 24 Apr 02 12:31:57 PM PDT 24 888785895 ps
T954 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3004290440 Apr 02 12:32:00 PM PDT 24 Apr 02 12:32:01 PM PDT 24 81436173 ps
T217 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3823420365 Apr 02 12:31:31 PM PDT 24 Apr 02 12:31:32 PM PDT 24 33848999 ps
T955 /workspace/coverage/cover_reg_top/5.edn_intr_test.821549958 Apr 02 12:32:38 PM PDT 24 Apr 02 12:32:39 PM PDT 24 60102463 ps
T956 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2462369754 Apr 02 12:31:29 PM PDT 24 Apr 02 12:31:30 PM PDT 24 26430157 ps
T957 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4020186293 Apr 02 12:31:32 PM PDT 24 Apr 02 12:31:34 PM PDT 24 94912573 ps
T958 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1582856596 Apr 02 12:32:23 PM PDT 24 Apr 02 12:32:25 PM PDT 24 22627561 ps
T959 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1647546017 Apr 02 12:31:25 PM PDT 24 Apr 02 12:31:26 PM PDT 24 156763284 ps
T960 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1073639682 Apr 02 12:31:50 PM PDT 24 Apr 02 12:31:54 PM PDT 24 613467662 ps
T961 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4154537217 Apr 02 12:31:31 PM PDT 24 Apr 02 12:31:38 PM PDT 24 171331972 ps
T962 /workspace/coverage/cover_reg_top/45.edn_intr_test.325251037 Apr 02 12:32:02 PM PDT 24 Apr 02 12:32:03 PM PDT 24 22504883 ps
T963 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4191570601 Apr 02 12:31:28 PM PDT 24 Apr 02 12:31:30 PM PDT 24 130068624 ps
T964 /workspace/coverage/cover_reg_top/35.edn_intr_test.3667886288 Apr 02 12:31:50 PM PDT 24 Apr 02 12:31:51 PM PDT 24 32878702 ps
T218 /workspace/coverage/cover_reg_top/4.edn_csr_rw.558151786 Apr 02 12:31:37 PM PDT 24 Apr 02 12:31:39 PM PDT 24 19342604 ps
T965 /workspace/coverage/cover_reg_top/47.edn_intr_test.2371830874 Apr 02 12:32:00 PM PDT 24 Apr 02 12:32:01 PM PDT 24 13328241 ps
T966 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1466148934 Apr 02 12:31:58 PM PDT 24 Apr 02 12:32:03 PM PDT 24 152402253 ps
T967 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3584242943 Apr 02 12:31:34 PM PDT 24 Apr 02 12:31:36 PM PDT 24 40533930 ps
T968 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1736494418 Apr 02 12:32:44 PM PDT 24 Apr 02 12:32:49 PM PDT 24 174597256 ps

Test location /workspace/coverage/default/182.edn_genbits.2104143556
Short name T20
Test name
Test status
Simulation time 54871623 ps
CPU time 1.66 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:23 PM PDT 24
Peak memory 218232 kb
Host smart-805e35d7-4d32-4c59-a9da-74ea0f72abc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104143556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2104143556
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3107965309
Short name T22
Test name
Test status
Simulation time 112182019478 ps
CPU time 1211.87 seconds
Started Apr 02 01:36:46 PM PDT 24
Finished Apr 02 01:56:58 PM PDT 24
Peak memory 223024 kb
Host smart-b22d2dda-4f17-4933-938d-d220e56cda14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107965309 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3107965309
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4133572954
Short name T58
Test name
Test status
Simulation time 211638930 ps
CPU time 1.19 seconds
Started Apr 02 01:36:43 PM PDT 24
Finished Apr 02 01:36:45 PM PDT 24
Peak memory 216536 kb
Host smart-d311e67c-c5b4-437c-a7ea-d76177bfe388
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133572954 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4133572954
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.2671107860
Short name T1
Test name
Test status
Simulation time 24763066 ps
CPU time 1.11 seconds
Started Apr 02 01:35:22 PM PDT 24
Finished Apr 02 01:35:24 PM PDT 24
Peak memory 215588 kb
Host smart-326d0c03-3934-46c8-83a7-52d2201e37c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671107860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2671107860
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1804241546
Short name T17
Test name
Test status
Simulation time 374221779 ps
CPU time 3.87 seconds
Started Apr 02 01:34:32 PM PDT 24
Finished Apr 02 01:34:36 PM PDT 24
Peak memory 234596 kb
Host smart-ba564a0a-7436-4964-9218-c0d8deef559f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804241546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1804241546
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/43.edn_err.1031561926
Short name T14
Test name
Test status
Simulation time 35456362 ps
CPU time 0.96 seconds
Started Apr 02 01:37:15 PM PDT 24
Finished Apr 02 01:37:16 PM PDT 24
Peak memory 231292 kb
Host smart-f8da4e40-45ab-48ae-b7d9-d867ad7a0254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031561926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1031561926
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1329277558
Short name T60
Test name
Test status
Simulation time 21800373 ps
CPU time 0.99 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 01:36:10 PM PDT 24
Peak memory 217308 kb
Host smart-fa59b810-01b1-4f48-a876-3e503fa91e33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329277558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1329277558
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.3038503843
Short name T26
Test name
Test status
Simulation time 24378280 ps
CPU time 1.31 seconds
Started Apr 02 01:36:00 PM PDT 24
Finished Apr 02 01:36:01 PM PDT 24
Peak memory 217944 kb
Host smart-300cb7cf-3242-43f0-8930-2ea81cd39fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038503843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3038503843
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3974412932
Short name T133
Test name
Test status
Simulation time 38070900628 ps
CPU time 860.24 seconds
Started Apr 02 01:35:42 PM PDT 24
Finished Apr 02 01:50:02 PM PDT 24
Peak memory 219576 kb
Host smart-4451694b-d85c-42d5-8359-8c450d818862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974412932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3974412932
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2510419789
Short name T63
Test name
Test status
Simulation time 36789263 ps
CPU time 1.38 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 215544 kb
Host smart-ee7f1ea2-572b-41af-8f47-70a60d71b6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510419789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2510419789
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/17.edn_intr.1526669671
Short name T113
Test name
Test status
Simulation time 36968545 ps
CPU time 0.91 seconds
Started Apr 02 01:35:41 PM PDT 24
Finished Apr 02 01:35:42 PM PDT 24
Peak memory 215528 kb
Host smart-2cc8687a-5269-4a84-9d99-50a936b870da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526669671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1526669671
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/43.edn_alert.3800048103
Short name T111
Test name
Test status
Simulation time 28834635 ps
CPU time 1.25 seconds
Started Apr 02 01:37:18 PM PDT 24
Finished Apr 02 01:37:20 PM PDT 24
Peak memory 215592 kb
Host smart-ee8bbafd-124f-40d2-8d2a-b91b70b50f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800048103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3800048103
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.1120216457
Short name T260
Test name
Test status
Simulation time 163029151 ps
CPU time 0.85 seconds
Started Apr 02 01:34:17 PM PDT 24
Finished Apr 02 01:34:18 PM PDT 24
Peak memory 206908 kb
Host smart-8ee7659c-3641-4307-9062-dd038a59dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120216457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1120216457
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/138.edn_genbits.3775573129
Short name T191
Test name
Test status
Simulation time 93190459 ps
CPU time 1.27 seconds
Started Apr 02 01:38:12 PM PDT 24
Finished Apr 02 01:38:14 PM PDT 24
Peak memory 217892 kb
Host smart-b38686d9-86d4-4b38-81df-8d1106fedb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775573129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3775573129
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_disable.2849787739
Short name T3
Test name
Test status
Simulation time 15815398 ps
CPU time 0.95 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 01:36:10 PM PDT 24
Peak memory 215856 kb
Host smart-909b6832-8806-4ae0-82b3-6b5bc334fbd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849787739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2849787739
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2125494554
Short name T205
Test name
Test status
Simulation time 62618538 ps
CPU time 0.94 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206224 kb
Host smart-7fcdabdb-0c8e-47f6-b30b-42b7c8d65999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125494554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2125494554
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/1.edn_alert.3757114540
Short name T92
Test name
Test status
Simulation time 58124817 ps
CPU time 1.11 seconds
Started Apr 02 01:34:25 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 215556 kb
Host smart-44bbe058-62f1-4550-9a7b-4e54d993b948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757114540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3757114540
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/35.edn_disable.1209871111
Short name T107
Test name
Test status
Simulation time 39795650 ps
CPU time 0.87 seconds
Started Apr 02 01:36:49 PM PDT 24
Finished Apr 02 01:36:50 PM PDT 24
Peak memory 215836 kb
Host smart-aa6b4016-9238-4c33-b010-155427c408a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209871111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1209871111
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3947235549
Short name T250
Test name
Test status
Simulation time 150452965 ps
CPU time 1.43 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206448 kb
Host smart-51579f98-6438-4e94-8baa-1b02f83b2dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947235549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3947235549
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/19.edn_disable.158849306
Short name T147
Test name
Test status
Simulation time 42470898 ps
CPU time 0.95 seconds
Started Apr 02 01:35:57 PM PDT 24
Finished Apr 02 01:35:58 PM PDT 24
Peak memory 215892 kb
Host smart-0116aef6-b6c7-487f-a3c0-566ab825b155
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158849306 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.158849306
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.3087258193
Short name T125
Test name
Test status
Simulation time 21433411 ps
CPU time 0.99 seconds
Started Apr 02 01:35:16 PM PDT 24
Finished Apr 02 01:35:17 PM PDT 24
Peak memory 215708 kb
Host smart-bb433144-b022-4e20-b5e9-15b50b888dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087258193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3087258193
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4281884179
Short name T61
Test name
Test status
Simulation time 51063744 ps
CPU time 1.08 seconds
Started Apr 02 01:36:34 PM PDT 24
Finished Apr 02 01:36:35 PM PDT 24
Peak memory 216772 kb
Host smart-8235f75d-9426-4796-8391-75188fc64d60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281884179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4281884179
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/196.edn_genbits.2870559912
Short name T467
Test name
Test status
Simulation time 157327679 ps
CPU time 2.14 seconds
Started Apr 02 01:38:24 PM PDT 24
Finished Apr 02 01:38:26 PM PDT 24
Peak memory 218360 kb
Host smart-2506bff6-7b4f-4e97-86dc-b9e961b25a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870559912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2870559912
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_disable.2385498104
Short name T519
Test name
Test status
Simulation time 18775207 ps
CPU time 0.89 seconds
Started Apr 02 01:37:30 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 207184 kb
Host smart-687b12fe-7a35-4504-a44b-982c8ab72dba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385498104 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2385498104
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable.780960807
Short name T108
Test name
Test status
Simulation time 16648048 ps
CPU time 0.84 seconds
Started Apr 02 01:37:04 PM PDT 24
Finished Apr 02 01:37:06 PM PDT 24
Peak memory 215748 kb
Host smart-7e15c357-7302-46c2-8d63-74cdce700fd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780960807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.780960807
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/3.edn_regwen.2607973337
Short name T126
Test name
Test status
Simulation time 40358342 ps
CPU time 0.93 seconds
Started Apr 02 01:34:31 PM PDT 24
Finished Apr 02 01:34:32 PM PDT 24
Peak memory 207096 kb
Host smart-ff557590-f453-43b7-89fe-b7dd23e81e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607973337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2607973337
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/24.edn_disable.3212953935
Short name T162
Test name
Test status
Simulation time 26466013 ps
CPU time 0.84 seconds
Started Apr 02 01:36:15 PM PDT 24
Finished Apr 02 01:36:15 PM PDT 24
Peak memory 215856 kb
Host smart-314002b5-b938-411c-a02d-1541c4502587
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212953935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3212953935
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable.3079031932
Short name T28
Test name
Test status
Simulation time 14617849 ps
CPU time 0.99 seconds
Started Apr 02 01:37:13 PM PDT 24
Finished Apr 02 01:37:14 PM PDT 24
Peak memory 216044 kb
Host smart-6f8ca4a2-95c9-4710-9b28-616e77fca9b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079031932 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3079031932
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/10.edn_genbits.3320467104
Short name T164
Test name
Test status
Simulation time 76649304 ps
CPU time 1.06 seconds
Started Apr 02 01:35:17 PM PDT 24
Finished Apr 02 01:35:18 PM PDT 24
Peak memory 216588 kb
Host smart-290dc028-64be-4578-9ab8-c35ebf4fdcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320467104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3320467104
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.3719152454
Short name T102
Test name
Test status
Simulation time 33168295 ps
CPU time 0.84 seconds
Started Apr 02 01:34:25 PM PDT 24
Finished Apr 02 01:34:26 PM PDT 24
Peak memory 215808 kb
Host smart-f1e4c9a9-0389-439b-bcb3-ef0d1dece98b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719152454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3719152454
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1483173023
Short name T789
Test name
Test status
Simulation time 41825559 ps
CPU time 1.41 seconds
Started Apr 02 01:35:21 PM PDT 24
Finished Apr 02 01:35:22 PM PDT 24
Peak memory 216400 kb
Host smart-8a6f897c-fa5d-4764-bdc7-9f36b443a7dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483173023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1483173023
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4036148344
Short name T67
Test name
Test status
Simulation time 153906995 ps
CPU time 1.17 seconds
Started Apr 02 01:35:26 PM PDT 24
Finished Apr 02 01:35:27 PM PDT 24
Peak memory 216372 kb
Host smart-a7e41df0-bb6c-4094-8b52-fe94db226fe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036148344 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4036148344
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1630513124
Short name T691
Test name
Test status
Simulation time 61460284 ps
CPU time 1.18 seconds
Started Apr 02 01:35:30 PM PDT 24
Finished Apr 02 01:35:31 PM PDT 24
Peak memory 216460 kb
Host smart-ad342370-7baf-436f-8a89-bb6339527eca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630513124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1630513124
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3059161383
Short name T83
Test name
Test status
Simulation time 65993357 ps
CPU time 1.2 seconds
Started Apr 02 01:35:36 PM PDT 24
Finished Apr 02 01:35:38 PM PDT 24
Peak memory 216204 kb
Host smart-637419a9-5d37-4ee3-ba47-4f6057dd044f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059161383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3059161383
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.3873182127
Short name T109
Test name
Test status
Simulation time 19845539 ps
CPU time 0.88 seconds
Started Apr 02 01:35:43 PM PDT 24
Finished Apr 02 01:35:44 PM PDT 24
Peak memory 215800 kb
Host smart-952f40a4-da47-45ab-8c12-c5f8cdc83cc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873182127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3873182127
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable.2032165728
Short name T90
Test name
Test status
Simulation time 11413971 ps
CPU time 0.89 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:37:28 PM PDT 24
Peak memory 216004 kb
Host smart-06fdbc02-5bc8-41d1-92b9-7768eeee7f3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032165728 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2032165728
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3177701864
Short name T181
Test name
Test status
Simulation time 45122338153 ps
CPU time 1054.94 seconds
Started Apr 02 01:35:29 PM PDT 24
Finished Apr 02 01:53:04 PM PDT 24
Peak memory 218728 kb
Host smart-a86c6047-115c-4a4d-8314-ed6a1d15e952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177701864 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3177701864
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.edn_genbits.1066115002
Short name T54
Test name
Test status
Simulation time 80848159 ps
CPU time 1.05 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 217788 kb
Host smart-0fae497c-e4b2-481c-939b-b20a4649a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066115002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1066115002
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.1750291770
Short name T838
Test name
Test status
Simulation time 18200778 ps
CPU time 1.02 seconds
Started Apr 02 01:35:10 PM PDT 24
Finished Apr 02 01:35:11 PM PDT 24
Peak memory 207156 kb
Host smart-9169c9af-f58a-42b8-bf41-b1fc75d0223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750291770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1750291770
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/13.edn_alert_test.574564362
Short name T339
Test name
Test status
Simulation time 20649657 ps
CPU time 1.07 seconds
Started Apr 02 01:35:32 PM PDT 24
Finished Apr 02 01:35:36 PM PDT 24
Peak memory 206584 kb
Host smart-20411fb2-6937-4a33-91b5-f2919ebb7412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574564362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.574564362
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4056722280
Short name T249
Test name
Test status
Simulation time 40677986 ps
CPU time 1.53 seconds
Started Apr 02 12:31:53 PM PDT 24
Finished Apr 02 12:31:55 PM PDT 24
Peak memory 206360 kb
Host smart-b1d4c20e-ade4-424b-80c9-6e55ef160d53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056722280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4056722280
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/107.edn_genbits.1121539341
Short name T298
Test name
Test status
Simulation time 67829254 ps
CPU time 1.41 seconds
Started Apr 02 01:38:05 PM PDT 24
Finished Apr 02 01:38:07 PM PDT 24
Peak memory 217564 kb
Host smart-37f18626-aeeb-46b8-8084-2ad200f8a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121539341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1121539341
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/210.edn_genbits.3732684609
Short name T289
Test name
Test status
Simulation time 56228622 ps
CPU time 1.31 seconds
Started Apr 02 01:38:27 PM PDT 24
Finished Apr 02 01:38:29 PM PDT 24
Peak memory 218028 kb
Host smart-d36cb021-5be6-464d-a292-2bc00f59e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732684609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3732684609
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3748606552
Short name T379
Test name
Test status
Simulation time 51330606 ps
CPU time 1.81 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 217944 kb
Host smart-9c0f4c82-36ee-4e41-8652-1a1f2d1f59b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748606552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3748606552
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.387550191
Short name T49
Test name
Test status
Simulation time 37120407 ps
CPU time 1.15 seconds
Started Apr 02 01:36:20 PM PDT 24
Finished Apr 02 01:36:21 PM PDT 24
Peak memory 215648 kb
Host smart-4b8223ce-6499-4533-bd7a-6570d878ecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387550191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.387550191
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/32.edn_intr.397459867
Short name T123
Test name
Test status
Simulation time 28735870 ps
CPU time 0.99 seconds
Started Apr 02 01:36:37 PM PDT 24
Finished Apr 02 01:36:39 PM PDT 24
Peak memory 215716 kb
Host smart-b24c0947-12bc-4319-bbec-e20c7d1e94d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397459867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.397459867
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/36.edn_alert.4217194198
Short name T264
Test name
Test status
Simulation time 381187049 ps
CPU time 1.5 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 215544 kb
Host smart-41304488-64b3-436a-ba4c-611b9a159a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217194198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4217194198
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/236.edn_genbits.2752294240
Short name T287
Test name
Test status
Simulation time 36456279 ps
CPU time 1.42 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 217800 kb
Host smart-ba623f68-d4f2-4b15-9c09-185f3722e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752294240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2752294240
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2351785876
Short name T201
Test name
Test status
Simulation time 16002444 ps
CPU time 0.84 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206284 kb
Host smart-f593a512-78b9-4bb3-896c-f9b0435ac789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351785876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2351785876
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_alert.1125126980
Short name T620
Test name
Test status
Simulation time 26099647 ps
CPU time 1.24 seconds
Started Apr 02 01:34:23 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 215572 kb
Host smart-f46e2283-4135-4b4a-8e1b-4e3cdfd0328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125126980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1125126980
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_stress_all.2583366761
Short name T465
Test name
Test status
Simulation time 315652339 ps
CPU time 6.66 seconds
Started Apr 02 01:34:25 PM PDT 24
Finished Apr 02 01:34:32 PM PDT 24
Peak memory 216788 kb
Host smart-31d47a2c-348a-474d-b205-c21c55a894d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583366761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2583366761
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/103.edn_genbits.3369822714
Short name T278
Test name
Test status
Simulation time 35584801 ps
CPU time 1.39 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:06 PM PDT 24
Peak memory 217924 kb
Host smart-92fd1a82-a972-4592-9013-1dc3eb402f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369822714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3369822714
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1551530452
Short name T94
Test name
Test status
Simulation time 113929391 ps
CPU time 1.09 seconds
Started Apr 02 01:35:40 PM PDT 24
Finished Apr 02 01:35:42 PM PDT 24
Peak memory 215636 kb
Host smart-6fa2ecbc-628e-4ea9-98ed-9c43fbe86808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551530452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1551530452
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.357675962
Short name T276
Test name
Test status
Simulation time 1085669544 ps
CPU time 8 seconds
Started Apr 02 01:38:12 PM PDT 24
Finished Apr 02 01:38:21 PM PDT 24
Peak memory 216744 kb
Host smart-d26e5a92-037e-4de7-9910-1a5bd64e06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357675962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.357675962
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.226605786
Short name T294
Test name
Test status
Simulation time 123214075 ps
CPU time 1.47 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:23 PM PDT 24
Peak memory 218008 kb
Host smart-6e6c630c-cffd-4fba-a971-0c2a96135d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226605786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.226605786
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2004466118
Short name T742
Test name
Test status
Simulation time 53860049 ps
CPU time 1.36 seconds
Started Apr 02 01:38:33 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 216660 kb
Host smart-ebbe838d-68b0-4395-88cb-ff6d38bdc111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004466118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2004466118
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3599080447
Short name T285
Test name
Test status
Simulation time 101305005 ps
CPU time 1.53 seconds
Started Apr 02 01:38:49 PM PDT 24
Finished Apr 02 01:38:50 PM PDT 24
Peak memory 218028 kb
Host smart-72621f99-db6d-43a7-ab55-c848d0fd3cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599080447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3599080447
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1489570133
Short name T273
Test name
Test status
Simulation time 187346361 ps
CPU time 2.41 seconds
Started Apr 02 01:38:50 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 219588 kb
Host smart-93218c20-ad5f-42cc-b5bc-830f11e2df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489570133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1489570133
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_genbits.1905584007
Short name T284
Test name
Test status
Simulation time 45622075 ps
CPU time 1.17 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:59 PM PDT 24
Peak memory 215184 kb
Host smart-5fa8b12c-6f5c-46c1-bf96-c81d7131a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905584007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1905584007
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3041674257
Short name T576
Test name
Test status
Simulation time 31110813 ps
CPU time 0.97 seconds
Started Apr 02 01:36:22 PM PDT 24
Finished Apr 02 01:36:23 PM PDT 24
Peak memory 215648 kb
Host smart-e22143e7-2cad-4d1a-83b3-92d7c2d4b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041674257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3041674257
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/1.edn_err.3447123401
Short name T608
Test name
Test status
Simulation time 21298092 ps
CPU time 0.98 seconds
Started Apr 02 01:34:29 PM PDT 24
Finished Apr 02 01:34:31 PM PDT 24
Peak memory 232556 kb
Host smart-f0a4552f-8e76-4141-a7af-de71ebc979a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447123401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3447123401
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/0.edn_err.3591781148
Short name T7
Test name
Test status
Simulation time 26911470 ps
CPU time 1.24 seconds
Started Apr 02 01:34:23 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 220188 kb
Host smart-610635a1-c091-4043-b674-59812a1c0a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591781148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3591781148
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.212333706
Short name T877
Test name
Test status
Simulation time 80699406 ps
CPU time 1.27 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206196 kb
Host smart-e60fc062-00b5-45d7-8ac9-f89df3684ea1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212333706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.212333706
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2659971395
Short name T886
Test name
Test status
Simulation time 180907094 ps
CPU time 4.75 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 206208 kb
Host smart-65045560-e54d-4dcc-b574-94b520445274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659971395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2659971395
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2462369754
Short name T956
Test name
Test status
Simulation time 26430157 ps
CPU time 1.02 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206416 kb
Host smart-d39a1111-38e2-4c46-9313-4ebc04fd3409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462369754 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2462369754
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2474754738
Short name T866
Test name
Test status
Simulation time 30294365 ps
CPU time 0.76 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206008 kb
Host smart-74e46321-0510-4116-96d1-811a825b7521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474754738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2474754738
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4191571459
Short name T892
Test name
Test status
Simulation time 17293145 ps
CPU time 1.11 seconds
Started Apr 02 12:32:53 PM PDT 24
Finished Apr 02 12:32:55 PM PDT 24
Peak memory 206288 kb
Host smart-e72d85e9-5351-4db2-af6b-9d55bcd313c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191571459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4191571459
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1074450804
Short name T864
Test name
Test status
Simulation time 64115946 ps
CPU time 2.49 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 214576 kb
Host smart-2df00ebe-ed0e-4453-b37e-cb90a9fdce6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074450804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1074450804
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.849308671
Short name T915
Test name
Test status
Simulation time 297225431 ps
CPU time 2.52 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206340 kb
Host smart-c4e6a2ac-1ba2-49e4-98a4-e8d2fb25a2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849308671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.849308671
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.178204894
Short name T212
Test name
Test status
Simulation time 174953819 ps
CPU time 1.23 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206348 kb
Host smart-d489faa3-cebb-4784-8684-593d29fd5076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178204894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.178204894
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1786847303
Short name T204
Test name
Test status
Simulation time 299495468 ps
CPU time 5.43 seconds
Started Apr 02 12:32:48 PM PDT 24
Finished Apr 02 12:32:54 PM PDT 24
Peak memory 206132 kb
Host smart-c8392df7-8bfe-4384-833a-93cb9ae494a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786847303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1786847303
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.718937444
Short name T209
Test name
Test status
Simulation time 22649319 ps
CPU time 0.85 seconds
Started Apr 02 12:32:45 PM PDT 24
Finished Apr 02 12:32:46 PM PDT 24
Peak memory 206128 kb
Host smart-4af1fb2e-3f84-4792-b803-cfc1af41de96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718937444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.718937444
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.138731954
Short name T931
Test name
Test status
Simulation time 45569083 ps
CPU time 1.27 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 214620 kb
Host smart-00ce4aa9-7fa7-4b8b-a971-4b7dead51649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138731954 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.138731954
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3507255145
Short name T220
Test name
Test status
Simulation time 42051881 ps
CPU time 0.86 seconds
Started Apr 02 12:31:36 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 206252 kb
Host smart-0b9d83fb-2780-44a8-bf9b-83f1c9b83352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507255145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3507255145
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3105165028
Short name T851
Test name
Test status
Simulation time 44042593 ps
CPU time 0.85 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206156 kb
Host smart-be2b6d62-366b-4ed4-a5e6-28250dc8e90b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105165028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3105165028
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2128783680
Short name T221
Test name
Test status
Simulation time 16085404 ps
CPU time 1 seconds
Started Apr 02 12:32:49 PM PDT 24
Finished Apr 02 12:32:51 PM PDT 24
Peak memory 206264 kb
Host smart-60569b4e-e205-450a-a00d-48fe80d403dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128783680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2128783680
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3143795006
Short name T908
Test name
Test status
Simulation time 171671578 ps
CPU time 1.79 seconds
Started Apr 02 12:32:27 PM PDT 24
Finished Apr 02 12:32:29 PM PDT 24
Peak memory 213764 kb
Host smart-dee10dd1-9081-4b3a-b42c-f356d2d0545f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143795006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3143795006
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1127276949
Short name T916
Test name
Test status
Simulation time 41932303 ps
CPU time 1.47 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 206388 kb
Host smart-1916ce28-ca3f-42f8-81ed-6ac38f91151d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127276949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1127276949
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.852064895
Short name T846
Test name
Test status
Simulation time 65573971 ps
CPU time 1.37 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 214708 kb
Host smart-07612a5a-bd36-4e68-9970-cc7950579b27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852064895 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.852064895
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2704605596
Short name T872
Test name
Test status
Simulation time 16995557 ps
CPU time 0.91 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206164 kb
Host smart-7a19787e-4d9a-4f0e-881a-718137ea64b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704605596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2704605596
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1434612146
Short name T900
Test name
Test status
Simulation time 14701711 ps
CPU time 0.88 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206144 kb
Host smart-d379d6c2-86e0-4f7f-88de-c776b63275ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434612146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1434612146
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.752932620
Short name T870
Test name
Test status
Simulation time 48518155 ps
CPU time 1.4 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206440 kb
Host smart-be04cc2c-5785-4f3d-90ac-a2aa21e0bd08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752932620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.752932620
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3211205934
Short name T843
Test name
Test status
Simulation time 523256666 ps
CPU time 4.49 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 218244 kb
Host smart-d1e125ca-1c37-4650-b648-afb806e3b9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211205934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3211205934
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2215492034
Short name T937
Test name
Test status
Simulation time 350835156 ps
CPU time 2.33 seconds
Started Apr 02 12:31:59 PM PDT 24
Finished Apr 02 12:32:02 PM PDT 24
Peak memory 206312 kb
Host smart-36ee2e54-d9df-4357-accc-5116316d0c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215492034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2215492034
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4278305922
Short name T852
Test name
Test status
Simulation time 89238803 ps
CPU time 1.58 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 214552 kb
Host smart-1c50f682-c48d-43f4-b38e-134fe6e00246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278305922 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4278305922
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1647546017
Short name T959
Test name
Test status
Simulation time 156763284 ps
CPU time 0.83 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 206000 kb
Host smart-0c324849-640e-474d-89f3-64c965fc4541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647546017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1647546017
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1761372458
Short name T842
Test name
Test status
Simulation time 46474600 ps
CPU time 0.83 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 205960 kb
Host smart-1de4c259-26a5-4cc8-a47d-1b431eea5a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761372458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1761372458
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.772494835
Short name T206
Test name
Test status
Simulation time 25111400 ps
CPU time 1.05 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206328 kb
Host smart-00f146e2-2337-4b80-bc69-04615d71508c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772494835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.772494835
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.392058003
Short name T850
Test name
Test status
Simulation time 61804138 ps
CPU time 2.67 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 214628 kb
Host smart-bbe07fec-9c83-4e35-bdc7-8fc42fc148f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392058003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.392058003
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4075914224
Short name T918
Test name
Test status
Simulation time 88102943 ps
CPU time 2.35 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 206348 kb
Host smart-2fe2ec08-fa25-427a-873a-1c47c1b7967e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075914224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4075914224
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.719317965
Short name T857
Test name
Test status
Simulation time 49587788 ps
CPU time 1.36 seconds
Started Apr 02 12:31:32 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 214604 kb
Host smart-21f224d6-0dfd-48c9-9978-83b37c3afb42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719317965 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.719317965
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2355860310
Short name T216
Test name
Test status
Simulation time 15394739 ps
CPU time 0.95 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206208 kb
Host smart-39f41579-09c7-4221-be00-0b69a92f1b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355860310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2355860310
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.726236437
Short name T888
Test name
Test status
Simulation time 23830425 ps
CPU time 0.86 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206184 kb
Host smart-d7244f0b-311c-4d85-b821-4590c6b9f698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726236437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.726236437
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3004290440
Short name T954
Test name
Test status
Simulation time 81436173 ps
CPU time 0.95 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 206396 kb
Host smart-c1146b28-7a7b-48bb-805d-2bad7c7e577e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004290440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3004290440
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1073639682
Short name T960
Test name
Test status
Simulation time 613467662 ps
CPU time 3.63 seconds
Started Apr 02 12:31:50 PM PDT 24
Finished Apr 02 12:31:54 PM PDT 24
Peak memory 214596 kb
Host smart-18121f5b-7995-4ef9-a3b0-ff01ec2549a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073639682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1073639682
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1634504325
Short name T854
Test name
Test status
Simulation time 42345757 ps
CPU time 1.42 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 214604 kb
Host smart-e2f1b011-e73e-45c0-ac96-30db81908541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634504325 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1634504325
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1355709390
Short name T210
Test name
Test status
Simulation time 16478319 ps
CPU time 0.93 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206292 kb
Host smart-4b7cd7a1-81aa-4c11-89f5-0b149c2f9f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355709390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1355709390
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2726666585
Short name T901
Test name
Test status
Simulation time 13908829 ps
CPU time 0.84 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 206176 kb
Host smart-6e29dbf8-6d5e-49ad-8e82-215dc73df965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726666585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2726666585
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3584242943
Short name T967
Test name
Test status
Simulation time 40533930 ps
CPU time 1 seconds
Started Apr 02 12:31:34 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 206348 kb
Host smart-cefdbc48-82b2-4cef-a64c-89d4c01792c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584242943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3584242943
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3864261636
Short name T921
Test name
Test status
Simulation time 166323421 ps
CPU time 3.06 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 214792 kb
Host smart-b27e9156-11f7-44c9-8be0-f7bd338956cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864261636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3864261636
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1578945851
Short name T252
Test name
Test status
Simulation time 297010406 ps
CPU time 2.31 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206380 kb
Host smart-88162574-8594-4309-ad8f-2554131a96aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578945851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1578945851
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4020186293
Short name T957
Test name
Test status
Simulation time 94912573 ps
CPU time 1.73 seconds
Started Apr 02 12:31:32 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 214508 kb
Host smart-84843842-6f41-4692-b361-358420ff9ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020186293 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4020186293
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3065560377
Short name T849
Test name
Test status
Simulation time 42467963 ps
CPU time 0.79 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 205996 kb
Host smart-6d92c791-60dd-49a1-8591-7d7c610552bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065560377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3065560377
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4180546639
Short name T943
Test name
Test status
Simulation time 23868547 ps
CPU time 0.81 seconds
Started Apr 02 12:31:43 PM PDT 24
Finished Apr 02 12:31:44 PM PDT 24
Peak memory 206184 kb
Host smart-19cf29b2-a71b-4fbc-8bee-997507a86a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180546639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4180546639
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.184348911
Short name T203
Test name
Test status
Simulation time 15532325 ps
CPU time 0.95 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 206388 kb
Host smart-3c0ed922-887c-496d-91e3-b571d605b53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184348911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.184348911
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2853350529
Short name T863
Test name
Test status
Simulation time 294018156 ps
CPU time 2.55 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 214604 kb
Host smart-d0bbce80-fb68-441d-8d4f-7d9bcc35606e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853350529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2853350529
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4043071844
Short name T874
Test name
Test status
Simulation time 278698863 ps
CPU time 3.09 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 206388 kb
Host smart-833cb054-1417-460d-89b2-6f0aa3a82485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043071844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4043071844
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.786722961
Short name T952
Test name
Test status
Simulation time 15085191 ps
CPU time 0.94 seconds
Started Apr 02 12:32:15 PM PDT 24
Finished Apr 02 12:32:16 PM PDT 24
Peak memory 206276 kb
Host smart-99693519-3ad1-41d1-8600-07abe8279637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786722961 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.786722961
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.849891622
Short name T213
Test name
Test status
Simulation time 16026791 ps
CPU time 0.9 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206180 kb
Host smart-32d7bcc4-fc9c-487e-96a8-871845c87790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849891622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.849891622
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1060149938
Short name T933
Test name
Test status
Simulation time 15768463 ps
CPU time 0.87 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206212 kb
Host smart-f21ecfa4-ceec-4e9c-9f7d-901c4d159cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060149938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1060149938
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3711280990
Short name T202
Test name
Test status
Simulation time 76264353 ps
CPU time 1.08 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:46 PM PDT 24
Peak memory 206404 kb
Host smart-e94dbbfe-54a6-4989-a3b3-47429ca29418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711280990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3711280990
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2066246250
Short name T884
Test name
Test status
Simulation time 42133793 ps
CPU time 2.47 seconds
Started Apr 02 12:31:44 PM PDT 24
Finished Apr 02 12:31:47 PM PDT 24
Peak memory 214532 kb
Host smart-8409bb5d-9f1d-46ca-9e6e-4c6633028507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066246250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2066246250
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4191570601
Short name T963
Test name
Test status
Simulation time 130068624 ps
CPU time 1.15 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 214716 kb
Host smart-6e50e393-f225-4b0e-9a95-22e13946ba13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191570601 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4191570601
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3663697902
Short name T222
Test name
Test status
Simulation time 14093216 ps
CPU time 0.92 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:32:11 PM PDT 24
Peak memory 206208 kb
Host smart-31329491-fa52-4c20-8c9d-fe7965600348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663697902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3663697902
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2711400190
Short name T855
Test name
Test status
Simulation time 14134508 ps
CPU time 0.89 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206360 kb
Host smart-af765b3d-6cd6-447e-9533-a1517f64762d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711400190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2711400190
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2676432647
Short name T912
Test name
Test status
Simulation time 59716887 ps
CPU time 1.36 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206492 kb
Host smart-cfa2830e-b59a-45d4-b1fc-8fe20adbe14e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676432647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2676432647
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2573007332
Short name T890
Test name
Test status
Simulation time 1106871332 ps
CPU time 4.38 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 214616 kb
Host smart-6c108594-8cf6-4732-948d-02268a770cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573007332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2573007332
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4013670331
Short name T953
Test name
Test status
Simulation time 888785895 ps
CPU time 2.5 seconds
Started Apr 02 12:31:54 PM PDT 24
Finished Apr 02 12:31:57 PM PDT 24
Peak memory 206304 kb
Host smart-44958bdf-0710-4b2c-9778-01eddd46dc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013670331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4013670331
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3093017755
Short name T934
Test name
Test status
Simulation time 49139605 ps
CPU time 1.18 seconds
Started Apr 02 12:31:47 PM PDT 24
Finished Apr 02 12:31:48 PM PDT 24
Peak memory 214716 kb
Host smart-5c2a7882-528d-4f42-91f6-42db07144b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093017755 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3093017755
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.439838634
Short name T948
Test name
Test status
Simulation time 14820758 ps
CPU time 0.91 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:44 PM PDT 24
Peak memory 206144 kb
Host smart-07086796-d955-4729-9ad9-b28e6655ab7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439838634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.439838634
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2599035074
Short name T946
Test name
Test status
Simulation time 42588865 ps
CPU time 0.8 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206132 kb
Host smart-1147fe95-a2c2-4ad1-bcd1-25fb0a7d972c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599035074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2599035074
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.527556032
Short name T883
Test name
Test status
Simulation time 37844162 ps
CPU time 1.07 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 206268 kb
Host smart-7a0bd576-c98a-4f9a-8002-5d9e0d96e04a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527556032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.527556032
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3148053654
Short name T924
Test name
Test status
Simulation time 371955971 ps
CPU time 3.47 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 214564 kb
Host smart-84e69207-7fe7-4322-bf92-16f14999d747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148053654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3148053654
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1915877043
Short name T914
Test name
Test status
Simulation time 88841658 ps
CPU time 1.57 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206328 kb
Host smart-349dcc15-2729-46d9-b544-4da66a6a7257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915877043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1915877043
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2183730187
Short name T944
Test name
Test status
Simulation time 30461454 ps
CPU time 1.25 seconds
Started Apr 02 12:31:43 PM PDT 24
Finished Apr 02 12:31:45 PM PDT 24
Peak memory 214640 kb
Host smart-103b2109-5c33-45a9-ad53-6f0de4acf321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183730187 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2183730187
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3714792882
Short name T867
Test name
Test status
Simulation time 19209138 ps
CPU time 0.83 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:46 PM PDT 24
Peak memory 205976 kb
Host smart-24ce9eb3-0d2b-4bf8-86b8-e18d87ddd3de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714792882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3714792882
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1907987032
Short name T853
Test name
Test status
Simulation time 21327283 ps
CPU time 0.88 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:32:06 PM PDT 24
Peak memory 206220 kb
Host smart-ea031a60-8ffd-4e74-b015-b44dca8fdcec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907987032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1907987032
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1207674317
Short name T913
Test name
Test status
Simulation time 46581460 ps
CPU time 0.94 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 206316 kb
Host smart-e28e3f76-dcd3-4011-889e-d50901a87223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207674317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1207674317
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.4147183338
Short name T860
Test name
Test status
Simulation time 40861969 ps
CPU time 1.63 seconds
Started Apr 02 12:31:56 PM PDT 24
Finished Apr 02 12:31:58 PM PDT 24
Peak memory 214652 kb
Host smart-b4cb25cd-8c07-4b75-999c-c4ac16fcf3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147183338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4147183338
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3690267146
Short name T247
Test name
Test status
Simulation time 177673501 ps
CPU time 1.72 seconds
Started Apr 02 12:31:32 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 206396 kb
Host smart-ddd2888c-8675-4542-8f35-e27bf772307a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690267146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3690267146
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.981993047
Short name T873
Test name
Test status
Simulation time 54208230 ps
CPU time 1.39 seconds
Started Apr 02 12:32:07 PM PDT 24
Finished Apr 02 12:32:10 PM PDT 24
Peak memory 214680 kb
Host smart-91a68967-5753-4a03-baf9-ff2a3c9d9d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981993047 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.981993047
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.311819179
Short name T885
Test name
Test status
Simulation time 14349599 ps
CPU time 0.89 seconds
Started Apr 02 12:31:40 PM PDT 24
Finished Apr 02 12:31:41 PM PDT 24
Peak memory 206184 kb
Host smart-74c3fbe8-c5bd-410d-88d5-43a6e34385c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311819179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.311819179
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3231751402
Short name T905
Test name
Test status
Simulation time 16153840 ps
CPU time 0.92 seconds
Started Apr 02 12:32:11 PM PDT 24
Finished Apr 02 12:32:12 PM PDT 24
Peak memory 206176 kb
Host smart-0ce7e933-0432-456f-afb0-15101a33b7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231751402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3231751402
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.838847638
Short name T881
Test name
Test status
Simulation time 39654523 ps
CPU time 1.44 seconds
Started Apr 02 12:32:02 PM PDT 24
Finished Apr 02 12:32:04 PM PDT 24
Peak memory 206356 kb
Host smart-32d50c80-b9b7-4dd3-9f64-460a1f20cfb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838847638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.838847638
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1979383814
Short name T861
Test name
Test status
Simulation time 72585416 ps
CPU time 2.88 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:48 PM PDT 24
Peak memory 214592 kb
Host smart-0187a934-9a07-44f9-b834-a65906add5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979383814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1979383814
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2063984427
Short name T904
Test name
Test status
Simulation time 70614070 ps
CPU time 1.97 seconds
Started Apr 02 12:31:57 PM PDT 24
Finished Apr 02 12:31:59 PM PDT 24
Peak memory 206376 kb
Host smart-0f0be119-0cc2-4529-b596-3babcb70298f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063984427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2063984427
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4020945499
Short name T911
Test name
Test status
Simulation time 43629065 ps
CPU time 1.62 seconds
Started Apr 02 12:31:51 PM PDT 24
Finished Apr 02 12:31:52 PM PDT 24
Peak memory 206212 kb
Host smart-ae6c60db-8ae7-4589-9073-f1a6b34be9c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020945499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4020945499
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1736494418
Short name T968
Test name
Test status
Simulation time 174597256 ps
CPU time 4.72 seconds
Started Apr 02 12:32:44 PM PDT 24
Finished Apr 02 12:32:49 PM PDT 24
Peak memory 206128 kb
Host smart-36322a1c-ea61-4286-8e0c-105e7798c50a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736494418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1736494418
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1282763408
Short name T893
Test name
Test status
Simulation time 47399585 ps
CPU time 0.85 seconds
Started Apr 02 12:32:59 PM PDT 24
Finished Apr 02 12:33:00 PM PDT 24
Peak memory 206132 kb
Host smart-fb886d1a-48d3-4060-9dfd-07d19d676e40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282763408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1282763408
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1883865919
Short name T899
Test name
Test status
Simulation time 25455207 ps
CPU time 1.56 seconds
Started Apr 02 12:32:47 PM PDT 24
Finished Apr 02 12:32:48 PM PDT 24
Peak memory 214608 kb
Host smart-ae1b52a3-194c-45cd-9671-1ed125ed623a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883865919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1883865919
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3431416183
Short name T215
Test name
Test status
Simulation time 26550518 ps
CPU time 0.79 seconds
Started Apr 02 12:31:49 PM PDT 24
Finished Apr 02 12:31:49 PM PDT 24
Peak memory 206032 kb
Host smart-66088f70-9166-4f24-832f-ab42702d367f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431416183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3431416183
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2877816733
Short name T902
Test name
Test status
Simulation time 10875144 ps
CPU time 0.82 seconds
Started Apr 02 12:31:50 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 206208 kb
Host smart-8a21ed06-44dd-4b73-bb28-d6361189172a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877816733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2877816733
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4154537217
Short name T961
Test name
Test status
Simulation time 171331972 ps
CPU time 1.45 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 206280 kb
Host smart-2f90937f-4854-493c-9abe-a80540d1ec0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154537217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4154537217
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4237038739
Short name T929
Test name
Test status
Simulation time 239968171 ps
CPU time 1.86 seconds
Started Apr 02 12:32:47 PM PDT 24
Finished Apr 02 12:32:49 PM PDT 24
Peak memory 217200 kb
Host smart-6d59bb3b-0f8d-4018-802b-f89802c88c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237038739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4237038739
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2625452634
Short name T253
Test name
Test status
Simulation time 158251679 ps
CPU time 1.48 seconds
Started Apr 02 12:31:21 PM PDT 24
Finished Apr 02 12:31:23 PM PDT 24
Peak memory 206276 kb
Host smart-e65d21b5-a48e-44e6-9ba1-13de08720aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625452634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2625452634
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.889685515
Short name T927
Test name
Test status
Simulation time 20075538 ps
CPU time 0.82 seconds
Started Apr 02 12:31:43 PM PDT 24
Finished Apr 02 12:31:44 PM PDT 24
Peak memory 206188 kb
Host smart-4ab1baba-3f62-450e-9ee7-43dcb7de07b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889685515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.889685515
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2219208673
Short name T947
Test name
Test status
Simulation time 34798126 ps
CPU time 0.83 seconds
Started Apr 02 12:31:35 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 206092 kb
Host smart-fcb62c68-a393-4224-a390-2af5283fe7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219208673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2219208673
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1121220608
Short name T938
Test name
Test status
Simulation time 49550490 ps
CPU time 0.82 seconds
Started Apr 02 12:31:34 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 206168 kb
Host smart-b9c9ad74-6004-4bbf-a582-f2f654dfb5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121220608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1121220608
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.779282026
Short name T862
Test name
Test status
Simulation time 12116124 ps
CPU time 0.9 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:32:05 PM PDT 24
Peak memory 206124 kb
Host smart-6c42e5d9-8d13-41d1-aee0-39a065381f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779282026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.779282026
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4225763910
Short name T896
Test name
Test status
Simulation time 27927731 ps
CPU time 0.74 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:45 PM PDT 24
Peak memory 206000 kb
Host smart-dda93722-f24b-47cb-a17c-2c2ed98d184d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225763910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4225763910
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2575165676
Short name T940
Test name
Test status
Simulation time 26847387 ps
CPU time 0.89 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:46 PM PDT 24
Peak memory 206152 kb
Host smart-a34712c4-3a9c-429a-bbbe-6073f5af2659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575165676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2575165676
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3570099590
Short name T840
Test name
Test status
Simulation time 42220400 ps
CPU time 0.82 seconds
Started Apr 02 12:31:34 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 206116 kb
Host smart-a18910fd-c02e-4c74-a0bc-5fcafcf4ea15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570099590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3570099590
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1207375041
Short name T895
Test name
Test status
Simulation time 12798849 ps
CPU time 0.85 seconds
Started Apr 02 12:31:39 PM PDT 24
Finished Apr 02 12:31:45 PM PDT 24
Peak memory 206212 kb
Host smart-fb836a74-75d5-47e1-9146-c9f7515621f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207375041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1207375041
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2834523318
Short name T845
Test name
Test status
Simulation time 21669546 ps
CPU time 0.83 seconds
Started Apr 02 12:32:01 PM PDT 24
Finished Apr 02 12:32:02 PM PDT 24
Peak memory 206208 kb
Host smart-5f0f5760-8307-4f87-87f9-a26b8d038afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834523318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2834523318
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1045670083
Short name T951
Test name
Test status
Simulation time 132354762 ps
CPU time 0.86 seconds
Started Apr 02 12:31:55 PM PDT 24
Finished Apr 02 12:31:56 PM PDT 24
Peak memory 206188 kb
Host smart-a04e84d6-7375-4014-b0b6-edd16704ed85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045670083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1045670083
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3823420365
Short name T217
Test name
Test status
Simulation time 33848999 ps
CPU time 1.22 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 206252 kb
Host smart-4833c40d-517d-4351-9baa-972c2be0ec31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823420365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3823420365
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2695204777
Short name T219
Test name
Test status
Simulation time 261695565 ps
CPU time 5.9 seconds
Started Apr 02 12:32:54 PM PDT 24
Finished Apr 02 12:33:00 PM PDT 24
Peak memory 206132 kb
Host smart-29adc635-caf9-4a44-9f7c-6ed156260370
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695204777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2695204777
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3332401356
Short name T214
Test name
Test status
Simulation time 43970138 ps
CPU time 0.85 seconds
Started Apr 02 12:31:35 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 206152 kb
Host smart-071b1f7c-ada9-4db9-befe-555058fbfe90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332401356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3332401356
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3768767426
Short name T925
Test name
Test status
Simulation time 48714157 ps
CPU time 1.17 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:46 PM PDT 24
Peak memory 214592 kb
Host smart-a876532c-7728-4b31-aae9-9818f8d65c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768767426 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3768767426
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2755678426
Short name T889
Test name
Test status
Simulation time 16975118 ps
CPU time 0.78 seconds
Started Apr 02 12:32:56 PM PDT 24
Finished Apr 02 12:32:57 PM PDT 24
Peak memory 205952 kb
Host smart-a058c82c-cab0-43c6-8f63-703f98cf3e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755678426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2755678426
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2523794158
Short name T949
Test name
Test status
Simulation time 19802010 ps
CPU time 0.78 seconds
Started Apr 02 12:32:38 PM PDT 24
Finished Apr 02 12:32:39 PM PDT 24
Peak memory 206076 kb
Host smart-8cf58d74-9c5e-4978-8070-6080deef65a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523794158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2523794158
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2861763752
Short name T910
Test name
Test status
Simulation time 19793565 ps
CPU time 1.08 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:49 PM PDT 24
Peak memory 206348 kb
Host smart-c324f2e3-3f3d-4684-a15c-364ba07904ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861763752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2861763752
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3267564241
Short name T868
Test name
Test status
Simulation time 54758280 ps
CPU time 2.5 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 214636 kb
Host smart-f6135ff1-5f5a-40c3-b7b2-f1b5aed2184e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267564241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3267564241
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3738034497
Short name T251
Test name
Test status
Simulation time 58347355 ps
CPU time 1.7 seconds
Started Apr 02 12:32:55 PM PDT 24
Finished Apr 02 12:32:57 PM PDT 24
Peak memory 206304 kb
Host smart-72fadc27-fcf5-420c-889f-dfdcc137b66b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738034497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3738034497
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1649567576
Short name T859
Test name
Test status
Simulation time 14178041 ps
CPU time 0.94 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:32:05 PM PDT 24
Peak memory 206180 kb
Host smart-70c6c84b-2bf4-4d73-9ed6-9361a0903101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649567576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1649567576
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3559553491
Short name T932
Test name
Test status
Simulation time 13090339 ps
CPU time 0.81 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:32:06 PM PDT 24
Peak memory 206220 kb
Host smart-fe7c99d9-2eb0-4afb-89e1-04ed7ae3dbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559553491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3559553491
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2614814205
Short name T950
Test name
Test status
Simulation time 14538327 ps
CPU time 0.9 seconds
Started Apr 02 12:31:56 PM PDT 24
Finished Apr 02 12:31:57 PM PDT 24
Peak memory 206164 kb
Host smart-1c9258dc-c540-4a1d-856b-cef4a2f66cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614814205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2614814205
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1476989268
Short name T936
Test name
Test status
Simulation time 16024707 ps
CPU time 0.81 seconds
Started Apr 02 12:31:54 PM PDT 24
Finished Apr 02 12:31:55 PM PDT 24
Peak memory 206208 kb
Host smart-86756c12-f9a2-40d7-b6a2-0fb916588365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476989268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1476989268
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2265282578
Short name T875
Test name
Test status
Simulation time 149368755 ps
CPU time 0.94 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 206184 kb
Host smart-d826b093-9ff4-4454-b78a-899f25bbbe57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265282578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2265282578
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3667886288
Short name T964
Test name
Test status
Simulation time 32878702 ps
CPU time 0.79 seconds
Started Apr 02 12:31:50 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 205976 kb
Host smart-0b71a6d6-464d-44a7-8995-6aad63bd5b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667886288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3667886288
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3456475488
Short name T839
Test name
Test status
Simulation time 28222600 ps
CPU time 0.77 seconds
Started Apr 02 12:32:09 PM PDT 24
Finished Apr 02 12:32:11 PM PDT 24
Peak memory 206072 kb
Host smart-d97e84ad-e261-42a0-a06d-34c8117dcd6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456475488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3456475488
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.778032766
Short name T923
Test name
Test status
Simulation time 16284731 ps
CPU time 0.79 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 205936 kb
Host smart-fa806e94-ca14-496c-8c2f-2854759a38f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778032766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.778032766
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3714498075
Short name T930
Test name
Test status
Simulation time 69813124 ps
CPU time 0.8 seconds
Started Apr 02 12:31:54 PM PDT 24
Finished Apr 02 12:31:55 PM PDT 24
Peak memory 205988 kb
Host smart-dbb5abb7-d33c-498c-b59f-8c8381ed92fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714498075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3714498075
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1720976892
Short name T880
Test name
Test status
Simulation time 22878910 ps
CPU time 0.76 seconds
Started Apr 02 12:31:56 PM PDT 24
Finished Apr 02 12:31:57 PM PDT 24
Peak memory 206028 kb
Host smart-8e8185e1-c578-46a6-83d3-c7e365becd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720976892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1720976892
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4083568560
Short name T897
Test name
Test status
Simulation time 20445841 ps
CPU time 1.25 seconds
Started Apr 02 12:32:52 PM PDT 24
Finished Apr 02 12:32:53 PM PDT 24
Peak memory 206232 kb
Host smart-95100eee-1048-44ab-be53-6d94e3f189f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083568560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4083568560
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.779189181
Short name T211
Test name
Test status
Simulation time 61023450 ps
CPU time 3.08 seconds
Started Apr 02 12:32:55 PM PDT 24
Finished Apr 02 12:32:59 PM PDT 24
Peak memory 206176 kb
Host smart-91414e5d-0b84-4e2f-b270-28f2f7ea1a33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779189181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.779189181
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2704738738
Short name T920
Test name
Test status
Simulation time 35283158 ps
CPU time 0.84 seconds
Started Apr 02 12:31:34 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 206212 kb
Host smart-aa473bff-4992-47fa-8b7b-1dc47ae150a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704738738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2704738738
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3278929151
Short name T882
Test name
Test status
Simulation time 23511090 ps
CPU time 1.15 seconds
Started Apr 02 12:32:59 PM PDT 24
Finished Apr 02 12:33:00 PM PDT 24
Peak memory 214516 kb
Host smart-02e5f482-a793-4547-acee-7ddb5c50d14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278929151 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3278929151
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.558151786
Short name T218
Test name
Test status
Simulation time 19342604 ps
CPU time 0.82 seconds
Started Apr 02 12:31:37 PM PDT 24
Finished Apr 02 12:31:39 PM PDT 24
Peak memory 206148 kb
Host smart-c24ccdcc-f789-4029-a90a-dc41efbd2bfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558151786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.558151786
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3114316716
Short name T841
Test name
Test status
Simulation time 16625030 ps
CPU time 0.92 seconds
Started Apr 02 12:31:54 PM PDT 24
Finished Apr 02 12:31:55 PM PDT 24
Peak memory 206208 kb
Host smart-d0012517-d202-4f9e-b0d5-9f7f9ab9e749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114316716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3114316716
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2076589549
Short name T208
Test name
Test status
Simulation time 16203642 ps
CPU time 1.06 seconds
Started Apr 02 12:31:50 PM PDT 24
Finished Apr 02 12:31:52 PM PDT 24
Peak memory 206424 kb
Host smart-ff5576c4-a8c8-4f25-95d4-ff096cb3874c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076589549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2076589549
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1671841616
Short name T939
Test name
Test status
Simulation time 423373676 ps
CPU time 4.06 seconds
Started Apr 02 12:32:58 PM PDT 24
Finished Apr 02 12:33:02 PM PDT 24
Peak memory 218020 kb
Host smart-8f7abfae-f5de-4f58-9928-89ce8a11844a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671841616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1671841616
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4090797382
Short name T236
Test name
Test status
Simulation time 86429181 ps
CPU time 2.28 seconds
Started Apr 02 12:32:53 PM PDT 24
Finished Apr 02 12:32:56 PM PDT 24
Peak memory 206268 kb
Host smart-5d6199ca-9289-46d8-9997-8ca4cab4ef94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090797382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.4090797382
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1206935221
Short name T919
Test name
Test status
Simulation time 26424098 ps
CPU time 0.84 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:32:05 PM PDT 24
Peak memory 206188 kb
Host smart-5186898c-9432-4852-a326-65049eb4413b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206935221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1206935221
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3891849785
Short name T942
Test name
Test status
Simulation time 19537191 ps
CPU time 0.87 seconds
Started Apr 02 12:31:32 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 206104 kb
Host smart-58c873ef-7862-422e-8825-11c1fb679c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891849785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3891849785
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1732870680
Short name T898
Test name
Test status
Simulation time 12477712 ps
CPU time 0.96 seconds
Started Apr 02 12:32:03 PM PDT 24
Finished Apr 02 12:32:05 PM PDT 24
Peak memory 206256 kb
Host smart-d03d352f-1520-4a9e-beae-ebb6c8d52987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732870680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1732870680
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.992138174
Short name T856
Test name
Test status
Simulation time 19392933 ps
CPU time 0.87 seconds
Started Apr 02 12:31:50 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 206144 kb
Host smart-556325b9-4b86-4a44-809d-106823c21b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992138174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.992138174
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.944700508
Short name T865
Test name
Test status
Simulation time 43537765 ps
CPU time 0.8 seconds
Started Apr 02 12:32:08 PM PDT 24
Finished Apr 02 12:32:09 PM PDT 24
Peak memory 206208 kb
Host smart-2d97b793-c673-4f21-b597-3e4597825cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944700508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.944700508
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.325251037
Short name T962
Test name
Test status
Simulation time 22504883 ps
CPU time 0.84 seconds
Started Apr 02 12:32:02 PM PDT 24
Finished Apr 02 12:32:03 PM PDT 24
Peak memory 206172 kb
Host smart-2e9cbc19-dc47-4786-b532-6f7f057d8748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325251037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.325251037
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1481059109
Short name T847
Test name
Test status
Simulation time 17464213 ps
CPU time 0.87 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:32:06 PM PDT 24
Peak memory 206236 kb
Host smart-f50e0316-01c7-45b1-8020-09ccaa0c5021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481059109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1481059109
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2371830874
Short name T965
Test name
Test status
Simulation time 13328241 ps
CPU time 0.89 seconds
Started Apr 02 12:32:00 PM PDT 24
Finished Apr 02 12:32:01 PM PDT 24
Peak memory 206236 kb
Host smart-313b04dc-290f-4087-9549-f25854a6ed11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371830874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2371830874
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2911646512
Short name T928
Test name
Test status
Simulation time 42297643 ps
CPU time 0.82 seconds
Started Apr 02 12:32:13 PM PDT 24
Finished Apr 02 12:32:14 PM PDT 24
Peak memory 206188 kb
Host smart-a92d7ede-685b-43e3-b09f-fe013e5b0a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911646512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2911646512
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.488504631
Short name T879
Test name
Test status
Simulation time 14469141 ps
CPU time 0.82 seconds
Started Apr 02 12:31:56 PM PDT 24
Finished Apr 02 12:31:57 PM PDT 24
Peak memory 206248 kb
Host smart-260b99ed-caee-445c-b360-9e8befc13b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488504631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.488504631
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.521915667
Short name T848
Test name
Test status
Simulation time 44351618 ps
CPU time 1.13 seconds
Started Apr 02 12:32:51 PM PDT 24
Finished Apr 02 12:32:52 PM PDT 24
Peak memory 214508 kb
Host smart-5821d777-9df5-4214-98e5-16777c3aee9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521915667 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.521915667
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.821549958
Short name T955
Test name
Test status
Simulation time 60102463 ps
CPU time 0.84 seconds
Started Apr 02 12:32:38 PM PDT 24
Finished Apr 02 12:32:39 PM PDT 24
Peak memory 206096 kb
Host smart-8da73050-bce8-4149-9dc2-02bda6bded59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821549958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.821549958
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1185713161
Short name T207
Test name
Test status
Simulation time 29926728 ps
CPU time 1.18 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:40 PM PDT 24
Peak memory 206348 kb
Host smart-631566c5-61b5-4649-9c60-f51930730f96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185713161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1185713161
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4205125668
Short name T891
Test name
Test status
Simulation time 38217403 ps
CPU time 2.38 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:32:27 PM PDT 24
Peak memory 213700 kb
Host smart-75db5659-410e-48d6-a3a1-6d7755da9583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205125668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4205125668
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.809283318
Short name T935
Test name
Test status
Simulation time 228544544 ps
CPU time 3.01 seconds
Started Apr 02 12:32:55 PM PDT 24
Finished Apr 02 12:32:59 PM PDT 24
Peak memory 206320 kb
Host smart-040545c9-1c3a-4079-a2ef-97d36424f19d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809283318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.809283318
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.756006900
Short name T878
Test name
Test status
Simulation time 47657044 ps
CPU time 1.44 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 214560 kb
Host smart-f17c44fd-5d6c-4605-b32c-0b96a947db70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756006900 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.756006900
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3028636069
Short name T887
Test name
Test status
Simulation time 161306827 ps
CPU time 0.88 seconds
Started Apr 02 12:32:48 PM PDT 24
Finished Apr 02 12:32:49 PM PDT 24
Peak memory 206132 kb
Host smart-c52cbfe7-9355-48cb-bb47-e0b360ee5735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028636069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3028636069
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2377961165
Short name T844
Test name
Test status
Simulation time 25528812 ps
CPU time 0.88 seconds
Started Apr 02 12:32:24 PM PDT 24
Finished Apr 02 12:32:30 PM PDT 24
Peak memory 205268 kb
Host smart-2db1457b-182e-4cfd-818f-63911e2980a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377961165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2377961165
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4170943525
Short name T876
Test name
Test status
Simulation time 251893074 ps
CPU time 1.31 seconds
Started Apr 02 12:32:38 PM PDT 24
Finished Apr 02 12:32:39 PM PDT 24
Peak memory 206272 kb
Host smart-c356dc92-8a3d-4cb4-a47a-b890730c2452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170943525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4170943525
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1324568809
Short name T869
Test name
Test status
Simulation time 86946568 ps
CPU time 2.72 seconds
Started Apr 02 12:32:39 PM PDT 24
Finished Apr 02 12:32:41 PM PDT 24
Peak memory 214620 kb
Host smart-4e3c7f9a-fc5b-479e-8c85-23c7e16a8fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324568809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1324568809
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1854768957
Short name T906
Test name
Test status
Simulation time 70275268 ps
CPU time 1.9 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 206336 kb
Host smart-6b9c5090-17d3-41ad-a4ba-14f05eb56a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854768957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1854768957
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.980204156
Short name T917
Test name
Test status
Simulation time 51989658 ps
CPU time 1.22 seconds
Started Apr 02 12:31:45 PM PDT 24
Finished Apr 02 12:31:47 PM PDT 24
Peak memory 216532 kb
Host smart-97977624-8952-4fde-9a9a-1d458ba97f29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980204156 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.980204156
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.100545654
Short name T922
Test name
Test status
Simulation time 23933235 ps
CPU time 0.88 seconds
Started Apr 02 12:32:52 PM PDT 24
Finished Apr 02 12:32:53 PM PDT 24
Peak memory 206132 kb
Host smart-e0109e2b-a67a-4685-b80c-22e8116c56b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100545654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.100545654
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.458776473
Short name T894
Test name
Test status
Simulation time 46800308 ps
CPU time 0.84 seconds
Started Apr 02 12:32:52 PM PDT 24
Finished Apr 02 12:32:53 PM PDT 24
Peak memory 206132 kb
Host smart-32b248c4-30cc-4489-8e06-56fc2dc12aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458776473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.458776473
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1582856596
Short name T958
Test name
Test status
Simulation time 22627561 ps
CPU time 1.18 seconds
Started Apr 02 12:32:23 PM PDT 24
Finished Apr 02 12:32:25 PM PDT 24
Peak memory 205396 kb
Host smart-27bc892d-cd11-4c2a-a7f1-811a8fca993b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582856596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1582856596
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1737393120
Short name T871
Test name
Test status
Simulation time 64080792 ps
CPU time 1.84 seconds
Started Apr 02 12:32:49 PM PDT 24
Finished Apr 02 12:32:52 PM PDT 24
Peak memory 222700 kb
Host smart-8965151d-f03c-4aa7-8409-b7c78bfa9c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737393120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1737393120
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2691352780
Short name T248
Test name
Test status
Simulation time 379697547 ps
CPU time 2.3 seconds
Started Apr 02 12:32:50 PM PDT 24
Finished Apr 02 12:32:53 PM PDT 24
Peak memory 206308 kb
Host smart-dbc3e3de-3d10-4be4-829e-1e834e5a8517
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691352780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2691352780
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1964015397
Short name T945
Test name
Test status
Simulation time 340159514 ps
CPU time 1.32 seconds
Started Apr 02 12:31:32 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 214616 kb
Host smart-28d059c0-04cc-4858-81ff-47118c1136f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964015397 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1964015397
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.733986701
Short name T234
Test name
Test status
Simulation time 20327815 ps
CPU time 0.82 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206184 kb
Host smart-792b54a0-a011-40e2-a1d3-cef53625b7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733986701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.733986701
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1727145509
Short name T909
Test name
Test status
Simulation time 28860376 ps
CPU time 0.75 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 206200 kb
Host smart-35997055-792e-43a4-9b3d-c06fd17dc3e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727145509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1727145509
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2603302881
Short name T941
Test name
Test status
Simulation time 65452473 ps
CPU time 1 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 206304 kb
Host smart-73c9a7a6-d64a-4c64-8928-c2eb836a1615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603302881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2603302881
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1466148934
Short name T966
Test name
Test status
Simulation time 152402253 ps
CPU time 4.58 seconds
Started Apr 02 12:31:58 PM PDT 24
Finished Apr 02 12:32:03 PM PDT 24
Peak memory 217992 kb
Host smart-5db982ea-2f66-4333-8deb-38369b1a0145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466148934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1466148934
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1683932753
Short name T237
Test name
Test status
Simulation time 760205173 ps
CPU time 1.93 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 206304 kb
Host smart-35cbb61a-06bb-4b6f-a33a-ac4b69835697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683932753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1683932753
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1352547552
Short name T907
Test name
Test status
Simulation time 81558876 ps
CPU time 1.17 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 214552 kb
Host smart-97ed9010-abc1-4af6-9103-a165fee24de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352547552 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1352547552
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2781523151
Short name T903
Test name
Test status
Simulation time 56840121 ps
CPU time 0.87 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 206176 kb
Host smart-8fa831f8-4155-47ab-b747-94d732acb226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781523151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2781523151
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1281774307
Short name T926
Test name
Test status
Simulation time 37778579 ps
CPU time 0.8 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 206036 kb
Host smart-7a97dc44-46d0-4067-8280-e210c7f83902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281774307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1281774307
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2364309646
Short name T223
Test name
Test status
Simulation time 43400771 ps
CPU time 1.05 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 206264 kb
Host smart-dcd90f1c-d9c5-4481-9ee8-aa2eb4bbcc4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364309646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2364309646
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.92191336
Short name T858
Test name
Test status
Simulation time 90599189 ps
CPU time 3.32 seconds
Started Apr 02 12:32:04 PM PDT 24
Finished Apr 02 12:32:07 PM PDT 24
Peak memory 214584 kb
Host smart-0633b581-f647-41d4-bf7f-d5d133e41b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92191336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.92191336
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3194729569
Short name T235
Test name
Test status
Simulation time 138838525 ps
CPU time 1.47 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 206356 kb
Host smart-aa4d43bb-644a-4066-a343-f6d41be581d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194729569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3194729569
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.1923313728
Short name T657
Test name
Test status
Simulation time 39450606 ps
CPU time 0.87 seconds
Started Apr 02 01:34:20 PM PDT 24
Finished Apr 02 01:34:22 PM PDT 24
Peak memory 206652 kb
Host smart-954e0646-13f3-4754-a5e1-cb54475fd6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923313728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1923313728
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1975025192
Short name T29
Test name
Test status
Simulation time 11281010 ps
CPU time 0.85 seconds
Started Apr 02 01:34:22 PM PDT 24
Finished Apr 02 01:34:26 PM PDT 24
Peak memory 215412 kb
Host smart-cdd7f81d-2ab9-4e1b-a447-db2b94a455a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975025192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1975025192
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3668298410
Short name T359
Test name
Test status
Simulation time 345537717 ps
CPU time 1.14 seconds
Started Apr 02 01:34:20 PM PDT 24
Finished Apr 02 01:34:22 PM PDT 24
Peak memory 217796 kb
Host smart-50c3b6f9-b221-4d45-877e-183bfc95d98d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668298410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3668298410
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.173558762
Short name T622
Test name
Test status
Simulation time 189919585 ps
CPU time 2.64 seconds
Started Apr 02 01:34:16 PM PDT 24
Finished Apr 02 01:34:19 PM PDT 24
Peak memory 217964 kb
Host smart-aec0f0d5-afdb-467c-bec7-212b21602d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173558762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.173558762
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1869168644
Short name T647
Test name
Test status
Simulation time 27855363 ps
CPU time 0.9 seconds
Started Apr 02 01:34:18 PM PDT 24
Finished Apr 02 01:34:19 PM PDT 24
Peak memory 215360 kb
Host smart-4dfdd418-27f3-4cde-a8e1-849bc843fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869168644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1869168644
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4056866503
Short name T45
Test name
Test status
Simulation time 188757459 ps
CPU time 3.75 seconds
Started Apr 02 01:34:23 PM PDT 24
Finished Apr 02 01:34:29 PM PDT 24
Peak memory 235924 kb
Host smart-57bf6120-6320-4104-8780-c15c45ce1799
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056866503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4056866503
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2445103219
Short name T482
Test name
Test status
Simulation time 33855109 ps
CPU time 0.88 seconds
Started Apr 02 01:34:18 PM PDT 24
Finished Apr 02 01:34:19 PM PDT 24
Peak memory 215220 kb
Host smart-0e1bc72a-1adb-436c-b325-cbe960e39ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445103219 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2445103219
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4283035658
Short name T196
Test name
Test status
Simulation time 153350352 ps
CPU time 3.33 seconds
Started Apr 02 01:34:18 PM PDT 24
Finished Apr 02 01:34:22 PM PDT 24
Peak memory 217684 kb
Host smart-41b0a7ae-80ff-4917-ab96-f4349539a4e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283035658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4283035658
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1411332351
Short name T486
Test name
Test status
Simulation time 54848510267 ps
CPU time 1257 seconds
Started Apr 02 01:34:16 PM PDT 24
Finished Apr 02 01:55:14 PM PDT 24
Peak memory 221208 kb
Host smart-b721f617-d4fa-40ec-943b-7e438e5a9e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411332351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1411332351
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2061810668
Short name T515
Test name
Test status
Simulation time 24691603 ps
CPU time 1.09 seconds
Started Apr 02 01:34:24 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 205908 kb
Host smart-d61b6af2-6f20-4cde-8623-5bf1c9edb2a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061810668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2061810668
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1832556245
Short name T397
Test name
Test status
Simulation time 30961677 ps
CPU time 1.18 seconds
Started Apr 02 01:34:24 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 217956 kb
Host smart-dcb0dc5b-c493-4b8b-9571-44f195db2949
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832556245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1832556245
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.921355858
Short name T541
Test name
Test status
Simulation time 63135801 ps
CPU time 1.77 seconds
Started Apr 02 01:34:26 PM PDT 24
Finished Apr 02 01:34:28 PM PDT 24
Peak memory 217784 kb
Host smart-b1b4638c-5532-4d87-85e5-7189c588967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921355858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.921355858
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3437463961
Short name T769
Test name
Test status
Simulation time 21658687 ps
CPU time 1.15 seconds
Started Apr 02 01:34:25 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 224064 kb
Host smart-325424f0-bffc-4ebf-b86b-f1577ab382c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437463961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3437463961
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.587599571
Short name T127
Test name
Test status
Simulation time 28075372 ps
CPU time 0.92 seconds
Started Apr 02 01:34:26 PM PDT 24
Finished Apr 02 01:34:27 PM PDT 24
Peak memory 207068 kb
Host smart-95560054-c1c8-4ec5-b006-394444d154c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587599571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.587599571
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.769425429
Short name T16
Test name
Test status
Simulation time 712400576 ps
CPU time 3.66 seconds
Started Apr 02 01:34:25 PM PDT 24
Finished Apr 02 01:34:29 PM PDT 24
Peak memory 235384 kb
Host smart-be00eecc-8290-4845-a939-73afda091830
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769425429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.769425429
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1029212060
Short name T427
Test name
Test status
Simulation time 32455216 ps
CPU time 0.9 seconds
Started Apr 02 01:34:24 PM PDT 24
Finished Apr 02 01:34:26 PM PDT 24
Peak memory 215092 kb
Host smart-3d6285fb-3b07-402e-96f1-b8a24210fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029212060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1029212060
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.621543347
Short name T188
Test name
Test status
Simulation time 119631123565 ps
CPU time 1964.18 seconds
Started Apr 02 01:34:24 PM PDT 24
Finished Apr 02 02:07:10 PM PDT 24
Peak memory 226704 kb
Host smart-9e2a2f5c-6f86-4e36-bee4-573018bf73b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621543347 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.621543347
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2346922741
Short name T538
Test name
Test status
Simulation time 26123533 ps
CPU time 0.92 seconds
Started Apr 02 01:35:23 PM PDT 24
Finished Apr 02 01:35:24 PM PDT 24
Peak memory 205932 kb
Host smart-af51fdb5-e164-4dad-8dbe-c3346e92a230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346922741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2346922741
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.564175411
Short name T426
Test name
Test status
Simulation time 59845731 ps
CPU time 0.85 seconds
Started Apr 02 01:35:21 PM PDT 24
Finished Apr 02 01:35:22 PM PDT 24
Peak memory 207200 kb
Host smart-77f5168a-9776-469b-bd4e-91511a784835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564175411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.564175411
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.397364827
Short name T144
Test name
Test status
Simulation time 18938930 ps
CPU time 1.06 seconds
Started Apr 02 01:35:21 PM PDT 24
Finished Apr 02 01:35:22 PM PDT 24
Peak memory 218152 kb
Host smart-f5f671ee-c680-445a-8083-60f6e4581e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397364827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.397364827
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_smoke.4127305251
Short name T618
Test name
Test status
Simulation time 41394837 ps
CPU time 0.97 seconds
Started Apr 02 01:35:17 PM PDT 24
Finished Apr 02 01:35:18 PM PDT 24
Peak memory 215284 kb
Host smart-ea5a7c95-c79e-4fe7-8c6e-afd6f8b97afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127305251 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.4127305251
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2806012911
Short name T724
Test name
Test status
Simulation time 274289913 ps
CPU time 4.93 seconds
Started Apr 02 01:35:18 PM PDT 24
Finished Apr 02 01:35:25 PM PDT 24
Peak memory 216480 kb
Host smart-482bd636-8754-44cf-9220-24f15c9b2682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806012911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2806012911
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1934612893
Short name T805
Test name
Test status
Simulation time 99245529470 ps
CPU time 482.23 seconds
Started Apr 02 01:35:16 PM PDT 24
Finished Apr 02 01:43:18 PM PDT 24
Peak memory 218316 kb
Host smart-046a6f75-8f5a-4ae9-a2b8-813a96c5a0a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934612893 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1934612893
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3328850318
Short name T593
Test name
Test status
Simulation time 40808985 ps
CPU time 1.5 seconds
Started Apr 02 01:38:03 PM PDT 24
Finished Apr 02 01:38:04 PM PDT 24
Peak memory 218016 kb
Host smart-38bda2c7-2a40-4fc1-9bea-049964c6f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328850318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3328850318
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1779719416
Short name T795
Test name
Test status
Simulation time 46673373 ps
CPU time 1.34 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:06 PM PDT 24
Peak memory 217840 kb
Host smart-460ca383-7b5c-4635-8b92-5cb7d10df2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779719416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1779719416
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2873136514
Short name T518
Test name
Test status
Simulation time 29306134 ps
CPU time 1.31 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:06 PM PDT 24
Peak memory 216808 kb
Host smart-5d64ad8e-6f85-4713-af6a-2f91a120d51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873136514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2873136514
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1277063406
Short name T505
Test name
Test status
Simulation time 44581675 ps
CPU time 1.11 seconds
Started Apr 02 01:38:02 PM PDT 24
Finished Apr 02 01:38:03 PM PDT 24
Peak memory 217836 kb
Host smart-40a2f3ef-796f-45a0-9dfb-26b5c4f3c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277063406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1277063406
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1960243961
Short name T439
Test name
Test status
Simulation time 37058685 ps
CPU time 1.3 seconds
Started Apr 02 01:38:01 PM PDT 24
Finished Apr 02 01:38:02 PM PDT 24
Peak memory 217752 kb
Host smart-6d556457-4dc0-4953-adb0-ead9053f7221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960243961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1960243961
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2131788867
Short name T571
Test name
Test status
Simulation time 39714060 ps
CPU time 1.17 seconds
Started Apr 02 01:38:10 PM PDT 24
Finished Apr 02 01:38:12 PM PDT 24
Peak memory 217944 kb
Host smart-617c0613-b771-469b-91da-f4ce756ecf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131788867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2131788867
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2326228382
Short name T473
Test name
Test status
Simulation time 67287934 ps
CPU time 1.17 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:05 PM PDT 24
Peak memory 216692 kb
Host smart-cee15166-31e9-4698-b37e-c6f545e123a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326228382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2326228382
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1666565039
Short name T317
Test name
Test status
Simulation time 42856750 ps
CPU time 1.43 seconds
Started Apr 02 01:38:05 PM PDT 24
Finished Apr 02 01:38:07 PM PDT 24
Peak memory 217820 kb
Host smart-dcd26100-8522-4c31-9457-e1f472816a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666565039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1666565039
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2200710202
Short name T266
Test name
Test status
Simulation time 57045007 ps
CPU time 1.23 seconds
Started Apr 02 01:35:26 PM PDT 24
Finished Apr 02 01:35:27 PM PDT 24
Peak memory 215636 kb
Host smart-250170fb-0d16-42b0-99f1-53c265e4494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200710202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2200710202
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2510808952
Short name T516
Test name
Test status
Simulation time 40209846 ps
CPU time 0.84 seconds
Started Apr 02 01:35:26 PM PDT 24
Finished Apr 02 01:35:27 PM PDT 24
Peak memory 205652 kb
Host smart-42d5e36f-09c2-41c1-a1d5-fceb0eb34578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510808952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2510808952
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2436931910
Short name T104
Test name
Test status
Simulation time 16613895 ps
CPU time 0.82 seconds
Started Apr 02 01:35:24 PM PDT 24
Finished Apr 02 01:35:25 PM PDT 24
Peak memory 215792 kb
Host smart-c701b2ec-e545-448f-9fa3-312ad216d56d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436931910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2436931910
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3508813450
Short name T732
Test name
Test status
Simulation time 28570659 ps
CPU time 1 seconds
Started Apr 02 01:35:25 PM PDT 24
Finished Apr 02 01:35:26 PM PDT 24
Peak memory 229756 kb
Host smart-962196e9-1e3a-4559-9a43-a97dc856bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508813450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3508813450
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1431924099
Short name T710
Test name
Test status
Simulation time 232104011 ps
CPU time 3.11 seconds
Started Apr 02 01:35:23 PM PDT 24
Finished Apr 02 01:35:27 PM PDT 24
Peak memory 216636 kb
Host smart-39ca71bc-7f86-4d2e-a115-89f0db8f8a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431924099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1431924099
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3399263554
Short name T358
Test name
Test status
Simulation time 108466145 ps
CPU time 0.88 seconds
Started Apr 02 01:35:25 PM PDT 24
Finished Apr 02 01:35:26 PM PDT 24
Peak memory 215324 kb
Host smart-e01c93f5-b617-4b4b-82e3-13ca3bb72f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399263554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3399263554
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.570570060
Short name T334
Test name
Test status
Simulation time 18661618 ps
CPU time 0.98 seconds
Started Apr 02 01:35:23 PM PDT 24
Finished Apr 02 01:35:25 PM PDT 24
Peak memory 215240 kb
Host smart-60e291ce-e021-48eb-891e-d28ab2767e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570570060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.570570060
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2832913932
Short name T198
Test name
Test status
Simulation time 203815334 ps
CPU time 2.53 seconds
Started Apr 02 01:35:25 PM PDT 24
Finished Apr 02 01:35:28 PM PDT 24
Peak memory 215140 kb
Host smart-5bb3181d-a62a-4ce2-8157-607ef17d9c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832913932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2832913932
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3155868328
Short name T185
Test name
Test status
Simulation time 415293119216 ps
CPU time 1470.62 seconds
Started Apr 02 01:35:24 PM PDT 24
Finished Apr 02 01:59:55 PM PDT 24
Peak memory 223968 kb
Host smart-23d1839e-dea1-44d7-8ffe-906c2679f0ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155868328 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3155868328
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.990608220
Short name T685
Test name
Test status
Simulation time 67542256 ps
CPU time 2 seconds
Started Apr 02 01:38:05 PM PDT 24
Finished Apr 02 01:38:07 PM PDT 24
Peak memory 218088 kb
Host smart-7e1d2baf-5bb7-4458-9c3d-33542b3d473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990608220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.990608220
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3077335296
Short name T303
Test name
Test status
Simulation time 49057937 ps
CPU time 1.8 seconds
Started Apr 02 01:38:06 PM PDT 24
Finished Apr 02 01:38:08 PM PDT 24
Peak memory 216636 kb
Host smart-7a76e03a-3a7b-4a6c-8129-4541203c1a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077335296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3077335296
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2542971903
Short name T491
Test name
Test status
Simulation time 45198844 ps
CPU time 1.39 seconds
Started Apr 02 01:38:05 PM PDT 24
Finished Apr 02 01:38:06 PM PDT 24
Peak memory 217640 kb
Host smart-a1c8b2d2-f08f-4e11-a4fd-b714fa0aedfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542971903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2542971903
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1918951415
Short name T819
Test name
Test status
Simulation time 71869107 ps
CPU time 1.15 seconds
Started Apr 02 01:38:06 PM PDT 24
Finished Apr 02 01:38:07 PM PDT 24
Peak memory 218976 kb
Host smart-b6454764-83c9-42d7-930a-123cdfd806b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918951415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1918951415
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2715064680
Short name T281
Test name
Test status
Simulation time 55758571 ps
CPU time 1.26 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:05 PM PDT 24
Peak memory 216632 kb
Host smart-14f3b5ad-d082-41c5-9d05-500ec32b9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715064680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2715064680
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2179478826
Short name T790
Test name
Test status
Simulation time 40432090 ps
CPU time 1.3 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:05 PM PDT 24
Peak memory 216364 kb
Host smart-e610f0ae-4fa2-4381-adc3-c10d973ad66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179478826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2179478826
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3401131849
Short name T480
Test name
Test status
Simulation time 182827905 ps
CPU time 1.29 seconds
Started Apr 02 01:38:04 PM PDT 24
Finished Apr 02 01:38:05 PM PDT 24
Peak memory 219200 kb
Host smart-520756d6-830b-4c98-bf34-a57de389d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401131849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3401131849
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2331704980
Short name T782
Test name
Test status
Simulation time 63266936 ps
CPU time 1.38 seconds
Started Apr 02 01:38:09 PM PDT 24
Finished Apr 02 01:38:10 PM PDT 24
Peak memory 216608 kb
Host smart-110b9608-3408-4f96-9761-5b92cd94f829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331704980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2331704980
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.240010382
Short name T659
Test name
Test status
Simulation time 42161142 ps
CPU time 1.47 seconds
Started Apr 02 01:38:08 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 217784 kb
Host smart-0313607d-81fe-4ec9-91ba-4faba2c268c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240010382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.240010382
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3204005715
Short name T420
Test name
Test status
Simulation time 64056390 ps
CPU time 1.61 seconds
Started Apr 02 01:38:07 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 218004 kb
Host smart-a651fdd4-76fa-40d3-a33b-d587aa79cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204005715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3204005715
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4006955439
Short name T238
Test name
Test status
Simulation time 269778144 ps
CPU time 1.35 seconds
Started Apr 02 01:35:27 PM PDT 24
Finished Apr 02 01:35:29 PM PDT 24
Peak memory 215560 kb
Host smart-bfd8442a-989a-4df7-b4f4-4d4f6e147e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006955439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4006955439
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3104731275
Short name T750
Test name
Test status
Simulation time 15275895 ps
CPU time 0.9 seconds
Started Apr 02 01:35:34 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 205848 kb
Host smart-4b4b3877-a493-4635-a3d7-f85096c802c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104731275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3104731275
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3284935953
Short name T393
Test name
Test status
Simulation time 15012028 ps
CPU time 0.86 seconds
Started Apr 02 01:35:29 PM PDT 24
Finished Apr 02 01:35:31 PM PDT 24
Peak memory 215576 kb
Host smart-9abe31f1-83db-4f82-a2dd-9c5aeacabfbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284935953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3284935953
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.4001488780
Short name T39
Test name
Test status
Simulation time 20892965 ps
CPU time 1.2 seconds
Started Apr 02 01:35:29 PM PDT 24
Finished Apr 02 01:35:30 PM PDT 24
Peak memory 229696 kb
Host smart-928f2115-a791-4a0d-abda-9bca6e880ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001488780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.4001488780
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.266110548
Short name T572
Test name
Test status
Simulation time 46113840 ps
CPU time 1.32 seconds
Started Apr 02 01:35:27 PM PDT 24
Finished Apr 02 01:35:29 PM PDT 24
Peak memory 217908 kb
Host smart-23391f05-31b8-49de-9857-c34624799470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266110548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.266110548
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.916385220
Short name T435
Test name
Test status
Simulation time 25263927 ps
CPU time 1.32 seconds
Started Apr 02 01:35:30 PM PDT 24
Finished Apr 02 01:35:32 PM PDT 24
Peak memory 224048 kb
Host smart-27dec7c9-77c5-467c-bb3a-de6330f88faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916385220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.916385220
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3282181179
Short name T587
Test name
Test status
Simulation time 57448444 ps
CPU time 0.96 seconds
Started Apr 02 01:35:26 PM PDT 24
Finished Apr 02 01:35:27 PM PDT 24
Peak memory 215288 kb
Host smart-147d685e-7ef3-40a3-bc86-79176056b930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282181179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3282181179
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1596241249
Short name T367
Test name
Test status
Simulation time 185488145 ps
CPU time 1.54 seconds
Started Apr 02 01:35:40 PM PDT 24
Finished Apr 02 01:35:42 PM PDT 24
Peak memory 216304 kb
Host smart-7329bd97-c4b3-4574-be44-e5a3eff156e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596241249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1596241249
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_genbits.4008971534
Short name T343
Test name
Test status
Simulation time 98639116 ps
CPU time 1.2 seconds
Started Apr 02 01:38:07 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 217948 kb
Host smart-ab7c81aa-beef-4e4c-bef5-c7339a8e5b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008971534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.4008971534
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.119569742
Short name T277
Test name
Test status
Simulation time 90268948 ps
CPU time 1.22 seconds
Started Apr 02 01:38:09 PM PDT 24
Finished Apr 02 01:38:10 PM PDT 24
Peak memory 217964 kb
Host smart-b7545db6-5dea-4496-a588-c1ff1cde5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119569742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.119569742
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.4293659705
Short name T708
Test name
Test status
Simulation time 67421479 ps
CPU time 1.34 seconds
Started Apr 02 01:38:05 PM PDT 24
Finished Apr 02 01:38:07 PM PDT 24
Peak memory 216784 kb
Host smart-f8530c2a-d5f2-4c2c-8aaf-264f450b6e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293659705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4293659705
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3438447873
Short name T744
Test name
Test status
Simulation time 44484891 ps
CPU time 1.51 seconds
Started Apr 02 01:38:09 PM PDT 24
Finished Apr 02 01:38:11 PM PDT 24
Peak memory 215292 kb
Host smart-c7d8816e-1777-45b0-bac0-7e404eca3948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438447873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3438447873
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1585545610
Short name T447
Test name
Test status
Simulation time 220510636 ps
CPU time 1.2 seconds
Started Apr 02 01:38:07 PM PDT 24
Finished Apr 02 01:38:08 PM PDT 24
Peak memory 216740 kb
Host smart-2bef8d6c-7b1b-444d-92c1-3ec4d10cba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585545610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1585545610
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.195210194
Short name T802
Test name
Test status
Simulation time 68602311 ps
CPU time 1.39 seconds
Started Apr 02 01:38:06 PM PDT 24
Finished Apr 02 01:38:08 PM PDT 24
Peak memory 217972 kb
Host smart-ec5da7ae-637c-44bf-b572-bde66370ec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195210194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.195210194
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.835529004
Short name T598
Test name
Test status
Simulation time 30701350 ps
CPU time 1.26 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:22 PM PDT 24
Peak memory 216780 kb
Host smart-fe4eb6bb-d9eb-4b4c-ae95-41a1c7c0fc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835529004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.835529004
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1210337348
Short name T364
Test name
Test status
Simulation time 28927198 ps
CPU time 1.27 seconds
Started Apr 02 01:38:09 PM PDT 24
Finished Apr 02 01:38:11 PM PDT 24
Peak memory 218972 kb
Host smart-04cfee58-9076-4220-8781-f08f2d8f0801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210337348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1210337348
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2640895865
Short name T775
Test name
Test status
Simulation time 36374627 ps
CPU time 1.32 seconds
Started Apr 02 01:38:12 PM PDT 24
Finished Apr 02 01:38:14 PM PDT 24
Peak memory 217772 kb
Host smart-15d68cf6-cd16-4fc7-a125-1f52ee721d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640895865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2640895865
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3857584237
Short name T640
Test name
Test status
Simulation time 58619707 ps
CPU time 1.07 seconds
Started Apr 02 01:38:08 PM PDT 24
Finished Apr 02 01:38:10 PM PDT 24
Peak memory 216640 kb
Host smart-49d7ab1e-31b4-4b80-a408-35d3a606d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857584237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3857584237
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_disable.3992065897
Short name T488
Test name
Test status
Simulation time 10907298 ps
CPU time 0.91 seconds
Started Apr 02 01:35:32 PM PDT 24
Finished Apr 02 01:35:36 PM PDT 24
Peak memory 215368 kb
Host smart-3ed273dd-e5d0-46fa-a530-50ad4dd8e0bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992065897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3992065897
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1418128681
Short name T311
Test name
Test status
Simulation time 53888656 ps
CPU time 0.98 seconds
Started Apr 02 01:35:32 PM PDT 24
Finished Apr 02 01:35:36 PM PDT 24
Peak memory 217692 kb
Host smart-78ed1845-9166-4e30-a9c9-1b306f44c162
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418128681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1418128681
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3769769026
Short name T197
Test name
Test status
Simulation time 62002301 ps
CPU time 1.06 seconds
Started Apr 02 01:35:32 PM PDT 24
Finished Apr 02 01:35:36 PM PDT 24
Peak memory 219564 kb
Host smart-d29b1cdd-ebc6-484a-afb9-825a437a9a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769769026 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3769769026
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4215450385
Short name T307
Test name
Test status
Simulation time 47048941 ps
CPU time 1.31 seconds
Started Apr 02 01:35:35 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 218708 kb
Host smart-b6e12409-918d-4584-bf54-7efd572a48be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215450385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4215450385
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.230072206
Short name T762
Test name
Test status
Simulation time 24001116 ps
CPU time 0.93 seconds
Started Apr 02 01:35:32 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 215684 kb
Host smart-66735287-c603-4e76-9d02-35fc2a09f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230072206 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.230072206
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3866425121
Short name T612
Test name
Test status
Simulation time 42596832 ps
CPU time 0.9 seconds
Started Apr 02 01:35:34 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 215116 kb
Host smart-3e68716f-f16e-4c4c-9f58-d37455ee2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866425121 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3866425121
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1399163361
Short name T384
Test name
Test status
Simulation time 122939645 ps
CPU time 2.86 seconds
Started Apr 02 01:35:32 PM PDT 24
Finished Apr 02 01:35:38 PM PDT 24
Peak memory 216468 kb
Host smart-cffb3f28-21ee-4499-81f8-19c0c404adfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399163361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1399163361
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2498848657
Short name T469
Test name
Test status
Simulation time 107442716355 ps
CPU time 746 seconds
Started Apr 02 01:35:33 PM PDT 24
Finished Apr 02 01:48:02 PM PDT 24
Peak memory 221596 kb
Host smart-1bebe534-58ca-439c-9993-42ed80182b4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498848657 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2498848657
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1947006567
Short name T286
Test name
Test status
Simulation time 79175140 ps
CPU time 2.11 seconds
Started Apr 02 01:38:10 PM PDT 24
Finished Apr 02 01:38:13 PM PDT 24
Peak memory 216732 kb
Host smart-af4b43f6-e58a-41b6-bcfb-09a78d6a42e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947006567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1947006567
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1144052982
Short name T624
Test name
Test status
Simulation time 107954230 ps
CPU time 1.51 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 216732 kb
Host smart-cccb7297-7f50-4c6f-93e6-3a1f70430412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144052982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1144052982
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.869768390
Short name T373
Test name
Test status
Simulation time 22052226 ps
CPU time 1.14 seconds
Started Apr 02 01:38:08 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 215180 kb
Host smart-e4c8e44a-bb5f-4e6a-8509-7c403a992ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869768390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.869768390
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.921202856
Short name T52
Test name
Test status
Simulation time 79578802 ps
CPU time 1.75 seconds
Started Apr 02 01:38:08 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 219332 kb
Host smart-85a17229-162d-40a5-af71-f22982cf08b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921202856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.921202856
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2529482901
Short name T559
Test name
Test status
Simulation time 39014958 ps
CPU time 1.17 seconds
Started Apr 02 01:38:11 PM PDT 24
Finished Apr 02 01:38:12 PM PDT 24
Peak memory 216528 kb
Host smart-045fa3d9-b63a-4bc7-b4d5-5ac7c467f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529482901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2529482901
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2474474272
Short name T327
Test name
Test status
Simulation time 32720449 ps
CPU time 1.32 seconds
Started Apr 02 01:38:09 PM PDT 24
Finished Apr 02 01:38:11 PM PDT 24
Peak memory 217856 kb
Host smart-d5fbe7d8-3cd9-4f7c-a89b-ffbe44eb5d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474474272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2474474272
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2459149970
Short name T243
Test name
Test status
Simulation time 49381842 ps
CPU time 1.24 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 216504 kb
Host smart-20eceb19-aaa7-4209-b030-351735e56637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459149970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2459149970
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3693813045
Short name T369
Test name
Test status
Simulation time 73170234 ps
CPU time 1.11 seconds
Started Apr 02 01:38:08 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 217900 kb
Host smart-a17503e6-f400-4cc6-b49e-efdf47f6446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693813045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3693813045
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.2190465142
Short name T489
Test name
Test status
Simulation time 29857260 ps
CPU time 1.31 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 217996 kb
Host smart-5de0bb4e-de49-4e8c-8645-21fb5337c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190465142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2190465142
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.398445885
Short name T240
Test name
Test status
Simulation time 79819255 ps
CPU time 1.09 seconds
Started Apr 02 01:35:34 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 215480 kb
Host smart-318dc2af-cc70-49b3-bd7e-306ea028627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398445885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.398445885
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1718685214
Short name T701
Test name
Test status
Simulation time 20655469 ps
CPU time 1.03 seconds
Started Apr 02 01:35:38 PM PDT 24
Finished Apr 02 01:35:39 PM PDT 24
Peak memory 205928 kb
Host smart-03342c84-24f1-4312-a4f4-fc1769ca5ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718685214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1718685214
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3164928275
Short name T89
Test name
Test status
Simulation time 31635491 ps
CPU time 0.78 seconds
Started Apr 02 01:35:37 PM PDT 24
Finished Apr 02 01:35:38 PM PDT 24
Peak memory 215380 kb
Host smart-8e64fed9-843c-41bc-ada0-68fd2171499a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164928275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3164928275
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.4170286120
Short name T811
Test name
Test status
Simulation time 19300442 ps
CPU time 1.09 seconds
Started Apr 02 01:35:35 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 218044 kb
Host smart-38ceac13-0036-4260-bd92-6d4575e26cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170286120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4170286120
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3187187374
Short name T774
Test name
Test status
Simulation time 43019582 ps
CPU time 1.19 seconds
Started Apr 02 01:35:39 PM PDT 24
Finished Apr 02 01:35:40 PM PDT 24
Peak memory 216752 kb
Host smart-b0ada1f1-0045-4f17-8636-54c33ca87dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187187374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3187187374
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2530406850
Short name T603
Test name
Test status
Simulation time 38807643 ps
CPU time 0.95 seconds
Started Apr 02 01:35:35 PM PDT 24
Finished Apr 02 01:35:38 PM PDT 24
Peak memory 215408 kb
Host smart-58edbe6d-106b-4aac-83d8-2922136354ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530406850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2530406850
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2436845492
Short name T361
Test name
Test status
Simulation time 82507732 ps
CPU time 0.9 seconds
Started Apr 02 01:35:34 PM PDT 24
Finished Apr 02 01:35:37 PM PDT 24
Peak memory 215244 kb
Host smart-f0bb248d-edd8-48fe-b1db-9364c1b5225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436845492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2436845492
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1252722779
Short name T195
Test name
Test status
Simulation time 189218913 ps
CPU time 2.4 seconds
Started Apr 02 01:35:35 PM PDT 24
Finished Apr 02 01:35:39 PM PDT 24
Peak memory 216388 kb
Host smart-6ec51ad1-bc77-4742-9d0a-9d8e8fd00592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252722779 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1252722779
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3318306222
Short name T182
Test name
Test status
Simulation time 116169683526 ps
CPU time 555.75 seconds
Started Apr 02 01:35:35 PM PDT 24
Finished Apr 02 01:44:52 PM PDT 24
Peak memory 219212 kb
Host smart-b9e540de-202b-4cc6-b249-2527208fb555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318306222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3318306222
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.132424667
Short name T399
Test name
Test status
Simulation time 52390172 ps
CPU time 2.03 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:20 PM PDT 24
Peak memory 218056 kb
Host smart-60f8af64-9d6e-4e22-86c8-7d7141a0bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132424667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.132424667
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3561152801
Short name T329
Test name
Test status
Simulation time 55736235 ps
CPU time 1.1 seconds
Started Apr 02 01:38:08 PM PDT 24
Finished Apr 02 01:38:09 PM PDT 24
Peak memory 216644 kb
Host smart-24c0bc08-c55f-4e5f-83b9-b3f748e09c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561152801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3561152801
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3867723467
Short name T175
Test name
Test status
Simulation time 90581557 ps
CPU time 1.32 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 218280 kb
Host smart-f4c5edcd-d6fd-44d4-93e8-1a2298b04ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867723467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3867723467
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2666868793
Short name T696
Test name
Test status
Simulation time 168534621 ps
CPU time 2.21 seconds
Started Apr 02 01:38:11 PM PDT 24
Finished Apr 02 01:38:14 PM PDT 24
Peak memory 219104 kb
Host smart-7d4ded86-663c-462c-825d-576595f6cec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666868793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2666868793
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3778132125
Short name T400
Test name
Test status
Simulation time 44799914 ps
CPU time 1.22 seconds
Started Apr 02 01:38:11 PM PDT 24
Finished Apr 02 01:38:13 PM PDT 24
Peak memory 217916 kb
Host smart-05ed96b6-90b9-40ee-aa0e-a3519e20711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778132125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3778132125
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3642776168
Short name T331
Test name
Test status
Simulation time 74604897 ps
CPU time 1.1 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 215292 kb
Host smart-44355172-69ab-40c0-a8dd-94b5c674e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642776168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3642776168
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1287675220
Short name T652
Test name
Test status
Simulation time 35091307 ps
CPU time 1.42 seconds
Started Apr 02 01:38:11 PM PDT 24
Finished Apr 02 01:38:13 PM PDT 24
Peak memory 217844 kb
Host smart-035b14d8-56e1-46bf-9067-37a66ac10cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287675220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1287675220
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1716501820
Short name T372
Test name
Test status
Simulation time 78864361 ps
CPU time 1.36 seconds
Started Apr 02 01:38:15 PM PDT 24
Finished Apr 02 01:38:17 PM PDT 24
Peak memory 217848 kb
Host smart-0bbe869c-65ac-4914-bc00-20f41af57ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716501820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1716501820
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1741468245
Short name T566
Test name
Test status
Simulation time 23306696 ps
CPU time 1.1 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 217776 kb
Host smart-92977b87-e609-4198-a190-f84bcdfe571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741468245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1741468245
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1437001924
Short name T468
Test name
Test status
Simulation time 126193556 ps
CPU time 1.23 seconds
Started Apr 02 01:35:47 PM PDT 24
Finished Apr 02 01:35:48 PM PDT 24
Peak memory 215460 kb
Host smart-a6d3ba17-3f0a-4af9-9bb1-12bcdf5fc5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437001924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1437001924
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3531199017
Short name T413
Test name
Test status
Simulation time 34058091 ps
CPU time 0.78 seconds
Started Apr 02 01:35:45 PM PDT 24
Finished Apr 02 01:35:46 PM PDT 24
Peak memory 206440 kb
Host smart-bc68e4b9-8379-48ec-9cc8-3d436a6dc647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531199017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3531199017
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2889959143
Short name T558
Test name
Test status
Simulation time 22490331 ps
CPU time 0.84 seconds
Started Apr 02 01:35:41 PM PDT 24
Finished Apr 02 01:35:42 PM PDT 24
Peak memory 215700 kb
Host smart-6eba0ec4-0c47-4a50-a9a7-31212ef4e30b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889959143 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2889959143
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.557445985
Short name T451
Test name
Test status
Simulation time 42077650 ps
CPU time 1.24 seconds
Started Apr 02 01:35:41 PM PDT 24
Finished Apr 02 01:35:42 PM PDT 24
Peak memory 224136 kb
Host smart-53e3ef97-587f-428d-8aa6-2184ef47a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557445985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.557445985
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1679084600
Short name T381
Test name
Test status
Simulation time 43496808 ps
CPU time 1.74 seconds
Started Apr 02 01:35:39 PM PDT 24
Finished Apr 02 01:35:40 PM PDT 24
Peak memory 217684 kb
Host smart-07cdb2c0-f6fa-4faf-ba21-523b054a462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679084600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1679084600
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.443948538
Short name T131
Test name
Test status
Simulation time 27877298 ps
CPU time 0.88 seconds
Started Apr 02 01:35:40 PM PDT 24
Finished Apr 02 01:35:41 PM PDT 24
Peak memory 215476 kb
Host smart-90cd3f4a-5212-4be2-ba2b-0c95473ae7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443948538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.443948538
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.4259652649
Short name T678
Test name
Test status
Simulation time 44086570 ps
CPU time 0.88 seconds
Started Apr 02 01:35:37 PM PDT 24
Finished Apr 02 01:35:38 PM PDT 24
Peak memory 215260 kb
Host smart-582b6a76-7af8-4a9e-9778-0dec06f407a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259652649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.4259652649
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2332614866
Short name T200
Test name
Test status
Simulation time 667828458 ps
CPU time 3.79 seconds
Started Apr 02 01:35:36 PM PDT 24
Finished Apr 02 01:35:41 PM PDT 24
Peak memory 216440 kb
Host smart-0540c068-c740-4392-9759-25c578016f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332614866 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2332614866
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3813745528
Short name T187
Test name
Test status
Simulation time 40465937214 ps
CPU time 930.94 seconds
Started Apr 02 01:35:37 PM PDT 24
Finished Apr 02 01:51:08 PM PDT 24
Peak memory 220068 kb
Host smart-6054b50b-92e5-4750-98d1-6fc8be8359ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813745528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3813745528
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2861526042
Short name T590
Test name
Test status
Simulation time 112759762 ps
CPU time 1.16 seconds
Started Apr 02 01:38:15 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 216508 kb
Host smart-764f507a-62aa-4db7-a6a5-32b136091e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861526042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2861526042
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.983940971
Short name T511
Test name
Test status
Simulation time 43062836 ps
CPU time 1.61 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:17 PM PDT 24
Peak memory 216572 kb
Host smart-835a06f6-ca96-41b3-bff2-e9bdf68666ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983940971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.983940971
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2473945937
Short name T431
Test name
Test status
Simulation time 85515456 ps
CPU time 1.23 seconds
Started Apr 02 01:38:16 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 217776 kb
Host smart-bf00f098-4c6a-4da1-9c6d-4ca52fdb4308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473945937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2473945937
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3988270028
Short name T646
Test name
Test status
Simulation time 138756607 ps
CPU time 1.24 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 216632 kb
Host smart-525ca776-9aff-4273-aaa1-cad613c9522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988270028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3988270028
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2599957525
Short name T314
Test name
Test status
Simulation time 43569623 ps
CPU time 1.26 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 217796 kb
Host smart-b2639331-72f5-46d6-83f2-66b8f2e5320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599957525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2599957525
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2072321166
Short name T741
Test name
Test status
Simulation time 54817453 ps
CPU time 1.4 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 216544 kb
Host smart-b8fee4f4-ca0e-43ec-96ca-b09763839c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072321166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2072321166
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.852517024
Short name T11
Test name
Test status
Simulation time 72902179 ps
CPU time 1.1 seconds
Started Apr 02 01:38:18 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 216856 kb
Host smart-d0faf195-32ff-44d8-803a-65b5a7356c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852517024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.852517024
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2471852259
Short name T498
Test name
Test status
Simulation time 58543366 ps
CPU time 0.98 seconds
Started Apr 02 01:38:15 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 216620 kb
Host smart-c95f2c73-eb04-47a5-b32c-dd7df7e8720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471852259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2471852259
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.85914099
Short name T360
Test name
Test status
Simulation time 49918256 ps
CPU time 1.16 seconds
Started Apr 02 01:38:15 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 216408 kb
Host smart-baa54c50-6acb-497e-8b5d-dc2cfe986525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85914099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.85914099
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.54651512
Short name T525
Test name
Test status
Simulation time 41834189 ps
CPU time 1.34 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 217788 kb
Host smart-56506abc-dc63-4c59-95f9-6720fc57af00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54651512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.54651512
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2349790812
Short name T269
Test name
Test status
Simulation time 97217117 ps
CPU time 1.25 seconds
Started Apr 02 01:35:37 PM PDT 24
Finished Apr 02 01:35:39 PM PDT 24
Peak memory 215648 kb
Host smart-9aaf9648-6eea-4437-86ec-8322116ee917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349790812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2349790812
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3503057345
Short name T375
Test name
Test status
Simulation time 43804244 ps
CPU time 0.83 seconds
Started Apr 02 01:35:45 PM PDT 24
Finished Apr 02 01:35:46 PM PDT 24
Peak memory 206360 kb
Host smart-a0badcb2-8be7-4390-940a-cecbe221968c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503057345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3503057345
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.373217174
Short name T692
Test name
Test status
Simulation time 83002642 ps
CPU time 1.09 seconds
Started Apr 02 01:35:43 PM PDT 24
Finished Apr 02 01:35:45 PM PDT 24
Peak memory 216544 kb
Host smart-44ef71b4-e6af-4ad0-83b3-345a557769e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373217174 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.373217174
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3974772678
Short name T153
Test name
Test status
Simulation time 19846858 ps
CPU time 1.18 seconds
Started Apr 02 01:35:39 PM PDT 24
Finished Apr 02 01:35:41 PM PDT 24
Peak memory 231276 kb
Host smart-a7957853-709b-4bab-b38c-bbc2d9168ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974772678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3974772678
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.193476077
Short name T25
Test name
Test status
Simulation time 59221031 ps
CPU time 2.12 seconds
Started Apr 02 01:35:43 PM PDT 24
Finished Apr 02 01:35:46 PM PDT 24
Peak memory 217800 kb
Host smart-eb834f68-4c36-416c-8454-50088cc43008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193476077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.193476077
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3380006379
Short name T445
Test name
Test status
Simulation time 20792779 ps
CPU time 1.17 seconds
Started Apr 02 01:35:39 PM PDT 24
Finished Apr 02 01:35:40 PM PDT 24
Peak memory 224044 kb
Host smart-9a1d256c-9485-4ac8-a09c-4a85a58baa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380006379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3380006379
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1099231561
Short name T394
Test name
Test status
Simulation time 50940701 ps
CPU time 0.96 seconds
Started Apr 02 01:35:37 PM PDT 24
Finished Apr 02 01:35:38 PM PDT 24
Peak memory 215272 kb
Host smart-70f7dd82-1c74-4b19-b736-c61b97e0052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099231561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1099231561
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.218374581
Short name T332
Test name
Test status
Simulation time 364111268 ps
CPU time 4.71 seconds
Started Apr 02 01:35:38 PM PDT 24
Finished Apr 02 01:35:43 PM PDT 24
Peak memory 215292 kb
Host smart-c0a99b90-d5fd-4dbb-8554-451454f5fd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218374581 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.218374581
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2637809616
Short name T689
Test name
Test status
Simulation time 23665717830 ps
CPU time 432.12 seconds
Started Apr 02 01:35:40 PM PDT 24
Finished Apr 02 01:42:53 PM PDT 24
Peak memory 221232 kb
Host smart-0f2862ec-6b6c-462e-acab-61d95273584a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637809616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2637809616
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.283823611
Short name T479
Test name
Test status
Simulation time 50067769 ps
CPU time 1.23 seconds
Started Apr 02 01:38:14 PM PDT 24
Finished Apr 02 01:38:16 PM PDT 24
Peak memory 217824 kb
Host smart-69aecb92-a4c3-4712-8230-52ee6f6443df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283823611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.283823611
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1866305124
Short name T580
Test name
Test status
Simulation time 29696410 ps
CPU time 1.23 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 216808 kb
Host smart-6f52fd82-a726-4ced-a146-05f0382abb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866305124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1866305124
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1804821363
Short name T643
Test name
Test status
Simulation time 41487540 ps
CPU time 1.51 seconds
Started Apr 02 01:38:13 PM PDT 24
Finished Apr 02 01:38:15 PM PDT 24
Peak memory 217736 kb
Host smart-a44e579b-2eb6-42f0-9f24-75315f4274d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804821363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1804821363
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.610007231
Short name T780
Test name
Test status
Simulation time 78309592 ps
CPU time 1.19 seconds
Started Apr 02 01:38:19 PM PDT 24
Finished Apr 02 01:38:20 PM PDT 24
Peak memory 216596 kb
Host smart-27f6aea2-259e-4774-8b07-e194bad1e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610007231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.610007231
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2190028330
Short name T241
Test name
Test status
Simulation time 54328081 ps
CPU time 1.68 seconds
Started Apr 02 01:38:18 PM PDT 24
Finished Apr 02 01:38:20 PM PDT 24
Peak memory 218036 kb
Host smart-03d2ebd6-983b-4166-a9d2-397d3b6ffa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190028330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2190028330
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2285861822
Short name T392
Test name
Test status
Simulation time 42122604 ps
CPU time 1.18 seconds
Started Apr 02 01:38:16 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 218236 kb
Host smart-3212114c-2d81-4775-8c62-75abd74d334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285861822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2285861822
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.795481830
Short name T526
Test name
Test status
Simulation time 34001467 ps
CPU time 0.99 seconds
Started Apr 02 01:38:29 PM PDT 24
Finished Apr 02 01:38:30 PM PDT 24
Peak memory 216608 kb
Host smart-24ac90c2-2fbf-41d6-a3c4-637ad59fa88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795481830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.795481830
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1498162518
Short name T389
Test name
Test status
Simulation time 53311413 ps
CPU time 1.29 seconds
Started Apr 02 01:38:19 PM PDT 24
Finished Apr 02 01:38:20 PM PDT 24
Peak memory 218192 kb
Host smart-bd6f5aa9-27c3-4239-9ace-5f439ab39ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498162518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1498162518
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1233832199
Short name T599
Test name
Test status
Simulation time 55116139 ps
CPU time 1.38 seconds
Started Apr 02 01:38:18 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 218132 kb
Host smart-bbcec9c7-00c9-4c6d-9094-9ac3eb4bbaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233832199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1233832199
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1473428267
Short name T386
Test name
Test status
Simulation time 61142647 ps
CPU time 1.03 seconds
Started Apr 02 01:38:18 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 216484 kb
Host smart-7671abbd-28a7-430e-b6d9-3803f2199fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473428267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1473428267
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2720893010
Short name T224
Test name
Test status
Simulation time 68516203 ps
CPU time 1.25 seconds
Started Apr 02 01:35:43 PM PDT 24
Finished Apr 02 01:35:45 PM PDT 24
Peak memory 215568 kb
Host smart-4ce0b0eb-fcd9-42a3-93ba-f760bdfdbb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720893010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2720893010
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.609729901
Short name T613
Test name
Test status
Simulation time 19507020 ps
CPU time 0.81 seconds
Started Apr 02 01:35:46 PM PDT 24
Finished Apr 02 01:35:47 PM PDT 24
Peak memory 205512 kb
Host smart-acfcaf8c-24a6-4b99-bc2c-f0095c42d22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609729901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.609729901
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1139626229
Short name T630
Test name
Test status
Simulation time 13511519 ps
CPU time 0.94 seconds
Started Apr 02 01:35:46 PM PDT 24
Finished Apr 02 01:35:47 PM PDT 24
Peak memory 215688 kb
Host smart-681be750-2494-4665-82fa-c0fe6af26d47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139626229 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1139626229
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.1680257481
Short name T429
Test name
Test status
Simulation time 20978769 ps
CPU time 1.07 seconds
Started Apr 02 01:35:42 PM PDT 24
Finished Apr 02 01:35:45 PM PDT 24
Peak memory 218132 kb
Host smart-8ab6a0e2-3c33-4b34-bc62-5d83c5e959f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680257481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1680257481
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.237601442
Short name T376
Test name
Test status
Simulation time 56374364 ps
CPU time 1.02 seconds
Started Apr 02 01:35:41 PM PDT 24
Finished Apr 02 01:35:42 PM PDT 24
Peak memory 216556 kb
Host smart-671b9567-d6a9-4546-b4ec-5a156a1f021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237601442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.237601442
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.3256399110
Short name T717
Test name
Test status
Simulation time 15628647 ps
CPU time 0.93 seconds
Started Apr 02 01:35:45 PM PDT 24
Finished Apr 02 01:35:46 PM PDT 24
Peak memory 215140 kb
Host smart-177dedb5-476a-4979-b9ec-f1f1aa41680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256399110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3256399110
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2148888589
Short name T810
Test name
Test status
Simulation time 484598492 ps
CPU time 5.87 seconds
Started Apr 02 01:35:43 PM PDT 24
Finished Apr 02 01:35:49 PM PDT 24
Peak memory 215348 kb
Host smart-b316e4a6-4039-4189-9565-e952249b221a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148888589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2148888589
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_genbits.3850424566
Short name T600
Test name
Test status
Simulation time 110128540 ps
CPU time 1.6 seconds
Started Apr 02 01:38:17 PM PDT 24
Finished Apr 02 01:38:19 PM PDT 24
Peak memory 218108 kb
Host smart-a965c0ae-bd43-41c7-b42b-bcbdd6f05c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850424566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3850424566
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3549322234
Short name T629
Test name
Test status
Simulation time 53568246 ps
CPU time 1.59 seconds
Started Apr 02 01:38:18 PM PDT 24
Finished Apr 02 01:38:20 PM PDT 24
Peak memory 217728 kb
Host smart-b8937cbe-0689-4ee7-9d9f-7e5031fddb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549322234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3549322234
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1847981590
Short name T787
Test name
Test status
Simulation time 27404729 ps
CPU time 1.22 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 216656 kb
Host smart-2b5316f3-0b9e-4338-aee2-1ae9fb27c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847981590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1847981590
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1434145595
Short name T514
Test name
Test status
Simulation time 42885470 ps
CPU time 1.42 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 215280 kb
Host smart-6c05f50e-6cbd-4bfb-a521-535d73e919ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434145595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1434145595
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.512078669
Short name T12
Test name
Test status
Simulation time 52079930 ps
CPU time 1.63 seconds
Started Apr 02 01:38:33 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 215288 kb
Host smart-0fc67f86-0809-47b1-bf06-0010f38f7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512078669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.512078669
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2727313173
Short name T280
Test name
Test status
Simulation time 53914822 ps
CPU time 0.99 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:22 PM PDT 24
Peak memory 216512 kb
Host smart-2dda0009-a804-42d4-a0cb-e9fcb194dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727313173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2727313173
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1486080181
Short name T165
Test name
Test status
Simulation time 51667903 ps
CPU time 1.6 seconds
Started Apr 02 01:38:22 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 218012 kb
Host smart-cba787c3-d0bf-4abf-8354-a7606c965c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486080181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1486080181
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1455662684
Short name T637
Test name
Test status
Simulation time 41498782 ps
CPU time 1.19 seconds
Started Apr 02 01:38:22 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 217828 kb
Host smart-a0a55a0b-8d7e-4d55-8a94-ec99fd61ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455662684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1455662684
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1129763614
Short name T462
Test name
Test status
Simulation time 44765300 ps
CPU time 1.67 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:23 PM PDT 24
Peak memory 217688 kb
Host smart-46f92e49-0b3b-4ba6-9725-410d136aefe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129763614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1129763614
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2041300172
Short name T472
Test name
Test status
Simulation time 88451746 ps
CPU time 1.87 seconds
Started Apr 02 01:38:22 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 219228 kb
Host smart-a0219af7-3724-4d4a-807c-6175a75e8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041300172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2041300172
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1909565080
Short name T268
Test name
Test status
Simulation time 50590511 ps
CPU time 1.23 seconds
Started Apr 02 01:35:51 PM PDT 24
Finished Apr 02 01:35:52 PM PDT 24
Peak memory 215628 kb
Host smart-8bd43499-d107-4ff9-8510-866449e2f815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909565080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1909565080
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3120706316
Short name T578
Test name
Test status
Simulation time 46148816 ps
CPU time 0.82 seconds
Started Apr 02 01:35:50 PM PDT 24
Finished Apr 02 01:35:51 PM PDT 24
Peak memory 205520 kb
Host smart-3863bba1-85cd-47ae-b62c-d3f066c02215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120706316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3120706316
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.898325049
Short name T32
Test name
Test status
Simulation time 11994678 ps
CPU time 0.87 seconds
Started Apr 02 01:35:49 PM PDT 24
Finished Apr 02 01:35:50 PM PDT 24
Peak memory 216000 kb
Host smart-c5488880-6c39-479f-acf4-695482b7cc3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898325049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.898325049
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.1754804269
Short name T43
Test name
Test status
Simulation time 24589100 ps
CPU time 1.23 seconds
Started Apr 02 01:35:51 PM PDT 24
Finished Apr 02 01:35:52 PM PDT 24
Peak memory 233324 kb
Host smart-3ceae2d2-5596-484c-8e57-e9c495f0fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754804269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1754804269
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1109981137
Short name T508
Test name
Test status
Simulation time 47431181 ps
CPU time 1.49 seconds
Started Apr 02 01:35:46 PM PDT 24
Finished Apr 02 01:35:48 PM PDT 24
Peak memory 217760 kb
Host smart-ad746588-003d-47dd-9438-9a24719f3f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109981137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1109981137
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3190006700
Short name T124
Test name
Test status
Simulation time 29638321 ps
CPU time 0.91 seconds
Started Apr 02 01:35:47 PM PDT 24
Finished Apr 02 01:35:48 PM PDT 24
Peak memory 215464 kb
Host smart-cf279bf7-0b79-4bb1-b7f6-93116a1864e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190006700 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3190006700
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2810879143
Short name T305
Test name
Test status
Simulation time 25725461 ps
CPU time 0.96 seconds
Started Apr 02 01:35:46 PM PDT 24
Finished Apr 02 01:35:47 PM PDT 24
Peak memory 206980 kb
Host smart-69870d9f-c6e5-4a83-b01c-812915d75783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810879143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2810879143
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4029092995
Short name T310
Test name
Test status
Simulation time 679273113 ps
CPU time 4.51 seconds
Started Apr 02 01:35:45 PM PDT 24
Finished Apr 02 01:35:50 PM PDT 24
Peak memory 216468 kb
Host smart-0e857a44-fbe7-479e-b772-228685fe4567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029092995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4029092995
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4065292037
Short name T615
Test name
Test status
Simulation time 75847731068 ps
CPU time 1491.97 seconds
Started Apr 02 01:35:44 PM PDT 24
Finished Apr 02 02:00:37 PM PDT 24
Peak memory 222640 kb
Host smart-4931cc92-10ae-4a1f-813e-2769b91f5b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065292037 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4065292037
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3495926583
Short name T728
Test name
Test status
Simulation time 294964501 ps
CPU time 4.03 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:25 PM PDT 24
Peak memory 217076 kb
Host smart-7ac20486-f99c-4853-a09b-00c2ec7cfe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495926583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3495926583
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.4127433994
Short name T421
Test name
Test status
Simulation time 60499550 ps
CPU time 2.12 seconds
Started Apr 02 01:38:33 PM PDT 24
Finished Apr 02 01:38:35 PM PDT 24
Peak memory 217964 kb
Host smart-1c007e4c-0ef5-428f-ac29-958f9505dbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127433994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4127433994
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.425812906
Short name T669
Test name
Test status
Simulation time 40296977 ps
CPU time 1.4 seconds
Started Apr 02 01:38:22 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 217560 kb
Host smart-44680cea-9e1d-4cfd-8f2a-37ead920ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425812906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.425812906
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1559863270
Short name T27
Test name
Test status
Simulation time 40783057 ps
CPU time 1.61 seconds
Started Apr 02 01:38:22 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 217872 kb
Host smart-99ae3a05-f07a-4655-9424-1c39bdcc9260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559863270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1559863270
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4220320334
Short name T836
Test name
Test status
Simulation time 108464244 ps
CPU time 1.63 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:23 PM PDT 24
Peak memory 217884 kb
Host smart-fcf0e419-9292-4398-9114-67a009c03c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220320334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4220320334
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.4068695499
Short name T627
Test name
Test status
Simulation time 89181152 ps
CPU time 1.19 seconds
Started Apr 02 01:38:21 PM PDT 24
Finished Apr 02 01:38:23 PM PDT 24
Peak memory 217820 kb
Host smart-274a1ffe-9a57-44d8-9adb-0404d1b29840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068695499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4068695499
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.189249106
Short name T567
Test name
Test status
Simulation time 42523775 ps
CPU time 1.74 seconds
Started Apr 02 01:38:24 PM PDT 24
Finished Apr 02 01:38:26 PM PDT 24
Peak memory 217608 kb
Host smart-cbfec51d-7428-462d-93e2-20450b96ec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189249106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.189249106
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3713461747
Short name T745
Test name
Test status
Simulation time 33577066 ps
CPU time 1.23 seconds
Started Apr 02 01:38:22 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 216632 kb
Host smart-50caee40-cf52-4134-bc5a-9ed9cfb54899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713461747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3713461747
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4221639238
Short name T138
Test name
Test status
Simulation time 100846185 ps
CPU time 1.35 seconds
Started Apr 02 01:36:02 PM PDT 24
Finished Apr 02 01:36:03 PM PDT 24
Peak memory 215596 kb
Host smart-8c68cce0-700f-4905-96fb-44cb37891af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221639238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4221639238
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3612992268
Short name T619
Test name
Test status
Simulation time 86619911 ps
CPU time 0.85 seconds
Started Apr 02 01:35:57 PM PDT 24
Finished Apr 02 01:35:58 PM PDT 24
Peak memory 205516 kb
Host smart-562a6a9f-980d-4f4b-b692-d9a09a9a6d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612992268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3612992268
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1475251136
Short name T77
Test name
Test status
Simulation time 31650495 ps
CPU time 1.1 seconds
Started Apr 02 01:35:55 PM PDT 24
Finished Apr 02 01:35:56 PM PDT 24
Peak memory 217792 kb
Host smart-366faece-52aa-46fe-a9ff-f3328bb7aef5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475251136 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1475251136
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1583341012
Short name T813
Test name
Test status
Simulation time 27922098 ps
CPU time 1.36 seconds
Started Apr 02 01:35:57 PM PDT 24
Finished Apr 02 01:35:59 PM PDT 24
Peak memory 232356 kb
Host smart-13fefc17-9a0e-4a73-af8d-119d2267c2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583341012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1583341012
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.292132416
Short name T53
Test name
Test status
Simulation time 31830563 ps
CPU time 1.23 seconds
Started Apr 02 01:35:54 PM PDT 24
Finished Apr 02 01:35:56 PM PDT 24
Peak memory 218120 kb
Host smart-cfd2827c-bc47-48c1-8cda-3c8fb8d29b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292132416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.292132416
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3900054431
Short name T654
Test name
Test status
Simulation time 21053756 ps
CPU time 1.15 seconds
Started Apr 02 01:35:56 PM PDT 24
Finished Apr 02 01:35:57 PM PDT 24
Peak memory 215456 kb
Host smart-e869eb5b-b815-4f4d-97be-ef74f9bd989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900054431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3900054431
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.4249622574
Short name T740
Test name
Test status
Simulation time 23968201 ps
CPU time 0.94 seconds
Started Apr 02 01:35:50 PM PDT 24
Finished Apr 02 01:35:51 PM PDT 24
Peak memory 215300 kb
Host smart-3f929986-61bc-4282-a4e7-5f211043a75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249622574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4249622574
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4243245714
Short name T687
Test name
Test status
Simulation time 404392059 ps
CPU time 4.22 seconds
Started Apr 02 01:35:55 PM PDT 24
Finished Apr 02 01:36:00 PM PDT 24
Peak memory 215292 kb
Host smart-7395128d-5193-4393-8aa9-595ee0c3e630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243245714 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4243245714
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3783644261
Short name T183
Test name
Test status
Simulation time 173458097751 ps
CPU time 985.85 seconds
Started Apr 02 01:35:53 PM PDT 24
Finished Apr 02 01:52:20 PM PDT 24
Peak memory 220688 kb
Host smart-412930f3-2dd5-4374-9e42-ae45325c3de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783644261 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3783644261
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2414871048
Short name T173
Test name
Test status
Simulation time 90994553 ps
CPU time 1.23 seconds
Started Apr 02 01:38:23 PM PDT 24
Finished Apr 02 01:38:24 PM PDT 24
Peak memory 217920 kb
Host smart-462bb712-c1e6-4692-bb55-9594f672b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414871048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2414871048
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.235526494
Short name T459
Test name
Test status
Simulation time 42057245 ps
CPU time 1.25 seconds
Started Apr 02 01:38:25 PM PDT 24
Finished Apr 02 01:38:26 PM PDT 24
Peak memory 216596 kb
Host smart-ab0cb3bd-5cf4-4a54-a2f1-cb6487d2543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235526494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.235526494
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.22634818
Short name T504
Test name
Test status
Simulation time 37009404 ps
CPU time 1.24 seconds
Started Apr 02 01:38:23 PM PDT 24
Finished Apr 02 01:38:25 PM PDT 24
Peak memory 218004 kb
Host smart-b3e532ef-1a56-4f41-9b19-f28135d0d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22634818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.22634818
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1660854057
Short name T714
Test name
Test status
Simulation time 94138651 ps
CPU time 3.32 seconds
Started Apr 02 01:38:25 PM PDT 24
Finished Apr 02 01:38:29 PM PDT 24
Peak memory 217932 kb
Host smart-6f17a124-513c-4380-8e2f-432674f72744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660854057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1660854057
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1037313501
Short name T166
Test name
Test status
Simulation time 68554975 ps
CPU time 1.39 seconds
Started Apr 02 01:38:24 PM PDT 24
Finished Apr 02 01:38:25 PM PDT 24
Peak memory 218264 kb
Host smart-e5b191ad-217a-490d-8913-f865a13558e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037313501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1037313501
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.783152976
Short name T824
Test name
Test status
Simulation time 95471289 ps
CPU time 1.29 seconds
Started Apr 02 01:38:25 PM PDT 24
Finished Apr 02 01:38:27 PM PDT 24
Peak memory 217928 kb
Host smart-7d5a9279-33a6-4eaa-822d-5883467e13ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783152976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.783152976
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3313291401
Short name T233
Test name
Test status
Simulation time 128458819 ps
CPU time 1.62 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 218152 kb
Host smart-9ce9650d-0cda-4d1d-b0d1-6c783ba710d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313291401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3313291401
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.4218118578
Short name T340
Test name
Test status
Simulation time 89104589 ps
CPU time 1.14 seconds
Started Apr 02 01:38:24 PM PDT 24
Finished Apr 02 01:38:26 PM PDT 24
Peak memory 216704 kb
Host smart-12e9bb7e-c180-4b55-a146-d2a600893cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218118578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4218118578
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3837190679
Short name T227
Test name
Test status
Simulation time 50795626 ps
CPU time 1.16 seconds
Started Apr 02 01:38:24 PM PDT 24
Finished Apr 02 01:38:25 PM PDT 24
Peak memory 216688 kb
Host smart-90b65e46-53de-4696-b5fe-fed6542b221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837190679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3837190679
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2611124334
Short name T501
Test name
Test status
Simulation time 125049163 ps
CPU time 1.21 seconds
Started Apr 02 01:34:31 PM PDT 24
Finished Apr 02 01:34:32 PM PDT 24
Peak memory 215616 kb
Host smart-0e4983b0-095a-4c43-bc25-23106b7955be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611124334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2611124334
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1503703511
Short name T809
Test name
Test status
Simulation time 13339566 ps
CPU time 0.86 seconds
Started Apr 02 01:34:31 PM PDT 24
Finished Apr 02 01:34:32 PM PDT 24
Peak memory 205736 kb
Host smart-81221fb7-f008-4224-bc23-a8df40f512a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503703511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1503703511
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2199968218
Short name T700
Test name
Test status
Simulation time 11710925 ps
CPU time 0.88 seconds
Started Apr 02 01:34:32 PM PDT 24
Finished Apr 02 01:34:33 PM PDT 24
Peak memory 215660 kb
Host smart-867e2c7e-ae7e-43d6-ba01-0452d27f931e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199968218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2199968218
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2569291774
Short name T487
Test name
Test status
Simulation time 26287307 ps
CPU time 1.11 seconds
Started Apr 02 01:34:33 PM PDT 24
Finished Apr 02 01:34:34 PM PDT 24
Peak memory 217824 kb
Host smart-46ede4a8-82cb-4b8b-8e23-ba3f7af35ccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569291774 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2569291774
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1278958871
Short name T142
Test name
Test status
Simulation time 36552268 ps
CPU time 1.25 seconds
Started Apr 02 01:34:29 PM PDT 24
Finished Apr 02 01:34:30 PM PDT 24
Peak memory 219348 kb
Host smart-0dc46fb4-3ca5-4ec4-ab29-7751eaee24b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278958871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1278958871
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4104809671
Short name T830
Test name
Test status
Simulation time 32220560 ps
CPU time 1.21 seconds
Started Apr 02 01:34:27 PM PDT 24
Finished Apr 02 01:34:29 PM PDT 24
Peak memory 217608 kb
Host smart-f19548b1-55e7-42cf-8695-7642b7454449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104809671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4104809671
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2502111926
Short name T800
Test name
Test status
Simulation time 22674072 ps
CPU time 1.08 seconds
Started Apr 02 01:34:30 PM PDT 24
Finished Apr 02 01:34:31 PM PDT 24
Peak memory 215420 kb
Host smart-151d52d7-7457-4dc6-bd0d-e1670c02872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502111926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2502111926
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2068439861
Short name T128
Test name
Test status
Simulation time 15662526 ps
CPU time 0.92 seconds
Started Apr 02 01:34:27 PM PDT 24
Finished Apr 02 01:34:29 PM PDT 24
Peak memory 207100 kb
Host smart-11415b4a-cbde-4932-95d7-81b47c229af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068439861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2068439861
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.215843822
Short name T380
Test name
Test status
Simulation time 19048076 ps
CPU time 1.01 seconds
Started Apr 02 01:34:29 PM PDT 24
Finished Apr 02 01:34:31 PM PDT 24
Peak memory 215296 kb
Host smart-0d987436-fdcb-4571-bb0f-ccab13c8fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215843822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.215843822
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3073174882
Short name T831
Test name
Test status
Simulation time 392029071 ps
CPU time 5.78 seconds
Started Apr 02 01:34:28 PM PDT 24
Finished Apr 02 01:34:34 PM PDT 24
Peak memory 216304 kb
Host smart-02032a8e-eadb-41b0-ba71-0ee131bdd678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073174882 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3073174882
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.93979133
Short name T415
Test name
Test status
Simulation time 63746529979 ps
CPU time 1554.19 seconds
Started Apr 02 01:34:29 PM PDT 24
Finished Apr 02 02:00:23 PM PDT 24
Peak memory 225432 kb
Host smart-f3aff17b-a6cb-4aa5-a234-0111c76b2138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93979133 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.93979133
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1659202029
Short name T720
Test name
Test status
Simulation time 33101366 ps
CPU time 1.26 seconds
Started Apr 02 01:35:59 PM PDT 24
Finished Apr 02 01:36:01 PM PDT 24
Peak memory 215588 kb
Host smart-9a39c490-8fcf-40b2-9151-f40f44280237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659202029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1659202029
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2799738481
Short name T304
Test name
Test status
Simulation time 20485924 ps
CPU time 0.92 seconds
Started Apr 02 01:35:59 PM PDT 24
Finished Apr 02 01:36:00 PM PDT 24
Peak memory 206000 kb
Host smart-d0b2746d-c655-439c-9005-d30d818c4edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799738481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2799738481
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2210765084
Short name T738
Test name
Test status
Simulation time 41664998 ps
CPU time 0.91 seconds
Started Apr 02 01:36:03 PM PDT 24
Finished Apr 02 01:36:04 PM PDT 24
Peak memory 215392 kb
Host smart-75b1562b-c977-43f3-88fd-ac6d1298431d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210765084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2210765084
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.844067082
Short name T605
Test name
Test status
Simulation time 24844627 ps
CPU time 1.06 seconds
Started Apr 02 01:35:59 PM PDT 24
Finished Apr 02 01:36:00 PM PDT 24
Peak memory 216332 kb
Host smart-f7f24dcb-3d14-4b6d-9a6f-420501fcf967
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844067082 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.844067082
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3959172625
Short name T161
Test name
Test status
Simulation time 31385783 ps
CPU time 0.94 seconds
Started Apr 02 01:35:59 PM PDT 24
Finished Apr 02 01:36:00 PM PDT 24
Peak memory 219068 kb
Host smart-881987f2-b341-4f83-913d-f56f39021feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959172625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3959172625
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2986190830
Short name T510
Test name
Test status
Simulation time 40813507 ps
CPU time 1.55 seconds
Started Apr 02 01:35:58 PM PDT 24
Finished Apr 02 01:36:00 PM PDT 24
Peak memory 217856 kb
Host smart-56c7e93d-f9e4-4e38-82fb-f41631b89019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986190830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2986190830
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1337804078
Short name T452
Test name
Test status
Simulation time 23246325 ps
CPU time 0.98 seconds
Started Apr 02 01:36:02 PM PDT 24
Finished Apr 02 01:36:03 PM PDT 24
Peak memory 215672 kb
Host smart-39047c80-8e2d-4a93-bfa0-ed6ca658ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337804078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1337804078
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1456953322
Short name T229
Test name
Test status
Simulation time 46051294 ps
CPU time 0.88 seconds
Started Apr 02 01:35:59 PM PDT 24
Finished Apr 02 01:36:00 PM PDT 24
Peak memory 215272 kb
Host smart-e171b9c6-8522-4555-a9cb-8fc22ed8c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456953322 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1456953322
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.4127342307
Short name T199
Test name
Test status
Simulation time 489909558 ps
CPU time 7.63 seconds
Started Apr 02 01:35:58 PM PDT 24
Finished Apr 02 01:36:06 PM PDT 24
Peak memory 215248 kb
Host smart-3ba9fb37-8804-432f-97f1-1e95c39b62b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127342307 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.4127342307
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1902382473
Short name T677
Test name
Test status
Simulation time 154941362329 ps
CPU time 940.88 seconds
Started Apr 02 01:35:59 PM PDT 24
Finished Apr 02 01:51:40 PM PDT 24
Peak memory 220072 kb
Host smart-ce905994-117a-4999-a847-a0cb7bbd15c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902382473 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1902382473
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.863639095
Short name T337
Test name
Test status
Simulation time 42152703 ps
CPU time 1.72 seconds
Started Apr 02 01:38:28 PM PDT 24
Finished Apr 02 01:38:30 PM PDT 24
Peak memory 217884 kb
Host smart-6e128f0e-e1b9-4494-8416-9d255479b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863639095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.863639095
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3631668076
Short name T442
Test name
Test status
Simulation time 82251167 ps
CPU time 1.42 seconds
Started Apr 02 01:38:25 PM PDT 24
Finished Apr 02 01:38:27 PM PDT 24
Peak memory 217924 kb
Host smart-e8eded1d-35e7-4971-a88b-fcd6c55bbfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631668076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3631668076
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3897790459
Short name T293
Test name
Test status
Simulation time 56128926 ps
CPU time 1.43 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 217760 kb
Host smart-373c50b9-a02d-4005-95c0-0183ec3c4a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897790459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3897790459
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3697225049
Short name T242
Test name
Test status
Simulation time 91014538 ps
CPU time 1.1 seconds
Started Apr 02 01:38:29 PM PDT 24
Finished Apr 02 01:38:31 PM PDT 24
Peak memory 216784 kb
Host smart-e9bd6fde-6da4-4f66-bbc0-ddb44df55459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697225049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3697225049
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3999491392
Short name T785
Test name
Test status
Simulation time 43319832 ps
CPU time 1.71 seconds
Started Apr 02 01:38:27 PM PDT 24
Finished Apr 02 01:38:29 PM PDT 24
Peak memory 217484 kb
Host smart-700c9a9a-cdbe-4108-973c-cc1e7615796b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999491392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3999491392
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3610308435
Short name T279
Test name
Test status
Simulation time 191074004 ps
CPU time 2.84 seconds
Started Apr 02 01:38:30 PM PDT 24
Finished Apr 02 01:38:33 PM PDT 24
Peak memory 216832 kb
Host smart-bd557b32-a4ca-4f2f-a9e8-0b7db874ff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610308435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3610308435
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3005360149
Short name T509
Test name
Test status
Simulation time 70295563 ps
CPU time 1.2 seconds
Started Apr 02 01:38:27 PM PDT 24
Finished Apr 02 01:38:29 PM PDT 24
Peak memory 216540 kb
Host smart-aa99bdfd-c103-4df2-8b88-ea50033f5488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005360149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3005360149
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2019656759
Short name T344
Test name
Test status
Simulation time 60628757 ps
CPU time 1.62 seconds
Started Apr 02 01:38:30 PM PDT 24
Finished Apr 02 01:38:32 PM PDT 24
Peak memory 216936 kb
Host smart-9f0effa1-6419-45e3-95d9-33344dcdbca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019656759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2019656759
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1767727475
Short name T357
Test name
Test status
Simulation time 43169925 ps
CPU time 1.28 seconds
Started Apr 02 01:38:30 PM PDT 24
Finished Apr 02 01:38:32 PM PDT 24
Peak memory 217808 kb
Host smart-a46c2e65-3a8b-4108-b8a6-31be1345cead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767727475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1767727475
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1408937653
Short name T829
Test name
Test status
Simulation time 49750436 ps
CPU time 1.25 seconds
Started Apr 02 01:38:28 PM PDT 24
Finished Apr 02 01:38:29 PM PDT 24
Peak memory 217936 kb
Host smart-ea313875-ff81-4bce-b4db-7f12d7332042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408937653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1408937653
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3217159888
Short name T265
Test name
Test status
Simulation time 83198272 ps
CPU time 1.27 seconds
Started Apr 02 01:36:03 PM PDT 24
Finished Apr 02 01:36:05 PM PDT 24
Peak memory 215580 kb
Host smart-732cef75-e0ef-47d2-9650-21d6de49c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217159888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3217159888
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.141285739
Short name T621
Test name
Test status
Simulation time 36786258 ps
CPU time 0.85 seconds
Started Apr 02 01:36:04 PM PDT 24
Finished Apr 02 01:36:05 PM PDT 24
Peak memory 205768 kb
Host smart-aeadd52e-6884-4461-a247-5fef22939884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141285739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.141285739
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1442751779
Short name T432
Test name
Test status
Simulation time 53200853 ps
CPU time 0.84 seconds
Started Apr 02 01:36:03 PM PDT 24
Finished Apr 02 01:36:04 PM PDT 24
Peak memory 215432 kb
Host smart-fbb2d449-e75d-4edd-8742-170f8bfd8a4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442751779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1442751779
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3556616665
Short name T719
Test name
Test status
Simulation time 143049794 ps
CPU time 1.02 seconds
Started Apr 02 01:36:03 PM PDT 24
Finished Apr 02 01:36:04 PM PDT 24
Peak memory 217508 kb
Host smart-b0b0f8a4-208b-4c33-8175-7b84dace5941
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556616665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3556616665
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.252028832
Short name T160
Test name
Test status
Simulation time 18859721 ps
CPU time 1.05 seconds
Started Apr 02 01:36:04 PM PDT 24
Finished Apr 02 01:36:05 PM PDT 24
Peak memory 218144 kb
Host smart-9f54a989-40d4-4ef0-b60e-164198a4dc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252028832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.252028832
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_intr.2260951607
Short name T748
Test name
Test status
Simulation time 101309931 ps
CPU time 0.82 seconds
Started Apr 02 01:36:03 PM PDT 24
Finished Apr 02 01:36:04 PM PDT 24
Peak memory 215224 kb
Host smart-96096fcd-bdd1-4243-851a-c1ada73690c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260951607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2260951607
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3689383133
Short name T837
Test name
Test status
Simulation time 42408899 ps
CPU time 0.89 seconds
Started Apr 02 01:35:58 PM PDT 24
Finished Apr 02 01:35:59 PM PDT 24
Peak memory 215276 kb
Host smart-830abb40-1099-4384-a0bb-c5a72d4c4042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689383133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3689383133
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2111477152
Short name T506
Test name
Test status
Simulation time 416956782 ps
CPU time 4.57 seconds
Started Apr 02 01:36:04 PM PDT 24
Finished Apr 02 01:36:09 PM PDT 24
Peak memory 216316 kb
Host smart-d762864b-1315-4e9f-a564-4e319f4d5992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111477152 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2111477152
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.663195629
Short name T626
Test name
Test status
Simulation time 38417340668 ps
CPU time 881.69 seconds
Started Apr 02 01:36:01 PM PDT 24
Finished Apr 02 01:50:43 PM PDT 24
Peak memory 217796 kb
Host smart-5bbd354a-192f-4e2b-a553-b7f58f530969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663195629 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.663195629
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/211.edn_genbits.1074782440
Short name T75
Test name
Test status
Simulation time 38621989 ps
CPU time 1.21 seconds
Started Apr 02 01:38:28 PM PDT 24
Finished Apr 02 01:38:30 PM PDT 24
Peak memory 219180 kb
Host smart-a9fb3548-d66a-4aa3-b5f6-a547aec1ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074782440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1074782440
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2162220425
Short name T31
Test name
Test status
Simulation time 53361431 ps
CPU time 1.31 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 216480 kb
Host smart-dfc19233-eb89-424d-a95b-790145c2420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162220425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2162220425
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3051990343
Short name T686
Test name
Test status
Simulation time 54678756 ps
CPU time 1.68 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 217544 kb
Host smart-acd6b19e-c246-4622-ac8f-3a5f4f0f7977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051990343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3051990343
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.609856790
Short name T543
Test name
Test status
Simulation time 81787134 ps
CPU time 1.19 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 216932 kb
Host smart-c3f04514-06ec-42c0-8887-3175feb7d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609856790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.609856790
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2015261275
Short name T606
Test name
Test status
Simulation time 34007760 ps
CPU time 1.43 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 217604 kb
Host smart-97b827a2-3cae-4fbe-b0fa-d7f127a3c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015261275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2015261275
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1382535390
Short name T667
Test name
Test status
Simulation time 28589312 ps
CPU time 1.34 seconds
Started Apr 02 01:38:31 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 216648 kb
Host smart-63177983-ecee-47dd-88f6-66c38f8e2867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382535390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1382535390
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4228836423
Short name T735
Test name
Test status
Simulation time 108515849 ps
CPU time 1.17 seconds
Started Apr 02 01:38:30 PM PDT 24
Finished Apr 02 01:38:31 PM PDT 24
Peak memory 216788 kb
Host smart-676241fa-6010-4737-baf7-492d6bcedae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228836423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4228836423
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1734370338
Short name T10
Test name
Test status
Simulation time 91386300 ps
CPU time 1.19 seconds
Started Apr 02 01:38:30 PM PDT 24
Finished Apr 02 01:38:32 PM PDT 24
Peak memory 216848 kb
Host smart-44d0e9bf-be9f-45f4-9e7f-c630bc4c7875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734370338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1734370338
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.823201240
Short name T484
Test name
Test status
Simulation time 61906658 ps
CPU time 1.31 seconds
Started Apr 02 01:38:32 PM PDT 24
Finished Apr 02 01:38:34 PM PDT 24
Peak memory 217852 kb
Host smart-329eea3e-242c-4972-8d64-cd5afa8ee098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823201240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.823201240
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3504218502
Short name T112
Test name
Test status
Simulation time 110250588 ps
CPU time 1.2 seconds
Started Apr 02 01:36:10 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 215544 kb
Host smart-58d419e0-ffa0-4347-ba4e-4991dbfcf7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504218502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3504218502
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1302481089
Short name T353
Test name
Test status
Simulation time 73640090 ps
CPU time 0.81 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 01:36:10 PM PDT 24
Peak memory 205596 kb
Host smart-af01d519-e109-4585-9079-6841d5d30e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302481089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1302481089
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.644424710
Short name T9
Test name
Test status
Simulation time 19703978 ps
CPU time 1.08 seconds
Started Apr 02 01:36:10 PM PDT 24
Finished Apr 02 01:36:11 PM PDT 24
Peak memory 218092 kb
Host smart-9ec8407d-fac0-48ff-9570-16a099bd6b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644424710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.644424710
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1604311255
Short name T670
Test name
Test status
Simulation time 59600435 ps
CPU time 1.17 seconds
Started Apr 02 01:36:05 PM PDT 24
Finished Apr 02 01:36:06 PM PDT 24
Peak memory 217900 kb
Host smart-7aa7247c-4f60-45c1-9aef-f423ee60897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604311255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1604311255
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3363689381
Short name T115
Test name
Test status
Simulation time 34913159 ps
CPU time 0.82 seconds
Started Apr 02 01:36:10 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 215452 kb
Host smart-d82ba4d4-6a82-4baa-9d92-31c8bd89e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363689381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3363689381
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2255686746
Short name T568
Test name
Test status
Simulation time 21848923 ps
CPU time 0.98 seconds
Started Apr 02 01:36:03 PM PDT 24
Finished Apr 02 01:36:04 PM PDT 24
Peak memory 215288 kb
Host smart-7a00c3c2-a43c-4594-8e86-a3ff2d91a624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255686746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2255686746
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4260152877
Short name T594
Test name
Test status
Simulation time 534134270 ps
CPU time 2.15 seconds
Started Apr 02 01:36:06 PM PDT 24
Finished Apr 02 01:36:08 PM PDT 24
Peak memory 215280 kb
Host smart-2cd75167-b3b8-44b1-ae52-eb3d8973cb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260152877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4260152877
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.227785289
Short name T23
Test name
Test status
Simulation time 387820468339 ps
CPU time 1594.12 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 02:02:44 PM PDT 24
Peak memory 226328 kb
Host smart-50d4645c-5959-4803-800a-3efb569a776c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227785289 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.227785289
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2094691038
Short name T731
Test name
Test status
Simulation time 49804945 ps
CPU time 1.64 seconds
Started Apr 02 01:38:33 PM PDT 24
Finished Apr 02 01:38:35 PM PDT 24
Peak memory 218072 kb
Host smart-ae797317-9d3a-4564-b31f-6846401c0069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094691038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2094691038
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2322888854
Short name T712
Test name
Test status
Simulation time 73724253 ps
CPU time 1.01 seconds
Started Apr 02 01:38:39 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 216568 kb
Host smart-055a0312-e322-47e8-80ef-278f7545b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322888854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2322888854
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.906723148
Short name T711
Test name
Test status
Simulation time 131488716 ps
CPU time 3.27 seconds
Started Apr 02 01:38:36 PM PDT 24
Finished Apr 02 01:38:39 PM PDT 24
Peak memory 216900 kb
Host smart-96a5f009-a94e-408f-9051-c489e8b648d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906723148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.906723148
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3639646770
Short name T411
Test name
Test status
Simulation time 29403727 ps
CPU time 1.21 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:35 PM PDT 24
Peak memory 217560 kb
Host smart-a098d669-1a69-43ec-8a45-11b8835b02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639646770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3639646770
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2591033404
Short name T404
Test name
Test status
Simulation time 168989295 ps
CPU time 0.96 seconds
Started Apr 02 01:38:38 PM PDT 24
Finished Apr 02 01:38:39 PM PDT 24
Peak memory 216508 kb
Host smart-758d552b-072a-4508-8b14-7738f4118324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591033404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2591033404
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3768365327
Short name T675
Test name
Test status
Simulation time 93279568 ps
CPU time 1.15 seconds
Started Apr 02 01:38:35 PM PDT 24
Finished Apr 02 01:38:37 PM PDT 24
Peak memory 216576 kb
Host smart-58be36d9-fa2d-461d-b961-d99a29bd710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768365327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3768365327
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3543138702
Short name T391
Test name
Test status
Simulation time 28783430 ps
CPU time 1.23 seconds
Started Apr 02 01:38:39 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 219072 kb
Host smart-8d8ce5ad-ae0f-4c3d-91e0-ee7f2d48765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543138702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3543138702
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1115522680
Short name T709
Test name
Test status
Simulation time 53214598 ps
CPU time 1.17 seconds
Started Apr 02 01:38:35 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 219020 kb
Host smart-9acb9ef5-2146-4e1c-9155-357dfc570f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115522680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1115522680
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2307431595
Short name T601
Test name
Test status
Simulation time 253582486 ps
CPU time 1.36 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 01:36:11 PM PDT 24
Peak memory 215644 kb
Host smart-05e052bc-c96e-49e1-a3b8-061b246f07d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307431595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2307431595
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2466498336
Short name T668
Test name
Test status
Simulation time 16004267 ps
CPU time 0.93 seconds
Started Apr 02 01:36:11 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 205952 kb
Host smart-cfcd16b0-951a-4806-a812-0f4e94c2b854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466498336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2466498336
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2943797667
Short name T158
Test name
Test status
Simulation time 36374680 ps
CPU time 0.89 seconds
Started Apr 02 01:36:12 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 215944 kb
Host smart-2fd2958d-5278-4738-ba7a-ecbfe8281f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943797667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2943797667
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2219170624
Short name T733
Test name
Test status
Simulation time 35096452 ps
CPU time 0.96 seconds
Started Apr 02 01:36:15 PM PDT 24
Finished Apr 02 01:36:16 PM PDT 24
Peak memory 217660 kb
Host smart-f01cf104-894e-4fcf-9044-b90ee64a8bf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219170624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2219170624
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1706372334
Short name T96
Test name
Test status
Simulation time 19319616 ps
CPU time 1.11 seconds
Started Apr 02 01:36:10 PM PDT 24
Finished Apr 02 01:36:11 PM PDT 24
Peak memory 215304 kb
Host smart-8e223363-b613-4126-a3b5-8bee640728ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706372334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1706372334
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.255438070
Short name T801
Test name
Test status
Simulation time 36423587 ps
CPU time 1.31 seconds
Started Apr 02 01:36:11 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 215180 kb
Host smart-b8a9eec4-2580-49c4-b17e-c761690928d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255438070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.255438070
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2763990127
Short name T30
Test name
Test status
Simulation time 28220327 ps
CPU time 0.89 seconds
Started Apr 02 01:36:42 PM PDT 24
Finished Apr 02 01:36:44 PM PDT 24
Peak memory 215528 kb
Host smart-68fae9be-996f-41c9-bf09-885dbebf14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763990127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2763990127
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3686414458
Short name T638
Test name
Test status
Simulation time 18979186 ps
CPU time 1.05 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 01:36:10 PM PDT 24
Peak memory 215296 kb
Host smart-d3d86ff7-6da7-4b3d-b40b-bc1e58c310ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686414458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3686414458
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3095146009
Short name T749
Test name
Test status
Simulation time 106556993 ps
CPU time 1.23 seconds
Started Apr 02 01:36:09 PM PDT 24
Finished Apr 02 01:36:10 PM PDT 24
Peak memory 216480 kb
Host smart-c5a907a1-0bc0-47e2-b3d9-91843b5343f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095146009 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3095146009
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3542234063
Short name T666
Test name
Test status
Simulation time 18453970108 ps
CPU time 406.22 seconds
Started Apr 02 01:36:10 PM PDT 24
Finished Apr 02 01:42:58 PM PDT 24
Peak memory 217800 kb
Host smart-15fd9ca8-8bd9-4fc2-8fdc-e30d19eee591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542234063 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3542234063
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1071000042
Short name T36
Test name
Test status
Simulation time 39585454 ps
CPU time 1.72 seconds
Started Apr 02 01:38:39 PM PDT 24
Finished Apr 02 01:38:41 PM PDT 24
Peak memory 217848 kb
Host smart-de415a7a-bacb-4a64-a74d-fcfa099b9d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071000042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1071000042
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3774978693
Short name T295
Test name
Test status
Simulation time 33637098 ps
CPU time 1.42 seconds
Started Apr 02 01:38:35 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 217980 kb
Host smart-6013d7e3-0f84-4365-baa9-70bd11f73c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774978693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3774978693
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2954600014
Short name T370
Test name
Test status
Simulation time 288730196 ps
CPU time 1.14 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 216760 kb
Host smart-76547650-e640-4eb5-b9c1-8fa3ec2a6cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954600014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2954600014
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2227762883
Short name T632
Test name
Test status
Simulation time 47531219 ps
CPU time 1.65 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 218084 kb
Host smart-1cfe7313-f49b-4d6e-8269-f5ef4fb06b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227762883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2227762883
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1838960460
Short name T333
Test name
Test status
Simulation time 38677151 ps
CPU time 1.62 seconds
Started Apr 02 01:38:34 PM PDT 24
Finished Apr 02 01:38:36 PM PDT 24
Peak memory 217872 kb
Host smart-2418cefb-d48b-4c46-8c42-f77847412079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838960460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1838960460
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4293232613
Short name T296
Test name
Test status
Simulation time 82023998 ps
CPU time 2.8 seconds
Started Apr 02 01:38:36 PM PDT 24
Finished Apr 02 01:38:39 PM PDT 24
Peak memory 219352 kb
Host smart-5df404a7-8f0d-44e6-a441-4fe07436177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293232613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4293232613
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1018131285
Short name T34
Test name
Test status
Simulation time 110873642 ps
CPU time 1.83 seconds
Started Apr 02 01:38:38 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 218264 kb
Host smart-801994aa-92f9-4235-8c36-76bab9cd9737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018131285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1018131285
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.991998213
Short name T300
Test name
Test status
Simulation time 76062213 ps
CPU time 2.91 seconds
Started Apr 02 01:38:37 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 216732 kb
Host smart-58ec71bb-553d-40a4-a771-9e9e85915758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991998213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.991998213
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1550149685
Short name T773
Test name
Test status
Simulation time 125061861 ps
CPU time 1.21 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 216768 kb
Host smart-502e86b3-62d3-4a09-9330-1ff9e654fcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550149685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1550149685
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2005452637
Short name T62
Test name
Test status
Simulation time 95060832 ps
CPU time 1.2 seconds
Started Apr 02 01:36:18 PM PDT 24
Finished Apr 02 01:36:19 PM PDT 24
Peak memory 215580 kb
Host smart-5dd0ca45-be7a-42fb-adbb-e8f892d8f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005452637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2005452637
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.507446804
Short name T697
Test name
Test status
Simulation time 24679897 ps
CPU time 0.88 seconds
Started Apr 02 01:36:12 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 206580 kb
Host smart-746ff66f-07ab-4354-87eb-39a6b8b37a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507446804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.507446804
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.314988793
Short name T658
Test name
Test status
Simulation time 57280627 ps
CPU time 1.05 seconds
Started Apr 02 01:36:12 PM PDT 24
Finished Apr 02 01:36:14 PM PDT 24
Peak memory 217684 kb
Host smart-b4d1258f-3be3-49a4-a501-56500b473a3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314988793 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.314988793
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2134386290
Short name T86
Test name
Test status
Simulation time 21785696 ps
CPU time 0.95 seconds
Started Apr 02 01:36:12 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 218044 kb
Host smart-87cdb675-1e69-4402-9682-1642396a1d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134386290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2134386290
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4210066533
Short name T548
Test name
Test status
Simulation time 200179965 ps
CPU time 1.13 seconds
Started Apr 02 01:36:14 PM PDT 24
Finished Apr 02 01:36:16 PM PDT 24
Peak memory 216732 kb
Host smart-7b099f3b-c15a-48fe-8443-e5a4f334a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210066533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4210066533
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3420094507
Short name T481
Test name
Test status
Simulation time 37541474 ps
CPU time 1.02 seconds
Started Apr 02 01:36:13 PM PDT 24
Finished Apr 02 01:36:14 PM PDT 24
Peak memory 223860 kb
Host smart-dee29bfc-26bc-4a3f-ba74-b035088c16cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420094507 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3420094507
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1959629270
Short name T48
Test name
Test status
Simulation time 27896442 ps
CPU time 0.86 seconds
Started Apr 02 01:36:12 PM PDT 24
Finished Apr 02 01:36:13 PM PDT 24
Peak memory 215220 kb
Host smart-ea436599-f410-4caf-835e-b31703be7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959629270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1959629270
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.884742695
Short name T323
Test name
Test status
Simulation time 68657110 ps
CPU time 1.88 seconds
Started Apr 02 01:36:11 PM PDT 24
Finished Apr 02 01:36:14 PM PDT 24
Peak memory 216380 kb
Host smart-f61295d7-1e74-4774-ace6-69cf21b7d4c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884742695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.884742695
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1625389989
Short name T454
Test name
Test status
Simulation time 7250184145 ps
CPU time 111.56 seconds
Started Apr 02 01:36:14 PM PDT 24
Finished Apr 02 01:38:06 PM PDT 24
Peak memory 219440 kb
Host smart-ee48a7ec-c69a-4f73-bdf7-fb698b23d585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625389989 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1625389989
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.495106872
Short name T245
Test name
Test status
Simulation time 76366808 ps
CPU time 1.13 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 216616 kb
Host smart-58af57ae-bc39-45a9-90ee-e18bfb38a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495106872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.495106872
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.66917073
Short name T478
Test name
Test status
Simulation time 30688813 ps
CPU time 1.33 seconds
Started Apr 02 01:38:37 PM PDT 24
Finished Apr 02 01:38:38 PM PDT 24
Peak memory 216508 kb
Host smart-a602ef5f-e06f-4e65-b595-21a1b41ec4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66917073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.66917073
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.792666522
Short name T382
Test name
Test status
Simulation time 34388869 ps
CPU time 1.12 seconds
Started Apr 02 01:38:37 PM PDT 24
Finished Apr 02 01:38:38 PM PDT 24
Peak memory 217052 kb
Host smart-1964aab1-fecd-460e-a7b2-8de1eba206cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792666522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.792666522
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3929049059
Short name T602
Test name
Test status
Simulation time 40956995 ps
CPU time 1.45 seconds
Started Apr 02 01:38:38 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 218892 kb
Host smart-c8b986bf-fadd-4d83-a333-e554876690c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929049059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3929049059
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3098979616
Short name T812
Test name
Test status
Simulation time 33437516 ps
CPU time 1.31 seconds
Started Apr 02 01:38:36 PM PDT 24
Finished Apr 02 01:38:38 PM PDT 24
Peak memory 218880 kb
Host smart-b88a36c2-c072-4939-9cf4-44aa3d2c8093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098979616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3098979616
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3228240325
Short name T464
Test name
Test status
Simulation time 155112440 ps
CPU time 1.57 seconds
Started Apr 02 01:38:41 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 218424 kb
Host smart-e725d77c-8d4f-4b95-9ebb-9082a01d4a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228240325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3228240325
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.241269299
Short name T537
Test name
Test status
Simulation time 55116336 ps
CPU time 1.28 seconds
Started Apr 02 01:38:37 PM PDT 24
Finished Apr 02 01:38:38 PM PDT 24
Peak memory 216844 kb
Host smart-9378be10-7249-4a21-b613-0839bbcd23cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241269299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.241269299
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4059939463
Short name T335
Test name
Test status
Simulation time 42694795 ps
CPU time 1.56 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 217700 kb
Host smart-d92c30c0-31a8-4d89-8bfb-0b2ac098253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059939463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4059939463
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3798655864
Short name T368
Test name
Test status
Simulation time 77513893 ps
CPU time 1.24 seconds
Started Apr 02 01:38:41 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 218956 kb
Host smart-748b1f8d-d4d7-48ed-8226-9dcd8d0f3db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798655864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3798655864
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.630010028
Short name T577
Test name
Test status
Simulation time 38166969 ps
CPU time 1.41 seconds
Started Apr 02 01:38:38 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 216472 kb
Host smart-10299555-765f-49ae-9ce0-4eaf9d79d8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630010028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.630010028
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.71814176
Short name T405
Test name
Test status
Simulation time 86452379 ps
CPU time 1.42 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 206144 kb
Host smart-94773428-94ac-4f24-ac40-cb4b73fc99ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71814176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.71814176
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2032495725
Short name T97
Test name
Test status
Simulation time 17215474 ps
CPU time 0.84 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 215852 kb
Host smart-e9f8a22f-08a3-4fdd-8344-c5e5fa859322
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032495725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2032495725
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2719181836
Short name T172
Test name
Test status
Simulation time 84740255 ps
CPU time 1.04 seconds
Started Apr 02 01:36:19 PM PDT 24
Finished Apr 02 01:36:21 PM PDT 24
Peak memory 216568 kb
Host smart-fca8cce9-29c1-43d6-9251-0c08d0518e17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719181836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2719181836
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3930752367
Short name T614
Test name
Test status
Simulation time 19352429 ps
CPU time 1.08 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 218060 kb
Host smart-4cabf9d4-e7f3-432b-ac62-f331871dba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930752367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3930752367
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2682045870
Short name T681
Test name
Test status
Simulation time 63310045 ps
CPU time 1.15 seconds
Started Apr 02 01:36:14 PM PDT 24
Finished Apr 02 01:36:15 PM PDT 24
Peak memory 216456 kb
Host smart-b5350ed1-e527-4a06-b4bc-bcf478bb743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682045870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2682045870
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3487334191
Short name T569
Test name
Test status
Simulation time 20983541 ps
CPU time 1.1 seconds
Started Apr 02 01:36:18 PM PDT 24
Finished Apr 02 01:36:19 PM PDT 24
Peak memory 215820 kb
Host smart-1642b827-8e63-4808-8862-92576ce29f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487334191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3487334191
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2296780865
Short name T797
Test name
Test status
Simulation time 44545538 ps
CPU time 0.88 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 215140 kb
Host smart-a0377bb9-38e9-40cc-b3db-a25588de539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296780865 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2296780865
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2352438519
Short name T527
Test name
Test status
Simulation time 172388305 ps
CPU time 2.33 seconds
Started Apr 02 01:36:15 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 215140 kb
Host smart-4f67b5ec-7792-496f-b7ff-c661b1684622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352438519 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2352438519
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1574258362
Short name T496
Test name
Test status
Simulation time 51433461631 ps
CPU time 1306.48 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:58:03 PM PDT 24
Peak memory 222944 kb
Host smart-06c2246c-7f52-4d0e-a545-4b03dd235690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574258362 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1574258362
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3336552246
Short name T517
Test name
Test status
Simulation time 29093620 ps
CPU time 1.29 seconds
Started Apr 02 01:38:37 PM PDT 24
Finished Apr 02 01:38:39 PM PDT 24
Peak memory 216864 kb
Host smart-563c9178-8e22-4a96-bc91-c00e3e54f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336552246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3336552246
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3921959133
Short name T584
Test name
Test status
Simulation time 107193713 ps
CPU time 1.77 seconds
Started Apr 02 01:38:38 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 217896 kb
Host smart-4773c5a2-154c-469a-930d-5e63e66906f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921959133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3921959133
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.231747016
Short name T272
Test name
Test status
Simulation time 62083303 ps
CPU time 1.79 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 219480 kb
Host smart-747eee9f-201b-45f9-9e58-ebdf5161a883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231747016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.231747016
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3444446147
Short name T586
Test name
Test status
Simulation time 74173213 ps
CPU time 1.23 seconds
Started Apr 02 01:38:41 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 216360 kb
Host smart-4d911180-2eeb-4db2-8fd0-c5fe3374f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444446147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3444446147
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2249263506
Short name T806
Test name
Test status
Simulation time 27842493 ps
CPU time 1.29 seconds
Started Apr 02 01:38:37 PM PDT 24
Finished Apr 02 01:38:39 PM PDT 24
Peak memory 216988 kb
Host smart-f04b0233-2161-4cd6-b1e3-1fca40da8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249263506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2249263506
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1562827845
Short name T495
Test name
Test status
Simulation time 30515412 ps
CPU time 1.32 seconds
Started Apr 02 01:38:38 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 219116 kb
Host smart-986d0c9f-d874-4b15-aede-af94555c04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562827845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1562827845
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.514741414
Short name T688
Test name
Test status
Simulation time 39186963 ps
CPU time 1.69 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 216636 kb
Host smart-395d86d5-fa29-47f0-b4e2-7e671ebf688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514741414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.514741414
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.785239060
Short name T706
Test name
Test status
Simulation time 45478698 ps
CPU time 1.6 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:48 PM PDT 24
Peak memory 217860 kb
Host smart-b664aeb0-31d7-456a-9b57-a8b553b73f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785239060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.785239060
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3666351598
Short name T604
Test name
Test status
Simulation time 31159340 ps
CPU time 1.26 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:48 PM PDT 24
Peak memory 217852 kb
Host smart-e8d2a23e-04b8-49df-a7d0-3fa00052a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666351598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3666351598
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.185603170
Short name T308
Test name
Test status
Simulation time 42903048 ps
CPU time 1.34 seconds
Started Apr 02 01:38:42 PM PDT 24
Finished Apr 02 01:38:43 PM PDT 24
Peak memory 217836 kb
Host smart-f771caf7-a845-4fa0-b5ce-3561148704d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185603170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.185603170
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4042663741
Short name T271
Test name
Test status
Simulation time 41975494 ps
CPU time 1.16 seconds
Started Apr 02 01:36:17 PM PDT 24
Finished Apr 02 01:36:18 PM PDT 24
Peak memory 215580 kb
Host smart-7eaf6618-e745-479f-9e9d-352f9e7ec910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042663741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4042663741
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3777709587
Short name T362
Test name
Test status
Simulation time 14669961 ps
CPU time 0.92 seconds
Started Apr 02 01:36:15 PM PDT 24
Finished Apr 02 01:36:16 PM PDT 24
Peak memory 206812 kb
Host smart-7db31174-1d8b-41b0-90b0-7a81fe46f3dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777709587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3777709587
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3739287058
Short name T176
Test name
Test status
Simulation time 13675152 ps
CPU time 0.92 seconds
Started Apr 02 01:36:17 PM PDT 24
Finished Apr 02 01:36:18 PM PDT 24
Peak memory 215884 kb
Host smart-3f5f77f5-64de-4536-8f83-e22c14549210
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739287058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3739287058
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1920184670
Short name T228
Test name
Test status
Simulation time 47336810 ps
CPU time 1.06 seconds
Started Apr 02 01:36:19 PM PDT 24
Finished Apr 02 01:36:21 PM PDT 24
Peak memory 219200 kb
Host smart-45615561-c528-4763-b50e-131d4390a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920184670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1920184670
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3471036952
Short name T533
Test name
Test status
Simulation time 58161572 ps
CPU time 1.44 seconds
Started Apr 02 01:36:17 PM PDT 24
Finished Apr 02 01:36:18 PM PDT 24
Peak memory 215288 kb
Host smart-1af6ed23-388c-461f-9528-ad1efb92c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471036952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3471036952
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2570891986
Short name T33
Test name
Test status
Simulation time 40298367 ps
CPU time 1.02 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 223984 kb
Host smart-cb3bab07-72ab-4a37-b39b-d9dd48ba2f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570891986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2570891986
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4178602947
Short name T530
Test name
Test status
Simulation time 17723812 ps
CPU time 1.03 seconds
Started Apr 02 01:36:16 PM PDT 24
Finished Apr 02 01:36:17 PM PDT 24
Peak memory 215108 kb
Host smart-eb73c068-5f9e-4dea-b72b-30f94dfddc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178602947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4178602947
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2151775127
Short name T820
Test name
Test status
Simulation time 326878005 ps
CPU time 4.04 seconds
Started Apr 02 01:36:20 PM PDT 24
Finished Apr 02 01:36:24 PM PDT 24
Peak memory 215268 kb
Host smart-3bf3ed1e-bed0-4440-83d1-d480fd72fe91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151775127 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2151775127
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1322099235
Short name T24
Test name
Test status
Simulation time 57180545221 ps
CPU time 1243.21 seconds
Started Apr 02 01:36:18 PM PDT 24
Finished Apr 02 01:57:02 PM PDT 24
Peak memory 219972 kb
Host smart-4d245796-e254-4746-a76a-ce7c36b3ce67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322099235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1322099235
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2181241499
Short name T758
Test name
Test status
Simulation time 32338107 ps
CPU time 1.24 seconds
Started Apr 02 01:38:41 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 218008 kb
Host smart-697e590c-5c1e-4423-b977-e4129a36b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181241499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2181241499
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2979971495
Short name T347
Test name
Test status
Simulation time 76914220 ps
CPU time 1.22 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 215336 kb
Host smart-95c46bd9-c318-42cc-8302-cf84f579f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979971495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2979971495
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2769897961
Short name T301
Test name
Test status
Simulation time 40710965 ps
CPU time 1.61 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 217904 kb
Host smart-41755658-0e45-4cc8-89db-923261898579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769897961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2769897961
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2059871442
Short name T583
Test name
Test status
Simulation time 145178818 ps
CPU time 1.12 seconds
Started Apr 02 01:38:39 PM PDT 24
Finished Apr 02 01:38:40 PM PDT 24
Peak memory 215260 kb
Host smart-46d0b7ae-426e-415f-abdc-6440b96dcb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059871442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2059871442
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3101578078
Short name T803
Test name
Test status
Simulation time 46837376 ps
CPU time 1.6 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 217984 kb
Host smart-37c0b2ae-b7fd-4443-9f9b-c47492565167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101578078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3101578078
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1040842566
Short name T324
Test name
Test status
Simulation time 32396913 ps
CPU time 0.97 seconds
Started Apr 02 01:38:42 PM PDT 24
Finished Apr 02 01:38:43 PM PDT 24
Peak memory 216720 kb
Host smart-e2d963b8-75f4-482f-b615-50d87f4f5048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040842566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1040842566
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2128041466
Short name T684
Test name
Test status
Simulation time 156510407 ps
CPU time 3.48 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:43 PM PDT 24
Peak memory 218964 kb
Host smart-e98f5962-7f91-4ec7-81f7-ccb953296691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128041466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2128041466
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3881311704
Short name T808
Test name
Test status
Simulation time 50856709 ps
CPU time 1.53 seconds
Started Apr 02 01:38:39 PM PDT 24
Finished Apr 02 01:38:41 PM PDT 24
Peak memory 217852 kb
Host smart-a7c56de2-1e9f-4a2f-8773-4d7c5e4e904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881311704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3881311704
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1088448359
Short name T743
Test name
Test status
Simulation time 130007183 ps
CPU time 1.56 seconds
Started Apr 02 01:38:40 PM PDT 24
Finished Apr 02 01:38:42 PM PDT 24
Peak memory 218012 kb
Host smart-8973f177-a043-4c0c-9415-b41ee81748e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088448359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1088448359
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3021356189
Short name T403
Test name
Test status
Simulation time 136941440 ps
CPU time 1.76 seconds
Started Apr 02 01:38:41 PM PDT 24
Finished Apr 02 01:38:43 PM PDT 24
Peak memory 216952 kb
Host smart-84159fee-e089-402f-bce4-2ec71fa7ca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021356189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3021356189
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.934280544
Short name T263
Test name
Test status
Simulation time 98057773 ps
CPU time 1.02 seconds
Started Apr 02 01:36:18 PM PDT 24
Finished Apr 02 01:36:19 PM PDT 24
Peak memory 215600 kb
Host smart-b52e160d-d420-418d-bfa1-f8b822ec3569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934280544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.934280544
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1591876861
Short name T635
Test name
Test status
Simulation time 95674542 ps
CPU time 0.9 seconds
Started Apr 02 01:36:19 PM PDT 24
Finished Apr 02 01:36:20 PM PDT 24
Peak memory 205968 kb
Host smart-eae927d6-204f-440c-aa2f-71c08349d3e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591876861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1591876861
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.514123956
Short name T582
Test name
Test status
Simulation time 16402311 ps
CPU time 0.86 seconds
Started Apr 02 01:36:18 PM PDT 24
Finished Apr 02 01:36:19 PM PDT 24
Peak memory 215460 kb
Host smart-204e0ada-a380-4a32-a779-1dca0472e619
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514123956 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.514123956
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1111536713
Short name T171
Test name
Test status
Simulation time 27842935 ps
CPU time 1.09 seconds
Started Apr 02 01:36:25 PM PDT 24
Finished Apr 02 01:36:26 PM PDT 24
Peak memory 216596 kb
Host smart-d7bf651b-6523-4cbd-aa9c-e621624f7bef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111536713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1111536713
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1033070821
Short name T59
Test name
Test status
Simulation time 25333339 ps
CPU time 0.98 seconds
Started Apr 02 01:36:21 PM PDT 24
Finished Apr 02 01:36:22 PM PDT 24
Peak memory 216732 kb
Host smart-3750de66-4662-488e-9469-22f1d703bdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033070821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1033070821
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4186232953
Short name T288
Test name
Test status
Simulation time 27687463 ps
CPU time 1.19 seconds
Started Apr 02 01:36:19 PM PDT 24
Finished Apr 02 01:36:20 PM PDT 24
Peak memory 217784 kb
Host smart-431d7d1e-754b-42d6-867a-7e3ea2b36a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186232953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4186232953
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4134055938
Short name T407
Test name
Test status
Simulation time 30105678 ps
CPU time 0.88 seconds
Started Apr 02 01:36:20 PM PDT 24
Finished Apr 02 01:36:21 PM PDT 24
Peak memory 215396 kb
Host smart-b79462c5-a9e3-4f0f-8c9a-1c3c28da1f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134055938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4134055938
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1761075500
Short name T328
Test name
Test status
Simulation time 16678821 ps
CPU time 0.97 seconds
Started Apr 02 01:36:17 PM PDT 24
Finished Apr 02 01:36:18 PM PDT 24
Peak memory 215260 kb
Host smart-947e18b7-3954-48a9-9352-d5600cb47b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761075500 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1761075500
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3475771021
Short name T649
Test name
Test status
Simulation time 60234958 ps
CPU time 1.33 seconds
Started Apr 02 01:36:21 PM PDT 24
Finished Apr 02 01:36:22 PM PDT 24
Peak memory 218684 kb
Host smart-a550a3a1-5b99-4374-965b-dce1ac782c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475771021 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3475771021
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.963421813
Short name T703
Test name
Test status
Simulation time 65053188618 ps
CPU time 357.12 seconds
Started Apr 02 01:36:18 PM PDT 24
Finished Apr 02 01:42:16 PM PDT 24
Peak memory 223720 kb
Host smart-31c64de9-801b-465e-8d34-fb88bd792926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963421813 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.963421813
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.64772282
Short name T753
Test name
Test status
Simulation time 83582720 ps
CPU time 1.41 seconds
Started Apr 02 01:38:45 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 218396 kb
Host smart-37da87d4-37cb-4c25-b057-dcbec3ceefe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64772282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.64772282
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4265881688
Short name T406
Test name
Test status
Simulation time 43385273 ps
CPU time 1.72 seconds
Started Apr 02 01:38:39 PM PDT 24
Finished Apr 02 01:38:41 PM PDT 24
Peak memory 216796 kb
Host smart-cfe573a2-f548-4d3a-beda-8b487ac5f7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265881688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4265881688
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3259963280
Short name T318
Test name
Test status
Simulation time 98833160 ps
CPU time 2.13 seconds
Started Apr 02 01:38:45 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 216932 kb
Host smart-7f0ec14e-6571-44dd-8791-fc58cc648f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259963280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3259963280
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3733432219
Short name T550
Test name
Test status
Simulation time 25993879 ps
CPU time 1.14 seconds
Started Apr 02 01:38:42 PM PDT 24
Finished Apr 02 01:38:43 PM PDT 24
Peak memory 219332 kb
Host smart-8c5a185b-b1e9-4d28-bb33-1fa2fafb3fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733432219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3733432219
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2742323023
Short name T737
Test name
Test status
Simulation time 103700935 ps
CPU time 1.37 seconds
Started Apr 02 01:38:43 PM PDT 24
Finished Apr 02 01:38:45 PM PDT 24
Peak memory 216804 kb
Host smart-f6dee6e1-7caf-458e-a607-f0b5f29de0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742323023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2742323023
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1571124615
Short name T282
Test name
Test status
Simulation time 46699126 ps
CPU time 1.29 seconds
Started Apr 02 01:38:47 PM PDT 24
Finished Apr 02 01:38:50 PM PDT 24
Peak memory 217920 kb
Host smart-580315e3-ac90-48f8-a307-1306a5fe6321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571124615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1571124615
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1451053825
Short name T456
Test name
Test status
Simulation time 67792021 ps
CPU time 1.75 seconds
Started Apr 02 01:38:50 PM PDT 24
Finished Apr 02 01:38:52 PM PDT 24
Peak memory 218100 kb
Host smart-76e65de6-54fb-4a41-8994-865f4ceffaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451053825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1451053825
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1540076525
Short name T641
Test name
Test status
Simulation time 32952188 ps
CPU time 1.35 seconds
Started Apr 02 01:38:44 PM PDT 24
Finished Apr 02 01:38:46 PM PDT 24
Peak memory 217808 kb
Host smart-af06112d-adcd-47aa-ba88-942d59d7432c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540076525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1540076525
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3156310653
Short name T226
Test name
Test status
Simulation time 128796220 ps
CPU time 1.65 seconds
Started Apr 02 01:38:43 PM PDT 24
Finished Apr 02 01:38:45 PM PDT 24
Peak memory 218044 kb
Host smart-ccd886d2-4c94-447c-b4c7-e9a0c693287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156310653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3156310653
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1685484516
Short name T225
Test name
Test status
Simulation time 89707099 ps
CPU time 1.77 seconds
Started Apr 02 01:38:47 PM PDT 24
Finished Apr 02 01:38:51 PM PDT 24
Peak memory 218168 kb
Host smart-dc807b8f-2fa3-42e3-928f-588615e5f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685484516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1685484516
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.746420526
Short name T815
Test name
Test status
Simulation time 41505916 ps
CPU time 1.19 seconds
Started Apr 02 01:36:23 PM PDT 24
Finished Apr 02 01:36:26 PM PDT 24
Peak memory 215624 kb
Host smart-2d7c3233-4858-414a-bd6a-492532bfae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746420526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.746420526
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.947918109
Short name T814
Test name
Test status
Simulation time 25743273 ps
CPU time 0.9 seconds
Started Apr 02 01:36:23 PM PDT 24
Finished Apr 02 01:36:24 PM PDT 24
Peak memory 206528 kb
Host smart-66ed0503-a102-4fe2-8201-a68330c37401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947918109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.947918109
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3034716452
Short name T663
Test name
Test status
Simulation time 24255432 ps
CPU time 0.9 seconds
Started Apr 02 01:36:24 PM PDT 24
Finished Apr 02 01:36:25 PM PDT 24
Peak memory 215696 kb
Host smart-ec3fb001-430e-4243-9fa4-d13d752b2e7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034716452 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3034716452
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2863196035
Short name T56
Test name
Test status
Simulation time 24527704 ps
CPU time 1 seconds
Started Apr 02 01:36:24 PM PDT 24
Finished Apr 02 01:36:25 PM PDT 24
Peak memory 219044 kb
Host smart-a86a52e2-358b-4547-b23b-22299330c939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863196035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2863196035
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.635998907
Short name T256
Test name
Test status
Simulation time 99760036 ps
CPU time 1.46 seconds
Started Apr 02 01:36:20 PM PDT 24
Finished Apr 02 01:36:21 PM PDT 24
Peak memory 218204 kb
Host smart-add8836c-4c0b-4828-b690-73a8b1de6ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635998907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.635998907
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.2348255535
Short name T793
Test name
Test status
Simulation time 113703740 ps
CPU time 0.85 seconds
Started Apr 02 01:36:19 PM PDT 24
Finished Apr 02 01:36:20 PM PDT 24
Peak memory 215324 kb
Host smart-6efbf81f-8017-44f9-aea2-b9fca8efd87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348255535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2348255535
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3305714608
Short name T727
Test name
Test status
Simulation time 671310520 ps
CPU time 3.94 seconds
Started Apr 02 01:36:19 PM PDT 24
Finished Apr 02 01:36:23 PM PDT 24
Peak memory 215276 kb
Host smart-fdca1e2f-2d9e-4241-b82f-ea5500b3f7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305714608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3305714608
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3388990321
Short name T184
Test name
Test status
Simulation time 124080471138 ps
CPU time 684.68 seconds
Started Apr 02 01:36:25 PM PDT 24
Finished Apr 02 01:47:50 PM PDT 24
Peak memory 219148 kb
Host smart-3d9bfc84-7265-46b4-8ebc-781f6699a117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388990321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3388990321
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.181805660
Short name T520
Test name
Test status
Simulation time 54918742 ps
CPU time 0.95 seconds
Started Apr 02 01:38:44 PM PDT 24
Finished Apr 02 01:38:45 PM PDT 24
Peak memory 216456 kb
Host smart-0e0c8e4b-fd0f-43cb-8d1d-6a73af66ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181805660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.181805660
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1982295153
Short name T351
Test name
Test status
Simulation time 33834066 ps
CPU time 1.33 seconds
Started Apr 02 01:38:45 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 217804 kb
Host smart-fd458e7c-6266-4fa0-9ba0-11e0763398bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982295153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1982295153
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1347329824
Short name T37
Test name
Test status
Simulation time 104832395 ps
CPU time 1.38 seconds
Started Apr 02 01:38:45 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 218212 kb
Host smart-a72e506f-c99e-4e2e-bcb2-4af62e7ad571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347329824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1347329824
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1218051963
Short name T477
Test name
Test status
Simulation time 37257841 ps
CPU time 1.12 seconds
Started Apr 02 01:38:45 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 216620 kb
Host smart-e4aa1f6b-9b2f-4a4e-a29c-2b6a64bac1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218051963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1218051963
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.241165204
Short name T419
Test name
Test status
Simulation time 93370613 ps
CPU time 1.15 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:48 PM PDT 24
Peak memory 216692 kb
Host smart-a4206b87-fa40-4ee0-a3d8-3c7ac27ca9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241165204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.241165204
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3615372282
Short name T777
Test name
Test status
Simulation time 105791990 ps
CPU time 1.54 seconds
Started Apr 02 01:38:49 PM PDT 24
Finished Apr 02 01:38:50 PM PDT 24
Peak memory 218244 kb
Host smart-57729315-aba1-4abe-bc9c-8942ee9692b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615372282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3615372282
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1950349000
Short name T585
Test name
Test status
Simulation time 51918561 ps
CPU time 2.04 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:49 PM PDT 24
Peak memory 219492 kb
Host smart-11d5916f-bfbb-4042-9a30-3ac0a230fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950349000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1950349000
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1539356423
Short name T35
Test name
Test status
Simulation time 50382557 ps
CPU time 2.12 seconds
Started Apr 02 01:38:47 PM PDT 24
Finished Apr 02 01:38:51 PM PDT 24
Peak memory 219248 kb
Host smart-e6e11140-0739-4966-867e-1473b400251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539356423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1539356423
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1561069384
Short name T316
Test name
Test status
Simulation time 24834682 ps
CPU time 1.02 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:47 PM PDT 24
Peak memory 216912 kb
Host smart-86775be9-9865-42cb-b4c1-47d2e5db5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561069384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1561069384
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1674316602
Short name T258
Test name
Test status
Simulation time 38061500 ps
CPU time 1.12 seconds
Started Apr 02 01:36:28 PM PDT 24
Finished Apr 02 01:36:29 PM PDT 24
Peak memory 215620 kb
Host smart-53b01863-60da-4ce1-8e06-b15dc667fdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674316602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1674316602
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4286841405
Short name T664
Test name
Test status
Simulation time 21381895 ps
CPU time 0.82 seconds
Started Apr 02 01:36:28 PM PDT 24
Finished Apr 02 01:36:29 PM PDT 24
Peak memory 205936 kb
Host smart-7062e98d-7a97-4c5d-844b-eeb697fb403b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286841405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4286841405
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1214936450
Short name T88
Test name
Test status
Simulation time 14214352 ps
CPU time 0.91 seconds
Started Apr 02 01:36:31 PM PDT 24
Finished Apr 02 01:36:33 PM PDT 24
Peak memory 215604 kb
Host smart-fe2ce302-3826-49b3-8d7e-3ce775bff29d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214936450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1214936450
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.1716835319
Short name T825
Test name
Test status
Simulation time 58262967 ps
CPU time 1.06 seconds
Started Apr 02 01:36:33 PM PDT 24
Finished Apr 02 01:36:35 PM PDT 24
Peak memory 220348 kb
Host smart-0eaf3ede-bf52-4e10-bf76-d4af76695e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716835319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1716835319
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1581471911
Short name T443
Test name
Test status
Simulation time 130696919 ps
CPU time 1.16 seconds
Started Apr 02 01:36:23 PM PDT 24
Finished Apr 02 01:36:24 PM PDT 24
Peak memory 216616 kb
Host smart-e6d5a3bd-a803-4c9c-b830-678d5343ab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581471911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1581471911
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3658572573
Short name T325
Test name
Test status
Simulation time 27747900 ps
CPU time 1.01 seconds
Started Apr 02 01:36:27 PM PDT 24
Finished Apr 02 01:36:28 PM PDT 24
Peak memory 215564 kb
Host smart-5c724533-d0c5-43df-a2a6-cf8af01b2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658572573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3658572573
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3306331654
Short name T47
Test name
Test status
Simulation time 22114151 ps
CPU time 0.98 seconds
Started Apr 02 01:36:23 PM PDT 24
Finished Apr 02 01:36:24 PM PDT 24
Peak memory 215244 kb
Host smart-ce6b5f5a-0c5a-41fd-938c-61354c25a4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306331654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3306331654
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1581378385
Short name T715
Test name
Test status
Simulation time 190356919 ps
CPU time 4.17 seconds
Started Apr 02 01:36:27 PM PDT 24
Finished Apr 02 01:36:31 PM PDT 24
Peak memory 216468 kb
Host smart-4e3b1051-77be-4ff6-bfdb-045308d78dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581378385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1581378385
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3125408177
Short name T796
Test name
Test status
Simulation time 50872412584 ps
CPU time 1163.62 seconds
Started Apr 02 01:36:27 PM PDT 24
Finished Apr 02 01:55:51 PM PDT 24
Peak memory 220140 kb
Host smart-ca7db839-0b7a-4310-8285-87e71e3fd213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125408177 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3125408177
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1847603333
Short name T410
Test name
Test status
Simulation time 45723888 ps
CPU time 1.34 seconds
Started Apr 02 01:38:48 PM PDT 24
Finished Apr 02 01:38:50 PM PDT 24
Peak memory 216608 kb
Host smart-4a89367f-2ef3-4af5-a687-6975ba0e2592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847603333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1847603333
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2040560707
Short name T832
Test name
Test status
Simulation time 70991359 ps
CPU time 1.33 seconds
Started Apr 02 01:38:46 PM PDT 24
Finished Apr 02 01:38:48 PM PDT 24
Peak memory 217924 kb
Host smart-25e4dd51-ddff-4896-8ccc-e08a8ec4946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040560707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2040560707
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1016601712
Short name T170
Test name
Test status
Simulation time 138275745 ps
CPU time 1.2 seconds
Started Apr 02 01:38:52 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 216636 kb
Host smart-4ef8baff-cfa6-4e4e-a99d-d1622a0e9063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016601712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1016601712
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1928351769
Short name T338
Test name
Test status
Simulation time 70224149 ps
CPU time 1.34 seconds
Started Apr 02 01:38:50 PM PDT 24
Finished Apr 02 01:38:51 PM PDT 24
Peak memory 218612 kb
Host smart-1276432d-676a-4eaa-be83-793e9c684744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928351769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1928351769
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1659785006
Short name T416
Test name
Test status
Simulation time 35378030 ps
CPU time 1.31 seconds
Started Apr 02 01:38:49 PM PDT 24
Finished Apr 02 01:38:51 PM PDT 24
Peak memory 216464 kb
Host smart-c58c6ca7-ee8b-463c-b24e-bf30a9c34ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659785006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1659785006
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4250970542
Short name T440
Test name
Test status
Simulation time 53347115 ps
CPU time 1.66 seconds
Started Apr 02 01:38:50 PM PDT 24
Finished Apr 02 01:38:52 PM PDT 24
Peak memory 218052 kb
Host smart-de88c61f-f810-4e2a-86a2-64bd7482f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250970542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4250970542
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2140807329
Short name T474
Test name
Test status
Simulation time 200954318 ps
CPU time 2.77 seconds
Started Apr 02 01:38:51 PM PDT 24
Finished Apr 02 01:38:54 PM PDT 24
Peak memory 216736 kb
Host smart-3f1d0575-0905-487a-891d-30363c77561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140807329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2140807329
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.199502549
Short name T274
Test name
Test status
Simulation time 55018090 ps
CPU time 1.41 seconds
Started Apr 02 01:38:54 PM PDT 24
Finished Apr 02 01:38:55 PM PDT 24
Peak memory 217768 kb
Host smart-89adeec3-79d7-461a-96b5-c7b6d93acb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199502549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.199502549
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3264192539
Short name T579
Test name
Test status
Simulation time 46266536 ps
CPU time 1.53 seconds
Started Apr 02 01:38:51 PM PDT 24
Finished Apr 02 01:38:53 PM PDT 24
Peak memory 216688 kb
Host smart-71bbdced-3084-4116-b4e6-42806b568589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264192539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3264192539
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1985771275
Short name T51
Test name
Test status
Simulation time 40635816 ps
CPU time 1.21 seconds
Started Apr 02 01:34:39 PM PDT 24
Finished Apr 02 01:34:41 PM PDT 24
Peak memory 215556 kb
Host smart-0effb35a-7107-4f83-aaf3-d86a57ce12de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985771275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1985771275
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2357149521
Short name T756
Test name
Test status
Simulation time 23620514 ps
CPU time 0.86 seconds
Started Apr 02 01:34:45 PM PDT 24
Finished Apr 02 01:34:48 PM PDT 24
Peak memory 205968 kb
Host smart-d5b7c770-2286-444b-9e4e-9d1cb7b5a070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357149521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2357149521
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2842996468
Short name T150
Test name
Test status
Simulation time 55465239 ps
CPU time 0.81 seconds
Started Apr 02 01:34:38 PM PDT 24
Finished Apr 02 01:34:41 PM PDT 24
Peak memory 215812 kb
Host smart-8ae9988c-88c4-46f6-95b9-c4f80b1f4794
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842996468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2842996468
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3175304219
Short name T821
Test name
Test status
Simulation time 154026868 ps
CPU time 1.08 seconds
Started Apr 02 01:34:42 PM PDT 24
Finished Apr 02 01:34:44 PM PDT 24
Peak memory 216332 kb
Host smart-e6b8a313-fc46-44b9-8835-c9e605ec6f8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175304219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3175304219
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2521718987
Short name T19
Test name
Test status
Simulation time 21806640 ps
CPU time 1 seconds
Started Apr 02 01:34:40 PM PDT 24
Finished Apr 02 01:34:41 PM PDT 24
Peak memory 218044 kb
Host smart-6199ebe3-9e38-4357-a916-2848a4cb440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521718987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2521718987
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.201649577
Short name T134
Test name
Test status
Simulation time 52994353 ps
CPU time 1.15 seconds
Started Apr 02 01:34:33 PM PDT 24
Finished Apr 02 01:34:34 PM PDT 24
Peak memory 215264 kb
Host smart-059d1dd2-98f2-43e2-9364-7f8f974e8d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201649577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.201649577
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2524114154
Short name T424
Test name
Test status
Simulation time 30681272 ps
CPU time 0.94 seconds
Started Apr 02 01:34:38 PM PDT 24
Finished Apr 02 01:34:39 PM PDT 24
Peak memory 215496 kb
Host smart-1530b5fd-fb11-4205-8df3-639198e66c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524114154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2524114154
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2292530161
Short name T46
Test name
Test status
Simulation time 361817160 ps
CPU time 6.21 seconds
Started Apr 02 01:34:44 PM PDT 24
Finished Apr 02 01:34:50 PM PDT 24
Peak memory 234496 kb
Host smart-8b912c17-c7ed-417c-bd7e-80c6689f49ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292530161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2292530161
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2422095899
Short name T648
Test name
Test status
Simulation time 15097458 ps
CPU time 0.93 seconds
Started Apr 02 01:34:29 PM PDT 24
Finished Apr 02 01:34:31 PM PDT 24
Peak memory 215272 kb
Host smart-ea5480b9-d030-489b-a421-d6f2d7de7ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422095899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2422095899
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.771833552
Short name T826
Test name
Test status
Simulation time 292176125 ps
CPU time 5.88 seconds
Started Apr 02 01:34:34 PM PDT 24
Finished Apr 02 01:34:40 PM PDT 24
Peak memory 219184 kb
Host smart-6ebe7473-99ad-486c-9041-2f8819d2d461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771833552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.771833552
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2459465304
Short name T178
Test name
Test status
Simulation time 66345205594 ps
CPU time 500.34 seconds
Started Apr 02 01:34:35 PM PDT 24
Finished Apr 02 01:42:55 PM PDT 24
Peak memory 223560 kb
Host smart-09c796be-db12-4c50-ac7a-bf683b685fdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459465304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2459465304
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2777476607
Short name T553
Test name
Test status
Simulation time 31197613 ps
CPU time 1.22 seconds
Started Apr 02 01:36:32 PM PDT 24
Finished Apr 02 01:36:34 PM PDT 24
Peak memory 215600 kb
Host smart-c0674463-eea8-47fb-90cf-edec5f504402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777476607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2777476607
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.538657542
Short name T140
Test name
Test status
Simulation time 15855825 ps
CPU time 0.91 seconds
Started Apr 02 01:36:31 PM PDT 24
Finished Apr 02 01:36:33 PM PDT 24
Peak memory 206532 kb
Host smart-70d109d0-69d8-42a3-b360-46f7a37db450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538657542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.538657542
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3608000913
Short name T366
Test name
Test status
Simulation time 13354788 ps
CPU time 0.89 seconds
Started Apr 02 01:36:34 PM PDT 24
Finished Apr 02 01:36:35 PM PDT 24
Peak memory 215536 kb
Host smart-3fa2b3c6-d564-4007-9aec-d74464e837ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608000913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3608000913
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.798896383
Short name T778
Test name
Test status
Simulation time 21121234 ps
CPU time 1.05 seconds
Started Apr 02 01:36:33 PM PDT 24
Finished Apr 02 01:36:34 PM PDT 24
Peak memory 217600 kb
Host smart-1a161233-e0df-4cc1-a3e1-b381b38e7d27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798896383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.798896383
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3855341517
Short name T151
Test name
Test status
Simulation time 33728405 ps
CPU time 1.08 seconds
Started Apr 02 01:36:34 PM PDT 24
Finished Apr 02 01:36:35 PM PDT 24
Peak memory 219336 kb
Host smart-ac2da9af-0d3e-465a-92b2-91e3a3b80b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855341517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3855341517
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2850655330
Short name T776
Test name
Test status
Simulation time 73936572 ps
CPU time 1.37 seconds
Started Apr 02 01:36:30 PM PDT 24
Finished Apr 02 01:36:32 PM PDT 24
Peak memory 218468 kb
Host smart-950e9ba8-f625-4afb-9bb3-03f1e9552318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850655330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2850655330
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.635720642
Short name T725
Test name
Test status
Simulation time 20754324 ps
CPU time 1.11 seconds
Started Apr 02 01:36:38 PM PDT 24
Finished Apr 02 01:36:39 PM PDT 24
Peak memory 215456 kb
Host smart-1ca5f283-aac4-4c67-bf25-7d2b9edb99a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635720642 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.635720642
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4277771396
Short name T44
Test name
Test status
Simulation time 27020521 ps
CPU time 1.03 seconds
Started Apr 02 01:36:35 PM PDT 24
Finished Apr 02 01:36:36 PM PDT 24
Peak memory 215264 kb
Host smart-cd503545-6599-4034-a93c-d29baaab0e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277771396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4277771396
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3573727306
Short name T682
Test name
Test status
Simulation time 120030399 ps
CPU time 2.85 seconds
Started Apr 02 01:36:30 PM PDT 24
Finished Apr 02 01:36:33 PM PDT 24
Peak memory 216672 kb
Host smart-d9fc0b92-7b7b-4c90-9d0f-a58dad5d8367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573727306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3573727306
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.4174752101
Short name T189
Test name
Test status
Simulation time 483804008943 ps
CPU time 2739.58 seconds
Started Apr 02 01:36:33 PM PDT 24
Finished Apr 02 02:22:13 PM PDT 24
Peak memory 228792 kb
Host smart-bc42ab9e-5d12-4e58-9fce-25fb079f74fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174752101 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.4174752101
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.975344686
Short name T257
Test name
Test status
Simulation time 67574945 ps
CPU time 1.21 seconds
Started Apr 02 01:36:36 PM PDT 24
Finished Apr 02 01:36:37 PM PDT 24
Peak memory 215648 kb
Host smart-9c542d6e-f3e6-4878-896c-bef25061f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975344686 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.975344686
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2916761914
Short name T698
Test name
Test status
Simulation time 25548209 ps
CPU time 0.88 seconds
Started Apr 02 01:36:36 PM PDT 24
Finished Apr 02 01:36:37 PM PDT 24
Peak memory 205944 kb
Host smart-9170c9ce-7379-49e4-ab29-23a1cfa8e1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916761914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2916761914
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.999117263
Short name T718
Test name
Test status
Simulation time 12512735 ps
CPU time 0.89 seconds
Started Apr 02 01:36:35 PM PDT 24
Finished Apr 02 01:36:36 PM PDT 24
Peak memory 215936 kb
Host smart-ac5ac329-5262-4111-9843-bab423f5e66a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999117263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.999117263
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1771293774
Short name T65
Test name
Test status
Simulation time 23926839 ps
CPU time 1.24 seconds
Started Apr 02 01:36:36 PM PDT 24
Finished Apr 02 01:36:39 PM PDT 24
Peak memory 229784 kb
Host smart-e0b7b887-b600-4c38-8429-8ff5aa14658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771293774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1771293774
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3407902069
Short name T422
Test name
Test status
Simulation time 29519883 ps
CPU time 1.28 seconds
Started Apr 02 01:36:38 PM PDT 24
Finished Apr 02 01:36:39 PM PDT 24
Peak memory 215180 kb
Host smart-313b9942-c7a0-48ce-8690-03175f40c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407902069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3407902069
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2860597766
Short name T453
Test name
Test status
Simulation time 36397292 ps
CPU time 1.02 seconds
Started Apr 02 01:36:41 PM PDT 24
Finished Apr 02 01:36:44 PM PDT 24
Peak memory 223948 kb
Host smart-41d52249-2ca8-4473-b664-0415c1824302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860597766 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2860597766
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3413169369
Short name T655
Test name
Test status
Simulation time 142377178 ps
CPU time 0.95 seconds
Started Apr 02 01:36:37 PM PDT 24
Finished Apr 02 01:36:39 PM PDT 24
Peak memory 215076 kb
Host smart-239977b9-bcfe-478e-a5e5-b71fce4679eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413169369 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3413169369
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2422632384
Short name T513
Test name
Test status
Simulation time 324933050 ps
CPU time 2.36 seconds
Started Apr 02 01:36:32 PM PDT 24
Finished Apr 02 01:36:35 PM PDT 24
Peak memory 215300 kb
Host smart-7bb1476f-5178-4940-82fb-9577152ffae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422632384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2422632384
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.931540880
Short name T827
Test name
Test status
Simulation time 22775067807 ps
CPU time 582.73 seconds
Started Apr 02 01:36:32 PM PDT 24
Finished Apr 02 01:46:15 PM PDT 24
Peak memory 220224 kb
Host smart-b5a339a3-b3ff-460e-aa0c-85b5b0bab404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931540880 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.931540880
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4279433959
Short name T547
Test name
Test status
Simulation time 121139736 ps
CPU time 1.23 seconds
Started Apr 02 01:36:39 PM PDT 24
Finished Apr 02 01:36:41 PM PDT 24
Peak memory 215584 kb
Host smart-d1571751-dd93-48f9-9d3c-c44e9ba0c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279433959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4279433959
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.498917810
Short name T319
Test name
Test status
Simulation time 41384383 ps
CPU time 0.85 seconds
Started Apr 02 01:36:42 PM PDT 24
Finished Apr 02 01:36:44 PM PDT 24
Peak memory 205816 kb
Host smart-badff0d6-4317-411a-80f2-b1811ce8b099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498917810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.498917810
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.4159734986
Short name T168
Test name
Test status
Simulation time 20923222 ps
CPU time 0.87 seconds
Started Apr 02 01:36:39 PM PDT 24
Finished Apr 02 01:36:41 PM PDT 24
Peak memory 215780 kb
Host smart-9b27b6fa-211c-4f31-b89e-e1fdf78dbbd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159734986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4159734986
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.1843010609
Short name T8
Test name
Test status
Simulation time 49204937 ps
CPU time 1.02 seconds
Started Apr 02 01:36:40 PM PDT 24
Finished Apr 02 01:36:43 PM PDT 24
Peak memory 220144 kb
Host smart-8be57d7f-bc27-47b2-b690-bd89979bd703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843010609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1843010609
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2499988205
Short name T561
Test name
Test status
Simulation time 35732623 ps
CPU time 1.28 seconds
Started Apr 02 01:36:40 PM PDT 24
Finished Apr 02 01:36:42 PM PDT 24
Peak memory 218916 kb
Host smart-b553b370-64b9-48f4-bf00-e15607f65034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499988205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2499988205
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.3725791935
Short name T414
Test name
Test status
Simulation time 17450763 ps
CPU time 1 seconds
Started Apr 02 01:36:36 PM PDT 24
Finished Apr 02 01:36:37 PM PDT 24
Peak memory 215236 kb
Host smart-75ad9cb4-6fb4-482a-9429-f4980399efd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725791935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3725791935
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.254499406
Short name T794
Test name
Test status
Simulation time 580189272 ps
CPU time 3.48 seconds
Started Apr 02 01:36:40 PM PDT 24
Finished Apr 02 01:36:44 PM PDT 24
Peak memory 215264 kb
Host smart-7a41959a-34b8-4a3e-a25b-9ec306fa3aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254499406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.254499406
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3192232176
Short name T690
Test name
Test status
Simulation time 47130223899 ps
CPU time 1186.86 seconds
Started Apr 02 01:36:39 PM PDT 24
Finished Apr 02 01:56:28 PM PDT 24
Peak memory 221508 kb
Host smart-6aa15417-25af-442a-91fd-0bacb6f0b9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192232176 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3192232176
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2925034777
Short name T13
Test name
Test status
Simulation time 27936690 ps
CPU time 1.31 seconds
Started Apr 02 01:36:46 PM PDT 24
Finished Apr 02 01:36:47 PM PDT 24
Peak memory 215612 kb
Host smart-f8eb80b5-b6fa-453b-adca-df4deffcef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925034777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2925034777
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1327346899
Short name T483
Test name
Test status
Simulation time 36042349 ps
CPU time 1.01 seconds
Started Apr 02 01:36:49 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 206448 kb
Host smart-4f491a3c-3a1d-4787-b12f-8e2c5a1b0b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327346899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1327346899
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.567805345
Short name T651
Test name
Test status
Simulation time 11659755 ps
CPU time 0.87 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 215400 kb
Host smart-4ae1a372-eaf2-42c1-b655-c564c7bbaed7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567805345 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.567805345
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2913746296
Short name T430
Test name
Test status
Simulation time 20502533 ps
CPU time 1.02 seconds
Started Apr 02 01:36:45 PM PDT 24
Finished Apr 02 01:36:46 PM PDT 24
Peak memory 217460 kb
Host smart-c17f5e00-0ea0-49f3-88da-e0ca912f577b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913746296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2913746296
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.986782804
Short name T721
Test name
Test status
Simulation time 19753863 ps
CPU time 1.03 seconds
Started Apr 02 01:36:49 PM PDT 24
Finished Apr 02 01:36:50 PM PDT 24
Peak memory 217908 kb
Host smart-5d4b1e42-69af-4555-b2fe-da44da869e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986782804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.986782804
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4184745683
Short name T290
Test name
Test status
Simulation time 38352314 ps
CPU time 1.43 seconds
Started Apr 02 01:36:40 PM PDT 24
Finished Apr 02 01:36:44 PM PDT 24
Peak memory 218876 kb
Host smart-970efa18-16b2-4a65-b323-a43e8e6f35dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184745683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4184745683
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1117794620
Short name T781
Test name
Test status
Simulation time 35772583 ps
CPU time 0.92 seconds
Started Apr 02 01:36:45 PM PDT 24
Finished Apr 02 01:36:46 PM PDT 24
Peak memory 215528 kb
Host smart-ac26f13d-6d58-4ff0-9fa9-42e3a46ad6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117794620 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1117794620
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.453637749
Short name T702
Test name
Test status
Simulation time 22439225 ps
CPU time 0.91 seconds
Started Apr 02 01:36:44 PM PDT 24
Finished Apr 02 01:36:46 PM PDT 24
Peak memory 215220 kb
Host smart-56ee0a23-ac7e-4088-94e1-b75f02d676d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453637749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.453637749
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1231378039
Short name T120
Test name
Test status
Simulation time 543776335 ps
CPU time 5.74 seconds
Started Apr 02 01:36:43 PM PDT 24
Finished Apr 02 01:36:49 PM PDT 24
Peak memory 215264 kb
Host smart-9e9aeb90-8a33-4721-8578-237ba7edb13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231378039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1231378039
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2309757207
Short name T428
Test name
Test status
Simulation time 49920276777 ps
CPU time 1259.71 seconds
Started Apr 02 01:36:43 PM PDT 24
Finished Apr 02 01:57:44 PM PDT 24
Peak memory 223728 kb
Host smart-84f65226-8dcb-455f-b9a8-158986cb8b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309757207 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2309757207
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2144852447
Short name T137
Test name
Test status
Simulation time 52499821 ps
CPU time 1.19 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:59 PM PDT 24
Peak memory 215504 kb
Host smart-cac03735-a66b-456f-a624-270beeee587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144852447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2144852447
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3356283010
Short name T309
Test name
Test status
Simulation time 12189795 ps
CPU time 0.84 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 205660 kb
Host smart-85a56cff-2f1d-46b9-8cb2-b16461171585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356283010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3356283010
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1631210095
Short name T661
Test name
Test status
Simulation time 37111102 ps
CPU time 0.85 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 215288 kb
Host smart-792fb0b3-403f-4fad-b941-66a2a8d38c6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631210095 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1631210095
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.120337913
Short name T71
Test name
Test status
Simulation time 58292274 ps
CPU time 1.13 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 216496 kb
Host smart-02adeed6-3b4a-4b5e-aff2-e38bc3aa52de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120337913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.120337913
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3783720798
Short name T779
Test name
Test status
Simulation time 28881076 ps
CPU time 1.34 seconds
Started Apr 02 01:36:46 PM PDT 24
Finished Apr 02 01:36:48 PM PDT 24
Peak memory 229804 kb
Host smart-a6953c4e-a41d-4de2-b5aa-9fa5fc48bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783720798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3783720798
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2490565050
Short name T574
Test name
Test status
Simulation time 35971346 ps
CPU time 1.54 seconds
Started Apr 02 01:36:46 PM PDT 24
Finished Apr 02 01:36:47 PM PDT 24
Peak memory 218008 kb
Host smart-21f6469b-da93-4665-8fdc-b864ec433a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490565050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2490565050
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1247128418
Short name T592
Test name
Test status
Simulation time 35780264 ps
CPU time 0.9 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 215324 kb
Host smart-bbf9d006-862b-4a59-b657-35dd7e871d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247128418 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1247128418
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.4182199553
Short name T639
Test name
Test status
Simulation time 27004819 ps
CPU time 0.95 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 215176 kb
Host smart-567c8a12-4690-489b-8dca-ccadad9503b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182199553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4182199553
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.580370459
Short name T355
Test name
Test status
Simulation time 929835936 ps
CPU time 5.09 seconds
Started Apr 02 01:36:48 PM PDT 24
Finished Apr 02 01:36:54 PM PDT 24
Peak memory 216640 kb
Host smart-94844de8-180c-4cc7-914c-1fefb4d5ba6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580370459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.580370459
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4150499775
Short name T705
Test name
Test status
Simulation time 73447560133 ps
CPU time 906.66 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:51:57 PM PDT 24
Peak memory 219768 kb
Host smart-2e4ca976-eb98-44a8-9fe8-5f47f76159a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150499775 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4150499775
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.3544314911
Short name T822
Test name
Test status
Simulation time 60710646 ps
CPU time 0.98 seconds
Started Apr 02 01:36:49 PM PDT 24
Finished Apr 02 01:36:50 PM PDT 24
Peak memory 206516 kb
Host smart-17a03435-e6de-447e-a385-dfadf363abda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544314911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3544314911
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.44236822
Short name T672
Test name
Test status
Simulation time 169324386 ps
CPU time 1.02 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 217708 kb
Host smart-d412a09e-c8c7-4970-9387-c480d9ed3aa7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44236822 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_dis
able_auto_req_mode.44236822
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3184216306
Short name T673
Test name
Test status
Simulation time 35670183 ps
CPU time 0.94 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 219284 kb
Host smart-07d0434a-2c20-4fab-8f4b-288e39551f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184216306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3184216306
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_intr.2989608166
Short name T132
Test name
Test status
Simulation time 20558730 ps
CPU time 1.04 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 215576 kb
Host smart-9fdd3262-ba20-4ae4-be81-a37941b9e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989608166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2989608166
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2837940213
Short name T570
Test name
Test status
Simulation time 17525494 ps
CPU time 1 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 215188 kb
Host smart-4e0d516d-75c8-4787-8ceb-c9dfb9f8c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837940213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2837940213
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4272951383
Short name T772
Test name
Test status
Simulation time 602886529 ps
CPU time 3.86 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:55 PM PDT 24
Peak memory 216484 kb
Host smart-59349932-b575-42c2-83e4-dcdeeaa4f756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272951383 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4272951383
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert_test.3200641481
Short name T458
Test name
Test status
Simulation time 81697342 ps
CPU time 0.82 seconds
Started Apr 02 01:36:56 PM PDT 24
Finished Apr 02 01:36:57 PM PDT 24
Peak memory 206484 kb
Host smart-0912a91f-1210-427c-8d85-25aebda18a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200641481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3200641481
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.698491481
Short name T148
Test name
Test status
Simulation time 75164447 ps
CPU time 0.89 seconds
Started Apr 02 01:36:53 PM PDT 24
Finished Apr 02 01:36:54 PM PDT 24
Peak memory 215808 kb
Host smart-5b53abfc-1ec4-4dc4-ab64-d36d8526fd39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698491481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.698491481
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.1067058902
Short name T82
Test name
Test status
Simulation time 34637133 ps
CPU time 1 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 229512 kb
Host smart-6167180c-e325-4fc1-864e-924392e9fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067058902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1067058902
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3640655484
Short name T650
Test name
Test status
Simulation time 165981153 ps
CPU time 1.4 seconds
Started Apr 02 01:36:49 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 216660 kb
Host smart-f7e14eb9-0c4d-4118-ae9c-e898ee554b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640655484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3640655484
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1430674836
Short name T122
Test name
Test status
Simulation time 29548649 ps
CPU time 0.86 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 215612 kb
Host smart-c5940ab3-335a-4fe6-8603-9fdb6b5c354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430674836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1430674836
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1703915840
Short name T121
Test name
Test status
Simulation time 26537469 ps
CPU time 0.96 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 215260 kb
Host smart-e6f3be7d-6638-456b-b883-59a64022d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703915840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1703915840
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.460475955
Short name T623
Test name
Test status
Simulation time 616417094 ps
CPU time 3.42 seconds
Started Apr 02 01:36:48 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 216536 kb
Host smart-d4c18e11-9ce5-49c3-a07d-c63d9a3e5546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460475955 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.460475955
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2735314076
Short name T554
Test name
Test status
Simulation time 47619689661 ps
CPU time 1072.49 seconds
Started Apr 02 01:36:49 PM PDT 24
Finished Apr 02 01:54:41 PM PDT 24
Peak memory 219976 kb
Host smart-2b35771e-89f1-48d4-985f-bf1497fa0f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735314076 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2735314076
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2384207303
Short name T656
Test name
Test status
Simulation time 81297692 ps
CPU time 1.12 seconds
Started Apr 02 01:36:52 PM PDT 24
Finished Apr 02 01:36:53 PM PDT 24
Peak memory 215636 kb
Host smart-90aa6a81-6379-45ac-8aff-33a9dc7e1d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384207303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2384207303
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.4131328012
Short name T346
Test name
Test status
Simulation time 61620071 ps
CPU time 0.84 seconds
Started Apr 02 01:36:52 PM PDT 24
Finished Apr 02 01:36:54 PM PDT 24
Peak memory 205784 kb
Host smart-9c796c63-a589-4342-98e9-06e33c270bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131328012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4131328012
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3770417911
Short name T154
Test name
Test status
Simulation time 20496237 ps
CPU time 0.87 seconds
Started Apr 02 01:36:52 PM PDT 24
Finished Apr 02 01:36:54 PM PDT 24
Peak memory 215704 kb
Host smart-a9734d17-5614-4ff5-b4a5-346c68abc831
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770417911 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3770417911
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1738407167
Short name T84
Test name
Test status
Simulation time 28425960 ps
CPU time 1.08 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 218964 kb
Host smart-1b8c3d00-75d4-42f6-84da-b3c3b5ff2858
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738407167 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1738407167
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1389038608
Short name T817
Test name
Test status
Simulation time 34347436 ps
CPU time 1.09 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 219256 kb
Host smart-b2c0e88d-06c4-44ee-84ea-28d380f1a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389038608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1389038608
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.146265381
Short name T524
Test name
Test status
Simulation time 61297065 ps
CPU time 1.5 seconds
Started Apr 02 01:36:53 PM PDT 24
Finished Apr 02 01:36:55 PM PDT 24
Peak memory 218132 kb
Host smart-637e5094-91dd-4333-b4c3-7a49fa711c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146265381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.146265381
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.553063558
Short name T40
Test name
Test status
Simulation time 24131852 ps
CPU time 1.07 seconds
Started Apr 02 01:36:54 PM PDT 24
Finished Apr 02 01:36:57 PM PDT 24
Peak memory 224076 kb
Host smart-095e753a-0dca-4857-980c-3f840a83732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553063558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.553063558
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3535286038
Short name T371
Test name
Test status
Simulation time 37040937 ps
CPU time 0.87 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:36:52 PM PDT 24
Peak memory 215272 kb
Host smart-6e8f8e5d-622f-4647-8ac8-e1530f76c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535286038 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3535286038
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1031110371
Short name T118
Test name
Test status
Simulation time 156219310 ps
CPU time 3.28 seconds
Started Apr 02 01:36:55 PM PDT 24
Finished Apr 02 01:36:59 PM PDT 24
Peak memory 216704 kb
Host smart-d65930b7-3542-45fc-bf6f-a493339a2982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031110371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1031110371
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4041053695
Short name T609
Test name
Test status
Simulation time 54160149394 ps
CPU time 1332.17 seconds
Started Apr 02 01:36:51 PM PDT 24
Finished Apr 02 01:59:04 PM PDT 24
Peak memory 223112 kb
Host smart-0e76f0e7-85ed-4b79-b9e4-9630b00ca3a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041053695 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4041053695
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.313939949
Short name T645
Test name
Test status
Simulation time 39061804 ps
CPU time 1.14 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 215660 kb
Host smart-6b33c3ab-7c05-40fc-817e-54215a1379b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313939949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.313939949
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3866156186
Short name T680
Test name
Test status
Simulation time 23736081 ps
CPU time 0.83 seconds
Started Apr 02 01:36:55 PM PDT 24
Finished Apr 02 01:36:56 PM PDT 24
Peak memory 206560 kb
Host smart-0041b007-4db6-432c-bf8d-3eb224528843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866156186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3866156186
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4175405032
Short name T103
Test name
Test status
Simulation time 13000362 ps
CPU time 0.91 seconds
Started Apr 02 01:36:55 PM PDT 24
Finished Apr 02 01:36:57 PM PDT 24
Peak memory 215972 kb
Host smart-801dfce1-e5d2-447e-b084-be186dcdd222
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175405032 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4175405032
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2120370113
Short name T70
Test name
Test status
Simulation time 48521403 ps
CPU time 1.39 seconds
Started Apr 02 01:36:55 PM PDT 24
Finished Apr 02 01:36:57 PM PDT 24
Peak memory 216348 kb
Host smart-d40b3424-df80-49ea-957e-abb8cf437299
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120370113 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2120370113
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3976119196
Short name T552
Test name
Test status
Simulation time 18003025 ps
CPU time 1.03 seconds
Started Apr 02 01:36:56 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 217552 kb
Host smart-4abb1b25-831d-429d-aa80-1b155c78b30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976119196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3976119196
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3552937698
Short name T804
Test name
Test status
Simulation time 521401202 ps
CPU time 5.37 seconds
Started Apr 02 01:36:55 PM PDT 24
Finished Apr 02 01:37:01 PM PDT 24
Peak memory 216720 kb
Host smart-490236ae-b5d5-427d-a836-81bf5700c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552937698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3552937698
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1015452444
Short name T55
Test name
Test status
Simulation time 23887525 ps
CPU time 0.97 seconds
Started Apr 02 01:36:56 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 215568 kb
Host smart-86110c68-6db0-4800-b031-21f0bf1bbc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015452444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1015452444
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2998330960
Short name T532
Test name
Test status
Simulation time 17716655 ps
CPU time 0.98 seconds
Started Apr 02 01:36:50 PM PDT 24
Finished Apr 02 01:36:51 PM PDT 24
Peak memory 215216 kb
Host smart-05d9000b-625b-4c41-923f-84717f242681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998330960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2998330960
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2718575346
Short name T535
Test name
Test status
Simulation time 243841109 ps
CPU time 5.24 seconds
Started Apr 02 01:36:52 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 216804 kb
Host smart-f136cbfd-5af7-4037-b8da-5e4bad1e7b0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718575346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2718575346
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1898022647
Short name T834
Test name
Test status
Simulation time 249539803989 ps
CPU time 1647.53 seconds
Started Apr 02 01:36:56 PM PDT 24
Finished Apr 02 02:04:24 PM PDT 24
Peak memory 225700 kb
Host smart-33401b47-ebc9-41cd-bf6a-c1b488133b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898022647 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1898022647
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1279353580
Short name T239
Test name
Test status
Simulation time 34451978 ps
CPU time 1.19 seconds
Started Apr 02 01:36:58 PM PDT 24
Finished Apr 02 01:36:59 PM PDT 24
Peak memory 215632 kb
Host smart-f42bc62b-bde8-459f-868e-d666b2ba773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279353580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1279353580
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2388070612
Short name T556
Test name
Test status
Simulation time 15527455 ps
CPU time 0.89 seconds
Started Apr 02 01:36:59 PM PDT 24
Finished Apr 02 01:37:00 PM PDT 24
Peak memory 205956 kb
Host smart-22d6e83f-85e8-4a06-b0a4-dba7bde5acdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388070612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2388070612
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.533316978
Short name T628
Test name
Test status
Simulation time 30897391 ps
CPU time 0.83 seconds
Started Apr 02 01:36:59 PM PDT 24
Finished Apr 02 01:37:01 PM PDT 24
Peak memory 215916 kb
Host smart-ad21784d-43dc-4705-946c-ff171ea2a17c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533316978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.533316978
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.423720510
Short name T79
Test name
Test status
Simulation time 26507952 ps
CPU time 1.06 seconds
Started Apr 02 01:36:57 PM PDT 24
Finished Apr 02 01:36:58 PM PDT 24
Peak memory 216508 kb
Host smart-40f40f1e-2ae8-4b9f-b334-a9fc0b3db466
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423720510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.423720510
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4215293763
Short name T156
Test name
Test status
Simulation time 46311272 ps
CPU time 1.14 seconds
Started Apr 02 01:36:59 PM PDT 24
Finished Apr 02 01:37:01 PM PDT 24
Peak memory 219000 kb
Host smart-16af8196-e7cc-461b-94ba-dcad27688f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215293763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4215293763
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1554506710
Short name T450
Test name
Test status
Simulation time 67232538 ps
CPU time 1.24 seconds
Started Apr 02 01:36:55 PM PDT 24
Finished Apr 02 01:36:57 PM PDT 24
Peak memory 218104 kb
Host smart-086dc1ed-5708-4b8c-83a0-a2349dfd0599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554506710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1554506710
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.791956835
Short name T747
Test name
Test status
Simulation time 73432866 ps
CPU time 0.88 seconds
Started Apr 02 01:37:00 PM PDT 24
Finished Apr 02 01:37:01 PM PDT 24
Peak memory 215224 kb
Host smart-a6c33166-253f-4bf0-beb9-62c549a0d67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791956835 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.791956835
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1393840882
Short name T644
Test name
Test status
Simulation time 17023391 ps
CPU time 0.99 seconds
Started Apr 02 01:36:58 PM PDT 24
Finished Apr 02 01:36:59 PM PDT 24
Peak memory 215284 kb
Host smart-76096280-f750-4b9d-a2be-be1100e386c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393840882 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1393840882
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1198674274
Short name T816
Test name
Test status
Simulation time 95738329 ps
CPU time 1.08 seconds
Started Apr 02 01:36:54 PM PDT 24
Finished Apr 02 01:36:57 PM PDT 24
Peak memory 205676 kb
Host smart-bda1dcca-a4ee-4bc0-883a-2dc144bb7649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198674274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1198674274
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.490261033
Short name T807
Test name
Test status
Simulation time 77029902838 ps
CPU time 1698.3 seconds
Started Apr 02 01:37:01 PM PDT 24
Finished Apr 02 02:05:19 PM PDT 24
Peak memory 224792 kb
Host smart-e34367c8-e5e6-4110-b672-105c8d11fbfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490261033 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.490261033
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1054243003
Short name T490
Test name
Test status
Simulation time 108483719 ps
CPU time 1.16 seconds
Started Apr 02 01:34:52 PM PDT 24
Finished Apr 02 01:34:53 PM PDT 24
Peak memory 215604 kb
Host smart-1cd858a2-eccf-4acc-8007-80ec0b73bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054243003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1054243003
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.24089111
Short name T455
Test name
Test status
Simulation time 14332321 ps
CPU time 0.89 seconds
Started Apr 02 01:34:52 PM PDT 24
Finished Apr 02 01:34:53 PM PDT 24
Peak memory 205964 kb
Host smart-2055f6f3-8e73-40ec-8f91-82d1a8e959ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24089111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.24089111
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1631757561
Short name T177
Test name
Test status
Simulation time 42604048 ps
CPU time 0.92 seconds
Started Apr 02 01:34:50 PM PDT 24
Finished Apr 02 01:34:51 PM PDT 24
Peak memory 215844 kb
Host smart-940439d5-3660-411b-b3c7-24f15e42ae0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631757561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1631757561
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.1946811889
Short name T231
Test name
Test status
Simulation time 32626516 ps
CPU time 0.86 seconds
Started Apr 02 01:34:50 PM PDT 24
Finished Apr 02 01:34:51 PM PDT 24
Peak memory 217748 kb
Host smart-60e5fea2-ae5b-4dde-a50d-38f51c703d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946811889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1946811889
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3091883894
Short name T531
Test name
Test status
Simulation time 90071089 ps
CPU time 1.54 seconds
Started Apr 02 01:34:51 PM PDT 24
Finished Apr 02 01:34:52 PM PDT 24
Peak memory 218308 kb
Host smart-612ff31c-d1d4-4597-92f4-7b38429afd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091883894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3091883894
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1513138030
Short name T395
Test name
Test status
Simulation time 22536679 ps
CPU time 1.09 seconds
Started Apr 02 01:34:50 PM PDT 24
Finished Apr 02 01:34:51 PM PDT 24
Peak memory 215480 kb
Host smart-55698b52-2894-470a-92e4-a9ead97e5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513138030 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1513138030
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1580329345
Short name T625
Test name
Test status
Simulation time 50811735 ps
CPU time 0.96 seconds
Started Apr 02 01:34:46 PM PDT 24
Finished Apr 02 01:34:48 PM PDT 24
Peak memory 207060 kb
Host smart-5ed93ecd-416d-44f7-ab9d-75d26b961873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580329345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1580329345
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4094912122
Short name T18
Test name
Test status
Simulation time 1503625825 ps
CPU time 6.36 seconds
Started Apr 02 01:34:52 PM PDT 24
Finished Apr 02 01:34:59 PM PDT 24
Peak memory 235876 kb
Host smart-8650e31d-3eb2-4335-b28d-b5119db454ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094912122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4094912122
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1214248861
Short name T398
Test name
Test status
Simulation time 25221155 ps
CPU time 0.9 seconds
Started Apr 02 01:34:47 PM PDT 24
Finished Apr 02 01:34:48 PM PDT 24
Peak memory 215200 kb
Host smart-ed9303fc-2349-4bb3-8e31-2adbf9defd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214248861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1214248861
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3594995998
Short name T336
Test name
Test status
Simulation time 360442853 ps
CPU time 6.52 seconds
Started Apr 02 01:34:49 PM PDT 24
Finished Apr 02 01:34:56 PM PDT 24
Peak memory 218880 kb
Host smart-9d3ca005-bf91-4ebf-adf7-f84d1c55922a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594995998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3594995998
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2658961513
Short name T828
Test name
Test status
Simulation time 54130344222 ps
CPU time 580.86 seconds
Started Apr 02 01:34:49 PM PDT 24
Finished Apr 02 01:44:31 PM PDT 24
Peak memory 223720 kb
Host smart-5ec173ec-9d58-4680-b0a0-5d865fc9a811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658961513 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2658961513
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.986450789
Short name T560
Test name
Test status
Simulation time 41188621 ps
CPU time 1.25 seconds
Started Apr 02 01:37:01 PM PDT 24
Finished Apr 02 01:37:03 PM PDT 24
Peak memory 215532 kb
Host smart-5e809a89-1a7d-4fb3-8363-6ea3b6f176f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986450789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.986450789
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.827258671
Short name T736
Test name
Test status
Simulation time 18891463 ps
CPU time 0.94 seconds
Started Apr 02 01:37:06 PM PDT 24
Finished Apr 02 01:37:07 PM PDT 24
Peak memory 205988 kb
Host smart-954bf0d2-182e-4888-8fc1-776d2e8b1f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827258671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.827258671
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_err.2658651503
Short name T610
Test name
Test status
Simulation time 30837033 ps
CPU time 1.26 seconds
Started Apr 02 01:37:05 PM PDT 24
Finished Apr 02 01:37:08 PM PDT 24
Peak memory 219236 kb
Host smart-765c05d8-358d-4c86-ab27-95f2e8f3392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658651503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2658651503
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.479370446
Short name T492
Test name
Test status
Simulation time 82696598 ps
CPU time 1.47 seconds
Started Apr 02 01:37:04 PM PDT 24
Finished Apr 02 01:37:06 PM PDT 24
Peak memory 217840 kb
Host smart-ca1d8973-3e4e-48c2-a4e7-f992aaeacb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479370446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.479370446
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2112874535
Short name T321
Test name
Test status
Simulation time 20516625 ps
CPU time 1.12 seconds
Started Apr 02 01:37:01 PM PDT 24
Finished Apr 02 01:37:02 PM PDT 24
Peak memory 215608 kb
Host smart-99c0c497-c651-48d9-ac11-8151ed9afda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112874535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2112874535
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.679997463
Short name T457
Test name
Test status
Simulation time 20522658 ps
CPU time 0.96 seconds
Started Apr 02 01:37:01 PM PDT 24
Finished Apr 02 01:37:03 PM PDT 24
Peak memory 215248 kb
Host smart-e35fec3d-e269-4803-b225-6610bb13c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679997463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.679997463
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2129023460
Short name T470
Test name
Test status
Simulation time 52699406 ps
CPU time 1.02 seconds
Started Apr 02 01:37:02 PM PDT 24
Finished Apr 02 01:37:03 PM PDT 24
Peak memory 205736 kb
Host smart-ee48f05b-de47-479c-9483-f1da2228c224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129023460 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2129023460
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.4069828123
Short name T291
Test name
Test status
Simulation time 28094907195 ps
CPU time 563.27 seconds
Started Apr 02 01:37:00 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 218388 kb
Host smart-18956d77-2ac1-4d1e-be0d-24acb1558ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069828123 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4069828123
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1260386790
Short name T110
Test name
Test status
Simulation time 27266670 ps
CPU time 1.22 seconds
Started Apr 02 01:37:08 PM PDT 24
Finished Apr 02 01:37:10 PM PDT 24
Peak memory 215508 kb
Host smart-06b5bdf2-a233-4023-b837-566a027fc100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260386790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1260386790
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.680883006
Short name T633
Test name
Test status
Simulation time 20140903 ps
CPU time 0.9 seconds
Started Apr 02 01:37:08 PM PDT 24
Finished Apr 02 01:37:09 PM PDT 24
Peak memory 205736 kb
Host smart-6014d168-cd9d-4591-a091-2009f8376a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680883006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.680883006
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2511504030
Short name T169
Test name
Test status
Simulation time 13402297 ps
CPU time 0.99 seconds
Started Apr 02 01:37:08 PM PDT 24
Finished Apr 02 01:37:09 PM PDT 24
Peak memory 215684 kb
Host smart-2a5a92ca-92c4-4703-809d-1239b1581edd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511504030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2511504030
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3692539227
Short name T575
Test name
Test status
Simulation time 34620786 ps
CPU time 1.06 seconds
Started Apr 02 01:37:08 PM PDT 24
Finished Apr 02 01:37:09 PM PDT 24
Peak memory 216628 kb
Host smart-0fb66478-ff94-4a68-9cd3-63ac3f63e214
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692539227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3692539227
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2498899467
Short name T356
Test name
Test status
Simulation time 76186242 ps
CPU time 0.89 seconds
Started Apr 02 01:37:09 PM PDT 24
Finished Apr 02 01:37:10 PM PDT 24
Peak memory 216672 kb
Host smart-e409f263-f521-4684-8d09-6159b43df06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498899467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2498899467
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.4182066859
Short name T475
Test name
Test status
Simulation time 184261051 ps
CPU time 1.16 seconds
Started Apr 02 01:37:04 PM PDT 24
Finished Apr 02 01:37:06 PM PDT 24
Peak memory 219252 kb
Host smart-a05e8ff4-9caa-4333-a05c-b932afda63fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182066859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4182066859
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3488319159
Short name T116
Test name
Test status
Simulation time 29499428 ps
CPU time 0.9 seconds
Started Apr 02 01:37:09 PM PDT 24
Finished Apr 02 01:37:10 PM PDT 24
Peak memory 215492 kb
Host smart-5e1d9e8b-23a0-4085-a973-286d4b380829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488319159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3488319159
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1446790739
Short name T699
Test name
Test status
Simulation time 47894893 ps
CPU time 0.95 seconds
Started Apr 02 01:37:05 PM PDT 24
Finished Apr 02 01:37:07 PM PDT 24
Peak memory 215268 kb
Host smart-d160e184-2ace-47a7-8aed-0c08b015ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446790739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1446790739
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.380545922
Short name T292
Test name
Test status
Simulation time 364127778 ps
CPU time 2.73 seconds
Started Apr 02 01:37:04 PM PDT 24
Finished Apr 02 01:37:08 PM PDT 24
Peak memory 219616 kb
Host smart-46f24d2f-2c31-4237-99be-0098380f7901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380545922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.380545922
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3119091444
Short name T671
Test name
Test status
Simulation time 15451724825 ps
CPU time 374.49 seconds
Started Apr 02 01:37:07 PM PDT 24
Finished Apr 02 01:43:22 PM PDT 24
Peak memory 217724 kb
Host smart-0f3a34bb-49b5-4d1c-a87a-37efa9db96d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119091444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3119091444
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3313968936
Short name T262
Test name
Test status
Simulation time 47873036 ps
CPU time 1.24 seconds
Started Apr 02 01:37:11 PM PDT 24
Finished Apr 02 01:37:13 PM PDT 24
Peak memory 215608 kb
Host smart-1281c23d-4b91-4e2c-a9a5-3fd2af22385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313968936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3313968936
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3998169975
Short name T409
Test name
Test status
Simulation time 53359318 ps
CPU time 0.93 seconds
Started Apr 02 01:37:11 PM PDT 24
Finished Apr 02 01:37:13 PM PDT 24
Peak memory 206884 kb
Host smart-c18a91bd-f01c-4b56-8560-34e66336d7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998169975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3998169975
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3048875439
Short name T69
Test name
Test status
Simulation time 141244541 ps
CPU time 1.18 seconds
Started Apr 02 01:37:13 PM PDT 24
Finished Apr 02 01:37:14 PM PDT 24
Peak memory 216544 kb
Host smart-f8fd02d2-fc99-48ec-bfa9-a859f03187be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048875439 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3048875439
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2484569039
Short name T80
Test name
Test status
Simulation time 32449921 ps
CPU time 0.99 seconds
Started Apr 02 01:37:11 PM PDT 24
Finished Apr 02 01:37:12 PM PDT 24
Peak memory 231384 kb
Host smart-0fd422e0-4efc-4dc1-9de1-be9a6afde872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484569039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2484569039
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2457538346
Short name T348
Test name
Test status
Simulation time 56961602 ps
CPU time 1.33 seconds
Started Apr 02 01:37:09 PM PDT 24
Finished Apr 02 01:37:10 PM PDT 24
Peak memory 216744 kb
Host smart-eba1ee2b-2d50-4d3d-b444-3dddedee21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457538346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2457538346
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2303807632
Short name T4
Test name
Test status
Simulation time 35641102 ps
CPU time 1.02 seconds
Started Apr 02 01:37:10 PM PDT 24
Finished Apr 02 01:37:11 PM PDT 24
Peak memory 223904 kb
Host smart-6f9a83d1-7ab6-4f55-9649-069cde9e073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303807632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2303807632
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.608055738
Short name T596
Test name
Test status
Simulation time 29153098 ps
CPU time 1.01 seconds
Started Apr 02 01:37:07 PM PDT 24
Finished Apr 02 01:37:09 PM PDT 24
Peak memory 215256 kb
Host smart-8255baf7-ce49-42b4-857c-a07300e1eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608055738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.608055738
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1401903330
Short name T417
Test name
Test status
Simulation time 159434515 ps
CPU time 2.21 seconds
Started Apr 02 01:37:06 PM PDT 24
Finished Apr 02 01:37:09 PM PDT 24
Peak memory 216436 kb
Host smart-aa738e1d-96e3-4708-9d75-41ef055ec87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401903330 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1401903330
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1699130056
Short name T461
Test name
Test status
Simulation time 141596777873 ps
CPU time 740.91 seconds
Started Apr 02 01:37:12 PM PDT 24
Finished Apr 02 01:49:34 PM PDT 24
Peak memory 220992 kb
Host smart-be034144-95f2-4fc4-8b85-5e42f27afe41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699130056 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1699130056
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.2593328721
Short name T139
Test name
Test status
Simulation time 20428312 ps
CPU time 0.84 seconds
Started Apr 02 01:37:16 PM PDT 24
Finished Apr 02 01:37:17 PM PDT 24
Peak memory 205520 kb
Host smart-9de96f23-f14d-490a-b04f-4034953e20b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593328721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2593328721
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2231957174
Short name T146
Test name
Test status
Simulation time 28133777 ps
CPU time 0.81 seconds
Started Apr 02 01:37:15 PM PDT 24
Finished Apr 02 01:37:16 PM PDT 24
Peak memory 215820 kb
Host smart-55720d18-cbe1-4fad-8937-6b97979b1341
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231957174 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2231957174
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.156901874
Short name T313
Test name
Test status
Simulation time 42579508 ps
CPU time 0.95 seconds
Started Apr 02 01:37:15 PM PDT 24
Finished Apr 02 01:37:16 PM PDT 24
Peak memory 217512 kb
Host smart-a0fc48c2-eb19-42d1-8557-05ecf2e974d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156901874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.156901874
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_genbits.1496211830
Short name T388
Test name
Test status
Simulation time 73030430 ps
CPU time 1.82 seconds
Started Apr 02 01:37:14 PM PDT 24
Finished Apr 02 01:37:16 PM PDT 24
Peak memory 218000 kb
Host smart-4b0dbf36-4062-48d4-b06a-9424ad435717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496211830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1496211830
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2413267800
Short name T129
Test name
Test status
Simulation time 22537845 ps
CPU time 0.95 seconds
Started Apr 02 01:37:15 PM PDT 24
Finished Apr 02 01:37:16 PM PDT 24
Peak memory 215692 kb
Host smart-984cb09f-2093-491f-96e1-3272e0edc11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413267800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2413267800
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3590819826
Short name T354
Test name
Test status
Simulation time 36199526 ps
CPU time 0.96 seconds
Started Apr 02 01:37:11 PM PDT 24
Finished Apr 02 01:37:12 PM PDT 24
Peak memory 215336 kb
Host smart-38177756-03cf-47c7-a179-62c1d3f7a7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590819826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3590819826
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1792484270
Short name T713
Test name
Test status
Simulation time 656430523 ps
CPU time 2.11 seconds
Started Apr 02 01:37:12 PM PDT 24
Finished Apr 02 01:37:15 PM PDT 24
Peak memory 219044 kb
Host smart-3730f4ad-5a24-4ac0-8b34-370120f6cd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792484270 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1792484270
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4099531302
Short name T179
Test name
Test status
Simulation time 15657934480 ps
CPU time 356.05 seconds
Started Apr 02 01:37:14 PM PDT 24
Finished Apr 02 01:43:10 PM PDT 24
Peak memory 218388 kb
Host smart-957dab8b-ecda-419a-946a-bb7d669e3261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099531302 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4099531302
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2900160916
Short name T270
Test name
Test status
Simulation time 27228531 ps
CPU time 1.23 seconds
Started Apr 02 01:37:16 PM PDT 24
Finished Apr 02 01:37:18 PM PDT 24
Peak memory 215628 kb
Host smart-f9665e08-5ee6-4b8b-98c1-68067854a76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900160916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2900160916
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1691657085
Short name T564
Test name
Test status
Simulation time 13039038 ps
CPU time 0.9 seconds
Started Apr 02 01:37:19 PM PDT 24
Finished Apr 02 01:37:20 PM PDT 24
Peak memory 205768 kb
Host smart-79e08865-4fa1-4074-941a-823d5630633e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691657085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1691657085
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2250720294
Short name T499
Test name
Test status
Simulation time 40413236 ps
CPU time 0.85 seconds
Started Apr 02 01:37:19 PM PDT 24
Finished Apr 02 01:37:20 PM PDT 24
Peak memory 215372 kb
Host smart-938470b1-9be0-48bd-ad5e-f98f6870f819
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250720294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2250720294
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.993485430
Short name T78
Test name
Test status
Simulation time 72603435 ps
CPU time 1.03 seconds
Started Apr 02 01:37:16 PM PDT 24
Finished Apr 02 01:37:18 PM PDT 24
Peak memory 216324 kb
Host smart-3fd0ceb3-20c0-412b-9f75-4b466f3ae761
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993485430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.993485430
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3912972489
Short name T66
Test name
Test status
Simulation time 32812721 ps
CPU time 1.09 seconds
Started Apr 02 01:37:18 PM PDT 24
Finished Apr 02 01:37:19 PM PDT 24
Peak memory 219012 kb
Host smart-76d801dc-5559-4525-ba0f-87c97bed5eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912972489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3912972489
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.529761554
Short name T463
Test name
Test status
Simulation time 688700463 ps
CPU time 5.55 seconds
Started Apr 02 01:37:19 PM PDT 24
Finished Apr 02 01:37:25 PM PDT 24
Peak memory 216880 kb
Host smart-d1de8801-a64e-49de-b1f7-910f2eedbe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529761554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.529761554
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3066411247
Short name T588
Test name
Test status
Simulation time 22872760 ps
CPU time 1.21 seconds
Started Apr 02 01:37:18 PM PDT 24
Finished Apr 02 01:37:20 PM PDT 24
Peak memory 224036 kb
Host smart-e759cfc5-6548-4838-86fc-22d1745e3873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066411247 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3066411247
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3466666411
Short name T503
Test name
Test status
Simulation time 18949785 ps
CPU time 0.94 seconds
Started Apr 02 01:37:14 PM PDT 24
Finished Apr 02 01:37:15 PM PDT 24
Peak memory 215328 kb
Host smart-594194a2-d122-4613-b6ca-dc081c7d6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466666411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3466666411
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1284433195
Short name T497
Test name
Test status
Simulation time 163008461 ps
CPU time 3.38 seconds
Started Apr 02 01:37:16 PM PDT 24
Finished Apr 02 01:37:21 PM PDT 24
Peak memory 216652 kb
Host smart-f90ceb5b-8a79-47ce-9c93-27c68d8fae61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284433195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1284433195
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4058108668
Short name T607
Test name
Test status
Simulation time 50525121259 ps
CPU time 657.63 seconds
Started Apr 02 01:37:16 PM PDT 24
Finished Apr 02 01:48:14 PM PDT 24
Peak memory 218416 kb
Host smart-0d2b8d20-f321-4d88-b69e-64cfc88d2582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058108668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4058108668
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3241922240
Short name T267
Test name
Test status
Simulation time 47042051 ps
CPU time 1.24 seconds
Started Apr 02 01:37:20 PM PDT 24
Finished Apr 02 01:37:21 PM PDT 24
Peak memory 215600 kb
Host smart-0f82e5ed-3591-45e3-a50b-847bd74a7c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241922240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3241922240
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1729845121
Short name T730
Test name
Test status
Simulation time 67738371 ps
CPU time 0.88 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:37:27 PM PDT 24
Peak memory 206580 kb
Host smart-395b6344-f3cf-44a2-a9aa-f2e139526438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729845121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1729845121
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_err.1274787725
Short name T761
Test name
Test status
Simulation time 23621061 ps
CPU time 0.93 seconds
Started Apr 02 01:37:19 PM PDT 24
Finished Apr 02 01:37:20 PM PDT 24
Peak memory 217672 kb
Host smart-4612eace-d98d-4661-90e1-11e2091d61ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274787725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1274787725
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3659184019
Short name T349
Test name
Test status
Simulation time 94727198 ps
CPU time 1.08 seconds
Started Apr 02 01:37:19 PM PDT 24
Finished Apr 02 01:37:21 PM PDT 24
Peak memory 216704 kb
Host smart-74efcb7a-81a6-4894-a2b1-39f009d95851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659184019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3659184019
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1121108055
Short name T695
Test name
Test status
Simulation time 21888375 ps
CPU time 1.12 seconds
Started Apr 02 01:37:21 PM PDT 24
Finished Apr 02 01:37:23 PM PDT 24
Peak memory 215484 kb
Host smart-c2f96e5e-bd69-4673-9980-60d839706ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121108055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1121108055
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1061249614
Short name T752
Test name
Test status
Simulation time 18802128 ps
CPU time 1.03 seconds
Started Apr 02 01:37:17 PM PDT 24
Finished Apr 02 01:37:19 PM PDT 24
Peak memory 215332 kb
Host smart-c1251433-5753-4ae2-ba2f-516ba5006ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061249614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1061249614
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2148263526
Short name T21
Test name
Test status
Simulation time 453708292 ps
CPU time 2.84 seconds
Started Apr 02 01:37:18 PM PDT 24
Finished Apr 02 01:37:22 PM PDT 24
Peak memory 216484 kb
Host smart-7017b00a-f4ea-4758-9875-d1e7491b9361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148263526 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2148263526
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.39841130
Short name T433
Test name
Test status
Simulation time 127022918543 ps
CPU time 852.54 seconds
Started Apr 02 01:37:21 PM PDT 24
Finished Apr 02 01:51:34 PM PDT 24
Peak memory 222292 kb
Host smart-cfb21c68-99e9-4053-8e19-0d769db5b009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841130 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.39841130
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1693357252
Short name T660
Test name
Test status
Simulation time 321007014 ps
CPU time 1.51 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:37:27 PM PDT 24
Peak memory 215592 kb
Host smart-3c77c900-981d-4ee0-aaf1-6f3ba67756fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693357252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1693357252
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2671987519
Short name T38
Test name
Test status
Simulation time 27211235 ps
CPU time 0.88 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 205992 kb
Host smart-4585803a-4609-4efe-8bf0-0748cb629bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671987519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2671987519
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3283039816
Short name T679
Test name
Test status
Simulation time 20753651 ps
CPU time 0.83 seconds
Started Apr 02 01:37:24 PM PDT 24
Finished Apr 02 01:37:25 PM PDT 24
Peak memory 215372 kb
Host smart-178cc00f-3925-476d-8970-26b2f17942a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283039816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3283039816
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2845424908
Short name T823
Test name
Test status
Simulation time 178041580 ps
CPU time 1.23 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:37:26 PM PDT 24
Peak memory 216532 kb
Host smart-58b5912e-98ae-4efd-83b9-8cb4861e37fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845424908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2845424908
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1226483316
Short name T493
Test name
Test status
Simulation time 33949907 ps
CPU time 0.91 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 217784 kb
Host smart-66591716-f8b5-44cc-943c-2db3f747b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226483316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1226483316
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1971095437
Short name T326
Test name
Test status
Simulation time 45866481 ps
CPU time 1.33 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:37:26 PM PDT 24
Peak memory 218064 kb
Host smart-25579ca2-7ebc-4a2e-afb9-07a44ba1f4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971095437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1971095437
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1978635393
Short name T42
Test name
Test status
Simulation time 25233834 ps
CPU time 1.09 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 224120 kb
Host smart-c2481ffb-9b60-4307-84d3-7fe94656f20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978635393 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1978635393
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3297115988
Short name T449
Test name
Test status
Simulation time 45647681 ps
CPU time 0.92 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:37:26 PM PDT 24
Peak memory 215276 kb
Host smart-56016f46-504e-4842-a488-8ad7cbcff4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297115988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3297115988
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2247489001
Short name T784
Test name
Test status
Simulation time 145595263 ps
CPU time 3.17 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:31 PM PDT 24
Peak memory 217688 kb
Host smart-a55cd80c-abf5-401b-ba93-e063f41ec0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247489001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2247489001
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1815236730
Short name T232
Test name
Test status
Simulation time 22859523119 ps
CPU time 507.25 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:45:54 PM PDT 24
Peak memory 217988 kb
Host smart-c94efea3-0986-49c2-a8de-93b3e1f53b70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815236730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1815236730
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1247805592
Short name T573
Test name
Test status
Simulation time 372797628 ps
CPU time 1.37 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:37:28 PM PDT 24
Peak memory 215596 kb
Host smart-6eb03414-633e-48b5-9ec5-a3b7ebbce6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247805592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1247805592
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2198249648
Short name T545
Test name
Test status
Simulation time 23638620 ps
CPU time 0.85 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 205952 kb
Host smart-be912214-1ff6-4df2-ad77-4c8b509b605e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198249648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2198249648
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2025050657
Short name T145
Test name
Test status
Simulation time 12708752 ps
CPU time 0.9 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:37:27 PM PDT 24
Peak memory 216008 kb
Host smart-97833a75-73bc-46a3-bacb-6d85aa0db36f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025050657 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2025050657
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.3605261016
Short name T149
Test name
Test status
Simulation time 18731681 ps
CPU time 1.08 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:37:27 PM PDT 24
Peak memory 218192 kb
Host smart-07df87a2-3fb7-4387-940e-429916749bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605261016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3605261016
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.289022659
Short name T320
Test name
Test status
Simulation time 33551933 ps
CPU time 1.29 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:37:27 PM PDT 24
Peak memory 216404 kb
Host smart-d40cbaad-52ea-42f8-a766-1001ed7f492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289022659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.289022659
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.635015116
Short name T363
Test name
Test status
Simulation time 24923511 ps
CPU time 0.96 seconds
Started Apr 02 01:37:24 PM PDT 24
Finished Apr 02 01:37:25 PM PDT 24
Peak memory 215416 kb
Host smart-a82640d5-5f17-4752-8942-a941537893e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635015116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.635015116
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.951221802
Short name T767
Test name
Test status
Simulation time 36297700 ps
CPU time 0.94 seconds
Started Apr 02 01:37:24 PM PDT 24
Finished Apr 02 01:37:25 PM PDT 24
Peak memory 215312 kb
Host smart-4a7ba38a-6719-4315-9794-8e22d66556c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951221802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.951221802
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3527651350
Short name T694
Test name
Test status
Simulation time 72412290 ps
CPU time 1.39 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 215192 kb
Host smart-190b92b7-2ea1-4291-b7bb-b590baf224c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527651350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3527651350
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1808942032
Short name T665
Test name
Test status
Simulation time 110381338228 ps
CPU time 1284.19 seconds
Started Apr 02 01:37:25 PM PDT 24
Finished Apr 02 01:58:49 PM PDT 24
Peak memory 222996 kb
Host smart-a24362c8-06c4-431f-81c7-de98b2aca56b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808942032 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1808942032
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2577805873
Short name T167
Test name
Test status
Simulation time 127826786 ps
CPU time 1.18 seconds
Started Apr 02 01:37:27 PM PDT 24
Finished Apr 02 01:37:28 PM PDT 24
Peak memory 215644 kb
Host smart-9ab7c243-944a-4385-b5f4-2f629b34b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577805873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2577805873
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1665707961
Short name T378
Test name
Test status
Simulation time 22591755 ps
CPU time 0.9 seconds
Started Apr 02 01:37:39 PM PDT 24
Finished Apr 02 01:37:40 PM PDT 24
Peak memory 205660 kb
Host smart-73ceb349-337c-4ed5-bb28-537d2c410f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665707961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1665707961
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3975386255
Short name T136
Test name
Test status
Simulation time 13624660 ps
CPU time 0.86 seconds
Started Apr 02 01:37:30 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 215484 kb
Host smart-499fe906-0327-4e98-8557-4b70aedb946d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975386255 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3975386255
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3896458339
Short name T143
Test name
Test status
Simulation time 261069981 ps
CPU time 0.96 seconds
Started Apr 02 01:37:39 PM PDT 24
Finished Apr 02 01:37:40 PM PDT 24
Peak memory 217428 kb
Host smart-d74fb5bc-addd-4a06-aa9b-2837f7db5eed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896458339 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3896458339
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.426552792
Short name T536
Test name
Test status
Simulation time 152822728 ps
CPU time 1.01 seconds
Started Apr 02 01:37:35 PM PDT 24
Finished Apr 02 01:37:36 PM PDT 24
Peak memory 231368 kb
Host smart-fd407da3-3dfe-40a7-8da9-b6e62a696e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426552792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.426552792
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.111795386
Short name T436
Test name
Test status
Simulation time 53959580 ps
CPU time 1.25 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:37:28 PM PDT 24
Peak memory 216812 kb
Host smart-eab58f89-65d5-4535-b46c-ebd22caa975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111795386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.111795386
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1377190097
Short name T722
Test name
Test status
Simulation time 64101923 ps
CPU time 0.88 seconds
Started Apr 02 01:37:27 PM PDT 24
Finished Apr 02 01:37:28 PM PDT 24
Peak memory 215284 kb
Host smart-caf9d10c-5153-4e0f-a819-5a28c1367746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377190097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1377190097
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2265702305
Short name T230
Test name
Test status
Simulation time 222501638 ps
CPU time 0.98 seconds
Started Apr 02 01:37:28 PM PDT 24
Finished Apr 02 01:37:29 PM PDT 24
Peak memory 215260 kb
Host smart-1bf652d0-26cf-49a1-923e-51e0f551264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265702305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2265702305
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.421494531
Short name T192
Test name
Test status
Simulation time 740318096 ps
CPU time 4.69 seconds
Started Apr 02 01:37:26 PM PDT 24
Finished Apr 02 01:37:31 PM PDT 24
Peak memory 216364 kb
Host smart-1f29d170-374b-4058-8b52-1b8e44063cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421494531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.421494531
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2545568214
Short name T448
Test name
Test status
Simulation time 573800989389 ps
CPU time 977.31 seconds
Started Apr 02 01:37:29 PM PDT 24
Finished Apr 02 01:53:47 PM PDT 24
Peak memory 221756 kb
Host smart-87becd67-905d-4e38-b7ef-eacc8b4a991c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545568214 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2545568214
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.177955361
Short name T729
Test name
Test status
Simulation time 165334904 ps
CPU time 1.28 seconds
Started Apr 02 01:37:33 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 215460 kb
Host smart-5ccfd1c0-f6ad-4f39-8dc5-78599a6e7cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177955361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.177955361
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1080930512
Short name T759
Test name
Test status
Simulation time 54003651 ps
CPU time 0.89 seconds
Started Apr 02 01:37:31 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 205880 kb
Host smart-f15c2460-8e8c-4b5f-8052-1f77bb30cc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080930512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1080930512
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4137127536
Short name T833
Test name
Test status
Simulation time 30095546 ps
CPU time 1.1 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 216352 kb
Host smart-f367fbc7-8470-40f9-b9d7-3b8e8a41045e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137127536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4137127536
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3748178017
Short name T444
Test name
Test status
Simulation time 33702545 ps
CPU time 0.98 seconds
Started Apr 02 01:37:30 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 222876 kb
Host smart-03c200fc-12a4-4139-aa11-ee6313faa878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748178017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3748178017
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2417069171
Short name T387
Test name
Test status
Simulation time 46695134 ps
CPU time 1.28 seconds
Started Apr 02 01:37:34 PM PDT 24
Finished Apr 02 01:37:36 PM PDT 24
Peak memory 216708 kb
Host smart-d2feab2b-e4af-43bb-a3aa-2c8fbe24a3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417069171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2417069171
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1893985864
Short name T117
Test name
Test status
Simulation time 21211411 ps
CPU time 1.11 seconds
Started Apr 02 01:37:32 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 215548 kb
Host smart-320523b5-e61a-43c5-bfed-cc20936bb64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893985864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1893985864
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.508452008
Short name T434
Test name
Test status
Simulation time 43061464 ps
CPU time 0.91 seconds
Started Apr 02 01:37:32 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 215224 kb
Host smart-6cbead2c-4ea1-4fd4-8ac5-8828d96a7930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508452008 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.508452008
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2746693134
Short name T5
Test name
Test status
Simulation time 76419038 ps
CPU time 1.4 seconds
Started Apr 02 01:37:30 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 215292 kb
Host smart-31bf7a96-d6d6-4d84-aed1-d65186245b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746693134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2746693134
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1128867723
Short name T799
Test name
Test status
Simulation time 15577444977 ps
CPU time 381.06 seconds
Started Apr 02 01:37:31 PM PDT 24
Finished Apr 02 01:43:54 PM PDT 24
Peak memory 218320 kb
Host smart-db310ef3-48f4-4ed0-af01-4929604b30db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128867723 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1128867723
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3258730223
Short name T2
Test name
Test status
Simulation time 43239202 ps
CPU time 1.15 seconds
Started Apr 02 01:34:57 PM PDT 24
Finished Apr 02 01:34:58 PM PDT 24
Peak memory 215660 kb
Host smart-87dad008-f649-4a8b-9aa3-4f8b74ee85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258730223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3258730223
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2027398777
Short name T485
Test name
Test status
Simulation time 51851745 ps
CPU time 0.89 seconds
Started Apr 02 01:34:56 PM PDT 24
Finished Apr 02 01:34:58 PM PDT 24
Peak memory 205816 kb
Host smart-6104b7cd-877e-4291-b4aa-47cce68d2604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027398777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2027398777
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1337019194
Short name T460
Test name
Test status
Simulation time 21034154 ps
CPU time 0.85 seconds
Started Apr 02 01:34:58 PM PDT 24
Finished Apr 02 01:34:59 PM PDT 24
Peak memory 215340 kb
Host smart-0c267c0e-7061-4451-b5b4-88bfb6304cb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337019194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1337019194
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2581577910
Short name T528
Test name
Test status
Simulation time 54477469 ps
CPU time 1.18 seconds
Started Apr 02 01:34:57 PM PDT 24
Finished Apr 02 01:34:58 PM PDT 24
Peak memory 217804 kb
Host smart-7825ec46-c904-4b1f-a9c8-ae60c44b56d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581577910 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2581577910
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2661059097
Short name T73
Test name
Test status
Simulation time 25334211 ps
CPU time 0.99 seconds
Started Apr 02 01:34:57 PM PDT 24
Finished Apr 02 01:34:58 PM PDT 24
Peak memory 219012 kb
Host smart-9e7f2512-682e-4d65-a5bb-8e21f3a00e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661059097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2661059097
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4171785745
Short name T246
Test name
Test status
Simulation time 101845034 ps
CPU time 1.09 seconds
Started Apr 02 01:34:53 PM PDT 24
Finished Apr 02 01:34:56 PM PDT 24
Peak memory 216504 kb
Host smart-37ccac54-960a-4605-8bae-362bba937bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171785745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4171785745
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3019384576
Short name T522
Test name
Test status
Simulation time 36256545 ps
CPU time 0.96 seconds
Started Apr 02 01:34:59 PM PDT 24
Finished Apr 02 01:35:00 PM PDT 24
Peak memory 224044 kb
Host smart-3a62fc7f-3eac-4c19-b06a-717e281ea41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019384576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3019384576
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2735215287
Short name T255
Test name
Test status
Simulation time 28079624 ps
CPU time 0.94 seconds
Started Apr 02 01:34:53 PM PDT 24
Finished Apr 02 01:34:55 PM PDT 24
Peak memory 207084 kb
Host smart-b4a9d91a-db8a-43b3-b83d-d1b43dd3d78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735215287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2735215287
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1206326006
Short name T512
Test name
Test status
Simulation time 66199710 ps
CPU time 0.86 seconds
Started Apr 02 01:34:49 PM PDT 24
Finished Apr 02 01:34:50 PM PDT 24
Peak memory 215328 kb
Host smart-1ac637b4-1c39-4aa2-806d-9f514487a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206326006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1206326006
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.262763709
Short name T771
Test name
Test status
Simulation time 198525815 ps
CPU time 4.43 seconds
Started Apr 02 01:34:57 PM PDT 24
Finished Apr 02 01:35:02 PM PDT 24
Peak memory 215304 kb
Host smart-b1785cf6-d20c-4ef4-af96-9b48a874600e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262763709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.262763709
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3318730647
Short name T186
Test name
Test status
Simulation time 107248069041 ps
CPU time 631.08 seconds
Started Apr 02 01:34:59 PM PDT 24
Finished Apr 02 01:45:30 PM PDT 24
Peak memory 219064 kb
Host smart-c483dfe6-977a-443c-872f-3d0eb05d8418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318730647 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3318730647
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.184555915
Short name T746
Test name
Test status
Simulation time 22015431 ps
CPU time 0.94 seconds
Started Apr 02 01:37:32 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 218148 kb
Host smart-80bb8283-2d3c-4a55-a7e8-fc5074a70ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184555915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.184555915
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2518657708
Short name T412
Test name
Test status
Simulation time 141328470 ps
CPU time 1.91 seconds
Started Apr 02 01:37:29 PM PDT 24
Finished Apr 02 01:37:31 PM PDT 24
Peak memory 219056 kb
Host smart-212074c6-b221-4b1d-82d1-571402cd5139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518657708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2518657708
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.623628402
Short name T365
Test name
Test status
Simulation time 18308009 ps
CPU time 1.21 seconds
Started Apr 02 01:37:41 PM PDT 24
Finished Apr 02 01:37:42 PM PDT 24
Peak memory 232472 kb
Host smart-b13871c8-b6ba-40ab-a83a-88172f2bc0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623628402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.623628402
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3267615149
Short name T402
Test name
Test status
Simulation time 45012728 ps
CPU time 1.18 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 216468 kb
Host smart-98a77bbf-4fc9-41f5-a286-af13582821e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267615149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3267615149
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2727842063
Short name T544
Test name
Test status
Simulation time 20906088 ps
CPU time 1.14 seconds
Started Apr 02 01:37:30 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 219376 kb
Host smart-341168fa-490c-4380-b410-4548ca812920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727842063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2727842063
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2533056164
Short name T565
Test name
Test status
Simulation time 66230702 ps
CPU time 1.36 seconds
Started Apr 02 01:37:30 PM PDT 24
Finished Apr 02 01:37:32 PM PDT 24
Peak memory 219248 kb
Host smart-6b7df796-1f0a-4a9f-9378-1614f5f58625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533056164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2533056164
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1775479334
Short name T105
Test name
Test status
Simulation time 33552173 ps
CPU time 1.1 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 231116 kb
Host smart-bad5317c-1586-4fe5-a9ea-ff752831f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775479334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1775479334
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3301813297
Short name T408
Test name
Test status
Simulation time 118331031 ps
CPU time 1.47 seconds
Started Apr 02 01:37:31 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 216488 kb
Host smart-d509b6d6-5777-4945-843a-cbe03637b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301813297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3301813297
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2281047274
Short name T72
Test name
Test status
Simulation time 25448733 ps
CPU time 1.3 seconds
Started Apr 02 01:37:36 PM PDT 24
Finished Apr 02 01:37:38 PM PDT 24
Peak memory 229792 kb
Host smart-44fc52cd-91a4-4dfa-a412-1bc9c1c5e116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281047274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2281047274
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1268026005
Short name T783
Test name
Test status
Simulation time 52404237 ps
CPU time 1.66 seconds
Started Apr 02 01:37:33 PM PDT 24
Finished Apr 02 01:37:35 PM PDT 24
Peak memory 217728 kb
Host smart-dee0f882-5622-4e62-bbae-2ff50c8e46a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268026005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1268026005
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1604395020
Short name T81
Test name
Test status
Simulation time 26638925 ps
CPU time 1.29 seconds
Started Apr 02 01:37:34 PM PDT 24
Finished Apr 02 01:37:35 PM PDT 24
Peak memory 232556 kb
Host smart-18c447c3-1119-4710-bfc7-9e5188160256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604395020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1604395020
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2472629830
Short name T693
Test name
Test status
Simulation time 50218089 ps
CPU time 1.34 seconds
Started Apr 02 01:37:34 PM PDT 24
Finished Apr 02 01:37:36 PM PDT 24
Peak memory 218184 kb
Host smart-6e2f3e7e-bb5a-4a98-ae7c-fd268097bb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472629830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2472629830
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1990124473
Short name T529
Test name
Test status
Simulation time 32852826 ps
CPU time 0.96 seconds
Started Apr 02 01:37:32 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 231108 kb
Host smart-ef7088f5-04c8-422f-9ffa-ae9af11357e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990124473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1990124473
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.916970384
Short name T818
Test name
Test status
Simulation time 136495688 ps
CPU time 1.82 seconds
Started Apr 02 01:37:32 PM PDT 24
Finished Apr 02 01:37:35 PM PDT 24
Peak memory 218204 kb
Host smart-e92cd092-b1dd-4669-a8e6-a1bbbc54c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916970384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.916970384
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2286383839
Short name T634
Test name
Test status
Simulation time 22142942 ps
CPU time 0.93 seconds
Started Apr 02 01:37:36 PM PDT 24
Finished Apr 02 01:37:37 PM PDT 24
Peak memory 217796 kb
Host smart-9753a044-78d8-4e02-85d2-e9a9b9622cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286383839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2286383839
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.230847455
Short name T119
Test name
Test status
Simulation time 36186978 ps
CPU time 1.06 seconds
Started Apr 02 01:37:36 PM PDT 24
Finished Apr 02 01:37:38 PM PDT 24
Peak memory 216508 kb
Host smart-b31a0b8a-84d6-4bd0-bd63-e894c1a140f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230847455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.230847455
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3374206205
Short name T546
Test name
Test status
Simulation time 33576833 ps
CPU time 0.86 seconds
Started Apr 02 01:37:35 PM PDT 24
Finished Apr 02 01:37:36 PM PDT 24
Peak memory 217596 kb
Host smart-a5aeffe5-a4b1-47c6-af5b-ce60c3fde202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374206205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3374206205
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1687567548
Short name T792
Test name
Test status
Simulation time 57855058 ps
CPU time 1.32 seconds
Started Apr 02 01:37:35 PM PDT 24
Finished Apr 02 01:37:37 PM PDT 24
Peak memory 217908 kb
Host smart-305d03e7-a4b1-441f-acd2-5cc0572698e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687567548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1687567548
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2035396392
Short name T101
Test name
Test status
Simulation time 30922244 ps
CPU time 0.81 seconds
Started Apr 02 01:37:36 PM PDT 24
Finished Apr 02 01:37:36 PM PDT 24
Peak memory 217824 kb
Host smart-618d322a-6141-4474-b259-c8af0f774335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035396392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2035396392
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3983173766
Short name T723
Test name
Test status
Simulation time 51612269 ps
CPU time 1.25 seconds
Started Apr 02 01:37:32 PM PDT 24
Finished Apr 02 01:37:34 PM PDT 24
Peak memory 216496 kb
Host smart-36579567-81a3-4cb8-83c0-685c0b58591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983173766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3983173766
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2230155990
Short name T770
Test name
Test status
Simulation time 119202523 ps
CPU time 1.19 seconds
Started Apr 02 01:35:01 PM PDT 24
Finished Apr 02 01:35:02 PM PDT 24
Peak memory 215532 kb
Host smart-d5b0f3b0-2b78-4d89-a8a5-b0859e98e1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230155990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2230155990
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2049382082
Short name T315
Test name
Test status
Simulation time 16584367 ps
CPU time 0.95 seconds
Started Apr 02 01:35:03 PM PDT 24
Finished Apr 02 01:35:04 PM PDT 24
Peak memory 205956 kb
Host smart-677a09e2-316d-4783-bf76-9357c1469d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049382082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2049382082
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3643859912
Short name T98
Test name
Test status
Simulation time 13427262 ps
CPU time 0.89 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:04 PM PDT 24
Peak memory 216124 kb
Host smart-7b6391ba-b74c-4335-b4b1-c678828459c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643859912 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3643859912
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1576822712
Short name T345
Test name
Test status
Simulation time 29068973 ps
CPU time 1.15 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:03 PM PDT 24
Peak memory 216508 kb
Host smart-6e7015c6-47f6-43ea-93f4-750c35f823ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576822712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1576822712
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1421320863
Short name T306
Test name
Test status
Simulation time 18583067 ps
CPU time 1.06 seconds
Started Apr 02 01:35:00 PM PDT 24
Finished Apr 02 01:35:02 PM PDT 24
Peak memory 218080 kb
Host smart-b0eddba1-09ff-497d-88fd-138bb0010a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421320863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1421320863
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.374288125
Short name T385
Test name
Test status
Simulation time 121928421 ps
CPU time 1.63 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:04 PM PDT 24
Peak memory 218224 kb
Host smart-0b59c254-0958-4312-accb-cdc74e0deb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374288125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.374288125
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.4087576052
Short name T595
Test name
Test status
Simulation time 30472585 ps
CPU time 1.01 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:03 PM PDT 24
Peak memory 215652 kb
Host smart-459589cb-0aed-4366-8351-9b74a1cfa7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087576052 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.4087576052
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2482037257
Short name T642
Test name
Test status
Simulation time 24999415 ps
CPU time 0.98 seconds
Started Apr 02 01:34:57 PM PDT 24
Finished Apr 02 01:34:58 PM PDT 24
Peak memory 207128 kb
Host smart-672253fb-e8b7-4bdc-bb04-2748481132a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482037257 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2482037257
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2194382273
Short name T322
Test name
Test status
Simulation time 58000482 ps
CPU time 0.87 seconds
Started Apr 02 01:34:57 PM PDT 24
Finished Apr 02 01:34:58 PM PDT 24
Peak memory 215264 kb
Host smart-6be2f48b-0761-4693-b9e8-b2e73b1f301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194382273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2194382273
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2730215862
Short name T194
Test name
Test status
Simulation time 221668611 ps
CPU time 4.64 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 216484 kb
Host smart-aa638cac-240d-47d9-be6e-667ba460d746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730215862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2730215862
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2646077508
Short name T190
Test name
Test status
Simulation time 631455867509 ps
CPU time 765.53 seconds
Started Apr 02 01:35:01 PM PDT 24
Finished Apr 02 01:47:47 PM PDT 24
Peak memory 219424 kb
Host smart-2804571c-bcc8-4b98-83d3-75bdb85a020d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646077508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2646077508
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.4179169544
Short name T152
Test name
Test status
Simulation time 28408387 ps
CPU time 1.25 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 219184 kb
Host smart-53b0c8cf-3067-4e6f-9f84-7907424a8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179169544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.4179169544
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2484377123
Short name T521
Test name
Test status
Simulation time 51693853 ps
CPU time 1.37 seconds
Started Apr 02 01:37:38 PM PDT 24
Finished Apr 02 01:37:39 PM PDT 24
Peak memory 218172 kb
Host smart-838b75a0-0ea8-402c-97bc-fa3471b54529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484377123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2484377123
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.542652196
Short name T374
Test name
Test status
Simulation time 19507815 ps
CPU time 1.04 seconds
Started Apr 02 01:37:41 PM PDT 24
Finished Apr 02 01:37:42 PM PDT 24
Peak memory 218044 kb
Host smart-021ef75e-e47a-4b9a-83da-6e5273db5c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542652196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.542652196
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3400762823
Short name T283
Test name
Test status
Simulation time 42581512 ps
CPU time 1.66 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:42 PM PDT 24
Peak memory 218884 kb
Host smart-1c560112-c729-4cbe-ae29-b64a7a31b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400762823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3400762823
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3181487996
Short name T76
Test name
Test status
Simulation time 24942284 ps
CPU time 1.17 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 219392 kb
Host smart-46f2aa9a-9d98-4eaf-98a6-824279f413f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181487996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3181487996
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2275216851
Short name T765
Test name
Test status
Simulation time 207392368 ps
CPU time 1.8 seconds
Started Apr 02 01:37:41 PM PDT 24
Finished Apr 02 01:37:43 PM PDT 24
Peak memory 218256 kb
Host smart-00049cf5-1a09-4770-b2c8-12cef0333e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275216851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2275216851
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3305396845
Short name T716
Test name
Test status
Simulation time 90853003 ps
CPU time 1.15 seconds
Started Apr 02 01:37:46 PM PDT 24
Finished Apr 02 01:37:47 PM PDT 24
Peak memory 232156 kb
Host smart-8459ec08-4dcf-49a8-a563-c3a174ed8b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305396845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3305396845
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2640069741
Short name T636
Test name
Test status
Simulation time 155188021 ps
CPU time 2.47 seconds
Started Apr 02 01:37:42 PM PDT 24
Finished Apr 02 01:37:45 PM PDT 24
Peak memory 219500 kb
Host smart-30278ea1-3eba-4ee8-b26a-b1414d06217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640069741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2640069741
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3744604161
Short name T85
Test name
Test status
Simulation time 32386796 ps
CPU time 0.85 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 217576 kb
Host smart-aed509b9-f0b5-465c-958f-fc3001e985e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744604161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3744604161
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3603146881
Short name T476
Test name
Test status
Simulation time 82968165 ps
CPU time 1.23 seconds
Started Apr 02 01:37:39 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 216928 kb
Host smart-a4a47138-7ab0-492d-894e-275644b17071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603146881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3603146881
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3383730561
Short name T786
Test name
Test status
Simulation time 20761397 ps
CPU time 1.04 seconds
Started Apr 02 01:37:40 PM PDT 24
Finished Apr 02 01:37:41 PM PDT 24
Peak memory 218140 kb
Host smart-3788ac50-9b0a-4792-93e5-a588a440830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383730561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3383730561
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1150554854
Short name T764
Test name
Test status
Simulation time 326200749 ps
CPU time 1.56 seconds
Started Apr 02 01:37:41 PM PDT 24
Finished Apr 02 01:37:43 PM PDT 24
Peak memory 218128 kb
Host smart-aec79727-0107-4ae7-88c2-086006166238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150554854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1150554854
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.764150414
Short name T390
Test name
Test status
Simulation time 20299124 ps
CPU time 1.09 seconds
Started Apr 02 01:37:43 PM PDT 24
Finished Apr 02 01:37:44 PM PDT 24
Peak memory 218028 kb
Host smart-8f0d4b49-d630-473f-a23a-a95e709a9cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764150414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.764150414
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2446558442
Short name T766
Test name
Test status
Simulation time 54995403 ps
CPU time 2.05 seconds
Started Apr 02 01:37:39 PM PDT 24
Finished Apr 02 01:37:42 PM PDT 24
Peak memory 216896 kb
Host smart-2bec8db5-c188-401b-9cab-892ddfd50790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446558442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2446558442
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.60802208
Short name T557
Test name
Test status
Simulation time 29825679 ps
CPU time 1.34 seconds
Started Apr 02 01:37:49 PM PDT 24
Finished Apr 02 01:37:50 PM PDT 24
Peak memory 233616 kb
Host smart-1d4db8d0-e59d-4859-832b-31b77a677016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60802208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.60802208
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3972870662
Short name T617
Test name
Test status
Simulation time 84487819 ps
CPU time 1.13 seconds
Started Apr 02 01:37:43 PM PDT 24
Finished Apr 02 01:37:44 PM PDT 24
Peak memory 216652 kb
Host smart-7ea72aac-4949-4e31-8d45-f2e1fdf434b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972870662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3972870662
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2638503070
Short name T74
Test name
Test status
Simulation time 81023060 ps
CPU time 0.9 seconds
Started Apr 02 01:37:42 PM PDT 24
Finished Apr 02 01:37:43 PM PDT 24
Peak memory 219232 kb
Host smart-a74d0e08-970c-467a-a665-e31c01166093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638503070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2638503070
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2053709856
Short name T299
Test name
Test status
Simulation time 66624868 ps
CPU time 1.34 seconds
Started Apr 02 01:37:46 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 217800 kb
Host smart-8de8c2d6-5d48-44bf-a670-5fc89269601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053709856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2053709856
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.452184526
Short name T662
Test name
Test status
Simulation time 29524069 ps
CPU time 0.86 seconds
Started Apr 02 01:37:43 PM PDT 24
Finished Apr 02 01:37:44 PM PDT 24
Peak memory 217448 kb
Host smart-88df0c1c-1e98-41b0-aa7b-49f603daf37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452184526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.452184526
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4249859859
Short name T135
Test name
Test status
Simulation time 102607712 ps
CPU time 1.15 seconds
Started Apr 02 01:37:49 PM PDT 24
Finished Apr 02 01:37:50 PM PDT 24
Peak memory 218048 kb
Host smart-3dadc604-f752-4627-9cf4-f3cb70f233ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249859859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4249859859
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2846954098
Short name T261
Test name
Test status
Simulation time 28804786 ps
CPU time 1.22 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:03 PM PDT 24
Peak memory 215616 kb
Host smart-69396614-eac0-47e9-a78d-7d182f4e97ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846954098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2846954098
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.271809324
Short name T193
Test name
Test status
Simulation time 13755317 ps
CPU time 0.88 seconds
Started Apr 02 01:35:05 PM PDT 24
Finished Apr 02 01:35:06 PM PDT 24
Peak memory 205648 kb
Host smart-7df5831e-3d4b-4dc4-b7da-9ba736c37455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271809324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.271809324
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3239166603
Short name T441
Test name
Test status
Simulation time 89275675 ps
CPU time 0.81 seconds
Started Apr 02 01:35:07 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 215964 kb
Host smart-dabf5a21-f164-4313-9297-f42a9cf9575a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239166603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3239166603
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2520571952
Short name T798
Test name
Test status
Simulation time 53612225 ps
CPU time 1.01 seconds
Started Apr 02 01:35:05 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 217844 kb
Host smart-20fc649e-3008-43aa-9709-6add322b649b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520571952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2520571952
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1130469050
Short name T555
Test name
Test status
Simulation time 44598140 ps
CPU time 1.1 seconds
Started Apr 02 01:35:03 PM PDT 24
Finished Apr 02 01:35:05 PM PDT 24
Peak memory 219124 kb
Host smart-03f9cd63-81cf-4007-953a-bf6328ee97cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130469050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1130469050
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1474740187
Short name T350
Test name
Test status
Simulation time 56229240 ps
CPU time 1.37 seconds
Started Apr 02 01:35:04 PM PDT 24
Finished Apr 02 01:35:05 PM PDT 24
Peak memory 215212 kb
Host smart-d489b9a2-3f50-4248-a62f-42e0c93ce2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474740187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1474740187
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.76961414
Short name T726
Test name
Test status
Simulation time 67982647 ps
CPU time 0.83 seconds
Started Apr 02 01:35:01 PM PDT 24
Finished Apr 02 01:35:02 PM PDT 24
Peak memory 215468 kb
Host smart-85425e9f-5f5f-416f-a303-5a029366f60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76961414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.76961414
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1556449364
Short name T254
Test name
Test status
Simulation time 18868317 ps
CPU time 0.98 seconds
Started Apr 02 01:35:05 PM PDT 24
Finished Apr 02 01:35:06 PM PDT 24
Peak memory 207128 kb
Host smart-27258b64-9f19-4980-9c66-9f8573b2ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556449364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1556449364
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3092330330
Short name T562
Test name
Test status
Simulation time 42679253 ps
CPU time 0.92 seconds
Started Apr 02 01:35:01 PM PDT 24
Finished Apr 02 01:35:03 PM PDT 24
Peak memory 215280 kb
Host smart-050fdeb7-2bbb-4efb-b8f8-a9364c032223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092330330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3092330330
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2142564486
Short name T540
Test name
Test status
Simulation time 328613113 ps
CPU time 3.63 seconds
Started Apr 02 01:35:02 PM PDT 24
Finished Apr 02 01:35:05 PM PDT 24
Peak memory 215264 kb
Host smart-95ce7848-00d3-4e21-868d-6aaab1ac934c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142564486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2142564486
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.391538591
Short name T791
Test name
Test status
Simulation time 113507052158 ps
CPU time 1358.3 seconds
Started Apr 02 01:35:01 PM PDT 24
Finished Apr 02 01:57:40 PM PDT 24
Peak memory 222024 kb
Host smart-03f1ee25-a8c9-4016-8f39-e242a0e3ee6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391538591 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.391538591
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.956664452
Short name T523
Test name
Test status
Simulation time 23932316 ps
CPU time 0.92 seconds
Started Apr 02 01:37:41 PM PDT 24
Finished Apr 02 01:37:42 PM PDT 24
Peak memory 217644 kb
Host smart-9c227909-8e4c-4018-92db-5c9e5e456e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956664452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.956664452
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.815228826
Short name T549
Test name
Test status
Simulation time 55373664 ps
CPU time 1.9 seconds
Started Apr 02 01:37:43 PM PDT 24
Finished Apr 02 01:37:45 PM PDT 24
Peak memory 217788 kb
Host smart-666378a7-8cfc-4547-976b-771e39afa1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815228826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.815228826
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1612961006
Short name T396
Test name
Test status
Simulation time 69542392 ps
CPU time 1.18 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 233596 kb
Host smart-7dfe9676-1ff4-4796-acca-b9e468346438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612961006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1612961006
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3904806665
Short name T757
Test name
Test status
Simulation time 2902291074 ps
CPU time 79.02 seconds
Started Apr 02 01:37:42 PM PDT 24
Finished Apr 02 01:39:01 PM PDT 24
Peak memory 216788 kb
Host smart-686c97a1-2ada-4e5d-ae1d-82799d408bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904806665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3904806665
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.36465340
Short name T494
Test name
Test status
Simulation time 75906278 ps
CPU time 1.09 seconds
Started Apr 02 01:37:46 PM PDT 24
Finished Apr 02 01:37:47 PM PDT 24
Peak memory 219164 kb
Host smart-0071df08-ce61-447f-91a2-80945686f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36465340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.36465340
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.157854880
Short name T534
Test name
Test status
Simulation time 86338888 ps
CPU time 1.29 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 217860 kb
Host smart-4d25beb6-9bf7-47c2-b050-f88ec83ed572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157854880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.157854880
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1374017963
Short name T91
Test name
Test status
Simulation time 23970600 ps
CPU time 1.03 seconds
Started Apr 02 01:37:45 PM PDT 24
Finished Apr 02 01:37:46 PM PDT 24
Peak memory 231292 kb
Host smart-4d043cbe-25d1-444a-ab48-93050309de8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374017963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1374017963
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2613979286
Short name T50
Test name
Test status
Simulation time 138497430 ps
CPU time 1.4 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 218360 kb
Host smart-79ae94c0-cb7f-4265-abf7-26505ee251f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613979286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2613979286
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3768561356
Short name T788
Test name
Test status
Simulation time 20192124 ps
CPU time 1.07 seconds
Started Apr 02 01:37:45 PM PDT 24
Finished Apr 02 01:37:46 PM PDT 24
Peak memory 217756 kb
Host smart-3aa1e541-6f62-48da-aae5-dacf94e8da19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768561356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3768561356
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2494615380
Short name T500
Test name
Test status
Simulation time 56405299 ps
CPU time 1.2 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 215348 kb
Host smart-5a97519d-f647-43ba-a544-a9825b86842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494615380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2494615380
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.4153186941
Short name T100
Test name
Test status
Simulation time 31488124 ps
CPU time 0.98 seconds
Started Apr 02 01:37:45 PM PDT 24
Finished Apr 02 01:37:46 PM PDT 24
Peak memory 230960 kb
Host smart-32d86284-6cb0-4c5d-bdd0-1df69957cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153186941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4153186941
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.4172540418
Short name T471
Test name
Test status
Simulation time 116015480 ps
CPU time 1.79 seconds
Started Apr 02 01:37:46 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 218080 kb
Host smart-3ac6541e-4b1e-44d4-8f95-d56b55021671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172540418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4172540418
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2368375629
Short name T64
Test name
Test status
Simulation time 25437993 ps
CPU time 1.23 seconds
Started Apr 02 01:37:50 PM PDT 24
Finished Apr 02 01:37:51 PM PDT 24
Peak memory 229596 kb
Host smart-9aacc696-7748-4e4d-972f-2189224ae3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368375629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2368375629
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.2494683792
Short name T597
Test name
Test status
Simulation time 27964795 ps
CPU time 1.11 seconds
Started Apr 02 01:37:51 PM PDT 24
Finished Apr 02 01:37:52 PM PDT 24
Peak memory 216872 kb
Host smart-7651dea1-405f-4224-8d53-977b4fbecbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494683792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2494683792
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4230087500
Short name T616
Test name
Test status
Simulation time 39216272 ps
CPU time 1.33 seconds
Started Apr 02 01:37:54 PM PDT 24
Finished Apr 02 01:37:56 PM PDT 24
Peak memory 217596 kb
Host smart-0fbdfb9a-4cfe-4653-8d4b-393fb9765562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230087500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4230087500
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3914417740
Short name T106
Test name
Test status
Simulation time 22696785 ps
CPU time 0.96 seconds
Started Apr 02 01:37:50 PM PDT 24
Finished Apr 02 01:37:51 PM PDT 24
Peak memory 217988 kb
Host smart-4ec1ff02-370c-42a6-8ce6-d57726c0fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914417740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3914417740
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1395440571
Short name T760
Test name
Test status
Simulation time 53977357 ps
CPU time 1.9 seconds
Started Apr 02 01:37:50 PM PDT 24
Finished Apr 02 01:37:52 PM PDT 24
Peak memory 218080 kb
Host smart-e35cda74-3e41-4eed-9ddd-7adb8d9a8761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395440571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1395440571
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.788239906
Short name T99
Test name
Test status
Simulation time 28174649 ps
CPU time 0.87 seconds
Started Apr 02 01:37:47 PM PDT 24
Finished Apr 02 01:37:48 PM PDT 24
Peak memory 217684 kb
Host smart-4a4c7f33-10bf-4034-b23a-541f9e8f0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788239906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.788239906
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1911085834
Short name T734
Test name
Test status
Simulation time 49062535 ps
CPU time 1.59 seconds
Started Apr 02 01:37:48 PM PDT 24
Finished Apr 02 01:37:50 PM PDT 24
Peak memory 219536 kb
Host smart-3fdf745d-d0b1-4ad7-a34d-77f2bef745f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911085834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1911085834
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.63178497
Short name T93
Test name
Test status
Simulation time 96694589 ps
CPU time 1.21 seconds
Started Apr 02 01:35:06 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 215604 kb
Host smart-67620c45-2f01-4f86-88ab-1a86b8aa8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63178497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.63178497
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3239186311
Short name T341
Test name
Test status
Simulation time 77519066 ps
CPU time 0.96 seconds
Started Apr 02 01:35:06 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 206488 kb
Host smart-c899fb5a-fdce-4b76-a20a-8ccabeafbca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239186311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3239186311
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.665510807
Short name T157
Test name
Test status
Simulation time 13777967 ps
CPU time 0.88 seconds
Started Apr 02 01:35:07 PM PDT 24
Finished Apr 02 01:35:08 PM PDT 24
Peak memory 215920 kb
Host smart-2d012faa-7c15-478b-a271-cb52c9bc197e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665510807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.665510807
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2097458817
Short name T330
Test name
Test status
Simulation time 122042523 ps
CPU time 1.14 seconds
Started Apr 02 01:35:07 PM PDT 24
Finished Apr 02 01:35:08 PM PDT 24
Peak memory 216352 kb
Host smart-7da643d3-e2fa-46f4-99b0-a6a89be5bf17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097458817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2097458817
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1641490334
Short name T87
Test name
Test status
Simulation time 19807836 ps
CPU time 1.1 seconds
Started Apr 02 01:35:06 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 218032 kb
Host smart-38677baf-6c55-46d9-8ace-253da31c2d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641490334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1641490334
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3288979952
Short name T244
Test name
Test status
Simulation time 248208519 ps
CPU time 1.49 seconds
Started Apr 02 01:35:04 PM PDT 24
Finished Apr 02 01:35:06 PM PDT 24
Peak memory 219240 kb
Host smart-4c3741b2-cbb1-4601-8e9f-6e39b57cbd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288979952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3288979952
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2328490602
Short name T114
Test name
Test status
Simulation time 21662934 ps
CPU time 1.07 seconds
Started Apr 02 01:35:06 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 215664 kb
Host smart-b8969d23-df3b-4756-b9ac-126cbae5fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328490602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2328490602
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.881151253
Short name T259
Test name
Test status
Simulation time 53499264 ps
CPU time 0.97 seconds
Started Apr 02 01:35:06 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 207024 kb
Host smart-c975a6d5-741b-42da-8b99-abfc84302b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881151253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.881151253
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1339344137
Short name T383
Test name
Test status
Simulation time 17232466 ps
CPU time 0.99 seconds
Started Apr 02 01:35:07 PM PDT 24
Finished Apr 02 01:35:08 PM PDT 24
Peak memory 215140 kb
Host smart-8924cf97-37f4-4bc9-858d-fdaa86451423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339344137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1339344137
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4116024876
Short name T6
Test name
Test status
Simulation time 69775093 ps
CPU time 0.98 seconds
Started Apr 02 01:35:06 PM PDT 24
Finished Apr 02 01:35:07 PM PDT 24
Peak memory 205640 kb
Host smart-8f23f5ea-a700-40b9-b20e-a18812eff657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116024876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4116024876
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3439546275
Short name T611
Test name
Test status
Simulation time 354951717669 ps
CPU time 2175.59 seconds
Started Apr 02 01:35:07 PM PDT 24
Finished Apr 02 02:11:23 PM PDT 24
Peak memory 225492 kb
Host smart-79b85945-ea2e-4e88-bdc0-735f4b251aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439546275 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3439546275
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4128623209
Short name T15
Test name
Test status
Simulation time 26706503 ps
CPU time 1.02 seconds
Started Apr 02 01:37:54 PM PDT 24
Finished Apr 02 01:37:55 PM PDT 24
Peak memory 231032 kb
Host smart-fbb3c25b-b425-4ae3-bc8e-a6b8384722da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128623209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4128623209
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1756216102
Short name T581
Test name
Test status
Simulation time 29788591 ps
CPU time 1.4 seconds
Started Apr 02 01:37:48 PM PDT 24
Finished Apr 02 01:37:50 PM PDT 24
Peak memory 217840 kb
Host smart-864cde2e-1bb1-47b8-92cb-84ae39951dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756216102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1756216102
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.38485298
Short name T437
Test name
Test status
Simulation time 44617717 ps
CPU time 0.8 seconds
Started Apr 02 01:37:50 PM PDT 24
Finished Apr 02 01:37:51 PM PDT 24
Peak memory 217980 kb
Host smart-d29fb1ff-e568-4473-a101-522a1d2bd4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38485298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.38485298
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1417085238
Short name T342
Test name
Test status
Simulation time 59388299 ps
CPU time 1.9 seconds
Started Apr 02 01:37:50 PM PDT 24
Finished Apr 02 01:37:52 PM PDT 24
Peak memory 219420 kb
Host smart-5477303b-952f-423d-bfe6-e1a1047050b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417085238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1417085238
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2158936073
Short name T163
Test name
Test status
Simulation time 123914887 ps
CPU time 1.06 seconds
Started Apr 02 01:37:53 PM PDT 24
Finished Apr 02 01:37:54 PM PDT 24
Peak memory 219216 kb
Host smart-de827f06-d7f9-448d-9980-532f85131f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158936073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2158936073
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1630372092
Short name T835
Test name
Test status
Simulation time 50656069 ps
CPU time 1.07 seconds
Started Apr 02 01:37:54 PM PDT 24
Finished Apr 02 01:37:55 PM PDT 24
Peak memory 216464 kb
Host smart-d3836b15-108f-42c0-80b5-ed1bfbd315b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630372092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1630372092
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2924367806
Short name T155
Test name
Test status
Simulation time 67757762 ps
CPU time 1.04 seconds
Started Apr 02 01:37:53 PM PDT 24
Finished Apr 02 01:37:54 PM PDT 24
Peak memory 219028 kb
Host smart-0d9e7c20-792d-46e9-be02-6b3c4b41860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924367806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2924367806
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2258791164
Short name T707
Test name
Test status
Simulation time 53687274 ps
CPU time 1.28 seconds
Started Apr 02 01:37:52 PM PDT 24
Finished Apr 02 01:37:53 PM PDT 24
Peak memory 218736 kb
Host smart-b36b7ad7-2fed-4671-83da-63d7dac7209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258791164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2258791164
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3908505968
Short name T551
Test name
Test status
Simulation time 67546800 ps
CPU time 1.29 seconds
Started Apr 02 01:37:51 PM PDT 24
Finished Apr 02 01:37:53 PM PDT 24
Peak memory 224220 kb
Host smart-4ce6864a-51de-4051-a090-4847f1b771eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908505968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3908505968
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3681166577
Short name T507
Test name
Test status
Simulation time 63293202 ps
CPU time 1.09 seconds
Started Apr 02 01:37:54 PM PDT 24
Finished Apr 02 01:37:55 PM PDT 24
Peak memory 218180 kb
Host smart-172c6333-7b36-4efb-8f2e-aa595add7707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681166577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3681166577
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3630096019
Short name T563
Test name
Test status
Simulation time 29770297 ps
CPU time 1.28 seconds
Started Apr 02 01:37:52 PM PDT 24
Finished Apr 02 01:37:54 PM PDT 24
Peak memory 218980 kb
Host smart-e1d13350-ef40-4c57-81d0-fbd7adfe989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630096019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3630096019
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.728933460
Short name T418
Test name
Test status
Simulation time 43288673 ps
CPU time 1.22 seconds
Started Apr 02 01:37:52 PM PDT 24
Finished Apr 02 01:37:53 PM PDT 24
Peak memory 218072 kb
Host smart-a93a91dc-d893-4825-b847-9c631198b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728933460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.728933460
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2172030604
Short name T41
Test name
Test status
Simulation time 44566530 ps
CPU time 0.98 seconds
Started Apr 02 01:37:52 PM PDT 24
Finished Apr 02 01:37:53 PM PDT 24
Peak memory 232384 kb
Host smart-e3c07f80-baa0-44ea-a034-1d8c96909ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172030604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2172030604
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1283903726
Short name T653
Test name
Test status
Simulation time 31784495 ps
CPU time 1.48 seconds
Started Apr 02 01:37:53 PM PDT 24
Finished Apr 02 01:37:54 PM PDT 24
Peak memory 219064 kb
Host smart-2bb6f158-5305-45be-9ace-c0a9b06cc8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283903726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1283903726
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1016016505
Short name T755
Test name
Test status
Simulation time 86714732 ps
CPU time 1.17 seconds
Started Apr 02 01:37:59 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 232236 kb
Host smart-0472109e-bd44-4a66-94c5-ce3026b9007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016016505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1016016505
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1454224426
Short name T312
Test name
Test status
Simulation time 31790404 ps
CPU time 1.53 seconds
Started Apr 02 01:37:53 PM PDT 24
Finished Apr 02 01:37:54 PM PDT 24
Peak memory 217764 kb
Host smart-04506e8c-b585-4c16-9b65-78f798e8a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454224426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1454224426
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3048772523
Short name T739
Test name
Test status
Simulation time 30277489 ps
CPU time 0.99 seconds
Started Apr 02 01:37:56 PM PDT 24
Finished Apr 02 01:37:57 PM PDT 24
Peak memory 231096 kb
Host smart-2fbebb6c-cb61-4de0-8eb9-8d4ff369ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048772523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3048772523
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3840623722
Short name T377
Test name
Test status
Simulation time 34645660 ps
CPU time 1.41 seconds
Started Apr 02 01:37:57 PM PDT 24
Finished Apr 02 01:37:58 PM PDT 24
Peak memory 219416 kb
Host smart-edce9b9e-27ac-4fc4-9fe9-fd9a974e6914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840623722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3840623722
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.789846209
Short name T751
Test name
Test status
Simulation time 24398074 ps
CPU time 0.97 seconds
Started Apr 02 01:37:55 PM PDT 24
Finished Apr 02 01:37:56 PM PDT 24
Peak memory 219312 kb
Host smart-03956588-0941-4c32-939e-87551fde67af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789846209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.789846209
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3308922735
Short name T542
Test name
Test status
Simulation time 34626329 ps
CPU time 1.33 seconds
Started Apr 02 01:37:54 PM PDT 24
Finished Apr 02 01:37:56 PM PDT 24
Peak memory 216672 kb
Host smart-f602d35c-18c7-43fd-8940-ef37aa509921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308922735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3308922735
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2537398872
Short name T768
Test name
Test status
Simulation time 102759284 ps
CPU time 1.27 seconds
Started Apr 02 01:35:14 PM PDT 24
Finished Apr 02 01:35:15 PM PDT 24
Peak memory 215632 kb
Host smart-5427de90-cef2-4498-b1c0-bbd97975a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537398872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2537398872
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1782251741
Short name T446
Test name
Test status
Simulation time 15996999 ps
CPU time 0.93 seconds
Started Apr 02 01:35:16 PM PDT 24
Finished Apr 02 01:35:17 PM PDT 24
Peak memory 206588 kb
Host smart-4fa7841a-e428-4c68-a86b-789c9812c619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782251741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1782251741
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2506527064
Short name T174
Test name
Test status
Simulation time 17614884 ps
CPU time 0.86 seconds
Started Apr 02 01:35:14 PM PDT 24
Finished Apr 02 01:35:15 PM PDT 24
Peak memory 215316 kb
Host smart-c4ae17dd-937b-4eb9-b335-7a8ce3454896
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506527064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2506527064
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2851264972
Short name T159
Test name
Test status
Simulation time 42810045 ps
CPU time 1.35 seconds
Started Apr 02 01:35:16 PM PDT 24
Finished Apr 02 01:35:17 PM PDT 24
Peak memory 216448 kb
Host smart-6c1d9936-96fc-4056-b71c-35ab7ec6aea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851264972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2851264972
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.81132136
Short name T674
Test name
Test status
Simulation time 20224876 ps
CPU time 1.07 seconds
Started Apr 02 01:35:13 PM PDT 24
Finished Apr 02 01:35:14 PM PDT 24
Peak memory 217812 kb
Host smart-f04ecefe-7567-46dd-9905-a3be6ea6ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81132136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.81132136
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1975421477
Short name T466
Test name
Test status
Simulation time 61087926 ps
CPU time 1.18 seconds
Started Apr 02 01:35:08 PM PDT 24
Finished Apr 02 01:35:10 PM PDT 24
Peak memory 216788 kb
Host smart-9bcc8574-1396-4fbb-bef7-899088462487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975421477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1975421477
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.894227987
Short name T130
Test name
Test status
Simulation time 70651325 ps
CPU time 0.86 seconds
Started Apr 02 01:35:14 PM PDT 24
Finished Apr 02 01:35:15 PM PDT 24
Peak memory 215452 kb
Host smart-bfb1d8cc-beb4-4905-8232-6d18eae3ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894227987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.894227987
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.1467602987
Short name T438
Test name
Test status
Simulation time 14832418 ps
CPU time 0.97 seconds
Started Apr 02 01:35:05 PM PDT 24
Finished Apr 02 01:35:06 PM PDT 24
Peak memory 215308 kb
Host smart-2f273bf4-b6c1-4b65-9f3c-a757a3666129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467602987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1467602987
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1720364723
Short name T704
Test name
Test status
Simulation time 1130811972 ps
CPU time 2.24 seconds
Started Apr 02 01:35:12 PM PDT 24
Finished Apr 02 01:35:14 PM PDT 24
Peak memory 216668 kb
Host smart-b5797260-b428-4573-ae66-9eae1ccdfaf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720364723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1720364723
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.688782479
Short name T180
Test name
Test status
Simulation time 38950829446 ps
CPU time 488.94 seconds
Started Apr 02 01:35:13 PM PDT 24
Finished Apr 02 01:43:23 PM PDT 24
Peak memory 218512 kb
Host smart-1cf1fcd4-36c2-48ba-903d-346cf14142ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688782479 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.688782479
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2984813495
Short name T591
Test name
Test status
Simulation time 30064346 ps
CPU time 0.97 seconds
Started Apr 02 01:37:55 PM PDT 24
Finished Apr 02 01:37:56 PM PDT 24
Peak memory 231132 kb
Host smart-028e7da7-8308-4c96-a64a-f6c1c2705fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984813495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2984813495
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1474832372
Short name T275
Test name
Test status
Simulation time 42137513 ps
CPU time 1.22 seconds
Started Apr 02 01:37:55 PM PDT 24
Finished Apr 02 01:37:56 PM PDT 24
Peak memory 216528 kb
Host smart-87a658d6-832f-42f0-be32-0d3e39eff7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474832372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1474832372
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3852190021
Short name T589
Test name
Test status
Simulation time 30107272 ps
CPU time 0.95 seconds
Started Apr 02 01:37:59 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 231136 kb
Host smart-1812ea07-a70a-46dc-bdba-db16c374e175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852190021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3852190021
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1435278558
Short name T57
Test name
Test status
Simulation time 84069600 ps
CPU time 2.9 seconds
Started Apr 02 01:38:03 PM PDT 24
Finished Apr 02 01:38:06 PM PDT 24
Peak memory 217684 kb
Host smart-0b6ebb2a-38cb-44ca-af5b-0ddd239eca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435278558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1435278558
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3599023891
Short name T425
Test name
Test status
Simulation time 25102103 ps
CPU time 0.98 seconds
Started Apr 02 01:37:58 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 218000 kb
Host smart-225587ab-9126-478c-90a4-6924e408e0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599023891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3599023891
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3487753841
Short name T763
Test name
Test status
Simulation time 49397608 ps
CPU time 1.39 seconds
Started Apr 02 01:37:59 PM PDT 24
Finished Apr 02 01:38:01 PM PDT 24
Peak memory 217944 kb
Host smart-df098835-3c0c-4443-94b6-c87f6746b239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487753841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3487753841
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3391805032
Short name T502
Test name
Test status
Simulation time 18034246 ps
CPU time 1.07 seconds
Started Apr 02 01:37:58 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 217784 kb
Host smart-a6da2bbc-54f2-4b93-877b-c620e6e2d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391805032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3391805032
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1201871355
Short name T683
Test name
Test status
Simulation time 88031318 ps
CPU time 1.05 seconds
Started Apr 02 01:37:58 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 216932 kb
Host smart-5f62fb73-de9e-4a6e-b556-95bc77a8883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201871355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1201871355
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3112593441
Short name T352
Test name
Test status
Simulation time 42155660 ps
CPU time 0.8 seconds
Started Apr 02 01:37:58 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 217580 kb
Host smart-952e9cb9-02bf-4239-9e5e-c72bd64e0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112593441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3112593441
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1284135753
Short name T302
Test name
Test status
Simulation time 55357571 ps
CPU time 1.25 seconds
Started Apr 02 01:37:59 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 218796 kb
Host smart-6fd9e91e-0a4c-4a34-acb6-db2c0c52847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284135753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1284135753
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1880657799
Short name T423
Test name
Test status
Simulation time 22541725 ps
CPU time 0.89 seconds
Started Apr 02 01:37:57 PM PDT 24
Finished Apr 02 01:37:58 PM PDT 24
Peak memory 217792 kb
Host smart-f3c22dc6-f9d3-453e-b4ab-13c5776de7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880657799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1880657799
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1140596803
Short name T297
Test name
Test status
Simulation time 144360022 ps
CPU time 2.93 seconds
Started Apr 02 01:37:59 PM PDT 24
Finished Apr 02 01:38:02 PM PDT 24
Peak memory 215264 kb
Host smart-6644896f-27d2-4648-a904-0f03595029e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140596803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1140596803
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2013229366
Short name T95
Test name
Test status
Simulation time 38754952 ps
CPU time 1.01 seconds
Started Apr 02 01:37:58 PM PDT 24
Finished Apr 02 01:38:00 PM PDT 24
Peak memory 232416 kb
Host smart-cae338d6-3549-4e2a-82af-584f76716d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013229366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2013229366
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.179920020
Short name T754
Test name
Test status
Simulation time 26497012 ps
CPU time 1.26 seconds
Started Apr 02 01:38:01 PM PDT 24
Finished Apr 02 01:38:03 PM PDT 24
Peak memory 217820 kb
Host smart-7aeca78b-97fa-4d25-8093-7df97589955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179920020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.179920020
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1874695734
Short name T141
Test name
Test status
Simulation time 18211261 ps
CPU time 1.09 seconds
Started Apr 02 01:38:02 PM PDT 24
Finished Apr 02 01:38:03 PM PDT 24
Peak memory 218264 kb
Host smart-ecc49f00-eae4-4275-ad27-ca87cdb07352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874695734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1874695734
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1656801325
Short name T676
Test name
Test status
Simulation time 27689071 ps
CPU time 1.25 seconds
Started Apr 02 01:37:59 PM PDT 24
Finished Apr 02 01:38:01 PM PDT 24
Peak memory 217760 kb
Host smart-f7298ee3-480a-45bc-af72-c8d586f7466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656801325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1656801325
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1622823089
Short name T401
Test name
Test status
Simulation time 20841464 ps
CPU time 0.97 seconds
Started Apr 02 01:38:03 PM PDT 24
Finished Apr 02 01:38:04 PM PDT 24
Peak memory 217540 kb
Host smart-d17a0a1d-b0f5-422a-876c-af49c642ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622823089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1622823089
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1810611905
Short name T539
Test name
Test status
Simulation time 188744563 ps
CPU time 1.13 seconds
Started Apr 02 01:38:01 PM PDT 24
Finished Apr 02 01:38:03 PM PDT 24
Peak memory 215248 kb
Host smart-ff494d86-11cb-44a4-a42e-13d4e5d14df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810611905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1810611905
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2224730639
Short name T68
Test name
Test status
Simulation time 25625412 ps
CPU time 1.17 seconds
Started Apr 02 01:38:01 PM PDT 24
Finished Apr 02 01:38:02 PM PDT 24
Peak memory 229672 kb
Host smart-faf5922a-bbdc-44d3-8a11-b91fa13d4717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224730639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2224730639
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.603442085
Short name T631
Test name
Test status
Simulation time 129314036 ps
CPU time 3.27 seconds
Started Apr 02 01:38:01 PM PDT 24
Finished Apr 02 01:38:05 PM PDT 24
Peak memory 216904 kb
Host smart-10e4b468-339c-4809-80fd-9ae377bdf161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603442085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.603442085
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%