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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.91 98.27 93.52 96.74 82.08 96.87 96.58 93.35


Total test records in report: 967
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T783 /workspace/coverage/default/228.edn_genbits.3901257551 Apr 04 03:35:02 PM PDT 24 Apr 04 03:35:05 PM PDT 24 72636769 ps
T784 /workspace/coverage/default/48.edn_intr.3872271326 Apr 04 03:33:58 PM PDT 24 Apr 04 03:33:59 PM PDT 24 31137056 ps
T785 /workspace/coverage/default/65.edn_genbits.3356417223 Apr 04 03:34:05 PM PDT 24 Apr 04 03:34:07 PM PDT 24 58737061 ps
T786 /workspace/coverage/default/17.edn_disable.1141894899 Apr 04 03:32:28 PM PDT 24 Apr 04 03:32:29 PM PDT 24 11371525 ps
T787 /workspace/coverage/default/75.edn_genbits.967520855 Apr 04 03:34:06 PM PDT 24 Apr 04 03:34:07 PM PDT 24 38400079 ps
T788 /workspace/coverage/default/46.edn_genbits.131070160 Apr 04 03:33:48 PM PDT 24 Apr 04 03:33:49 PM PDT 24 58055688 ps
T789 /workspace/coverage/default/29.edn_intr.1229853761 Apr 04 03:32:57 PM PDT 24 Apr 04 03:32:58 PM PDT 24 22138811 ps
T790 /workspace/coverage/default/247.edn_genbits.1633956860 Apr 04 03:35:06 PM PDT 24 Apr 04 03:35:09 PM PDT 24 46324428 ps
T791 /workspace/coverage/default/25.edn_disable.967262741 Apr 04 03:32:46 PM PDT 24 Apr 04 03:32:47 PM PDT 24 20611568 ps
T792 /workspace/coverage/default/134.edn_genbits.1260142360 Apr 04 03:34:57 PM PDT 24 Apr 04 03:34:59 PM PDT 24 49460452 ps
T793 /workspace/coverage/default/4.edn_smoke.1806660527 Apr 04 03:31:32 PM PDT 24 Apr 04 03:31:33 PM PDT 24 17236007 ps
T79 /workspace/coverage/default/35.edn_disable_auto_req_mode.985371812 Apr 04 03:33:24 PM PDT 24 Apr 04 03:33:26 PM PDT 24 45924003 ps
T794 /workspace/coverage/default/94.edn_err.3679489873 Apr 04 03:34:41 PM PDT 24 Apr 04 03:34:42 PM PDT 24 46265029 ps
T795 /workspace/coverage/default/30.edn_intr.630936954 Apr 04 03:32:56 PM PDT 24 Apr 04 03:32:58 PM PDT 24 38342389 ps
T796 /workspace/coverage/default/2.edn_genbits.2431084272 Apr 04 03:31:18 PM PDT 24 Apr 04 03:31:19 PM PDT 24 56843518 ps
T797 /workspace/coverage/default/67.edn_genbits.3173618344 Apr 04 03:34:07 PM PDT 24 Apr 04 03:34:10 PM PDT 24 119102272 ps
T798 /workspace/coverage/default/48.edn_alert_test.1568491500 Apr 04 03:33:55 PM PDT 24 Apr 04 03:33:56 PM PDT 24 104406243 ps
T799 /workspace/coverage/default/189.edn_genbits.662535877 Apr 04 03:35:02 PM PDT 24 Apr 04 03:35:05 PM PDT 24 114275187 ps
T800 /workspace/coverage/default/44.edn_alert.280434576 Apr 04 03:33:43 PM PDT 24 Apr 04 03:33:45 PM PDT 24 87870685 ps
T801 /workspace/coverage/default/4.edn_stress_all.1435106987 Apr 04 03:31:32 PM PDT 24 Apr 04 03:31:33 PM PDT 24 73887276 ps
T802 /workspace/coverage/default/28.edn_alert.2306050919 Apr 04 03:32:58 PM PDT 24 Apr 04 03:32:59 PM PDT 24 26191747 ps
T803 /workspace/coverage/default/2.edn_intr.588121845 Apr 04 03:31:19 PM PDT 24 Apr 04 03:31:21 PM PDT 24 27844889 ps
T804 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1038767371 Apr 04 03:32:28 PM PDT 24 Apr 04 04:05:33 PM PDT 24 156755836223 ps
T805 /workspace/coverage/default/11.edn_genbits.1906646534 Apr 04 03:31:55 PM PDT 24 Apr 04 03:31:56 PM PDT 24 53743554 ps
T806 /workspace/coverage/default/49.edn_smoke.1521839621 Apr 04 03:34:01 PM PDT 24 Apr 04 03:34:01 PM PDT 24 41515711 ps
T807 /workspace/coverage/default/12.edn_disable.833526839 Apr 04 03:31:56 PM PDT 24 Apr 04 03:31:57 PM PDT 24 40654644 ps
T808 /workspace/coverage/default/18.edn_genbits.3950507700 Apr 04 03:32:26 PM PDT 24 Apr 04 03:32:28 PM PDT 24 110570227 ps
T809 /workspace/coverage/default/69.edn_err.2403377823 Apr 04 03:34:17 PM PDT 24 Apr 04 03:34:18 PM PDT 24 72041776 ps
T810 /workspace/coverage/default/39.edn_smoke.1752505646 Apr 04 03:33:27 PM PDT 24 Apr 04 03:33:29 PM PDT 24 26338256 ps
T811 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1205468416 Apr 04 03:33:27 PM PDT 24 Apr 04 03:51:28 PM PDT 24 191217945653 ps
T812 /workspace/coverage/default/276.edn_genbits.3743565507 Apr 04 03:35:18 PM PDT 24 Apr 04 03:35:21 PM PDT 24 88677476 ps
T813 /workspace/coverage/default/10.edn_genbits.1790549677 Apr 04 03:31:48 PM PDT 24 Apr 04 03:31:51 PM PDT 24 135946972 ps
T814 /workspace/coverage/default/3.edn_disable.1202813010 Apr 04 03:31:31 PM PDT 24 Apr 04 03:31:31 PM PDT 24 28352398 ps
T815 /workspace/coverage/default/28.edn_alert_test.2214973417 Apr 04 03:32:58 PM PDT 24 Apr 04 03:32:59 PM PDT 24 46123537 ps
T816 /workspace/coverage/default/196.edn_genbits.3773982636 Apr 04 03:35:06 PM PDT 24 Apr 04 03:35:07 PM PDT 24 26321597 ps
T817 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1216915623 Apr 04 03:32:57 PM PDT 24 Apr 04 03:39:19 PM PDT 24 29372566926 ps
T818 /workspace/coverage/default/5.edn_genbits.2793434909 Apr 04 03:31:34 PM PDT 24 Apr 04 03:31:36 PM PDT 24 98756242 ps
T819 /workspace/coverage/default/16.edn_intr.1275011210 Apr 04 03:32:26 PM PDT 24 Apr 04 03:32:27 PM PDT 24 25582903 ps
T820 /workspace/coverage/default/13.edn_err.2847279139 Apr 04 03:32:07 PM PDT 24 Apr 04 03:32:08 PM PDT 24 24036775 ps
T821 /workspace/coverage/default/260.edn_genbits.3458353522 Apr 04 03:35:16 PM PDT 24 Apr 04 03:35:18 PM PDT 24 163827493 ps
T822 /workspace/coverage/default/130.edn_genbits.1716939166 Apr 04 03:34:58 PM PDT 24 Apr 04 03:34:59 PM PDT 24 46825101 ps
T823 /workspace/coverage/default/50.edn_err.2549387868 Apr 04 03:34:01 PM PDT 24 Apr 04 03:34:02 PM PDT 24 39756004 ps
T824 /workspace/coverage/default/3.edn_err.1052298792 Apr 04 03:31:33 PM PDT 24 Apr 04 03:31:35 PM PDT 24 81393121 ps
T825 /workspace/coverage/default/118.edn_genbits.1840156189 Apr 04 03:34:40 PM PDT 24 Apr 04 03:34:41 PM PDT 24 94554185 ps
T826 /workspace/coverage/default/123.edn_genbits.3100712211 Apr 04 03:34:55 PM PDT 24 Apr 04 03:34:57 PM PDT 24 42852364 ps
T827 /workspace/coverage/default/1.edn_alert.3084987697 Apr 04 03:31:04 PM PDT 24 Apr 04 03:31:05 PM PDT 24 69855325 ps
T828 /workspace/coverage/default/198.edn_genbits.3736195919 Apr 04 03:35:03 PM PDT 24 Apr 04 03:35:05 PM PDT 24 164417147 ps
T829 /workspace/coverage/default/16.edn_genbits.2003611000 Apr 04 03:32:27 PM PDT 24 Apr 04 03:32:28 PM PDT 24 91171280 ps
T830 /workspace/coverage/default/19.edn_smoke.943580874 Apr 04 03:32:27 PM PDT 24 Apr 04 03:32:29 PM PDT 24 35155098 ps
T831 /workspace/coverage/default/92.edn_genbits.3165998394 Apr 04 03:34:42 PM PDT 24 Apr 04 03:34:43 PM PDT 24 101959869 ps
T192 /workspace/coverage/default/32.edn_disable.347521222 Apr 04 03:33:10 PM PDT 24 Apr 04 03:33:11 PM PDT 24 23838678 ps
T832 /workspace/coverage/default/282.edn_genbits.3688234427 Apr 04 03:35:18 PM PDT 24 Apr 04 03:35:19 PM PDT 24 68484041 ps
T833 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3643022281 Apr 04 02:52:14 PM PDT 24 Apr 04 02:52:16 PM PDT 24 116123316 ps
T834 /workspace/coverage/cover_reg_top/9.edn_intr_test.3904063813 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 14123734 ps
T835 /workspace/coverage/cover_reg_top/8.edn_intr_test.2809503284 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:12 PM PDT 24 12102960 ps
T836 /workspace/coverage/cover_reg_top/35.edn_intr_test.108500609 Apr 04 02:52:30 PM PDT 24 Apr 04 02:52:31 PM PDT 24 36010200 ps
T837 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2892197257 Apr 04 02:51:57 PM PDT 24 Apr 04 02:52:00 PM PDT 24 87446660 ps
T838 /workspace/coverage/cover_reg_top/9.edn_tl_errors.443566447 Apr 04 02:52:18 PM PDT 24 Apr 04 02:52:21 PM PDT 24 138031021 ps
T839 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1574439866 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:14 PM PDT 24 111111579 ps
T238 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3060692795 Apr 04 02:52:20 PM PDT 24 Apr 04 02:52:22 PM PDT 24 1187675466 ps
T840 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3485229839 Apr 04 02:52:09 PM PDT 24 Apr 04 02:52:11 PM PDT 24 42260319 ps
T232 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3360335044 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:13 PM PDT 24 20208371 ps
T841 /workspace/coverage/cover_reg_top/19.edn_intr_test.1233415751 Apr 04 02:52:23 PM PDT 24 Apr 04 02:52:24 PM PDT 24 45356552 ps
T213 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1212244111 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 47836897 ps
T842 /workspace/coverage/cover_reg_top/16.edn_intr_test.1220511984 Apr 04 02:52:15 PM PDT 24 Apr 04 02:52:16 PM PDT 24 32028644 ps
T214 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2087517630 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 428376820 ps
T843 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2995777964 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:15 PM PDT 24 202333240 ps
T844 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.410034908 Apr 04 02:52:22 PM PDT 24 Apr 04 02:52:23 PM PDT 24 55114076 ps
T239 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3126481431 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:03 PM PDT 24 90751800 ps
T845 /workspace/coverage/cover_reg_top/18.edn_intr_test.1886788880 Apr 04 02:52:24 PM PDT 24 Apr 04 02:52:25 PM PDT 24 45900775 ps
T846 /workspace/coverage/cover_reg_top/37.edn_intr_test.4202937257 Apr 04 02:52:21 PM PDT 24 Apr 04 02:52:22 PM PDT 24 12305259 ps
T847 /workspace/coverage/cover_reg_top/23.edn_intr_test.1197457858 Apr 04 02:52:24 PM PDT 24 Apr 04 02:52:25 PM PDT 24 30305787 ps
T848 /workspace/coverage/cover_reg_top/0.edn_tl_errors.994828083 Apr 04 02:51:58 PM PDT 24 Apr 04 02:52:02 PM PDT 24 857642939 ps
T849 /workspace/coverage/cover_reg_top/20.edn_intr_test.688876125 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 28572398 ps
T850 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2295012217 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 27056930 ps
T851 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3767991159 Apr 04 02:51:58 PM PDT 24 Apr 04 02:52:04 PM PDT 24 182884082 ps
T233 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4226004564 Apr 04 02:52:23 PM PDT 24 Apr 04 02:52:24 PM PDT 24 31147952 ps
T236 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1235632880 Apr 04 02:51:58 PM PDT 24 Apr 04 02:51:59 PM PDT 24 68030477 ps
T852 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.574061157 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:04 PM PDT 24 105906010 ps
T240 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2185817054 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:14 PM PDT 24 243808349 ps
T853 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3749493532 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:12 PM PDT 24 21232014 ps
T854 /workspace/coverage/cover_reg_top/11.edn_intr_test.1832981016 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 14843146 ps
T855 /workspace/coverage/cover_reg_top/7.edn_intr_test.2801931997 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:13 PM PDT 24 14093180 ps
T215 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3107154563 Apr 04 02:52:14 PM PDT 24 Apr 04 02:52:16 PM PDT 24 58043054 ps
T856 /workspace/coverage/cover_reg_top/7.edn_tl_errors.263993760 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:15 PM PDT 24 68224626 ps
T216 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.614855325 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 47026400 ps
T857 /workspace/coverage/cover_reg_top/21.edn_intr_test.4271031825 Apr 04 02:52:20 PM PDT 24 Apr 04 02:52:21 PM PDT 24 21597120 ps
T858 /workspace/coverage/cover_reg_top/6.edn_intr_test.1904468314 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 33868873 ps
T859 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2645598747 Apr 04 02:52:22 PM PDT 24 Apr 04 02:52:25 PM PDT 24 326090525 ps
T217 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.324647068 Apr 04 02:52:09 PM PDT 24 Apr 04 02:52:11 PM PDT 24 29670510 ps
T249 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.153098410 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:04 PM PDT 24 188857007 ps
T860 /workspace/coverage/cover_reg_top/34.edn_intr_test.2677806106 Apr 04 02:52:22 PM PDT 24 Apr 04 02:52:23 PM PDT 24 33687947 ps
T237 /workspace/coverage/cover_reg_top/8.edn_csr_rw.365633881 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 23955095 ps
T861 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2802089129 Apr 04 02:52:09 PM PDT 24 Apr 04 02:52:11 PM PDT 24 87509896 ps
T862 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1375895998 Apr 04 02:52:16 PM PDT 24 Apr 04 02:52:18 PM PDT 24 152390630 ps
T863 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2142764261 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 80423888 ps
T864 /workspace/coverage/cover_reg_top/12.edn_tl_errors.880100996 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:14 PM PDT 24 37422611 ps
T218 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2261913239 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:01 PM PDT 24 20584002 ps
T234 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4003021889 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:01 PM PDT 24 19667930 ps
T219 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1427025241 Apr 04 02:52:15 PM PDT 24 Apr 04 02:52:17 PM PDT 24 192675425 ps
T865 /workspace/coverage/cover_reg_top/14.edn_intr_test.1826154305 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:13 PM PDT 24 78225204 ps
T866 /workspace/coverage/cover_reg_top/15.edn_intr_test.1393150180 Apr 04 02:52:16 PM PDT 24 Apr 04 02:52:17 PM PDT 24 24771813 ps
T867 /workspace/coverage/cover_reg_top/16.edn_tl_errors.4266677278 Apr 04 02:52:14 PM PDT 24 Apr 04 02:52:17 PM PDT 24 64674372 ps
T868 /workspace/coverage/cover_reg_top/4.edn_intr_test.3415818513 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:03 PM PDT 24 17496811 ps
T869 /workspace/coverage/cover_reg_top/42.edn_intr_test.350494891 Apr 04 02:52:21 PM PDT 24 Apr 04 02:52:22 PM PDT 24 49463073 ps
T870 /workspace/coverage/cover_reg_top/40.edn_intr_test.3644074363 Apr 04 02:52:32 PM PDT 24 Apr 04 02:52:33 PM PDT 24 22516687 ps
T871 /workspace/coverage/cover_reg_top/33.edn_intr_test.3165071944 Apr 04 02:52:24 PM PDT 24 Apr 04 02:52:25 PM PDT 24 17827231 ps
T872 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1491785351 Apr 04 02:52:15 PM PDT 24 Apr 04 02:52:16 PM PDT 24 22130312 ps
T220 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1236615150 Apr 04 02:52:17 PM PDT 24 Apr 04 02:52:18 PM PDT 24 52879435 ps
T873 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3784976575 Apr 04 02:51:59 PM PDT 24 Apr 04 02:52:01 PM PDT 24 60753446 ps
T235 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3229054474 Apr 04 02:51:56 PM PDT 24 Apr 04 02:51:57 PM PDT 24 15281769 ps
T874 /workspace/coverage/cover_reg_top/19.edn_tl_errors.421812098 Apr 04 02:52:22 PM PDT 24 Apr 04 02:52:25 PM PDT 24 195652265 ps
T875 /workspace/coverage/cover_reg_top/45.edn_intr_test.2641720253 Apr 04 02:52:22 PM PDT 24 Apr 04 02:52:23 PM PDT 24 26344463 ps
T876 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.480540569 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:03 PM PDT 24 142711083 ps
T877 /workspace/coverage/cover_reg_top/11.edn_csr_rw.325809592 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:12 PM PDT 24 14560003 ps
T878 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1129478496 Apr 04 02:52:18 PM PDT 24 Apr 04 02:52:20 PM PDT 24 51632123 ps
T879 /workspace/coverage/cover_reg_top/26.edn_intr_test.4293006652 Apr 04 02:52:24 PM PDT 24 Apr 04 02:52:25 PM PDT 24 32342004 ps
T880 /workspace/coverage/cover_reg_top/5.edn_csr_rw.983749864 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:02 PM PDT 24 15687057 ps
T881 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2127365266 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:13 PM PDT 24 44441543 ps
T882 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2500402729 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 34125683 ps
T883 /workspace/coverage/cover_reg_top/36.edn_intr_test.3074097995 Apr 04 02:52:19 PM PDT 24 Apr 04 02:52:20 PM PDT 24 45682204 ps
T884 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2593732569 Apr 04 02:51:57 PM PDT 24 Apr 04 02:52:00 PM PDT 24 220375468 ps
T885 /workspace/coverage/cover_reg_top/22.edn_intr_test.2266199859 Apr 04 02:52:21 PM PDT 24 Apr 04 02:52:21 PM PDT 24 87157123 ps
T886 /workspace/coverage/cover_reg_top/44.edn_intr_test.1162028685 Apr 04 02:52:24 PM PDT 24 Apr 04 02:52:25 PM PDT 24 34417457 ps
T221 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.703775902 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:03 PM PDT 24 33278817 ps
T887 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3538702566 Apr 04 02:51:57 PM PDT 24 Apr 04 02:52:00 PM PDT 24 162249747 ps
T888 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2600558116 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:03 PM PDT 24 143826233 ps
T889 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3760771943 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:14 PM PDT 24 199503573 ps
T890 /workspace/coverage/cover_reg_top/0.edn_intr_test.4014658519 Apr 04 02:51:57 PM PDT 24 Apr 04 02:51:59 PM PDT 24 15633260 ps
T891 /workspace/coverage/cover_reg_top/17.edn_intr_test.4021746319 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 12729966 ps
T892 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1405130692 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:12 PM PDT 24 44838982 ps
T893 /workspace/coverage/cover_reg_top/43.edn_intr_test.4261156281 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 33360722 ps
T894 /workspace/coverage/cover_reg_top/41.edn_intr_test.1284237250 Apr 04 02:52:24 PM PDT 24 Apr 04 02:52:24 PM PDT 24 16530917 ps
T895 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3367775657 Apr 04 02:52:17 PM PDT 24 Apr 04 02:52:19 PM PDT 24 91772267 ps
T896 /workspace/coverage/cover_reg_top/6.edn_tl_errors.925968061 Apr 04 02:52:09 PM PDT 24 Apr 04 02:52:12 PM PDT 24 166751967 ps
T897 /workspace/coverage/cover_reg_top/30.edn_intr_test.2920270854 Apr 04 02:52:22 PM PDT 24 Apr 04 02:52:23 PM PDT 24 19252252 ps
T222 /workspace/coverage/cover_reg_top/18.edn_csr_rw.166950823 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 14427329 ps
T250 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1407491631 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:12 PM PDT 24 914762529 ps
T898 /workspace/coverage/cover_reg_top/3.edn_csr_rw.291156475 Apr 04 02:51:59 PM PDT 24 Apr 04 02:52:00 PM PDT 24 32123036 ps
T899 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.80060173 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:04 PM PDT 24 174564324 ps
T900 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2130895748 Apr 04 02:51:56 PM PDT 24 Apr 04 02:51:57 PM PDT 24 45987026 ps
T901 /workspace/coverage/cover_reg_top/12.edn_intr_test.519977026 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:13 PM PDT 24 14145771 ps
T902 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1872372328 Apr 04 02:52:26 PM PDT 24 Apr 04 02:52:27 PM PDT 24 18352983 ps
T903 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2276283015 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:01 PM PDT 24 350132054 ps
T904 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2178338496 Apr 04 02:52:14 PM PDT 24 Apr 04 02:52:15 PM PDT 24 22543773 ps
T905 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2584983424 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 70587728 ps
T906 /workspace/coverage/cover_reg_top/2.edn_intr_test.1503857637 Apr 04 02:51:57 PM PDT 24 Apr 04 02:51:59 PM PDT 24 18732046 ps
T907 /workspace/coverage/cover_reg_top/47.edn_intr_test.935192498 Apr 04 02:52:32 PM PDT 24 Apr 04 02:52:33 PM PDT 24 14225431 ps
T908 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2745922441 Apr 04 02:52:17 PM PDT 24 Apr 04 02:52:18 PM PDT 24 49937582 ps
T909 /workspace/coverage/cover_reg_top/39.edn_intr_test.31241486 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 25631409 ps
T910 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2871840606 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:01 PM PDT 24 11953381 ps
T911 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.887026663 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:02 PM PDT 24 14875495 ps
T912 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3997318699 Apr 04 02:52:14 PM PDT 24 Apr 04 02:52:15 PM PDT 24 30780213 ps
T913 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1130141603 Apr 04 02:52:32 PM PDT 24 Apr 04 02:52:34 PM PDT 24 169739766 ps
T914 /workspace/coverage/cover_reg_top/10.edn_intr_test.2050894921 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 14956581 ps
T915 /workspace/coverage/cover_reg_top/38.edn_intr_test.3686134047 Apr 04 02:52:23 PM PDT 24 Apr 04 02:52:24 PM PDT 24 71538339 ps
T916 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2329854631 Apr 04 02:52:15 PM PDT 24 Apr 04 02:52:19 PM PDT 24 508480118 ps
T917 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2269607208 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:15 PM PDT 24 54837495 ps
T918 /workspace/coverage/cover_reg_top/5.edn_intr_test.1271851269 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:02 PM PDT 24 14927772 ps
T223 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2670412827 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 31898710 ps
T919 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3282284584 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:05 PM PDT 24 362226082 ps
T920 /workspace/coverage/cover_reg_top/24.edn_intr_test.1643890815 Apr 04 02:52:26 PM PDT 24 Apr 04 02:52:27 PM PDT 24 44884934 ps
T921 /workspace/coverage/cover_reg_top/29.edn_intr_test.2063373138 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 73732422 ps
T922 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2240785425 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:12 PM PDT 24 37106769 ps
T224 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.985300048 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:03 PM PDT 24 57659702 ps
T923 /workspace/coverage/cover_reg_top/49.edn_intr_test.2788232911 Apr 04 02:52:20 PM PDT 24 Apr 04 02:52:21 PM PDT 24 25567056 ps
T924 /workspace/coverage/cover_reg_top/3.edn_intr_test.2605635655 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:02 PM PDT 24 19660831 ps
T925 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4010201588 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:04 PM PDT 24 403958696 ps
T225 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1073289635 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 13613677 ps
T926 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2010107603 Apr 04 02:51:59 PM PDT 24 Apr 04 02:52:01 PM PDT 24 23000272 ps
T927 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2840576002 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:13 PM PDT 24 194703936 ps
T928 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3359836514 Apr 04 02:51:59 PM PDT 24 Apr 04 02:52:01 PM PDT 24 22417750 ps
T929 /workspace/coverage/cover_reg_top/32.edn_intr_test.1405467923 Apr 04 02:52:21 PM PDT 24 Apr 04 02:52:22 PM PDT 24 62698965 ps
T930 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4072227186 Apr 04 02:51:57 PM PDT 24 Apr 04 02:51:59 PM PDT 24 13968856 ps
T931 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1052305258 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:14 PM PDT 24 44946944 ps
T932 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4085195856 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:13 PM PDT 24 13191205 ps
T933 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2923104546 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:13 PM PDT 24 26596844 ps
T934 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.313414471 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:12 PM PDT 24 15107588 ps
T935 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3990751276 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:13 PM PDT 24 14609669 ps
T936 /workspace/coverage/cover_reg_top/25.edn_intr_test.422589761 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 18147667 ps
T226 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2947004987 Apr 04 02:51:58 PM PDT 24 Apr 04 02:51:59 PM PDT 24 53739609 ps
T937 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2625248226 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:01 PM PDT 24 37508213 ps
T938 /workspace/coverage/cover_reg_top/28.edn_intr_test.2960303767 Apr 04 02:52:32 PM PDT 24 Apr 04 02:52:33 PM PDT 24 15461282 ps
T939 /workspace/coverage/cover_reg_top/46.edn_intr_test.76432127 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 13694144 ps
T227 /workspace/coverage/cover_reg_top/14.edn_csr_rw.4146940144 Apr 04 02:52:17 PM PDT 24 Apr 04 02:52:18 PM PDT 24 21211566 ps
T228 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1516336808 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:14 PM PDT 24 32622141 ps
T940 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2551134990 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:02 PM PDT 24 358890112 ps
T941 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.166233239 Apr 04 02:52:15 PM PDT 24 Apr 04 02:52:16 PM PDT 24 172694771 ps
T942 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.373065473 Apr 04 02:52:21 PM PDT 24 Apr 04 02:52:22 PM PDT 24 44794613 ps
T943 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.805178847 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:02 PM PDT 24 13741666 ps
T944 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2412392475 Apr 04 02:52:09 PM PDT 24 Apr 04 02:52:12 PM PDT 24 107889539 ps
T945 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3232585112 Apr 04 02:52:11 PM PDT 24 Apr 04 02:52:14 PM PDT 24 90666734 ps
T946 /workspace/coverage/cover_reg_top/48.edn_intr_test.3278174004 Apr 04 02:52:32 PM PDT 24 Apr 04 02:52:33 PM PDT 24 36327285 ps
T947 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1425557448 Apr 04 02:52:17 PM PDT 24 Apr 04 02:52:18 PM PDT 24 70480381 ps
T948 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1419581956 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:04 PM PDT 24 144487318 ps
T949 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1862507360 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:02 PM PDT 24 209382497 ps
T950 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2271137567 Apr 04 02:52:17 PM PDT 24 Apr 04 02:52:20 PM PDT 24 75975388 ps
T231 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3265481966 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 31934403 ps
T951 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2500581504 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:05 PM PDT 24 109980917 ps
T952 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3013462929 Apr 04 02:52:14 PM PDT 24 Apr 04 02:52:15 PM PDT 24 20883001 ps
T953 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1011714996 Apr 04 02:52:13 PM PDT 24 Apr 04 02:52:16 PM PDT 24 106770489 ps
T954 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1801039167 Apr 04 02:51:58 PM PDT 24 Apr 04 02:52:00 PM PDT 24 82197601 ps
T955 /workspace/coverage/cover_reg_top/1.edn_intr_test.2798797427 Apr 04 02:51:58 PM PDT 24 Apr 04 02:51:59 PM PDT 24 68361148 ps
T956 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.255354248 Apr 04 02:51:59 PM PDT 24 Apr 04 02:52:03 PM PDT 24 198670451 ps
T957 /workspace/coverage/cover_reg_top/31.edn_intr_test.2652548819 Apr 04 02:52:31 PM PDT 24 Apr 04 02:52:32 PM PDT 24 15496124 ps
T958 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3140738034 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:16 PM PDT 24 111157260 ps
T959 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2896578680 Apr 04 02:52:12 PM PDT 24 Apr 04 02:52:14 PM PDT 24 110074579 ps
T960 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2867990886 Apr 04 02:52:00 PM PDT 24 Apr 04 02:52:02 PM PDT 24 95198758 ps
T229 /workspace/coverage/cover_reg_top/6.edn_csr_rw.250438198 Apr 04 02:52:08 PM PDT 24 Apr 04 02:52:10 PM PDT 24 12404596 ps
T961 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3910860306 Apr 04 02:52:25 PM PDT 24 Apr 04 02:52:26 PM PDT 24 22728778 ps
T962 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2330354634 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:04 PM PDT 24 132163801 ps
T230 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3567263543 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:03 PM PDT 24 31389168 ps
T963 /workspace/coverage/cover_reg_top/27.edn_intr_test.1156339115 Apr 04 02:52:21 PM PDT 24 Apr 04 02:52:22 PM PDT 24 14578852 ps
T964 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3477419014 Apr 04 02:52:01 PM PDT 24 Apr 04 02:52:02 PM PDT 24 78439904 ps
T965 /workspace/coverage/cover_reg_top/13.edn_intr_test.3455592557 Apr 04 02:52:10 PM PDT 24 Apr 04 02:52:11 PM PDT 24 88434352 ps
T966 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1255585914 Apr 04 02:52:15 PM PDT 24 Apr 04 02:52:17 PM PDT 24 41937248 ps
T967 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4179699311 Apr 04 02:52:02 PM PDT 24 Apr 04 02:52:03 PM PDT 24 30669434 ps

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2279897875
Short name T6
Test name
Test status
Simulation time 197672423991 ps
CPU time 1153.03 seconds
Started Apr 04 03:30:50 PM PDT 24
Finished Apr 04 03:50:03 PM PDT 24
Peak memory 221204 kb
Host smart-45101bbf-58cb-4de7-8707-edc63b3c05f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279897875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2279897875
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.edn_genbits.2630251294
Short name T28
Test name
Test status
Simulation time 241032765 ps
CPU time 3.03 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 217656 kb
Host smart-82bd6bba-800d-473e-9854-b5ada8e79256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630251294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2630251294
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.215329747
Short name T27
Test name
Test status
Simulation time 68009599 ps
CPU time 0.82 seconds
Started Apr 04 03:34:06 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 217280 kb
Host smart-7d102ca4-42dc-4cdb-99a9-762481f356a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215329747 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.215329747
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/229.edn_genbits.1384646351
Short name T1
Test name
Test status
Simulation time 36293183 ps
CPU time 1.31 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 214912 kb
Host smart-e1caba90-4384-4ae7-8c02-23e413528751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384646351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1384646351
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_alert.2369035646
Short name T18
Test name
Test status
Simulation time 28382579 ps
CPU time 1.3 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 215260 kb
Host smart-93a2cc59-db06-421d-9801-3d2c569cd931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369035646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2369035646
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1813506320
Short name T22
Test name
Test status
Simulation time 188847717 ps
CPU time 3.59 seconds
Started Apr 04 03:31:19 PM PDT 24
Finished Apr 04 03:31:23 PM PDT 24
Peak memory 234164 kb
Host smart-4dc66d6f-d16e-4acc-a530-d53c02fbcd31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813506320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1813506320
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/76.edn_err.4281266607
Short name T16
Test name
Test status
Simulation time 18757383 ps
CPU time 1.11 seconds
Started Apr 04 03:34:14 PM PDT 24
Finished Apr 04 03:34:16 PM PDT 24
Peak memory 222780 kb
Host smart-b0c13d57-80c0-4dbd-8f63-5e97d64aa287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281266607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4281266607
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3878421994
Short name T70
Test name
Test status
Simulation time 31968645 ps
CPU time 0.94 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 217200 kb
Host smart-8d7d6bf1-93cf-4d7f-9d4e-b217182f1cff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878421994 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3878421994
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3626334669
Short name T145
Test name
Test status
Simulation time 48271746109 ps
CPU time 1112.69 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:51:01 PM PDT 24
Peak memory 220888 kb
Host smart-63465eb7-32fb-4a89-9dff-f515bf29d4de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626334669 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3626334669
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.edn_genbits.3213202632
Short name T206
Test name
Test status
Simulation time 30968810 ps
CPU time 1.21 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:12 PM PDT 24
Peak memory 219052 kb
Host smart-c5f308ba-92ea-45c7-92be-68db5bf06a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213202632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3213202632
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2822647367
Short name T17
Test name
Test status
Simulation time 89830639 ps
CPU time 1.24 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:11 PM PDT 24
Peak memory 215248 kb
Host smart-a246df32-170e-4c76-9abf-ac49dbdb59bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822647367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2822647367
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/43.edn_intr.3387282562
Short name T129
Test name
Test status
Simulation time 21168211 ps
CPU time 1.06 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 215400 kb
Host smart-e15747d2-5f08-43e6-ab59-074489ebaadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387282562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3387282562
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.242903858
Short name T136
Test name
Test status
Simulation time 46038214 ps
CPU time 0.86 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:19 PM PDT 24
Peak memory 206800 kb
Host smart-c18f1fda-39dc-4329-897f-3f94b4bf2b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242903858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.242903858
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3060692795
Short name T238
Test name
Test status
Simulation time 1187675466 ps
CPU time 2.12 seconds
Started Apr 04 02:52:20 PM PDT 24
Finished Apr 04 02:52:22 PM PDT 24
Peak memory 206352 kb
Host smart-450bf088-7342-4021-94ef-79b1e8e244d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060692795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3060692795
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.4182810069
Short name T92
Test name
Test status
Simulation time 48275530 ps
CPU time 1.06 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 216044 kb
Host smart-50fe0d25-6dc4-45af-9306-98ecb29d153d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182810069 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.4182810069
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/81.edn_genbits.3199096133
Short name T13
Test name
Test status
Simulation time 184424010 ps
CPU time 1.38 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 216448 kb
Host smart-9b67a02d-0157-4198-9d3b-c26447a67216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199096133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3199096133
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_alert.1289441812
Short name T103
Test name
Test status
Simulation time 41826258 ps
CPU time 1.24 seconds
Started Apr 04 03:31:36 PM PDT 24
Finished Apr 04 03:31:37 PM PDT 24
Peak memory 215256 kb
Host smart-b1bd3e63-83d1-4b0d-acb3-93f7aca8eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289441812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1289441812
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/40.edn_disable.1970010237
Short name T123
Test name
Test status
Simulation time 14052767 ps
CPU time 0.92 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 215532 kb
Host smart-3b542941-5f07-4491-990c-957201e211fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970010237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1970010237
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2261913239
Short name T218
Test name
Test status
Simulation time 20584002 ps
CPU time 1 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 206168 kb
Host smart-9f10d3bc-4e55-44cc-975a-40d57cd09f12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261913239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2261913239
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2945991938
Short name T244
Test name
Test status
Simulation time 24217327 ps
CPU time 1.24 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 215260 kb
Host smart-f94c1562-9945-47eb-9bb2-ea9a2c761ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945991938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2945991938
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/23.edn_disable.3464643694
Short name T661
Test name
Test status
Simulation time 36557819 ps
CPU time 0.85 seconds
Started Apr 04 03:32:50 PM PDT 24
Finished Apr 04 03:32:51 PM PDT 24
Peak memory 215468 kb
Host smart-0a4bf219-f38e-4bc6-a1af-35af04d92f5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464643694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3464643694
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3871838292
Short name T164
Test name
Test status
Simulation time 142219704 ps
CPU time 1.13 seconds
Started Apr 04 03:31:57 PM PDT 24
Finished Apr 04 03:31:58 PM PDT 24
Peak memory 215980 kb
Host smart-4f56570c-a7f9-44d3-a041-7c2b5d904d4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871838292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3871838292
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable.2552893862
Short name T114
Test name
Test status
Simulation time 12771895 ps
CPU time 0.95 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 215648 kb
Host smart-624d47db-cb49-46ba-9602-3ae261f69a45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552893862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2552893862
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/125.edn_genbits.3818967176
Short name T2
Test name
Test status
Simulation time 33031196 ps
CPU time 1.24 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 216260 kb
Host smart-c53e3b30-01a8-43ec-ab41-0452354c3523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818967176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3818967176
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_disable.3739232384
Short name T62
Test name
Test status
Simulation time 27021849 ps
CPU time 0.8 seconds
Started Apr 04 03:31:19 PM PDT 24
Finished Apr 04 03:31:20 PM PDT 24
Peak memory 215056 kb
Host smart-bb7eab31-590b-4817-9901-9638703eb213
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739232384 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3739232384
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/292.edn_genbits.2218255690
Short name T190
Test name
Test status
Simulation time 119971261 ps
CPU time 1.16 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 218000 kb
Host smart-90795a27-a435-497d-8ce6-35d240c1e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218255690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2218255690
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4203578992
Short name T127
Test name
Test status
Simulation time 24271640 ps
CPU time 0.9 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 215340 kb
Host smart-6849cd1d-3887-4708-afa2-945d531299a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203578992 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4203578992
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/20.edn_alert.685600697
Short name T189
Test name
Test status
Simulation time 76605295 ps
CPU time 1.27 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 215256 kb
Host smart-3c016ff6-8c61-4b97-800a-534d1bceb378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685600697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.685600697
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1275916205
Short name T24
Test name
Test status
Simulation time 90661808604 ps
CPU time 595.11 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:43:43 PM PDT 24
Peak memory 218760 kb
Host smart-2295e42f-54d2-44b0-9ed0-91bb5acf4151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275916205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1275916205
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_disable.2864931690
Short name T167
Test name
Test status
Simulation time 18921173 ps
CPU time 0.87 seconds
Started Apr 04 03:30:53 PM PDT 24
Finished Apr 04 03:30:54 PM PDT 24
Peak memory 215620 kb
Host smart-e6b28e39-dab9-41a0-8449-eb1ce08c8412
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864931690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2864931690
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1070454783
Short name T85
Test name
Test status
Simulation time 29531747 ps
CPU time 1.2 seconds
Started Apr 04 03:32:55 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 216176 kb
Host smart-7f26f7f9-2b90-4aba-9ab8-8e48fca47991
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070454783 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1070454783
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.3072426328
Short name T175
Test name
Test status
Simulation time 65100336 ps
CPU time 0.86 seconds
Started Apr 04 03:32:55 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 215468 kb
Host smart-d368d257-84df-4f4d-8402-52521726d1c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072426328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3072426328
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/38.edn_intr.628788942
Short name T132
Test name
Test status
Simulation time 57692569 ps
CPU time 0.79 seconds
Started Apr 04 03:33:23 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 215156 kb
Host smart-a79ac354-af5b-42a2-880d-49a56a15185c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628788942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.628788942
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2313427024
Short name T74
Test name
Test status
Simulation time 39131269 ps
CPU time 1.3 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 215924 kb
Host smart-7501c6fc-62a1-4c2e-ba8b-227ff7634908
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313427024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2313427024
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.3419027564
Short name T156
Test name
Test status
Simulation time 36459651 ps
CPU time 0.87 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 215456 kb
Host smart-092619b1-4638-445f-84e6-1b610559cfe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419027564 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3419027564
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.2027739705
Short name T120
Test name
Test status
Simulation time 16451766 ps
CPU time 0.9 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:52 PM PDT 24
Peak memory 215624 kb
Host smart-6029fa39-92d6-40f3-94d0-8b30b7f1f144
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027739705 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2027739705
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1202850536
Short name T172
Test name
Test status
Simulation time 140241077 ps
CPU time 1.04 seconds
Started Apr 04 03:32:56 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 216168 kb
Host smart-39ce98f3-27ad-482b-9511-1cdd9b6f8ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202850536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1202850536
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.985371812
Short name T79
Test name
Test status
Simulation time 45924003 ps
CPU time 1.33 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 216004 kb
Host smart-491483fd-7119-4dec-9e57-e0d0396c8835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985371812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.985371812
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3846196310
Short name T173
Test name
Test status
Simulation time 86831151 ps
CPU time 1.12 seconds
Started Apr 04 03:33:29 PM PDT 24
Finished Apr 04 03:33:30 PM PDT 24
Peak memory 216056 kb
Host smart-6a9c059a-e10d-4011-a368-f8d1c4424df8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846196310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3846196310
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.3690384465
Short name T294
Test name
Test status
Simulation time 35322462 ps
CPU time 1.35 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 218540 kb
Host smart-e9466910-8fe0-4a18-89e4-725f1c5bc8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690384465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3690384465
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.765889635
Short name T298
Test name
Test status
Simulation time 13279478 ps
CPU time 0.92 seconds
Started Apr 04 03:31:59 PM PDT 24
Finished Apr 04 03:32:00 PM PDT 24
Peak memory 206336 kb
Host smart-889be50d-3de4-484a-bfcb-81bce02b8011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765889635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.765889635
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/236.edn_genbits.858156374
Short name T12
Test name
Test status
Simulation time 181204749 ps
CPU time 1.36 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 218200 kb
Host smart-9fb088be-9ad8-499b-8d1e-7cbf36c9c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858156374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.858156374
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.3800149759
Short name T257
Test name
Test status
Simulation time 43192163 ps
CPU time 0.84 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 206624 kb
Host smart-ab98de97-5beb-404e-b56e-9ff7cbf16785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800149759 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3800149759
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_stress_all.2409456551
Short name T211
Test name
Test status
Simulation time 934232387 ps
CPU time 4.82 seconds
Started Apr 04 03:31:59 PM PDT 24
Finished Apr 04 03:32:03 PM PDT 24
Peak memory 217472 kb
Host smart-17df5fe4-154d-451d-88a6-614ae0a477fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409456551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2409456551
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_err.3221301600
Short name T7
Test name
Test status
Simulation time 26197206 ps
CPU time 0.95 seconds
Started Apr 04 03:31:17 PM PDT 24
Finished Apr 04 03:31:18 PM PDT 24
Peak memory 218884 kb
Host smart-bb3fad75-5d7f-4669-bdb9-736e79035f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221301600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3221301600
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4003021889
Short name T234
Test name
Test status
Simulation time 19667930 ps
CPU time 0.82 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 205896 kb
Host smart-cb1a7147-7592-406b-857d-9f24ab122a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003021889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4003021889
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2947004987
Short name T226
Test name
Test status
Simulation time 53739609 ps
CPU time 0.94 seconds
Started Apr 04 02:51:58 PM PDT 24
Finished Apr 04 02:51:59 PM PDT 24
Peak memory 206168 kb
Host smart-d5eccf39-4aaf-4e11-ab1c-442afd4caf31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947004987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2947004987
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/0.edn_regwen.2900779263
Short name T207
Test name
Test status
Simulation time 18800561 ps
CPU time 1.05 seconds
Started Apr 04 03:31:01 PM PDT 24
Finished Apr 04 03:31:02 PM PDT 24
Peak memory 206792 kb
Host smart-32da0023-7453-4c8e-82e7-f7b37c0a3b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900779263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2900779263
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_alert.3084987697
Short name T827
Test name
Test status
Simulation time 69855325 ps
CPU time 1.17 seconds
Started Apr 04 03:31:04 PM PDT 24
Finished Apr 04 03:31:05 PM PDT 24
Peak memory 215260 kb
Host smart-0d6f2bb4-b993-4aac-8950-125b7047ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084987697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3084987697
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1854143530
Short name T499
Test name
Test status
Simulation time 203603731925 ps
CPU time 1353 seconds
Started Apr 04 03:31:06 PM PDT 24
Finished Apr 04 03:53:39 PM PDT 24
Peak memory 224460 kb
Host smart-9483a867-ef28-4984-b6d7-2dffe2ac69f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854143530 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1854143530
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_stress_all.3799894477
Short name T463
Test name
Test status
Simulation time 957002012 ps
CPU time 4.62 seconds
Started Apr 04 03:31:52 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 217608 kb
Host smart-e9a75b18-9315-44f8-bc1d-b5672fe1ac30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799894477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3799894477
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/105.edn_genbits.1232946213
Short name T670
Test name
Test status
Simulation time 208495285 ps
CPU time 1.76 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 217628 kb
Host smart-227b12f8-3d6b-4f9f-a045-9b22cdd86a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232946213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1232946213
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3492667200
Short name T282
Test name
Test status
Simulation time 543661487 ps
CPU time 3.62 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:44 PM PDT 24
Peak memory 216680 kb
Host smart-02e13173-3857-4277-8b64-070402db0746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492667200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3492667200
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2572935694
Short name T485
Test name
Test status
Simulation time 83104362 ps
CPU time 1.13 seconds
Started Apr 04 03:31:57 PM PDT 24
Finished Apr 04 03:31:59 PM PDT 24
Peak memory 215268 kb
Host smart-4f014a14-ab39-43e5-933e-2478824c680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572935694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2572935694
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.3714959215
Short name T71
Test name
Test status
Simulation time 74337453 ps
CPU time 1.25 seconds
Started Apr 04 03:32:00 PM PDT 24
Finished Apr 04 03:32:02 PM PDT 24
Peak memory 215252 kb
Host smart-90c28c6f-0c76-4de1-8ab8-844a4936629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714959215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3714959215
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.423333553
Short name T270
Test name
Test status
Simulation time 57163015 ps
CPU time 1.37 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 217828 kb
Host smart-de72ae57-629b-4760-b8ca-2691a3386ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423333553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.423333553
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.1716939166
Short name T822
Test name
Test status
Simulation time 46825101 ps
CPU time 1.28 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217704 kb
Host smart-cad965e7-1755-4dc5-85cf-1315cb0a0439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716939166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1716939166
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2068941824
Short name T273
Test name
Test status
Simulation time 82629398 ps
CPU time 1.02 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 217812 kb
Host smart-1903f813-2a7a-477c-934c-f27ad8b18dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068941824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2068941824
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3168864270
Short name T288
Test name
Test status
Simulation time 476407263 ps
CPU time 5.01 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 217596 kb
Host smart-a61011f4-1bdd-4241-a363-70048b06736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168864270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3168864270
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1287154064
Short name T182
Test name
Test status
Simulation time 78953864 ps
CPU time 3 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 216556 kb
Host smart-d33c5343-f44f-40cc-addf-2d613b6590a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287154064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1287154064
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.501553733
Short name T285
Test name
Test status
Simulation time 35961221 ps
CPU time 1.52 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:35:01 PM PDT 24
Peak memory 217632 kb
Host smart-a8005139-0ba8-4a0b-a875-87a61b012fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501553733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.501553733
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2146080004
Short name T154
Test name
Test status
Simulation time 37604877 ps
CPU time 1.23 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 215160 kb
Host smart-a30b5197-4317-400e-8298-5ff24f19fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146080004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2146080004
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert.557283092
Short name T110
Test name
Test status
Simulation time 26675678 ps
CPU time 1.15 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 215224 kb
Host smart-a60bbad2-b43b-4b1d-b8c6-18b48300e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557283092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.557283092
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3569433742
Short name T90
Test name
Test status
Simulation time 27754605 ps
CPU time 1.06 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 216084 kb
Host smart-e03caa0d-2e39-4ebe-be93-90787edfcb4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569433742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3569433742
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2330354634
Short name T962
Test name
Test status
Simulation time 132163801 ps
CPU time 1.43 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 206156 kb
Host smart-f718d72a-68a0-45d8-bc17-7e8631ca3abe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330354634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2330354634
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2593732569
Short name T884
Test name
Test status
Simulation time 220375468 ps
CPU time 3.06 seconds
Started Apr 04 02:51:57 PM PDT 24
Finished Apr 04 02:52:00 PM PDT 24
Peak memory 206180 kb
Host smart-d9a18245-169c-4ccd-bf05-08b8d45f001e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593732569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2593732569
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1235632880
Short name T236
Test name
Test status
Simulation time 68030477 ps
CPU time 0.88 seconds
Started Apr 04 02:51:58 PM PDT 24
Finished Apr 04 02:51:59 PM PDT 24
Peak memory 206140 kb
Host smart-23a66e74-613c-4952-9b50-0522706a8944
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235632880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1235632880
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1801039167
Short name T954
Test name
Test status
Simulation time 82197601 ps
CPU time 1.17 seconds
Started Apr 04 02:51:58 PM PDT 24
Finished Apr 04 02:52:00 PM PDT 24
Peak memory 214512 kb
Host smart-0dbc3cc5-bb3d-4c93-85cb-b241d0049170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801039167 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1801039167
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4014658519
Short name T890
Test name
Test status
Simulation time 15633260 ps
CPU time 0.9 seconds
Started Apr 04 02:51:57 PM PDT 24
Finished Apr 04 02:51:59 PM PDT 24
Peak memory 206148 kb
Host smart-7dd94cd3-6d01-4dfa-bd21-c44f3af086a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014658519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4014658519
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2625248226
Short name T937
Test name
Test status
Simulation time 37508213 ps
CPU time 1.17 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 206356 kb
Host smart-4a56d08e-6d66-40c6-a8be-cf6937174a6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625248226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2625248226
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.994828083
Short name T848
Test name
Test status
Simulation time 857642939 ps
CPU time 3.49 seconds
Started Apr 04 02:51:58 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 214748 kb
Host smart-b5d140a3-612b-442f-b8a1-aae86a533908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994828083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.994828083
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.153098410
Short name T249
Test name
Test status
Simulation time 188857007 ps
CPU time 1.96 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 206244 kb
Host smart-f0a480d2-2d41-414c-974a-d25e680201f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153098410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.153098410
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2010107603
Short name T926
Test name
Test status
Simulation time 23000272 ps
CPU time 1.17 seconds
Started Apr 04 02:51:59 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 206180 kb
Host smart-545b3a75-aacf-45f7-a61f-dccc5b3707a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010107603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2010107603
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3767991159
Short name T851
Test name
Test status
Simulation time 182884082 ps
CPU time 5.25 seconds
Started Apr 04 02:51:58 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 206176 kb
Host smart-28529d0a-ce85-4f55-8425-decc850b35e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767991159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3767991159
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4072227186
Short name T930
Test name
Test status
Simulation time 13968856 ps
CPU time 1 seconds
Started Apr 04 02:51:57 PM PDT 24
Finished Apr 04 02:51:59 PM PDT 24
Peak memory 206372 kb
Host smart-ffc1e87c-1ddc-44f9-a990-c868590ff73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072227186 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4072227186
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3229054474
Short name T235
Test name
Test status
Simulation time 15281769 ps
CPU time 0.97 seconds
Started Apr 04 02:51:56 PM PDT 24
Finished Apr 04 02:51:57 PM PDT 24
Peak memory 206100 kb
Host smart-4a92f187-a407-42a6-bd69-487b7846f2f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229054474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3229054474
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2798797427
Short name T955
Test name
Test status
Simulation time 68361148 ps
CPU time 0.85 seconds
Started Apr 04 02:51:58 PM PDT 24
Finished Apr 04 02:51:59 PM PDT 24
Peak memory 206172 kb
Host smart-3e9bf521-4fd2-4e75-af09-760c4cdd14e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798797427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2798797427
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.887026663
Short name T911
Test name
Test status
Simulation time 14875495 ps
CPU time 1.03 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 206372 kb
Host smart-4c6de043-6865-40e5-924a-953fbefdd1d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887026663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.887026663
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2892197257
Short name T837
Test name
Test status
Simulation time 87446660 ps
CPU time 2.86 seconds
Started Apr 04 02:51:57 PM PDT 24
Finished Apr 04 02:52:00 PM PDT 24
Peak memory 214584 kb
Host smart-e33b6f03-e50d-4759-ba45-064434163a70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892197257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2892197257
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3784976575
Short name T873
Test name
Test status
Simulation time 60753446 ps
CPU time 1.8 seconds
Started Apr 04 02:51:59 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 206260 kb
Host smart-de739d39-5dea-479b-97c3-b80dde7d2fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784976575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3784976575
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.313414471
Short name T934
Test name
Test status
Simulation time 15107588 ps
CPU time 0.95 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 206364 kb
Host smart-9bd2dbe9-f99c-4273-8744-6541d7fe96d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313414471 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.313414471
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3990751276
Short name T935
Test name
Test status
Simulation time 14609669 ps
CPU time 0.91 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206192 kb
Host smart-3f30502c-9ca3-4e28-aec3-d2af093b872a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990751276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3990751276
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2050894921
Short name T914
Test name
Test status
Simulation time 14956581 ps
CPU time 0.89 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206104 kb
Host smart-7725e51a-7750-4034-bba0-2e35b3f3c4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050894921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2050894921
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3997318699
Short name T912
Test name
Test status
Simulation time 30780213 ps
CPU time 1.1 seconds
Started Apr 04 02:52:14 PM PDT 24
Finished Apr 04 02:52:15 PM PDT 24
Peak memory 206340 kb
Host smart-3ff76e56-dd72-40e6-9fbe-5c53cdee90aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997318699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3997318699
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1011714996
Short name T953
Test name
Test status
Simulation time 106770489 ps
CPU time 2.6 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 214668 kb
Host smart-01ae6d0d-bb19-4b35-b1be-a8f4b71c0ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011714996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1011714996
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2142764261
Short name T863
Test name
Test status
Simulation time 80423888 ps
CPU time 1.45 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206332 kb
Host smart-4c8c5aee-2f95-466e-8ea1-d099cef33337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142764261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2142764261
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1405130692
Short name T892
Test name
Test status
Simulation time 44838982 ps
CPU time 1.15 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 214676 kb
Host smart-97389686-a2db-4ef9-a893-1a089714edfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405130692 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1405130692
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.325809592
Short name T877
Test name
Test status
Simulation time 14560003 ps
CPU time 0.98 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 206176 kb
Host smart-8dec6ddc-c0b0-43e4-ad91-95b93e4b0224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325809592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.325809592
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1832981016
Short name T854
Test name
Test status
Simulation time 14843146 ps
CPU time 0.88 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206192 kb
Host smart-9a517a81-1667-461e-90b9-e040ceae8f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832981016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1832981016
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2087517630
Short name T214
Test name
Test status
Simulation time 428376820 ps
CPU time 1.34 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206240 kb
Host smart-1b08db12-f479-45b5-963e-d19c20e35561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087517630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2087517630
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3140738034
Short name T958
Test name
Test status
Simulation time 111157260 ps
CPU time 3.69 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 214596 kb
Host smart-ea1b2ca5-256c-4328-910c-c5d217a511d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140738034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3140738034
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1052305258
Short name T931
Test name
Test status
Simulation time 44946944 ps
CPU time 1.59 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206368 kb
Host smart-e17b2a52-f4d5-4dda-865b-7eeb3cd1c3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052305258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1052305258
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3749493532
Short name T853
Test name
Test status
Simulation time 21232014 ps
CPU time 1 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 206328 kb
Host smart-9a84c391-f74e-4fb2-9f76-07f278245b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749493532 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3749493532
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2127365266
Short name T881
Test name
Test status
Simulation time 44441543 ps
CPU time 0.87 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206168 kb
Host smart-3d56f105-ce5d-4366-98ff-76ecb06d67ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127365266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2127365266
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.519977026
Short name T901
Test name
Test status
Simulation time 14145771 ps
CPU time 0.91 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206176 kb
Host smart-8f490c02-bf23-4704-9a75-4b4a4d616dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519977026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.519977026
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2584983424
Short name T905
Test name
Test status
Simulation time 70587728 ps
CPU time 1.03 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206324 kb
Host smart-d63b9272-d59c-4c79-8785-3f38fdb93552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584983424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2584983424
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.880100996
Short name T864
Test name
Test status
Simulation time 37422611 ps
CPU time 1.79 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 214604 kb
Host smart-0802a871-e35e-406b-bbe8-ea4f8cb81fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880100996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.880100996
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2802089129
Short name T861
Test name
Test status
Simulation time 87509896 ps
CPU time 1.61 seconds
Started Apr 04 02:52:09 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206336 kb
Host smart-a0728c79-034f-4be0-aa95-5665e4b93b80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802089129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2802089129
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1129478496
Short name T878
Test name
Test status
Simulation time 51632123 ps
CPU time 2.01 seconds
Started Apr 04 02:52:18 PM PDT 24
Finished Apr 04 02:52:20 PM PDT 24
Peak memory 214584 kb
Host smart-1b86a62a-dc7e-4539-9664-b911f61b0594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129478496 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1129478496
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3265481966
Short name T231
Test name
Test status
Simulation time 31934403 ps
CPU time 0.86 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206136 kb
Host smart-12effc10-f4e5-4517-95b0-f76d4f92b50d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265481966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3265481966
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3455592557
Short name T965
Test name
Test status
Simulation time 88434352 ps
CPU time 0.85 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 205992 kb
Host smart-bf7fc60c-2412-49e1-9184-796785baecad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455592557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3455592557
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.324647068
Short name T217
Test name
Test status
Simulation time 29670510 ps
CPU time 1.33 seconds
Started Apr 04 02:52:09 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206320 kb
Host smart-0d2c50c9-f566-4471-98b3-07ee64396e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324647068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.324647068
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2329854631
Short name T916
Test name
Test status
Simulation time 508480118 ps
CPU time 3.84 seconds
Started Apr 04 02:52:15 PM PDT 24
Finished Apr 04 02:52:19 PM PDT 24
Peak memory 214620 kb
Host smart-748c57f2-66a5-4205-8b6a-4f7891906d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329854631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2329854631
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1407491631
Short name T250
Test name
Test status
Simulation time 914762529 ps
CPU time 2.34 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 206416 kb
Host smart-873cbe60-7fcb-4762-b617-91011e5b1a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407491631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1407491631
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1491785351
Short name T872
Test name
Test status
Simulation time 22130312 ps
CPU time 1.11 seconds
Started Apr 04 02:52:15 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 215724 kb
Host smart-27edcc9e-6f89-4cbf-9cad-d81ad4e6de1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491785351 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1491785351
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4146940144
Short name T227
Test name
Test status
Simulation time 21211566 ps
CPU time 0.78 seconds
Started Apr 04 02:52:17 PM PDT 24
Finished Apr 04 02:52:18 PM PDT 24
Peak memory 205920 kb
Host smart-7679154c-7ecb-463b-a184-3b7ed4a777ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146940144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4146940144
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1826154305
Short name T865
Test name
Test status
Simulation time 78225204 ps
CPU time 0.8 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206168 kb
Host smart-786d896f-a307-430c-a06b-89bf8b7d2228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826154305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1826154305
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1212244111
Short name T213
Test name
Test status
Simulation time 47836897 ps
CPU time 0.94 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206344 kb
Host smart-a2aab68f-784d-4d36-be85-ba08ec2c856f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212244111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1212244111
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2271137567
Short name T950
Test name
Test status
Simulation time 75975388 ps
CPU time 2.79 seconds
Started Apr 04 02:52:17 PM PDT 24
Finished Apr 04 02:52:20 PM PDT 24
Peak memory 214480 kb
Host smart-8d14fd72-f656-4bc4-bb6d-52b656f912ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271137567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2271137567
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2185817054
Short name T240
Test name
Test status
Simulation time 243808349 ps
CPU time 2.06 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206376 kb
Host smart-46f75879-f955-445f-b77e-d19be09b4269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185817054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2185817054
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2295012217
Short name T850
Test name
Test status
Simulation time 27056930 ps
CPU time 1.31 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 214584 kb
Host smart-73b26996-4ac6-4c5e-ba64-5a8ab8f2066c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295012217 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2295012217
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1425557448
Short name T947
Test name
Test status
Simulation time 70480381 ps
CPU time 0.96 seconds
Started Apr 04 02:52:17 PM PDT 24
Finished Apr 04 02:52:18 PM PDT 24
Peak memory 206164 kb
Host smart-15114074-4d96-4f64-b761-941841913e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425557448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1425557448
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1393150180
Short name T866
Test name
Test status
Simulation time 24771813 ps
CPU time 0.87 seconds
Started Apr 04 02:52:16 PM PDT 24
Finished Apr 04 02:52:17 PM PDT 24
Peak memory 206168 kb
Host smart-da7f7146-dac9-4093-8262-ecd79534f928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393150180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1393150180
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3107154563
Short name T215
Test name
Test status
Simulation time 58043054 ps
CPU time 1.08 seconds
Started Apr 04 02:52:14 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 206368 kb
Host smart-8775b9c5-0d2e-4780-b324-ecc6e57c22ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107154563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3107154563
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3367775657
Short name T895
Test name
Test status
Simulation time 91772267 ps
CPU time 1.68 seconds
Started Apr 04 02:52:17 PM PDT 24
Finished Apr 04 02:52:19 PM PDT 24
Peak memory 214580 kb
Host smart-0cfcfc92-2a28-4127-8e48-b38c5f251b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367775657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3367775657
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3232585112
Short name T945
Test name
Test status
Simulation time 90666734 ps
CPU time 1.44 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206296 kb
Host smart-eff5e396-5711-4059-ab75-99b91ef98ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232585112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3232585112
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2745922441
Short name T908
Test name
Test status
Simulation time 49937582 ps
CPU time 1.29 seconds
Started Apr 04 02:52:17 PM PDT 24
Finished Apr 04 02:52:18 PM PDT 24
Peak memory 214484 kb
Host smart-4eaaf32d-f788-4e82-9fbf-81a2f417f67a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745922441 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2745922441
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1236615150
Short name T220
Test name
Test status
Simulation time 52879435 ps
CPU time 0.94 seconds
Started Apr 04 02:52:17 PM PDT 24
Finished Apr 04 02:52:18 PM PDT 24
Peak memory 206092 kb
Host smart-594b08cb-ad8d-4b16-a898-54b376c5ced7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236615150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1236615150
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1220511984
Short name T842
Test name
Test status
Simulation time 32028644 ps
CPU time 0.79 seconds
Started Apr 04 02:52:15 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 205988 kb
Host smart-15279f3a-5f44-447c-843e-c82535288a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220511984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1220511984
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1255585914
Short name T966
Test name
Test status
Simulation time 41937248 ps
CPU time 1.56 seconds
Started Apr 04 02:52:15 PM PDT 24
Finished Apr 04 02:52:17 PM PDT 24
Peak memory 206296 kb
Host smart-4d8fab26-82df-41af-ac00-0d18c4a30df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255585914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1255585914
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4266677278
Short name T867
Test name
Test status
Simulation time 64674372 ps
CPU time 2.56 seconds
Started Apr 04 02:52:14 PM PDT 24
Finished Apr 04 02:52:17 PM PDT 24
Peak memory 214520 kb
Host smart-65df7e16-3127-45c3-b243-d2644a92af9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266677278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4266677278
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2840576002
Short name T927
Test name
Test status
Simulation time 194703936 ps
CPU time 2.22 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206316 kb
Host smart-ba54058e-5531-4df4-866b-e47bdfc9e3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840576002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2840576002
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2178338496
Short name T904
Test name
Test status
Simulation time 22543773 ps
CPU time 1.5 seconds
Started Apr 04 02:52:14 PM PDT 24
Finished Apr 04 02:52:15 PM PDT 24
Peak memory 214656 kb
Host smart-9d7981cb-2c47-4e5c-8f39-7608294174e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178338496 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2178338496
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1516336808
Short name T228
Test name
Test status
Simulation time 32622141 ps
CPU time 0.8 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206024 kb
Host smart-c93939ca-ad3e-4838-a7e8-b1d3e65533d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516336808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1516336808
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4021746319
Short name T891
Test name
Test status
Simulation time 12729966 ps
CPU time 0.86 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206132 kb
Host smart-491919e1-3510-425f-a5f0-739f3c68d6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021746319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4021746319
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2500402729
Short name T882
Test name
Test status
Simulation time 34125683 ps
CPU time 1.05 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206344 kb
Host smart-fca99d00-281b-4eaf-9e58-fcd17e4fbe5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500402729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2500402729
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3643022281
Short name T833
Test name
Test status
Simulation time 116123316 ps
CPU time 2.31 seconds
Started Apr 04 02:52:14 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 214628 kb
Host smart-30552f36-49e1-4507-ba3e-a6ad48a03d51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643022281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3643022281
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1375895998
Short name T862
Test name
Test status
Simulation time 152390630 ps
CPU time 2.23 seconds
Started Apr 04 02:52:16 PM PDT 24
Finished Apr 04 02:52:18 PM PDT 24
Peak memory 206296 kb
Host smart-3e12961c-6cc3-4bae-b091-fed6c475b8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375895998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1375895998
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.410034908
Short name T844
Test name
Test status
Simulation time 55114076 ps
CPU time 1.28 seconds
Started Apr 04 02:52:22 PM PDT 24
Finished Apr 04 02:52:23 PM PDT 24
Peak memory 214624 kb
Host smart-edd4c450-ce28-40ce-9350-5261c24d28dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410034908 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.410034908
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.166950823
Short name T222
Test name
Test status
Simulation time 14427329 ps
CPU time 0.92 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 206216 kb
Host smart-f4c4884b-3b27-49a2-b4da-732f68b5ef5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166950823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.166950823
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1886788880
Short name T845
Test name
Test status
Simulation time 45900775 ps
CPU time 0.89 seconds
Started Apr 04 02:52:24 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 206108 kb
Host smart-8606cf8d-e014-4011-9d28-ee6405fed071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886788880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1886788880
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4226004564
Short name T233
Test name
Test status
Simulation time 31147952 ps
CPU time 0.88 seconds
Started Apr 04 02:52:23 PM PDT 24
Finished Apr 04 02:52:24 PM PDT 24
Peak memory 206388 kb
Host smart-f7f44b27-eb5b-4a40-b6f1-7d662fceb220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226004564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4226004564
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2645598747
Short name T859
Test name
Test status
Simulation time 326090525 ps
CPU time 2.75 seconds
Started Apr 04 02:52:22 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 214628 kb
Host smart-b6704ae3-978e-440f-9d9e-3242e7a092cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645598747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2645598747
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3910860306
Short name T961
Test name
Test status
Simulation time 22728778 ps
CPU time 0.95 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 206364 kb
Host smart-a399dd91-a0d4-4ddc-b352-1b18d9403b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910860306 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3910860306
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1872372328
Short name T902
Test name
Test status
Simulation time 18352983 ps
CPU time 0.83 seconds
Started Apr 04 02:52:26 PM PDT 24
Finished Apr 04 02:52:27 PM PDT 24
Peak memory 206184 kb
Host smart-07d1accf-feae-45e0-8eff-ce6e7b270387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872372328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1872372328
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1233415751
Short name T841
Test name
Test status
Simulation time 45356552 ps
CPU time 0.79 seconds
Started Apr 04 02:52:23 PM PDT 24
Finished Apr 04 02:52:24 PM PDT 24
Peak memory 206128 kb
Host smart-384afd79-4b91-4998-80ad-468839100fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233415751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1233415751
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.373065473
Short name T942
Test name
Test status
Simulation time 44794613 ps
CPU time 1.42 seconds
Started Apr 04 02:52:21 PM PDT 24
Finished Apr 04 02:52:22 PM PDT 24
Peak memory 206340 kb
Host smart-50cf1c28-ed8c-4ec1-b7a7-35277d2fe73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373065473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.373065473
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.421812098
Short name T874
Test name
Test status
Simulation time 195652265 ps
CPU time 3.72 seconds
Started Apr 04 02:52:22 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 214536 kb
Host smart-8424d0bb-22ae-4224-97f6-e5a65ba1550d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421812098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.421812098
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1130141603
Short name T913
Test name
Test status
Simulation time 169739766 ps
CPU time 1.58 seconds
Started Apr 04 02:52:32 PM PDT 24
Finished Apr 04 02:52:34 PM PDT 24
Peak memory 206296 kb
Host smart-508b4d30-ac68-49fe-9402-8c040d36bcc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130141603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1130141603
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.985300048
Short name T224
Test name
Test status
Simulation time 57659702 ps
CPU time 1.2 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206296 kb
Host smart-3060d33d-43f7-4268-ae09-c67bf630b02c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985300048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.985300048
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.255354248
Short name T956
Test name
Test status
Simulation time 198670451 ps
CPU time 3.14 seconds
Started Apr 04 02:51:59 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206136 kb
Host smart-b4ccfb51-e195-440f-91fc-56554e5177c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255354248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.255354248
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3567263543
Short name T230
Test name
Test status
Simulation time 31389168 ps
CPU time 0.95 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206196 kb
Host smart-f57396e9-3cd1-44bf-a745-d78ad044880c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567263543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3567263543
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2276283015
Short name T903
Test name
Test status
Simulation time 350132054 ps
CPU time 1.34 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 216792 kb
Host smart-fc4d6c0e-36eb-4c72-9a69-e44f6d2fae3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276283015 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2276283015
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2130895748
Short name T900
Test name
Test status
Simulation time 45987026 ps
CPU time 0.9 seconds
Started Apr 04 02:51:56 PM PDT 24
Finished Apr 04 02:51:57 PM PDT 24
Peak memory 206116 kb
Host smart-853d4a48-d240-4ba8-bbce-1a0e0fcc42e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130895748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2130895748
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1503857637
Short name T906
Test name
Test status
Simulation time 18732046 ps
CPU time 0.82 seconds
Started Apr 04 02:51:57 PM PDT 24
Finished Apr 04 02:51:59 PM PDT 24
Peak memory 206020 kb
Host smart-cd89ea84-648b-4d11-ae1c-8f191d430781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503857637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1503857637
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3359836514
Short name T928
Test name
Test status
Simulation time 22417750 ps
CPU time 0.94 seconds
Started Apr 04 02:51:59 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 206416 kb
Host smart-137d9254-024b-4a48-ada3-b904d6aead81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359836514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3359836514
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3538702566
Short name T887
Test name
Test status
Simulation time 162249747 ps
CPU time 3.07 seconds
Started Apr 04 02:51:57 PM PDT 24
Finished Apr 04 02:52:00 PM PDT 24
Peak memory 217920 kb
Host smart-ad92886b-4b47-44f7-8152-9823daa6d042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538702566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3538702566
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2551134990
Short name T940
Test name
Test status
Simulation time 358890112 ps
CPU time 2.35 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 206264 kb
Host smart-ede65b01-e987-4565-9ce1-35eda92aa6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551134990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2551134990
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.688876125
Short name T849
Test name
Test status
Simulation time 28572398 ps
CPU time 0.82 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 206144 kb
Host smart-c1bafe55-c6c9-459a-93e4-ad44db10d0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688876125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.688876125
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4271031825
Short name T857
Test name
Test status
Simulation time 21597120 ps
CPU time 0.83 seconds
Started Apr 04 02:52:20 PM PDT 24
Finished Apr 04 02:52:21 PM PDT 24
Peak memory 206200 kb
Host smart-cfd5d1f7-1a21-4f1b-90bd-e108e56ada3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271031825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4271031825
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2266199859
Short name T885
Test name
Test status
Simulation time 87157123 ps
CPU time 0.85 seconds
Started Apr 04 02:52:21 PM PDT 24
Finished Apr 04 02:52:21 PM PDT 24
Peak memory 206168 kb
Host smart-fcca4d1e-1ad3-4e11-b2d4-1114ddd9e91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266199859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2266199859
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1197457858
Short name T847
Test name
Test status
Simulation time 30305787 ps
CPU time 0.77 seconds
Started Apr 04 02:52:24 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 205912 kb
Host smart-d2c1a5f6-3430-437f-92b6-96da3ca3022d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197457858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1197457858
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1643890815
Short name T920
Test name
Test status
Simulation time 44884934 ps
CPU time 0.87 seconds
Started Apr 04 02:52:26 PM PDT 24
Finished Apr 04 02:52:27 PM PDT 24
Peak memory 206192 kb
Host smart-2762ec66-7aaf-4e00-98db-1b2dc573c3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643890815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1643890815
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.422589761
Short name T936
Test name
Test status
Simulation time 18147667 ps
CPU time 0.83 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 206184 kb
Host smart-f31e316c-be65-45e9-afb6-63758ff6fd60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422589761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.422589761
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4293006652
Short name T879
Test name
Test status
Simulation time 32342004 ps
CPU time 0.93 seconds
Started Apr 04 02:52:24 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 206100 kb
Host smart-270aac2d-44d6-4d06-8cf0-15b375479c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293006652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4293006652
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1156339115
Short name T963
Test name
Test status
Simulation time 14578852 ps
CPU time 0.91 seconds
Started Apr 04 02:52:21 PM PDT 24
Finished Apr 04 02:52:22 PM PDT 24
Peak memory 206192 kb
Host smart-96aa18c6-ee83-47a6-baed-271014b559b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156339115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1156339115
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2960303767
Short name T938
Test name
Test status
Simulation time 15461282 ps
CPU time 0.87 seconds
Started Apr 04 02:52:32 PM PDT 24
Finished Apr 04 02:52:33 PM PDT 24
Peak memory 206156 kb
Host smart-63f48efc-520d-4763-9b40-5b0c6d5399bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960303767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2960303767
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2063373138
Short name T921
Test name
Test status
Simulation time 73732422 ps
CPU time 0.77 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 205976 kb
Host smart-449e2c81-4217-42a7-a89c-95cbc0987aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063373138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2063373138
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1862507360
Short name T949
Test name
Test status
Simulation time 209382497 ps
CPU time 1.59 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 206200 kb
Host smart-3ff01474-811d-4d9f-8bf6-5c9296ceae2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862507360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1862507360
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3282284584
Short name T919
Test name
Test status
Simulation time 362226082 ps
CPU time 2.94 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:05 PM PDT 24
Peak memory 206156 kb
Host smart-e9e0663a-2e4f-4cc7-9823-531e63383227
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282284584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3282284584
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.805178847
Short name T943
Test name
Test status
Simulation time 13741666 ps
CPU time 0.92 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 206088 kb
Host smart-84171978-36da-4811-9ec7-12df9d570eea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805178847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.805178847
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4179699311
Short name T967
Test name
Test status
Simulation time 30669434 ps
CPU time 1 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206388 kb
Host smart-b3f4d795-6e3e-4791-a650-a7d43733127a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179699311 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4179699311
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.291156475
Short name T898
Test name
Test status
Simulation time 32123036 ps
CPU time 0.79 seconds
Started Apr 04 02:51:59 PM PDT 24
Finished Apr 04 02:52:00 PM PDT 24
Peak memory 205944 kb
Host smart-f6a6a809-b5fd-4372-97f7-3f2b86a6cc01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291156475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.291156475
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2605635655
Short name T924
Test name
Test status
Simulation time 19660831 ps
CPU time 0.82 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 205948 kb
Host smart-4dcc7e7a-5da6-4b5f-a37d-f73a74e7280a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605635655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2605635655
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.480540569
Short name T876
Test name
Test status
Simulation time 142711083 ps
CPU time 1.11 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206244 kb
Host smart-58062a3f-4bdf-43ca-89e3-cb062a23a933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480540569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.480540569
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4010201588
Short name T925
Test name
Test status
Simulation time 403958696 ps
CPU time 3.49 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 214564 kb
Host smart-dda2261f-e72f-443b-ae1a-aaeee31156ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010201588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4010201588
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3126481431
Short name T239
Test name
Test status
Simulation time 90751800 ps
CPU time 2.46 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206240 kb
Host smart-7b3d2133-b454-4e42-b2a1-e7e1ec68503e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126481431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3126481431
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2920270854
Short name T897
Test name
Test status
Simulation time 19252252 ps
CPU time 0.81 seconds
Started Apr 04 02:52:22 PM PDT 24
Finished Apr 04 02:52:23 PM PDT 24
Peak memory 205976 kb
Host smart-61134df9-ebe9-4cce-8c61-fda965f19a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920270854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2920270854
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2652548819
Short name T957
Test name
Test status
Simulation time 15496124 ps
CPU time 0.9 seconds
Started Apr 04 02:52:31 PM PDT 24
Finished Apr 04 02:52:32 PM PDT 24
Peak memory 206224 kb
Host smart-eeb2d736-7618-4998-9eb2-a8311dea4f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652548819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2652548819
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1405467923
Short name T929
Test name
Test status
Simulation time 62698965 ps
CPU time 0.81 seconds
Started Apr 04 02:52:21 PM PDT 24
Finished Apr 04 02:52:22 PM PDT 24
Peak memory 206016 kb
Host smart-53be045a-bf95-4d06-b255-f5b160381822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405467923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1405467923
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3165071944
Short name T871
Test name
Test status
Simulation time 17827231 ps
CPU time 0.83 seconds
Started Apr 04 02:52:24 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 206176 kb
Host smart-d002fd45-83da-4a72-b982-64d13635a905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165071944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3165071944
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2677806106
Short name T860
Test name
Test status
Simulation time 33687947 ps
CPU time 0.8 seconds
Started Apr 04 02:52:22 PM PDT 24
Finished Apr 04 02:52:23 PM PDT 24
Peak memory 206000 kb
Host smart-0a2d09fc-943a-4d60-9ae4-b062b3400cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677806106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2677806106
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.108500609
Short name T836
Test name
Test status
Simulation time 36010200 ps
CPU time 0.85 seconds
Started Apr 04 02:52:30 PM PDT 24
Finished Apr 04 02:52:31 PM PDT 24
Peak memory 205996 kb
Host smart-77884e5a-ae77-4021-9f1a-01dab08da2ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108500609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.108500609
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3074097995
Short name T883
Test name
Test status
Simulation time 45682204 ps
CPU time 0.9 seconds
Started Apr 04 02:52:19 PM PDT 24
Finished Apr 04 02:52:20 PM PDT 24
Peak memory 206176 kb
Host smart-25773759-fa22-43c0-abf1-3078551e7b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074097995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3074097995
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4202937257
Short name T846
Test name
Test status
Simulation time 12305259 ps
CPU time 0.85 seconds
Started Apr 04 02:52:21 PM PDT 24
Finished Apr 04 02:52:22 PM PDT 24
Peak memory 206176 kb
Host smart-a0b01adc-2939-4684-81bf-7c7d2634eab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202937257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4202937257
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3686134047
Short name T915
Test name
Test status
Simulation time 71538339 ps
CPU time 0.86 seconds
Started Apr 04 02:52:23 PM PDT 24
Finished Apr 04 02:52:24 PM PDT 24
Peak memory 206128 kb
Host smart-8474d36b-4cba-4759-9a01-4c351d64e27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686134047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3686134047
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.31241486
Short name T909
Test name
Test status
Simulation time 25631409 ps
CPU time 0.89 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 206188 kb
Host smart-29d63b7d-b9dc-4a4a-ae8f-89fba0c6da02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.31241486
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.703775902
Short name T221
Test name
Test status
Simulation time 33278817 ps
CPU time 1.24 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 206260 kb
Host smart-4d11686c-b6f8-47b0-9a09-8152a65b97de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703775902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.703775902
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2500581504
Short name T951
Test name
Test status
Simulation time 109980917 ps
CPU time 3.28 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:05 PM PDT 24
Peak memory 206152 kb
Host smart-4542e823-4326-4ad6-8006-50d907d53d75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500581504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2500581504
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.574061157
Short name T852
Test name
Test status
Simulation time 105906010 ps
CPU time 1.37 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 214608 kb
Host smart-a4d63522-d64d-4d58-a34c-4cc61338282a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574061157 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.574061157
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2871840606
Short name T910
Test name
Test status
Simulation time 11953381 ps
CPU time 0.86 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:01 PM PDT 24
Peak memory 206180 kb
Host smart-5651aa84-f084-4fa4-8c87-7dae282b8f52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871840606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2871840606
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3415818513
Short name T868
Test name
Test status
Simulation time 17496811 ps
CPU time 0.82 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 205920 kb
Host smart-0d49ce81-2c0d-47f5-b39f-59ef8499b853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415818513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3415818513
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3477419014
Short name T964
Test name
Test status
Simulation time 78439904 ps
CPU time 1.09 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 206316 kb
Host smart-3935b414-0fff-4e83-b8fc-9592a6db2602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477419014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3477419014
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2867990886
Short name T960
Test name
Test status
Simulation time 95198758 ps
CPU time 1.93 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 214596 kb
Host smart-4fc3674c-352b-43b3-8c09-4f40e2892507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867990886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2867990886
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.80060173
Short name T899
Test name
Test status
Simulation time 174564324 ps
CPU time 2.47 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 206128 kb
Host smart-c36fed3f-dfa8-43fa-b6b7-b1521fa2db5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80060173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.80060173
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3644074363
Short name T870
Test name
Test status
Simulation time 22516687 ps
CPU time 0.85 seconds
Started Apr 04 02:52:32 PM PDT 24
Finished Apr 04 02:52:33 PM PDT 24
Peak memory 206156 kb
Host smart-442ecfaa-ed81-4b7d-b9d0-13024428c621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644074363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3644074363
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1284237250
Short name T894
Test name
Test status
Simulation time 16530917 ps
CPU time 0.79 seconds
Started Apr 04 02:52:24 PM PDT 24
Finished Apr 04 02:52:24 PM PDT 24
Peak memory 206152 kb
Host smart-4e406f3f-5d54-4e06-9928-bafebe9fac8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284237250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1284237250
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.350494891
Short name T869
Test name
Test status
Simulation time 49463073 ps
CPU time 0.88 seconds
Started Apr 04 02:52:21 PM PDT 24
Finished Apr 04 02:52:22 PM PDT 24
Peak memory 206188 kb
Host smart-2c017989-60ca-4e56-adc2-c46e5e8a60ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350494891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.350494891
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4261156281
Short name T893
Test name
Test status
Simulation time 33360722 ps
CPU time 0.78 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 205956 kb
Host smart-a3ab984e-b945-423f-945f-281457a86ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261156281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4261156281
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1162028685
Short name T886
Test name
Test status
Simulation time 34417457 ps
CPU time 0.81 seconds
Started Apr 04 02:52:24 PM PDT 24
Finished Apr 04 02:52:25 PM PDT 24
Peak memory 205924 kb
Host smart-b9e3bc60-0774-476b-93da-8f47aa02db08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162028685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1162028685
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2641720253
Short name T875
Test name
Test status
Simulation time 26344463 ps
CPU time 0.82 seconds
Started Apr 04 02:52:22 PM PDT 24
Finished Apr 04 02:52:23 PM PDT 24
Peak memory 206144 kb
Host smart-d890e6c3-01a2-4ae4-9df3-d942a5c3fa05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641720253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2641720253
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.76432127
Short name T939
Test name
Test status
Simulation time 13694144 ps
CPU time 0.86 seconds
Started Apr 04 02:52:25 PM PDT 24
Finished Apr 04 02:52:26 PM PDT 24
Peak memory 206184 kb
Host smart-ead3ee58-5873-465d-acbd-968503afaac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76432127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.76432127
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.935192498
Short name T907
Test name
Test status
Simulation time 14225431 ps
CPU time 0.88 seconds
Started Apr 04 02:52:32 PM PDT 24
Finished Apr 04 02:52:33 PM PDT 24
Peak memory 206164 kb
Host smart-44d59a99-10df-47f3-9aed-904ad04f3aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935192498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.935192498
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3278174004
Short name T946
Test name
Test status
Simulation time 36327285 ps
CPU time 0.81 seconds
Started Apr 04 02:52:32 PM PDT 24
Finished Apr 04 02:52:33 PM PDT 24
Peak memory 206040 kb
Host smart-37484658-1936-448a-a89f-4feda2c8880f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278174004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3278174004
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2788232911
Short name T923
Test name
Test status
Simulation time 25567056 ps
CPU time 0.85 seconds
Started Apr 04 02:52:20 PM PDT 24
Finished Apr 04 02:52:21 PM PDT 24
Peak memory 206164 kb
Host smart-65f2f8e3-0975-464f-be8a-373ef7257e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788232911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2788232911
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2240785425
Short name T922
Test name
Test status
Simulation time 37106769 ps
CPU time 1.3 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 214616 kb
Host smart-2da358ad-db94-4651-b22a-6f52815d1bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240785425 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2240785425
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.983749864
Short name T880
Test name
Test status
Simulation time 15687057 ps
CPU time 0.9 seconds
Started Apr 04 02:52:01 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 205972 kb
Host smart-0a3065ec-c0c0-4a9b-9327-ffae5a4a52ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983749864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.983749864
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1271851269
Short name T918
Test name
Test status
Simulation time 14927772 ps
CPU time 0.93 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:02 PM PDT 24
Peak memory 206176 kb
Host smart-c69b34d6-fc7b-4392-b9b1-b77328416194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271851269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1271851269
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4085195856
Short name T932
Test name
Test status
Simulation time 13191205 ps
CPU time 1.03 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206324 kb
Host smart-1fc3a669-9612-49d4-82d9-caf2934b290f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085195856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4085195856
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2600558116
Short name T888
Test name
Test status
Simulation time 143826233 ps
CPU time 2.75 seconds
Started Apr 04 02:52:00 PM PDT 24
Finished Apr 04 02:52:03 PM PDT 24
Peak memory 214732 kb
Host smart-7df2c1ed-5623-4972-96ec-1e9e553d6714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600558116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2600558116
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1419581956
Short name T948
Test name
Test status
Simulation time 144487318 ps
CPU time 1.44 seconds
Started Apr 04 02:52:02 PM PDT 24
Finished Apr 04 02:52:04 PM PDT 24
Peak memory 206280 kb
Host smart-3a9b8349-66a7-4fd0-9a87-8d0b37223ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419581956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1419581956
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2995777964
Short name T843
Test name
Test status
Simulation time 202333240 ps
CPU time 1.47 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:15 PM PDT 24
Peak memory 214608 kb
Host smart-1dfb2c04-1425-478c-aa41-092e13a8094b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995777964 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2995777964
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.250438198
Short name T229
Test name
Test status
Simulation time 12404596 ps
CPU time 0.92 seconds
Started Apr 04 02:52:08 PM PDT 24
Finished Apr 04 02:52:10 PM PDT 24
Peak memory 206196 kb
Host smart-eefb82fc-a9d4-454e-82e5-39fdc8a71d40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250438198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.250438198
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1904468314
Short name T858
Test name
Test status
Simulation time 33868873 ps
CPU time 0.78 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 205928 kb
Host smart-9959aa33-50ec-4919-8c7a-c6dd38c98ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904468314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1904468314
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1427025241
Short name T219
Test name
Test status
Simulation time 192675425 ps
CPU time 1.42 seconds
Started Apr 04 02:52:15 PM PDT 24
Finished Apr 04 02:52:17 PM PDT 24
Peak memory 206316 kb
Host smart-76381484-8f2f-435a-8ac7-e2a1bce0c9ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427025241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1427025241
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.925968061
Short name T896
Test name
Test status
Simulation time 166751967 ps
CPU time 2.92 seconds
Started Apr 04 02:52:09 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 214824 kb
Host smart-85d45899-4b5a-4a69-b6ff-664ca5240b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925968061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.925968061
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.166233239
Short name T941
Test name
Test status
Simulation time 172694771 ps
CPU time 1.56 seconds
Started Apr 04 02:52:15 PM PDT 24
Finished Apr 04 02:52:16 PM PDT 24
Peak memory 206244 kb
Host smart-a63644bd-b3a4-44d5-9da0-2adfb12803bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166233239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.166233239
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3013462929
Short name T952
Test name
Test status
Simulation time 20883001 ps
CPU time 1 seconds
Started Apr 04 02:52:14 PM PDT 24
Finished Apr 04 02:52:15 PM PDT 24
Peak memory 206304 kb
Host smart-d7bc74ce-3e0a-4d8a-b8aa-532cd8e4bbfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013462929 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3013462929
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2670412827
Short name T223
Test name
Test status
Simulation time 31898710 ps
CPU time 0.9 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206212 kb
Host smart-88539778-c533-4460-bf6a-0a9c9290ee06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670412827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2670412827
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2801931997
Short name T855
Test name
Test status
Simulation time 14093180 ps
CPU time 0.84 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206196 kb
Host smart-009ae633-aa27-4c1c-9910-b1740d8a3383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801931997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2801931997
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3360335044
Short name T232
Test name
Test status
Simulation time 20208371 ps
CPU time 1.15 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206380 kb
Host smart-a61fb722-570f-4d85-95b4-ab6c6645435d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360335044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3360335044
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.263993760
Short name T856
Test name
Test status
Simulation time 68224626 ps
CPU time 1.61 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:15 PM PDT 24
Peak memory 214620 kb
Host smart-d690e68c-c8b7-4b4b-8607-51c5079676ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263993760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.263993760
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2412392475
Short name T944
Test name
Test status
Simulation time 107889539 ps
CPU time 2.56 seconds
Started Apr 04 02:52:09 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 206356 kb
Host smart-2058c333-6a58-44cf-bf40-2044e864fe4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412392475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2412392475
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1574439866
Short name T839
Test name
Test status
Simulation time 111111579 ps
CPU time 1.39 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 214600 kb
Host smart-3f7cce3d-18d8-4778-8158-c461ba36a87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574439866 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1574439866
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.365633881
Short name T237
Test name
Test status
Simulation time 23955095 ps
CPU time 0.8 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 205952 kb
Host smart-10f0da84-beed-49ff-b299-d0fffdffab44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365633881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.365633881
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2809503284
Short name T835
Test name
Test status
Simulation time 12102960 ps
CPU time 0.82 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:12 PM PDT 24
Peak memory 206184 kb
Host smart-4376bfba-edd3-4053-af08-41d332bc5f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809503284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2809503284
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2923104546
Short name T933
Test name
Test status
Simulation time 26596844 ps
CPU time 1.3 seconds
Started Apr 04 02:52:11 PM PDT 24
Finished Apr 04 02:52:13 PM PDT 24
Peak memory 206320 kb
Host smart-cdd142b8-4f45-430b-ad32-d057b593eaa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923104546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2923104546
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3485229839
Short name T840
Test name
Test status
Simulation time 42260319 ps
CPU time 1.74 seconds
Started Apr 04 02:52:09 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 217292 kb
Host smart-064600e1-ef79-43a6-bc52-decea9d9b813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485229839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3485229839
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2269607208
Short name T917
Test name
Test status
Simulation time 54837495 ps
CPU time 1.81 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:15 PM PDT 24
Peak memory 206428 kb
Host smart-dd9a83cc-1aeb-46a1-bbb2-6eb7215150d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269607208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2269607208
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2896578680
Short name T959
Test name
Test status
Simulation time 110074579 ps
CPU time 1.27 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 214568 kb
Host smart-524d4005-5d61-450f-9b3f-81e88cbbc03d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896578680 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2896578680
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1073289635
Short name T225
Test name
Test status
Simulation time 13613677 ps
CPU time 0.87 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206196 kb
Host smart-0dc4a4c7-b13c-43fc-bceb-24af977f94d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073289635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1073289635
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3904063813
Short name T834
Test name
Test status
Simulation time 14123734 ps
CPU time 0.86 seconds
Started Apr 04 02:52:13 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206224 kb
Host smart-c4b700c9-63cc-4e1b-bcac-10f009c3259b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904063813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3904063813
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.614855325
Short name T216
Test name
Test status
Simulation time 47026400 ps
CPU time 1.17 seconds
Started Apr 04 02:52:10 PM PDT 24
Finished Apr 04 02:52:11 PM PDT 24
Peak memory 206444 kb
Host smart-36087f1b-b656-4110-9b2f-9cca93ed6182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614855325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.614855325
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.443566447
Short name T838
Test name
Test status
Simulation time 138031021 ps
CPU time 2.81 seconds
Started Apr 04 02:52:18 PM PDT 24
Finished Apr 04 02:52:21 PM PDT 24
Peak memory 214572 kb
Host smart-0a538e04-26b8-4f52-9a1d-aac890472ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443566447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.443566447
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3760771943
Short name T889
Test name
Test status
Simulation time 199503573 ps
CPU time 1.76 seconds
Started Apr 04 02:52:12 PM PDT 24
Finished Apr 04 02:52:14 PM PDT 24
Peak memory 206292 kb
Host smart-8c5b4eb5-f4b5-446f-b07c-a65cb928ee1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760771943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3760771943
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2037976289
Short name T689
Test name
Test status
Simulation time 81817778 ps
CPU time 1.11 seconds
Started Apr 04 03:30:52 PM PDT 24
Finished Apr 04 03:30:53 PM PDT 24
Peak memory 215276 kb
Host smart-90a83c88-7b96-429d-9ddf-2756f07d1dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037976289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2037976289
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.987678961
Short name T705
Test name
Test status
Simulation time 21410358 ps
CPU time 0.83 seconds
Started Apr 04 03:30:52 PM PDT 24
Finished Apr 04 03:30:53 PM PDT 24
Peak memory 205412 kb
Host smart-ab4170e7-66db-44e8-84db-d3cfeda328ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987678961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.987678961
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.1814928563
Short name T567
Test name
Test status
Simulation time 18225486 ps
CPU time 1.19 seconds
Started Apr 04 03:30:52 PM PDT 24
Finished Apr 04 03:30:54 PM PDT 24
Peak memory 231100 kb
Host smart-36c7fda2-9bf7-4313-a29e-baf6fc634f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814928563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1814928563
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2495297247
Short name T368
Test name
Test status
Simulation time 45926054 ps
CPU time 1.43 seconds
Started Apr 04 03:30:52 PM PDT 24
Finished Apr 04 03:30:54 PM PDT 24
Peak memory 217640 kb
Host smart-68eca1dc-159c-4f5b-b678-3d177720797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495297247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2495297247
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3028611394
Short name T341
Test name
Test status
Simulation time 21687981 ps
CPU time 1.18 seconds
Started Apr 04 03:30:59 PM PDT 24
Finished Apr 04 03:31:00 PM PDT 24
Peak memory 215060 kb
Host smart-da18064f-cdf5-4390-a307-88337357487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028611394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3028611394
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4014507584
Short name T50
Test name
Test status
Simulation time 660045743 ps
CPU time 3.35 seconds
Started Apr 04 03:30:52 PM PDT 24
Finished Apr 04 03:30:56 PM PDT 24
Peak memory 233048 kb
Host smart-652ac38c-6bd9-4602-8fb1-b05fd6119ce7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014507584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4014507584
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3806608392
Short name T711
Test name
Test status
Simulation time 21671596 ps
CPU time 0.91 seconds
Started Apr 04 03:30:53 PM PDT 24
Finished Apr 04 03:30:54 PM PDT 24
Peak memory 215012 kb
Host smart-8fd4ae10-1c4d-4869-a981-1e2431f17b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806608392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3806608392
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2969067619
Short name T36
Test name
Test status
Simulation time 340996908 ps
CPU time 3.43 seconds
Started Apr 04 03:30:52 PM PDT 24
Finished Apr 04 03:30:55 PM PDT 24
Peak memory 219116 kb
Host smart-d6c5465a-3281-4a74-8700-184b9080c9cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969067619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2969067619
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.2294250896
Short name T650
Test name
Test status
Simulation time 41761555 ps
CPU time 0.85 seconds
Started Apr 04 03:31:19 PM PDT 24
Finished Apr 04 03:31:20 PM PDT 24
Peak memory 206352 kb
Host smart-ab21f4b7-8116-46b5-9543-15a2c85e895a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294250896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2294250896
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3878812401
Short name T158
Test name
Test status
Simulation time 11075808 ps
CPU time 0.88 seconds
Started Apr 04 03:31:17 PM PDT 24
Finished Apr 04 03:31:18 PM PDT 24
Peak memory 215460 kb
Host smart-c0789edf-296b-4e8e-ba44-847e244dd5af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878812401 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3878812401
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3137244362
Short name T76
Test name
Test status
Simulation time 126409633 ps
CPU time 1.13 seconds
Started Apr 04 03:31:17 PM PDT 24
Finished Apr 04 03:31:19 PM PDT 24
Peak memory 216200 kb
Host smart-228f8564-32a2-4dc1-bdd0-eb6203a33791
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137244362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3137244362
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3282745982
Short name T727
Test name
Test status
Simulation time 22681823 ps
CPU time 1.01 seconds
Started Apr 04 03:31:11 PM PDT 24
Finished Apr 04 03:31:13 PM PDT 24
Peak memory 219020 kb
Host smart-87da9a80-82f6-4c6b-a1c0-d96230bc38b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282745982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3282745982
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4082499672
Short name T306
Test name
Test status
Simulation time 73275767 ps
CPU time 1.33 seconds
Started Apr 04 03:31:03 PM PDT 24
Finished Apr 04 03:31:05 PM PDT 24
Peak memory 217480 kb
Host smart-743a0bd7-6af5-4331-86ec-d35b7f5f1f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082499672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4082499672
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.434567496
Short name T723
Test name
Test status
Simulation time 29817084 ps
CPU time 1.03 seconds
Started Apr 04 03:31:06 PM PDT 24
Finished Apr 04 03:31:07 PM PDT 24
Peak memory 223800 kb
Host smart-86c502aa-bf19-4415-857c-74fb259d7eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434567496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.434567496
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1921026354
Short name T255
Test name
Test status
Simulation time 31810130 ps
CPU time 1 seconds
Started Apr 04 03:30:53 PM PDT 24
Finished Apr 04 03:30:54 PM PDT 24
Peak memory 206820 kb
Host smart-5aff6841-b873-4b7b-b8e5-4801b9218725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921026354 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1921026354
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2382492295
Short name T20
Test name
Test status
Simulation time 939056352 ps
CPU time 6.74 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:25 PM PDT 24
Peak memory 235368 kb
Host smart-b4e79ade-1f0d-44b1-8fb4-9eb136f68a81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382492295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2382492295
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3119077399
Short name T627
Test name
Test status
Simulation time 39025104 ps
CPU time 0.87 seconds
Started Apr 04 03:30:55 PM PDT 24
Finished Apr 04 03:30:56 PM PDT 24
Peak memory 215008 kb
Host smart-10f01674-aee9-4c09-85b4-bdf581f19292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119077399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3119077399
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2839973679
Short name T569
Test name
Test status
Simulation time 375326532 ps
CPU time 7.23 seconds
Started Apr 04 03:31:03 PM PDT 24
Finished Apr 04 03:31:10 PM PDT 24
Peak memory 215008 kb
Host smart-09eb47a2-6de5-4c9e-8d0d-73e151409cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839973679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2839973679
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.3220616376
Short name T441
Test name
Test status
Simulation time 245579425 ps
CPU time 1.32 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 215276 kb
Host smart-ce34daaf-d7d8-4aa4-b7a2-c8069772cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220616376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3220616376
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1998991926
Short name T452
Test name
Test status
Simulation time 27672423 ps
CPU time 0.99 seconds
Started Apr 04 03:32:00 PM PDT 24
Finished Apr 04 03:32:01 PM PDT 24
Peak memory 206340 kb
Host smart-95588b96-f341-4998-b80e-b9205d0cf857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998991926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1998991926
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.52516653
Short name T364
Test name
Test status
Simulation time 22602407 ps
CPU time 0.86 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:49 PM PDT 24
Peak memory 215236 kb
Host smart-77b2f3cd-421e-4c34-b0b4-ed506c9303b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52516653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.52516653
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1586464443
Short name T174
Test name
Test status
Simulation time 29940366 ps
CPU time 1.17 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 232212 kb
Host smart-441ebbe7-e19c-4497-955a-1b9909850345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586464443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1586464443
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1790549677
Short name T813
Test name
Test status
Simulation time 135946972 ps
CPU time 3.05 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:51 PM PDT 24
Peak memory 218948 kb
Host smart-b4ecaa0a-3aef-4562-820c-d583d8e70fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790549677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1790549677
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3682419734
Short name T744
Test name
Test status
Simulation time 39300457 ps
CPU time 0.86 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 215088 kb
Host smart-bc185f36-3d1d-4798-adee-d38881e5821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682419734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3682419734
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3674998319
Short name T639
Test name
Test status
Simulation time 18242410 ps
CPU time 1.02 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:50 PM PDT 24
Peak memory 215064 kb
Host smart-74ccb24e-fe2c-4ba4-9f66-ddee19663949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674998319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3674998319
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4269856122
Short name T146
Test name
Test status
Simulation time 62312829534 ps
CPU time 813.47 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:45:25 PM PDT 24
Peak memory 223492 kb
Host smart-89e7897a-6d47-4f3d-ab14-56717d795497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269856122 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4269856122
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1920323795
Short name T638
Test name
Test status
Simulation time 49096270 ps
CPU time 1.14 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216272 kb
Host smart-78420f3f-ac5b-4286-b500-fa9c06cc6659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920323795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1920323795
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1531552659
Short name T44
Test name
Test status
Simulation time 79105092 ps
CPU time 1.34 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217964 kb
Host smart-bf21ba31-0786-4560-9fda-beb5787545bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531552659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1531552659
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3067366915
Short name T324
Test name
Test status
Simulation time 29979999 ps
CPU time 1.33 seconds
Started Apr 04 03:34:38 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217536 kb
Host smart-1c09f596-dcd7-4ee7-90ec-dd0dd24c1222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067366915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3067366915
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2976590966
Short name T662
Test name
Test status
Simulation time 128833626 ps
CPU time 1.38 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217404 kb
Host smart-4c2dc086-728d-4de2-8294-8e7a3e31b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976590966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2976590966
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.4091603079
Short name T358
Test name
Test status
Simulation time 225196056 ps
CPU time 3.56 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 218320 kb
Host smart-6fd00a60-1c3c-4673-8014-f8de0232c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091603079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4091603079
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.753553590
Short name T272
Test name
Test status
Simulation time 95426143 ps
CPU time 1.08 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216308 kb
Host smart-4d686f3a-0bdc-4aca-b512-25fba78ba6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753553590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.753553590
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2388619862
Short name T657
Test name
Test status
Simulation time 82143562 ps
CPU time 1.11 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216268 kb
Host smart-ab233d51-7cf4-461c-a7c0-d2ead69f94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388619862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2388619862
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.911350814
Short name T366
Test name
Test status
Simulation time 74332980 ps
CPU time 2.42 seconds
Started Apr 04 03:34:41 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 218060 kb
Host smart-b1dc420b-9f15-4600-b451-2d84f3aa946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911350814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.911350814
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable.3009645249
Short name T253
Test name
Test status
Simulation time 36461909 ps
CPU time 0.84 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 215536 kb
Host smart-ff1944e9-6ef3-4047-becb-6dcb6f15dee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009645249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3009645249
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.455053611
Short name T107
Test name
Test status
Simulation time 45187387 ps
CPU time 1.22 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:58 PM PDT 24
Peak memory 233128 kb
Host smart-6ea4ce09-d4ac-48c3-a60f-2d2156c7b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455053611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.455053611
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1906646534
Short name T805
Test name
Test status
Simulation time 53743554 ps
CPU time 1.18 seconds
Started Apr 04 03:31:55 PM PDT 24
Finished Apr 04 03:31:56 PM PDT 24
Peak memory 217796 kb
Host smart-b57d9d5c-7c78-4e35-b1d8-eeb8644cc656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906646534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1906646534
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.143290924
Short name T316
Test name
Test status
Simulation time 24250635 ps
CPU time 0.98 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 215084 kb
Host smart-4a515ebf-f877-4814-879d-f11b0c870a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143290924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.143290924
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1020841619
Short name T328
Test name
Test status
Simulation time 24301274 ps
CPU time 0.89 seconds
Started Apr 04 03:31:57 PM PDT 24
Finished Apr 04 03:31:59 PM PDT 24
Peak memory 215004 kb
Host smart-020596c5-0699-4de5-84eb-26445391eb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020841619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1020841619
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.373260467
Short name T749
Test name
Test status
Simulation time 484194514594 ps
CPU time 1808.98 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 04:02:05 PM PDT 24
Peak memory 224364 kb
Host smart-a641423f-12a0-4c36-8a74-5791e60fec43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373260467 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.373260467
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2498362860
Short name T517
Test name
Test status
Simulation time 81052394 ps
CPU time 1.12 seconds
Started Apr 04 03:35:04 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217628 kb
Host smart-e23b4cd0-44e3-432c-8bad-9a45310873cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498362860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2498362860
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3602755984
Short name T284
Test name
Test status
Simulation time 71200902 ps
CPU time 1.13 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216248 kb
Host smart-ba544cae-ca43-40d8-9ac3-3fd2296afcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602755984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3602755984
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2706454373
Short name T535
Test name
Test status
Simulation time 35374920 ps
CPU time 1.48 seconds
Started Apr 04 03:34:37 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217572 kb
Host smart-a715db8a-3f99-4f04-86fa-514f25e9a8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706454373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2706454373
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2154754470
Short name T181
Test name
Test status
Simulation time 135304124 ps
CPU time 1.45 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 217420 kb
Host smart-77097dc1-4499-4cf9-928a-34bcbb1f89fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154754470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2154754470
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1850763810
Short name T26
Test name
Test status
Simulation time 52269533 ps
CPU time 1.65 seconds
Started Apr 04 03:34:37 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216140 kb
Host smart-6b1480ea-ecf8-4806-87a2-ca9903141307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850763810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1850763810
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.4129000376
Short name T351
Test name
Test status
Simulation time 42142210 ps
CPU time 1.49 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 217616 kb
Host smart-151cee2b-6fdb-4fe4-91ef-46a6f337887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129000376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4129000376
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3426876613
Short name T448
Test name
Test status
Simulation time 35959934 ps
CPU time 1.35 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 218844 kb
Host smart-a75794e9-550d-4cad-a86e-29bc680304c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426876613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3426876613
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1737486003
Short name T437
Test name
Test status
Simulation time 112012008 ps
CPU time 0.95 seconds
Started Apr 04 03:34:38 PM PDT 24
Finished Apr 04 03:34:40 PM PDT 24
Peak memory 216168 kb
Host smart-a5ed1509-15b2-4f76-8d0c-2aab0415af03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737486003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1737486003
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1840156189
Short name T825
Test name
Test status
Simulation time 94554185 ps
CPU time 1.61 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217668 kb
Host smart-921ca98e-c6a4-48eb-9318-b92af8260ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840156189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1840156189
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3484707112
Short name T709
Test name
Test status
Simulation time 69243764 ps
CPU time 1.12 seconds
Started Apr 04 03:34:41 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 217452 kb
Host smart-e5666778-95f9-4158-9689-44e412b75b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484707112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3484707112
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2926532439
Short name T599
Test name
Test status
Simulation time 49303773 ps
CPU time 0.83 seconds
Started Apr 04 03:31:57 PM PDT 24
Finished Apr 04 03:31:58 PM PDT 24
Peak memory 205752 kb
Host smart-185bb30e-595f-4001-8e0d-8047dc34b02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926532439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2926532439
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.833526839
Short name T807
Test name
Test status
Simulation time 40654644 ps
CPU time 0.84 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 215472 kb
Host smart-2663f158-9e0f-4fe4-8f13-55888df0f03e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833526839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.833526839
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2847134178
Short name T331
Test name
Test status
Simulation time 37766427 ps
CPU time 1 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 216124 kb
Host smart-b30fecad-3813-49b1-ad6c-175e8d77aba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847134178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2847134178
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.573483957
Short name T39
Test name
Test status
Simulation time 23892273 ps
CPU time 1.03 seconds
Started Apr 04 03:31:57 PM PDT 24
Finished Apr 04 03:31:58 PM PDT 24
Peak memory 232280 kb
Host smart-6f718b26-7704-486c-9843-55a5aee95d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573483957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.573483957
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.223321762
Short name T241
Test name
Test status
Simulation time 42784383 ps
CPU time 1.07 seconds
Started Apr 04 03:31:57 PM PDT 24
Finished Apr 04 03:31:59 PM PDT 24
Peak memory 216088 kb
Host smart-9e0c00a5-fc3e-4a36-b86d-2f3d3f3e3d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223321762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.223321762
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.3913171441
Short name T179
Test name
Test status
Simulation time 19553998 ps
CPU time 1.02 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:31:57 PM PDT 24
Peak memory 214988 kb
Host smart-37af3311-c009-441b-8941-cc0ce1a001c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913171441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3913171441
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.705200232
Short name T414
Test name
Test status
Simulation time 198869860 ps
CPU time 2.86 seconds
Started Apr 04 03:32:01 PM PDT 24
Finished Apr 04 03:32:04 PM PDT 24
Peak memory 216472 kb
Host smart-7009226b-3682-46d2-b429-133f1ae65071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705200232 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.705200232
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.129540466
Short name T141
Test name
Test status
Simulation time 72797382736 ps
CPU time 429.64 seconds
Started Apr 04 03:31:56 PM PDT 24
Finished Apr 04 03:39:06 PM PDT 24
Peak memory 218068 kb
Host smart-36ad63d6-49d8-46f3-8978-07aeb4acaf46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129540466 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.129540466
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3069212106
Short name T777
Test name
Test status
Simulation time 207638041 ps
CPU time 1.54 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 217960 kb
Host smart-f0cd6574-2ccf-46dd-ac1b-69d13ab60619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069212106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3069212106
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3029314444
Short name T568
Test name
Test status
Simulation time 216902267 ps
CPU time 2.8 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:02 PM PDT 24
Peak memory 216844 kb
Host smart-9ea2cd00-7979-4ec8-99af-403e3391d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029314444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3029314444
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1264018539
Short name T391
Test name
Test status
Simulation time 55204629 ps
CPU time 1.18 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 215008 kb
Host smart-8d623006-31a2-4f2c-abf6-c8697642d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264018539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1264018539
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3100712211
Short name T826
Test name
Test status
Simulation time 42852364 ps
CPU time 1.59 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 216240 kb
Host smart-92ca869b-91ff-4532-b883-1083b38aabc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100712211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3100712211
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2648356272
Short name T616
Test name
Test status
Simulation time 71302314 ps
CPU time 1.4 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217960 kb
Host smart-5d62da66-5e03-4413-8ac2-2fb6b5e4b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648356272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2648356272
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1723259778
Short name T388
Test name
Test status
Simulation time 47721811 ps
CPU time 1.4 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 217500 kb
Host smart-cca417a2-8ccb-48a3-af9a-a818da8b69e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723259778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1723259778
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.4285331060
Short name T577
Test name
Test status
Simulation time 39251600 ps
CPU time 1.13 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 219044 kb
Host smart-6a559756-aab9-4c58-a1a8-41c12036dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285331060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.4285331060
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.780793199
Short name T740
Test name
Test status
Simulation time 35300832 ps
CPU time 1.34 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 216632 kb
Host smart-4a5e8229-ad76-491f-b1fd-fe9a1af35ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780793199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.780793199
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.724070286
Short name T34
Test name
Test status
Simulation time 16930596 ps
CPU time 0.96 seconds
Started Apr 04 03:32:12 PM PDT 24
Finished Apr 04 03:32:13 PM PDT 24
Peak memory 205716 kb
Host smart-e6ace632-56b3-4f9e-9d98-d15deb9f88c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724070286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.724070286
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3659348990
Short name T456
Test name
Test status
Simulation time 99047620 ps
CPU time 0.84 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 215084 kb
Host smart-afa392d5-dcd8-43cf-a211-1a2235d36ece
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659348990 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3659348990
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1641113351
Short name T496
Test name
Test status
Simulation time 21824827 ps
CPU time 1.01 seconds
Started Apr 04 03:32:14 PM PDT 24
Finished Apr 04 03:32:15 PM PDT 24
Peak memory 217224 kb
Host smart-98d1fba9-616e-4b0e-b183-be2411c3394f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641113351 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1641113351
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2847279139
Short name T820
Test name
Test status
Simulation time 24036775 ps
CPU time 0.91 seconds
Started Apr 04 03:32:07 PM PDT 24
Finished Apr 04 03:32:08 PM PDT 24
Peak memory 215132 kb
Host smart-2a210c11-acf2-4e82-b734-6fd1bea58998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847279139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2847279139
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.716618414
Short name T453
Test name
Test status
Simulation time 56688899 ps
CPU time 1.63 seconds
Started Apr 04 03:32:14 PM PDT 24
Finished Apr 04 03:32:16 PM PDT 24
Peak memory 217864 kb
Host smart-e3aba083-9dea-4f7b-884a-62e4adb78d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716618414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.716618414
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.80560535
Short name T589
Test name
Test status
Simulation time 24504425 ps
CPU time 1.07 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 223840 kb
Host smart-5897506e-ef54-4ece-bac3-33c01747372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80560535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.80560535
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1529753995
Short name T575
Test name
Test status
Simulation time 19950978 ps
CPU time 0.92 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 03:32:09 PM PDT 24
Peak memory 214988 kb
Host smart-23580fd0-ab29-43ce-9d2e-d9f36266805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529753995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1529753995
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3277504523
Short name T724
Test name
Test status
Simulation time 508069931 ps
CPU time 5.33 seconds
Started Apr 04 03:32:12 PM PDT 24
Finished Apr 04 03:32:18 PM PDT 24
Peak memory 216160 kb
Host smart-31c57686-422b-4059-98ca-d804ca6d3772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277504523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3277504523
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1056032015
Short name T203
Test name
Test status
Simulation time 75765864551 ps
CPU time 1721.8 seconds
Started Apr 04 03:32:10 PM PDT 24
Finished Apr 04 04:00:52 PM PDT 24
Peak memory 223880 kb
Host smart-d1404f1f-eef0-4ea0-9acb-bca1da2f98ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056032015 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1056032015
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.2833821137
Short name T407
Test name
Test status
Simulation time 68560148 ps
CPU time 1.28 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 216272 kb
Host smart-41a7434e-46fa-4e31-9db1-db11f154068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833821137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2833821137
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1252866380
Short name T780
Test name
Test status
Simulation time 41340885 ps
CPU time 1.68 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 217776 kb
Host smart-5c79faec-d527-4c38-8a2d-60c3a3101de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252866380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1252866380
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.491900090
Short name T475
Test name
Test status
Simulation time 79664219 ps
CPU time 1.18 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 216436 kb
Host smart-ff67438e-5058-4fae-95f0-d5505faf4377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491900090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.491900090
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1260142360
Short name T792
Test name
Test status
Simulation time 49460452 ps
CPU time 1.36 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217340 kb
Host smart-a88e28a4-65d4-4468-a472-e4d7d7d3d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260142360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1260142360
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.513418233
Short name T417
Test name
Test status
Simulation time 57971300 ps
CPU time 1.22 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217540 kb
Host smart-1387ae41-9a25-4837-a23b-3d9cfc56eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513418233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.513418233
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2056369655
Short name T205
Test name
Test status
Simulation time 69940858 ps
CPU time 1.71 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217708 kb
Host smart-c47eec18-7d8d-4a72-97f1-991c57b9fb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056369655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2056369655
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.4061964697
Short name T262
Test name
Test status
Simulation time 51981026 ps
CPU time 1.24 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 215260 kb
Host smart-0a265e38-6fd0-4dbe-bb46-9c6b9c1887b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061964697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4061964697
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2830802217
Short name T295
Test name
Test status
Simulation time 47799368 ps
CPU time 0.97 seconds
Started Apr 04 03:32:17 PM PDT 24
Finished Apr 04 03:32:18 PM PDT 24
Peak memory 205728 kb
Host smart-87a4f8b7-fbdf-457a-ba2b-a966ba71d6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830802217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2830802217
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1016993180
Short name T594
Test name
Test status
Simulation time 40223327 ps
CPU time 0.88 seconds
Started Apr 04 03:32:16 PM PDT 24
Finished Apr 04 03:32:17 PM PDT 24
Peak memory 215048 kb
Host smart-a68cdeab-4ed4-48d5-a221-b60f01f01572
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016993180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1016993180
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4271998775
Short name T663
Test name
Test status
Simulation time 84574933 ps
CPU time 1.05 seconds
Started Apr 04 03:32:16 PM PDT 24
Finished Apr 04 03:32:17 PM PDT 24
Peak memory 217356 kb
Host smart-a3537f8c-c457-440e-8216-e2fcb4d31bff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271998775 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4271998775
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2660763587
Short name T712
Test name
Test status
Simulation time 18666752 ps
CPU time 1.01 seconds
Started Apr 04 03:32:11 PM PDT 24
Finished Apr 04 03:32:12 PM PDT 24
Peak memory 217264 kb
Host smart-f60fbe45-1c96-4255-9327-5cf01befd896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660763587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2660763587
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.638448638
Short name T138
Test name
Test status
Simulation time 20439930 ps
CPU time 1.06 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 215300 kb
Host smart-5cccc406-05d4-42b3-9d56-363d2e12f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638448638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.638448638
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.715452750
Short name T591
Test name
Test status
Simulation time 23690304 ps
CPU time 0.89 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 214980 kb
Host smart-1f6ca007-d235-4490-bcb2-03b2adf0c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715452750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.715452750
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.972836024
Short name T420
Test name
Test status
Simulation time 304947266 ps
CPU time 5.69 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 03:32:14 PM PDT 24
Peak memory 219300 kb
Host smart-ffbfa281-ffa8-44be-bb84-ce0914f578f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972836024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.972836024
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1200385763
Short name T403
Test name
Test status
Simulation time 302527723196 ps
CPU time 3385.35 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 04:28:34 PM PDT 24
Peak memory 232404 kb
Host smart-fb306be8-7297-4c98-89f2-741358612f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200385763 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1200385763
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1416981314
Short name T767
Test name
Test status
Simulation time 32164071 ps
CPU time 0.99 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 216188 kb
Host smart-1d0c6548-dfd4-4d13-b52d-291584c3d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416981314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1416981314
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.833495021
Short name T708
Test name
Test status
Simulation time 168546376 ps
CPU time 1.18 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 216264 kb
Host smart-e8e933cb-79ad-4351-a362-454456514265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833495021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.833495021
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4256357548
Short name T474
Test name
Test status
Simulation time 97917942 ps
CPU time 1.25 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 216364 kb
Host smart-ccb9d9a6-99cf-483b-a292-5a30da4da921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256357548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4256357548
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.302553985
Short name T704
Test name
Test status
Simulation time 40926175 ps
CPU time 1.51 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217564 kb
Host smart-49effef6-2af7-4b98-95e8-51c5a0af7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302553985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.302553985
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2216491495
Short name T461
Test name
Test status
Simulation time 40635141 ps
CPU time 1.11 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 216376 kb
Host smart-48fb0c2c-0fba-4392-a648-9d2d0ccafd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216491495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2216491495
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1449340863
Short name T455
Test name
Test status
Simulation time 4567713350 ps
CPU time 90 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 219636 kb
Host smart-69618a86-e9d8-49dc-b767-782e0be29362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449340863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1449340863
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1430238323
Short name T383
Test name
Test status
Simulation time 125267982 ps
CPU time 1.57 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 217988 kb
Host smart-888a63cd-2701-48d6-ad62-0441b88bd979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430238323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1430238323
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2651303564
Short name T754
Test name
Test status
Simulation time 38790230 ps
CPU time 1.47 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 216372 kb
Host smart-518840cd-de9d-45f5-931c-044c83dc1c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651303564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2651303564
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2993872302
Short name T555
Test name
Test status
Simulation time 175448787 ps
CPU time 2.27 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 218532 kb
Host smart-f97ac177-4f3f-484f-b600-3220bece9c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993872302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2993872302
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.906029935
Short name T111
Test name
Test status
Simulation time 95807524 ps
CPU time 1.06 seconds
Started Apr 04 03:32:14 PM PDT 24
Finished Apr 04 03:32:15 PM PDT 24
Peak memory 215276 kb
Host smart-910d50ec-0c2f-4fcb-9b00-e07ba223849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906029935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.906029935
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2935608728
Short name T33
Test name
Test status
Simulation time 81794818 ps
CPU time 0.88 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 03:32:09 PM PDT 24
Peak memory 205664 kb
Host smart-16108f17-68f1-450e-925a-b4205dc0594e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935608728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2935608728
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1118516516
Short name T626
Test name
Test status
Simulation time 13294320 ps
CPU time 0.92 seconds
Started Apr 04 03:32:11 PM PDT 24
Finished Apr 04 03:32:12 PM PDT 24
Peak memory 215288 kb
Host smart-cd26f7f7-7873-43aa-bccc-cdf91c7ab0af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118516516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1118516516
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.745249000
Short name T443
Test name
Test status
Simulation time 19280103 ps
CPU time 1.11 seconds
Started Apr 04 03:32:09 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 217808 kb
Host smart-254a7aec-1c79-45d0-9b4d-62497d111387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745249000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.745249000
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1160085028
Short name T757
Test name
Test status
Simulation time 40471429 ps
CPU time 1.51 seconds
Started Apr 04 03:32:17 PM PDT 24
Finished Apr 04 03:32:19 PM PDT 24
Peak memory 217440 kb
Host smart-f423bdaf-8450-4d29-bc85-1ba94283fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160085028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1160085028
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3272539046
Short name T728
Test name
Test status
Simulation time 22505686 ps
CPU time 1.04 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 03:32:10 PM PDT 24
Peak memory 215080 kb
Host smart-d38474b6-0294-4559-9b64-0423cd38b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272539046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3272539046
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2039365753
Short name T550
Test name
Test status
Simulation time 51826281 ps
CPU time 0.92 seconds
Started Apr 04 03:32:08 PM PDT 24
Finished Apr 04 03:32:09 PM PDT 24
Peak memory 214972 kb
Host smart-20ba34da-c863-4f44-a6db-cc45e9282f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039365753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2039365753
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2920921713
Short name T340
Test name
Test status
Simulation time 1132254756 ps
CPU time 2.11 seconds
Started Apr 04 03:32:11 PM PDT 24
Finished Apr 04 03:32:13 PM PDT 24
Peak memory 214996 kb
Host smart-66600320-5fda-4982-a37f-d6da4745e488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920921713 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2920921713
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1802618712
Short name T201
Test name
Test status
Simulation time 192423975284 ps
CPU time 1828.05 seconds
Started Apr 04 03:32:11 PM PDT 24
Finished Apr 04 04:02:39 PM PDT 24
Peak memory 224712 kb
Host smart-e70961b9-5517-4da4-b9c3-921bb96624b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802618712 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1802618712
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2683951779
Short name T542
Test name
Test status
Simulation time 33215665 ps
CPU time 1.55 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:01 PM PDT 24
Peak memory 217508 kb
Host smart-abe10f11-6416-45f5-906a-6dfbe79fe9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683951779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2683951779
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3704816018
Short name T736
Test name
Test status
Simulation time 110615266 ps
CPU time 1.58 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217792 kb
Host smart-700ea884-c2f5-481e-a172-c4ec9c39f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704816018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3704816018
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.4241150233
Short name T532
Test name
Test status
Simulation time 204664592 ps
CPU time 1.13 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 216308 kb
Host smart-cbd181d6-4b3f-4677-960a-a69f07305038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241150233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4241150233
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2489326865
Short name T360
Test name
Test status
Simulation time 313919273 ps
CPU time 3.98 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:07 PM PDT 24
Peak memory 217648 kb
Host smart-28a10887-68a3-47db-ae16-6a0fa84a1817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489326865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2489326865
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.4100707545
Short name T743
Test name
Test status
Simulation time 157474289 ps
CPU time 1.16 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 216544 kb
Host smart-1fbb91d6-b659-4e4d-90be-f87d101a3114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100707545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4100707545
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1741964703
Short name T329
Test name
Test status
Simulation time 38804124 ps
CPU time 1.5 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 217844 kb
Host smart-dc5d9092-46bd-49f6-badc-fb44533ecf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741964703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1741964703
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2472323394
Short name T248
Test name
Test status
Simulation time 68148024 ps
CPU time 1.31 seconds
Started Apr 04 03:34:56 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 217408 kb
Host smart-0526a884-4f44-4259-9769-4bdefe5e0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472323394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2472323394
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2296848423
Short name T193
Test name
Test status
Simulation time 49146502 ps
CPU time 1.51 seconds
Started Apr 04 03:34:57 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 217372 kb
Host smart-cbad71a3-d530-4885-8c81-3f06b57d73d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296848423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2296848423
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.390990793
Short name T381
Test name
Test status
Simulation time 48867081 ps
CPU time 1.24 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:34:59 PM PDT 24
Peak memory 218576 kb
Host smart-3c19ff12-d856-4d26-beb3-8b116fe6524e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390990793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.390990793
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2561367455
Short name T105
Test name
Test status
Simulation time 51666603 ps
CPU time 1.23 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 215244 kb
Host smart-ed0d1df7-3ec1-4995-a470-106fda92d2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561367455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2561367455
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3145757493
Short name T698
Test name
Test status
Simulation time 18334183 ps
CPU time 0.82 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 205420 kb
Host smart-452c90d0-6f0e-4f50-95a0-0f1c85cc2687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145757493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3145757493
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2439813725
Short name T165
Test name
Test status
Simulation time 22022369 ps
CPU time 0.84 seconds
Started Apr 04 03:32:27 PM PDT 24
Finished Apr 04 03:32:28 PM PDT 24
Peak memory 215412 kb
Host smart-11d0fa34-6cbd-4e5f-a272-d0106b7a77fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439813725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2439813725
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.817599101
Short name T520
Test name
Test status
Simulation time 19757750 ps
CPU time 1.08 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 217492 kb
Host smart-be7cf115-28b3-4406-840e-96fb1ea68565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817599101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.817599101
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2003611000
Short name T829
Test name
Test status
Simulation time 91171280 ps
CPU time 1.09 seconds
Started Apr 04 03:32:27 PM PDT 24
Finished Apr 04 03:32:28 PM PDT 24
Peak memory 216364 kb
Host smart-667520f8-ae76-4218-b96b-be24e2766857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003611000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2003611000
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1275011210
Short name T819
Test name
Test status
Simulation time 25582903 ps
CPU time 0.99 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:32:27 PM PDT 24
Peak memory 215100 kb
Host smart-62cf46de-a85b-4490-9979-d490ad81ce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275011210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1275011210
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.551887204
Short name T526
Test name
Test status
Simulation time 71573420 ps
CPU time 0.86 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:32:27 PM PDT 24
Peak memory 214952 kb
Host smart-fa37df31-f847-419d-9744-c5cbf93cd77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551887204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.551887204
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.813766683
Short name T648
Test name
Test status
Simulation time 191963550 ps
CPU time 2.34 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 216176 kb
Host smart-88b3a9be-1942-48c5-aa53-c11a45a2de6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813766683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.813766683
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1038767371
Short name T804
Test name
Test status
Simulation time 156755836223 ps
CPU time 1985.31 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 04:05:33 PM PDT 24
Peak memory 228964 kb
Host smart-f081800d-aa6d-486d-b814-870e0adeb2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038767371 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1038767371
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1877239783
Short name T529
Test name
Test status
Simulation time 86654405 ps
CPU time 1.02 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:57 PM PDT 24
Peak memory 216500 kb
Host smart-4e136770-7f73-4695-91db-0e0c0224fa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877239783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1877239783
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3356637943
Short name T335
Test name
Test status
Simulation time 123685489 ps
CPU time 1.33 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216596 kb
Host smart-0886b461-0026-4755-8d90-0232fa91595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356637943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3356637943
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1751967888
Short name T265
Test name
Test status
Simulation time 150660210 ps
CPU time 1.1 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 217484 kb
Host smart-1a445449-143a-46aa-9a3b-215e83d1b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751967888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1751967888
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2716996987
Short name T59
Test name
Test status
Simulation time 75133464 ps
CPU time 1.27 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 217676 kb
Host smart-6c4d281c-eaff-4328-b0ef-e2cffe6f9583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716996987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2716996987
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.545553770
Short name T147
Test name
Test status
Simulation time 31375160 ps
CPU time 1.23 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 215896 kb
Host smart-af153ea3-889e-415c-9993-960778458963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545553770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.545553770
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2426951860
Short name T144
Test name
Test status
Simulation time 82904027 ps
CPU time 1.24 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 216392 kb
Host smart-652498ed-39e8-4bbf-bc00-1fb1f5aa89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426951860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2426951860
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3118000672
Short name T702
Test name
Test status
Simulation time 335282184 ps
CPU time 3.36 seconds
Started Apr 04 03:34:55 PM PDT 24
Finished Apr 04 03:34:58 PM PDT 24
Peak memory 219368 kb
Host smart-51cfe6ef-23ef-4113-aad5-7124f6ae8ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118000672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3118000672
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1396467815
Short name T353
Test name
Test status
Simulation time 86030835 ps
CPU time 1.19 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216420 kb
Host smart-0976353e-1d3d-4a83-8900-8bdbfe6db0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396467815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1396467815
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.954399029
Short name T507
Test name
Test status
Simulation time 26236672 ps
CPU time 1.22 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 217516 kb
Host smart-781ad27c-7fe7-4066-9524-b35fbef41048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954399029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.954399029
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.798778486
Short name T478
Test name
Test status
Simulation time 66093213 ps
CPU time 1.08 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 216280 kb
Host smart-8a2a2119-b99c-4797-b6cc-b5d9365194a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798778486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.798778486
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2231112791
Short name T243
Test name
Test status
Simulation time 39718465 ps
CPU time 1.12 seconds
Started Apr 04 03:32:30 PM PDT 24
Finished Apr 04 03:32:31 PM PDT 24
Peak memory 215304 kb
Host smart-13a6b051-ffa2-4a67-8622-1c564166d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231112791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2231112791
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3513274302
Short name T297
Test name
Test status
Simulation time 16807937 ps
CPU time 0.95 seconds
Started Apr 04 03:32:27 PM PDT 24
Finished Apr 04 03:32:28 PM PDT 24
Peak memory 206340 kb
Host smart-2fe0ad6c-c9f0-486f-afef-39ae4b953c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513274302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3513274302
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1141894899
Short name T786
Test name
Test status
Simulation time 11371525 ps
CPU time 0.86 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 215056 kb
Host smart-822d7464-0bc0-4643-9ab9-50df40dcdcd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141894899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1141894899
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.538543878
Short name T518
Test name
Test status
Simulation time 23274245 ps
CPU time 0.97 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 217760 kb
Host smart-67bc29b9-07c7-4989-8b09-68709f872d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538543878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.538543878
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3396008750
Short name T511
Test name
Test status
Simulation time 31400052 ps
CPU time 1.31 seconds
Started Apr 04 03:32:27 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 216100 kb
Host smart-84433d0a-3be1-4f3c-b1a9-185118aee392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396008750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3396008750
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3505998919
Short name T459
Test name
Test status
Simulation time 22470866 ps
CPU time 1.07 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:32:27 PM PDT 24
Peak memory 215136 kb
Host smart-ef9fc17d-c82f-4e0b-bf91-c9a9993e0de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505998919 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3505998919
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1263553112
Short name T617
Test name
Test status
Simulation time 44221461 ps
CPU time 0.89 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 214988 kb
Host smart-027e8640-ed1d-4fc5-a261-ee133bb8841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263553112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1263553112
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1716520800
Short name T397
Test name
Test status
Simulation time 619301376 ps
CPU time 6.47 seconds
Started Apr 04 03:32:30 PM PDT 24
Finished Apr 04 03:32:36 PM PDT 24
Peak memory 216272 kb
Host smart-9021785f-8d7c-4935-825a-9d3571036bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716520800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1716520800
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3413818557
Short name T593
Test name
Test status
Simulation time 126129936430 ps
CPU time 1657.23 seconds
Started Apr 04 03:32:27 PM PDT 24
Finished Apr 04 04:00:05 PM PDT 24
Peak memory 226276 kb
Host smart-e0e726dc-21c4-4186-abd8-b7bdd48c8e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413818557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3413818557
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1003471498
Short name T446
Test name
Test status
Simulation time 46697103 ps
CPU time 1.75 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217376 kb
Host smart-39804710-42d3-4cfc-8d73-6a4be3936b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003471498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1003471498
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2028371104
Short name T321
Test name
Test status
Simulation time 57273053 ps
CPU time 1.2 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 219084 kb
Host smart-5f9624ac-56c1-4db4-86ac-0a4def234233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028371104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2028371104
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.616055930
Short name T375
Test name
Test status
Simulation time 122270680 ps
CPU time 1.66 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217644 kb
Host smart-a379b951-f7eb-4f9d-98b2-d55a0a719f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616055930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.616055930
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2709633179
Short name T361
Test name
Test status
Simulation time 66334103 ps
CPU time 1.06 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 216396 kb
Host smart-298055e9-3242-49a9-be89-31a64715ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709633179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2709633179
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4059079457
Short name T772
Test name
Test status
Simulation time 55060657 ps
CPU time 1.37 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:01 PM PDT 24
Peak memory 217340 kb
Host smart-e493679d-cb82-4f0c-99d9-2d9f940d72d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059079457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4059079457
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1233611241
Short name T537
Test name
Test status
Simulation time 59012930 ps
CPU time 1.41 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217612 kb
Host smart-c8fe95c7-f503-4ad6-aa0f-64cb9acc0d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233611241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1233611241
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1699987319
Short name T706
Test name
Test status
Simulation time 55936898 ps
CPU time 1.83 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217348 kb
Host smart-2055b930-2bcc-4b1f-87d6-e0c9a9272b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699987319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1699987319
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2132577544
Short name T634
Test name
Test status
Simulation time 35665025 ps
CPU time 1.34 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 219020 kb
Host smart-0f826c75-3dae-4c55-b614-b0416ffc2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132577544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2132577544
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1114925212
Short name T373
Test name
Test status
Simulation time 111323479 ps
CPU time 2.16 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 219272 kb
Host smart-6c1a0326-f00a-41fe-bfc4-bbd3598c5343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114925212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1114925212
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1248218113
Short name T645
Test name
Test status
Simulation time 79694981 ps
CPU time 1.25 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217992 kb
Host smart-16352609-6676-42d8-9e4c-c6353971d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248218113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1248218113
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.291685207
Short name T126
Test name
Test status
Simulation time 25539242 ps
CPU time 1.18 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:31 PM PDT 24
Peak memory 215252 kb
Host smart-44bc1b3a-888c-439b-a28d-914e56d9c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291685207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.291685207
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1292787998
Short name T450
Test name
Test status
Simulation time 23544655 ps
CPU time 0.88 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:32:27 PM PDT 24
Peak memory 206320 kb
Host smart-3a78adce-2be4-4585-bfc1-cffed306ac48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292787998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1292787998
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3822400959
Short name T628
Test name
Test status
Simulation time 53957908 ps
CPU time 0.88 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 215180 kb
Host smart-27d4eff0-9f76-4975-aa98-e08b7b810f88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822400959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3822400959
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2832948689
Short name T561
Test name
Test status
Simulation time 95240916 ps
CPU time 1.11 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 217584 kb
Host smart-baa12b0c-33cf-4b0d-9f59-9681aad2195c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832948689 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2832948689
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2891721353
Short name T624
Test name
Test status
Simulation time 26397016 ps
CPU time 0.91 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 217224 kb
Host smart-908d163f-20b3-496f-a029-02bc73c54f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891721353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2891721353
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3950507700
Short name T808
Test name
Test status
Simulation time 110570227 ps
CPU time 1.23 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:32:28 PM PDT 24
Peak memory 218916 kb
Host smart-a82202e0-d5d4-4204-a018-9c0122545f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950507700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3950507700
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3623902765
Short name T336
Test name
Test status
Simulation time 23928990 ps
CPU time 0.98 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 215180 kb
Host smart-2b7665e1-5a97-4b4a-8521-81534add8d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623902765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3623902765
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4167489880
Short name T578
Test name
Test status
Simulation time 17789452 ps
CPU time 1.02 seconds
Started Apr 04 03:32:30 PM PDT 24
Finished Apr 04 03:32:31 PM PDT 24
Peak memory 215040 kb
Host smart-3e553d7d-c4db-483e-b895-903265222445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167489880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4167489880
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1166578317
Short name T748
Test name
Test status
Simulation time 259687889 ps
CPU time 5.29 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:34 PM PDT 24
Peak memory 215028 kb
Host smart-1dad88c6-4da5-429e-8761-0c2db5318d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166578317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1166578317
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_genbits.3318811894
Short name T684
Test name
Test status
Simulation time 43798291 ps
CPU time 1.4 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 214988 kb
Host smart-5dccba4b-4aa4-4496-a217-17471e5ba979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318811894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3318811894
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.944650989
Short name T584
Test name
Test status
Simulation time 100959024 ps
CPU time 1.39 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 219260 kb
Host smart-e8631c83-df04-422a-8b31-04301f11417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944650989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.944650989
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.896504354
Short name T710
Test name
Test status
Simulation time 71708135 ps
CPU time 1.44 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 219164 kb
Host smart-a7cd9813-8e9b-4e06-9f94-5d8d5e36fb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896504354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.896504354
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1548326146
Short name T247
Test name
Test status
Simulation time 73720004 ps
CPU time 1.62 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217708 kb
Host smart-769649d3-0229-45eb-86d1-0cc98b377adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548326146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1548326146
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.703381095
Short name T292
Test name
Test status
Simulation time 67331652 ps
CPU time 1.65 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217492 kb
Host smart-e23170e6-fc01-4af1-8213-965040fc702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703381095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.703381095
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2903608899
Short name T649
Test name
Test status
Simulation time 106299410 ps
CPU time 1.35 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216360 kb
Host smart-0329a163-f30e-4060-befb-4c77ac98cf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903608899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2903608899
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2135426283
Short name T317
Test name
Test status
Simulation time 366798498 ps
CPU time 2.16 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217960 kb
Host smart-9339d00f-537b-4c14-9cf6-0e7b6a07244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135426283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2135426283
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3638218166
Short name T519
Test name
Test status
Simulation time 75880618 ps
CPU time 2.96 seconds
Started Apr 04 03:35:03 PM PDT 24
Finished Apr 04 03:35:07 PM PDT 24
Peak memory 217564 kb
Host smart-5438df80-c2ae-430d-aeea-b3a73d1d03e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638218166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3638218166
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.325359765
Short name T760
Test name
Test status
Simulation time 78851386 ps
CPU time 1.37 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217964 kb
Host smart-7ee7e4f9-a59a-4aa3-b990-04f03fef3352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325359765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.325359765
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.662535877
Short name T799
Test name
Test status
Simulation time 114275187 ps
CPU time 1.22 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 218648 kb
Host smart-9d0f404e-f5bc-473d-b829-89ccff191351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662535877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.662535877
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.1705819918
Short name T581
Test name
Test status
Simulation time 54910004 ps
CPU time 0.96 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 206236 kb
Host smart-c8070598-158f-42b8-b939-f75ed136ec57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705819918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1705819918
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.719536239
Short name T122
Test name
Test status
Simulation time 40545877 ps
CPU time 0.83 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 215476 kb
Host smart-a7dd2d9c-acdc-44c1-bbb2-c706253153bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719536239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.719536239
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.971605754
Short name T531
Test name
Test status
Simulation time 27834041 ps
CPU time 1.1 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 217440 kb
Host smart-3ca4a117-a509-4659-b54a-7e751e102da5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971605754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.971605754
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1967303312
Short name T613
Test name
Test status
Simulation time 21561083 ps
CPU time 0.92 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 217608 kb
Host smart-7db3e39f-b2ad-4870-9c89-750c74e9a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967303312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1967303312
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4071995599
Short name T419
Test name
Test status
Simulation time 49105380 ps
CPU time 1.19 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 217664 kb
Host smart-5bee8956-da66-4e7d-8d28-21edf5701da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071995599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4071995599
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3273086619
Short name T378
Test name
Test status
Simulation time 20956300 ps
CPU time 1.04 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:32:27 PM PDT 24
Peak memory 215180 kb
Host smart-87cb944e-62a4-461c-8cdd-debde469d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273086619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3273086619
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.943580874
Short name T830
Test name
Test status
Simulation time 35155098 ps
CPU time 0.99 seconds
Started Apr 04 03:32:27 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 214948 kb
Host smart-c187417f-ca85-48a4-b91c-b28138be259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943580874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.943580874
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1302477632
Short name T209
Test name
Test status
Simulation time 850195852 ps
CPU time 4.67 seconds
Started Apr 04 03:32:30 PM PDT 24
Finished Apr 04 03:32:35 PM PDT 24
Peak memory 217460 kb
Host smart-0add6dbe-f0aa-47b2-bdb3-61916fbfb8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302477632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1302477632
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1258791337
Short name T197
Test name
Test status
Simulation time 32028946798 ps
CPU time 685.34 seconds
Started Apr 04 03:32:26 PM PDT 24
Finished Apr 04 03:43:52 PM PDT 24
Peak memory 218332 kb
Host smart-1c727dcb-e383-4203-888d-3bfd10b7a33f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258791337 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1258791337
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2262058565
Short name T349
Test name
Test status
Simulation time 29398851 ps
CPU time 1.21 seconds
Started Apr 04 03:35:03 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217584 kb
Host smart-39903f24-a839-41da-930a-0057dc6ccc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262058565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2262058565
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2090140839
Short name T55
Test name
Test status
Simulation time 33698125 ps
CPU time 1.24 seconds
Started Apr 04 03:35:05 PM PDT 24
Finished Apr 04 03:35:07 PM PDT 24
Peak memory 216484 kb
Host smart-74555b58-929d-4eeb-b3b7-b448fabf0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090140839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2090140839
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1131175371
Short name T604
Test name
Test status
Simulation time 140124085 ps
CPU time 0.99 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216392 kb
Host smart-763b2a34-44d2-40aa-a780-4704d4761be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131175371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1131175371
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2232226873
Short name T655
Test name
Test status
Simulation time 33620681 ps
CPU time 1.29 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217560 kb
Host smart-c53a1b78-ef4c-4498-a0e4-5b0333b03a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232226873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2232226873
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3644845748
Short name T489
Test name
Test status
Simulation time 37813262 ps
CPU time 1.41 seconds
Started Apr 04 03:35:07 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 219012 kb
Host smart-d261bfad-bf96-4b40-85a3-d033af63e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644845748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3644845748
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2694126773
Short name T750
Test name
Test status
Simulation time 78095928 ps
CPU time 1.37 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:08 PM PDT 24
Peak memory 217820 kb
Host smart-4d67b8bf-0347-4500-b495-50d35962cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694126773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2694126773
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3773982636
Short name T816
Test name
Test status
Simulation time 26321597 ps
CPU time 1.19 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:07 PM PDT 24
Peak memory 216240 kb
Host smart-c0c496b1-ac8b-4cca-9ad4-eed8081a2205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773982636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3773982636
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3002713283
Short name T376
Test name
Test status
Simulation time 192201614 ps
CPU time 1.12 seconds
Started Apr 04 03:35:07 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216208 kb
Host smart-d55def88-6f01-44f2-8b44-0098ad79aa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002713283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3002713283
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3736195919
Short name T828
Test name
Test status
Simulation time 164417147 ps
CPU time 1.68 seconds
Started Apr 04 03:35:03 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217616 kb
Host smart-e331e435-6ec4-4d2f-8670-440057e0b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736195919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3736195919
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2892051370
Short name T29
Test name
Test status
Simulation time 99970876 ps
CPU time 1.62 seconds
Started Apr 04 03:35:03 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217880 kb
Host smart-cfbc9966-9d39-4f91-9b49-5ef959ee8de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892051370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2892051370
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3635611625
Short name T260
Test name
Test status
Simulation time 22727597 ps
CPU time 1.15 seconds
Started Apr 04 03:31:17 PM PDT 24
Finished Apr 04 03:31:18 PM PDT 24
Peak memory 215212 kb
Host smart-bb6e1e7a-4e21-45ce-980b-d6f6e8949626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635611625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3635611625
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.132066614
Short name T729
Test name
Test status
Simulation time 84156413 ps
CPU time 0.93 seconds
Started Apr 04 03:31:17 PM PDT 24
Finished Apr 04 03:31:18 PM PDT 24
Peak memory 206244 kb
Host smart-e25ae023-8248-4aa5-97b1-4ab20f680000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132066614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.132066614
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3042997057
Short name T618
Test name
Test status
Simulation time 25869703 ps
CPU time 1.1 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:19 PM PDT 24
Peak memory 215984 kb
Host smart-c24915e7-d389-4cf2-9750-0e89f36a2f80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042997057 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3042997057
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_genbits.2431084272
Short name T796
Test name
Test status
Simulation time 56843518 ps
CPU time 1.09 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:19 PM PDT 24
Peak memory 215076 kb
Host smart-e4688b42-f83e-4a06-9acd-b26029923f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431084272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2431084272
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.588121845
Short name T803
Test name
Test status
Simulation time 27844889 ps
CPU time 1.08 seconds
Started Apr 04 03:31:19 PM PDT 24
Finished Apr 04 03:31:21 PM PDT 24
Peak memory 223764 kb
Host smart-d51b79ae-79ee-423d-80ad-1704b4ee7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588121845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.588121845
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.751009578
Short name T135
Test name
Test status
Simulation time 18877270 ps
CPU time 1.05 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:19 PM PDT 24
Peak memory 206788 kb
Host smart-0ecd581a-1347-4626-97fc-6527fc107127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751009578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.751009578
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.1494620922
Short name T506
Test name
Test status
Simulation time 29837784 ps
CPU time 0.94 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:19 PM PDT 24
Peak memory 215020 kb
Host smart-2abd2e0f-1180-4aeb-b7b3-64a15117758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494620922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1494620922
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2180052265
Short name T367
Test name
Test status
Simulation time 223461360 ps
CPU time 4.43 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:23 PM PDT 24
Peak memory 216276 kb
Host smart-6025d3b2-20a3-4f14-857d-13efc9ffe3a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180052265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2180052265
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3566764145
Short name T571
Test name
Test status
Simulation time 177295522472 ps
CPU time 710.83 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:43:09 PM PDT 24
Peak memory 219012 kb
Host smart-f8cb3b59-8715-4ebb-b3a0-8291d2d09688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566764145 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3566764145
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.1788153824
Short name T530
Test name
Test status
Simulation time 18028614 ps
CPU time 1.01 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:44 PM PDT 24
Peak memory 205732 kb
Host smart-ac23fee1-2c2d-4c86-97b3-da0fc5b7f659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788153824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1788153824
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.916036191
Short name T184
Test name
Test status
Simulation time 20445316 ps
CPU time 0.81 seconds
Started Apr 04 03:32:30 PM PDT 24
Finished Apr 04 03:32:31 PM PDT 24
Peak memory 215060 kb
Host smart-95411fb6-ea3f-47eb-bb6e-75cf2ce54103
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916036191 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.916036191
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.971626798
Short name T566
Test name
Test status
Simulation time 29779447 ps
CPU time 0.9 seconds
Started Apr 04 03:32:30 PM PDT 24
Finished Apr 04 03:32:31 PM PDT 24
Peak memory 217352 kb
Host smart-8d896472-335f-4a10-9c16-3e2d8f844cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971626798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.971626798
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1802645116
Short name T58
Test name
Test status
Simulation time 52334667 ps
CPU time 1.47 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:31 PM PDT 24
Peak memory 217380 kb
Host smart-472bb415-bad1-497a-aea8-ab9bcfd3711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802645116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1802645116
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4212962476
Short name T590
Test name
Test status
Simulation time 40761563 ps
CPU time 0.83 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:29 PM PDT 24
Peak memory 215208 kb
Host smart-1116f43e-ab0d-4ee3-a9a2-410d0a380974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212962476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4212962476
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.76774457
Short name T699
Test name
Test status
Simulation time 30172872 ps
CPU time 0.99 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 214972 kb
Host smart-244b467c-fc85-4626-8d77-6c3e8d1e8c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76774457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.76774457
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2689028065
Short name T556
Test name
Test status
Simulation time 67299045 ps
CPU time 1.36 seconds
Started Apr 04 03:32:29 PM PDT 24
Finished Apr 04 03:32:30 PM PDT 24
Peak memory 215004 kb
Host smart-8f82c58e-9865-4e35-ac11-181948ff1de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689028065 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2689028065
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2303989699
Short name T592
Test name
Test status
Simulation time 73073777473 ps
CPU time 1642.96 seconds
Started Apr 04 03:32:28 PM PDT 24
Finished Apr 04 03:59:52 PM PDT 24
Peak memory 223544 kb
Host smart-dfe35142-1769-41bd-8957-70a6cb99a5b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303989699 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2303989699
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4262231795
Short name T718
Test name
Test status
Simulation time 96182206 ps
CPU time 1.14 seconds
Started Apr 04 03:35:09 PM PDT 24
Finished Apr 04 03:35:11 PM PDT 24
Peak memory 218892 kb
Host smart-edb9fed5-3a3c-4758-bdee-30193329c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262231795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4262231795
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1179684701
Short name T314
Test name
Test status
Simulation time 150368300 ps
CPU time 1.15 seconds
Started Apr 04 03:35:10 PM PDT 24
Finished Apr 04 03:35:11 PM PDT 24
Peak memory 217692 kb
Host smart-c3a5a439-141a-42ab-abf1-3cd2142f8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179684701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1179684701
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.914023115
Short name T382
Test name
Test status
Simulation time 74403111 ps
CPU time 1.75 seconds
Started Apr 04 03:35:11 PM PDT 24
Finished Apr 04 03:35:14 PM PDT 24
Peak memory 217788 kb
Host smart-167ceac4-15c0-4e32-832b-0c09ac9eab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914023115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.914023115
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2542881543
Short name T377
Test name
Test status
Simulation time 83838594 ps
CPU time 1.46 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217732 kb
Host smart-024e09fc-1550-45c2-a9d9-6355094ed516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542881543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2542881543
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2983831884
Short name T267
Test name
Test status
Simulation time 60968974 ps
CPU time 1.32 seconds
Started Apr 04 03:35:07 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216524 kb
Host smart-76c1e055-25da-46a8-bc95-3bc34c296682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983831884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2983831884
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1849082572
Short name T347
Test name
Test status
Simulation time 38991997 ps
CPU time 1.36 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:08 PM PDT 24
Peak memory 217684 kb
Host smart-c72d51cc-9020-4490-82a5-808422ee8d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849082572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1849082572
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3819765458
Short name T319
Test name
Test status
Simulation time 47720203 ps
CPU time 1 seconds
Started Apr 04 03:35:05 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216392 kb
Host smart-cf3c9c59-106d-4f81-abd0-1b7ac379b8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819765458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3819765458
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1541970767
Short name T64
Test name
Test status
Simulation time 27989397 ps
CPU time 1.21 seconds
Started Apr 04 03:35:07 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 217856 kb
Host smart-4a8eeee1-7037-4ae7-9b42-07959966f7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541970767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1541970767
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2105757920
Short name T557
Test name
Test status
Simulation time 79203848 ps
CPU time 1.08 seconds
Started Apr 04 03:35:04 PM PDT 24
Finished Apr 04 03:35:06 PM PDT 24
Peak memory 216344 kb
Host smart-1199d98c-3a17-42fb-9971-31c4f9325829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105757920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2105757920
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3954788885
Short name T781
Test name
Test status
Simulation time 71084985 ps
CPU time 1.37 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 217720 kb
Host smart-782fc10a-8144-47ca-8654-a44ead84dd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954788885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3954788885
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.443444295
Short name T261
Test name
Test status
Simulation time 75716420 ps
CPU time 1.26 seconds
Started Apr 04 03:32:41 PM PDT 24
Finished Apr 04 03:32:43 PM PDT 24
Peak memory 215252 kb
Host smart-ed00b95b-94fa-461f-9e9b-bb2e4b5c26e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443444295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.443444295
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1620018035
Short name T311
Test name
Test status
Simulation time 14105840 ps
CPU time 0.89 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 205736 kb
Host smart-173df398-f35c-4b9e-b4cc-399cf8e38dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620018035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1620018035
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2638479562
Short name T660
Test name
Test status
Simulation time 37725003 ps
CPU time 0.88 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:44 PM PDT 24
Peak memory 215244 kb
Host smart-9097dba4-9f6c-400c-aafd-db4fbeb25c33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638479562 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2638479562
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3833014785
Short name T194
Test name
Test status
Simulation time 100452945 ps
CPU time 1.05 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 216228 kb
Host smart-da20299d-f105-4bd8-ace9-0abb236da529
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833014785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3833014785
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3239233848
Short name T101
Test name
Test status
Simulation time 33059674 ps
CPU time 0.87 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:44 PM PDT 24
Peak memory 217344 kb
Host smart-f837a6d4-c3a2-4139-829f-7de0f158cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239233848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3239233848
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2214279618
Short name T652
Test name
Test status
Simulation time 51475009 ps
CPU time 1.32 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 217472 kb
Host smart-785daff3-b19e-4cfc-b416-fe050534880f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214279618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2214279618
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3874933562
Short name T651
Test name
Test status
Simulation time 34396711 ps
CPU time 1 seconds
Started Apr 04 03:32:41 PM PDT 24
Finished Apr 04 03:32:42 PM PDT 24
Peak memory 215064 kb
Host smart-5e986153-9cf9-4206-8bee-d2949cf6e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874933562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3874933562
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1436688405
Short name T346
Test name
Test status
Simulation time 24830848 ps
CPU time 0.9 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:44 PM PDT 24
Peak memory 215020 kb
Host smart-54eb6206-b4c0-4c53-be4b-d9ad21ce0500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436688405 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1436688405
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2705648801
Short name T212
Test name
Test status
Simulation time 2808710552 ps
CPU time 5.16 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:49 PM PDT 24
Peak memory 215024 kb
Host smart-5033850b-8a4c-4c1d-a990-8db4d470878b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705648801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2705648801
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.792579852
Short name T204
Test name
Test status
Simulation time 74949189277 ps
CPU time 475.27 seconds
Started Apr 04 03:32:41 PM PDT 24
Finished Apr 04 03:40:37 PM PDT 24
Peak memory 217440 kb
Host smart-7d43be4e-51b8-4a7e-b803-4a408d085bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792579852 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.792579852
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2238627924
Short name T685
Test name
Test status
Simulation time 86987396 ps
CPU time 1.15 seconds
Started Apr 04 03:35:07 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 217728 kb
Host smart-3dd4fb6d-956f-42df-85dc-b73c4aed942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238627924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2238627924
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.89031308
Short name T274
Test name
Test status
Simulation time 35653257 ps
CPU time 1.4 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:08 PM PDT 24
Peak memory 216412 kb
Host smart-3968d570-f8e6-4028-9d87-2ca09a27f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89031308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.89031308
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1990410820
Short name T245
Test name
Test status
Simulation time 32112467 ps
CPU time 1.28 seconds
Started Apr 04 03:35:03 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217280 kb
Host smart-86dc0c92-db1d-4f64-b29e-6241af4ab256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990410820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1990410820
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1872086203
Short name T612
Test name
Test status
Simulation time 321850474 ps
CPU time 3.45 seconds
Started Apr 04 03:35:08 PM PDT 24
Finished Apr 04 03:35:11 PM PDT 24
Peak memory 218996 kb
Host smart-f5f64e33-812d-4b03-b2e3-92a3cd714483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872086203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1872086203
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1968289634
Short name T266
Test name
Test status
Simulation time 53863876 ps
CPU time 1.17 seconds
Started Apr 04 03:35:08 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216168 kb
Host smart-888dee2b-d5e7-43c1-a2d9-13c54b064e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968289634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1968289634
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.730281764
Short name T725
Test name
Test status
Simulation time 45851207 ps
CPU time 1.31 seconds
Started Apr 04 03:35:07 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 219056 kb
Host smart-cf7fefce-625f-4794-851c-542a8300d3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730281764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.730281764
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1284409134
Short name T277
Test name
Test status
Simulation time 36475463 ps
CPU time 1.35 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 218572 kb
Host smart-c7d7f536-1a1f-461e-a956-c3e993e9461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284409134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1284409134
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3257122525
Short name T188
Test name
Test status
Simulation time 142286952 ps
CPU time 1.63 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:01 PM PDT 24
Peak memory 218384 kb
Host smart-2bd7ae66-0912-4ba6-9756-913a3c97e4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257122525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3257122525
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.993301870
Short name T635
Test name
Test status
Simulation time 100014726 ps
CPU time 1.24 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216044 kb
Host smart-b46bd847-5157-4bba-a27f-024f2626d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993301870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.993301870
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4286419713
Short name T246
Test name
Test status
Simulation time 40121122 ps
CPU time 1.15 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:03 PM PDT 24
Peak memory 216444 kb
Host smart-2a99de01-3297-4065-94c8-ab04f0d7e9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286419713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4286419713
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.924454382
Short name T693
Test name
Test status
Simulation time 42923416 ps
CPU time 1.23 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:48 PM PDT 24
Peak memory 215324 kb
Host smart-9cd801dc-77df-47ff-9c45-088ff3b4b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924454382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.924454382
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2011761570
Short name T669
Test name
Test status
Simulation time 14012351 ps
CPU time 0.87 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 206564 kb
Host smart-e9047316-a958-4e1a-9ca6-9b3d958cb42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011761570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2011761570
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1489831422
Short name T428
Test name
Test status
Simulation time 108757775 ps
CPU time 1.18 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 217288 kb
Host smart-e1a1db7f-f331-45d9-b512-d6cc13da9989
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489831422 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1489831422
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2324971319
Short name T38
Test name
Test status
Simulation time 65685143 ps
CPU time 0.91 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 230840 kb
Host smart-fa5cf0cd-5e8c-4146-9e1e-8e4a69aac0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324971319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2324971319
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3900419797
Short name T32
Test name
Test status
Simulation time 90787627 ps
CPU time 1.26 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 216360 kb
Host smart-0354bdd7-a370-4112-8fdb-e1f8a9165952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900419797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3900419797
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.197645108
Short name T128
Test name
Test status
Simulation time 25047264 ps
CPU time 0.93 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 215448 kb
Host smart-9ba2fdf2-756b-42d1-bf16-86852d121736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197645108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.197645108
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1685864819
Short name T460
Test name
Test status
Simulation time 82672014 ps
CPU time 0.92 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 214844 kb
Host smart-17d7e0ba-c65d-4394-b934-1ef47a6559ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685864819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1685864819
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4173215120
Short name T694
Test name
Test status
Simulation time 395638435 ps
CPU time 2.9 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 215020 kb
Host smart-85825258-ec3e-40b2-8953-6846d4a00ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173215120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4173215120
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2373132619
Short name T384
Test name
Test status
Simulation time 12558360658 ps
CPU time 282.95 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:37:29 PM PDT 24
Peak memory 218040 kb
Host smart-09acbbcb-ac1d-40a3-b269-e89b64bceaec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373132619 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2373132619
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3269244648
Short name T637
Test name
Test status
Simulation time 98361599 ps
CPU time 1.13 seconds
Started Apr 04 03:34:58 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 216284 kb
Host smart-1642f763-00ed-49ac-a207-f358c5b30d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269244648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3269244648
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1587630551
Short name T673
Test name
Test status
Simulation time 126639160 ps
CPU time 1.44 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216712 kb
Host smart-07a23038-4290-4b2c-b8ea-58556d8d2475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587630551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1587630551
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2521362108
Short name T713
Test name
Test status
Simulation time 297466166 ps
CPU time 2.56 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 216588 kb
Host smart-45f4d725-f086-4666-8d90-2c26c31c1b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521362108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2521362108
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1200509224
Short name T678
Test name
Test status
Simulation time 320761504 ps
CPU time 1.4 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217724 kb
Host smart-48279f8b-97be-43d2-84a5-4c786fefef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200509224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1200509224
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.139026504
Short name T312
Test name
Test status
Simulation time 102043104 ps
CPU time 1.62 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217496 kb
Host smart-7cc5bd7c-b393-4288-af2e-c6b3bd6bc483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139026504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.139026504
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.955228143
Short name T372
Test name
Test status
Simulation time 50510601 ps
CPU time 1.41 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:00 PM PDT 24
Peak memory 217844 kb
Host smart-d4725330-c39f-479c-8a09-a6b402657b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955228143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.955228143
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3153296332
Short name T9
Test name
Test status
Simulation time 87846228 ps
CPU time 2.98 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:06 PM PDT 24
Peak memory 217504 kb
Host smart-a8be4306-ee0e-4e22-bfa9-b7828bfc9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153296332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3153296332
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1805820695
Short name T180
Test name
Test status
Simulation time 66494189 ps
CPU time 1.05 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216332 kb
Host smart-dc76df09-d397-4978-94bf-2be37dad4143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805820695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1805820695
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3901257551
Short name T783
Test name
Test status
Simulation time 72636769 ps
CPU time 1.82 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 216632 kb
Host smart-88409784-a664-4b70-8b63-ddebbc522007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901257551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3901257551
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2339268693
Short name T580
Test name
Test status
Simulation time 134608130 ps
CPU time 1.31 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 215256 kb
Host smart-84320ceb-0ae2-4e9c-ae95-b544866483cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339268693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2339268693
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2033235209
Short name T313
Test name
Test status
Simulation time 35321882 ps
CPU time 0.97 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 206568 kb
Host smart-f0b4dca5-f46c-47c6-a517-7e7b23e675b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033235209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2033235209
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.38818563
Short name T170
Test name
Test status
Simulation time 144316695 ps
CPU time 0.97 seconds
Started Apr 04 03:32:50 PM PDT 24
Finished Apr 04 03:32:52 PM PDT 24
Peak memory 216180 kb
Host smart-d81eacae-a78a-4bb1-8ccc-96dfb9bb1fbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818563 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_dis
able_auto_req_mode.38818563
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1636365101
Short name T106
Test name
Test status
Simulation time 29318169 ps
CPU time 1.32 seconds
Started Apr 04 03:32:48 PM PDT 24
Finished Apr 04 03:32:50 PM PDT 24
Peak memory 218784 kb
Host smart-8862026c-46fb-4f80-a85b-6c9ed7ced29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636365101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1636365101
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1289978540
Short name T334
Test name
Test status
Simulation time 44808140 ps
CPU time 1.4 seconds
Started Apr 04 03:32:47 PM PDT 24
Finished Apr 04 03:32:49 PM PDT 24
Peak memory 218084 kb
Host smart-6fe177da-d74b-4fda-b9a6-5405a5b06010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289978540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1289978540
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2508868627
Short name T60
Test name
Test status
Simulation time 23702050 ps
CPU time 0.94 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 215060 kb
Host smart-cd0414ea-93bb-42ef-bc84-7b6ba3cf0d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508868627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2508868627
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.744414566
Short name T625
Test name
Test status
Simulation time 16094194 ps
CPU time 0.91 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 214948 kb
Host smart-439bb84f-f3b5-4285-a149-ef25c980114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744414566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.744414566
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.4095467296
Short name T498
Test name
Test status
Simulation time 127906015 ps
CPU time 1.9 seconds
Started Apr 04 03:32:47 PM PDT 24
Finished Apr 04 03:32:49 PM PDT 24
Peak memory 214956 kb
Host smart-003538c9-90b6-4195-ad74-e87ea43c0667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095467296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4095467296
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.146476365
Short name T199
Test name
Test status
Simulation time 35839727341 ps
CPU time 261.98 seconds
Started Apr 04 03:32:48 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 218468 kb
Host smart-19e01f88-9b14-4b83-9952-40610f099633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146476365 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.146476365
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.882009283
Short name T666
Test name
Test status
Simulation time 50598858 ps
CPU time 1.72 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217616 kb
Host smart-bea72395-c1f2-47d4-8fdd-596fed7652c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882009283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.882009283
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1001246355
Short name T763
Test name
Test status
Simulation time 38976989 ps
CPU time 1.36 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 216264 kb
Host smart-2b9bb66b-bebf-487e-bb0a-a85c75f2887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001246355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1001246355
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.150847295
Short name T252
Test name
Test status
Simulation time 304491463 ps
CPU time 3.86 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:07 PM PDT 24
Peak memory 219036 kb
Host smart-8a382432-4dd2-4d46-8963-5d96072048e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150847295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.150847295
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.4283694855
Short name T514
Test name
Test status
Simulation time 59002886 ps
CPU time 1.26 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216472 kb
Host smart-160b8102-c12f-4c5d-b163-9516cc6415a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283694855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.4283694855
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.496804719
Short name T457
Test name
Test status
Simulation time 29077096 ps
CPU time 1.02 seconds
Started Apr 04 03:35:00 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216292 kb
Host smart-7261f787-74f7-402f-9d7d-20dcbeccfc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496804719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.496804719
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.202163621
Short name T280
Test name
Test status
Simulation time 39603822 ps
CPU time 1.59 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 219080 kb
Host smart-0d4abd8c-7e59-4c83-93bb-d29f70c655cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202163621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.202163621
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.257926572
Short name T51
Test name
Test status
Simulation time 79482420 ps
CPU time 1.08 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216328 kb
Host smart-12e5ee7a-f97d-4e37-9c2b-8775a5f4b9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257926572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.257926572
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1852615227
Short name T344
Test name
Test status
Simulation time 54021381 ps
CPU time 1.38 seconds
Started Apr 04 03:35:03 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 217764 kb
Host smart-491d49cc-7143-413b-95ac-afbafcee77f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852615227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1852615227
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.517521152
Short name T449
Test name
Test status
Simulation time 43921607 ps
CPU time 1.48 seconds
Started Apr 04 03:34:59 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 215032 kb
Host smart-4a0de3fd-4dae-45d5-bd92-e35006d108e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517521152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.517521152
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3385898400
Short name T125
Test name
Test status
Simulation time 115831054 ps
CPU time 1.2 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:50 PM PDT 24
Peak memory 215256 kb
Host smart-11b694e2-7235-4197-8c7f-ea8a4facfb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385898400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3385898400
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.684931511
Short name T464
Test name
Test status
Simulation time 34137049 ps
CPU time 0.78 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 204988 kb
Host smart-d2aa90c5-ecc3-4dd9-9255-bdcc77584dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684931511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.684931511
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_err.3454251746
Short name T502
Test name
Test status
Simulation time 21074019 ps
CPU time 1.02 seconds
Started Apr 04 03:32:50 PM PDT 24
Finished Apr 04 03:32:52 PM PDT 24
Peak memory 217560 kb
Host smart-9ba71ae8-ec5f-41b9-b87d-c1e4129a7b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454251746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3454251746
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3514714388
Short name T357
Test name
Test status
Simulation time 57902930 ps
CPU time 1.24 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:50 PM PDT 24
Peak memory 217700 kb
Host smart-e87f72a6-4b71-43b0-9ad7-4fecd5424732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514714388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3514714388
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3916704772
Short name T466
Test name
Test status
Simulation time 34092415 ps
CPU time 1.07 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 224136 kb
Host smart-127deeee-c0d3-41bf-9acb-7145f13a6ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916704772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3916704772
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.735620122
Short name T773
Test name
Test status
Simulation time 23434689 ps
CPU time 0.92 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:51 PM PDT 24
Peak memory 214988 kb
Host smart-68fab0b4-0e90-4e7b-9d30-7465e7d751d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735620122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.735620122
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.592903322
Short name T579
Test name
Test status
Simulation time 43529243 ps
CPU time 1.05 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 205468 kb
Host smart-6cd0b12b-9a6a-49fb-8b1b-31e175dc2ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592903322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.592903322
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.662332242
Short name T782
Test name
Test status
Simulation time 260059069432 ps
CPU time 1480.71 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:57:24 PM PDT 24
Peak memory 223604 kb
Host smart-25e940c3-f5d0-4cab-b2e1-705f314f845b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662332242 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.662332242
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3463869133
Short name T433
Test name
Test status
Simulation time 53786089 ps
CPU time 1.4 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 217600 kb
Host smart-58107812-d132-4a57-87fb-fe86cec61f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463869133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3463869133
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.151209199
Short name T352
Test name
Test status
Simulation time 64462967 ps
CPU time 0.93 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:04 PM PDT 24
Peak memory 216320 kb
Host smart-6e0e6ea6-5663-479d-b196-54eea1f134af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151209199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.151209199
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2318100438
Short name T667
Test name
Test status
Simulation time 86273284 ps
CPU time 1.17 seconds
Started Apr 04 03:35:05 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 216416 kb
Host smart-b1a3960a-5df4-499d-91bc-8ca4d53cb812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318100438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2318100438
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1709442148
Short name T271
Test name
Test status
Simulation time 52418806 ps
CPU time 1.8 seconds
Started Apr 04 03:35:01 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 218796 kb
Host smart-ecff700d-639f-4f10-99c7-5e575df8c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709442148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1709442148
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.239062485
Short name T278
Test name
Test status
Simulation time 34027480 ps
CPU time 1.39 seconds
Started Apr 04 03:35:04 PM PDT 24
Finished Apr 04 03:35:07 PM PDT 24
Peak memory 217412 kb
Host smart-02024f20-6c29-4b14-bd89-ace7777bd4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239062485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.239062485
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4228422866
Short name T714
Test name
Test status
Simulation time 44644018 ps
CPU time 1.49 seconds
Started Apr 04 03:35:04 PM PDT 24
Finished Apr 04 03:35:06 PM PDT 24
Peak memory 217424 kb
Host smart-5c19de09-b966-4edf-9507-1946a9822ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228422866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4228422866
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.218027273
Short name T582
Test name
Test status
Simulation time 62098982 ps
CPU time 1.6 seconds
Started Apr 04 03:35:12 PM PDT 24
Finished Apr 04 03:35:14 PM PDT 24
Peak memory 218868 kb
Host smart-dd8e6d55-cc98-4760-a52a-b49852a1d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218027273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.218027273
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1633956860
Short name T790
Test name
Test status
Simulation time 46324428 ps
CPU time 1.76 seconds
Started Apr 04 03:35:06 PM PDT 24
Finished Apr 04 03:35:09 PM PDT 24
Peak memory 217528 kb
Host smart-e93f17bb-7b3c-4cba-bbe3-4bbf87c1f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633956860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1633956860
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.219646132
Short name T374
Test name
Test status
Simulation time 48621303 ps
CPU time 1.22 seconds
Started Apr 04 03:35:12 PM PDT 24
Finished Apr 04 03:35:13 PM PDT 24
Peak memory 216420 kb
Host smart-6f3ed0e6-f2d4-4821-8e49-a01fa00d8377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219646132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.219646132
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.4049270597
Short name T422
Test name
Test status
Simulation time 35219976 ps
CPU time 1.38 seconds
Started Apr 04 03:35:02 PM PDT 24
Finished Apr 04 03:35:05 PM PDT 24
Peak memory 216372 kb
Host smart-97ce89da-faf9-404c-87e3-c3cbc8a5ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049270597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4049270597
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4066862078
Short name T104
Test name
Test status
Simulation time 73943381 ps
CPU time 1.14 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:50 PM PDT 24
Peak memory 215216 kb
Host smart-69a52d9a-9dda-4881-a060-ce26e2476be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066862078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4066862078
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3265986263
Short name T305
Test name
Test status
Simulation time 42033371 ps
CPU time 0.84 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 206376 kb
Host smart-3c961636-1118-4ee1-8a9c-bc33c9c8a1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265986263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3265986263
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.967262741
Short name T791
Test name
Test status
Simulation time 20611568 ps
CPU time 0.84 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 215068 kb
Host smart-760599f4-61b6-4c5b-852f-c8b46ce97470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967262741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.967262741
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.1087154560
Short name T112
Test name
Test status
Simulation time 50586044 ps
CPU time 0.83 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:51 PM PDT 24
Peak memory 217452 kb
Host smart-37de10d1-4158-489e-b1f4-89273213e9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087154560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1087154560
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3377747452
Short name T309
Test name
Test status
Simulation time 47218825 ps
CPU time 1.81 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:48 PM PDT 24
Peak memory 217440 kb
Host smart-809f5618-7ba8-471b-8d57-5e7c3b57f33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377747452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3377747452
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2067267379
Short name T633
Test name
Test status
Simulation time 21108288 ps
CPU time 1.1 seconds
Started Apr 04 03:32:48 PM PDT 24
Finished Apr 04 03:32:49 PM PDT 24
Peak memory 215152 kb
Host smart-6bbb0249-d1bc-4f7d-9aa4-25f9188c5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067267379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2067267379
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.339510379
Short name T386
Test name
Test status
Simulation time 17076679 ps
CPU time 1 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 215012 kb
Host smart-bcbbc208-849e-47bf-b8d6-1d20d4ed5abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339510379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.339510379
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3254331208
Short name T469
Test name
Test status
Simulation time 556962171 ps
CPU time 3.61 seconds
Started Apr 04 03:32:50 PM PDT 24
Finished Apr 04 03:32:54 PM PDT 24
Peak memory 216144 kb
Host smart-af524c4f-4733-4429-812c-f91db23f625a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254331208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3254331208
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3556251594
Short name T202
Test name
Test status
Simulation time 44425307843 ps
CPU time 948.39 seconds
Started Apr 04 03:32:48 PM PDT 24
Finished Apr 04 03:48:37 PM PDT 24
Peak memory 218120 kb
Host smart-390d4745-a979-4338-9dff-bbdb77ebf7a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556251594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3556251594
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3250480018
Short name T286
Test name
Test status
Simulation time 35025602 ps
CPU time 1.42 seconds
Started Apr 04 03:35:12 PM PDT 24
Finished Apr 04 03:35:13 PM PDT 24
Peak memory 216444 kb
Host smart-0007f53d-cb1b-418d-98c2-251f36b61f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250480018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3250480018
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.584121614
Short name T752
Test name
Test status
Simulation time 49186033 ps
CPU time 1.13 seconds
Started Apr 04 03:35:14 PM PDT 24
Finished Apr 04 03:35:16 PM PDT 24
Peak memory 216332 kb
Host smart-a24a3086-7224-4e2a-b358-4e4a48aa7cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584121614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.584121614
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3160357877
Short name T564
Test name
Test status
Simulation time 39905355 ps
CPU time 1.37 seconds
Started Apr 04 03:35:18 PM PDT 24
Finished Apr 04 03:35:21 PM PDT 24
Peak memory 215020 kb
Host smart-4b518f3e-8009-44b3-b19d-cab0b68dace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160357877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3160357877
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1919090622
Short name T281
Test name
Test status
Simulation time 49605040 ps
CPU time 1.35 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 218496 kb
Host smart-46446891-5db6-4702-86a4-2a57a83ed256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919090622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1919090622
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.171316688
Short name T183
Test name
Test status
Simulation time 168454033 ps
CPU time 1.82 seconds
Started Apr 04 03:35:14 PM PDT 24
Finished Apr 04 03:35:16 PM PDT 24
Peak memory 217960 kb
Host smart-e0f5d2eb-ac78-4014-87aa-9d31ccc94fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171316688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.171316688
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.665704189
Short name T576
Test name
Test status
Simulation time 35283141 ps
CPU time 1.39 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 217688 kb
Host smart-524ecd09-190c-40d0-adde-3b099fa0a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665704189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.665704189
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2624019843
Short name T686
Test name
Test status
Simulation time 56717656 ps
CPU time 2.08 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 219368 kb
Host smart-668159af-680b-478a-9870-71288aad76b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624019843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2624019843
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2334730557
Short name T497
Test name
Test status
Simulation time 31512780 ps
CPU time 1.48 seconds
Started Apr 04 03:35:13 PM PDT 24
Finished Apr 04 03:35:14 PM PDT 24
Peak memory 217544 kb
Host smart-40d5d3ef-b6f7-4106-9b5e-1c2db8e62d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334730557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2334730557
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3370075841
Short name T653
Test name
Test status
Simulation time 189099439 ps
CPU time 1.02 seconds
Started Apr 04 03:35:14 PM PDT 24
Finished Apr 04 03:35:16 PM PDT 24
Peak memory 216300 kb
Host smart-9317a3c5-9c16-42d8-aff3-2b4f990ce563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370075841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3370075841
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3719302693
Short name T435
Test name
Test status
Simulation time 32508574 ps
CPU time 1.06 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 218696 kb
Host smart-86b6e633-eee5-44fb-8291-b4d2c8931950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719302693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3719302693
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2073632623
Short name T586
Test name
Test status
Simulation time 40566313 ps
CPU time 1.13 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 215252 kb
Host smart-98e2c15f-7216-4388-81d2-4949e79daaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073632623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2073632623
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1011843486
Short name T370
Test name
Test status
Simulation time 18753093 ps
CPU time 0.99 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 206620 kb
Host smart-736c0285-4235-4f62-808a-ff62ca8451ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011843486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1011843486
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4164866899
Short name T549
Test name
Test status
Simulation time 12040144 ps
CPU time 0.88 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 215468 kb
Host smart-8ff4a154-7b4a-4e31-9183-42133d1998b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164866899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4164866899
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.634481070
Short name T551
Test name
Test status
Simulation time 30060908 ps
CPU time 1.14 seconds
Started Apr 04 03:32:46 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 217476 kb
Host smart-251e4949-b8b3-41c6-a5b1-ab3a23fb1422
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634481070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.634481070
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.714734
Short name T720
Test name
Test status
Simulation time 24722759 ps
CPU time 1.16 seconds
Started Apr 04 03:32:42 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 217776 kb
Host smart-cf05f28b-4447-43d0-8282-e7d548670f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.714734
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2202487595
Short name T632
Test name
Test status
Simulation time 60811440 ps
CPU time 1.02 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 216300 kb
Host smart-8eda16d6-4b72-429f-aeb1-f06dd82aa83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202487595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2202487595
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.505978307
Short name T476
Test name
Test status
Simulation time 25685754 ps
CPU time 1.07 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 223832 kb
Host smart-9f4ed522-d373-4bae-baa1-f1cb73f138e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505978307 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.505978307
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3259643003
Short name T395
Test name
Test status
Simulation time 69307265 ps
CPU time 0.9 seconds
Started Apr 04 03:32:44 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 215024 kb
Host smart-4c34bdcb-d380-4b88-99c0-0b009f383a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259643003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3259643003
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3169367164
Short name T385
Test name
Test status
Simulation time 1701511842 ps
CPU time 4.87 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:48 PM PDT 24
Peak memory 214956 kb
Host smart-8c527401-e501-4e7c-9f1c-2389cbc79266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169367164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3169367164
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2489423260
Short name T23
Test name
Test status
Simulation time 67109737963 ps
CPU time 610.29 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:42:54 PM PDT 24
Peak memory 218136 kb
Host smart-a0a05ab6-dce7-4c47-83fa-4caad28ad0e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489423260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2489423260
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3458353522
Short name T821
Test name
Test status
Simulation time 163827493 ps
CPU time 1.33 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 218904 kb
Host smart-972ca0bf-e3bf-48b2-8b25-f946080e3c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458353522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3458353522
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3186505984
Short name T668
Test name
Test status
Simulation time 51809942 ps
CPU time 2.02 seconds
Started Apr 04 03:35:13 PM PDT 24
Finished Apr 04 03:35:15 PM PDT 24
Peak memory 219172 kb
Host smart-e4231953-d83c-4899-bfcb-bf4eceebd84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186505984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3186505984
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2046479311
Short name T513
Test name
Test status
Simulation time 31893682 ps
CPU time 1.24 seconds
Started Apr 04 03:35:14 PM PDT 24
Finished Apr 04 03:35:15 PM PDT 24
Peak memory 217312 kb
Host smart-cdf60027-2fb3-46e2-a9b6-0f0dc7c5364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046479311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2046479311
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2226160372
Short name T399
Test name
Test status
Simulation time 69872066 ps
CPU time 1.04 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 216208 kb
Host smart-4a039c5c-fe7e-452d-b204-f902974d732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226160372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2226160372
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1171099401
Short name T745
Test name
Test status
Simulation time 114686944 ps
CPU time 1.61 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 217976 kb
Host smart-ff446a40-327c-493d-b052-2d83174be6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171099401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1171099401
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2923719954
Short name T462
Test name
Test status
Simulation time 76844144 ps
CPU time 1.24 seconds
Started Apr 04 03:35:19 PM PDT 24
Finished Apr 04 03:35:21 PM PDT 24
Peak memory 217828 kb
Host smart-326f25b6-dfe0-400f-a378-0e4b03f9ee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923719954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2923719954
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2765062610
Short name T486
Test name
Test status
Simulation time 247038498 ps
CPU time 1.13 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 216352 kb
Host smart-98fbfa73-18fd-479e-b2b4-d9d400b700aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765062610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2765062610
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4088205848
Short name T392
Test name
Test status
Simulation time 26492297 ps
CPU time 1.06 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 216332 kb
Host smart-3a05b4c5-4c0a-41f9-a9ac-18d27c097660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088205848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4088205848
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1269023107
Short name T703
Test name
Test status
Simulation time 36654116 ps
CPU time 1.33 seconds
Started Apr 04 03:35:15 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 216324 kb
Host smart-a118d935-c537-44ec-970b-72fba0a81b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269023107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1269023107
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.846064794
Short name T425
Test name
Test status
Simulation time 69545059 ps
CPU time 1.34 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 217636 kb
Host smart-ddcf961b-be89-42f0-b059-6500266ca48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846064794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.846064794
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.493108541
Short name T646
Test name
Test status
Simulation time 39252240 ps
CPU time 1.15 seconds
Started Apr 04 03:32:47 PM PDT 24
Finished Apr 04 03:32:48 PM PDT 24
Peak memory 215208 kb
Host smart-dfa00ea4-2807-4878-9090-32c22f43c12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493108541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.493108541
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3399515030
Short name T320
Test name
Test status
Simulation time 66541114 ps
CPU time 0.97 seconds
Started Apr 04 03:32:48 PM PDT 24
Finished Apr 04 03:32:49 PM PDT 24
Peak memory 205832 kb
Host smart-10ff0837-4b45-404b-b474-8eacc08363e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399515030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3399515030
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1350496511
Short name T722
Test name
Test status
Simulation time 38382033 ps
CPU time 0.81 seconds
Started Apr 04 03:32:47 PM PDT 24
Finished Apr 04 03:32:48 PM PDT 24
Peak memory 215004 kb
Host smart-168e977e-fac0-451e-8a78-a40cfaa49d17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350496511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1350496511
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2975326370
Short name T379
Test name
Test status
Simulation time 57966428 ps
CPU time 1.19 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:47 PM PDT 24
Peak memory 217200 kb
Host smart-5003a5cb-ca55-427d-857c-6e0e18fa1db5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975326370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2975326370
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.609667354
Short name T588
Test name
Test status
Simulation time 23581230 ps
CPU time 1.06 seconds
Started Apr 04 03:32:48 PM PDT 24
Finished Apr 04 03:32:49 PM PDT 24
Peak memory 222796 kb
Host smart-4c77ab85-d342-46a6-8227-c261adc698fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609667354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.609667354
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.583057019
Short name T636
Test name
Test status
Simulation time 81416809 ps
CPU time 0.89 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 216388 kb
Host smart-016899d2-752c-449f-832e-cba527635670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583057019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.583057019
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2439482125
Short name T14
Test name
Test status
Simulation time 21076605 ps
CPU time 1.19 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 223780 kb
Host smart-c43ff539-eaef-4c19-9552-db9f440a44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439482125 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2439482125
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1067499915
Short name T337
Test name
Test status
Simulation time 65157431 ps
CPU time 0.95 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:32:46 PM PDT 24
Peak memory 215004 kb
Host smart-c9fd4b22-6519-4b8e-bfbe-ea7d7275ac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067499915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1067499915
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1194948603
Short name T610
Test name
Test status
Simulation time 242164351 ps
CPU time 1.71 seconds
Started Apr 04 03:32:43 PM PDT 24
Finished Apr 04 03:32:45 PM PDT 24
Peak memory 216292 kb
Host smart-170bb60a-caeb-4f1c-8368-1c5d4545391c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194948603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1194948603
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3233665630
Short name T196
Test name
Test status
Simulation time 67205996794 ps
CPU time 915.12 seconds
Started Apr 04 03:32:45 PM PDT 24
Finished Apr 04 03:48:00 PM PDT 24
Peak memory 220740 kb
Host smart-acc0288d-3367-4f97-93cd-9aeab638e622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233665630 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3233665630
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1500802941
Short name T402
Test name
Test status
Simulation time 36489650 ps
CPU time 1.29 seconds
Started Apr 04 03:35:18 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 216292 kb
Host smart-2a3bd0c4-85af-429d-814d-193efa5ceaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500802941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1500802941
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2445804822
Short name T436
Test name
Test status
Simulation time 35126926 ps
CPU time 1.33 seconds
Started Apr 04 03:35:23 PM PDT 24
Finished Apr 04 03:35:25 PM PDT 24
Peak memory 217504 kb
Host smart-22f7040b-51d5-436f-97e7-818501cfeb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445804822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2445804822
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1650413411
Short name T501
Test name
Test status
Simulation time 54603664 ps
CPU time 2.13 seconds
Started Apr 04 03:35:19 PM PDT 24
Finished Apr 04 03:35:21 PM PDT 24
Peak memory 217520 kb
Host smart-c7dbf35e-0812-490e-ae74-c2909657831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650413411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1650413411
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1418543645
Short name T326
Test name
Test status
Simulation time 70013897 ps
CPU time 1.34 seconds
Started Apr 04 03:35:23 PM PDT 24
Finished Apr 04 03:35:24 PM PDT 24
Peak memory 217396 kb
Host smart-ecbebd38-da3f-45eb-9787-6b38958de2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418543645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1418543645
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3561794380
Short name T572
Test name
Test status
Simulation time 98816193 ps
CPU time 1.35 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 218012 kb
Host smart-4dfdf67b-4024-4ed4-926d-9abfaed9ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561794380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3561794380
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1951067895
Short name T440
Test name
Test status
Simulation time 58956976 ps
CPU time 2.33 seconds
Started Apr 04 03:35:24 PM PDT 24
Finished Apr 04 03:35:27 PM PDT 24
Peak memory 219232 kb
Host smart-c1a378b7-8481-43ff-9d15-8ed32863482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951067895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1951067895
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3743565507
Short name T812
Test name
Test status
Simulation time 88677476 ps
CPU time 1.2 seconds
Started Apr 04 03:35:18 PM PDT 24
Finished Apr 04 03:35:21 PM PDT 24
Peak memory 216212 kb
Host smart-de631c6e-0de4-4422-884e-aba1ee23ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743565507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3743565507
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1528962565
Short name T508
Test name
Test status
Simulation time 70211328 ps
CPU time 1.05 seconds
Started Apr 04 03:35:11 PM PDT 24
Finished Apr 04 03:35:13 PM PDT 24
Peak memory 215020 kb
Host smart-57e536ae-09ec-48f4-9f21-780282a51ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528962565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1528962565
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3450704547
Short name T605
Test name
Test status
Simulation time 144598070 ps
CPU time 3.3 seconds
Started Apr 04 03:35:24 PM PDT 24
Finished Apr 04 03:35:28 PM PDT 24
Peak memory 219052 kb
Host smart-7fb080e0-b8eb-4bc3-a257-775d8fde4119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450704547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3450704547
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1331125022
Short name T560
Test name
Test status
Simulation time 73787264 ps
CPU time 1.08 seconds
Started Apr 04 03:35:23 PM PDT 24
Finished Apr 04 03:35:25 PM PDT 24
Peak memory 216512 kb
Host smart-1f0fc873-1740-42ae-a570-c4e11ed35339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331125022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1331125022
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2306050919
Short name T802
Test name
Test status
Simulation time 26191747 ps
CPU time 1.25 seconds
Started Apr 04 03:32:58 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 215052 kb
Host smart-7a349ca2-f4d0-487b-a949-9980ec8fabde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306050919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2306050919
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2214973417
Short name T815
Test name
Test status
Simulation time 46123537 ps
CPU time 0.91 seconds
Started Apr 04 03:32:58 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 205544 kb
Host smart-a7c59151-901c-4dc9-8cb6-b1afbfda1da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214973417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2214973417
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1023300312
Short name T747
Test name
Test status
Simulation time 119569949 ps
CPU time 0.85 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 215332 kb
Host smart-be7c344d-748e-4c7c-a86a-681447ea27ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023300312 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1023300312
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3383693816
Short name T641
Test name
Test status
Simulation time 26574415 ps
CPU time 0.91 seconds
Started Apr 04 03:32:56 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 217700 kb
Host smart-3e8bbdc8-d94a-4c86-8a9e-62aa7599d6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383693816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3383693816
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.700300415
Short name T527
Test name
Test status
Simulation time 87340013 ps
CPU time 1.49 seconds
Started Apr 04 03:32:53 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 217456 kb
Host smart-6d6ba11a-fb3f-43a5-a8fa-ec6ae79def17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700300415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.700300415
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.837818674
Short name T15
Test name
Test status
Simulation time 42793317 ps
CPU time 0.95 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 223596 kb
Host smart-4f66442a-575c-4bdf-b4bb-13967ee51ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837818674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.837818674
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2290345193
Short name T644
Test name
Test status
Simulation time 16352418 ps
CPU time 0.97 seconds
Started Apr 04 03:32:49 PM PDT 24
Finished Apr 04 03:32:51 PM PDT 24
Peak memory 215004 kb
Host smart-5516f765-068d-4927-954d-d692bb6d8d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290345193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2290345193
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3454998345
Short name T771
Test name
Test status
Simulation time 283707539 ps
CPU time 5.46 seconds
Started Apr 04 03:32:53 PM PDT 24
Finished Apr 04 03:33:02 PM PDT 24
Peak memory 214976 kb
Host smart-18a7f317-d859-4ef0-9812-1f924ebfa2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454998345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3454998345
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1216915623
Short name T817
Test name
Test status
Simulation time 29372566926 ps
CPU time 382.36 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:39:19 PM PDT 24
Peak memory 217396 kb
Host smart-5a4ba7a4-b819-4e05-8490-fe3399014f7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216915623 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1216915623
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.480652947
Short name T547
Test name
Test status
Simulation time 37079161 ps
CPU time 1.47 seconds
Started Apr 04 03:35:24 PM PDT 24
Finished Apr 04 03:35:26 PM PDT 24
Peak memory 217604 kb
Host smart-cb4e75fb-436a-4a67-a574-8eb5d1cf2fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480652947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.480652947
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.388166978
Short name T251
Test name
Test status
Simulation time 70723077 ps
CPU time 2.4 seconds
Started Apr 04 03:35:12 PM PDT 24
Finished Apr 04 03:35:14 PM PDT 24
Peak memory 218976 kb
Host smart-b2bea874-694c-4a74-97da-4c3678545ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388166978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.388166978
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3688234427
Short name T832
Test name
Test status
Simulation time 68484041 ps
CPU time 1.14 seconds
Started Apr 04 03:35:18 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 218824 kb
Host smart-b0632159-0d33-4ff5-9695-80e94b9389ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688234427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3688234427
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1064193326
Short name T510
Test name
Test status
Simulation time 207202562 ps
CPU time 1.08 seconds
Started Apr 04 03:35:23 PM PDT 24
Finished Apr 04 03:35:24 PM PDT 24
Peak memory 216340 kb
Host smart-16dfa893-eb6a-4cf4-a670-9a7722e64992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064193326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1064193326
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1043624176
Short name T630
Test name
Test status
Simulation time 60882993 ps
CPU time 1.31 seconds
Started Apr 04 03:35:19 PM PDT 24
Finished Apr 04 03:35:21 PM PDT 24
Peak memory 216324 kb
Host smart-47512ddf-37b1-4522-82c1-0963f8f6622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043624176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1043624176
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.802974267
Short name T546
Test name
Test status
Simulation time 102719089 ps
CPU time 1.21 seconds
Started Apr 04 03:35:22 PM PDT 24
Finished Apr 04 03:35:23 PM PDT 24
Peak memory 218016 kb
Host smart-b6ae9be1-21f6-47a8-b163-16520744171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802974267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.802974267
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3803147977
Short name T268
Test name
Test status
Simulation time 38876282 ps
CPU time 1.63 seconds
Started Apr 04 03:35:23 PM PDT 24
Finished Apr 04 03:35:25 PM PDT 24
Peak memory 217332 kb
Host smart-727072ba-1db2-4530-97d1-e2b5055168fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803147977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3803147977
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1696742982
Short name T323
Test name
Test status
Simulation time 97635858 ps
CPU time 1.46 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 217724 kb
Host smart-009d9c8f-9491-44d3-ba5e-52642225f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696742982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1696742982
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.295455244
Short name T445
Test name
Test status
Simulation time 179305942 ps
CPU time 1.3 seconds
Started Apr 04 03:35:18 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 218992 kb
Host smart-77ac0686-475c-4d57-b6dc-4f88649d1f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295455244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.295455244
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.591990080
Short name T719
Test name
Test status
Simulation time 59181674 ps
CPU time 1.25 seconds
Started Apr 04 03:35:17 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 217476 kb
Host smart-4735582f-d9ce-44da-9f23-2a9e0fb1db0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591990080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.591990080
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.4127573867
Short name T779
Test name
Test status
Simulation time 35790679 ps
CPU time 1.09 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 215260 kb
Host smart-5d03d851-36f8-4a9f-82c5-26cdb2257006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127573867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.4127573867
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.687315719
Short name T468
Test name
Test status
Simulation time 31769901 ps
CPU time 0.93 seconds
Started Apr 04 03:32:55 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 206224 kb
Host smart-9a785d7c-958b-435f-b6be-b232cc6c6407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687315719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.687315719
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_err.3394800649
Short name T415
Test name
Test status
Simulation time 72137286 ps
CPU time 1.14 seconds
Started Apr 04 03:32:54 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 233244 kb
Host smart-5f66ff41-6df1-444e-b183-78e73dd632c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394800649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3394800649
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.414911144
Short name T359
Test name
Test status
Simulation time 24879485 ps
CPU time 1.26 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 217484 kb
Host smart-4dad3fce-5605-49ef-a044-a5c29adb7cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414911144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.414911144
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1229853761
Short name T789
Test name
Test status
Simulation time 22138811 ps
CPU time 1.05 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 215176 kb
Host smart-74037fd5-76cc-4a92-8757-efcd0ba4b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229853761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1229853761
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3729814651
Short name T541
Test name
Test status
Simulation time 32484734 ps
CPU time 0.99 seconds
Started Apr 04 03:32:55 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 214944 kb
Host smart-679a369a-aeec-4748-a04b-d715a4007d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729814651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3729814651
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1512444088
Short name T732
Test name
Test status
Simulation time 438269034 ps
CPU time 2.79 seconds
Started Apr 04 03:32:59 PM PDT 24
Finished Apr 04 03:33:02 PM PDT 24
Peak memory 215020 kb
Host smart-dd9f0bda-a82a-481d-88b5-d1e1aa5926ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512444088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1512444088
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2943530437
Short name T48
Test name
Test status
Simulation time 52514326057 ps
CPU time 681.85 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:44:19 PM PDT 24
Peak memory 218924 kb
Host smart-0e0ddf87-338f-4976-baf0-65bf5c87f8d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943530437 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2943530437
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3869880578
Short name T559
Test name
Test status
Simulation time 37443214 ps
CPU time 1.33 seconds
Started Apr 04 03:35:16 PM PDT 24
Finished Apr 04 03:35:18 PM PDT 24
Peak memory 216516 kb
Host smart-3d076ee3-ee4f-4356-8347-178a0fbf5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869880578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3869880578
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3555675660
Short name T46
Test name
Test status
Simulation time 60087279 ps
CPU time 1.46 seconds
Started Apr 04 03:35:17 PM PDT 24
Finished Apr 04 03:35:19 PM PDT 24
Peak memory 217544 kb
Host smart-53f5138f-3579-466b-b4d6-2e70903470ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555675660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3555675660
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.4268206884
Short name T408
Test name
Test status
Simulation time 42294473 ps
CPU time 1.71 seconds
Started Apr 04 03:35:20 PM PDT 24
Finished Apr 04 03:35:22 PM PDT 24
Peak memory 217640 kb
Host smart-e84382d8-2b71-47c3-871f-9b0e8f9cfa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268206884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.4268206884
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1581654841
Short name T427
Test name
Test status
Simulation time 71958157 ps
CPU time 1.77 seconds
Started Apr 04 03:35:22 PM PDT 24
Finished Apr 04 03:35:24 PM PDT 24
Peak memory 217684 kb
Host smart-34fe4589-ac52-43b9-9429-b51a7f403723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581654841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1581654841
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1199849193
Short name T10
Test name
Test status
Simulation time 70295844 ps
CPU time 1.47 seconds
Started Apr 04 03:35:22 PM PDT 24
Finished Apr 04 03:35:24 PM PDT 24
Peak memory 218636 kb
Host smart-6a90accc-d8f1-4a7d-a7b3-cdcbeb8fe2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199849193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1199849193
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3950891932
Short name T308
Test name
Test status
Simulation time 33963193 ps
CPU time 1.36 seconds
Started Apr 04 03:35:25 PM PDT 24
Finished Apr 04 03:35:28 PM PDT 24
Peak memory 217728 kb
Host smart-4ee8cdf4-0868-431e-964f-e5eb7a73e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950891932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3950891932
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1887217742
Short name T608
Test name
Test status
Simulation time 43001946 ps
CPU time 1.23 seconds
Started Apr 04 03:35:21 PM PDT 24
Finished Apr 04 03:35:23 PM PDT 24
Peak memory 216160 kb
Host smart-ea0d280f-e09f-4c13-bf72-d79d529f1e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887217742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1887217742
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4283230504
Short name T483
Test name
Test status
Simulation time 42599658 ps
CPU time 1.51 seconds
Started Apr 04 03:35:22 PM PDT 24
Finished Apr 04 03:35:24 PM PDT 24
Peak memory 217648 kb
Host smart-d83bcb00-028e-4983-aafb-e171fe01d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283230504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4283230504
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1074583935
Short name T565
Test name
Test status
Simulation time 76071650 ps
CPU time 2.09 seconds
Started Apr 04 03:35:21 PM PDT 24
Finished Apr 04 03:35:24 PM PDT 24
Peak memory 217664 kb
Host smart-7047cc5f-c99c-45db-806c-88167a9fa283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074583935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1074583935
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3155349741
Short name T151
Test name
Test status
Simulation time 185482779 ps
CPU time 1.35 seconds
Started Apr 04 03:31:33 PM PDT 24
Finished Apr 04 03:31:34 PM PDT 24
Peak memory 215260 kb
Host smart-da03be8c-ab76-4b27-9281-e6fb32890426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155349741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3155349741
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.772029756
Short name T770
Test name
Test status
Simulation time 46479413 ps
CPU time 0.87 seconds
Started Apr 04 03:31:33 PM PDT 24
Finished Apr 04 03:31:34 PM PDT 24
Peak memory 205680 kb
Host smart-c91f1455-3da5-4dad-9b3e-1e19a0a4d7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772029756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.772029756
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1202813010
Short name T814
Test name
Test status
Simulation time 28352398 ps
CPU time 0.79 seconds
Started Apr 04 03:31:31 PM PDT 24
Finished Apr 04 03:31:31 PM PDT 24
Peak memory 215480 kb
Host smart-ecbf9653-dff2-469b-9a5e-24ed751e7dca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202813010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1202813010
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1460803062
Short name T683
Test name
Test status
Simulation time 44760341 ps
CPU time 1.07 seconds
Started Apr 04 03:31:35 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 216072 kb
Host smart-2e5ce8ce-4bca-44f8-92f5-7c37c90ea612
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460803062 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1460803062
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1052298792
Short name T824
Test name
Test status
Simulation time 81393121 ps
CPU time 1.2 seconds
Started Apr 04 03:31:33 PM PDT 24
Finished Apr 04 03:31:35 PM PDT 24
Peak memory 233256 kb
Host smart-6484c2ba-aa89-427b-b20e-8a28f23788ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052298792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1052298792
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1558592720
Short name T342
Test name
Test status
Simulation time 172489681 ps
CPU time 1.47 seconds
Started Apr 04 03:31:20 PM PDT 24
Finished Apr 04 03:31:22 PM PDT 24
Peak memory 217724 kb
Host smart-3bfc865a-03b4-47df-954e-18f89b778849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558592720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1558592720
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3870270136
Short name T137
Test name
Test status
Simulation time 60315987 ps
CPU time 0.92 seconds
Started Apr 04 03:31:31 PM PDT 24
Finished Apr 04 03:31:32 PM PDT 24
Peak memory 215204 kb
Host smart-6655f61d-3c17-4d4c-9fac-6e6fcd2bea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870270136 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3870270136
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.104202634
Short name T49
Test name
Test status
Simulation time 864478915 ps
CPU time 6.32 seconds
Started Apr 04 03:31:31 PM PDT 24
Finished Apr 04 03:31:38 PM PDT 24
Peak memory 236552 kb
Host smart-57f71b1c-3ce4-4ac3-9f93-bb94e71e6b96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104202634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.104202634
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2491673209
Short name T322
Test name
Test status
Simulation time 40304994 ps
CPU time 0.9 seconds
Started Apr 04 03:31:19 PM PDT 24
Finished Apr 04 03:31:21 PM PDT 24
Peak memory 214968 kb
Host smart-e4c4d5b7-f28b-494d-8476-c2e7e3d7705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491673209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2491673209
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.952673033
Short name T304
Test name
Test status
Simulation time 321683452 ps
CPU time 6.18 seconds
Started Apr 04 03:31:18 PM PDT 24
Finished Apr 04 03:31:24 PM PDT 24
Peak memory 219140 kb
Host smart-2b5476f5-67d2-4c1d-b256-5dd8dc5d7a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952673033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.952673033
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.122397283
Short name T159
Test name
Test status
Simulation time 37861874824 ps
CPU time 981.76 seconds
Started Apr 04 03:31:19 PM PDT 24
Finished Apr 04 03:47:41 PM PDT 24
Peak memory 219504 kb
Host smart-cc979f95-878b-46f7-9c29-7aa90a39138f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122397283 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.122397283
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2890091702
Short name T186
Test name
Test status
Simulation time 76842502 ps
CPU time 1.12 seconds
Started Apr 04 03:32:56 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 215256 kb
Host smart-b061deed-a0af-4b1c-9169-e7eadc90f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890091702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2890091702
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3537249198
Short name T622
Test name
Test status
Simulation time 49197219 ps
CPU time 0.9 seconds
Started Apr 04 03:32:55 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 206312 kb
Host smart-a748d224-a36f-4b78-bb2c-c786023bfdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537249198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3537249198
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3679515587
Short name T52
Test name
Test status
Simulation time 57581731 ps
CPU time 0.84 seconds
Started Apr 04 03:32:59 PM PDT 24
Finished Apr 04 03:33:00 PM PDT 24
Peak memory 215480 kb
Host smart-5152d809-ca5b-4e10-b3f1-1ddf4b717a86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679515587 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3679515587
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2763875486
Short name T68
Test name
Test status
Simulation time 117901952 ps
CPU time 1.25 seconds
Started Apr 04 03:32:55 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 216096 kb
Host smart-e6c6b01a-9c68-415b-a3e1-6c38dda831c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763875486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2763875486
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.767095470
Short name T89
Test name
Test status
Simulation time 56609432 ps
CPU time 1.04 seconds
Started Apr 04 03:32:58 PM PDT 24
Finished Apr 04 03:33:00 PM PDT 24
Peak memory 216248 kb
Host smart-0a4fb5dd-a37b-47c0-8353-65fe18ac6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767095470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.767095470
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.749339829
Short name T601
Test name
Test status
Simulation time 46312830 ps
CPU time 1.73 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 217436 kb
Host smart-489ba5ca-5724-4099-8608-31571e5b5265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749339829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.749339829
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.630936954
Short name T795
Test name
Test status
Simulation time 38342389 ps
CPU time 0.88 seconds
Started Apr 04 03:32:56 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 215136 kb
Host smart-5c35e566-b6bb-477a-80d0-53de252ce4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630936954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.630936954
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2062815918
Short name T671
Test name
Test status
Simulation time 18557857 ps
CPU time 1.02 seconds
Started Apr 04 03:32:54 PM PDT 24
Finished Apr 04 03:32:58 PM PDT 24
Peak memory 215000 kb
Host smart-68f6f4e5-6c8a-4bbe-9523-7c815e3c6652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062815918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2062815918
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4205922117
Short name T160
Test name
Test status
Simulation time 129198214 ps
CPU time 1.96 seconds
Started Apr 04 03:32:57 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 216112 kb
Host smart-168b923e-ba7f-4cbb-9932-f404d16bb1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205922117 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4205922117
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3745394783
Short name T490
Test name
Test status
Simulation time 92589466323 ps
CPU time 553.12 seconds
Started Apr 04 03:32:54 PM PDT 24
Finished Apr 04 03:42:10 PM PDT 24
Peak memory 218472 kb
Host smart-9d446911-bf11-4e7c-8ff9-6f79746e13a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745394783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3745394783
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.900351707
Short name T536
Test name
Test status
Simulation time 43056825 ps
CPU time 1.19 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:33:12 PM PDT 24
Peak memory 215260 kb
Host smart-421e2a12-ddb5-48cf-874a-0a20a732ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900351707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.900351707
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1695399499
Short name T665
Test name
Test status
Simulation time 27982678 ps
CPU time 0.91 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:10 PM PDT 24
Peak memory 206316 kb
Host smart-4edc50b2-b2c2-452d-aca2-01af9277e262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695399499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1695399499
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3511751608
Short name T481
Test name
Test status
Simulation time 18973595 ps
CPU time 0.88 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:10 PM PDT 24
Peak memory 215032 kb
Host smart-0ec874e4-530f-4890-a5cd-1f834b0bdfa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511751608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3511751608
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3062422656
Short name T83
Test name
Test status
Simulation time 29444708 ps
CPU time 1.03 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:10 PM PDT 24
Peak memory 217416 kb
Host smart-6aba63fc-1b94-447b-8350-30f9352cd027
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062422656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3062422656
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2028358649
Short name T66
Test name
Test status
Simulation time 20765248 ps
CPU time 1.27 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:33:12 PM PDT 24
Peak memory 229504 kb
Host smart-04429f6e-9e85-468b-9ff3-a81bb1abb2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028358649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2028358649
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3391545764
Short name T30
Test name
Test status
Simulation time 56158956 ps
CPU time 1.61 seconds
Started Apr 04 03:32:56 PM PDT 24
Finished Apr 04 03:32:59 PM PDT 24
Peak memory 217640 kb
Host smart-4ae2de9d-905f-4815-80a5-21fe2e9d7628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391545764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3391545764
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3225425802
Short name T133
Test name
Test status
Simulation time 20500916 ps
CPU time 1.04 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:33:12 PM PDT 24
Peak memory 215412 kb
Host smart-6a6bb875-406f-4172-8840-a29d1f1eb6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225425802 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3225425802
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1186640427
Short name T574
Test name
Test status
Simulation time 19064672 ps
CPU time 1.06 seconds
Started Apr 04 03:32:59 PM PDT 24
Finished Apr 04 03:33:01 PM PDT 24
Peak memory 206908 kb
Host smart-09d76aa2-dc35-4c15-a33d-ddca4210edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186640427 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1186640427
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2398468102
Short name T503
Test name
Test status
Simulation time 507080571 ps
CPU time 2.66 seconds
Started Apr 04 03:32:53 PM PDT 24
Finished Apr 04 03:32:56 PM PDT 24
Peak memory 215000 kb
Host smart-927d7b05-d465-45cd-aa4f-aa285b653557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398468102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2398468102
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4066029253
Short name T735
Test name
Test status
Simulation time 311082727352 ps
CPU time 1909.46 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 04:04:59 PM PDT 24
Peak memory 236076 kb
Host smart-a6b6552f-521c-44d2-9edb-902a5626a737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066029253 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4066029253
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1968933108
Short name T658
Test name
Test status
Simulation time 25992496 ps
CPU time 1.13 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:10 PM PDT 24
Peak memory 215264 kb
Host smart-a4669c4b-a4b6-44a2-9d2c-3862abaf1153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968933108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1968933108
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1832366907
Short name T512
Test name
Test status
Simulation time 40280015 ps
CPU time 0.84 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:33:12 PM PDT 24
Peak memory 206096 kb
Host smart-1d25a820-9ece-4edb-bfa0-a44e391501e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832366907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1832366907
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.347521222
Short name T192
Test name
Test status
Simulation time 23838678 ps
CPU time 0.87 seconds
Started Apr 04 03:33:10 PM PDT 24
Finished Apr 04 03:33:11 PM PDT 24
Peak memory 215176 kb
Host smart-14980e9f-3a5b-46e3-b741-e8bae9b16ccb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347521222 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.347521222
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2802063207
Short name T91
Test name
Test status
Simulation time 36396589 ps
CPU time 1.37 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:11 PM PDT 24
Peak memory 216008 kb
Host smart-4cf67ec8-0d1d-4c78-a258-c64ad6517a78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802063207 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2802063207
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3814886157
Short name T116
Test name
Test status
Simulation time 22152014 ps
CPU time 0.88 seconds
Started Apr 04 03:33:08 PM PDT 24
Finished Apr 04 03:33:09 PM PDT 24
Peak memory 217692 kb
Host smart-7813f134-5466-4843-bf62-b2f01ef56898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814886157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3814886157
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4041001706
Short name T707
Test name
Test status
Simulation time 108111715 ps
CPU time 1.62 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:33:12 PM PDT 24
Peak memory 217712 kb
Host smart-397dba03-b9aa-4a15-af33-2245eb3badbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041001706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4041001706
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.702516929
Short name T43
Test name
Test status
Simulation time 24531930 ps
CPU time 1.04 seconds
Started Apr 04 03:33:08 PM PDT 24
Finished Apr 04 03:33:09 PM PDT 24
Peak memory 223792 kb
Host smart-643683e0-5d1a-4971-8d62-49490e553e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702516929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.702516929
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1808858603
Short name T521
Test name
Test status
Simulation time 44554676 ps
CPU time 0.93 seconds
Started Apr 04 03:33:10 PM PDT 24
Finished Apr 04 03:33:11 PM PDT 24
Peak memory 214996 kb
Host smart-9efe47aa-2e8d-43b2-943a-aa79e02e42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808858603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1808858603
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3154309459
Short name T396
Test name
Test status
Simulation time 358507556 ps
CPU time 3.41 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:13 PM PDT 24
Peak memory 216152 kb
Host smart-a5c0aaed-307c-48ec-b3da-a9d1cf981127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154309459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3154309459
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3535642104
Short name T701
Test name
Test status
Simulation time 81406745077 ps
CPU time 1166.54 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:52:36 PM PDT 24
Peak memory 223628 kb
Host smart-122bf3df-fe1a-439f-9710-f72806d2aa75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535642104 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3535642104
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2230476608
Short name T242
Test name
Test status
Simulation time 30922111 ps
CPU time 1.21 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:10 PM PDT 24
Peak memory 215216 kb
Host smart-f8c4b4de-6c62-41d6-b12c-a9a853df963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230476608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2230476608
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1871371598
Short name T600
Test name
Test status
Simulation time 47814900 ps
CPU time 0.9 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 206588 kb
Host smart-63f6ee30-a049-4447-833c-8a8b0a2d296b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871371598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1871371598
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1075918990
Short name T119
Test name
Test status
Simulation time 13986097 ps
CPU time 0.9 seconds
Started Apr 04 03:33:08 PM PDT 24
Finished Apr 04 03:33:09 PM PDT 24
Peak memory 215640 kb
Host smart-52a42c0f-769e-4ce3-a199-662a43e6c05d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075918990 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1075918990
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1204269018
Short name T554
Test name
Test status
Simulation time 61047078 ps
CPU time 0.99 seconds
Started Apr 04 03:33:10 PM PDT 24
Finished Apr 04 03:33:11 PM PDT 24
Peak memory 216136 kb
Host smart-4f571e1a-56fa-4ae1-806b-0a292b2a41fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204269018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1204269018
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3341805046
Short name T333
Test name
Test status
Simulation time 66414066 ps
CPU time 0.79 seconds
Started Apr 04 03:33:10 PM PDT 24
Finished Apr 04 03:33:11 PM PDT 24
Peak memory 217224 kb
Host smart-9bedcb29-b77e-40dc-8955-a4a968c6471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341805046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3341805046
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4154855314
Short name T406
Test name
Test status
Simulation time 109945170 ps
CPU time 1.2 seconds
Started Apr 04 03:33:10 PM PDT 24
Finished Apr 04 03:33:11 PM PDT 24
Peak memory 216348 kb
Host smart-becf26af-5092-4c0b-ad80-7bbf0130ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154855314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4154855314
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3717289571
Short name T734
Test name
Test status
Simulation time 22612479 ps
CPU time 1.12 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:10 PM PDT 24
Peak memory 215092 kb
Host smart-e5ebeef2-c11b-4f56-a56a-0fb02a74b896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717289571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3717289571
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2604608174
Short name T143
Test name
Test status
Simulation time 28989470 ps
CPU time 0.91 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:33:12 PM PDT 24
Peak memory 214912 kb
Host smart-ee4f6769-6afc-4097-b5c5-c72cf0efd3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604608174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2604608174
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3902604763
Short name T410
Test name
Test status
Simulation time 408143319 ps
CPU time 4.13 seconds
Started Apr 04 03:33:09 PM PDT 24
Finished Apr 04 03:33:13 PM PDT 24
Peak memory 216376 kb
Host smart-c5586859-f29f-41f8-b940-52551f89a335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902604763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3902604763
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3521795714
Short name T350
Test name
Test status
Simulation time 35925785962 ps
CPU time 808.69 seconds
Started Apr 04 03:33:11 PM PDT 24
Finished Apr 04 03:46:40 PM PDT 24
Peak memory 218512 kb
Host smart-68aa220a-767d-4218-93b2-781f8aad1c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521795714 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3521795714
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.476138674
Short name T738
Test name
Test status
Simulation time 123276256 ps
CPU time 1.4 seconds
Started Apr 04 03:33:28 PM PDT 24
Finished Apr 04 03:33:30 PM PDT 24
Peak memory 215268 kb
Host smart-b08903fa-556b-40a9-8155-54ecc52d0db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476138674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.476138674
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4045322753
Short name T609
Test name
Test status
Simulation time 58019321 ps
CPU time 0.92 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 206336 kb
Host smart-6f8c840a-1096-4f0f-aad6-ba5af0e48328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045322753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4045322753
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2474481242
Short name T522
Test name
Test status
Simulation time 22921717 ps
CPU time 0.84 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 215040 kb
Host smart-11a595b7-0930-4b4f-846a-9e86e4830d24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474481242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2474481242
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2146957393
Short name T606
Test name
Test status
Simulation time 33476534 ps
CPU time 1.27 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 216144 kb
Host smart-04c7a5ec-45ce-4c5e-bb2a-719b9bfe201b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146957393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2146957393
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4108552132
Short name T87
Test name
Test status
Simulation time 26575433 ps
CPU time 1.32 seconds
Started Apr 04 03:33:30 PM PDT 24
Finished Apr 04 03:33:31 PM PDT 24
Peak memory 232996 kb
Host smart-d0591931-1b6a-428c-a460-47611efa63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108552132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4108552132
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2044574050
Short name T279
Test name
Test status
Simulation time 37278251 ps
CPU time 1.18 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 217568 kb
Host smart-c10010db-356d-4056-abdc-7d5c02a91131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044574050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2044574050
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.705155656
Short name T139
Test name
Test status
Simulation time 21749101 ps
CPU time 0.95 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 215380 kb
Host smart-0a3fc68d-c386-4d2c-b01c-081177e686a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705155656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.705155656
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1428449086
Short name T418
Test name
Test status
Simulation time 166089889 ps
CPU time 0.9 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 214948 kb
Host smart-2b0d957e-9db0-47cf-a5c5-dbe6e3919707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428449086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1428449086
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.286231675
Short name T544
Test name
Test status
Simulation time 1092984866 ps
CPU time 4.18 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:30 PM PDT 24
Peak memory 215012 kb
Host smart-aae7c505-b214-494c-9c43-d1e1fa26c8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286231675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.286231675
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3358242653
Short name T149
Test name
Test status
Simulation time 90727512005 ps
CPU time 270.08 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 217968 kb
Host smart-402a8007-d850-43fd-950c-90eab7b2289b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358242653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3358242653
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3583893341
Short name T152
Test name
Test status
Simulation time 81556107 ps
CPU time 1.2 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 215300 kb
Host smart-7723590e-cc5f-4c05-ae8a-37af2c2f48d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583893341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3583893341
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.608566145
Short name T681
Test name
Test status
Simulation time 20333983 ps
CPU time 0.88 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 205688 kb
Host smart-32797453-4837-4638-88d1-b4fc06eee435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608566145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.608566145
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3988571088
Short name T447
Test name
Test status
Simulation time 21770209 ps
CPU time 0.89 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 215236 kb
Host smart-d674fa71-d5ca-4d73-8bea-8641d10db5e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988571088 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3988571088
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.4021835370
Short name T96
Test name
Test status
Simulation time 19316235 ps
CPU time 1.18 seconds
Started Apr 04 03:33:28 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 232216 kb
Host smart-3dbd4368-792a-4ed4-b8e2-2cf1d473c4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021835370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4021835370
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.350036169
Short name T289
Test name
Test status
Simulation time 180759445 ps
CPU time 1.07 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 216360 kb
Host smart-5effdc91-8be9-4abf-91f9-d93b943cb294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350036169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.350036169
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3115306673
Short name T318
Test name
Test status
Simulation time 37612345 ps
CPU time 0.86 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 215184 kb
Host smart-dd0aa47b-f1b4-4fab-80e6-3930bbc0710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115306673 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3115306673
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3284840819
Short name T778
Test name
Test status
Simulation time 24923461 ps
CPU time 0.95 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 215012 kb
Host smart-45e82bcc-599a-46c9-b979-80a632365d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284840819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3284840819
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2035011405
Short name T682
Test name
Test status
Simulation time 1750206565 ps
CPU time 4.62 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:31 PM PDT 24
Peak memory 216504 kb
Host smart-78395fcb-5402-4fa9-adbf-5ef9d8a1fdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035011405 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2035011405
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1205468416
Short name T811
Test name
Test status
Simulation time 191217945653 ps
CPU time 1081.28 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:51:28 PM PDT 24
Peak memory 221796 kb
Host smart-b3f2fd9b-344c-4828-a6c2-112f5141501d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205468416 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1205468416
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.4064720939
Short name T404
Test name
Test status
Simulation time 96453815 ps
CPU time 1.33 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 215256 kb
Host smart-0336f6df-1bf6-4111-a1fc-9c21ace75c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064720939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4064720939
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3024618288
Short name T389
Test name
Test status
Simulation time 24316078 ps
CPU time 0.87 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 206368 kb
Host smart-7fcc3f03-5b19-4c3c-8b03-6e9cd2a681cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024618288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3024618288
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2050777882
Short name T98
Test name
Test status
Simulation time 17495651 ps
CPU time 0.89 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 215188 kb
Host smart-21128327-60ca-40c3-8fa9-d11224f6cce1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050777882 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2050777882
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.2688645930
Short name T100
Test name
Test status
Simulation time 63378566 ps
CPU time 0.98 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 231072 kb
Host smart-7b73697b-60bc-4321-af0a-173273c7a01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688645930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2688645930
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.261720564
Short name T3
Test name
Test status
Simulation time 84515126 ps
CPU time 1.06 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 216164 kb
Host smart-8c69e019-21de-45ee-b868-303f9a476f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261720564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.261720564
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3788244796
Short name T140
Test name
Test status
Simulation time 36715015 ps
CPU time 0.89 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 215236 kb
Host smart-211d6eb6-b7f1-4654-99bc-0989b20582e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788244796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3788244796
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3291462233
Short name T500
Test name
Test status
Simulation time 17641867 ps
CPU time 0.99 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 214972 kb
Host smart-70836932-08eb-4d55-895b-59e440f9e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291462233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3291462233
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4273469272
Short name T301
Test name
Test status
Simulation time 454130583 ps
CPU time 4.94 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:33 PM PDT 24
Peak memory 214936 kb
Host smart-a4ae1ead-72e7-4b96-90d8-d42050ad7708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273469272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4273469272
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3614831986
Short name T755
Test name
Test status
Simulation time 209201258515 ps
CPU time 1111.03 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:51:58 PM PDT 24
Peak memory 222088 kb
Host smart-c313e973-a2ad-4d34-9132-53efbaff82aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614831986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3614831986
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1299043216
Short name T264
Test name
Test status
Simulation time 28174819 ps
CPU time 1.23 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 215256 kb
Host smart-94307111-a61f-4692-a0a2-8721a6964519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299043216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1299043216
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1704506817
Short name T746
Test name
Test status
Simulation time 39544769 ps
CPU time 0.92 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 205528 kb
Host smart-5e8de83e-6c2e-43ef-b027-a94fccdd6e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704506817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1704506817
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1764544138
Short name T742
Test name
Test status
Simulation time 202466646 ps
CPU time 1.01 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 216008 kb
Host smart-24e1679a-06e6-4e8b-a9ed-3139ca71fd71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764544138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1764544138
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3185615881
Short name T690
Test name
Test status
Simulation time 31570014 ps
CPU time 1.38 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 223936 kb
Host smart-5f2d7808-bd7c-4988-98ab-f196211d076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185615881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3185615881
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.214242288
Short name T595
Test name
Test status
Simulation time 94686097 ps
CPU time 1.48 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 216456 kb
Host smart-37d43ee6-452a-45a9-a46d-c9143b9a7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214242288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.214242288
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2903938235
Short name T523
Test name
Test status
Simulation time 21942876 ps
CPU time 1.19 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 223792 kb
Host smart-57611b42-6563-4334-a262-755af83e71c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903938235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2903938235
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1195939892
Short name T53
Test name
Test status
Simulation time 17677164 ps
CPU time 0.98 seconds
Started Apr 04 03:33:30 PM PDT 24
Finished Apr 04 03:33:31 PM PDT 24
Peak memory 214940 kb
Host smart-bcf51136-ed17-419c-b832-84dcfa8f207e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195939892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1195939892
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1314508809
Short name T623
Test name
Test status
Simulation time 297067666 ps
CPU time 2.15 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 216460 kb
Host smart-6b43fb7b-1ba6-4ac8-8735-82a8357bf601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314508809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1314508809
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2112900074
Short name T409
Test name
Test status
Simulation time 38566849057 ps
CPU time 444.11 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:40:52 PM PDT 24
Peak memory 218016 kb
Host smart-4374f10e-59b1-4672-89fd-3265c19ec1ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112900074 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2112900074
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1470387925
Short name T495
Test name
Test status
Simulation time 43297065 ps
CPU time 1.19 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 215256 kb
Host smart-13d34bca-054e-46c8-9630-7bcdfd9e3e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470387925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1470387925
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4121392363
Short name T345
Test name
Test status
Simulation time 51671279 ps
CPU time 0.87 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 206496 kb
Host smart-88c1b2b5-bf52-407c-bb9e-2c9fb6132ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121392363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4121392363
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3284748024
Short name T303
Test name
Test status
Simulation time 40903009 ps
CPU time 0.81 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 215216 kb
Host smart-cf829753-c49d-4f1c-9b45-7e06334ec31d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284748024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3284748024
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3012987945
Short name T88
Test name
Test status
Simulation time 51591160 ps
CPU time 1.1 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 229724 kb
Host smart-4117740e-ac04-4756-b31e-953f7a0399da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012987945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3012987945
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.676847373
Short name T762
Test name
Test status
Simulation time 46884561 ps
CPU time 1.12 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 217448 kb
Host smart-d956e235-e610-404c-8f84-14ef7df266be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676847373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.676847373
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.1476479437
Short name T451
Test name
Test status
Simulation time 45478114 ps
CPU time 0.9 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:27 PM PDT 24
Peak memory 215012 kb
Host smart-49c0225f-eec6-470f-97c4-925a1f9eccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476479437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1476479437
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1677029936
Short name T148
Test name
Test status
Simulation time 1115586009 ps
CPU time 3.03 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:31 PM PDT 24
Peak memory 216308 kb
Host smart-9a8f3957-f441-4650-93b3-246b9af79640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677029936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1677029936
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2951783219
Short name T283
Test name
Test status
Simulation time 78567015467 ps
CPU time 380.03 seconds
Started Apr 04 03:33:30 PM PDT 24
Finished Apr 04 03:39:50 PM PDT 24
Peak memory 223424 kb
Host smart-989d4313-5482-45d4-a311-05d0770b5d36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951783219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2951783219
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.189210015
Short name T717
Test name
Test status
Simulation time 40806025 ps
CPU time 1.2 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 215304 kb
Host smart-ca20646d-60df-4f05-83d9-d13da0dbbeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189210015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.189210015
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.26643890
Short name T596
Test name
Test status
Simulation time 62010542 ps
CPU time 0.9 seconds
Started Apr 04 03:33:29 PM PDT 24
Finished Apr 04 03:33:30 PM PDT 24
Peak memory 205744 kb
Host smart-4e98b38d-0103-4206-8fef-02a3880ffd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26643890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.26643890
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2551258009
Short name T115
Test name
Test status
Simulation time 27881461 ps
CPU time 0.91 seconds
Started Apr 04 03:33:25 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 215576 kb
Host smart-442283d2-e68d-4897-9b03-c8de986c25a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551258009 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2551258009
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2300719772
Short name T338
Test name
Test status
Simulation time 50414638 ps
CPU time 1.8 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 216096 kb
Host smart-715264c1-229f-47cd-99f8-8b9ef62770b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300719772 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2300719772
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3079389272
Short name T423
Test name
Test status
Simulation time 18956339 ps
CPU time 1.02 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 217364 kb
Host smart-c1888616-e8e1-4179-9395-b4a5df94ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079389272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3079389272
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3228762795
Short name T276
Test name
Test status
Simulation time 210653909 ps
CPU time 1.33 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 218360 kb
Host smart-2d3e3660-872c-4308-92f4-0391570a4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228762795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3228762795
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3476656090
Short name T515
Test name
Test status
Simulation time 24592907 ps
CPU time 1.02 seconds
Started Apr 04 03:33:24 PM PDT 24
Finished Apr 04 03:33:26 PM PDT 24
Peak memory 223760 kb
Host smart-4e116534-6f0e-4eca-aec7-ab5994e14be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476656090 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3476656090
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1752505646
Short name T810
Test name
Test status
Simulation time 26338256 ps
CPU time 0.93 seconds
Started Apr 04 03:33:27 PM PDT 24
Finished Apr 04 03:33:29 PM PDT 24
Peak memory 215000 kb
Host smart-9a892d8e-ddb1-4e48-a97c-3fe774561d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752505646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1752505646
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.324975129
Short name T444
Test name
Test status
Simulation time 75207316 ps
CPU time 1.38 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:33:28 PM PDT 24
Peak memory 216320 kb
Host smart-70667590-7aa2-4ad8-878b-c056a683eb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324975129 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.324975129
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.916792874
Short name T198
Test name
Test status
Simulation time 67054650115 ps
CPU time 1420.1 seconds
Started Apr 04 03:33:26 PM PDT 24
Finished Apr 04 03:57:07 PM PDT 24
Peak memory 223472 kb
Host smart-04ed467e-9c8a-4a63-9f17-e83e7d6db665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916792874 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.916792874
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2842523731
Short name T548
Test name
Test status
Simulation time 25017061 ps
CPU time 1.2 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 215248 kb
Host smart-bbc3dbc4-bba6-47bd-bd6f-d987ad7895e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842523731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2842523731
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1395235171
Short name T315
Test name
Test status
Simulation time 91996855 ps
CPU time 1.06 seconds
Started Apr 04 03:31:33 PM PDT 24
Finished Apr 04 03:31:34 PM PDT 24
Peak memory 205752 kb
Host smart-1e63b630-432a-4370-bc03-ab033a045223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395235171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1395235171
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3117403470
Short name T163
Test name
Test status
Simulation time 11231442 ps
CPU time 0.89 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 215440 kb
Host smart-dd3f0d09-ceb8-404b-ae33-64068cb5dc3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117403470 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3117403470
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.33227424
Short name T113
Test name
Test status
Simulation time 18616337 ps
CPU time 1.04 seconds
Started Apr 04 03:31:37 PM PDT 24
Finished Apr 04 03:31:38 PM PDT 24
Peak memory 217700 kb
Host smart-6d884294-3354-4042-8919-c994e9b5d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33227424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.33227424
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.653660218
Short name T371
Test name
Test status
Simulation time 39616684 ps
CPU time 1.51 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:34 PM PDT 24
Peak memory 216408 kb
Host smart-cb6ab845-9528-4527-9b71-f46935c896a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653660218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.653660218
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3536022107
Short name T765
Test name
Test status
Simulation time 37266678 ps
CPU time 1.02 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 223788 kb
Host smart-b7beed82-a0f2-428f-9f46-5b07dac6ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536022107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3536022107
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1754581961
Short name T254
Test name
Test status
Simulation time 55534525 ps
CPU time 0.89 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 206740 kb
Host smart-99f59340-2e53-4dfc-a3d2-0ab9f90c6e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754581961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1754581961
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2945265097
Short name T21
Test name
Test status
Simulation time 387207630 ps
CPU time 5.95 seconds
Started Apr 04 03:31:30 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 234984 kb
Host smart-ee948915-a67d-480e-bd7e-22d83e5c6aa1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945265097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2945265097
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1806660527
Short name T793
Test name
Test status
Simulation time 17236007 ps
CPU time 1.05 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 215008 kb
Host smart-faf1b1fc-21ba-4081-8ea9-439ea076ca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806660527 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1806660527
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1435106987
Short name T801
Test name
Test status
Simulation time 73887276 ps
CPU time 0.95 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 205692 kb
Host smart-eb246ce0-7c1b-4810-90ff-c0797884c409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435106987 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1435106987
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3119287380
Short name T758
Test name
Test status
Simulation time 99819099761 ps
CPU time 1468.71 seconds
Started Apr 04 03:31:31 PM PDT 24
Finished Apr 04 03:56:00 PM PDT 24
Peak memory 222068 kb
Host smart-ca85e306-1ca9-4e1b-b077-785ed85d1ea1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119287380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3119287380
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.953911429
Short name T191
Test name
Test status
Simulation time 31940220 ps
CPU time 1.37 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 215244 kb
Host smart-08b99223-c0d9-466b-989c-d9148175ccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953911429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.953911429
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2583782421
Short name T155
Test name
Test status
Simulation time 42394527 ps
CPU time 1.08 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 205744 kb
Host smart-48f9a060-1c62-4f2c-9b53-17289901d81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583782421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2583782421
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.970916891
Short name T134
Test name
Test status
Simulation time 30851546 ps
CPU time 1.13 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 217264 kb
Host smart-52a7b00c-265a-4322-b553-c57e9b572ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970916891 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.970916891
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2096458395
Short name T121
Test name
Test status
Simulation time 21378493 ps
CPU time 1.12 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 232256 kb
Host smart-f3de6522-6076-40e0-aef4-e16bfed57b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096458395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2096458395
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3566029327
Short name T470
Test name
Test status
Simulation time 69662184 ps
CPU time 1.51 seconds
Started Apr 04 03:33:39 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 217544 kb
Host smart-95ec2847-c465-4ace-b9dc-ce549e094b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566029327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3566029327
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1644323963
Short name T130
Test name
Test status
Simulation time 23237313 ps
CPU time 1.01 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 215456 kb
Host smart-18d44ea5-b278-4a57-820a-9e4b4fcf1d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644323963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1644323963
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1991958022
Short name T715
Test name
Test status
Simulation time 18054072 ps
CPU time 0.99 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 214956 kb
Host smart-d27acefe-742d-4dbd-b538-e7aa89b6e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991958022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1991958022
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2052891403
Short name T210
Test name
Test status
Simulation time 199875346 ps
CPU time 1.55 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 206852 kb
Host smart-685bf8b9-0a7e-4578-a789-12989f50ff04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052891403 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2052891403
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3663574727
Short name T676
Test name
Test status
Simulation time 123873478164 ps
CPU time 796.1 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:47:00 PM PDT 24
Peak memory 220356 kb
Host smart-1ed340bf-38de-4b8a-9a65-f077ccb813a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663574727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3663574727
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2311892642
Short name T259
Test name
Test status
Simulation time 48560042 ps
CPU time 1.25 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 215212 kb
Host smart-5d8174c5-b7cb-4670-aa7b-452e7488b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311892642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2311892642
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1439592815
Short name T583
Test name
Test status
Simulation time 27550644 ps
CPU time 0.9 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 206204 kb
Host smart-0cf7c1ac-0515-4be7-8561-2889c18512dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439592815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1439592815
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.166983130
Short name T343
Test name
Test status
Simulation time 21496319 ps
CPU time 0.94 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 215632 kb
Host smart-9eb29fe2-f98c-4d69-be1b-d463fd2ae240
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166983130 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.166983130
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.1869532461
Short name T4
Test name
Test status
Simulation time 33491247 ps
CPU time 0.9 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 218800 kb
Host smart-bfd1ce68-56d7-4fad-87f5-1f33a2a8bbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869532461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1869532461
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.829838239
Short name T434
Test name
Test status
Simulation time 32888496 ps
CPU time 1.24 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 217580 kb
Host smart-1a7ec1b6-f2c5-4839-83a5-e5086077babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829838239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.829838239
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3061781210
Short name T585
Test name
Test status
Simulation time 21631190 ps
CPU time 1.06 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 215064 kb
Host smart-1d399ee1-213d-417a-b000-6c393a454185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061781210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3061781210
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1831654241
Short name T296
Test name
Test status
Simulation time 89137109 ps
CPU time 0.91 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 214824 kb
Host smart-61cdd8e3-966a-4156-a435-25706031ed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831654241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1831654241
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.584143690
Short name T656
Test name
Test status
Simulation time 68867207 ps
CPU time 1.33 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 214936 kb
Host smart-057f6201-83a3-44cc-b0dd-8eca5c627c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584143690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.584143690
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.732687665
Short name T640
Test name
Test status
Simulation time 298005991746 ps
CPU time 1655.28 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 04:01:22 PM PDT 24
Peak memory 223500 kb
Host smart-ded22ba8-a72b-4bb2-be3a-cf067f81e72d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732687665 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.732687665
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.1258057521
Short name T472
Test name
Test status
Simulation time 89537160 ps
CPU time 0.82 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 205504 kb
Host smart-5dece065-5e26-4976-af89-d19309ab0b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258057521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1258057521
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1669520938
Short name T493
Test name
Test status
Simulation time 21990454 ps
CPU time 0.87 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:33:41 PM PDT 24
Peak memory 215188 kb
Host smart-aa409b9a-719e-4265-b624-35ad75c1af16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669520938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1669520938
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.1296795536
Short name T161
Test name
Test status
Simulation time 18131437 ps
CPU time 1 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 217500 kb
Host smart-f0083748-ef63-43fc-9191-ad539ce838b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296795536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1296795536
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1781579410
Short name T416
Test name
Test status
Simulation time 52032173 ps
CPU time 1.95 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 216652 kb
Host smart-8a25c574-c80d-4d1f-98f0-296b965357b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781579410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1781579410
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3795603626
Short name T307
Test name
Test status
Simulation time 25915487 ps
CPU time 0.93 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:33:41 PM PDT 24
Peak memory 215072 kb
Host smart-f6e2668b-8265-4649-8d97-e7104caed7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795603626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3795603626
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2790393937
Short name T739
Test name
Test status
Simulation time 15384092 ps
CPU time 0.93 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 215012 kb
Host smart-d05ce82a-060a-4bd3-8c08-76fe9a42a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790393937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2790393937
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3581031570
Short name T387
Test name
Test status
Simulation time 726861502 ps
CPU time 3.99 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:50 PM PDT 24
Peak memory 218912 kb
Host smart-bb78dcd1-4100-4e08-a6cf-952eb98bb291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581031570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3581031570
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1797511691
Short name T756
Test name
Test status
Simulation time 334634175178 ps
CPU time 1824.71 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 04:04:12 PM PDT 24
Peak memory 225444 kb
Host smart-58bbc9f4-5d6f-4fad-b97c-733217a8a2de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797511691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1797511691
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.1259607791
Short name T411
Test name
Test status
Simulation time 30930173 ps
CPU time 0.86 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 206208 kb
Host smart-f0427153-41f5-4204-8ebc-6fa8aa20cc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259607791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1259607791
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1879817609
Short name T162
Test name
Test status
Simulation time 25924282 ps
CPU time 0.86 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 215556 kb
Host smart-aa37fddd-1d8b-4b73-b479-93f0fc1b4dc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879817609 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1879817609
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.451324700
Short name T57
Test name
Test status
Simulation time 116312217 ps
CPU time 1.03 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:33:42 PM PDT 24
Peak memory 217364 kb
Host smart-73b8ca01-2fab-43ba-b950-28646c20572f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451324700 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.451324700
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1449900218
Short name T42
Test name
Test status
Simulation time 61949050 ps
CPU time 1.12 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 229236 kb
Host smart-d0049b7c-4225-4b68-875a-7372cbfe88b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449900218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1449900218
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.162281406
Short name T726
Test name
Test status
Simulation time 71476247 ps
CPU time 1.34 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 217508 kb
Host smart-e1076124-7c6f-44c2-aaaa-316dff98aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162281406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.162281406
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_smoke.968080765
Short name T621
Test name
Test status
Simulation time 44589128 ps
CPU time 0.88 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 214812 kb
Host smart-4fb0bf65-4902-42f3-b50e-420f6ef91802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968080765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.968080765
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1217675200
Short name T505
Test name
Test status
Simulation time 135438474 ps
CPU time 2.91 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 219072 kb
Host smart-82e369ff-b650-43db-b19f-5f386fe3794b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217675200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1217675200
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2090158129
Short name T365
Test name
Test status
Simulation time 59808839044 ps
CPU time 515.88 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:42:19 PM PDT 24
Peak memory 217748 kb
Host smart-c8fc31e5-44c9-4a55-a756-7929138dedb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090158129 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2090158129
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.280434576
Short name T800
Test name
Test status
Simulation time 87870685 ps
CPU time 1.33 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 215208 kb
Host smart-c462bcea-bd41-4690-83f0-32f6e8ebcc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280434576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.280434576
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2091172135
Short name T332
Test name
Test status
Simulation time 48063865 ps
CPU time 0.84 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 205744 kb
Host smart-fc3cc73a-75c2-42a9-ab02-c190dd3ece87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091172135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2091172135
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4068128270
Short name T171
Test name
Test status
Simulation time 60135168 ps
CPU time 0.86 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 215552 kb
Host smart-19ee4cf7-77ed-43c2-b00f-2304c3ca0a93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068128270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4068128270
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2778735251
Short name T539
Test name
Test status
Simulation time 55339680 ps
CPU time 1.08 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 216276 kb
Host smart-9a3f4386-948e-4c34-a925-a6d0e51906ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778735251 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2778735251
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3622864322
Short name T741
Test name
Test status
Simulation time 20030162 ps
CPU time 1.09 seconds
Started Apr 04 03:33:43 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 230960 kb
Host smart-cf138732-48ad-4da6-9489-889b60148664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622864322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3622864322
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.295229565
Short name T494
Test name
Test status
Simulation time 370806077 ps
CPU time 4.03 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 216464 kb
Host smart-174dc829-8abf-4341-8f31-7ada9b79c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295229565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.295229565
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3220716552
Short name T620
Test name
Test status
Simulation time 25538680 ps
CPU time 0.95 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:44 PM PDT 24
Peak memory 215084 kb
Host smart-d3e4a057-b8b1-4f45-a531-de1760e15322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220716552 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3220716552
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2877370198
Short name T642
Test name
Test status
Simulation time 24651920 ps
CPU time 0.91 seconds
Started Apr 04 03:33:41 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 206744 kb
Host smart-5b089303-4822-4dc2-bcbc-2f46319c91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877370198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2877370198
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1073098721
Short name T439
Test name
Test status
Simulation time 399353491 ps
CPU time 2.45 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 214976 kb
Host smart-5419ffa9-8fc1-4dd6-b760-3005f55a50c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073098721 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1073098721
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2213460450
Short name T482
Test name
Test status
Simulation time 37495776274 ps
CPU time 875.34 seconds
Started Apr 04 03:33:40 PM PDT 24
Finished Apr 04 03:48:16 PM PDT 24
Peak memory 217752 kb
Host smart-2e378c60-2369-4fce-be32-03bb0bcd082e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213460450 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2213460450
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1209032646
Short name T563
Test name
Test status
Simulation time 86095121 ps
CPU time 1.22 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 215252 kb
Host smart-77ef384c-3994-4e6e-855e-eb3a0d74eb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209032646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1209032646
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3290606848
Short name T528
Test name
Test status
Simulation time 30211920 ps
CPU time 0.83 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 206232 kb
Host smart-d65783e6-5549-45b2-9042-4bcf784de342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290606848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3290606848
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1386766947
Short name T97
Test name
Test status
Simulation time 99700727 ps
CPU time 0.86 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 215028 kb
Host smart-6fced37d-3e53-442f-84e3-1031fd21c7e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386766947 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1386766947
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.432204526
Short name T432
Test name
Test status
Simulation time 46182138 ps
CPU time 1.43 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 218344 kb
Host smart-eb2bd3c7-4c73-4e78-918b-4ff8a36d8445
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432204526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.432204526
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3905281656
Short name T108
Test name
Test status
Simulation time 20315905 ps
CPU time 1.16 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 231040 kb
Host smart-d0a45fe7-cc64-4690-b084-0374d2e36de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905281656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3905281656
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.242579327
Short name T697
Test name
Test status
Simulation time 74566209 ps
CPU time 1.73 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 217644 kb
Host smart-ec7f876b-1913-4ea3-98fc-11d94042b528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242579327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.242579327
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2007346389
Short name T131
Test name
Test status
Simulation time 26808098 ps
CPU time 0.88 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 215192 kb
Host smart-7af47e77-1309-4395-b212-a3f4f44a0d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007346389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2007346389
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1744094915
Short name T553
Test name
Test status
Simulation time 17939629 ps
CPU time 1.02 seconds
Started Apr 04 03:33:45 PM PDT 24
Finished Apr 04 03:33:46 PM PDT 24
Peak memory 214996 kb
Host smart-87c319a0-ab40-4f54-a1c4-65bfaff8fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744094915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1744094915
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1344263197
Short name T679
Test name
Test status
Simulation time 480734865 ps
CPU time 2.77 seconds
Started Apr 04 03:33:39 PM PDT 24
Finished Apr 04 03:33:43 PM PDT 24
Peak memory 215984 kb
Host smart-38e6c2f3-f5f5-4389-8692-9e5e0a89b590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344263197 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1344263197
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.520044021
Short name T405
Test name
Test status
Simulation time 511148624483 ps
CPU time 1610.75 seconds
Started Apr 04 03:33:42 PM PDT 24
Finished Apr 04 04:00:34 PM PDT 24
Peak memory 225796 kb
Host smart-fd40e0af-8bed-4602-a07e-a62159681af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520044021 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.520044021
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.3046825763
Short name T429
Test name
Test status
Simulation time 10486625 ps
CPU time 0.79 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:49 PM PDT 24
Peak memory 205432 kb
Host smart-09fb970b-8379-4efd-9af8-75ada60559c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046825763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3046825763
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2010805779
Short name T102
Test name
Test status
Simulation time 20623696 ps
CPU time 0.84 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 215036 kb
Host smart-28376aab-b0f2-46de-a750-477a9f543b01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010805779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2010805779
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2749861061
Short name T491
Test name
Test status
Simulation time 30120732 ps
CPU time 1.16 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 217468 kb
Host smart-c965e9dc-5d2f-44f6-84fa-42fc046097ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749861061 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2749861061
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2786728816
Short name T65
Test name
Test status
Simulation time 20657358 ps
CPU time 1.17 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 229396 kb
Host smart-ad8fab7d-4e5c-4ef0-afab-13f90d921687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786728816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2786728816
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.131070160
Short name T788
Test name
Test status
Simulation time 58055688 ps
CPU time 1.22 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:49 PM PDT 24
Peak memory 214964 kb
Host smart-1c15ba6f-1f2d-4ed4-85c7-6c7725ef9f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131070160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.131070160
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2968490263
Short name T37
Test name
Test status
Simulation time 22610716 ps
CPU time 1.21 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 223772 kb
Host smart-399ab266-a418-4ca4-84d3-3d89fb2b975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968490263 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2968490263
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.537383189
Short name T413
Test name
Test status
Simulation time 88107043 ps
CPU time 0.86 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 214984 kb
Host smart-47daebbd-a294-4600-89f4-5eab60c7fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537383189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.537383189
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2613215415
Short name T35
Test name
Test status
Simulation time 147360298 ps
CPU time 3.44 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:50 PM PDT 24
Peak memory 216184 kb
Host smart-a557538e-4c30-45f9-8eac-1a9ed3bb7ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613215415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2613215415
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1348487838
Short name T200
Test name
Test status
Simulation time 47478318257 ps
CPU time 1058.53 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:51:27 PM PDT 24
Peak memory 223376 kb
Host smart-b939ddd5-19a4-44cf-8f1d-b671cb73ecef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348487838 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1348487838
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1505274828
Short name T150
Test name
Test status
Simulation time 221073163 ps
CPU time 1.37 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:50 PM PDT 24
Peak memory 215220 kb
Host smart-b616c7a5-50ed-48ef-9ef4-0a3f73f49d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505274828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1505274828
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2007733489
Short name T467
Test name
Test status
Simulation time 19366001 ps
CPU time 0.93 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 205680 kb
Host smart-cb971f97-ec6c-4722-8774-516fb73a1a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007733489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2007733489
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.247102444
Short name T504
Test name
Test status
Simulation time 19092127 ps
CPU time 0.94 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:49 PM PDT 24
Peak memory 215488 kb
Host smart-ebb0390d-5dd5-41ac-8ed6-7e92236d8c4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247102444 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.247102444
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.788104569
Short name T75
Test name
Test status
Simulation time 64084877 ps
CPU time 0.98 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:49 PM PDT 24
Peak memory 216084 kb
Host smart-c4dc2267-5859-439d-b7e2-11668a715bf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788104569 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.788104569
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2890834975
Short name T677
Test name
Test status
Simulation time 19354888 ps
CPU time 1.06 seconds
Started Apr 04 03:33:44 PM PDT 24
Finished Apr 04 03:33:45 PM PDT 24
Peak memory 217604 kb
Host smart-75ff4074-4beb-4100-bdc7-5ba24eaac36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890834975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2890834975
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3785784636
Short name T291
Test name
Test status
Simulation time 45972995 ps
CPU time 1.68 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:49 PM PDT 24
Peak memory 216424 kb
Host smart-ed86709a-90e7-4ef2-866a-6b994940a510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785784636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3785784636
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2940055754
Short name T465
Test name
Test status
Simulation time 21108915 ps
CPU time 1.15 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:48 PM PDT 24
Peak memory 215036 kb
Host smart-d7084050-cfb8-4b87-9fc7-a108044c1908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940055754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2940055754
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.360172070
Short name T300
Test name
Test status
Simulation time 30218491 ps
CPU time 1.02 seconds
Started Apr 04 03:33:46 PM PDT 24
Finished Apr 04 03:33:47 PM PDT 24
Peak memory 214992 kb
Host smart-4d07e15d-19d3-4794-976a-000b5a1fbdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360172070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.360172070
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1778676436
Short name T142
Test name
Test status
Simulation time 2026087767 ps
CPU time 4.65 seconds
Started Apr 04 03:33:47 PM PDT 24
Finished Apr 04 03:33:51 PM PDT 24
Peak memory 216268 kb
Host smart-023808fb-0316-4722-8e59-f13efdb73262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778676436 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1778676436
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.294214495
Short name T19
Test name
Test status
Simulation time 33349582 ps
CPU time 1.08 seconds
Started Apr 04 03:33:59 PM PDT 24
Finished Apr 04 03:34:00 PM PDT 24
Peak memory 215268 kb
Host smart-26c96f49-790d-4033-b733-f83df6871bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294214495 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.294214495
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1568491500
Short name T798
Test name
Test status
Simulation time 104406243 ps
CPU time 0.89 seconds
Started Apr 04 03:33:55 PM PDT 24
Finished Apr 04 03:33:56 PM PDT 24
Peak memory 205732 kb
Host smart-a86afa82-cd08-4647-a7d2-b80e31d5736c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568491500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1568491500
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2087722598
Short name T168
Test name
Test status
Simulation time 12413426 ps
CPU time 0.92 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:58 PM PDT 24
Peak memory 215184 kb
Host smart-cbc01e3d-d5a7-4f89-b2ac-9ead456a6ba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087722598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2087722598
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.3702972372
Short name T524
Test name
Test status
Simulation time 30146875 ps
CPU time 0.89 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:58 PM PDT 24
Peak memory 217236 kb
Host smart-2ffb219f-b55c-457e-b38b-2f50175364e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702972372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3702972372
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3420932445
Short name T293
Test name
Test status
Simulation time 61658148 ps
CPU time 1.59 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:50 PM PDT 24
Peak memory 219340 kb
Host smart-146ace71-1b6f-4f2e-a4fe-aea8656e927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420932445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3420932445
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3872271326
Short name T784
Test name
Test status
Simulation time 31137056 ps
CPU time 0.93 seconds
Started Apr 04 03:33:58 PM PDT 24
Finished Apr 04 03:33:59 PM PDT 24
Peak memory 215276 kb
Host smart-87e56876-25c2-4897-9a61-ac62468b0d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872271326 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3872271326
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3411420914
Short name T348
Test name
Test status
Simulation time 35598737 ps
CPU time 0.89 seconds
Started Apr 04 03:33:48 PM PDT 24
Finished Apr 04 03:33:49 PM PDT 24
Peak memory 214956 kb
Host smart-79f5b015-7f75-4e3c-a191-3889c26a3e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411420914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3411420914
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2407531566
Short name T380
Test name
Test status
Simulation time 266541948 ps
CPU time 5.36 seconds
Started Apr 04 03:33:56 PM PDT 24
Finished Apr 04 03:34:01 PM PDT 24
Peak memory 216188 kb
Host smart-4f46ca47-3e90-42d6-a0e4-62b15b0f410b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407531566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2407531566
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2482544438
Short name T716
Test name
Test status
Simulation time 290769738175 ps
CPU time 1712.92 seconds
Started Apr 04 03:33:56 PM PDT 24
Finished Apr 04 04:02:29 PM PDT 24
Peak memory 231508 kb
Host smart-24d9d27b-3cab-4856-a198-f8b52d38ca00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482544438 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2482544438
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2337254969
Short name T72
Test name
Test status
Simulation time 89380729 ps
CPU time 1.25 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:58 PM PDT 24
Peak memory 215240 kb
Host smart-4827ef5a-5b4f-4db1-bf32-22eb65a13ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337254969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2337254969
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.24092858
Short name T540
Test name
Test status
Simulation time 112760803 ps
CPU time 0.92 seconds
Started Apr 04 03:34:02 PM PDT 24
Finished Apr 04 03:34:03 PM PDT 24
Peak memory 206144 kb
Host smart-7bfedc6c-bd72-4374-9671-edfe62fb6c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24092858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.24092858
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1126018495
Short name T176
Test name
Test status
Simulation time 31538388 ps
CPU time 0.84 seconds
Started Apr 04 03:33:59 PM PDT 24
Finished Apr 04 03:34:00 PM PDT 24
Peak memory 215420 kb
Host smart-c10a3177-c51d-431f-94ff-f5e7e4c4c8d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126018495 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1126018495
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1915145936
Short name T84
Test name
Test status
Simulation time 34483879 ps
CPU time 1.21 seconds
Started Apr 04 03:33:56 PM PDT 24
Finished Apr 04 03:33:57 PM PDT 24
Peak memory 217612 kb
Host smart-e8aa325c-50f8-47a2-8d89-8c53ba437cfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915145936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1915145936
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1398285812
Short name T77
Test name
Test status
Simulation time 36275122 ps
CPU time 0.91 seconds
Started Apr 04 03:33:56 PM PDT 24
Finished Apr 04 03:33:57 PM PDT 24
Peak memory 216420 kb
Host smart-238d7668-fc0f-4978-b3c8-c5c73ea52f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398285812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1398285812
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3298944069
Short name T753
Test name
Test status
Simulation time 73808845 ps
CPU time 1.37 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:59 PM PDT 24
Peak memory 217600 kb
Host smart-2bf44749-ef3e-46d3-bf14-631a58d596f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298944069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3298944069
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3371205928
Short name T672
Test name
Test status
Simulation time 22434166 ps
CPU time 1.18 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:58 PM PDT 24
Peak memory 223752 kb
Host smart-71f4edf4-88fe-4198-99ac-b57a8c1cb883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371205928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3371205928
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1521839621
Short name T806
Test name
Test status
Simulation time 41515711 ps
CPU time 0.91 seconds
Started Apr 04 03:34:01 PM PDT 24
Finished Apr 04 03:34:01 PM PDT 24
Peak memory 214956 kb
Host smart-74509227-76e0-4fc7-ae43-5bb12e987657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521839621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1521839621
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2676203319
Short name T737
Test name
Test status
Simulation time 427527014 ps
CPU time 2.88 seconds
Started Apr 04 03:33:56 PM PDT 24
Finished Apr 04 03:33:59 PM PDT 24
Peak memory 216400 kb
Host smart-a4517e08-9a21-46b0-97dc-8a2923943f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676203319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2676203319
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.416799587
Short name T691
Test name
Test status
Simulation time 46594073007 ps
CPU time 502.7 seconds
Started Apr 04 03:33:59 PM PDT 24
Finished Apr 04 03:42:22 PM PDT 24
Peak memory 217680 kb
Host smart-78b6ff7a-36ad-445f-a26d-2d8610dfc7a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416799587 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.416799587
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.3992074457
Short name T310
Test name
Test status
Simulation time 22179968 ps
CPU time 1.02 seconds
Started Apr 04 03:31:34 PM PDT 24
Finished Apr 04 03:31:35 PM PDT 24
Peak memory 205748 kb
Host smart-7702ae19-3329-4148-a79d-0295c58eb8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992074457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3992074457
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2723348270
Short name T479
Test name
Test status
Simulation time 33028591 ps
CPU time 0.89 seconds
Started Apr 04 03:31:35 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 215488 kb
Host smart-6f555805-d4cb-44e7-a372-d049fc5c7405
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723348270 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2723348270
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.126909195
Short name T430
Test name
Test status
Simulation time 48720222 ps
CPU time 0.93 seconds
Started Apr 04 03:31:34 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 230828 kb
Host smart-180d4b81-02cb-4c64-9116-8c5e12a18d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126909195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.126909195
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2793434909
Short name T818
Test name
Test status
Simulation time 98756242 ps
CPU time 2.17 seconds
Started Apr 04 03:31:34 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 217748 kb
Host smart-ff0ca3ea-e7a1-4a33-8906-f1953a462e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793434909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2793434909
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.824536978
Short name T774
Test name
Test status
Simulation time 21202709 ps
CPU time 1.09 seconds
Started Apr 04 03:31:35 PM PDT 24
Finished Apr 04 03:31:37 PM PDT 24
Peak memory 215048 kb
Host smart-f3be0650-7819-41c3-9c0b-106c8f8dd4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824536978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.824536978
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3432556986
Short name T47
Test name
Test status
Simulation time 44682653 ps
CPU time 0.9 seconds
Started Apr 04 03:31:32 PM PDT 24
Finished Apr 04 03:31:33 PM PDT 24
Peak memory 206780 kb
Host smart-9960de0e-f378-4675-9d17-e819ffa2638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432556986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3432556986
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3077823051
Short name T598
Test name
Test status
Simulation time 19938382 ps
CPU time 1 seconds
Started Apr 04 03:31:31 PM PDT 24
Finished Apr 04 03:31:32 PM PDT 24
Peak memory 214968 kb
Host smart-368923ca-4697-4660-b8a8-067ebd4e1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077823051 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3077823051
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2889788085
Short name T695
Test name
Test status
Simulation time 215943426 ps
CPU time 4.46 seconds
Started Apr 04 03:31:33 PM PDT 24
Finished Apr 04 03:31:37 PM PDT 24
Peak memory 216212 kb
Host smart-57209f1b-666c-4497-8930-ff8cfad1decb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889788085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2889788085
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.487625186
Short name T730
Test name
Test status
Simulation time 23760221447 ps
CPU time 511.39 seconds
Started Apr 04 03:31:34 PM PDT 24
Finished Apr 04 03:40:06 PM PDT 24
Peak memory 217636 kb
Host smart-192b69cc-4aa5-48cf-a8f8-0df8967b1fcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487625186 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.487625186
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2549387868
Short name T823
Test name
Test status
Simulation time 39756004 ps
CPU time 1.15 seconds
Started Apr 04 03:34:01 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 216432 kb
Host smart-0583ce8a-503d-4bbf-a222-5689e718f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549387868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2549387868
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1814597424
Short name T764
Test name
Test status
Simulation time 118537335 ps
CPU time 2.5 seconds
Started Apr 04 03:33:59 PM PDT 24
Finished Apr 04 03:34:01 PM PDT 24
Peak memory 218236 kb
Host smart-50c039fc-96f2-417a-8d0e-e9bef26a354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814597424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1814597424
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2435548248
Short name T61
Test name
Test status
Simulation time 123780637 ps
CPU time 1.09 seconds
Started Apr 04 03:33:56 PM PDT 24
Finished Apr 04 03:33:57 PM PDT 24
Peak memory 218668 kb
Host smart-734251c3-411e-496f-b697-fd656f7102ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435548248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2435548248
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2548639329
Short name T545
Test name
Test status
Simulation time 112138175 ps
CPU time 1.64 seconds
Started Apr 04 03:34:00 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 217648 kb
Host smart-f383581a-42f4-4005-b645-0e2a8581288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548639329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2548639329
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.669880760
Short name T73
Test name
Test status
Simulation time 51052931 ps
CPU time 1.12 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:58 PM PDT 24
Peak memory 229436 kb
Host smart-927c1bae-978f-4580-bd57-e27f22c83374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669880760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.669880760
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3982708611
Short name T674
Test name
Test status
Simulation time 87918848 ps
CPU time 1.96 seconds
Started Apr 04 03:34:01 PM PDT 24
Finished Apr 04 03:34:03 PM PDT 24
Peak memory 217944 kb
Host smart-84f1481d-f27e-443b-a367-a67f005162a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982708611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3982708611
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2988071453
Short name T109
Test name
Test status
Simulation time 73476036 ps
CPU time 0.85 seconds
Started Apr 04 03:33:58 PM PDT 24
Finished Apr 04 03:33:59 PM PDT 24
Peak memory 217300 kb
Host smart-a9d44803-ed38-4c08-8d4e-509cae33a8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988071453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2988071453
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3383683430
Short name T275
Test name
Test status
Simulation time 52252911 ps
CPU time 1.24 seconds
Started Apr 04 03:34:02 PM PDT 24
Finished Apr 04 03:34:03 PM PDT 24
Peak memory 216432 kb
Host smart-fafb7bf4-8d97-4b71-b2ca-495f6e50298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383683430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3383683430
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.719626972
Short name T63
Test name
Test status
Simulation time 41594687 ps
CPU time 0.83 seconds
Started Apr 04 03:33:57 PM PDT 24
Finished Apr 04 03:33:58 PM PDT 24
Peak memory 217668 kb
Host smart-97866a09-2356-4fe5-b133-406d91ee0cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719626972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.719626972
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3716890265
Short name T477
Test name
Test status
Simulation time 49155297 ps
CPU time 1.12 seconds
Started Apr 04 03:33:59 PM PDT 24
Finished Apr 04 03:34:00 PM PDT 24
Peak memory 216232 kb
Host smart-4c10d616-d420-4224-85df-d1b56b33f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716890265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3716890265
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.292153481
Short name T81
Test name
Test status
Simulation time 24922922 ps
CPU time 1.34 seconds
Started Apr 04 03:34:03 PM PDT 24
Finished Apr 04 03:34:05 PM PDT 24
Peak memory 229348 kb
Host smart-3d663cd5-7f16-4ee4-a593-ce1071bfd58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292153481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.292153481
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1997329095
Short name T587
Test name
Test status
Simulation time 39618034 ps
CPU time 1.42 seconds
Started Apr 04 03:34:00 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 218932 kb
Host smart-e2d23703-8dd5-4d36-8880-e45e1e9eeb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997329095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1997329095
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2687820305
Short name T166
Test name
Test status
Simulation time 18558289 ps
CPU time 1.19 seconds
Started Apr 04 03:34:02 PM PDT 24
Finished Apr 04 03:34:03 PM PDT 24
Peak memory 230960 kb
Host smart-d58d8b33-5822-41cd-816b-7b3ad67fc237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687820305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2687820305
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1374288601
Short name T664
Test name
Test status
Simulation time 69666906 ps
CPU time 1.07 seconds
Started Apr 04 03:34:00 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 216324 kb
Host smart-4fc07f18-6332-4c8f-a65a-cbc2117b3a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374288601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1374288601
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3301469179
Short name T597
Test name
Test status
Simulation time 24578204 ps
CPU time 1.2 seconds
Started Apr 04 03:33:59 PM PDT 24
Finished Apr 04 03:34:01 PM PDT 24
Peak memory 217584 kb
Host smart-9b0d63ac-0dcd-4cad-9034-d0a0b272861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301469179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3301469179
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.961596063
Short name T492
Test name
Test status
Simulation time 54660815 ps
CPU time 1.21 seconds
Started Apr 04 03:34:01 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 216536 kb
Host smart-482d40ef-510c-497f-9927-569cd257d5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961596063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.961596063
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2589459902
Short name T390
Test name
Test status
Simulation time 18035948 ps
CPU time 1.02 seconds
Started Apr 04 03:34:05 PM PDT 24
Finished Apr 04 03:34:06 PM PDT 24
Peak memory 217576 kb
Host smart-1abb8b1e-2fa1-491b-9d75-d6153f0a4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589459902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2589459902
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4003452209
Short name T398
Test name
Test status
Simulation time 75583473 ps
CPU time 1.33 seconds
Started Apr 04 03:34:01 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 217664 kb
Host smart-3bb7e103-147d-49ee-9aec-fcb9d3c83f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003452209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4003452209
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3172913407
Short name T169
Test name
Test status
Simulation time 76738500 ps
CPU time 1.2 seconds
Started Apr 04 03:34:05 PM PDT 24
Finished Apr 04 03:34:06 PM PDT 24
Peak memory 224020 kb
Host smart-332ebbdc-a27d-43f7-9079-d7723673214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172913407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3172913407
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3040818423
Short name T768
Test name
Test status
Simulation time 69320016 ps
CPU time 1.21 seconds
Started Apr 04 03:34:03 PM PDT 24
Finished Apr 04 03:34:04 PM PDT 24
Peak memory 217624 kb
Host smart-41258be6-efb0-4728-bf8b-9aab93d74f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040818423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3040818423
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1818983647
Short name T692
Test name
Test status
Simulation time 97398884 ps
CPU time 1.31 seconds
Started Apr 04 03:31:36 PM PDT 24
Finished Apr 04 03:31:37 PM PDT 24
Peak memory 215256 kb
Host smart-88b60c7c-4f2b-4926-b1ff-384e99d9a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818983647 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1818983647
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2065451733
Short name T412
Test name
Test status
Simulation time 45774877 ps
CPU time 0.88 seconds
Started Apr 04 03:31:38 PM PDT 24
Finished Apr 04 03:31:39 PM PDT 24
Peak memory 206248 kb
Host smart-486269e7-4ce8-46bb-97d0-1f97c7e92ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065451733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2065451733
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.444316186
Short name T124
Test name
Test status
Simulation time 13905033 ps
CPU time 0.89 seconds
Started Apr 04 03:31:36 PM PDT 24
Finished Apr 04 03:31:38 PM PDT 24
Peak memory 215708 kb
Host smart-58082a71-6a00-426a-bf26-7bf39824a191
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444316186 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.444316186
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.11076054
Short name T69
Test name
Test status
Simulation time 136729842 ps
CPU time 1.25 seconds
Started Apr 04 03:31:36 PM PDT 24
Finished Apr 04 03:31:37 PM PDT 24
Peak memory 217352 kb
Host smart-e21f1af8-2bc0-433c-a4b7-965e054c4d8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076054 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disa
ble_auto_req_mode.11076054
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4250640380
Short name T8
Test name
Test status
Simulation time 34082241 ps
CPU time 0.9 seconds
Started Apr 04 03:31:36 PM PDT 24
Finished Apr 04 03:31:37 PM PDT 24
Peak memory 218812 kb
Host smart-1b06aef8-e7d1-466c-abc3-8f02a5357959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250640380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4250640380
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3836656402
Short name T516
Test name
Test status
Simulation time 49997047 ps
CPU time 1.51 seconds
Started Apr 04 03:31:37 PM PDT 24
Finished Apr 04 03:31:39 PM PDT 24
Peak memory 217484 kb
Host smart-cf39c891-3ef6-4c5e-b862-5706255fa386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836656402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3836656402
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2424680912
Short name T538
Test name
Test status
Simulation time 21942201 ps
CPU time 1.14 seconds
Started Apr 04 03:31:34 PM PDT 24
Finished Apr 04 03:31:35 PM PDT 24
Peak memory 215008 kb
Host smart-7c00a84f-beec-4604-a662-475eefd7dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424680912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2424680912
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.4199525930
Short name T258
Test name
Test status
Simulation time 18620945 ps
CPU time 0.98 seconds
Started Apr 04 03:31:34 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 206768 kb
Host smart-7443fd7a-46b1-44af-a860-6834a04d375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199525930 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4199525930
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.309605739
Short name T327
Test name
Test status
Simulation time 25031555 ps
CPU time 0.92 seconds
Started Apr 04 03:31:35 PM PDT 24
Finished Apr 04 03:31:36 PM PDT 24
Peak memory 215004 kb
Host smart-b589664c-761b-4e5b-8a26-52f834ece59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309605739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.309605739
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2269838308
Short name T45
Test name
Test status
Simulation time 318652003 ps
CPU time 3.46 seconds
Started Apr 04 03:31:37 PM PDT 24
Finished Apr 04 03:31:40 PM PDT 24
Peak memory 216220 kb
Host smart-75df2dbe-f1bd-4872-960b-644ed04d0b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269838308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2269838308
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.888744618
Short name T40
Test name
Test status
Simulation time 62982024 ps
CPU time 1.17 seconds
Started Apr 04 03:34:07 PM PDT 24
Finished Apr 04 03:34:09 PM PDT 24
Peak memory 231916 kb
Host smart-18f81430-04f2-4e4b-96a2-80551bb5ebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888744618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.888744618
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2059377236
Short name T369
Test name
Test status
Simulation time 37888099 ps
CPU time 1.39 seconds
Started Apr 04 03:34:00 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 216264 kb
Host smart-581b7338-4aa7-4a22-a1f5-ca92e40bacdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059377236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2059377236
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2303039464
Short name T438
Test name
Test status
Simulation time 24599103 ps
CPU time 0.87 seconds
Started Apr 04 03:34:07 PM PDT 24
Finished Apr 04 03:34:08 PM PDT 24
Peak memory 217268 kb
Host smart-d0f27d14-35f3-412e-97c5-8823bf4fc429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303039464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2303039464
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1756042239
Short name T484
Test name
Test status
Simulation time 107626873 ps
CPU time 0.97 seconds
Started Apr 04 03:34:06 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 216292 kb
Host smart-d9e33190-a3a0-44e3-9fe3-a79d64ec0bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756042239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1756042239
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3014380795
Short name T330
Test name
Test status
Simulation time 29110855 ps
CPU time 0.84 seconds
Started Apr 04 03:34:06 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 217268 kb
Host smart-cf726465-83ea-49c2-a185-53b04954eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014380795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3014380795
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2370116778
Short name T473
Test name
Test status
Simulation time 40508931 ps
CPU time 1.35 seconds
Started Apr 04 03:34:05 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 217696 kb
Host smart-4cba3dc7-9fa0-4ba6-aeb0-d6a805e67542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370116778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2370116778
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3567395698
Short name T78
Test name
Test status
Simulation time 31925623 ps
CPU time 0.99 seconds
Started Apr 04 03:34:05 PM PDT 24
Finished Apr 04 03:34:06 PM PDT 24
Peak memory 218800 kb
Host smart-94cbd3cc-8cc2-4b10-a665-b51b657623da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567395698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3567395698
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1958074528
Short name T615
Test name
Test status
Simulation time 48106741 ps
CPU time 1.2 seconds
Started Apr 04 03:34:07 PM PDT 24
Finished Apr 04 03:34:09 PM PDT 24
Peak memory 218616 kb
Host smart-4c91c2b3-c755-452f-8e62-ac77ff1066ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958074528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1958074528
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_genbits.484816289
Short name T643
Test name
Test status
Simulation time 176999464 ps
CPU time 1.02 seconds
Started Apr 04 03:34:04 PM PDT 24
Finished Apr 04 03:34:05 PM PDT 24
Peak memory 216288 kb
Host smart-c2aa0e3d-5326-4ad8-80cc-649846c7ba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484816289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.484816289
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2465526099
Short name T552
Test name
Test status
Simulation time 65438479 ps
CPU time 0.81 seconds
Started Apr 04 03:34:06 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 217148 kb
Host smart-4da16868-d539-497f-b91b-09a5ce156c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465526099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2465526099
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3356417223
Short name T785
Test name
Test status
Simulation time 58737061 ps
CPU time 1.51 seconds
Started Apr 04 03:34:05 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 216380 kb
Host smart-d4432364-87c7-40d6-bf85-8cfabd0c296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356417223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3356417223
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2186991720
Short name T302
Test name
Test status
Simulation time 19454062 ps
CPU time 1.11 seconds
Started Apr 04 03:34:01 PM PDT 24
Finished Apr 04 03:34:02 PM PDT 24
Peak memory 217488 kb
Host smart-9cabddcd-9440-42cd-8378-68a2694f166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186991720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2186991720
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2366653160
Short name T687
Test name
Test status
Simulation time 115130873 ps
CPU time 1.88 seconds
Started Apr 04 03:34:02 PM PDT 24
Finished Apr 04 03:34:04 PM PDT 24
Peak memory 218020 kb
Host smart-8ef824eb-2bdd-402a-bedb-0e3e9e283700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366653160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2366653160
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.721424648
Short name T471
Test name
Test status
Simulation time 22875340 ps
CPU time 1.07 seconds
Started Apr 04 03:34:04 PM PDT 24
Finished Apr 04 03:34:05 PM PDT 24
Peak memory 222700 kb
Host smart-bbcb9fcc-c2ce-438b-8945-5bcba0c7f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721424648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.721424648
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3173618344
Short name T797
Test name
Test status
Simulation time 119102272 ps
CPU time 2.62 seconds
Started Apr 04 03:34:07 PM PDT 24
Finished Apr 04 03:34:10 PM PDT 24
Peak memory 216484 kb
Host smart-1e153a86-07c2-4c58-b7ef-31f89bcd0c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173618344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3173618344
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3943542870
Short name T95
Test name
Test status
Simulation time 28485339 ps
CPU time 1.32 seconds
Started Apr 04 03:34:07 PM PDT 24
Finished Apr 04 03:34:08 PM PDT 24
Peak memory 223928 kb
Host smart-66ce1790-d4d9-4c75-8210-fff370e47c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943542870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3943542870
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.4077677359
Short name T287
Test name
Test status
Simulation time 52902427 ps
CPU time 2.01 seconds
Started Apr 04 03:34:06 PM PDT 24
Finished Apr 04 03:34:08 PM PDT 24
Peak memory 218196 kb
Host smart-3e850a1e-ed28-4436-8af1-6930874c186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077677359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4077677359
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2403377823
Short name T809
Test name
Test status
Simulation time 72041776 ps
CPU time 1.02 seconds
Started Apr 04 03:34:17 PM PDT 24
Finished Apr 04 03:34:18 PM PDT 24
Peak memory 218820 kb
Host smart-6e98648a-41d5-4ffc-b9a5-5b9aba57d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403377823 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2403377823
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1671528063
Short name T458
Test name
Test status
Simulation time 81526835 ps
CPU time 1.15 seconds
Started Apr 04 03:34:04 PM PDT 24
Finished Apr 04 03:34:05 PM PDT 24
Peak memory 216104 kb
Host smart-7e0af0cc-0bbb-4f49-aecc-65f01ccb9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671528063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1671528063
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.325479463
Short name T153
Test name
Test status
Simulation time 24940817 ps
CPU time 1.19 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 215268 kb
Host smart-57ecdb49-1b6f-4cd3-86b0-1547e5edaf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325479463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.325479463
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4024340633
Short name T325
Test name
Test status
Simulation time 51245160 ps
CPU time 0.93 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:49 PM PDT 24
Peak memory 206388 kb
Host smart-9a31d474-f516-4c06-a096-dd9b7c218bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024340633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4024340633
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1916363240
Short name T570
Test name
Test status
Simulation time 13589104 ps
CPU time 0.94 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 215648 kb
Host smart-8bc219a0-6a95-4d4d-8c5a-333a93d3d56c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916363240 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1916363240
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2556724299
Short name T688
Test name
Test status
Simulation time 35232353 ps
CPU time 1.19 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:49 PM PDT 24
Peak memory 217460 kb
Host smart-e3715a6e-140b-4d36-9088-23f8630fcceb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556724299 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2556724299
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3897407800
Short name T393
Test name
Test status
Simulation time 18148695 ps
CPU time 1.15 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 230888 kb
Host smart-996263c7-d382-4800-8fbc-267592772b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897407800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3897407800
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1442403091
Short name T426
Test name
Test status
Simulation time 43834418 ps
CPU time 1.54 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:49 PM PDT 24
Peak memory 217660 kb
Host smart-37f3ad37-234d-48d9-9f66-5af39345fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442403091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1442403091
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4275227523
Short name T363
Test name
Test status
Simulation time 31259977 ps
CPU time 1.01 seconds
Started Apr 04 03:31:49 PM PDT 24
Finished Apr 04 03:31:50 PM PDT 24
Peak memory 223772 kb
Host smart-1789ef73-df1c-4c7f-a355-4f7b821a7290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275227523 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4275227523
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.338812468
Short name T208
Test name
Test status
Simulation time 53934719 ps
CPU time 0.97 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 215028 kb
Host smart-999249c3-a513-4a68-80aa-bb6278436730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338812468 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.338812468
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4159225838
Short name T487
Test name
Test status
Simulation time 443717533 ps
CPU time 2.83 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:54 PM PDT 24
Peak memory 216180 kb
Host smart-71f91163-61af-4962-8af0-b9d9f2aff01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159225838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4159225838
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2470321149
Short name T761
Test name
Test status
Simulation time 836121541526 ps
CPU time 2667.67 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 04:16:20 PM PDT 24
Peak memory 226840 kb
Host smart-89603a3b-3a99-4062-8b87-b770beb02833
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470321149 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2470321149
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2000505491
Short name T534
Test name
Test status
Simulation time 25501862 ps
CPU time 0.86 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 217172 kb
Host smart-df620ee6-d0b8-4424-bfa3-b599a3dac503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000505491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2000505491
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4030077311
Short name T356
Test name
Test status
Simulation time 37537035 ps
CPU time 1.31 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 216224 kb
Host smart-e3e8aef9-4456-4f1b-9ca5-a98e8dca421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030077311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4030077311
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1321318988
Short name T99
Test name
Test status
Simulation time 29633158 ps
CPU time 0.99 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 230876 kb
Host smart-4028fca6-8f01-4522-bf9c-432ff91c675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321318988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1321318988
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.628412147
Short name T11
Test name
Test status
Simulation time 83979814 ps
CPU time 1.17 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 218556 kb
Host smart-650abd89-784f-463c-ad3c-f4c6d2eaa0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628412147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.628412147
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3613762437
Short name T480
Test name
Test status
Simulation time 49298204 ps
CPU time 0.99 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 218780 kb
Host smart-f85cacb3-1000-446f-af98-efa08924d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613762437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3613762437
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.543912252
Short name T421
Test name
Test status
Simulation time 54712594 ps
CPU time 1.24 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:12 PM PDT 24
Peak memory 216228 kb
Host smart-49459358-88c0-48bd-92d7-a4d2b36fb634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543912252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.543912252
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2555926790
Short name T93
Test name
Test status
Simulation time 37538805 ps
CPU time 0.9 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 218880 kb
Host smart-308ffa6c-49b2-454c-90c2-96632db51ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555926790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2555926790
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1680602100
Short name T533
Test name
Test status
Simulation time 81302253 ps
CPU time 1.45 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 217804 kb
Host smart-1884549c-57be-43b7-aab9-fd741a554cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680602100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1680602100
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.292058178
Short name T525
Test name
Test status
Simulation time 41173308 ps
CPU time 0.78 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:12 PM PDT 24
Peak memory 217080 kb
Host smart-b209307b-1b35-4320-9a6c-41afb5255e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292058178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.292058178
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1620336542
Short name T355
Test name
Test status
Simulation time 65100600 ps
CPU time 1.32 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:12 PM PDT 24
Peak memory 217740 kb
Host smart-af6c4b47-e801-42a7-a67a-e19915777feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620336542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1620336542
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1083550085
Short name T178
Test name
Test status
Simulation time 23937935 ps
CPU time 0.92 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:12 PM PDT 24
Peak memory 217588 kb
Host smart-06393415-b8f9-4ba7-9d15-e242ace452f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083550085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1083550085
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.967520855
Short name T787
Test name
Test status
Simulation time 38400079 ps
CPU time 1.36 seconds
Started Apr 04 03:34:06 PM PDT 24
Finished Apr 04 03:34:07 PM PDT 24
Peak memory 217488 kb
Host smart-486b5b7a-07bd-4ef1-99f8-ac70c908ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967520855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.967520855
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_genbits.2435515021
Short name T631
Test name
Test status
Simulation time 75036782 ps
CPU time 1.08 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 218684 kb
Host smart-a9f6b3ff-c5ad-44f5-a004-011b8d48561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435515021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2435515021
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1787435575
Short name T424
Test name
Test status
Simulation time 23388546 ps
CPU time 0.97 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 217636 kb
Host smart-5c7bea63-8dcd-44b7-a0ff-7ea322b74aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787435575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1787435575
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3522614990
Short name T31
Test name
Test status
Simulation time 146639889 ps
CPU time 1.19 seconds
Started Apr 04 03:34:14 PM PDT 24
Finished Apr 04 03:34:15 PM PDT 24
Peak memory 216272 kb
Host smart-43ddab6a-7bd1-40db-b9b7-4f11d383825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522614990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3522614990
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3958102905
Short name T118
Test name
Test status
Simulation time 42100105 ps
CPU time 0.92 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:12 PM PDT 24
Peak memory 222724 kb
Host smart-4b8c4028-0505-4e7a-a263-f87ea31c44d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958102905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3958102905
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1900017091
Short name T290
Test name
Test status
Simulation time 95072899 ps
CPU time 1.22 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 218048 kb
Host smart-24d5e88e-a523-4d69-b30f-af0be0dde8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900017091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1900017091
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1884178278
Short name T401
Test name
Test status
Simulation time 19282521 ps
CPU time 1.06 seconds
Started Apr 04 03:34:15 PM PDT 24
Finished Apr 04 03:34:16 PM PDT 24
Peak memory 217808 kb
Host smart-26424ed4-46c3-4d9e-89df-6b6746ef4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884178278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1884178278
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.974464332
Short name T751
Test name
Test status
Simulation time 53271946 ps
CPU time 1.1 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 219000 kb
Host smart-8e094c0e-2302-41dd-9889-bfee03300cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974464332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.974464332
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1176631188
Short name T675
Test name
Test status
Simulation time 218796408 ps
CPU time 1.27 seconds
Started Apr 04 03:31:46 PM PDT 24
Finished Apr 04 03:31:47 PM PDT 24
Peak memory 215220 kb
Host smart-db709c68-6c6e-46c0-a397-31ec6271180c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176631188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1176631188
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2191869333
Short name T619
Test name
Test status
Simulation time 66220771 ps
CPU time 0.95 seconds
Started Apr 04 03:31:52 PM PDT 24
Finished Apr 04 03:31:54 PM PDT 24
Peak memory 205736 kb
Host smart-18dbe471-0282-44cc-b4c9-b8690431827b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191869333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2191869333
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3559641698
Short name T185
Test name
Test status
Simulation time 22883139 ps
CPU time 0.93 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 215636 kb
Host smart-0d098ff5-1501-4d2a-a66b-8e3132d4ffc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559641698 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3559641698
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.344079747
Short name T766
Test name
Test status
Simulation time 23760323 ps
CPU time 1.12 seconds
Started Apr 04 03:31:46 PM PDT 24
Finished Apr 04 03:31:47 PM PDT 24
Peak memory 219076 kb
Host smart-7e7d47d4-3f4a-4998-bbb2-43bf4632622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344079747 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.344079747
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3156318217
Short name T629
Test name
Test status
Simulation time 33033992 ps
CPU time 1.25 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:50 PM PDT 24
Peak memory 217256 kb
Host smart-47463020-df93-464d-b382-d4ba5ae8e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156318217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3156318217
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3954624305
Short name T454
Test name
Test status
Simulation time 52717709 ps
CPU time 0.87 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 214844 kb
Host smart-aa7db020-3563-44f0-98f3-293bac8d5b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954624305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3954624305
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.997905143
Short name T263
Test name
Test status
Simulation time 26209248 ps
CPU time 0.92 seconds
Started Apr 04 03:31:45 PM PDT 24
Finished Apr 04 03:31:46 PM PDT 24
Peak memory 206760 kb
Host smart-3afc1dcd-41aa-4f97-9fd6-8e766e43adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997905143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.997905143
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2070308852
Short name T299
Test name
Test status
Simulation time 19170797 ps
CPU time 1.01 seconds
Started Apr 04 03:31:45 PM PDT 24
Finished Apr 04 03:31:46 PM PDT 24
Peak memory 215036 kb
Host smart-b15c0d6f-9088-4795-b593-b4a8d2ebb622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070308852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2070308852
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3890813553
Short name T558
Test name
Test status
Simulation time 513016912 ps
CPU time 3.28 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:52 PM PDT 24
Peak memory 216208 kb
Host smart-a8ea8aae-c592-41dc-b9d9-c92765ccade7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890813553 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3890813553
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3214112683
Short name T603
Test name
Test status
Simulation time 83465041822 ps
CPU time 1839.32 seconds
Started Apr 04 03:31:42 PM PDT 24
Finished Apr 04 04:02:22 PM PDT 24
Peak memory 225140 kb
Host smart-f9a31e72-220f-4696-8a6b-85db260c15aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214112683 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3214112683
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4016484959
Short name T177
Test name
Test status
Simulation time 18444923 ps
CPU time 1.07 seconds
Started Apr 04 03:34:11 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 217712 kb
Host smart-ea92ee0f-d33b-4c34-befa-b3e6bb28c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016484959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4016484959
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3930045195
Short name T54
Test name
Test status
Simulation time 134855616 ps
CPU time 1.43 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:15 PM PDT 24
Peak memory 217964 kb
Host smart-6fa7bacc-5341-482c-8097-bf60e4adf8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930045195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3930045195
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3339805862
Short name T680
Test name
Test status
Simulation time 22807991 ps
CPU time 1.04 seconds
Started Apr 04 03:34:15 PM PDT 24
Finished Apr 04 03:34:16 PM PDT 24
Peak memory 230968 kb
Host smart-bcda80d9-877d-434b-abc7-bb5ca2bbea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339805862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3339805862
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.1839684706
Short name T5
Test name
Test status
Simulation time 23420931 ps
CPU time 0.89 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 217572 kb
Host smart-5ba29b1a-b3a5-4fc4-baff-98c74a1affdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839684706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1839684706
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.814952180
Short name T562
Test name
Test status
Simulation time 37075396 ps
CPU time 0.99 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 230804 kb
Host smart-46b9673c-3c56-4837-a9d5-865015f47fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814952180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.814952180
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2346009515
Short name T775
Test name
Test status
Simulation time 25503517 ps
CPU time 1.3 seconds
Started Apr 04 03:34:15 PM PDT 24
Finished Apr 04 03:34:16 PM PDT 24
Peak memory 216208 kb
Host smart-46745e1a-8af0-4681-9a0b-9c61a2288c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346009515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2346009515
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3948428464
Short name T700
Test name
Test status
Simulation time 68089856 ps
CPU time 1.03 seconds
Started Apr 04 03:34:15 PM PDT 24
Finished Apr 04 03:34:17 PM PDT 24
Peak memory 218524 kb
Host smart-0d88432e-8d2a-4994-b620-8f8ee38b4785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948428464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3948428464
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3690333035
Short name T354
Test name
Test status
Simulation time 25252552 ps
CPU time 1.17 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 216632 kb
Host smart-c213d22a-f9ab-4e03-85b8-936958df703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690333035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3690333035
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1927636396
Short name T543
Test name
Test status
Simulation time 35389735 ps
CPU time 0.84 seconds
Started Apr 04 03:34:16 PM PDT 24
Finished Apr 04 03:34:17 PM PDT 24
Peak memory 217372 kb
Host smart-419871d9-c969-47a7-9d0e-be5f6efc6902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927636396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1927636396
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.26680532
Short name T573
Test name
Test status
Simulation time 47791216 ps
CPU time 1.72 seconds
Started Apr 04 03:34:14 PM PDT 24
Finished Apr 04 03:34:16 PM PDT 24
Peak memory 217716 kb
Host smart-56d155ae-fd45-41cb-a976-a5a89fbe7259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26680532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.26680532
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2546164069
Short name T117
Test name
Test status
Simulation time 49599436 ps
CPU time 0.83 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:13 PM PDT 24
Peak memory 217316 kb
Host smart-cc866264-74db-4542-b8a4-85f7a4fef749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546164069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2546164069
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4034571860
Short name T721
Test name
Test status
Simulation time 133395368 ps
CPU time 1.38 seconds
Started Apr 04 03:34:12 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 217624 kb
Host smart-3fcd5329-492b-484d-87b7-7c037941cc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034571860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4034571860
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3899327771
Short name T394
Test name
Test status
Simulation time 82278448 ps
CPU time 1.03 seconds
Started Apr 04 03:34:10 PM PDT 24
Finished Apr 04 03:34:11 PM PDT 24
Peak memory 218728 kb
Host smart-2b80708d-3289-43fe-bfc3-c0830c0d6d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899327771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3899327771
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.242300248
Short name T602
Test name
Test status
Simulation time 34333294 ps
CPU time 1.34 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:14 PM PDT 24
Peak memory 217552 kb
Host smart-0d2d2d65-c210-4cc1-9431-c39e9be27e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242300248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.242300248
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.241993213
Short name T611
Test name
Test status
Simulation time 23544745 ps
CPU time 1.18 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 232144 kb
Host smart-b9398744-d579-4269-ae10-d4296f79c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241993213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.241993213
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1948612237
Short name T659
Test name
Test status
Simulation time 65282030 ps
CPU time 1.29 seconds
Started Apr 04 03:34:13 PM PDT 24
Finished Apr 04 03:34:15 PM PDT 24
Peak memory 217464 kb
Host smart-6c3440f0-b126-4ae4-9d55-a7ac2cea364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948612237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1948612237
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.4170112455
Short name T776
Test name
Test status
Simulation time 27311918 ps
CPU time 1.16 seconds
Started Apr 04 03:34:38 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216660 kb
Host smart-aff6c64b-b686-425b-94f7-056e2d123cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170112455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4170112455
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3666642304
Short name T56
Test name
Test status
Simulation time 128379406 ps
CPU time 1.17 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216412 kb
Host smart-12cadbff-4cd7-4356-966c-54f67b299c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666642304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3666642304
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2796426827
Short name T731
Test name
Test status
Simulation time 94739458 ps
CPU time 1.2 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:49 PM PDT 24
Peak memory 215252 kb
Host smart-a74b754d-f633-4918-991e-c6da136158c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796426827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2796426827
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2318258254
Short name T607
Test name
Test status
Simulation time 46818184 ps
CPU time 0.85 seconds
Started Apr 04 03:31:46 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 205716 kb
Host smart-2f6dea32-f662-45fd-96ba-d40e68600753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318258254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2318258254
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3496317455
Short name T157
Test name
Test status
Simulation time 29972998 ps
CPU time 0.83 seconds
Started Apr 04 03:31:48 PM PDT 24
Finished Apr 04 03:31:49 PM PDT 24
Peak memory 215480 kb
Host smart-cdb730b7-f5fe-42eb-950e-c0f925bf698c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496317455 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3496317455
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.3638162469
Short name T94
Test name
Test status
Simulation time 42105181 ps
CPU time 0.88 seconds
Started Apr 04 03:31:50 PM PDT 24
Finished Apr 04 03:31:52 PM PDT 24
Peak memory 217516 kb
Host smart-3561dac7-8d87-4c30-924b-dc17f0dcfe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638162469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3638162469
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1320391087
Short name T269
Test name
Test status
Simulation time 33824198 ps
CPU time 1.54 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:31:53 PM PDT 24
Peak memory 217528 kb
Host smart-7d48a54d-212c-4d5c-8fbf-cd0378550fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320391087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1320391087
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1616231810
Short name T442
Test name
Test status
Simulation time 28419574 ps
CPU time 1.1 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 223752 kb
Host smart-eab58ea3-e422-49bd-8561-d941ffc69485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616231810 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1616231810
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1424178659
Short name T256
Test name
Test status
Simulation time 35040468 ps
CPU time 0.93 seconds
Started Apr 04 03:31:45 PM PDT 24
Finished Apr 04 03:31:46 PM PDT 24
Peak memory 206776 kb
Host smart-926dbbb3-5b04-4066-a7f4-97731f92e8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424178659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1424178659
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1889670747
Short name T400
Test name
Test status
Simulation time 28801090 ps
CPU time 0.94 seconds
Started Apr 04 03:31:47 PM PDT 24
Finished Apr 04 03:31:48 PM PDT 24
Peak memory 214984 kb
Host smart-5fbf852a-8ee8-4267-aa0f-80d7a93da479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889670747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1889670747
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2424899510
Short name T488
Test name
Test status
Simulation time 553682530 ps
CPU time 2.07 seconds
Started Apr 04 03:31:49 PM PDT 24
Finished Apr 04 03:31:52 PM PDT 24
Peak memory 218832 kb
Host smart-2d58863e-0c92-4cb0-a7ba-c2b956f3102a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424899510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2424899510
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3919338449
Short name T195
Test name
Test status
Simulation time 150884330795 ps
CPU time 893.12 seconds
Started Apr 04 03:31:51 PM PDT 24
Finished Apr 04 03:46:45 PM PDT 24
Peak memory 220092 kb
Host smart-83abb539-a97a-4930-bfab-a819b9dad954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919338449 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3919338449
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1723135277
Short name T759
Test name
Test status
Simulation time 61131866 ps
CPU time 1.04 seconds
Started Apr 04 03:34:42 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 217720 kb
Host smart-049ceba5-f699-458d-b8f0-8c9341df53a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723135277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1723135277
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1930413124
Short name T362
Test name
Test status
Simulation time 66830730 ps
CPU time 1.16 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 218300 kb
Host smart-0498ec0b-ab86-4446-92af-b22bbbae63b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930413124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1930413124
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.195841514
Short name T67
Test name
Test status
Simulation time 28374414 ps
CPU time 0.92 seconds
Started Apr 04 03:34:38 PM PDT 24
Finished Apr 04 03:34:40 PM PDT 24
Peak memory 216388 kb
Host smart-fb37cca8-e95a-4b79-b11c-1ea0f24142af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195841514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.195841514
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.383916256
Short name T431
Test name
Test status
Simulation time 261652967 ps
CPU time 3.59 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 219188 kb
Host smart-c93bd3a7-d0f0-4e6f-b5fb-b6d1d0037a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383916256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.383916256
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.389665982
Short name T80
Test name
Test status
Simulation time 32478696 ps
CPU time 1.02 seconds
Started Apr 04 03:34:41 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 218828 kb
Host smart-aae22b5b-d8f2-4558-8413-7a1f4e2d3cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389665982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.389665982
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3165998394
Short name T831
Test name
Test status
Simulation time 101959869 ps
CPU time 1.15 seconds
Started Apr 04 03:34:42 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 218292 kb
Host smart-08943b49-99a2-4e56-b13d-35b100dc0613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165998394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3165998394
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3641658870
Short name T86
Test name
Test status
Simulation time 61135312 ps
CPU time 1.09 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 232084 kb
Host smart-f74334d0-2b44-43e9-9f9a-daef2d74d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641658870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3641658870
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3273755887
Short name T187
Test name
Test status
Simulation time 101862481 ps
CPU time 1.31 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216408 kb
Host smart-9851f029-93c2-4aae-8551-834c9654cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273755887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3273755887
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3679489873
Short name T794
Test name
Test status
Simulation time 46265029 ps
CPU time 0.94 seconds
Started Apr 04 03:34:41 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 217580 kb
Host smart-f05ad1c8-e139-43fb-b1c4-65894d02e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679489873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3679489873
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3632140090
Short name T25
Test name
Test status
Simulation time 58368837 ps
CPU time 1.47 seconds
Started Apr 04 03:34:41 PM PDT 24
Finished Apr 04 03:34:42 PM PDT 24
Peak memory 217600 kb
Host smart-a68f1ea0-a081-48bc-b026-977ae69dfe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632140090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3632140090
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3064227030
Short name T41
Test name
Test status
Simulation time 36666051 ps
CPU time 1.02 seconds
Started Apr 04 03:34:37 PM PDT 24
Finished Apr 04 03:34:40 PM PDT 24
Peak memory 229552 kb
Host smart-1c12ecbc-e902-4add-a643-a81d001558c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064227030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3064227030
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.453021404
Short name T733
Test name
Test status
Simulation time 80967163 ps
CPU time 1.36 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217500 kb
Host smart-68434e32-e7f8-4023-98fb-64e1713c88db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453021404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.453021404
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1527939706
Short name T509
Test name
Test status
Simulation time 18318002 ps
CPU time 1.02 seconds
Started Apr 04 03:34:42 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 217708 kb
Host smart-58d1eda5-76de-46ec-b9d1-6fabf644baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527939706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1527939706
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3222562654
Short name T339
Test name
Test status
Simulation time 39964516 ps
CPU time 1.16 seconds
Started Apr 04 03:34:40 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 216180 kb
Host smart-d9e94019-af94-4d5f-9c11-60d10383fc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222562654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3222562654
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3315028104
Short name T82
Test name
Test status
Simulation time 27812933 ps
CPU time 1.09 seconds
Started Apr 04 03:34:37 PM PDT 24
Finished Apr 04 03:34:40 PM PDT 24
Peak memory 229340 kb
Host smart-da5329fb-5954-4d1b-99b8-06b6ca7e3efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315028104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3315028104
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2479072723
Short name T696
Test name
Test status
Simulation time 47045378 ps
CPU time 1.25 seconds
Started Apr 04 03:34:42 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 218424 kb
Host smart-c1abc173-91b8-45dd-9ea9-915b394880d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479072723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2479072723
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.371539139
Short name T654
Test name
Test status
Simulation time 25875825 ps
CPU time 1.13 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 219148 kb
Host smart-aebec098-c017-45a6-af5b-ba534897987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371539139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.371539139
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.796373183
Short name T614
Test name
Test status
Simulation time 39174291 ps
CPU time 1.08 seconds
Started Apr 04 03:34:39 PM PDT 24
Finished Apr 04 03:34:41 PM PDT 24
Peak memory 217480 kb
Host smart-8958e997-f435-4948-a472-42f95d2c302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796373183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.796373183
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3230396238
Short name T769
Test name
Test status
Simulation time 27858030 ps
CPU time 0.93 seconds
Started Apr 04 03:34:42 PM PDT 24
Finished Apr 04 03:34:43 PM PDT 24
Peak memory 217496 kb
Host smart-7da6aa97-a04a-48ea-a87c-f8cfbd8c1e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230396238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3230396238
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1090989270
Short name T647
Test name
Test status
Simulation time 9880032156 ps
CPU time 105.41 seconds
Started Apr 04 03:34:41 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 219196 kb
Host smart-6b64f629-4aef-4152-898d-0afebca92354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090989270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1090989270
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%