Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.07 98.27 93.71 96.79 83.82 96.87 96.58 92.46


Total test records in report: 968
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T63 /workspace/coverage/default/88.edn_err.11039824 Apr 15 02:20:43 PM PDT 24 Apr 15 02:20:44 PM PDT 24 38505252 ps
T788 /workspace/coverage/default/41.edn_genbits.2264834612 Apr 15 02:19:57 PM PDT 24 Apr 15 02:19:59 PM PDT 24 40758588 ps
T286 /workspace/coverage/default/215.edn_genbits.1081037963 Apr 15 02:21:14 PM PDT 24 Apr 15 02:21:16 PM PDT 24 99697262 ps
T308 /workspace/coverage/default/41.edn_alert.3860598750 Apr 15 02:19:58 PM PDT 24 Apr 15 02:19:59 PM PDT 24 172229449 ps
T789 /workspace/coverage/default/49.edn_disable.1632990994 Apr 15 02:20:21 PM PDT 24 Apr 15 02:20:22 PM PDT 24 11447604 ps
T790 /workspace/coverage/default/152.edn_genbits.4135167388 Apr 15 02:20:59 PM PDT 24 Apr 15 02:21:03 PM PDT 24 174079080 ps
T791 /workspace/coverage/default/9.edn_smoke.2987250004 Apr 15 02:17:00 PM PDT 24 Apr 15 02:17:02 PM PDT 24 41724065 ps
T792 /workspace/coverage/default/28.edn_stress_all.4198907650 Apr 15 02:19:20 PM PDT 24 Apr 15 02:19:23 PM PDT 24 1161992080 ps
T793 /workspace/coverage/default/158.edn_genbits.3679960479 Apr 15 02:21:00 PM PDT 24 Apr 15 02:21:02 PM PDT 24 31868259 ps
T794 /workspace/coverage/default/39.edn_genbits.1121456716 Apr 15 02:19:53 PM PDT 24 Apr 15 02:19:55 PM PDT 24 36382046 ps
T795 /workspace/coverage/default/34.edn_alert_test.3401094067 Apr 15 02:19:44 PM PDT 24 Apr 15 02:19:46 PM PDT 24 35824710 ps
T796 /workspace/coverage/default/103.edn_genbits.1502263956 Apr 15 02:20:52 PM PDT 24 Apr 15 02:20:54 PM PDT 24 67131949 ps
T797 /workspace/coverage/default/11.edn_stress_all.4193479576 Apr 15 02:17:23 PM PDT 24 Apr 15 02:17:29 PM PDT 24 803274032 ps
T798 /workspace/coverage/default/66.edn_genbits.2823302944 Apr 15 02:20:33 PM PDT 24 Apr 15 02:20:35 PM PDT 24 33919344 ps
T799 /workspace/coverage/default/123.edn_genbits.492897490 Apr 15 02:20:57 PM PDT 24 Apr 15 02:20:59 PM PDT 24 59662310 ps
T800 /workspace/coverage/default/1.edn_smoke.1133787168 Apr 15 02:15:01 PM PDT 24 Apr 15 02:15:03 PM PDT 24 16542940 ps
T801 /workspace/coverage/default/213.edn_genbits.521242984 Apr 15 02:21:14 PM PDT 24 Apr 15 02:21:16 PM PDT 24 29536542 ps
T128 /workspace/coverage/default/40.edn_intr.157795020 Apr 15 02:19:54 PM PDT 24 Apr 15 02:19:55 PM PDT 24 38158567 ps
T802 /workspace/coverage/default/204.edn_genbits.595855028 Apr 15 02:21:14 PM PDT 24 Apr 15 02:21:16 PM PDT 24 112720217 ps
T803 /workspace/coverage/default/5.edn_err.2472286047 Apr 15 02:16:18 PM PDT 24 Apr 15 02:16:19 PM PDT 24 22653135 ps
T804 /workspace/coverage/default/22.edn_alert_test.3720051429 Apr 15 02:18:58 PM PDT 24 Apr 15 02:18:59 PM PDT 24 21118220 ps
T805 /workspace/coverage/default/156.edn_genbits.1148527429 Apr 15 02:21:02 PM PDT 24 Apr 15 02:21:04 PM PDT 24 63914127 ps
T806 /workspace/coverage/default/35.edn_err.4282600137 Apr 15 02:19:46 PM PDT 24 Apr 15 02:19:47 PM PDT 24 126522808 ps
T807 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1518052258 Apr 15 02:19:14 PM PDT 24 Apr 15 02:22:37 PM PDT 24 15431994027 ps
T808 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3544140194 Apr 15 02:20:24 PM PDT 24 Apr 15 02:29:15 PM PDT 24 20666653725 ps
T809 /workspace/coverage/default/17.edn_disable.2515648117 Apr 15 02:18:16 PM PDT 24 Apr 15 02:18:17 PM PDT 24 36223619 ps
T810 /workspace/coverage/default/24.edn_alert_test.3227406191 Apr 15 02:19:05 PM PDT 24 Apr 15 02:19:07 PM PDT 24 42811773 ps
T811 /workspace/coverage/default/17.edn_intr.2155698439 Apr 15 02:18:16 PM PDT 24 Apr 15 02:18:18 PM PDT 24 33727945 ps
T812 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4036206468 Apr 15 02:18:50 PM PDT 24 Apr 15 03:09:55 PM PDT 24 388384701228 ps
T813 /workspace/coverage/default/162.edn_genbits.3139079096 Apr 15 02:21:06 PM PDT 24 Apr 15 02:21:08 PM PDT 24 27223677 ps
T161 /workspace/coverage/default/2.edn_disable.2099181178 Apr 15 02:15:35 PM PDT 24 Apr 15 02:15:36 PM PDT 24 12909078 ps
T814 /workspace/coverage/default/2.edn_alert_test.293359546 Apr 15 02:15:39 PM PDT 24 Apr 15 02:15:40 PM PDT 24 34673445 ps
T815 /workspace/coverage/default/35.edn_genbits.262763258 Apr 15 02:19:43 PM PDT 24 Apr 15 02:19:45 PM PDT 24 44214529 ps
T288 /workspace/coverage/default/134.edn_genbits.3850282210 Apr 15 02:21:01 PM PDT 24 Apr 15 02:21:04 PM PDT 24 56789976 ps
T816 /workspace/coverage/default/76.edn_genbits.1717710395 Apr 15 02:20:36 PM PDT 24 Apr 15 02:20:38 PM PDT 24 42418269 ps
T817 /workspace/coverage/default/13.edn_smoke.3205969216 Apr 15 02:17:37 PM PDT 24 Apr 15 02:17:38 PM PDT 24 23575623 ps
T818 /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1606932864 Apr 15 02:19:30 PM PDT 24 Apr 15 02:27:01 PM PDT 24 77324282011 ps
T819 /workspace/coverage/default/16.edn_alert_test.1808754525 Apr 15 02:18:10 PM PDT 24 Apr 15 02:18:11 PM PDT 24 22909707 ps
T820 /workspace/coverage/default/51.edn_genbits.2856621016 Apr 15 02:20:27 PM PDT 24 Apr 15 02:20:29 PM PDT 24 68646688 ps
T821 /workspace/coverage/default/10.edn_disable_auto_req_mode.1182485120 Apr 15 02:17:21 PM PDT 24 Apr 15 02:17:23 PM PDT 24 39979385 ps
T822 /workspace/coverage/default/181.edn_genbits.2735057529 Apr 15 02:21:06 PM PDT 24 Apr 15 02:21:07 PM PDT 24 112503582 ps
T823 /workspace/coverage/default/18.edn_intr.341314735 Apr 15 02:18:25 PM PDT 24 Apr 15 02:18:27 PM PDT 24 32326192 ps
T824 /workspace/coverage/default/7.edn_disable.3921592519 Apr 15 02:16:52 PM PDT 24 Apr 15 02:16:53 PM PDT 24 24390950 ps
T825 /workspace/coverage/default/2.edn_regwen.2393827328 Apr 15 02:15:18 PM PDT 24 Apr 15 02:15:19 PM PDT 24 128995550 ps
T826 /workspace/coverage/default/43.edn_alert.3292821502 Apr 15 02:20:02 PM PDT 24 Apr 15 02:20:04 PM PDT 24 217312206 ps
T827 /workspace/coverage/default/24.edn_smoke.3569061941 Apr 15 02:19:01 PM PDT 24 Apr 15 02:19:02 PM PDT 24 28048393 ps
T828 /workspace/coverage/default/286.edn_genbits.2812119074 Apr 15 02:21:33 PM PDT 24 Apr 15 02:21:35 PM PDT 24 47182075 ps
T829 /workspace/coverage/default/257.edn_genbits.3420447676 Apr 15 02:21:22 PM PDT 24 Apr 15 02:21:25 PM PDT 24 58833638 ps
T830 /workspace/coverage/default/153.edn_genbits.2339236476 Apr 15 02:21:00 PM PDT 24 Apr 15 02:21:03 PM PDT 24 38268870 ps
T831 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.110836744 Apr 15 02:19:14 PM PDT 24 Apr 15 02:40:10 PM PDT 24 108373104031 ps
T832 /workspace/coverage/default/6.edn_intr.3785026288 Apr 15 02:16:31 PM PDT 24 Apr 15 02:16:33 PM PDT 24 81109475 ps
T833 /workspace/coverage/default/0.edn_alert.3580761523 Apr 15 02:14:45 PM PDT 24 Apr 15 02:14:46 PM PDT 24 80684827 ps
T834 /workspace/coverage/default/44.edn_smoke.691778939 Apr 15 02:20:05 PM PDT 24 Apr 15 02:20:06 PM PDT 24 18620406 ps
T257 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1177255679 Apr 15 12:30:05 PM PDT 24 Apr 15 12:30:08 PM PDT 24 97194325 ps
T835 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3916891032 Apr 15 12:30:18 PM PDT 24 Apr 15 12:30:20 PM PDT 24 257399835 ps
T836 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1692338918 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:07 PM PDT 24 155028501 ps
T256 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1572774407 Apr 15 12:30:08 PM PDT 24 Apr 15 12:30:09 PM PDT 24 45882816 ps
T837 /workspace/coverage/cover_reg_top/0.edn_intr_test.94047909 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:26 PM PDT 24 23186929 ps
T258 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3527541538 Apr 15 12:30:14 PM PDT 24 Apr 15 12:30:16 PM PDT 24 154877783 ps
T838 /workspace/coverage/cover_reg_top/14.edn_tl_errors.968246371 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:31 PM PDT 24 129321126 ps
T229 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3949114608 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 65582875 ps
T839 /workspace/coverage/cover_reg_top/44.edn_intr_test.3432966244 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:34 PM PDT 24 32610203 ps
T230 /workspace/coverage/cover_reg_top/5.edn_csr_rw.129819307 Apr 15 12:30:22 PM PDT 24 Apr 15 12:30:24 PM PDT 24 14747726 ps
T259 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.897132439 Apr 15 12:30:08 PM PDT 24 Apr 15 12:30:11 PM PDT 24 120039016 ps
T840 /workspace/coverage/cover_reg_top/19.edn_tl_errors.7727738 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:37 PM PDT 24 66089420 ps
T841 /workspace/coverage/cover_reg_top/32.edn_intr_test.3138097972 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 28109335 ps
T248 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2304537635 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:30 PM PDT 24 142966442 ps
T842 /workspace/coverage/cover_reg_top/8.edn_intr_test.3515195654 Apr 15 12:30:13 PM PDT 24 Apr 15 12:30:14 PM PDT 24 17307445 ps
T843 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3254520564 Apr 15 12:30:12 PM PDT 24 Apr 15 12:30:14 PM PDT 24 75808755 ps
T844 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3830198809 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:05 PM PDT 24 27234690 ps
T845 /workspace/coverage/cover_reg_top/18.edn_intr_test.417549739 Apr 15 12:30:30 PM PDT 24 Apr 15 12:30:32 PM PDT 24 15811978 ps
T231 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.588307975 Apr 15 12:30:24 PM PDT 24 Apr 15 12:30:26 PM PDT 24 39917707 ps
T846 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1177617484 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:37 PM PDT 24 63534497 ps
T847 /workspace/coverage/cover_reg_top/23.edn_intr_test.3327739813 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:36 PM PDT 24 134514133 ps
T848 /workspace/coverage/cover_reg_top/12.edn_intr_test.3442331161 Apr 15 12:30:10 PM PDT 24 Apr 15 12:30:11 PM PDT 24 12996372 ps
T849 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3696576170 Apr 15 12:30:06 PM PDT 24 Apr 15 12:30:08 PM PDT 24 49114026 ps
T850 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1107553899 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:34 PM PDT 24 17919385 ps
T232 /workspace/coverage/cover_reg_top/16.edn_csr_rw.729993823 Apr 15 12:30:27 PM PDT 24 Apr 15 12:30:29 PM PDT 24 33943277 ps
T851 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2771751658 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:31 PM PDT 24 386286611 ps
T269 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3485091402 Apr 15 12:30:07 PM PDT 24 Apr 15 12:30:09 PM PDT 24 80404015 ps
T852 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1011865439 Apr 15 12:30:00 PM PDT 24 Apr 15 12:30:03 PM PDT 24 29495947 ps
T271 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3383716156 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:28 PM PDT 24 97624894 ps
T233 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1219023682 Apr 15 12:30:15 PM PDT 24 Apr 15 12:30:16 PM PDT 24 37125020 ps
T853 /workspace/coverage/cover_reg_top/34.edn_intr_test.1927174013 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 21319255 ps
T854 /workspace/coverage/cover_reg_top/11.edn_intr_test.1301749392 Apr 15 12:30:18 PM PDT 24 Apr 15 12:30:19 PM PDT 24 14789010 ps
T249 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1342119571 Apr 15 12:30:20 PM PDT 24 Apr 15 12:30:22 PM PDT 24 32218887 ps
T855 /workspace/coverage/cover_reg_top/9.edn_csr_rw.377398366 Apr 15 12:30:27 PM PDT 24 Apr 15 12:30:29 PM PDT 24 13501346 ps
T856 /workspace/coverage/cover_reg_top/13.edn_intr_test.400803277 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:35 PM PDT 24 25704197 ps
T234 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3430472897 Apr 15 12:30:02 PM PDT 24 Apr 15 12:30:04 PM PDT 24 20980662 ps
T857 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.24046146 Apr 15 12:30:20 PM PDT 24 Apr 15 12:30:26 PM PDT 24 694985362 ps
T250 /workspace/coverage/cover_reg_top/12.edn_csr_rw.490271057 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:34 PM PDT 24 20160822 ps
T858 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1876070379 Apr 15 12:30:30 PM PDT 24 Apr 15 12:30:32 PM PDT 24 23759640 ps
T859 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2909866962 Apr 15 12:30:05 PM PDT 24 Apr 15 12:30:06 PM PDT 24 57803049 ps
T860 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.317178095 Apr 15 12:30:16 PM PDT 24 Apr 15 12:30:19 PM PDT 24 181908001 ps
T235 /workspace/coverage/cover_reg_top/17.edn_csr_rw.4028477051 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:37 PM PDT 24 38440303 ps
T861 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3655138892 Apr 15 12:30:23 PM PDT 24 Apr 15 12:30:27 PM PDT 24 496666203 ps
T862 /workspace/coverage/cover_reg_top/38.edn_intr_test.2668132993 Apr 15 12:30:40 PM PDT 24 Apr 15 12:30:41 PM PDT 24 29925266 ps
T236 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1918219447 Apr 15 12:30:09 PM PDT 24 Apr 15 12:30:10 PM PDT 24 25208806 ps
T251 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.124446605 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:36 PM PDT 24 66734812 ps
T863 /workspace/coverage/cover_reg_top/15.edn_tl_errors.734805882 Apr 15 12:30:27 PM PDT 24 Apr 15 12:30:31 PM PDT 24 68792007 ps
T864 /workspace/coverage/cover_reg_top/14.edn_intr_test.87156413 Apr 15 12:30:20 PM PDT 24 Apr 15 12:30:22 PM PDT 24 23139041 ps
T865 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.843050472 Apr 15 12:30:10 PM PDT 24 Apr 15 12:30:13 PM PDT 24 74783630 ps
T270 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2983721473 Apr 15 12:30:02 PM PDT 24 Apr 15 12:30:05 PM PDT 24 134287106 ps
T866 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.538752228 Apr 15 12:30:04 PM PDT 24 Apr 15 12:30:10 PM PDT 24 347057131 ps
T867 /workspace/coverage/cover_reg_top/39.edn_intr_test.819678164 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 51105383 ps
T868 /workspace/coverage/cover_reg_top/11.edn_tl_errors.834835455 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:32 PM PDT 24 148311205 ps
T237 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2982827378 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:37 PM PDT 24 13480877 ps
T869 /workspace/coverage/cover_reg_top/24.edn_intr_test.3252512169 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:36 PM PDT 24 32728159 ps
T238 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2885242710 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:05 PM PDT 24 19124385 ps
T239 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2211306568 Apr 15 12:30:08 PM PDT 24 Apr 15 12:30:10 PM PDT 24 41583115 ps
T870 /workspace/coverage/cover_reg_top/36.edn_intr_test.1575324849 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:36 PM PDT 24 57427621 ps
T871 /workspace/coverage/cover_reg_top/33.edn_intr_test.3932723017 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 15765267 ps
T872 /workspace/coverage/cover_reg_top/19.edn_intr_test.2030698980 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:37 PM PDT 24 17700200 ps
T873 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2244882123 Apr 15 12:30:36 PM PDT 24 Apr 15 12:30:38 PM PDT 24 13775253 ps
T874 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2690248124 Apr 15 12:30:06 PM PDT 24 Apr 15 12:30:14 PM PDT 24 318284968 ps
T875 /workspace/coverage/cover_reg_top/22.edn_intr_test.3840028120 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:30 PM PDT 24 24677442 ps
T876 /workspace/coverage/cover_reg_top/26.edn_intr_test.3073010319 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:30 PM PDT 24 11915705 ps
T877 /workspace/coverage/cover_reg_top/1.edn_csr_rw.400052960 Apr 15 12:30:01 PM PDT 24 Apr 15 12:30:03 PM PDT 24 30629616 ps
T878 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1629386668 Apr 15 12:30:24 PM PDT 24 Apr 15 12:30:26 PM PDT 24 149140775 ps
T879 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2512141002 Apr 15 12:30:01 PM PDT 24 Apr 15 12:30:03 PM PDT 24 43762993 ps
T880 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4294149830 Apr 15 12:30:11 PM PDT 24 Apr 15 12:30:12 PM PDT 24 44424361 ps
T240 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2481959479 Apr 15 12:30:02 PM PDT 24 Apr 15 12:30:03 PM PDT 24 81529333 ps
T881 /workspace/coverage/cover_reg_top/4.edn_tl_errors.867207511 Apr 15 12:30:07 PM PDT 24 Apr 15 12:30:09 PM PDT 24 32571379 ps
T882 /workspace/coverage/cover_reg_top/40.edn_intr_test.37183852 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:37 PM PDT 24 35963143 ps
T241 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1515242999 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:29 PM PDT 24 15492490 ps
T883 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3391535433 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 26809053 ps
T884 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.310876135 Apr 15 12:30:06 PM PDT 24 Apr 15 12:30:08 PM PDT 24 33617173 ps
T885 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3236715185 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:27 PM PDT 24 47401094 ps
T886 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2516463413 Apr 15 12:30:23 PM PDT 24 Apr 15 12:30:25 PM PDT 24 35197441 ps
T887 /workspace/coverage/cover_reg_top/43.edn_intr_test.881678262 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:40 PM PDT 24 39377611 ps
T888 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3040710158 Apr 15 12:30:19 PM PDT 24 Apr 15 12:30:21 PM PDT 24 15936037 ps
T889 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.420968434 Apr 15 12:30:01 PM PDT 24 Apr 15 12:30:03 PM PDT 24 62671102 ps
T890 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1113243298 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 27210620 ps
T891 /workspace/coverage/cover_reg_top/3.edn_intr_test.2961333489 Apr 15 12:30:09 PM PDT 24 Apr 15 12:30:10 PM PDT 24 48845666 ps
T892 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2609210436 Apr 15 12:30:16 PM PDT 24 Apr 15 12:30:18 PM PDT 24 77585287 ps
T893 /workspace/coverage/cover_reg_top/7.edn_tl_errors.505233695 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:29 PM PDT 24 102775239 ps
T894 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4032076282 Apr 15 12:30:08 PM PDT 24 Apr 15 12:30:10 PM PDT 24 25458503 ps
T242 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2618950606 Apr 15 12:30:00 PM PDT 24 Apr 15 12:30:02 PM PDT 24 16873135 ps
T895 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3473602942 Apr 15 12:30:24 PM PDT 24 Apr 15 12:30:26 PM PDT 24 78395701 ps
T896 /workspace/coverage/cover_reg_top/7.edn_intr_test.4054183730 Apr 15 12:30:20 PM PDT 24 Apr 15 12:30:21 PM PDT 24 42226276 ps
T897 /workspace/coverage/cover_reg_top/4.edn_intr_test.3961575740 Apr 15 12:30:11 PM PDT 24 Apr 15 12:30:13 PM PDT 24 58295024 ps
T898 /workspace/coverage/cover_reg_top/16.edn_intr_test.1226300406 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:27 PM PDT 24 22829767 ps
T899 /workspace/coverage/cover_reg_top/45.edn_intr_test.1965996636 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:37 PM PDT 24 21942944 ps
T900 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2103094492 Apr 15 12:30:16 PM PDT 24 Apr 15 12:30:17 PM PDT 24 16697148 ps
T901 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.419408790 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:29 PM PDT 24 34544257 ps
T243 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4232369302 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:04 PM PDT 24 56206274 ps
T902 /workspace/coverage/cover_reg_top/21.edn_intr_test.2664041414 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:30 PM PDT 24 13804465 ps
T903 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3916133157 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:30 PM PDT 24 16985841 ps
T904 /workspace/coverage/cover_reg_top/35.edn_intr_test.1928618369 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 19658631 ps
T905 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2898189802 Apr 15 12:30:27 PM PDT 24 Apr 15 12:30:30 PM PDT 24 107700268 ps
T906 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1129997873 Apr 15 12:30:06 PM PDT 24 Apr 15 12:30:10 PM PDT 24 167604936 ps
T272 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1713914262 Apr 15 12:30:10 PM PDT 24 Apr 15 12:30:21 PM PDT 24 686074052 ps
T907 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2891408470 Apr 15 12:30:27 PM PDT 24 Apr 15 12:30:30 PM PDT 24 80756262 ps
T908 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2743776683 Apr 15 12:30:12 PM PDT 24 Apr 15 12:30:14 PM PDT 24 55204859 ps
T909 /workspace/coverage/cover_reg_top/47.edn_intr_test.3425692085 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 100965741 ps
T910 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.441035262 Apr 15 12:30:15 PM PDT 24 Apr 15 12:30:17 PM PDT 24 61781772 ps
T911 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1372987719 Apr 15 12:30:02 PM PDT 24 Apr 15 12:30:04 PM PDT 24 44600363 ps
T912 /workspace/coverage/cover_reg_top/10.edn_intr_test.1519329615 Apr 15 12:30:24 PM PDT 24 Apr 15 12:30:25 PM PDT 24 26435698 ps
T913 /workspace/coverage/cover_reg_top/9.edn_intr_test.369545013 Apr 15 12:30:07 PM PDT 24 Apr 15 12:30:08 PM PDT 24 17081172 ps
T914 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1154661378 Apr 15 12:30:04 PM PDT 24 Apr 15 12:30:07 PM PDT 24 42826887 ps
T915 /workspace/coverage/cover_reg_top/48.edn_intr_test.3346625956 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:30 PM PDT 24 27323576 ps
T916 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3325374768 Apr 15 12:30:19 PM PDT 24 Apr 15 12:30:21 PM PDT 24 243904771 ps
T917 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1042291341 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 57188584 ps
T918 /workspace/coverage/cover_reg_top/0.edn_tl_errors.399447144 Apr 15 12:30:09 PM PDT 24 Apr 15 12:30:14 PM PDT 24 555397376 ps
T919 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1458750084 Apr 15 12:30:13 PM PDT 24 Apr 15 12:30:14 PM PDT 24 13074910 ps
T920 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2604864693 Apr 15 12:30:17 PM PDT 24 Apr 15 12:30:19 PM PDT 24 86259904 ps
T921 /workspace/coverage/cover_reg_top/46.edn_intr_test.1162182117 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:36 PM PDT 24 16036135 ps
T922 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3183168524 Apr 15 12:30:14 PM PDT 24 Apr 15 12:30:16 PM PDT 24 62703072 ps
T923 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4099694763 Apr 15 12:30:10 PM PDT 24 Apr 15 12:30:11 PM PDT 24 137920689 ps
T924 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3992737347 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 83697172 ps
T925 /workspace/coverage/cover_reg_top/37.edn_intr_test.533476158 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:26 PM PDT 24 29824334 ps
T926 /workspace/coverage/cover_reg_top/30.edn_intr_test.2586267572 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:31 PM PDT 24 16426176 ps
T927 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4134878331 Apr 15 12:30:06 PM PDT 24 Apr 15 12:30:09 PM PDT 24 226539384 ps
T928 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2217441532 Apr 15 12:30:30 PM PDT 24 Apr 15 12:30:32 PM PDT 24 102318494 ps
T929 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3592463913 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:34 PM PDT 24 24431072 ps
T930 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1052842249 Apr 15 12:30:23 PM PDT 24 Apr 15 12:30:25 PM PDT 24 58961282 ps
T931 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2797939604 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:08 PM PDT 24 419280730 ps
T244 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.257186354 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:06 PM PDT 24 135863727 ps
T932 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1442289569 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:35 PM PDT 24 175355311 ps
T933 /workspace/coverage/cover_reg_top/5.edn_intr_test.1332375179 Apr 15 12:30:22 PM PDT 24 Apr 15 12:30:23 PM PDT 24 35365936 ps
T934 /workspace/coverage/cover_reg_top/15.edn_intr_test.3955212691 Apr 15 12:30:14 PM PDT 24 Apr 15 12:30:16 PM PDT 24 15335325 ps
T935 /workspace/coverage/cover_reg_top/2.edn_intr_test.1059107911 Apr 15 12:30:06 PM PDT 24 Apr 15 12:30:07 PM PDT 24 12700472 ps
T936 /workspace/coverage/cover_reg_top/11.edn_csr_rw.53210140 Apr 15 12:30:23 PM PDT 24 Apr 15 12:30:25 PM PDT 24 20989114 ps
T937 /workspace/coverage/cover_reg_top/42.edn_intr_test.4238395099 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 46082827 ps
T938 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2854773657 Apr 15 12:30:13 PM PDT 24 Apr 15 12:30:16 PM PDT 24 113643998 ps
T939 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2122556312 Apr 15 12:30:09 PM PDT 24 Apr 15 12:30:13 PM PDT 24 569801707 ps
T940 /workspace/coverage/cover_reg_top/25.edn_intr_test.1286018199 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 14619154 ps
T941 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.525612959 Apr 15 12:30:05 PM PDT 24 Apr 15 12:30:09 PM PDT 24 58835509 ps
T245 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1343834204 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:27 PM PDT 24 46717140 ps
T246 /workspace/coverage/cover_reg_top/4.edn_csr_rw.91186984 Apr 15 12:30:09 PM PDT 24 Apr 15 12:30:10 PM PDT 24 29839056 ps
T942 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3000071926 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:35 PM PDT 24 114617623 ps
T943 /workspace/coverage/cover_reg_top/2.edn_csr_rw.396987826 Apr 15 12:30:03 PM PDT 24 Apr 15 12:30:04 PM PDT 24 33704366 ps
T944 /workspace/coverage/cover_reg_top/31.edn_intr_test.3380277331 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:28 PM PDT 24 76319149 ps
T945 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3684550639 Apr 15 12:30:08 PM PDT 24 Apr 15 12:30:09 PM PDT 24 24882151 ps
T946 /workspace/coverage/cover_reg_top/29.edn_intr_test.306202752 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 43718360 ps
T947 /workspace/coverage/cover_reg_top/8.edn_tl_errors.218848393 Apr 15 12:30:07 PM PDT 24 Apr 15 12:30:10 PM PDT 24 203497442 ps
T948 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3550803456 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:34 PM PDT 24 898757498 ps
T949 /workspace/coverage/cover_reg_top/28.edn_intr_test.897567747 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:35 PM PDT 24 39486790 ps
T950 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3452039523 Apr 15 12:30:07 PM PDT 24 Apr 15 12:30:09 PM PDT 24 61074939 ps
T951 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3692851935 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:29 PM PDT 24 42145916 ps
T952 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3096327727 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:36 PM PDT 24 135491431 ps
T953 /workspace/coverage/cover_reg_top/6.edn_tl_errors.927005207 Apr 15 12:30:08 PM PDT 24 Apr 15 12:30:11 PM PDT 24 36652458 ps
T954 /workspace/coverage/cover_reg_top/1.edn_intr_test.187455721 Apr 15 12:30:04 PM PDT 24 Apr 15 12:30:06 PM PDT 24 58402432 ps
T955 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.799359780 Apr 15 12:30:26 PM PDT 24 Apr 15 12:30:30 PM PDT 24 616214140 ps
T956 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2657167993 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:36 PM PDT 24 296362881 ps
T957 /workspace/coverage/cover_reg_top/49.edn_intr_test.3141550181 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:35 PM PDT 24 43651209 ps
T958 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3276521084 Apr 15 12:30:23 PM PDT 24 Apr 15 12:30:26 PM PDT 24 414014596 ps
T959 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2104794823 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:33 PM PDT 24 222833134 ps
T960 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.970278371 Apr 15 12:30:02 PM PDT 24 Apr 15 12:30:04 PM PDT 24 200139665 ps
T961 /workspace/coverage/cover_reg_top/41.edn_intr_test.2981135758 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:37 PM PDT 24 238439104 ps
T962 /workspace/coverage/cover_reg_top/20.edn_intr_test.850945841 Apr 15 12:30:30 PM PDT 24 Apr 15 12:30:32 PM PDT 24 16285976 ps
T963 /workspace/coverage/cover_reg_top/27.edn_intr_test.3994997494 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:36 PM PDT 24 22381180 ps
T964 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2771027293 Apr 15 12:30:30 PM PDT 24 Apr 15 12:30:32 PM PDT 24 13868129 ps
T247 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2144109395 Apr 15 12:30:25 PM PDT 24 Apr 15 12:30:27 PM PDT 24 31200986 ps
T965 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1161481503 Apr 15 12:30:22 PM PDT 24 Apr 15 12:30:24 PM PDT 24 16597902 ps
T966 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1235659576 Apr 15 12:30:27 PM PDT 24 Apr 15 12:30:29 PM PDT 24 18932830 ps
T967 /workspace/coverage/cover_reg_top/6.edn_intr_test.3919138218 Apr 15 12:30:16 PM PDT 24 Apr 15 12:30:18 PM PDT 24 46669330 ps
T968 /workspace/coverage/cover_reg_top/17.edn_intr_test.537168292 Apr 15 12:30:31 PM PDT 24 Apr 15 12:30:33 PM PDT 24 79179286 ps

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.87696712
Short name T8
Test name
Test status
Simulation time 127348540 ps
CPU time 1.09 seconds
Started Apr 15 02:19:51 PM PDT 24
Finished Apr 15 02:19:53 PM PDT 24
Peak memory 216128 kb
Host smart-b1baf7ec-23d7-4baa-a667-ea8f13485cfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87696712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_dis
able_auto_req_mode.87696712
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/121.edn_genbits.3553809605
Short name T22
Test name
Test status
Simulation time 109216628 ps
CPU time 1.19 seconds
Started Apr 15 02:21:02 PM PDT 24
Finished Apr 15 02:21:04 PM PDT 24
Peak memory 216360 kb
Host smart-e12aa314-2291-4d24-a756-5c3ddff77d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553809605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3553809605
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3250891791
Short name T5
Test name
Test status
Simulation time 1204277606 ps
CPU time 3.58 seconds
Started Apr 15 02:15:48 PM PDT 24
Finished Apr 15 02:15:53 PM PDT 24
Peak memory 234180 kb
Host smart-c32ef2a8-8005-405b-b44f-5d14e91b16cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250891791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3250891791
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/40.edn_alert.359070631
Short name T16
Test name
Test status
Simulation time 72543408 ps
CPU time 1.13 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:19:54 PM PDT 24
Peak memory 215384 kb
Host smart-25dbdc06-7339-407f-afc1-dcf41618e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359070631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.359070631
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3889260653
Short name T23
Test name
Test status
Simulation time 38947253468 ps
CPU time 850.96 seconds
Started Apr 15 02:16:01 PM PDT 24
Finished Apr 15 02:30:13 PM PDT 24
Peak memory 217848 kb
Host smart-456a7579-1d6b-43d1-806b-fc2577c0b669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889260653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3889260653
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_genbits.2417893840
Short name T35
Test name
Test status
Simulation time 190101003 ps
CPU time 1.42 seconds
Started Apr 15 02:20:05 PM PDT 24
Finished Apr 15 02:20:07 PM PDT 24
Peak memory 216516 kb
Host smart-c2d40de0-33a0-45bf-a3d9-9f826b81bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417893840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2417893840
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_stress_all.2292992028
Short name T41
Test name
Test status
Simulation time 498684736 ps
CPU time 4.92 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 219108 kb
Host smart-6e924a79-b74d-4aaf-aec3-2a9f130e322d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292992028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2292992028
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1928559342
Short name T52
Test name
Test status
Simulation time 3108293897 ps
CPU time 5.82 seconds
Started Apr 15 02:15:18 PM PDT 24
Finished Apr 15 02:15:25 PM PDT 24
Peak memory 236232 kb
Host smart-6009cf08-12e5-4d10-b10f-780cf8e7f06b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928559342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1928559342
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/176.edn_genbits.789862351
Short name T123
Test name
Test status
Simulation time 33917779 ps
CPU time 1.24 seconds
Started Apr 15 02:21:04 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 218268 kb
Host smart-eedb5790-efdb-4b75-a1f7-0932b1373054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789862351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.789862351
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.473867900
Short name T26
Test name
Test status
Simulation time 16304734 ps
CPU time 0.94 seconds
Started Apr 15 02:15:39 PM PDT 24
Finished Apr 15 02:15:40 PM PDT 24
Peak memory 206616 kb
Host smart-e0447e0b-1b9d-4852-b7e6-753d52c3db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473867900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.473867900
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/32.edn_alert.1776375655
Short name T65
Test name
Test status
Simulation time 26019896 ps
CPU time 1.25 seconds
Started Apr 15 02:19:36 PM PDT 24
Finished Apr 15 02:19:37 PM PDT 24
Peak memory 215220 kb
Host smart-703573b2-141d-4b59-901b-80edb1a52366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776375655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1776375655
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert.1412988140
Short name T101
Test name
Test status
Simulation time 220311097 ps
CPU time 1.07 seconds
Started Apr 15 02:17:08 PM PDT 24
Finished Apr 15 02:17:10 PM PDT 24
Peak memory 215288 kb
Host smart-6df0c117-c1d6-41a8-b4ff-4f41eb9b5ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412988140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1412988140
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/29.edn_intr.1641320581
Short name T44
Test name
Test status
Simulation time 54649896 ps
CPU time 0.83 seconds
Started Apr 15 02:19:22 PM PDT 24
Finished Apr 15 02:19:23 PM PDT 24
Peak memory 215264 kb
Host smart-5127fcd7-7d16-4154-8120-216cb0a88b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641320581 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1641320581
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2983721473
Short name T270
Test name
Test status
Simulation time 134287106 ps
CPU time 2.22 seconds
Started Apr 15 12:30:02 PM PDT 24
Finished Apr 15 12:30:05 PM PDT 24
Peak memory 206276 kb
Host smart-e25fe1a5-2280-4cb3-b5ca-54e052de0532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983721473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2983721473
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/16.edn_disable.2204597220
Short name T61
Test name
Test status
Simulation time 90945435 ps
CPU time 0.77 seconds
Started Apr 15 02:18:07 PM PDT 24
Finished Apr 15 02:18:08 PM PDT 24
Peak memory 215492 kb
Host smart-4a95b0d9-f3e5-4d98-bc82-f0cb7643eb9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204597220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2204597220
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2470602800
Short name T208
Test name
Test status
Simulation time 30806200088 ps
CPU time 684.91 seconds
Started Apr 15 02:20:15 PM PDT 24
Finished Apr 15 02:31:40 PM PDT 24
Peak memory 221364 kb
Host smart-a004015e-30d3-4725-9b05-77126807c56f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470602800 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2470602800
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.129819307
Short name T230
Test name
Test status
Simulation time 14747726 ps
CPU time 1 seconds
Started Apr 15 12:30:22 PM PDT 24
Finished Apr 15 12:30:24 PM PDT 24
Peak memory 205992 kb
Host smart-d7d5a449-ee93-4bae-bb37-dddd81ea3554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129819307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.129819307
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/default/281.edn_genbits.169997600
Short name T62
Test name
Test status
Simulation time 173232448 ps
CPU time 1.41 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 217716 kb
Host smart-5f3a0452-b749-4c0b-8aba-c1b1de5b4750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169997600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.169997600
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_alert.2861898948
Short name T39
Test name
Test status
Simulation time 25061796 ps
CPU time 1.17 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:00 PM PDT 24
Peak memory 215388 kb
Host smart-4331ac73-d3d0-4711-bd1c-21e3815b8a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861898948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2861898948
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2901700110
Short name T169
Test name
Test status
Simulation time 62799489 ps
CPU time 1.2 seconds
Started Apr 15 02:19:19 PM PDT 24
Finished Apr 15 02:19:21 PM PDT 24
Peak memory 216024 kb
Host smart-20cedce3-42ee-42f0-8aa7-57d94f9e2fd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901700110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2901700110
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_disable.2348551628
Short name T673
Test name
Test status
Simulation time 29117871 ps
CPU time 0.84 seconds
Started Apr 15 02:20:03 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 215516 kb
Host smart-f320447d-9e82-4823-8c8f-efc94da8660b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348551628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2348551628
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.2036579853
Short name T108
Test name
Test status
Simulation time 35666792 ps
CPU time 0.79 seconds
Started Apr 15 02:17:45 PM PDT 24
Finished Apr 15 02:17:46 PM PDT 24
Peak memory 215472 kb
Host smart-4bfbd762-e4de-49e7-8724-e03dd2fa7d5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036579853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2036579853
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.2592617931
Short name T28
Test name
Test status
Simulation time 16185828 ps
CPU time 0.78 seconds
Started Apr 15 02:18:32 PM PDT 24
Finished Apr 15 02:18:33 PM PDT 24
Peak memory 215568 kb
Host smart-526a77f2-43a7-41be-9711-52c2ca7c0059
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592617931 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2592617931
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/28.edn_intr.394729491
Short name T127
Test name
Test status
Simulation time 46715297 ps
CPU time 0.78 seconds
Started Apr 15 02:19:18 PM PDT 24
Finished Apr 15 02:19:19 PM PDT 24
Peak memory 215236 kb
Host smart-f68c4fd7-67ad-47fd-b0f1-fb203ea6c67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394729491 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.394729491
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3459690969
Short name T78
Test name
Test status
Simulation time 167419895 ps
CPU time 1.1 seconds
Started Apr 15 02:19:40 PM PDT 24
Finished Apr 15 02:19:42 PM PDT 24
Peak memory 217748 kb
Host smart-88e90055-eb42-4026-8d8d-a0c84c5dfdb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459690969 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3459690969
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_stress_all.2437677821
Short name T43
Test name
Test status
Simulation time 316162832 ps
CPU time 3.38 seconds
Started Apr 15 02:18:05 PM PDT 24
Finished Apr 15 02:18:08 PM PDT 24
Peak memory 214928 kb
Host smart-da8695c8-72fa-4fcc-9f00-750221bdafbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437677821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2437677821
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.469383693
Short name T312
Test name
Test status
Simulation time 30812804 ps
CPU time 1.28 seconds
Started Apr 15 02:15:02 PM PDT 24
Finished Apr 15 02:15:04 PM PDT 24
Peak memory 215288 kb
Host smart-850e4f66-93ef-42bd-9310-c2bd2492c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469383693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.469383693
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/221.edn_genbits.3981425089
Short name T267
Test name
Test status
Simulation time 79555724 ps
CPU time 1.33 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 217932 kb
Host smart-e20b6c66-ea1c-45b3-abda-fcb4ac711150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981425089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3981425089
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.217128612
Short name T2
Test name
Test status
Simulation time 48199100 ps
CPU time 0.89 seconds
Started Apr 15 02:16:52 PM PDT 24
Finished Apr 15 02:16:53 PM PDT 24
Peak memory 206716 kb
Host smart-514ddbf7-0df0-427e-9811-c16484c6db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217128612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.217128612
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_disable.2515648117
Short name T809
Test name
Test status
Simulation time 36223619 ps
CPU time 0.82 seconds
Started Apr 15 02:18:16 PM PDT 24
Finished Apr 15 02:18:17 PM PDT 24
Peak memory 215004 kb
Host smart-e00d6913-f755-4f4b-97ac-e011d85e368f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515648117 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2515648117
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable.2634464121
Short name T165
Test name
Test status
Simulation time 34374690 ps
CPU time 0.86 seconds
Started Apr 15 02:19:50 PM PDT 24
Finished Apr 15 02:19:52 PM PDT 24
Peak memory 215668 kb
Host smart-9654c1f0-6e27-4104-8aff-0b65b933d572
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634464121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2634464121
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable.3990207955
Short name T118
Test name
Test status
Simulation time 12880923 ps
CPU time 0.89 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:24 PM PDT 24
Peak memory 215664 kb
Host smart-810772cf-ff38-4866-9e25-2d04021a4040
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990207955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3990207955
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.2159261576
Short name T113
Test name
Test status
Simulation time 36026382 ps
CPU time 0.82 seconds
Started Apr 15 02:17:22 PM PDT 24
Finished Apr 15 02:17:24 PM PDT 24
Peak memory 215404 kb
Host smart-8ed997d6-a973-43db-a2c0-4178e5cc80be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159261576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2159261576
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1550184163
Short name T91
Test name
Test status
Simulation time 108773911 ps
CPU time 1.05 seconds
Started Apr 15 02:18:17 PM PDT 24
Finished Apr 15 02:18:19 PM PDT 24
Peak memory 216084 kb
Host smart-d6deb46a-a173-412b-8371-d4133e8add40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550184163 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1550184163
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.2099181178
Short name T161
Test name
Test status
Simulation time 12909078 ps
CPU time 0.85 seconds
Started Apr 15 02:15:35 PM PDT 24
Finished Apr 15 02:15:36 PM PDT 24
Peak memory 215588 kb
Host smart-bf4610b9-922f-4001-8ce6-e4c208fba8e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099181178 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2099181178
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.462453033
Short name T151
Test name
Test status
Simulation time 17348704 ps
CPU time 0.88 seconds
Started Apr 15 02:19:07 PM PDT 24
Finished Apr 15 02:19:08 PM PDT 24
Peak memory 215760 kb
Host smart-b12840cc-4500-4a4d-a8a8-c1a9f720444f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462453033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.462453033
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.3435521217
Short name T174
Test name
Test status
Simulation time 15133449 ps
CPU time 0.91 seconds
Started Apr 15 02:19:27 PM PDT 24
Finished Apr 15 02:19:28 PM PDT 24
Peak memory 215620 kb
Host smart-b50b550d-9e97-480d-a3da-b9fc052d38c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435521217 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3435521217
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3931319337
Short name T176
Test name
Test status
Simulation time 29815486 ps
CPU time 1.26 seconds
Started Apr 15 02:19:51 PM PDT 24
Finished Apr 15 02:19:53 PM PDT 24
Peak memory 216152 kb
Host smart-3a4d6165-57c2-445a-95ba-d9f78b8320f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931319337 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3931319337
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2819603233
Short name T72
Test name
Test status
Simulation time 98243356 ps
CPU time 1.11 seconds
Started Apr 15 02:17:15 PM PDT 24
Finished Apr 15 02:17:17 PM PDT 24
Peak memory 215288 kb
Host smart-a0b68ae3-420f-4940-abc9-5615c672c616
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819603233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2819603233
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/151.edn_genbits.833691252
Short name T282
Test name
Test status
Simulation time 98027416 ps
CPU time 2.29 seconds
Started Apr 15 02:21:09 PM PDT 24
Finished Apr 15 02:21:11 PM PDT 24
Peak memory 219092 kb
Host smart-e9b109d5-399c-487d-8b8a-b6da88a4552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833691252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.833691252
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.430321351
Short name T334
Test name
Test status
Simulation time 15660403 ps
CPU time 0.9 seconds
Started Apr 15 02:17:25 PM PDT 24
Finished Apr 15 02:17:27 PM PDT 24
Peak memory 205708 kb
Host smart-3d2db54c-c743-4a7c-90a1-368e6d8244fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430321351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.430321351
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/293.edn_genbits.1294593387
Short name T9
Test name
Test status
Simulation time 120016745 ps
CPU time 1.37 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:36 PM PDT 24
Peak memory 218900 kb
Host smart-bd07c198-c9f1-4046-82aa-e7eb8341d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294593387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1294593387
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.671692779
Short name T185
Test name
Test status
Simulation time 43185489 ps
CPU time 1.14 seconds
Started Apr 15 02:21:01 PM PDT 24
Finished Apr 15 02:21:02 PM PDT 24
Peak memory 216356 kb
Host smart-05b17854-d643-4dfd-b9da-f2f9c24ee213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671692779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.671692779
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2703066558
Short name T195
Test name
Test status
Simulation time 41682667323 ps
CPU time 1097.86 seconds
Started Apr 15 02:15:01 PM PDT 24
Finished Apr 15 02:33:20 PM PDT 24
Peak memory 220248 kb
Host smart-af0bff79-5a23-4470-a6b9-3802942f6022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703066558 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2703066558
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_intr.3925705545
Short name T125
Test name
Test status
Simulation time 22435900 ps
CPU time 1.02 seconds
Started Apr 15 02:17:24 PM PDT 24
Finished Apr 15 02:17:25 PM PDT 24
Peak memory 215408 kb
Host smart-bf018d94-3e91-42a3-b381-78cb705b2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925705545 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3925705545
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/14.edn_stress_all.3445649050
Short name T42
Test name
Test status
Simulation time 279253367 ps
CPU time 1.29 seconds
Started Apr 15 02:17:49 PM PDT 24
Finished Apr 15 02:17:51 PM PDT 24
Peak memory 206640 kb
Host smart-0d38b4a2-5028-498c-9749-41c44cc8d94f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445649050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3445649050
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_err.1692613693
Short name T48
Test name
Test status
Simulation time 23371822 ps
CPU time 1.24 seconds
Started Apr 15 02:18:46 PM PDT 24
Finished Apr 15 02:18:48 PM PDT 24
Peak memory 231056 kb
Host smart-aee8a5d4-2f0f-442c-ad23-3b41295ad192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692613693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1692613693
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.490271057
Short name T250
Test name
Test status
Simulation time 20160822 ps
CPU time 0.84 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 206008 kb
Host smart-865bf294-c1cc-4780-b9ca-f291503f79a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490271057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.490271057
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_alert.3580761523
Short name T833
Test name
Test status
Simulation time 80684827 ps
CPU time 1.01 seconds
Started Apr 15 02:14:45 PM PDT 24
Finished Apr 15 02:14:46 PM PDT 24
Peak memory 215264 kb
Host smart-302cd043-f803-4f62-b9b4-68c35a32de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580761523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3580761523
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3673879666
Short name T290
Test name
Test status
Simulation time 125378179776 ps
CPU time 1665.73 seconds
Started Apr 15 02:14:43 PM PDT 24
Finished Apr 15 02:42:29 PM PDT 24
Peak memory 226292 kb
Host smart-dbe31af9-c087-4372-badf-717769b92bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673879666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3673879666
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.edn_genbits.4191982665
Short name T337
Test name
Test status
Simulation time 44968908 ps
CPU time 1.64 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217620 kb
Host smart-858020fa-c83d-4c1d-9a8e-9baf1b343289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191982665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4191982665
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3209906690
Short name T279
Test name
Test status
Simulation time 46200877 ps
CPU time 1.24 seconds
Started Apr 15 02:20:56 PM PDT 24
Finished Apr 15 02:20:58 PM PDT 24
Peak memory 217592 kb
Host smart-805b78c4-ac82-4d3b-b66b-aa555628c821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209906690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3209906690
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2624369570
Short name T102
Test name
Test status
Simulation time 25936856 ps
CPU time 1.12 seconds
Started Apr 15 02:17:40 PM PDT 24
Finished Apr 15 02:17:41 PM PDT 24
Peak memory 215260 kb
Host smart-d6b228ff-793f-4441-ac75-e2686261fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624369570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2624369570
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2924307379
Short name T293
Test name
Test status
Simulation time 62402700 ps
CPU time 1.34 seconds
Started Apr 15 02:20:58 PM PDT 24
Finished Apr 15 02:21:00 PM PDT 24
Peak memory 217444 kb
Host smart-58942d73-a1b7-4bcd-9785-47c5bbdb96a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924307379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2924307379
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3147989253
Short name T218
Test name
Test status
Simulation time 180062464 ps
CPU time 2.67 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:10 PM PDT 24
Peak memory 219112 kb
Host smart-c4ff822c-b117-4074-a126-a3405a36b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147989253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3147989253
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.560783110
Short name T266
Test name
Test status
Simulation time 25648169 ps
CPU time 1.21 seconds
Started Apr 15 02:18:23 PM PDT 24
Finished Apr 15 02:18:25 PM PDT 24
Peak memory 215292 kb
Host smart-4f19ca01-63b6-4903-b1e8-e1d507394e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560783110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.560783110
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.942164179
Short name T285
Test name
Test status
Simulation time 42926827 ps
CPU time 1.29 seconds
Started Apr 15 02:21:04 PM PDT 24
Finished Apr 15 02:21:06 PM PDT 24
Peak memory 217596 kb
Host smart-8f8c7596-f305-4905-bf6d-8c5eca2ad9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942164179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.942164179
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.655320293
Short name T31
Test name
Test status
Simulation time 62944530 ps
CPU time 1.95 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 217604 kb
Host smart-05b3f2b5-7ccf-4581-b631-effbe9211ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655320293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.655320293
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4154303311
Short name T300
Test name
Test status
Simulation time 151436110 ps
CPU time 3.1 seconds
Started Apr 15 02:21:25 PM PDT 24
Finished Apr 15 02:21:28 PM PDT 24
Peak memory 219112 kb
Host smart-c901da2e-d3e6-4bd4-ad79-f76064fc2980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154303311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4154303311
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.261679148
Short name T147
Test name
Test status
Simulation time 42657332 ps
CPU time 1.12 seconds
Started Apr 15 02:19:08 PM PDT 24
Finished Apr 15 02:19:10 PM PDT 24
Peak memory 215232 kb
Host smart-53a878cc-a8f7-43a3-8c80-3ad053e94915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261679148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.261679148
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_genbits.2771225167
Short name T274
Test name
Test status
Simulation time 50938896 ps
CPU time 1.5 seconds
Started Apr 15 02:19:04 PM PDT 24
Finished Apr 15 02:19:06 PM PDT 24
Peak memory 217604 kb
Host smart-99e35982-6521-4481-898d-4f5c52ee7b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771225167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2771225167
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_alert.2746951013
Short name T311
Test name
Test status
Simulation time 114349914 ps
CPU time 1.33 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:01 PM PDT 24
Peak memory 215308 kb
Host smart-84917646-ca15-4467-a46b-a12676cce16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746951013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2746951013
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert.3218962727
Short name T106
Test name
Test status
Simulation time 24944056 ps
CPU time 1.15 seconds
Started Apr 15 02:20:16 PM PDT 24
Finished Apr 15 02:20:17 PM PDT 24
Peak memory 215284 kb
Host smart-5f147465-e2f2-4473-8c54-46756d14555d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218962727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3218962727
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/17.edn_intr.2155698439
Short name T811
Test name
Test status
Simulation time 33727945 ps
CPU time 0.85 seconds
Started Apr 15 02:18:16 PM PDT 24
Finished Apr 15 02:18:18 PM PDT 24
Peak memory 215404 kb
Host smart-da8d08a8-b46d-4240-87be-c8ebdcde1f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155698439 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2155698439
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/53.edn_genbits.879840750
Short name T781
Test name
Test status
Simulation time 164406013 ps
CPU time 1.69 seconds
Started Apr 15 02:20:27 PM PDT 24
Finished Apr 15 02:20:29 PM PDT 24
Peak memory 216612 kb
Host smart-75ae69bf-8169-423a-8047-95a202af5615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879840750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.879840750
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2211306568
Short name T239
Test name
Test status
Simulation time 41583115 ps
CPU time 1.11 seconds
Started Apr 15 12:30:08 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 206112 kb
Host smart-92ab7e90-2c8e-4e61-9607-9722dda0d8c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211306568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2211306568
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.317178095
Short name T860
Test name
Test status
Simulation time 181908001 ps
CPU time 3.01 seconds
Started Apr 15 12:30:16 PM PDT 24
Finished Apr 15 12:30:19 PM PDT 24
Peak memory 206100 kb
Host smart-b964d5dd-3b9b-4e22-ae4e-2886e6fad85f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317178095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.317178095
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2885242710
Short name T238
Test name
Test status
Simulation time 19124385 ps
CPU time 0.97 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:05 PM PDT 24
Peak memory 205908 kb
Host smart-fa93c2b9-2332-41e0-95db-df48a7267b53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885242710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2885242710
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1011865439
Short name T852
Test name
Test status
Simulation time 29495947 ps
CPU time 1.4 seconds
Started Apr 15 12:30:00 PM PDT 24
Finished Apr 15 12:30:03 PM PDT 24
Peak memory 214280 kb
Host smart-d65ef9f5-04d1-4d94-b991-21d263b9a4f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011865439 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1011865439
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4232369302
Short name T243
Test name
Test status
Simulation time 56206274 ps
CPU time 0.86 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 205976 kb
Host smart-2f6cb247-6aac-4343-8573-d9c3cc3cc6f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232369302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4232369302
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.94047909
Short name T837
Test name
Test status
Simulation time 23186929 ps
CPU time 0.81 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 205880 kb
Host smart-cb88c6c1-997f-4e8e-8741-4cb20d96904b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94047909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.94047909
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1372987719
Short name T911
Test name
Test status
Simulation time 44600363 ps
CPU time 1.47 seconds
Started Apr 15 12:30:02 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 206104 kb
Host smart-e06962ed-cdc7-451e-90a0-3a9e38cd9e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372987719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1372987719
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.399447144
Short name T918
Test name
Test status
Simulation time 555397376 ps
CPU time 4.21 seconds
Started Apr 15 12:30:09 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 214304 kb
Host smart-cbebc0b8-c9ef-47d9-a676-8356c8a94468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399447144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.399447144
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1129997873
Short name T906
Test name
Test status
Simulation time 167604936 ps
CPU time 2.88 seconds
Started Apr 15 12:30:06 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 206060 kb
Host smart-0900774c-06cc-437f-a5a0-33ddc69cd297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129997873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1129997873
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2481959479
Short name T240
Test name
Test status
Simulation time 81529333 ps
CPU time 1 seconds
Started Apr 15 12:30:02 PM PDT 24
Finished Apr 15 12:30:03 PM PDT 24
Peak memory 206040 kb
Host smart-13fa5d42-5913-4b97-9220-bd9398771897
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481959479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2481959479
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.538752228
Short name T866
Test name
Test status
Simulation time 347057131 ps
CPU time 5.17 seconds
Started Apr 15 12:30:04 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 205908 kb
Host smart-27fddda1-2bb9-4ed5-8144-e3d527d87a79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538752228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.538752228
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.420968434
Short name T889
Test name
Test status
Simulation time 62671102 ps
CPU time 0.93 seconds
Started Apr 15 12:30:01 PM PDT 24
Finished Apr 15 12:30:03 PM PDT 24
Peak memory 205972 kb
Host smart-bc52a57a-9754-42b0-be2a-a0cdca085f3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420968434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.420968434
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.970278371
Short name T960
Test name
Test status
Simulation time 200139665 ps
CPU time 1.37 seconds
Started Apr 15 12:30:02 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 214296 kb
Host smart-5c3c9d9e-c7d4-4d66-af3b-591f4a6f6430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970278371 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.970278371
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.400052960
Short name T877
Test name
Test status
Simulation time 30629616 ps
CPU time 0.89 seconds
Started Apr 15 12:30:01 PM PDT 24
Finished Apr 15 12:30:03 PM PDT 24
Peak memory 205900 kb
Host smart-72b8d26e-cbad-4105-920f-eddcb6ee745e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400052960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.400052960
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.187455721
Short name T954
Test name
Test status
Simulation time 58402432 ps
CPU time 0.81 seconds
Started Apr 15 12:30:04 PM PDT 24
Finished Apr 15 12:30:06 PM PDT 24
Peak memory 205964 kb
Host smart-a99b7a0c-dc89-4994-a66b-3fba925bcf25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187455721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.187455721
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.441035262
Short name T910
Test name
Test status
Simulation time 61781772 ps
CPU time 1.31 seconds
Started Apr 15 12:30:15 PM PDT 24
Finished Apr 15 12:30:17 PM PDT 24
Peak memory 206152 kb
Host smart-b759d12d-de59-45de-ad23-9c23f74e24b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441035262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.441035262
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1154661378
Short name T914
Test name
Test status
Simulation time 42826887 ps
CPU time 2.77 seconds
Started Apr 15 12:30:04 PM PDT 24
Finished Apr 15 12:30:07 PM PDT 24
Peak memory 214332 kb
Host smart-c79fb9dd-3562-4958-916c-5162a4a0dc8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154661378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1154661378
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1107553899
Short name T850
Test name
Test status
Simulation time 17919385 ps
CPU time 1.18 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 214260 kb
Host smart-ed604e74-2768-467d-809a-e464c9345980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107553899 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1107553899
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1458750084
Short name T919
Test name
Test status
Simulation time 13074910 ps
CPU time 0.92 seconds
Started Apr 15 12:30:13 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 206080 kb
Host smart-56d29885-30da-4693-b06d-52d2f0f007c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458750084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1458750084
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1519329615
Short name T912
Test name
Test status
Simulation time 26435698 ps
CPU time 0.76 seconds
Started Apr 15 12:30:24 PM PDT 24
Finished Apr 15 12:30:25 PM PDT 24
Peak memory 205812 kb
Host smart-240d153e-25da-4946-9e6a-02fce78b856e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519329615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1519329615
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4294149830
Short name T880
Test name
Test status
Simulation time 44424361 ps
CPU time 0.91 seconds
Started Apr 15 12:30:11 PM PDT 24
Finished Apr 15 12:30:12 PM PDT 24
Peak memory 206164 kb
Host smart-705b1b62-8e9c-43a7-befe-2f3b77eab76c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294149830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4294149830
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1052842249
Short name T930
Test name
Test status
Simulation time 58961282 ps
CPU time 2.03 seconds
Started Apr 15 12:30:23 PM PDT 24
Finished Apr 15 12:30:25 PM PDT 24
Peak memory 214284 kb
Host smart-0d066d3a-49b1-4b6c-8330-c20dcdf2464c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052842249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1052842249
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3276521084
Short name T958
Test name
Test status
Simulation time 414014596 ps
CPU time 2.6 seconds
Started Apr 15 12:30:23 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 214276 kb
Host smart-c29f3b92-e0a4-4a23-938f-5128a335bf59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276521084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3276521084
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3992737347
Short name T924
Test name
Test status
Simulation time 83697172 ps
CPU time 1.22 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 214380 kb
Host smart-2a623e2d-6389-4ff1-9773-713c5097ea45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992737347 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3992737347
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.53210140
Short name T936
Test name
Test status
Simulation time 20989114 ps
CPU time 0.87 seconds
Started Apr 15 12:30:23 PM PDT 24
Finished Apr 15 12:30:25 PM PDT 24
Peak memory 205824 kb
Host smart-b1737d7c-bd46-480d-aa74-0dbc8a01b7a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53210140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.53210140
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1301749392
Short name T854
Test name
Test status
Simulation time 14789010 ps
CPU time 0.89 seconds
Started Apr 15 12:30:18 PM PDT 24
Finished Apr 15 12:30:19 PM PDT 24
Peak memory 205988 kb
Host smart-bd0cbf4d-3ac2-48c5-bc8d-2f8d4633c6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301749392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1301749392
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3183168524
Short name T922
Test name
Test status
Simulation time 62703072 ps
CPU time 1.33 seconds
Started Apr 15 12:30:14 PM PDT 24
Finished Apr 15 12:30:16 PM PDT 24
Peak memory 206124 kb
Host smart-e3a32f93-60ca-49c3-9c2b-296ce60ec374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183168524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3183168524
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.834835455
Short name T868
Test name
Test status
Simulation time 148311205 ps
CPU time 2.79 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 214240 kb
Host smart-14c1729d-e9c4-406c-a452-4d16b2cd3f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834835455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.834835455
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1442289569
Short name T932
Test name
Test status
Simulation time 175355311 ps
CPU time 1.36 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 206060 kb
Host smart-cfa792cb-e9b3-4966-b319-ce4b33a64d77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442289569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1442289569
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3592463913
Short name T929
Test name
Test status
Simulation time 24431072 ps
CPU time 0.9 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 206092 kb
Host smart-b0a16111-8621-4d46-8e7f-693fc915a720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592463913 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3592463913
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3442331161
Short name T848
Test name
Test status
Simulation time 12996372 ps
CPU time 0.81 seconds
Started Apr 15 12:30:10 PM PDT 24
Finished Apr 15 12:30:11 PM PDT 24
Peak memory 205912 kb
Host smart-33eb0e7c-8d3e-48e0-a54d-32d9cb181665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442331161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3442331161
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2982827378
Short name T237
Test name
Test status
Simulation time 13480877 ps
CPU time 0.94 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 206120 kb
Host smart-6fcc866e-7a3f-405a-bb46-8469a04856cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982827378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2982827378
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3655138892
Short name T861
Test name
Test status
Simulation time 496666203 ps
CPU time 3.44 seconds
Started Apr 15 12:30:23 PM PDT 24
Finished Apr 15 12:30:27 PM PDT 24
Peak memory 214312 kb
Host smart-eae91751-d4bc-414f-9f02-7f1c31e213cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655138892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3655138892
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2743776683
Short name T908
Test name
Test status
Simulation time 55204859 ps
CPU time 1.65 seconds
Started Apr 15 12:30:12 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 206020 kb
Host smart-86b2ac74-055a-4d23-aa67-d70f5c0568c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743776683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2743776683
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1235659576
Short name T966
Test name
Test status
Simulation time 18932830 ps
CPU time 1.07 seconds
Started Apr 15 12:30:27 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 214360 kb
Host smart-962fc9a2-41ca-4e2d-ad20-325848e3e239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235659576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1235659576
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1515242999
Short name T241
Test name
Test status
Simulation time 15492490 ps
CPU time 0.89 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 205928 kb
Host smart-2f5a6b6b-a00c-49ac-a63f-e7f7ee277fad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515242999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1515242999
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.400803277
Short name T856
Test name
Test status
Simulation time 25704197 ps
CPU time 0.9 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 205864 kb
Host smart-6d911278-7267-467e-8386-42f2a90c4f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400803277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.400803277
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.124446605
Short name T251
Test name
Test status
Simulation time 66734812 ps
CPU time 1.43 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 206036 kb
Host smart-de679abc-b4e1-4845-85fe-7741b67df49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124446605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.124446605
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2854773657
Short name T938
Test name
Test status
Simulation time 113643998 ps
CPU time 2.45 seconds
Started Apr 15 12:30:13 PM PDT 24
Finished Apr 15 12:30:16 PM PDT 24
Peak memory 214300 kb
Host smart-c9fc1843-849c-441c-82e3-6c41faff10a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854773657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2854773657
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2609210436
Short name T892
Test name
Test status
Simulation time 77585287 ps
CPU time 1.46 seconds
Started Apr 15 12:30:16 PM PDT 24
Finished Apr 15 12:30:18 PM PDT 24
Peak memory 206132 kb
Host smart-418fd598-4ffa-4257-98a3-64aab96a6852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609210436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2609210436
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3916891032
Short name T835
Test name
Test status
Simulation time 257399835 ps
CPU time 2.14 seconds
Started Apr 15 12:30:18 PM PDT 24
Finished Apr 15 12:30:20 PM PDT 24
Peak memory 214300 kb
Host smart-da98221f-f106-42a7-a69b-a6708f6513cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916891032 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3916891032
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2144109395
Short name T247
Test name
Test status
Simulation time 31200986 ps
CPU time 0.76 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:27 PM PDT 24
Peak memory 205900 kb
Host smart-d2ecc97b-3d3a-4beb-a79d-c4a2d9467961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144109395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2144109395
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.87156413
Short name T864
Test name
Test status
Simulation time 23139041 ps
CPU time 0.79 seconds
Started Apr 15 12:30:20 PM PDT 24
Finished Apr 15 12:30:22 PM PDT 24
Peak memory 205908 kb
Host smart-6aa5c955-74d8-47db-9011-003d93405198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87156413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.87156413
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2304537635
Short name T248
Test name
Test status
Simulation time 142966442 ps
CPU time 1.12 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 206028 kb
Host smart-03d29126-eea1-44ee-9e12-66e6d8397f08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304537635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2304537635
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.968246371
Short name T838
Test name
Test status
Simulation time 129321126 ps
CPU time 1.62 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:31 PM PDT 24
Peak memory 214452 kb
Host smart-5396f980-d5d8-4d42-bd6d-79abcadf75f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968246371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.968246371
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3000071926
Short name T942
Test name
Test status
Simulation time 114617623 ps
CPU time 2.67 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 205980 kb
Host smart-29478188-415d-46ed-98b8-a65e751a6fe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000071926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3000071926
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3254520564
Short name T843
Test name
Test status
Simulation time 75808755 ps
CPU time 1.09 seconds
Started Apr 15 12:30:12 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 214268 kb
Host smart-550828d3-24e5-4753-9bb6-eb69cb5679c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254520564 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3254520564
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1042291341
Short name T917
Test name
Test status
Simulation time 57188584 ps
CPU time 0.96 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 205976 kb
Host smart-13f780cb-6ed9-4eb4-9415-f0fe6248aa67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042291341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1042291341
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3955212691
Short name T934
Test name
Test status
Simulation time 15335325 ps
CPU time 0.84 seconds
Started Apr 15 12:30:14 PM PDT 24
Finished Apr 15 12:30:16 PM PDT 24
Peak memory 205800 kb
Host smart-a5c4782b-39d5-4648-9dcb-9fda0e348276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955212691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3955212691
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.419408790
Short name T901
Test name
Test status
Simulation time 34544257 ps
CPU time 1.09 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 206116 kb
Host smart-db60369e-49e7-4daa-8508-dc27f9f728e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419408790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.419408790
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.734805882
Short name T863
Test name
Test status
Simulation time 68792007 ps
CPU time 2.59 seconds
Started Apr 15 12:30:27 PM PDT 24
Finished Apr 15 12:30:31 PM PDT 24
Peak memory 214280 kb
Host smart-9a18b3dd-dbd1-4a3e-896b-db37ac2aacfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734805882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.734805882
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3527541538
Short name T258
Test name
Test status
Simulation time 154877783 ps
CPU time 1.54 seconds
Started Apr 15 12:30:14 PM PDT 24
Finished Apr 15 12:30:16 PM PDT 24
Peak memory 206020 kb
Host smart-869af463-3638-4c25-9265-b20999da1db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527541538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3527541538
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3391535433
Short name T883
Test name
Test status
Simulation time 26809053 ps
CPU time 0.96 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 206116 kb
Host smart-ed5a3a0d-4c06-49cc-8c58-2e719799444e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391535433 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3391535433
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.729993823
Short name T232
Test name
Test status
Simulation time 33943277 ps
CPU time 0.83 seconds
Started Apr 15 12:30:27 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 205900 kb
Host smart-6835cba5-0ce3-4334-b870-a842aa6f86c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729993823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.729993823
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1226300406
Short name T898
Test name
Test status
Simulation time 22829767 ps
CPU time 0.84 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:27 PM PDT 24
Peak memory 205924 kb
Host smart-c77fb291-bb57-43b9-8e5b-18565186c314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226300406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1226300406
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3692851935
Short name T951
Test name
Test status
Simulation time 42145916 ps
CPU time 1.09 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 206052 kb
Host smart-168913e4-0d55-4b85-94c7-b22cd92a5ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692851935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3692851935
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2104794823
Short name T959
Test name
Test status
Simulation time 222833134 ps
CPU time 3.93 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 214360 kb
Host smart-f411d412-1839-479c-b969-3423b4b6c775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104794823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2104794823
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3383716156
Short name T271
Test name
Test status
Simulation time 97624894 ps
CPU time 2.16 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 206020 kb
Host smart-9f45e02b-1fe6-4481-845f-d773f38b93e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383716156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3383716156
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2771751658
Short name T851
Test name
Test status
Simulation time 386286611 ps
CPU time 1.36 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:31 PM PDT 24
Peak memory 222504 kb
Host smart-174af88b-04eb-4e38-a5c5-bb07960470cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771751658 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2771751658
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4028477051
Short name T235
Test name
Test status
Simulation time 38440303 ps
CPU time 0.87 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 205976 kb
Host smart-ba9caefe-ddb4-4687-87ed-a8f45d7db8a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028477051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4028477051
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.537168292
Short name T968
Test name
Test status
Simulation time 79179286 ps
CPU time 0.78 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 205788 kb
Host smart-70e31315-c78d-4f15-a06e-8d801485baf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537168292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.537168292
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1342119571
Short name T249
Test name
Test status
Simulation time 32218887 ps
CPU time 1.36 seconds
Started Apr 15 12:30:20 PM PDT 24
Finished Apr 15 12:30:22 PM PDT 24
Peak memory 205996 kb
Host smart-1a9d45cc-d6b0-4038-9760-2d5a188e8f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342119571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1342119571
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3096327727
Short name T952
Test name
Test status
Simulation time 135491431 ps
CPU time 1.84 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 214284 kb
Host smart-3bcef829-f6f3-43f7-a304-466363bad993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096327727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3096327727
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3550803456
Short name T948
Test name
Test status
Simulation time 898757498 ps
CPU time 3.64 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 206056 kb
Host smart-0aaaaf2b-56ee-4b96-9467-8296080dd03a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550803456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3550803456
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2217441532
Short name T928
Test name
Test status
Simulation time 102318494 ps
CPU time 1.41 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 214252 kb
Host smart-afc4b801-5dea-4f4c-8f42-6bbe7c870751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217441532 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2217441532
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2244882123
Short name T873
Test name
Test status
Simulation time 13775253 ps
CPU time 0.89 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:38 PM PDT 24
Peak memory 205952 kb
Host smart-5f3fd8f1-9b74-4dd8-8146-380f96d7157e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244882123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2244882123
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.417549739
Short name T845
Test name
Test status
Simulation time 15811978 ps
CPU time 0.91 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 205916 kb
Host smart-d0928d3a-2e95-4b80-8d06-b21d4e1e660b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417549739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.417549739
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3916133157
Short name T903
Test name
Test status
Simulation time 16985841 ps
CPU time 0.96 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 206044 kb
Host smart-1462b860-4f32-4f44-ab83-35d3827d4136
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916133157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3916133157
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1177617484
Short name T846
Test name
Test status
Simulation time 63534497 ps
CPU time 2.3 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 214268 kb
Host smart-5f7664b6-8b6a-4c11-b6e9-b06bf8c4e6a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177617484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1177617484
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.799359780
Short name T955
Test name
Test status
Simulation time 616214140 ps
CPU time 2.36 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 206120 kb
Host smart-c5dfe67d-41fa-4306-92ba-9da4efb32360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799359780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.799359780
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1876070379
Short name T858
Test name
Test status
Simulation time 23759640 ps
CPU time 1.19 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 214348 kb
Host smart-0c02ecbf-c937-46c9-903b-795853de4bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876070379 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1876070379
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1343834204
Short name T245
Test name
Test status
Simulation time 46717140 ps
CPU time 0.81 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:27 PM PDT 24
Peak memory 205896 kb
Host smart-31d43c1a-5bcd-45a2-ad48-a96f10c6984e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343834204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1343834204
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2030698980
Short name T872
Test name
Test status
Simulation time 17700200 ps
CPU time 0.97 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 205876 kb
Host smart-ed1b9c60-2795-488e-aa38-991f0b2fd1ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030698980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2030698980
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2771027293
Short name T964
Test name
Test status
Simulation time 13868129 ps
CPU time 0.93 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 206040 kb
Host smart-948a11e6-b250-439f-8996-826a836a1551
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771027293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2771027293
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.7727738
Short name T840
Test name
Test status
Simulation time 66089420 ps
CPU time 2.45 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 214288 kb
Host smart-7ddc8aed-e0e5-45cf-bafb-a8bee86809b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7727738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.7727738
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2657167993
Short name T956
Test name
Test status
Simulation time 296362881 ps
CPU time 2.32 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 206000 kb
Host smart-c58f13a1-c579-4bff-a6c8-b7bfdcf59b04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657167993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2657167993
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3430472897
Short name T234
Test name
Test status
Simulation time 20980662 ps
CPU time 1.31 seconds
Started Apr 15 12:30:02 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 206280 kb
Host smart-54d81936-01c1-4920-ae5f-3c1df566081d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430472897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3430472897
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.525612959
Short name T941
Test name
Test status
Simulation time 58835509 ps
CPU time 3.23 seconds
Started Apr 15 12:30:05 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 205928 kb
Host smart-95251468-2322-4eb6-8171-11b8a44d3a12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525612959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.525612959
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2909866962
Short name T859
Test name
Test status
Simulation time 57803049 ps
CPU time 0.93 seconds
Started Apr 15 12:30:05 PM PDT 24
Finished Apr 15 12:30:06 PM PDT 24
Peak memory 205960 kb
Host smart-a95864d3-0ad1-4e8f-a7cf-9c41cda278c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909866962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2909866962
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3830198809
Short name T844
Test name
Test status
Simulation time 27234690 ps
CPU time 1.16 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:05 PM PDT 24
Peak memory 216100 kb
Host smart-e9f31961-a2fe-4a69-be45-fa4e6fbe5fe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830198809 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3830198809
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.396987826
Short name T943
Test name
Test status
Simulation time 33704366 ps
CPU time 0.87 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 205924 kb
Host smart-dfeab1f9-be41-4f34-8505-44a564aa30e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396987826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.396987826
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1059107911
Short name T935
Test name
Test status
Simulation time 12700472 ps
CPU time 0.87 seconds
Started Apr 15 12:30:06 PM PDT 24
Finished Apr 15 12:30:07 PM PDT 24
Peak memory 205868 kb
Host smart-773e082d-1ca6-48fd-a4bb-95d1e7011866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059107911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1059107911
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2512141002
Short name T879
Test name
Test status
Simulation time 43762993 ps
CPU time 1.26 seconds
Started Apr 15 12:30:01 PM PDT 24
Finished Apr 15 12:30:03 PM PDT 24
Peak memory 206032 kb
Host smart-4e352ccc-3c91-4227-819f-9f33783266c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512141002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2512141002
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1692338918
Short name T836
Test name
Test status
Simulation time 155028501 ps
CPU time 2.38 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:07 PM PDT 24
Peak memory 214272 kb
Host smart-3883e805-6b4e-4ade-9541-09b0b0fb8f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692338918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1692338918
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1177255679
Short name T257
Test name
Test status
Simulation time 97194325 ps
CPU time 2.46 seconds
Started Apr 15 12:30:05 PM PDT 24
Finished Apr 15 12:30:08 PM PDT 24
Peak memory 206048 kb
Host smart-df62edfd-bc9c-44ac-8755-a11e89908c69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177255679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1177255679
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.850945841
Short name T962
Test name
Test status
Simulation time 16285976 ps
CPU time 0.76 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 205788 kb
Host smart-80ee488b-2f32-4a2b-9230-09cd96f61509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850945841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.850945841
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2664041414
Short name T902
Test name
Test status
Simulation time 13804465 ps
CPU time 0.87 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 205920 kb
Host smart-a7c0fa69-101a-4640-af48-68be878f0b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664041414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2664041414
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3840028120
Short name T875
Test name
Test status
Simulation time 24677442 ps
CPU time 0.83 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 205892 kb
Host smart-b2decf40-2c07-442b-9c21-c1cabda36991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840028120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3840028120
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3327739813
Short name T847
Test name
Test status
Simulation time 134514133 ps
CPU time 0.92 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 205888 kb
Host smart-1fe88537-6d9e-42ae-bb2d-88369858ef9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327739813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3327739813
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3252512169
Short name T869
Test name
Test status
Simulation time 32728159 ps
CPU time 0.86 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 205512 kb
Host smart-7488b567-a604-4562-ad0c-517a3528f620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252512169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3252512169
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1286018199
Short name T940
Test name
Test status
Simulation time 14619154 ps
CPU time 0.89 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 205832 kb
Host smart-442420bd-4ecf-4f8b-8199-8954ecc26fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286018199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1286018199
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3073010319
Short name T876
Test name
Test status
Simulation time 11915705 ps
CPU time 0.84 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 205892 kb
Host smart-ff9bc82a-7c94-44e6-bb1c-fd2df5a6da15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073010319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3073010319
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3994997494
Short name T963
Test name
Test status
Simulation time 22381180 ps
CPU time 0.82 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 205880 kb
Host smart-36b9bdcb-455f-47fc-b13d-d95d3c225d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994997494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3994997494
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.897567747
Short name T949
Test name
Test status
Simulation time 39486790 ps
CPU time 0.85 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 205916 kb
Host smart-3370f51b-c13f-4dfc-af94-d66a88d330f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897567747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.897567747
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.306202752
Short name T946
Test name
Test status
Simulation time 43718360 ps
CPU time 0.83 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 205876 kb
Host smart-dabbd5ec-89c1-462a-af5c-aada406d1864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306202752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.306202752
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.257186354
Short name T244
Test name
Test status
Simulation time 135863727 ps
CPU time 1.18 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:06 PM PDT 24
Peak memory 206052 kb
Host smart-944fd364-d8b1-4132-9278-248e4d5528c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257186354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.257186354
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2122556312
Short name T939
Test name
Test status
Simulation time 569801707 ps
CPU time 3.52 seconds
Started Apr 15 12:30:09 PM PDT 24
Finished Apr 15 12:30:13 PM PDT 24
Peak memory 205996 kb
Host smart-e084ebd9-c707-4214-b292-c1aaa7314262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122556312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2122556312
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2618950606
Short name T242
Test name
Test status
Simulation time 16873135 ps
CPU time 0.98 seconds
Started Apr 15 12:30:00 PM PDT 24
Finished Apr 15 12:30:02 PM PDT 24
Peak memory 205972 kb
Host smart-edff1630-728d-49f0-9455-f9647cd0062c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618950606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2618950606
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3696576170
Short name T849
Test name
Test status
Simulation time 49114026 ps
CPU time 1.18 seconds
Started Apr 15 12:30:06 PM PDT 24
Finished Apr 15 12:30:08 PM PDT 24
Peak memory 214348 kb
Host smart-d2a2d92f-8e60-4502-828e-9778d7fd0be9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696576170 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3696576170
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3684550639
Short name T945
Test name
Test status
Simulation time 24882151 ps
CPU time 0.85 seconds
Started Apr 15 12:30:08 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 205972 kb
Host smart-48caf090-9915-4852-bcf6-6e6f243ac7ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684550639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3684550639
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2961333489
Short name T891
Test name
Test status
Simulation time 48845666 ps
CPU time 0.88 seconds
Started Apr 15 12:30:09 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 205920 kb
Host smart-8efeeebc-5dc6-40cb-8127-43727d16591d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961333489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2961333489
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4099694763
Short name T923
Test name
Test status
Simulation time 137920689 ps
CPU time 1.1 seconds
Started Apr 15 12:30:10 PM PDT 24
Finished Apr 15 12:30:11 PM PDT 24
Peak memory 206108 kb
Host smart-d7a7e660-4f7d-471f-b3d3-49095862f2a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099694763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4099694763
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2797939604
Short name T931
Test name
Test status
Simulation time 419280730 ps
CPU time 3.75 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:08 PM PDT 24
Peak memory 214308 kb
Host smart-3253c14e-dc52-4f32-8c3a-98d81b7bece0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797939604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2797939604
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.843050472
Short name T865
Test name
Test status
Simulation time 74783630 ps
CPU time 2.22 seconds
Started Apr 15 12:30:10 PM PDT 24
Finished Apr 15 12:30:13 PM PDT 24
Peak memory 206264 kb
Host smart-ff91aa8a-ac7a-4d8a-ab40-e0b8da8403d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843050472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.843050472
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2586267572
Short name T926
Test name
Test status
Simulation time 16426176 ps
CPU time 0.95 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:31 PM PDT 24
Peak memory 205868 kb
Host smart-e8945927-03c9-477b-8890-bd89d012779b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586267572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2586267572
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3380277331
Short name T944
Test name
Test status
Simulation time 76319149 ps
CPU time 0.88 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205796 kb
Host smart-84876c87-7728-4f75-ab92-ef0a54a534ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380277331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3380277331
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3138097972
Short name T841
Test name
Test status
Simulation time 28109335 ps
CPU time 0.77 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205808 kb
Host smart-a2e6deda-0905-4ddb-aa6d-17f066c068ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138097972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3138097972
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3932723017
Short name T871
Test name
Test status
Simulation time 15765267 ps
CPU time 0.84 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205888 kb
Host smart-00cc140e-e205-4cc0-a7eb-cab65b750d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932723017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3932723017
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1927174013
Short name T853
Test name
Test status
Simulation time 21319255 ps
CPU time 0.81 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205876 kb
Host smart-fef80b87-0ed0-488a-a2f7-9452f4b90af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927174013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1927174013
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1928618369
Short name T904
Test name
Test status
Simulation time 19658631 ps
CPU time 0.92 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205860 kb
Host smart-e68a27c2-09ee-4e40-8b13-067607a6f88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928618369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1928618369
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1575324849
Short name T870
Test name
Test status
Simulation time 57427621 ps
CPU time 0.81 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 205808 kb
Host smart-80335319-87f6-44f2-807a-aa1aabc0f7d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575324849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1575324849
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.533476158
Short name T925
Test name
Test status
Simulation time 29824334 ps
CPU time 0.82 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 205912 kb
Host smart-26e80a44-3775-4227-8d28-4056b3c84077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533476158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.533476158
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2668132993
Short name T862
Test name
Test status
Simulation time 29925266 ps
CPU time 0.88 seconds
Started Apr 15 12:30:40 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 205916 kb
Host smart-c2da2204-1753-4a50-bc17-29134fe54d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668132993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2668132993
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.819678164
Short name T867
Test name
Test status
Simulation time 51105383 ps
CPU time 0.79 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205832 kb
Host smart-2287f58d-41e4-47ba-aa57-51e531806a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819678164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.819678164
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3236715185
Short name T885
Test name
Test status
Simulation time 47401094 ps
CPU time 1.09 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:27 PM PDT 24
Peak memory 206044 kb
Host smart-b0566d65-e49a-4734-88ae-8320e4183718
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236715185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3236715185
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.24046146
Short name T857
Test name
Test status
Simulation time 694985362 ps
CPU time 5.75 seconds
Started Apr 15 12:30:20 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 205972 kb
Host smart-81af0dfb-0d27-4692-85ea-7e485dde5910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24046146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.24046146
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1219023682
Short name T233
Test name
Test status
Simulation time 37125020 ps
CPU time 0.85 seconds
Started Apr 15 12:30:15 PM PDT 24
Finished Apr 15 12:30:16 PM PDT 24
Peak memory 205868 kb
Host smart-aa96e88d-8a13-4dbb-a940-4c91555910a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219023682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1219023682
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2898189802
Short name T905
Test name
Test status
Simulation time 107700268 ps
CPU time 1.96 seconds
Started Apr 15 12:30:27 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 214340 kb
Host smart-9f1e30e4-a882-48bd-aa2f-05e98617621a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898189802 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2898189802
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.91186984
Short name T246
Test name
Test status
Simulation time 29839056 ps
CPU time 0.97 seconds
Started Apr 15 12:30:09 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 205976 kb
Host smart-737f308f-4b9b-4ced-b353-59eb8c496389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91186984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.91186984
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3961575740
Short name T897
Test name
Test status
Simulation time 58295024 ps
CPU time 0.85 seconds
Started Apr 15 12:30:11 PM PDT 24
Finished Apr 15 12:30:13 PM PDT 24
Peak memory 205908 kb
Host smart-ebd9f96f-c235-4eba-9e1b-5f72bf2a86e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961575740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3961575740
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1161481503
Short name T965
Test name
Test status
Simulation time 16597902 ps
CPU time 0.96 seconds
Started Apr 15 12:30:22 PM PDT 24
Finished Apr 15 12:30:24 PM PDT 24
Peak memory 206108 kb
Host smart-b188cddf-2517-4c8a-bcf9-19c99804a79a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161481503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1161481503
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.867207511
Short name T881
Test name
Test status
Simulation time 32571379 ps
CPU time 2.17 seconds
Started Apr 15 12:30:07 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 214304 kb
Host smart-4f05ae89-fd61-4560-99c4-fea0521cb51d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867207511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.867207511
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1713914262
Short name T272
Test name
Test status
Simulation time 686074052 ps
CPU time 10.11 seconds
Started Apr 15 12:30:10 PM PDT 24
Finished Apr 15 12:30:21 PM PDT 24
Peak memory 206024 kb
Host smart-6cfb2b4a-cb52-4245-8d28-a66252ce4485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713914262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1713914262
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.37183852
Short name T882
Test name
Test status
Simulation time 35963143 ps
CPU time 0.89 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 205872 kb
Host smart-8c7fa443-8208-4f02-b706-d4b859dc79d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37183852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.37183852
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2981135758
Short name T961
Test name
Test status
Simulation time 238439104 ps
CPU time 1.04 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 205876 kb
Host smart-afa3083b-5dc6-4830-9e57-ce232b417248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981135758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2981135758
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4238395099
Short name T937
Test name
Test status
Simulation time 46082827 ps
CPU time 0.81 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 205888 kb
Host smart-7fe37953-808a-4a8f-97d2-ec7efdc6168f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238395099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4238395099
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.881678262
Short name T887
Test name
Test status
Simulation time 39377611 ps
CPU time 0.78 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 205888 kb
Host smart-bdd1500a-b80a-4961-bedd-5ec35c35803c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881678262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.881678262
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3432966244
Short name T839
Test name
Test status
Simulation time 32610203 ps
CPU time 0.84 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 205968 kb
Host smart-4e7fba3b-efc9-414d-b5ee-f133e1b1317f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432966244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3432966244
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1965996636
Short name T899
Test name
Test status
Simulation time 21942944 ps
CPU time 0.79 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 205832 kb
Host smart-2d26e0e0-76c9-4666-81af-2fd6720fb8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965996636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1965996636
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1162182117
Short name T921
Test name
Test status
Simulation time 16036135 ps
CPU time 0.89 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 205956 kb
Host smart-dfe8918a-10be-4c00-89a6-bc4a05beec33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162182117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1162182117
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3425692085
Short name T909
Test name
Test status
Simulation time 100965741 ps
CPU time 0.75 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205796 kb
Host smart-a1a271ea-a05c-4ddd-bf2c-ee4b95e38f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425692085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3425692085
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3346625956
Short name T915
Test name
Test status
Simulation time 27323576 ps
CPU time 0.9 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 205968 kb
Host smart-1a05976f-cd55-4268-abe5-1c01d6e1d301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346625956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3346625956
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3141550181
Short name T957
Test name
Test status
Simulation time 43651209 ps
CPU time 0.82 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 205892 kb
Host smart-0c37a5ef-0698-4123-aecb-4396a932a76d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141550181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3141550181
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1113243298
Short name T890
Test name
Test status
Simulation time 27210620 ps
CPU time 0.99 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:30:33 PM PDT 24
Peak memory 214344 kb
Host smart-ff67391f-8184-4689-a22d-e0129cae1bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113243298 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1113243298
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1332375179
Short name T933
Test name
Test status
Simulation time 35365936 ps
CPU time 0.92 seconds
Started Apr 15 12:30:22 PM PDT 24
Finished Apr 15 12:30:23 PM PDT 24
Peak memory 205884 kb
Host smart-755a2446-767b-41e7-868b-b30b756ee118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332375179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1332375179
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3325374768
Short name T916
Test name
Test status
Simulation time 243904771 ps
CPU time 1.15 seconds
Started Apr 15 12:30:19 PM PDT 24
Finished Apr 15 12:30:21 PM PDT 24
Peak memory 206088 kb
Host smart-b6b29a63-432b-4c0e-8f72-d09560a36b39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325374768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3325374768
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2690248124
Short name T874
Test name
Test status
Simulation time 318284968 ps
CPU time 2.98 seconds
Started Apr 15 12:30:06 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 214264 kb
Host smart-7fac0de8-1d73-4bfb-af2e-2fdd03cdc4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690248124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2690248124
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2891408470
Short name T907
Test name
Test status
Simulation time 80756262 ps
CPU time 2.07 seconds
Started Apr 15 12:30:27 PM PDT 24
Finished Apr 15 12:30:30 PM PDT 24
Peak memory 206076 kb
Host smart-f0ad42a6-f35a-4a40-9585-70114e7147a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891408470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2891408470
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2516463413
Short name T886
Test name
Test status
Simulation time 35197441 ps
CPU time 1.32 seconds
Started Apr 15 12:30:23 PM PDT 24
Finished Apr 15 12:30:25 PM PDT 24
Peak memory 222528 kb
Host smart-54f1a071-6f70-4cbb-9af0-1463d1a7bb2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516463413 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2516463413
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1572774407
Short name T256
Test name
Test status
Simulation time 45882816 ps
CPU time 0.85 seconds
Started Apr 15 12:30:08 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 206032 kb
Host smart-b8f73021-2156-4447-b164-55c913186b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572774407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1572774407
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3919138218
Short name T967
Test name
Test status
Simulation time 46669330 ps
CPU time 0.92 seconds
Started Apr 15 12:30:16 PM PDT 24
Finished Apr 15 12:30:18 PM PDT 24
Peak memory 205892 kb
Host smart-fa6f69aa-0935-456b-966a-63a8a74748c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919138218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3919138218
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1918219447
Short name T236
Test name
Test status
Simulation time 25208806 ps
CPU time 1.09 seconds
Started Apr 15 12:30:09 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 206040 kb
Host smart-3e8a001f-4921-4948-9d4d-4f232b37fc84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918219447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1918219447
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.927005207
Short name T953
Test name
Test status
Simulation time 36652458 ps
CPU time 2.39 seconds
Started Apr 15 12:30:08 PM PDT 24
Finished Apr 15 12:30:11 PM PDT 24
Peak memory 222440 kb
Host smart-3b3c2f1b-d6e7-4b1b-96b9-d2232ed6f4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927005207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.927005207
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3485091402
Short name T269
Test name
Test status
Simulation time 80404015 ps
CPU time 1.49 seconds
Started Apr 15 12:30:07 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 206080 kb
Host smart-c25ec97a-2a98-4a04-86e4-f785352959d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485091402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3485091402
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2604864693
Short name T920
Test name
Test status
Simulation time 86259904 ps
CPU time 1.57 seconds
Started Apr 15 12:30:17 PM PDT 24
Finished Apr 15 12:30:19 PM PDT 24
Peak memory 222500 kb
Host smart-c90a17a7-ab7d-4c2a-af2f-a6f90b0d755d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604864693 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2604864693
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2103094492
Short name T900
Test name
Test status
Simulation time 16697148 ps
CPU time 0.83 seconds
Started Apr 15 12:30:16 PM PDT 24
Finished Apr 15 12:30:17 PM PDT 24
Peak memory 205892 kb
Host smart-3f479b65-942e-4283-98fc-5ab4e5583ed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103094492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2103094492
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4054183730
Short name T896
Test name
Test status
Simulation time 42226276 ps
CPU time 0.8 seconds
Started Apr 15 12:30:20 PM PDT 24
Finished Apr 15 12:30:21 PM PDT 24
Peak memory 205824 kb
Host smart-7df3c396-8204-4dfa-b38f-6bd6716ffa0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054183730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4054183730
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.588307975
Short name T231
Test name
Test status
Simulation time 39917707 ps
CPU time 1.44 seconds
Started Apr 15 12:30:24 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 205968 kb
Host smart-8dd544ae-138e-464c-8a3d-e3ccc098bde1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588307975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.588307975
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.505233695
Short name T893
Test name
Test status
Simulation time 102775239 ps
CPU time 2.96 seconds
Started Apr 15 12:30:25 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 214284 kb
Host smart-3e6d0b79-08ae-426e-a608-773d68bbf973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505233695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.505233695
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1629386668
Short name T878
Test name
Test status
Simulation time 149140775 ps
CPU time 1.59 seconds
Started Apr 15 12:30:24 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 206036 kb
Host smart-600fa00d-3511-47d6-908c-1a80273b4c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629386668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1629386668
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.310876135
Short name T884
Test name
Test status
Simulation time 33617173 ps
CPU time 1.4 seconds
Started Apr 15 12:30:06 PM PDT 24
Finished Apr 15 12:30:08 PM PDT 24
Peak memory 214368 kb
Host smart-94c937e5-eaeb-4b7c-9107-e4b4fc6ff3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310876135 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.310876135
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4032076282
Short name T894
Test name
Test status
Simulation time 25458503 ps
CPU time 0.93 seconds
Started Apr 15 12:30:08 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 205984 kb
Host smart-ea7f3d37-5275-40c5-b80d-daac90758f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032076282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4032076282
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3515195654
Short name T842
Test name
Test status
Simulation time 17307445 ps
CPU time 0.88 seconds
Started Apr 15 12:30:13 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 205892 kb
Host smart-bf6f905a-2ff0-4e7f-882c-e13f85eb282e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515195654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3515195654
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3949114608
Short name T229
Test name
Test status
Simulation time 65582875 ps
CPU time 0.99 seconds
Started Apr 15 12:30:26 PM PDT 24
Finished Apr 15 12:30:28 PM PDT 24
Peak memory 205992 kb
Host smart-212e59d4-89a2-4943-b341-9f858221d374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949114608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3949114608
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.218848393
Short name T947
Test name
Test status
Simulation time 203497442 ps
CPU time 2.06 seconds
Started Apr 15 12:30:07 PM PDT 24
Finished Apr 15 12:30:10 PM PDT 24
Peak memory 214428 kb
Host smart-cb07be06-9026-4c60-aea8-49933190f7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218848393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.218848393
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.897132439
Short name T259
Test name
Test status
Simulation time 120039016 ps
CPU time 2.98 seconds
Started Apr 15 12:30:08 PM PDT 24
Finished Apr 15 12:30:11 PM PDT 24
Peak memory 206072 kb
Host smart-0ca31b6f-73c9-4348-8267-e4e75b16c48a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897132439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.897132439
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3452039523
Short name T950
Test name
Test status
Simulation time 61074939 ps
CPU time 1.18 seconds
Started Apr 15 12:30:07 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 214384 kb
Host smart-13aee87e-cca7-4da1-835e-72f8762ee9b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452039523 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3452039523
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.377398366
Short name T855
Test name
Test status
Simulation time 13501346 ps
CPU time 0.86 seconds
Started Apr 15 12:30:27 PM PDT 24
Finished Apr 15 12:30:29 PM PDT 24
Peak memory 205936 kb
Host smart-0f9e7d6f-3e9d-4fa2-9d51-f16af64c80af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377398366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.377398366
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.369545013
Short name T913
Test name
Test status
Simulation time 17081172 ps
CPU time 0.8 seconds
Started Apr 15 12:30:07 PM PDT 24
Finished Apr 15 12:30:08 PM PDT 24
Peak memory 205852 kb
Host smart-c8751a54-1280-4c78-97ce-9dad3476e25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369545013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.369545013
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3040710158
Short name T888
Test name
Test status
Simulation time 15936037 ps
CPU time 0.99 seconds
Started Apr 15 12:30:19 PM PDT 24
Finished Apr 15 12:30:21 PM PDT 24
Peak memory 205980 kb
Host smart-b3faa5ed-16d9-451b-a2d1-f4d3705f4696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040710158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3040710158
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3473602942
Short name T895
Test name
Test status
Simulation time 78395701 ps
CPU time 1.42 seconds
Started Apr 15 12:30:24 PM PDT 24
Finished Apr 15 12:30:26 PM PDT 24
Peak memory 214276 kb
Host smart-0aa527aa-3e02-4d00-9a1e-8305069b5817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473602942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3473602942
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4134878331
Short name T927
Test name
Test status
Simulation time 226539384 ps
CPU time 1.84 seconds
Started Apr 15 12:30:06 PM PDT 24
Finished Apr 15 12:30:09 PM PDT 24
Peak memory 206040 kb
Host smart-306a66b6-cc4a-470c-b3b0-71b1e3e196ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134878331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4134878331
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2110610202
Short name T431
Test name
Test status
Simulation time 43008393 ps
CPU time 0.86 seconds
Started Apr 15 02:15:03 PM PDT 24
Finished Apr 15 02:15:04 PM PDT 24
Peak memory 206528 kb
Host smart-a3aee1b3-94a0-411f-89e7-3d58bdc96532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110610202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2110610202
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3542788216
Short name T110
Test name
Test status
Simulation time 30482081 ps
CPU time 0.8 seconds
Started Apr 15 02:14:55 PM PDT 24
Finished Apr 15 02:14:56 PM PDT 24
Peak memory 215504 kb
Host smart-40d23a06-a91e-437b-adb5-239bdf54eb40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542788216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3542788216
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3622442903
Short name T766
Test name
Test status
Simulation time 30912520 ps
CPU time 1 seconds
Started Apr 15 02:14:54 PM PDT 24
Finished Apr 15 02:14:55 PM PDT 24
Peak memory 217208 kb
Host smart-22daa028-444a-4250-836d-2f4012882c76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622442903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3622442903
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.338477454
Short name T88
Test name
Test status
Simulation time 94627720 ps
CPU time 0.98 seconds
Started Apr 15 02:14:50 PM PDT 24
Finished Apr 15 02:14:51 PM PDT 24
Peak memory 219796 kb
Host smart-edb70869-5657-4924-8286-8ea797ea4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338477454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.338477454
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4169238978
Short name T729
Test name
Test status
Simulation time 141237829 ps
CPU time 1.05 seconds
Started Apr 15 02:14:32 PM PDT 24
Finished Apr 15 02:14:34 PM PDT 24
Peak memory 216288 kb
Host smart-644a648c-e0b3-40c9-a6f8-052c3d98ed82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169238978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4169238978
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1296300781
Short name T605
Test name
Test status
Simulation time 21363385 ps
CPU time 1.18 seconds
Started Apr 15 02:14:44 PM PDT 24
Finished Apr 15 02:14:46 PM PDT 24
Peak memory 223624 kb
Host smart-10c53e39-dea7-41f9-b785-a00232d52841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296300781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1296300781
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1732035107
Short name T222
Test name
Test status
Simulation time 30373380 ps
CPU time 0.92 seconds
Started Apr 15 02:14:33 PM PDT 24
Finished Apr 15 02:14:34 PM PDT 24
Peak memory 206712 kb
Host smart-699edb41-036a-4599-a9a8-aea4d37d90a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732035107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1732035107
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3340981286
Short name T387
Test name
Test status
Simulation time 24815781 ps
CPU time 0.91 seconds
Started Apr 15 02:14:29 PM PDT 24
Finished Apr 15 02:14:30 PM PDT 24
Peak memory 214872 kb
Host smart-9276c8a5-899f-4e6c-8631-89270be0f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340981286 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3340981286
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2639650267
Short name T591
Test name
Test status
Simulation time 275480401 ps
CPU time 3.17 seconds
Started Apr 15 02:14:32 PM PDT 24
Finished Apr 15 02:14:35 PM PDT 24
Peak memory 216008 kb
Host smart-9baaf10c-3183-43f9-9f44-e0af9a629471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639650267 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2639650267
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.2522913298
Short name T620
Test name
Test status
Simulation time 51898286 ps
CPU time 0.87 seconds
Started Apr 15 02:15:17 PM PDT 24
Finished Apr 15 02:15:19 PM PDT 24
Peak memory 206324 kb
Host smart-61130fbc-5919-4eba-8f2d-1c1345886db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522913298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2522913298
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2418766509
Short name T96
Test name
Test status
Simulation time 48304893 ps
CPU time 0.85 seconds
Started Apr 15 02:15:07 PM PDT 24
Finished Apr 15 02:15:08 PM PDT 24
Peak memory 214900 kb
Host smart-d944187f-942f-4761-9191-1531f7a40012
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418766509 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2418766509
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2681097471
Short name T68
Test name
Test status
Simulation time 193112613 ps
CPU time 1.12 seconds
Started Apr 15 02:15:09 PM PDT 24
Finished Apr 15 02:15:10 PM PDT 24
Peak memory 216032 kb
Host smart-016475b8-e2c1-43b1-8f1c-29f77c3c06aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681097471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2681097471
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2771560027
Short name T112
Test name
Test status
Simulation time 32458842 ps
CPU time 0.81 seconds
Started Apr 15 02:15:07 PM PDT 24
Finished Apr 15 02:15:08 PM PDT 24
Peak memory 217568 kb
Host smart-37e5f061-bd63-4bda-ab83-f44452835509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771560027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2771560027
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.811077706
Short name T543
Test name
Test status
Simulation time 277637107 ps
CPU time 1.32 seconds
Started Apr 15 02:15:06 PM PDT 24
Finished Apr 15 02:15:07 PM PDT 24
Peak memory 219400 kb
Host smart-c4c6b015-eec8-4aa8-8802-2ae813d9733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811077706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.811077706
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2047134316
Short name T49
Test name
Test status
Simulation time 20766510 ps
CPU time 1.24 seconds
Started Apr 15 02:15:01 PM PDT 24
Finished Apr 15 02:15:03 PM PDT 24
Peak memory 223740 kb
Host smart-b74a3211-a9cb-4eee-b2ae-c4e6cff41730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047134316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2047134316
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1961607328
Short name T571
Test name
Test status
Simulation time 16435991 ps
CPU time 0.94 seconds
Started Apr 15 02:15:06 PM PDT 24
Finished Apr 15 02:15:07 PM PDT 24
Peak memory 206620 kb
Host smart-b709fe96-dae0-47dd-bad8-a549be2b5893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961607328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1961607328
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1133787168
Short name T800
Test name
Test status
Simulation time 16542940 ps
CPU time 0.95 seconds
Started Apr 15 02:15:01 PM PDT 24
Finished Apr 15 02:15:03 PM PDT 24
Peak memory 214832 kb
Host smart-bce65ee7-c01c-4d05-9456-f1f5c7d0ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133787168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1133787168
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.932143068
Short name T539
Test name
Test status
Simulation time 818728149 ps
CPU time 1.75 seconds
Started Apr 15 02:15:01 PM PDT 24
Finished Apr 15 02:15:03 PM PDT 24
Peak memory 214996 kb
Host smart-237cc27e-6651-40df-b5d9-18faa277e3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932143068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.932143068
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.2016509974
Short name T252
Test name
Test status
Simulation time 106201933 ps
CPU time 1.35 seconds
Started Apr 15 02:17:21 PM PDT 24
Finished Apr 15 02:17:23 PM PDT 24
Peak memory 215236 kb
Host smart-85045bb4-c9e0-4d10-a54e-9dc37d198f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016509974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2016509974
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2854794765
Short name T469
Test name
Test status
Simulation time 18297167 ps
CPU time 0.92 seconds
Started Apr 15 02:17:21 PM PDT 24
Finished Apr 15 02:17:22 PM PDT 24
Peak memory 205748 kb
Host smart-b19bb335-41d0-43f9-bd21-0bd9357e31eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854794765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2854794765
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1182485120
Short name T821
Test name
Test status
Simulation time 39979385 ps
CPU time 1.22 seconds
Started Apr 15 02:17:21 PM PDT 24
Finished Apr 15 02:17:23 PM PDT 24
Peak memory 216064 kb
Host smart-20e1848b-9108-42aa-8730-38fd87ba2a55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182485120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1182485120
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2549804704
Short name T690
Test name
Test status
Simulation time 35301068 ps
CPU time 0.93 seconds
Started Apr 15 02:17:21 PM PDT 24
Finished Apr 15 02:17:23 PM PDT 24
Peak memory 231936 kb
Host smart-429f2b31-b51b-45c2-9133-20fa918d0681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549804704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2549804704
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1063928908
Short name T574
Test name
Test status
Simulation time 26082563 ps
CPU time 1.15 seconds
Started Apr 15 02:17:16 PM PDT 24
Finished Apr 15 02:17:18 PM PDT 24
Peak memory 218704 kb
Host smart-c0984e9f-cd4c-4fa5-8b90-6c429f5bb510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063928908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1063928908
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2810733535
Short name T754
Test name
Test status
Simulation time 25410491 ps
CPU time 0.95 seconds
Started Apr 15 02:17:21 PM PDT 24
Finished Apr 15 02:17:23 PM PDT 24
Peak memory 215096 kb
Host smart-23e008bf-3ac9-4f1b-87af-5357cac93041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810733535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2810733535
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1197685965
Short name T391
Test name
Test status
Simulation time 16800105 ps
CPU time 0.95 seconds
Started Apr 15 02:17:16 PM PDT 24
Finished Apr 15 02:17:17 PM PDT 24
Peak memory 214868 kb
Host smart-29f369c5-9d12-49e3-8a6c-19d2b2185bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197685965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1197685965
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1904281758
Short name T684
Test name
Test status
Simulation time 594749709 ps
CPU time 2.52 seconds
Started Apr 15 02:17:17 PM PDT 24
Finished Apr 15 02:17:20 PM PDT 24
Peak memory 217368 kb
Host smart-b179e42b-c157-49a2-8ee2-8c72838b1ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904281758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1904281758
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1904574822
Short name T480
Test name
Test status
Simulation time 123223989546 ps
CPU time 1468.59 seconds
Started Apr 15 02:17:17 PM PDT 24
Finished Apr 15 02:41:46 PM PDT 24
Peak memory 231880 kb
Host smart-189e6e71-d99c-4776-a47f-4b3168b55782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904574822 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1904574822
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1944079812
Short name T355
Test name
Test status
Simulation time 48828613 ps
CPU time 1.47 seconds
Started Apr 15 02:20:49 PM PDT 24
Finished Apr 15 02:20:51 PM PDT 24
Peak memory 217420 kb
Host smart-898f63a0-72ac-4630-9436-b6d9099963cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944079812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1944079812
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2230600337
Short name T388
Test name
Test status
Simulation time 104629535 ps
CPU time 1.81 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217988 kb
Host smart-6be44c0f-9d37-4bf9-be64-d748a6445f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230600337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2230600337
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.4125805065
Short name T564
Test name
Test status
Simulation time 72676204 ps
CPU time 1.57 seconds
Started Apr 15 02:20:49 PM PDT 24
Finished Apr 15 02:20:51 PM PDT 24
Peak memory 217768 kb
Host smart-ef91e176-293c-49e9-9388-3fc2792909d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125805065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.4125805065
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1502263956
Short name T796
Test name
Test status
Simulation time 67131949 ps
CPU time 1.33 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217428 kb
Host smart-bea0f45d-f5c2-4ec4-92c3-2ed336a96d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502263956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1502263956
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1164639299
Short name T532
Test name
Test status
Simulation time 47722273 ps
CPU time 1.72 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:55 PM PDT 24
Peak memory 217240 kb
Host smart-f8e7f8e1-08db-4689-95e4-434bf0ee6416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164639299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1164639299
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3174950933
Short name T466
Test name
Test status
Simulation time 21151525 ps
CPU time 1.11 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217392 kb
Host smart-c6ecc45f-a3f6-470a-879a-38fa39cd8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174950933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3174950933
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.74040961
Short name T331
Test name
Test status
Simulation time 172558914 ps
CPU time 1.26 seconds
Started Apr 15 02:20:54 PM PDT 24
Finished Apr 15 02:20:56 PM PDT 24
Peak memory 214916 kb
Host smart-7b2b896b-bd99-495c-adda-96e9c94e6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74040961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.74040961
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2106433412
Short name T412
Test name
Test status
Simulation time 79146360 ps
CPU time 1.06 seconds
Started Apr 15 02:20:51 PM PDT 24
Finished Apr 15 02:20:53 PM PDT 24
Peak memory 217940 kb
Host smart-c9641ade-d5f9-42e4-aca7-0b8070f5b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106433412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2106433412
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.93571374
Short name T708
Test name
Test status
Simulation time 54595588 ps
CPU time 1.33 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:09 PM PDT 24
Peak memory 216304 kb
Host smart-afcbc7be-e332-4e41-88ae-972e5610bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93571374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.93571374
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.424698393
Short name T785
Test name
Test status
Simulation time 27544132 ps
CPU time 1.2 seconds
Started Apr 15 02:17:23 PM PDT 24
Finished Apr 15 02:17:25 PM PDT 24
Peak memory 215208 kb
Host smart-7e61b7a7-0fdb-4181-bd8d-6f48c383514e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424698393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.424698393
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2661447633
Short name T155
Test name
Test status
Simulation time 10828886 ps
CPU time 0.85 seconds
Started Apr 15 02:17:24 PM PDT 24
Finished Apr 15 02:17:25 PM PDT 24
Peak memory 215616 kb
Host smart-1e828208-1e21-483b-97b0-e6aac09a8322
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661447633 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2661447633
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2347204646
Short name T85
Test name
Test status
Simulation time 112118459 ps
CPU time 1.06 seconds
Started Apr 15 02:17:28 PM PDT 24
Finished Apr 15 02:17:29 PM PDT 24
Peak memory 216332 kb
Host smart-8dc53c78-572c-40e9-8ea3-c7d77b9e2f84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347204646 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2347204646
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2152633627
Short name T633
Test name
Test status
Simulation time 37097090 ps
CPU time 0.9 seconds
Started Apr 15 02:17:27 PM PDT 24
Finished Apr 15 02:17:28 PM PDT 24
Peak memory 214916 kb
Host smart-a0e42e4c-ef0c-476e-8095-fc0083b58dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152633627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2152633627
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2007794312
Short name T268
Test name
Test status
Simulation time 86259086 ps
CPU time 1.48 seconds
Started Apr 15 02:17:20 PM PDT 24
Finished Apr 15 02:17:22 PM PDT 24
Peak memory 218040 kb
Host smart-5226eece-efe0-41c0-ab7b-164a04490b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007794312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2007794312
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.2770771764
Short name T136
Test name
Test status
Simulation time 53517600 ps
CPU time 0.93 seconds
Started Apr 15 02:17:23 PM PDT 24
Finished Apr 15 02:17:25 PM PDT 24
Peak memory 214864 kb
Host smart-e5e98fd2-4e13-43c1-8b18-e759af64f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770771764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2770771764
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4193479576
Short name T797
Test name
Test status
Simulation time 803274032 ps
CPU time 4.62 seconds
Started Apr 15 02:17:23 PM PDT 24
Finished Apr 15 02:17:29 PM PDT 24
Peak memory 214848 kb
Host smart-1b61b1b4-5e28-4282-b1e9-c6221e92069f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193479576 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4193479576
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.526570860
Short name T607
Test name
Test status
Simulation time 507912751670 ps
CPU time 1990.66 seconds
Started Apr 15 02:17:23 PM PDT 24
Finished Apr 15 02:50:34 PM PDT 24
Peak memory 224576 kb
Host smart-8451b1b6-66d5-4042-8c66-045ba3d46d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526570860 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.526570860
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2373743596
Short name T386
Test name
Test status
Simulation time 112879713 ps
CPU time 1.12 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217244 kb
Host smart-eaaff7ec-00dc-4d87-99a7-9da03e0cf0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373743596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2373743596
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.147373601
Short name T715
Test name
Test status
Simulation time 64644109 ps
CPU time 1.33 seconds
Started Apr 15 02:20:51 PM PDT 24
Finished Apr 15 02:20:53 PM PDT 24
Peak memory 216372 kb
Host smart-aabeb625-ad41-4a30-913a-756f7632b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147373601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.147373601
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3561093111
Short name T327
Test name
Test status
Simulation time 87312068 ps
CPU time 1.26 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217748 kb
Host smart-7df99f00-5618-42af-924b-0188bc129767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561093111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3561093111
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.850126152
Short name T10
Test name
Test status
Simulation time 36941494 ps
CPU time 1.29 seconds
Started Apr 15 02:20:56 PM PDT 24
Finished Apr 15 02:20:58 PM PDT 24
Peak memory 216320 kb
Host smart-ebca83b2-f460-4847-a609-68703fc97e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850126152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.850126152
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.233494037
Short name T596
Test name
Test status
Simulation time 41097953 ps
CPU time 1.47 seconds
Started Apr 15 02:20:51 PM PDT 24
Finished Apr 15 02:20:53 PM PDT 24
Peak memory 217572 kb
Host smart-9d0b1f0f-b38a-400d-badd-ccaa862fe4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233494037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.233494037
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1423172872
Short name T731
Test name
Test status
Simulation time 52902736 ps
CPU time 1.27 seconds
Started Apr 15 02:20:55 PM PDT 24
Finished Apr 15 02:20:56 PM PDT 24
Peak memory 218828 kb
Host smart-9b4f056d-b940-4516-b313-bd19fb95b1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423172872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1423172872
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2377921001
Short name T379
Test name
Test status
Simulation time 37431002 ps
CPU time 1.3 seconds
Started Apr 15 02:20:52 PM PDT 24
Finished Apr 15 02:20:54 PM PDT 24
Peak memory 217388 kb
Host smart-3b63a796-098b-4e9e-8daa-e9c9e64cee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377921001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2377921001
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3718695248
Short name T260
Test name
Test status
Simulation time 63669372 ps
CPU time 1.24 seconds
Started Apr 15 02:20:53 PM PDT 24
Finished Apr 15 02:20:55 PM PDT 24
Peak memory 216192 kb
Host smart-8c85805a-dc9b-44fc-8932-d9be1fe1b508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718695248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3718695248
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.30241432
Short name T737
Test name
Test status
Simulation time 83099714 ps
CPU time 1.13 seconds
Started Apr 15 02:20:57 PM PDT 24
Finished Apr 15 02:20:59 PM PDT 24
Peak memory 217772 kb
Host smart-9de52853-10fe-4904-80e3-8e27f33a8e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30241432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.30241432
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2320833050
Short name T186
Test name
Test status
Simulation time 24426104 ps
CPU time 1.21 seconds
Started Apr 15 02:17:35 PM PDT 24
Finished Apr 15 02:17:36 PM PDT 24
Peak memory 215348 kb
Host smart-15f282ce-e5f3-4b9d-b238-59619adde759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320833050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2320833050
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2362589051
Short name T149
Test name
Test status
Simulation time 12924409 ps
CPU time 0.83 seconds
Started Apr 15 02:17:40 PM PDT 24
Finished Apr 15 02:17:41 PM PDT 24
Peak memory 205392 kb
Host smart-0ae83700-b5e4-4cf9-b9db-371426b8c26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362589051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2362589051
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1887868332
Short name T409
Test name
Test status
Simulation time 15291600 ps
CPU time 0.98 seconds
Started Apr 15 02:17:35 PM PDT 24
Finished Apr 15 02:17:36 PM PDT 24
Peak memory 215488 kb
Host smart-8c4c4f29-39c1-444d-9318-2a71df8bc303
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887868332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1887868332
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3059582597
Short name T510
Test name
Test status
Simulation time 34397371 ps
CPU time 0.96 seconds
Started Apr 15 02:17:36 PM PDT 24
Finished Apr 15 02:17:37 PM PDT 24
Peak memory 217100 kb
Host smart-f0cc5a5a-37d9-4c86-b36f-e13587ae563e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059582597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3059582597
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3807739002
Short name T84
Test name
Test status
Simulation time 21245795 ps
CPU time 1.17 seconds
Started Apr 15 02:17:34 PM PDT 24
Finished Apr 15 02:17:35 PM PDT 24
Peak memory 229312 kb
Host smart-e63dba05-81b5-4648-891d-86196c95a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807739002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3807739002
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1114895544
Short name T189
Test name
Test status
Simulation time 65992301 ps
CPU time 1.01 seconds
Started Apr 15 02:17:24 PM PDT 24
Finished Apr 15 02:17:25 PM PDT 24
Peak memory 216252 kb
Host smart-5e15a9ce-ce04-4632-8e97-40fa61ccd36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114895544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1114895544
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2434686515
Short name T683
Test name
Test status
Simulation time 44322348 ps
CPU time 0.85 seconds
Started Apr 15 02:17:34 PM PDT 24
Finished Apr 15 02:17:35 PM PDT 24
Peak memory 215220 kb
Host smart-19db7529-c4ca-42bc-aaef-8ccc1b093f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434686515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2434686515
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.336747513
Short name T509
Test name
Test status
Simulation time 92680666 ps
CPU time 0.88 seconds
Started Apr 15 02:17:25 PM PDT 24
Finished Apr 15 02:17:26 PM PDT 24
Peak memory 214664 kb
Host smart-91b427e5-0aff-49c4-8aab-35a7cba2c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336747513 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.336747513
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.637874735
Short name T507
Test name
Test status
Simulation time 118719555 ps
CPU time 1.58 seconds
Started Apr 15 02:17:31 PM PDT 24
Finished Apr 15 02:17:33 PM PDT 24
Peak memory 216256 kb
Host smart-e4f56b8c-c21f-4983-b940-c8e22206e048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637874735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.637874735
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2118340188
Short name T723
Test name
Test status
Simulation time 45533785115 ps
CPU time 1033.44 seconds
Started Apr 15 02:17:30 PM PDT 24
Finished Apr 15 02:34:44 PM PDT 24
Peak memory 223248 kb
Host smart-f5f88174-10a6-4671-a3c0-ffb8d7347bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118340188 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2118340188
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3398750932
Short name T275
Test name
Test status
Simulation time 52620511 ps
CPU time 1.15 seconds
Started Apr 15 02:20:58 PM PDT 24
Finished Apr 15 02:21:00 PM PDT 24
Peak memory 216132 kb
Host smart-2c88e94e-0d85-45b2-9f38-7343b53f9d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398750932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3398750932
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.492897490
Short name T799
Test name
Test status
Simulation time 59662310 ps
CPU time 1.44 seconds
Started Apr 15 02:20:57 PM PDT 24
Finished Apr 15 02:20:59 PM PDT 24
Peak memory 216304 kb
Host smart-a8b7d5db-6dd4-4695-832d-48428e761f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492897490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.492897490
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2757921484
Short name T600
Test name
Test status
Simulation time 83683185 ps
CPU time 1.36 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:10 PM PDT 24
Peak memory 218852 kb
Host smart-01141350-7776-4dba-b80f-ae03881279a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757921484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2757921484
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.736506256
Short name T612
Test name
Test status
Simulation time 42689835 ps
CPU time 1.51 seconds
Started Apr 15 02:21:01 PM PDT 24
Finished Apr 15 02:21:03 PM PDT 24
Peak memory 216508 kb
Host smart-d2dd65c8-af53-4d8c-8d71-8db0c31056ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736506256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.736506256
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1183692450
Short name T635
Test name
Test status
Simulation time 36884204 ps
CPU time 1.17 seconds
Started Apr 15 02:20:56 PM PDT 24
Finished Apr 15 02:20:58 PM PDT 24
Peak memory 217644 kb
Host smart-e19d56eb-c5ab-4369-8d98-6e98762420e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183692450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1183692450
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.138187414
Short name T444
Test name
Test status
Simulation time 54464372 ps
CPU time 1.47 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:09 PM PDT 24
Peak memory 216344 kb
Host smart-862c265d-26d1-4623-9800-b859a8fe92bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138187414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.138187414
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1951714997
Short name T542
Test name
Test status
Simulation time 81906391 ps
CPU time 1.72 seconds
Started Apr 15 02:21:03 PM PDT 24
Finished Apr 15 02:21:05 PM PDT 24
Peak memory 217792 kb
Host smart-06805d94-c4f1-43e3-b773-45a23ca462a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951714997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1951714997
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.258214465
Short name T590
Test name
Test status
Simulation time 44551975 ps
CPU time 1.54 seconds
Started Apr 15 02:20:58 PM PDT 24
Finished Apr 15 02:21:00 PM PDT 24
Peak memory 217364 kb
Host smart-fade460d-1b4b-453d-a327-c0e98c6dc5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258214465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.258214465
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3525574537
Short name T481
Test name
Test status
Simulation time 34408317 ps
CPU time 0.94 seconds
Started Apr 15 02:17:43 PM PDT 24
Finished Apr 15 02:17:45 PM PDT 24
Peak memory 206596 kb
Host smart-47de3ef7-a058-4960-ac1c-56fabafce6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525574537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3525574537
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3230432981
Short name T86
Test name
Test status
Simulation time 40049531 ps
CPU time 1.31 seconds
Started Apr 15 02:17:45 PM PDT 24
Finished Apr 15 02:17:47 PM PDT 24
Peak memory 216196 kb
Host smart-cafc0141-1c85-476d-baed-44d2018dd2b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230432981 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3230432981
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1918004990
Short name T221
Test name
Test status
Simulation time 25852510 ps
CPU time 1.11 seconds
Started Apr 15 02:17:42 PM PDT 24
Finished Apr 15 02:17:44 PM PDT 24
Peak memory 215072 kb
Host smart-90787f0f-e5df-41db-95ae-39687513eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918004990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1918004990
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1480387717
Short name T582
Test name
Test status
Simulation time 40672170 ps
CPU time 1.04 seconds
Started Apr 15 02:17:37 PM PDT 24
Finished Apr 15 02:17:38 PM PDT 24
Peak memory 216124 kb
Host smart-50873471-1b8b-487b-bfe1-99f6539dae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480387717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1480387717
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2066228325
Short name T341
Test name
Test status
Simulation time 20946644 ps
CPU time 1.03 seconds
Started Apr 15 02:17:42 PM PDT 24
Finished Apr 15 02:17:43 PM PDT 24
Peak memory 215152 kb
Host smart-dffe9543-264d-428d-9a6e-71a2f9a37ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066228325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2066228325
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3205969216
Short name T817
Test name
Test status
Simulation time 23575623 ps
CPU time 0.87 seconds
Started Apr 15 02:17:37 PM PDT 24
Finished Apr 15 02:17:38 PM PDT 24
Peak memory 214932 kb
Host smart-0aed7362-ad7f-49ed-b4f5-f4cefc0d35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205969216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3205969216
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4250989058
Short name T531
Test name
Test status
Simulation time 152004827 ps
CPU time 1.23 seconds
Started Apr 15 02:17:41 PM PDT 24
Finished Apr 15 02:17:43 PM PDT 24
Peak memory 206712 kb
Host smart-e12a644e-491f-46f6-bcaa-2bee4769bac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250989058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4250989058
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3201216938
Short name T623
Test name
Test status
Simulation time 12767054859 ps
CPU time 333.37 seconds
Started Apr 15 02:17:41 PM PDT 24
Finished Apr 15 02:23:15 PM PDT 24
Peak memory 222432 kb
Host smart-977779c6-dee8-4750-a6af-e98ea82789e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201216938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3201216938
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2349741111
Short name T143
Test name
Test status
Simulation time 44618801 ps
CPU time 1.09 seconds
Started Apr 15 02:20:57 PM PDT 24
Finished Apr 15 02:20:59 PM PDT 24
Peak memory 216432 kb
Host smart-e7a99e7b-8c83-4841-ad9d-5f1950c2a1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349741111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2349741111
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2559709745
Short name T782
Test name
Test status
Simulation time 91470938 ps
CPU time 1.41 seconds
Started Apr 15 02:20:59 PM PDT 24
Finished Apr 15 02:21:01 PM PDT 24
Peak memory 217744 kb
Host smart-c24b316b-fb9a-4b07-a249-cb9e0ae0dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559709745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2559709745
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1197948031
Short name T358
Test name
Test status
Simulation time 68607184 ps
CPU time 1.36 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:09 PM PDT 24
Peak memory 217816 kb
Host smart-e185844a-4837-48af-9c15-6a6a57341180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197948031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1197948031
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3626130683
Short name T637
Test name
Test status
Simulation time 50584107 ps
CPU time 1.48 seconds
Started Apr 15 02:21:03 PM PDT 24
Finished Apr 15 02:21:05 PM PDT 24
Peak memory 217672 kb
Host smart-8b4ceb8b-de4f-4ec5-b106-e12b3bb06598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626130683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3626130683
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3850282210
Short name T288
Test name
Test status
Simulation time 56789976 ps
CPU time 2.12 seconds
Started Apr 15 02:21:01 PM PDT 24
Finished Apr 15 02:21:04 PM PDT 24
Peak memory 216460 kb
Host smart-e433ed34-4a89-4d66-96e4-49fdcdce160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850282210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3850282210
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2691298399
Short name T643
Test name
Test status
Simulation time 55952083 ps
CPU time 1.64 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:10 PM PDT 24
Peak memory 216456 kb
Host smart-c94d76e9-0aa3-46e2-95b9-1b45fb8dc281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691298399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2691298399
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1235835036
Short name T294
Test name
Test status
Simulation time 95255012 ps
CPU time 1.37 seconds
Started Apr 15 02:20:59 PM PDT 24
Finished Apr 15 02:21:01 PM PDT 24
Peak memory 216244 kb
Host smart-9f6a0cc7-a656-4ab5-8158-3dbd54a45280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235835036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1235835036
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.422585799
Short name T742
Test name
Test status
Simulation time 79979237 ps
CPU time 1.2 seconds
Started Apr 15 02:20:57 PM PDT 24
Finished Apr 15 02:20:58 PM PDT 24
Peak memory 217972 kb
Host smart-91454ecf-c4b5-46a4-b0f1-8a22d11b1686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422585799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.422585799
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.4072584609
Short name T609
Test name
Test status
Simulation time 24597421 ps
CPU time 1.31 seconds
Started Apr 15 02:20:58 PM PDT 24
Finished Apr 15 02:21:00 PM PDT 24
Peak memory 217404 kb
Host smart-670fb7cc-b7b1-4f17-91c6-181a799ff62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072584609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4072584609
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.336910742
Short name T253
Test name
Test status
Simulation time 71410862 ps
CPU time 1.59 seconds
Started Apr 15 02:20:57 PM PDT 24
Finished Apr 15 02:21:00 PM PDT 24
Peak memory 217424 kb
Host smart-ce470fc5-20fd-48ad-9962-489f639879e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336910742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.336910742
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.4039200402
Short name T148
Test name
Test status
Simulation time 79694708 ps
CPU time 1.19 seconds
Started Apr 15 02:17:54 PM PDT 24
Finished Apr 15 02:17:56 PM PDT 24
Peak memory 215248 kb
Host smart-46950453-ed79-42cb-88ef-222656a41379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039200402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4039200402
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1376794091
Short name T618
Test name
Test status
Simulation time 38824640 ps
CPU time 0.8 seconds
Started Apr 15 02:17:52 PM PDT 24
Finished Apr 15 02:17:53 PM PDT 24
Peak memory 206584 kb
Host smart-670b7857-1a5c-4c60-a392-369eb92e5cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376794091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1376794091
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.3626421054
Short name T758
Test name
Test status
Simulation time 54043511 ps
CPU time 1 seconds
Started Apr 15 02:17:54 PM PDT 24
Finished Apr 15 02:17:55 PM PDT 24
Peak memory 219968 kb
Host smart-c658563c-6502-4de7-8ab5-bf3fa6eee9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626421054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3626421054
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1698731590
Short name T349
Test name
Test status
Simulation time 45927306 ps
CPU time 1.17 seconds
Started Apr 15 02:17:49 PM PDT 24
Finished Apr 15 02:17:51 PM PDT 24
Peak memory 216504 kb
Host smart-961f80b9-7bd6-46be-bbec-7daccc0ca0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698731590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1698731590
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2586254725
Short name T577
Test name
Test status
Simulation time 23836157 ps
CPU time 0.91 seconds
Started Apr 15 02:17:53 PM PDT 24
Finished Apr 15 02:17:55 PM PDT 24
Peak memory 215408 kb
Host smart-a7d597bf-c555-4084-a061-1c9d9c5c65af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586254725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2586254725
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.4256530165
Short name T413
Test name
Test status
Simulation time 23286351 ps
CPU time 0.92 seconds
Started Apr 15 02:17:47 PM PDT 24
Finished Apr 15 02:17:49 PM PDT 24
Peak memory 214888 kb
Host smart-9e2f447e-0c7b-4e52-beed-541fc681c95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256530165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4256530165
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.9036841
Short name T428
Test name
Test status
Simulation time 131263868760 ps
CPU time 2101.08 seconds
Started Apr 15 02:17:50 PM PDT 24
Finished Apr 15 02:52:52 PM PDT 24
Peak memory 226392 kb
Host smart-dc4101a3-499a-4f38-bdb5-be3186a270c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9036841 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.9036841
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1133354709
Short name T499
Test name
Test status
Simulation time 22020986 ps
CPU time 1.24 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:09 PM PDT 24
Peak memory 216216 kb
Host smart-956cd1e6-55f3-47e7-b629-39a96bb00266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133354709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1133354709
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2512020726
Short name T365
Test name
Test status
Simulation time 66263054 ps
CPU time 1.11 seconds
Started Apr 15 02:21:03 PM PDT 24
Finished Apr 15 02:21:04 PM PDT 24
Peak memory 216400 kb
Host smart-5f3c9fe2-95d1-4edd-9512-80a3c61f9e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512020726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2512020726
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3376817017
Short name T408
Test name
Test status
Simulation time 28544453 ps
CPU time 1.18 seconds
Started Apr 15 02:20:56 PM PDT 24
Finished Apr 15 02:20:58 PM PDT 24
Peak memory 216324 kb
Host smart-f23cbdf4-5516-4a35-8685-8801afed53fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376817017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3376817017
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2352029158
Short name T641
Test name
Test status
Simulation time 65410353 ps
CPU time 1.19 seconds
Started Apr 15 02:21:03 PM PDT 24
Finished Apr 15 02:21:05 PM PDT 24
Peak memory 216276 kb
Host smart-43b1f809-3d5e-475b-b676-77231eb86b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352029158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2352029158
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1575962449
Short name T598
Test name
Test status
Simulation time 55671241 ps
CPU time 1.04 seconds
Started Apr 15 02:21:00 PM PDT 24
Finished Apr 15 02:21:01 PM PDT 24
Peak memory 216192 kb
Host smart-a80ef73c-03b9-435c-b2aa-71e414b53a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575962449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1575962449
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3143412706
Short name T613
Test name
Test status
Simulation time 36634235 ps
CPU time 1.58 seconds
Started Apr 15 02:21:00 PM PDT 24
Finished Apr 15 02:21:02 PM PDT 24
Peak memory 217372 kb
Host smart-59c1d872-1374-4c2f-b043-468e0679e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143412706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3143412706
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2169557897
Short name T324
Test name
Test status
Simulation time 60202829 ps
CPU time 1.51 seconds
Started Apr 15 02:21:03 PM PDT 24
Finished Apr 15 02:21:05 PM PDT 24
Peak memory 217720 kb
Host smart-d1568022-206a-40fa-81ee-49a367245abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169557897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2169557897
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.894594324
Short name T753
Test name
Test status
Simulation time 165321782 ps
CPU time 3.25 seconds
Started Apr 15 02:21:03 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 219216 kb
Host smart-953c7cf6-174f-49cb-aeec-31d499561213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894594324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.894594324
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3633204404
Short name T198
Test name
Test status
Simulation time 38892968 ps
CPU time 1.57 seconds
Started Apr 15 02:21:02 PM PDT 24
Finished Apr 15 02:21:04 PM PDT 24
Peak memory 217532 kb
Host smart-3fc6ffef-6af2-41bd-8482-119c8f4a2277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633204404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3633204404
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3940838702
Short name T313
Test name
Test status
Simulation time 29636504 ps
CPU time 1.21 seconds
Started Apr 15 02:17:58 PM PDT 24
Finished Apr 15 02:18:00 PM PDT 24
Peak memory 215304 kb
Host smart-47071495-3fa4-4436-aee6-27e6076a98d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940838702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3940838702
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2123024978
Short name T395
Test name
Test status
Simulation time 57597358 ps
CPU time 0.88 seconds
Started Apr 15 02:18:02 PM PDT 24
Finished Apr 15 02:18:03 PM PDT 24
Peak memory 205688 kb
Host smart-357f672a-992b-4164-b96a-d039888c0ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123024978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2123024978
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.423553953
Short name T362
Test name
Test status
Simulation time 22351293 ps
CPU time 0.82 seconds
Started Apr 15 02:17:58 PM PDT 24
Finished Apr 15 02:17:59 PM PDT 24
Peak memory 215168 kb
Host smart-637535bc-8a4f-4499-b63c-9dfb9077633e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423553953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.423553953
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.534243574
Short name T717
Test name
Test status
Simulation time 32378183 ps
CPU time 0.85 seconds
Started Apr 15 02:17:59 PM PDT 24
Finished Apr 15 02:18:01 PM PDT 24
Peak memory 217548 kb
Host smart-b4dd6c24-280d-4e73-a9f9-2f2ade0943bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534243574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.534243574
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.988110745
Short name T442
Test name
Test status
Simulation time 511967683 ps
CPU time 2.66 seconds
Started Apr 15 02:17:52 PM PDT 24
Finished Apr 15 02:17:55 PM PDT 24
Peak memory 218344 kb
Host smart-140658a3-d02f-4401-a57a-dbf76b90d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988110745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.988110745
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1330637045
Short name T130
Test name
Test status
Simulation time 19451806 ps
CPU time 1.05 seconds
Started Apr 15 02:17:57 PM PDT 24
Finished Apr 15 02:17:59 PM PDT 24
Peak memory 214768 kb
Host smart-4cce9bfd-ffcd-4c1f-b931-832f7e92a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330637045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1330637045
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2653053278
Short name T212
Test name
Test status
Simulation time 35611439 ps
CPU time 0.84 seconds
Started Apr 15 02:17:53 PM PDT 24
Finished Apr 15 02:17:54 PM PDT 24
Peak memory 214696 kb
Host smart-459a0539-b0e3-4ca2-ad7e-b640af42d8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653053278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2653053278
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1676264814
Short name T567
Test name
Test status
Simulation time 296853697 ps
CPU time 3.22 seconds
Started Apr 15 02:17:59 PM PDT 24
Finished Apr 15 02:18:03 PM PDT 24
Peak memory 216092 kb
Host smart-3d1a60d4-54f9-4344-826b-29296b911571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676264814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1676264814
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3876057740
Short name T207
Test name
Test status
Simulation time 58658128629 ps
CPU time 661.73 seconds
Started Apr 15 02:18:02 PM PDT 24
Finished Apr 15 02:29:04 PM PDT 24
Peak memory 217936 kb
Host smart-a019ec95-1147-4a73-a8ca-ee525200e178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876057740 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3876057740
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3382851647
Short name T462
Test name
Test status
Simulation time 97691202 ps
CPU time 1.21 seconds
Started Apr 15 02:20:59 PM PDT 24
Finished Apr 15 02:21:01 PM PDT 24
Peak memory 216608 kb
Host smart-59783ae2-31d1-4b75-8acc-9e79985e1586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382851647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3382851647
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.4135167388
Short name T790
Test name
Test status
Simulation time 174079080 ps
CPU time 2.46 seconds
Started Apr 15 02:20:59 PM PDT 24
Finished Apr 15 02:21:03 PM PDT 24
Peak memory 216428 kb
Host smart-d1fd6591-e25a-4bda-988a-e391386d8b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135167388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4135167388
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2339236476
Short name T830
Test name
Test status
Simulation time 38268870 ps
CPU time 1.46 seconds
Started Apr 15 02:21:00 PM PDT 24
Finished Apr 15 02:21:03 PM PDT 24
Peak memory 216280 kb
Host smart-8038dd54-a328-4c3c-8151-1aec4cc18717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339236476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2339236476
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1567053224
Short name T219
Test name
Test status
Simulation time 113296496 ps
CPU time 1.42 seconds
Started Apr 15 02:21:05 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217760 kb
Host smart-b174a29c-e231-4265-886e-6982258459af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567053224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1567053224
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2195087563
Short name T287
Test name
Test status
Simulation time 50145210 ps
CPU time 1.05 seconds
Started Apr 15 02:21:01 PM PDT 24
Finished Apr 15 02:21:03 PM PDT 24
Peak memory 218940 kb
Host smart-8e91932e-d408-49bf-841d-5b276b2e70f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195087563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2195087563
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1148527429
Short name T805
Test name
Test status
Simulation time 63914127 ps
CPU time 1.42 seconds
Started Apr 15 02:21:02 PM PDT 24
Finished Apr 15 02:21:04 PM PDT 24
Peak memory 219004 kb
Host smart-0f33e50d-f563-427f-a981-64e4dc846c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148527429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1148527429
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.4139471801
Short name T624
Test name
Test status
Simulation time 56871480 ps
CPU time 1.42 seconds
Started Apr 15 02:21:04 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217348 kb
Host smart-cc1aa913-3b64-4ecb-ae03-371e9adbbde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139471801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4139471801
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3679960479
Short name T793
Test name
Test status
Simulation time 31868259 ps
CPU time 1.28 seconds
Started Apr 15 02:21:00 PM PDT 24
Finished Apr 15 02:21:02 PM PDT 24
Peak memory 218960 kb
Host smart-8789defd-4425-4b05-8c7e-1dabc36dc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679960479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3679960479
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.724658864
Short name T316
Test name
Test status
Simulation time 85504618 ps
CPU time 2.14 seconds
Started Apr 15 02:21:04 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217564 kb
Host smart-5e4dac3f-c52c-4664-8426-84abd3ef9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724658864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.724658864
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.641844119
Short name T749
Test name
Test status
Simulation time 27957018 ps
CPU time 1.2 seconds
Started Apr 15 02:18:06 PM PDT 24
Finished Apr 15 02:18:08 PM PDT 24
Peak memory 215240 kb
Host smart-191eec7c-6911-4086-91d9-d872e7e50c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641844119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.641844119
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1808754525
Short name T819
Test name
Test status
Simulation time 22909707 ps
CPU time 0.84 seconds
Started Apr 15 02:18:10 PM PDT 24
Finished Apr 15 02:18:11 PM PDT 24
Peak memory 205728 kb
Host smart-64b42bf9-7902-4d26-9b39-2bf1eddae196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808754525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1808754525
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.4923044
Short name T654
Test name
Test status
Simulation time 19541295 ps
CPU time 0.91 seconds
Started Apr 15 02:18:12 PM PDT 24
Finished Apr 15 02:18:13 PM PDT 24
Peak memory 215980 kb
Host smart-adab1be8-3884-4ba5-af45-9ebeba4f5ed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4923044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disa
ble_auto_req_mode.4923044
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1651787758
Short name T54
Test name
Test status
Simulation time 125433083 ps
CPU time 0.98 seconds
Started Apr 15 02:18:07 PM PDT 24
Finished Apr 15 02:18:08 PM PDT 24
Peak memory 217852 kb
Host smart-9fd82537-3eef-4858-96de-2780552c5dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651787758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1651787758
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.883582203
Short name T458
Test name
Test status
Simulation time 49977690 ps
CPU time 1.43 seconds
Started Apr 15 02:18:02 PM PDT 24
Finished Apr 15 02:18:04 PM PDT 24
Peak memory 217524 kb
Host smart-742fb046-6977-4b33-9e39-490dc8932590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883582203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.883582203
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.679386217
Short name T14
Test name
Test status
Simulation time 26051083 ps
CPU time 1.03 seconds
Started Apr 15 02:18:02 PM PDT 24
Finished Apr 15 02:18:04 PM PDT 24
Peak memory 223684 kb
Host smart-01128abe-6634-44a7-ac74-0afad162241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679386217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.679386217
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2947595523
Short name T734
Test name
Test status
Simulation time 17579993 ps
CPU time 0.96 seconds
Started Apr 15 02:17:57 PM PDT 24
Finished Apr 15 02:17:58 PM PDT 24
Peak memory 214908 kb
Host smart-f9612323-ea62-45f2-8ccf-fe03f7f83d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947595523 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2947595523
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1859490227
Short name T209
Test name
Test status
Simulation time 181054726655 ps
CPU time 1084.71 seconds
Started Apr 15 02:18:02 PM PDT 24
Finished Apr 15 02:36:08 PM PDT 24
Peak memory 223364 kb
Host smart-33dc9304-fb03-452a-9928-571f4484bb7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859490227 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1859490227
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1757812486
Short name T360
Test name
Test status
Simulation time 33568587 ps
CPU time 1.33 seconds
Started Apr 15 02:21:07 PM PDT 24
Finished Apr 15 02:21:09 PM PDT 24
Peak memory 216328 kb
Host smart-81973636-26e2-4adf-9ebe-4bf4f6ee96b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757812486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1757812486
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.946225585
Short name T21
Test name
Test status
Simulation time 65958330 ps
CPU time 1.08 seconds
Started Apr 15 02:21:05 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217788 kb
Host smart-b6d59f5a-5af5-43b0-b92c-1ae1aa637c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946225585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.946225585
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3139079096
Short name T813
Test name
Test status
Simulation time 27223677 ps
CPU time 1.28 seconds
Started Apr 15 02:21:06 PM PDT 24
Finished Apr 15 02:21:08 PM PDT 24
Peak memory 217564 kb
Host smart-4d809877-52cd-412e-bc7f-239f05ba00ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139079096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3139079096
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2876489010
Short name T602
Test name
Test status
Simulation time 77113627 ps
CPU time 1.12 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:12 PM PDT 24
Peak memory 216224 kb
Host smart-c635fc47-9258-406f-be83-a61a71216286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876489010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2876489010
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2766857837
Short name T563
Test name
Test status
Simulation time 68018102 ps
CPU time 1.08 seconds
Started Apr 15 02:21:04 PM PDT 24
Finished Apr 15 02:21:06 PM PDT 24
Peak memory 214944 kb
Host smart-fe04edb4-307c-458e-b928-f0bc34580a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766857837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2766857837
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.600863074
Short name T440
Test name
Test status
Simulation time 57832740 ps
CPU time 1.37 seconds
Started Apr 15 02:21:08 PM PDT 24
Finished Apr 15 02:21:10 PM PDT 24
Peak memory 217580 kb
Host smart-731dbf1e-b5d7-49fe-939a-3e7e5ee30644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600863074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.600863074
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2906773178
Short name T511
Test name
Test status
Simulation time 263286566 ps
CPU time 1.91 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 217632 kb
Host smart-5ae597c3-5de0-4cda-bf45-82bafbdd501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906773178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2906773178
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2493188148
Short name T521
Test name
Test status
Simulation time 43841693 ps
CPU time 1.24 seconds
Started Apr 15 02:21:04 PM PDT 24
Finished Apr 15 02:21:06 PM PDT 24
Peak memory 218572 kb
Host smart-97cb1fde-f29e-4051-8d16-a2954616256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493188148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2493188148
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3527540175
Short name T295
Test name
Test status
Simulation time 87586824 ps
CPU time 1.15 seconds
Started Apr 15 02:21:05 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 216352 kb
Host smart-126904e8-e99b-48bf-bca5-7ca41ba4c1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527540175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3527540175
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.4024694950
Short name T142
Test name
Test status
Simulation time 51017177 ps
CPU time 1.16 seconds
Started Apr 15 02:21:06 PM PDT 24
Finished Apr 15 02:21:08 PM PDT 24
Peak memory 217700 kb
Host smart-b80ed9c7-6375-4ee6-bd86-29cf74bfe4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024694950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4024694950
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1727157594
Short name T182
Test name
Test status
Simulation time 71951691 ps
CPU time 1.05 seconds
Started Apr 15 02:18:17 PM PDT 24
Finished Apr 15 02:18:18 PM PDT 24
Peak memory 215316 kb
Host smart-61036b6b-c755-4cb4-bb51-38139d0360c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727157594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1727157594
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3670444918
Short name T741
Test name
Test status
Simulation time 31911086 ps
CPU time 0.95 seconds
Started Apr 15 02:18:20 PM PDT 24
Finished Apr 15 02:18:21 PM PDT 24
Peak memory 206256 kb
Host smart-4cd40aa0-1771-4267-b58e-e65eda59a5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670444918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3670444918
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.3891978323
Short name T665
Test name
Test status
Simulation time 35916840 ps
CPU time 0.86 seconds
Started Apr 15 02:18:15 PM PDT 24
Finished Apr 15 02:18:16 PM PDT 24
Peak memory 230780 kb
Host smart-dc178e9d-a450-4d51-9c9e-3cebab528dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891978323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3891978323
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1901357041
Short name T301
Test name
Test status
Simulation time 40309095 ps
CPU time 1.38 seconds
Started Apr 15 02:18:11 PM PDT 24
Finished Apr 15 02:18:13 PM PDT 24
Peak memory 217396 kb
Host smart-ba99376b-b161-4a4f-8dc0-6eb53523ae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901357041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1901357041
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.2218926102
Short name T20
Test name
Test status
Simulation time 17976017 ps
CPU time 0.96 seconds
Started Apr 15 02:18:12 PM PDT 24
Finished Apr 15 02:18:14 PM PDT 24
Peak memory 214860 kb
Host smart-ccd45eb0-2a0e-4bff-b446-aec380526718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218926102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2218926102
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2878457665
Short name T459
Test name
Test status
Simulation time 1526414903 ps
CPU time 4.36 seconds
Started Apr 15 02:18:11 PM PDT 24
Finished Apr 15 02:18:16 PM PDT 24
Peak memory 216344 kb
Host smart-909619d5-4498-4cf3-a206-48463fe2196f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878457665 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2878457665
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1210743624
Short name T693
Test name
Test status
Simulation time 153466702686 ps
CPU time 322.84 seconds
Started Apr 15 02:18:28 PM PDT 24
Finished Apr 15 02:23:51 PM PDT 24
Peak memory 217732 kb
Host smart-0a217a07-e381-45b4-a325-64dbe70688bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210743624 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1210743624
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1921673083
Short name T647
Test name
Test status
Simulation time 216793624 ps
CPU time 2.95 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 216392 kb
Host smart-99f41b6d-6d5c-4d07-a5b0-cb3cac3fa390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921673083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1921673083
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3468046220
Short name T593
Test name
Test status
Simulation time 31064194 ps
CPU time 1.3 seconds
Started Apr 15 02:21:05 PM PDT 24
Finished Apr 15 02:21:08 PM PDT 24
Peak memory 217892 kb
Host smart-78729ab7-53e3-48c5-a87c-b20f33b4dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468046220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3468046220
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2131363922
Short name T518
Test name
Test status
Simulation time 114950313 ps
CPU time 1.01 seconds
Started Apr 15 02:21:06 PM PDT 24
Finished Apr 15 02:21:08 PM PDT 24
Peak memory 216212 kb
Host smart-58d61220-07c6-412d-b0ff-ae49eb8069d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131363922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2131363922
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2094160094
Short name T739
Test name
Test status
Simulation time 102741312 ps
CPU time 1.35 seconds
Started Apr 15 02:21:09 PM PDT 24
Finished Apr 15 02:21:11 PM PDT 24
Peak memory 217640 kb
Host smart-dc556589-d871-47f6-ada4-7385ee44f4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094160094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2094160094
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3323873449
Short name T350
Test name
Test status
Simulation time 60847041 ps
CPU time 1.3 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 217664 kb
Host smart-c72035fa-9b3d-474f-9748-fbf4031a9cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323873449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3323873449
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2148317067
Short name T748
Test name
Test status
Simulation time 63136922 ps
CPU time 1.07 seconds
Started Apr 15 02:21:08 PM PDT 24
Finished Apr 15 02:21:10 PM PDT 24
Peak memory 219056 kb
Host smart-f9b9a24e-834e-4ceb-b02f-856ac21470cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148317067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2148317067
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2491609952
Short name T631
Test name
Test status
Simulation time 63280457 ps
CPU time 1.09 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:12 PM PDT 24
Peak memory 216600 kb
Host smart-9e3c8706-b432-4b43-9a9a-576b0dbfb076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491609952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2491609952
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3620235900
Short name T443
Test name
Test status
Simulation time 28252281 ps
CPU time 1.21 seconds
Started Apr 15 02:21:05 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217504 kb
Host smart-eeb4b9a1-ea3e-4179-8303-54bc231d112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620235900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3620235900
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.610943670
Short name T756
Test name
Test status
Simulation time 49802975 ps
CPU time 0.87 seconds
Started Apr 15 02:18:29 PM PDT 24
Finished Apr 15 02:18:31 PM PDT 24
Peak memory 205764 kb
Host smart-f775171c-72dd-4931-91ef-f4c0f4a97653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610943670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.610943670
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2477468779
Short name T336
Test name
Test status
Simulation time 12723812 ps
CPU time 0.91 seconds
Started Apr 15 02:18:32 PM PDT 24
Finished Apr 15 02:18:33 PM PDT 24
Peak memory 215428 kb
Host smart-7214479a-c841-47c9-aeac-a42a8cc1f8f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477468779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2477468779
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2403815177
Short name T569
Test name
Test status
Simulation time 68383644 ps
CPU time 0.95 seconds
Started Apr 15 02:18:30 PM PDT 24
Finished Apr 15 02:18:32 PM PDT 24
Peak memory 216064 kb
Host smart-3819a30c-7921-4b7a-a284-695bc3dd33c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403815177 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2403815177
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1590920066
Short name T448
Test name
Test status
Simulation time 21081555 ps
CPU time 1.01 seconds
Started Apr 15 02:18:25 PM PDT 24
Finished Apr 15 02:18:27 PM PDT 24
Peak memory 230944 kb
Host smart-c6a910ad-53fa-41d3-8dff-62f8f874d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590920066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1590920066
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.828804100
Short name T680
Test name
Test status
Simulation time 77677824 ps
CPU time 1.1 seconds
Started Apr 15 02:18:21 PM PDT 24
Finished Apr 15 02:18:23 PM PDT 24
Peak memory 216148 kb
Host smart-e342d815-76aa-4e67-914b-b804070f61e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828804100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.828804100
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.341314735
Short name T823
Test name
Test status
Simulation time 32326192 ps
CPU time 0.8 seconds
Started Apr 15 02:18:25 PM PDT 24
Finished Apr 15 02:18:27 PM PDT 24
Peak memory 215228 kb
Host smart-62831854-9295-4cac-9453-a074a8e4b319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341314735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.341314735
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4249777908
Short name T578
Test name
Test status
Simulation time 35934509 ps
CPU time 0.89 seconds
Started Apr 15 02:18:19 PM PDT 24
Finished Apr 15 02:18:21 PM PDT 24
Peak memory 206712 kb
Host smart-a32b730e-99f1-42f4-a937-2f66761f924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249777908 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4249777908
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3711350083
Short name T752
Test name
Test status
Simulation time 59103424 ps
CPU time 1.7 seconds
Started Apr 15 02:18:20 PM PDT 24
Finished Apr 15 02:18:22 PM PDT 24
Peak memory 206796 kb
Host smart-bf8234e4-ac16-436e-afea-847757e3be02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711350083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3711350083
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2802181874
Short name T191
Test name
Test status
Simulation time 100364311133 ps
CPU time 935.38 seconds
Started Apr 15 02:18:25 PM PDT 24
Finished Apr 15 02:34:01 PM PDT 24
Peak memory 223352 kb
Host smart-dcc29cef-2a39-44fe-859d-c7f5085dedfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802181874 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2802181874
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4113118860
Short name T137
Test name
Test status
Simulation time 43313625 ps
CPU time 1.43 seconds
Started Apr 15 02:21:05 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217780 kb
Host smart-0ae16ca3-83c0-4f4a-91ce-e5df2a105d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113118860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4113118860
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2735057529
Short name T822
Test name
Test status
Simulation time 112503582 ps
CPU time 1.14 seconds
Started Apr 15 02:21:06 PM PDT 24
Finished Apr 15 02:21:07 PM PDT 24
Peak memory 217564 kb
Host smart-955735d9-fe37-44d7-bce6-359e92cd955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735057529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2735057529
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3289832642
Short name T392
Test name
Test status
Simulation time 84646469 ps
CPU time 1.5 seconds
Started Apr 15 02:21:25 PM PDT 24
Finished Apr 15 02:21:27 PM PDT 24
Peak memory 218216 kb
Host smart-34addb55-25cb-4491-93b7-cbc712c24117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289832642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3289832642
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1068724538
Short name T320
Test name
Test status
Simulation time 85817386 ps
CPU time 1.31 seconds
Started Apr 15 02:21:11 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 217580 kb
Host smart-84ebbd1c-cd63-48ae-b107-5cdf1239f53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068724538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1068724538
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.893321068
Short name T261
Test name
Test status
Simulation time 42351870 ps
CPU time 1.54 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 217424 kb
Host smart-4bcfeea1-0ed0-4c93-ae2c-34e3712c1942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893321068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.893321068
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3359602629
Short name T29
Test name
Test status
Simulation time 168306135 ps
CPU time 1.28 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 216324 kb
Host smart-5ad79223-5449-45c8-97b0-e25282cb2e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359602629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3359602629
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1112607751
Short name T342
Test name
Test status
Simulation time 92925147 ps
CPU time 1.04 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:12 PM PDT 24
Peak memory 216192 kb
Host smart-68ed9025-0504-4372-9921-f73a6e00d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112607751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1112607751
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3336978636
Short name T486
Test name
Test status
Simulation time 43502681 ps
CPU time 1.31 seconds
Started Apr 15 02:21:09 PM PDT 24
Finished Apr 15 02:21:12 PM PDT 24
Peak memory 218736 kb
Host smart-4e2fa818-7fc6-478b-9834-9793db809152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336978636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3336978636
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.4107630130
Short name T588
Test name
Test status
Simulation time 122083800 ps
CPU time 2.39 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 219180 kb
Host smart-3d51231b-a257-4284-870e-b50d318f6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107630130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4107630130
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2600307240
Short name T314
Test name
Test status
Simulation time 87142207 ps
CPU time 1.17 seconds
Started Apr 15 02:18:30 PM PDT 24
Finished Apr 15 02:18:32 PM PDT 24
Peak memory 215268 kb
Host smart-0cf29454-0e1c-4f54-81c4-be26240959fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600307240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2600307240
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2459155959
Short name T150
Test name
Test status
Simulation time 22564210 ps
CPU time 0.78 seconds
Started Apr 15 02:18:34 PM PDT 24
Finished Apr 15 02:18:35 PM PDT 24
Peak memory 205436 kb
Host smart-c559273f-cd59-4257-9824-00bf2e8ac138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459155959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2459155959
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1873804569
Short name T707
Test name
Test status
Simulation time 50814219 ps
CPU time 1.06 seconds
Started Apr 15 02:18:31 PM PDT 24
Finished Apr 15 02:18:33 PM PDT 24
Peak memory 218492 kb
Host smart-91c321cf-4129-410e-9255-5f41582bab0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873804569 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1873804569
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2003630320
Short name T76
Test name
Test status
Simulation time 26507850 ps
CPU time 1.09 seconds
Started Apr 15 02:18:32 PM PDT 24
Finished Apr 15 02:18:34 PM PDT 24
Peak memory 219684 kb
Host smart-57a53d78-954f-4b98-a10b-2fddc3e88f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003630320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2003630320
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3895217116
Short name T139
Test name
Test status
Simulation time 31867685 ps
CPU time 1.28 seconds
Started Apr 15 02:18:30 PM PDT 24
Finished Apr 15 02:18:32 PM PDT 24
Peak memory 217472 kb
Host smart-06795a82-c6a2-435f-8b87-c63c54a11fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895217116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3895217116
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1413369351
Short name T129
Test name
Test status
Simulation time 26909032 ps
CPU time 0.85 seconds
Started Apr 15 02:18:28 PM PDT 24
Finished Apr 15 02:18:30 PM PDT 24
Peak memory 215480 kb
Host smart-cf906ff3-83ad-491d-a764-2e475a2c7bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413369351 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1413369351
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1102899630
Short name T712
Test name
Test status
Simulation time 91974107 ps
CPU time 0.89 seconds
Started Apr 15 02:18:31 PM PDT 24
Finished Apr 15 02:18:32 PM PDT 24
Peak memory 214820 kb
Host smart-e7258b22-95a0-4285-b5e8-f99b8e04b802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102899630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1102899630
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2238684568
Short name T436
Test name
Test status
Simulation time 484532002 ps
CPU time 2.86 seconds
Started Apr 15 02:18:31 PM PDT 24
Finished Apr 15 02:18:34 PM PDT 24
Peak memory 214836 kb
Host smart-1b6c1bd1-46b1-4762-92a8-d7910e4c3610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238684568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2238684568
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.625079294
Short name T210
Test name
Test status
Simulation time 126819333261 ps
CPU time 1223.16 seconds
Started Apr 15 02:18:29 PM PDT 24
Finished Apr 15 02:38:53 PM PDT 24
Peak memory 222100 kb
Host smart-be3a98ed-6328-41a3-9e18-4c3a7b1835c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625079294 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.625079294
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3191389921
Short name T438
Test name
Test status
Simulation time 71615678 ps
CPU time 1.12 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 217732 kb
Host smart-d16d2fc9-0d53-43a7-81c7-0d059d81c38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191389921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3191389921
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4194020463
Short name T348
Test name
Test status
Simulation time 46327347 ps
CPU time 1.06 seconds
Started Apr 15 02:21:08 PM PDT 24
Finished Apr 15 02:21:10 PM PDT 24
Peak memory 216324 kb
Host smart-df6f7e93-ec1c-443e-be55-492bd3aceba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194020463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4194020463
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2335952457
Short name T200
Test name
Test status
Simulation time 51719035 ps
CPU time 1.87 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:15 PM PDT 24
Peak memory 218484 kb
Host smart-832c45dd-6f5b-48e8-abec-5b54aa81dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335952457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2335952457
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.408199716
Short name T639
Test name
Test status
Simulation time 26620998 ps
CPU time 1.36 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 216216 kb
Host smart-ff505544-51a3-4517-950b-7c5dfc01e30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408199716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.408199716
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.60977462
Short name T32
Test name
Test status
Simulation time 106012015 ps
CPU time 1.29 seconds
Started Apr 15 02:21:24 PM PDT 24
Finished Apr 15 02:21:26 PM PDT 24
Peak memory 216320 kb
Host smart-08f3423f-f516-4c30-833d-c3be43a32c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60977462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.60977462
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.619956185
Short name T340
Test name
Test status
Simulation time 72025187 ps
CPU time 1.33 seconds
Started Apr 15 02:21:09 PM PDT 24
Finished Apr 15 02:21:12 PM PDT 24
Peak memory 217892 kb
Host smart-92c73dc0-88a4-4abf-8777-beb3f2fa8ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619956185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.619956185
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.914536767
Short name T366
Test name
Test status
Simulation time 36028726 ps
CPU time 1.31 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 217468 kb
Host smart-42aed6c2-42ad-4a46-8554-b12f057d804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914536767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.914536767
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1246361156
Short name T730
Test name
Test status
Simulation time 26938931 ps
CPU time 1.23 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 216152 kb
Host smart-9bcf5acd-bb6e-44ea-916c-50439200da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246361156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1246361156
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.667226694
Short name T662
Test name
Test status
Simulation time 106254559 ps
CPU time 1.13 seconds
Started Apr 15 02:15:29 PM PDT 24
Finished Apr 15 02:15:31 PM PDT 24
Peak memory 215280 kb
Host smart-9663c338-d605-452b-beb9-24b61c5b417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667226694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.667226694
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.293359546
Short name T814
Test name
Test status
Simulation time 34673445 ps
CPU time 0.9 seconds
Started Apr 15 02:15:39 PM PDT 24
Finished Apr 15 02:15:40 PM PDT 24
Peak memory 205808 kb
Host smart-294e96ce-b9ca-427f-9e19-2883e240db2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293359546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.293359546
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3860159314
Short name T64
Test name
Test status
Simulation time 56599654 ps
CPU time 1.08 seconds
Started Apr 15 02:15:35 PM PDT 24
Finished Apr 15 02:15:36 PM PDT 24
Peak memory 216260 kb
Host smart-b2b4be1e-f46d-49fa-9be9-5aa34884c934
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860159314 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3860159314
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4161594825
Short name T171
Test name
Test status
Simulation time 18481664 ps
CPU time 1.01 seconds
Started Apr 15 02:15:30 PM PDT 24
Finished Apr 15 02:15:31 PM PDT 24
Peak memory 217596 kb
Host smart-0f358fe4-7d35-4832-94c5-0ffc83ee6bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161594825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4161594825
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1187884504
Short name T675
Test name
Test status
Simulation time 42156092 ps
CPU time 1.51 seconds
Started Apr 15 02:15:23 PM PDT 24
Finished Apr 15 02:15:25 PM PDT 24
Peak memory 216260 kb
Host smart-90884b9c-666b-41f9-906a-c5aa8bf2a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187884504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1187884504
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2296895187
Short name T126
Test name
Test status
Simulation time 33528821 ps
CPU time 0.97 seconds
Started Apr 15 02:15:26 PM PDT 24
Finished Apr 15 02:15:27 PM PDT 24
Peak memory 215436 kb
Host smart-97147e3b-25d7-40ae-9fa1-d41793bfd15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296895187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2296895187
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2393827328
Short name T825
Test name
Test status
Simulation time 128995550 ps
CPU time 0.91 seconds
Started Apr 15 02:15:18 PM PDT 24
Finished Apr 15 02:15:19 PM PDT 24
Peak memory 206696 kb
Host smart-47fb3d2b-d20a-4c33-b77a-62a93c393ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393827328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2393827328
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3835870405
Short name T18
Test name
Test status
Simulation time 181138533 ps
CPU time 3.3 seconds
Started Apr 15 02:15:38 PM PDT 24
Finished Apr 15 02:15:43 PM PDT 24
Peak memory 233092 kb
Host smart-e88a030e-df5f-4031-ac52-398dfecca543
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835870405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3835870405
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1231297353
Short name T406
Test name
Test status
Simulation time 18218445 ps
CPU time 0.94 seconds
Started Apr 15 02:15:17 PM PDT 24
Finished Apr 15 02:15:18 PM PDT 24
Peak memory 214892 kb
Host smart-1f8efae4-94c8-43c8-866d-330d82e9b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231297353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1231297353
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3800461587
Short name T220
Test name
Test status
Simulation time 1089106729 ps
CPU time 5.29 seconds
Started Apr 15 02:15:30 PM PDT 24
Finished Apr 15 02:15:35 PM PDT 24
Peak memory 214872 kb
Host smart-0f583e4a-8665-483a-9652-f39fd255b554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800461587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3800461587
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4265192456
Short name T211
Test name
Test status
Simulation time 53245527964 ps
CPU time 591.76 seconds
Started Apr 15 02:15:26 PM PDT 24
Finished Apr 15 02:25:18 PM PDT 24
Peak memory 217988 kb
Host smart-161f7d69-a1f9-4261-b271-9e621342f07e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265192456 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4265192456
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2680490645
Short name T107
Test name
Test status
Simulation time 70275323 ps
CPU time 1.11 seconds
Started Apr 15 02:18:38 PM PDT 24
Finished Apr 15 02:18:40 PM PDT 24
Peak memory 215272 kb
Host smart-60b7cf2f-db14-42ce-9782-e3db95a0b6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680490645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2680490645
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.797134192
Short name T547
Test name
Test status
Simulation time 19148803 ps
CPU time 0.96 seconds
Started Apr 15 02:18:42 PM PDT 24
Finished Apr 15 02:18:44 PM PDT 24
Peak memory 206272 kb
Host smart-e696e237-dcd4-4f8b-89e6-59486d1660d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797134192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.797134192
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3384448857
Short name T768
Test name
Test status
Simulation time 14311297 ps
CPU time 0.89 seconds
Started Apr 15 02:18:42 PM PDT 24
Finished Apr 15 02:18:43 PM PDT 24
Peak memory 215736 kb
Host smart-ec8a2371-fa88-48ae-885e-f9bb39f718fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384448857 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3384448857
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.4162459603
Short name T75
Test name
Test status
Simulation time 33033604 ps
CPU time 1.03 seconds
Started Apr 15 02:18:37 PM PDT 24
Finished Apr 15 02:18:38 PM PDT 24
Peak memory 229428 kb
Host smart-1296019e-7a1c-4bff-bf3d-b86f9d0c0c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162459603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.4162459603
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1721960536
Short name T743
Test name
Test status
Simulation time 54209285 ps
CPU time 1.53 seconds
Started Apr 15 02:18:34 PM PDT 24
Finished Apr 15 02:18:36 PM PDT 24
Peak memory 217788 kb
Host smart-433f2ef2-34eb-4518-a419-7af8accbe887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721960536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1721960536
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1365879601
Short name T57
Test name
Test status
Simulation time 25677530 ps
CPU time 0.9 seconds
Started Apr 15 02:18:37 PM PDT 24
Finished Apr 15 02:18:39 PM PDT 24
Peak memory 215396 kb
Host smart-09f55947-239c-440a-806d-9801a8865dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365879601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1365879601
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.226276769
Short name T134
Test name
Test status
Simulation time 55034994 ps
CPU time 1 seconds
Started Apr 15 02:18:34 PM PDT 24
Finished Apr 15 02:18:35 PM PDT 24
Peak memory 206704 kb
Host smart-0762db1e-eae1-4ba3-b213-d7b4bb829bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226276769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.226276769
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1515932609
Short name T213
Test name
Test status
Simulation time 152021027 ps
CPU time 3.17 seconds
Started Apr 15 02:18:40 PM PDT 24
Finished Apr 15 02:18:44 PM PDT 24
Peak memory 216104 kb
Host smart-77e40692-83ec-4bc3-bb10-b3caa16ad279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515932609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1515932609
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1019255759
Short name T202
Test name
Test status
Simulation time 111517649873 ps
CPU time 677.78 seconds
Started Apr 15 02:18:37 PM PDT 24
Finished Apr 15 02:29:56 PM PDT 24
Peak memory 220128 kb
Host smart-0486c383-95e8-41a5-80e2-a4694039fd4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019255759 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1019255759
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.4293815843
Short name T592
Test name
Test status
Simulation time 46329049 ps
CPU time 1.63 seconds
Started Apr 15 02:21:11 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 216316 kb
Host smart-8f69ec5b-c6c9-4af5-b067-69bc868ea951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293815843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4293815843
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2166117951
Short name T703
Test name
Test status
Simulation time 33449933 ps
CPU time 1.55 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 216412 kb
Host smart-407825d6-6aa2-4128-94f9-baf504bbd9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166117951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2166117951
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3407917568
Short name T696
Test name
Test status
Simulation time 44616814 ps
CPU time 1.81 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:12 PM PDT 24
Peak memory 217588 kb
Host smart-587c703d-be30-49cb-8f81-925dfd817320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407917568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3407917568
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1917484681
Short name T390
Test name
Test status
Simulation time 49142002 ps
CPU time 1.27 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 217680 kb
Host smart-72c96cf2-3b28-4871-8fbe-bbd0174252b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917484681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1917484681
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.595855028
Short name T802
Test name
Test status
Simulation time 112720217 ps
CPU time 1.19 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 218736 kb
Host smart-913371a9-2b7e-4724-b326-1d5408d8f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595855028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.595855028
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3804891766
Short name T402
Test name
Test status
Simulation time 196647302 ps
CPU time 3.35 seconds
Started Apr 15 02:21:10 PM PDT 24
Finished Apr 15 02:21:15 PM PDT 24
Peak memory 217556 kb
Host smart-2be2b0e7-fed3-41a7-9aa5-0fe6b9acf9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804891766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3804891766
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2369863885
Short name T552
Test name
Test status
Simulation time 58226382 ps
CPU time 1.25 seconds
Started Apr 15 02:21:13 PM PDT 24
Finished Apr 15 02:21:15 PM PDT 24
Peak memory 216312 kb
Host smart-92b8943d-02d6-4ed4-98d5-0c76f89e6733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369863885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2369863885
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3458904758
Short name T770
Test name
Test status
Simulation time 190451797 ps
CPU time 2.71 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 217712 kb
Host smart-c74308c1-bbc5-42b6-bd7c-8be36cfa82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458904758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3458904758
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1877935186
Short name T262
Test name
Test status
Simulation time 40933790 ps
CPU time 1.32 seconds
Started Apr 15 02:21:11 PM PDT 24
Finished Apr 15 02:21:13 PM PDT 24
Peak memory 217824 kb
Host smart-602eb0d9-fea4-4797-a378-ca52554124d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877935186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1877935186
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4211862505
Short name T621
Test name
Test status
Simulation time 190140467 ps
CPU time 2.62 seconds
Started Apr 15 02:21:15 PM PDT 24
Finished Apr 15 02:21:18 PM PDT 24
Peak memory 218996 kb
Host smart-e36b95ae-76bb-46ea-9b06-a993999e594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211862505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4211862505
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4178537759
Short name T264
Test name
Test status
Simulation time 110050374 ps
CPU time 1.16 seconds
Started Apr 15 02:18:45 PM PDT 24
Finished Apr 15 02:18:47 PM PDT 24
Peak memory 215312 kb
Host smart-85c33c67-f4e6-46b5-9359-e946e88f8c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178537759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4178537759
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1314339686
Short name T689
Test name
Test status
Simulation time 32677931 ps
CPU time 0.92 seconds
Started Apr 15 02:18:51 PM PDT 24
Finished Apr 15 02:18:52 PM PDT 24
Peak memory 205800 kb
Host smart-d15c4722-7588-4fee-bd78-2eeba70e81be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314339686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1314339686
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3397700674
Short name T152
Test name
Test status
Simulation time 23413129 ps
CPU time 0.85 seconds
Started Apr 15 02:18:52 PM PDT 24
Finished Apr 15 02:18:53 PM PDT 24
Peak memory 215484 kb
Host smart-ead367d3-547e-4597-b38c-8d13232c66ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397700674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3397700674
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.4049380214
Short name T636
Test name
Test status
Simulation time 78904369 ps
CPU time 0.96 seconds
Started Apr 15 02:18:51 PM PDT 24
Finished Apr 15 02:18:52 PM PDT 24
Peak memory 217388 kb
Host smart-dfc833af-110b-414c-93c5-c5a3cf4e1b85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049380214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.4049380214
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.977086227
Short name T456
Test name
Test status
Simulation time 143357430 ps
CPU time 1.55 seconds
Started Apr 15 02:18:42 PM PDT 24
Finished Apr 15 02:18:44 PM PDT 24
Peak memory 217600 kb
Host smart-78ae948b-9df0-4bfc-9560-0e36ebf9645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977086227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.977086227
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3120807368
Short name T540
Test name
Test status
Simulation time 80239843 ps
CPU time 0.9 seconds
Started Apr 15 02:18:47 PM PDT 24
Finished Apr 15 02:18:49 PM PDT 24
Peak memory 214904 kb
Host smart-ab809988-2428-4e6f-98b3-f2f9f387fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120807368 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3120807368
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.378151793
Short name T461
Test name
Test status
Simulation time 122913648 ps
CPU time 0.88 seconds
Started Apr 15 02:18:43 PM PDT 24
Finished Apr 15 02:18:44 PM PDT 24
Peak memory 214892 kb
Host smart-61ff1fcc-edd1-4626-96b2-e4b6d437c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378151793 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.378151793
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1839722285
Short name T450
Test name
Test status
Simulation time 357495981 ps
CPU time 2.4 seconds
Started Apr 15 02:18:47 PM PDT 24
Finished Apr 15 02:18:49 PM PDT 24
Peak memory 216076 kb
Host smart-1a14e859-d938-4282-b452-ad5dcbab9c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839722285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1839722285
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3294133938
Short name T196
Test name
Test status
Simulation time 116957504285 ps
CPU time 678.86 seconds
Started Apr 15 02:18:47 PM PDT 24
Finished Apr 15 02:30:06 PM PDT 24
Peak memory 219212 kb
Host smart-0bf31c71-0d26-40e1-9384-94c43ba819ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294133938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3294133938
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1480133274
Short name T750
Test name
Test status
Simulation time 101800443 ps
CPU time 0.98 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 216364 kb
Host smart-5fd6dce8-ef2d-4fd2-95e4-2cc34ea7a39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480133274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1480133274
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.450512216
Short name T587
Test name
Test status
Simulation time 24085995 ps
CPU time 1.18 seconds
Started Apr 15 02:21:17 PM PDT 24
Finished Apr 15 02:21:19 PM PDT 24
Peak memory 217664 kb
Host smart-bca93599-5cc6-414e-81ac-6bfcbe7b9bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450512216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.450512216
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.399249422
Short name T453
Test name
Test status
Simulation time 64675482 ps
CPU time 1.05 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 216320 kb
Host smart-bdbc83a6-4172-4376-bc84-2b51b345d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399249422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.399249422
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.521242984
Short name T801
Test name
Test status
Simulation time 29536542 ps
CPU time 1.29 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 216120 kb
Host smart-e16abda7-68d1-446b-a142-9ad2536cfb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521242984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.521242984
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1381598095
Short name T399
Test name
Test status
Simulation time 62765050 ps
CPU time 1.26 seconds
Started Apr 15 02:21:15 PM PDT 24
Finished Apr 15 02:21:17 PM PDT 24
Peak memory 217492 kb
Host smart-6e4e446e-3d2c-46d1-9d52-5df2d5e4b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381598095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1381598095
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1081037963
Short name T286
Test name
Test status
Simulation time 99697262 ps
CPU time 1.18 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 218148 kb
Host smart-4cee1c03-24d1-4b28-9b02-76814238dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081037963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1081037963
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1771815338
Short name T265
Test name
Test status
Simulation time 126900068 ps
CPU time 1.09 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 216180 kb
Host smart-0ebe3cc2-0ed3-4b84-bf1f-a507d9f02927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771815338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1771815338
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3731369463
Short name T653
Test name
Test status
Simulation time 275209169 ps
CPU time 1.04 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 216240 kb
Host smart-026bf49f-6283-4bc7-bc8c-851c234d74aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731369463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3731369463
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.752183473
Short name T291
Test name
Test status
Simulation time 37761260 ps
CPU time 1.39 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:17 PM PDT 24
Peak memory 217576 kb
Host smart-b10c7f96-92b8-452e-a634-b4f5ece82f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752183473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.752183473
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1528547265
Short name T615
Test name
Test status
Simulation time 43994121 ps
CPU time 1.53 seconds
Started Apr 15 02:21:17 PM PDT 24
Finished Apr 15 02:21:19 PM PDT 24
Peak memory 218908 kb
Host smart-026130ae-6918-4cdc-b872-76d146003667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528547265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1528547265
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.4162110046
Short name T611
Test name
Test status
Simulation time 123573571 ps
CPU time 1.19 seconds
Started Apr 15 02:18:50 PM PDT 24
Finished Apr 15 02:18:52 PM PDT 24
Peak memory 215276 kb
Host smart-1505c325-b719-4460-a407-b00383bb2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162110046 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4162110046
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3720051429
Short name T804
Test name
Test status
Simulation time 21118220 ps
CPU time 0.87 seconds
Started Apr 15 02:18:58 PM PDT 24
Finished Apr 15 02:18:59 PM PDT 24
Peak memory 205432 kb
Host smart-f014b76f-c4a3-4f3c-8bbf-f27cefe57bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720051429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3720051429
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.427529511
Short name T162
Test name
Test status
Simulation time 82894619 ps
CPU time 0.83 seconds
Started Apr 15 02:18:50 PM PDT 24
Finished Apr 15 02:18:52 PM PDT 24
Peak memory 215488 kb
Host smart-e2d68007-e866-4b33-8d80-4ae463814df0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427529511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.427529511
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2440346366
Short name T404
Test name
Test status
Simulation time 84443109 ps
CPU time 0.98 seconds
Started Apr 15 02:18:54 PM PDT 24
Finished Apr 15 02:18:56 PM PDT 24
Peak memory 215964 kb
Host smart-155255e3-a7c6-4860-b047-c322b55be071
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440346366 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2440346366
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1517642947
Short name T536
Test name
Test status
Simulation time 32059985 ps
CPU time 1.03 seconds
Started Apr 15 02:18:51 PM PDT 24
Finished Apr 15 02:18:52 PM PDT 24
Peak memory 217884 kb
Host smart-2fd489df-dcbf-4af0-9960-15ba40e65e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517642947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1517642947
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2711616910
Short name T401
Test name
Test status
Simulation time 54679564 ps
CPU time 2.07 seconds
Started Apr 15 02:18:51 PM PDT 24
Finished Apr 15 02:18:53 PM PDT 24
Peak memory 217676 kb
Host smart-dbea2735-1765-4610-8cf4-2afbb2ca8638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711616910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2711616910
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3411233040
Short name T58
Test name
Test status
Simulation time 19958830 ps
CPU time 1.05 seconds
Started Apr 15 02:18:54 PM PDT 24
Finished Apr 15 02:18:55 PM PDT 24
Peak memory 215664 kb
Host smart-822c16b9-7333-4673-a6a6-72f33e04e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411233040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3411233040
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.20928533
Short name T338
Test name
Test status
Simulation time 24723014 ps
CPU time 0.91 seconds
Started Apr 15 02:18:51 PM PDT 24
Finished Apr 15 02:18:53 PM PDT 24
Peak memory 214904 kb
Host smart-1212bbdc-59b3-4a56-a366-7cc5740eb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20928533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.20928533
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1172991219
Short name T718
Test name
Test status
Simulation time 130239184 ps
CPU time 2.8 seconds
Started Apr 15 02:18:51 PM PDT 24
Finished Apr 15 02:18:54 PM PDT 24
Peak memory 216032 kb
Host smart-ba9a8268-683e-4d0b-b1e2-66791fbbcc66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172991219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1172991219
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4036206468
Short name T812
Test name
Test status
Simulation time 388384701228 ps
CPU time 3064.49 seconds
Started Apr 15 02:18:50 PM PDT 24
Finished Apr 15 03:09:55 PM PDT 24
Peak memory 235268 kb
Host smart-6698f3a5-a5f9-415e-9ff2-8e0bd2458f0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036206468 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4036206468
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3991305354
Short name T296
Test name
Test status
Simulation time 69607187 ps
CPU time 1.33 seconds
Started Apr 15 02:21:12 PM PDT 24
Finished Apr 15 02:21:14 PM PDT 24
Peak memory 217828 kb
Host smart-9d165ada-dcf7-4ec2-86f6-6689b0b91eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991305354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3991305354
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2636099963
Short name T27
Test name
Test status
Simulation time 76468178 ps
CPU time 1.46 seconds
Started Apr 15 02:21:19 PM PDT 24
Finished Apr 15 02:21:21 PM PDT 24
Peak memory 217416 kb
Host smart-1c94e6dd-d483-4156-bf17-bc4965af5e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636099963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2636099963
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1628803544
Short name T283
Test name
Test status
Simulation time 37160919 ps
CPU time 1.08 seconds
Started Apr 15 02:21:16 PM PDT 24
Finished Apr 15 02:21:17 PM PDT 24
Peak memory 216360 kb
Host smart-efca232c-a6a9-4a4f-9a6e-42d20a300cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628803544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1628803544
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1511064342
Short name T494
Test name
Test status
Simulation time 86348292 ps
CPU time 1.24 seconds
Started Apr 15 02:21:17 PM PDT 24
Finished Apr 15 02:21:18 PM PDT 24
Peak memory 216336 kb
Host smart-8adabfaf-a347-48af-b9d6-5cff14d4f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511064342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1511064342
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.710553160
Short name T606
Test name
Test status
Simulation time 56213361 ps
CPU time 1.21 seconds
Started Apr 15 02:21:19 PM PDT 24
Finished Apr 15 02:21:20 PM PDT 24
Peak memory 216356 kb
Host smart-abb4c759-6ba5-4e77-ac8d-53c6cd997929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710553160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.710553160
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2154082286
Short name T579
Test name
Test status
Simulation time 39725489 ps
CPU time 1.57 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 217500 kb
Host smart-2f9285ad-7689-4920-8fd7-487dfc20381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154082286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2154082286
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3143677001
Short name T292
Test name
Test status
Simulation time 70630073 ps
CPU time 2.55 seconds
Started Apr 15 02:21:25 PM PDT 24
Finished Apr 15 02:21:28 PM PDT 24
Peak memory 217780 kb
Host smart-0aaec9cb-0510-4495-98cf-d0838d4e3262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143677001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3143677001
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1760300371
Short name T724
Test name
Test status
Simulation time 75037967 ps
CPU time 1.07 seconds
Started Apr 15 02:21:24 PM PDT 24
Finished Apr 15 02:21:26 PM PDT 24
Peak memory 216320 kb
Host smart-eda7efad-f1cc-45d2-beba-08458b8510de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760300371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1760300371
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2991886131
Short name T122
Test name
Test status
Simulation time 40162817 ps
CPU time 1.39 seconds
Started Apr 15 02:21:14 PM PDT 24
Finished Apr 15 02:21:16 PM PDT 24
Peak memory 218920 kb
Host smart-7234c1e6-4c6d-4770-bbda-1c5023379395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991886131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2991886131
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.826820980
Short name T146
Test name
Test status
Simulation time 89039653 ps
CPU time 1.24 seconds
Started Apr 15 02:18:59 PM PDT 24
Finished Apr 15 02:19:01 PM PDT 24
Peak memory 215308 kb
Host smart-2496acdf-9883-4477-9890-6b1986d97e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826820980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.826820980
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2824878
Short name T566
Test name
Test status
Simulation time 18156703 ps
CPU time 0.95 seconds
Started Apr 15 02:19:00 PM PDT 24
Finished Apr 15 02:19:01 PM PDT 24
Peak memory 206484 kb
Host smart-83ac1fe0-5c9f-43f7-8439-9ccf21593270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2824878
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2081420987
Short name T625
Test name
Test status
Simulation time 46901507 ps
CPU time 0.8 seconds
Started Apr 15 02:18:58 PM PDT 24
Finished Apr 15 02:18:59 PM PDT 24
Peak memory 215516 kb
Host smart-36d484bb-b544-487d-b712-e83cf3a08a64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081420987 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2081420987
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.969983643
Short name T608
Test name
Test status
Simulation time 37942044 ps
CPU time 1.1 seconds
Started Apr 15 02:19:01 PM PDT 24
Finished Apr 15 02:19:02 PM PDT 24
Peak memory 217280 kb
Host smart-607a7576-618f-45c1-9d02-99580b520443
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969983643 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.969983643
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1432535977
Short name T163
Test name
Test status
Simulation time 47191650 ps
CPU time 1.07 seconds
Started Apr 15 02:19:01 PM PDT 24
Finished Apr 15 02:19:02 PM PDT 24
Peak memory 215108 kb
Host smart-a6e7e776-efd9-4578-87b2-a914919b6b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432535977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1432535977
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3046668825
Short name T297
Test name
Test status
Simulation time 40415687 ps
CPU time 1.39 seconds
Started Apr 15 02:18:56 PM PDT 24
Finished Apr 15 02:18:58 PM PDT 24
Peak memory 216616 kb
Host smart-57ddda3f-71e5-422d-a593-524e8e92efea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046668825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3046668825
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.13478506
Short name T53
Test name
Test status
Simulation time 29440322 ps
CPU time 0.87 seconds
Started Apr 15 02:19:00 PM PDT 24
Finished Apr 15 02:19:02 PM PDT 24
Peak memory 215124 kb
Host smart-6c622038-7299-40f5-bbb9-3824bd6a6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13478506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.13478506
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2542683780
Short name T473
Test name
Test status
Simulation time 46445734 ps
CPU time 0.83 seconds
Started Apr 15 02:18:54 PM PDT 24
Finished Apr 15 02:18:55 PM PDT 24
Peak memory 214900 kb
Host smart-d04419fc-9215-4a9b-87ff-3d06a458be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542683780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2542683780
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1369630326
Short name T671
Test name
Test status
Simulation time 220397773 ps
CPU time 1.71 seconds
Started Apr 15 02:18:53 PM PDT 24
Finished Apr 15 02:18:56 PM PDT 24
Peak memory 214996 kb
Host smart-5861dd03-f1ab-47c1-89bf-414c427fbad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369630326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1369630326
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3936145873
Short name T746
Test name
Test status
Simulation time 24128491045 ps
CPU time 519.35 seconds
Started Apr 15 02:18:54 PM PDT 24
Finished Apr 15 02:27:34 PM PDT 24
Peak memory 216992 kb
Host smart-24132a79-4f02-4829-b0e8-fb5357f8d795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936145873 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3936145873
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.962578821
Short name T538
Test name
Test status
Simulation time 83189478 ps
CPU time 1.06 seconds
Started Apr 15 02:21:16 PM PDT 24
Finished Apr 15 02:21:18 PM PDT 24
Peak memory 216276 kb
Host smart-3720ede6-0a23-4aeb-b936-483c9fc83b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962578821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.962578821
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3462618382
Short name T410
Test name
Test status
Simulation time 99875341 ps
CPU time 2.69 seconds
Started Apr 15 02:21:19 PM PDT 24
Finished Apr 15 02:21:22 PM PDT 24
Peak memory 218288 kb
Host smart-1ed68531-22d3-4a11-a2b4-ecca17c18204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462618382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3462618382
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2589297692
Short name T651
Test name
Test status
Simulation time 87021289 ps
CPU time 1.11 seconds
Started Apr 15 02:21:19 PM PDT 24
Finished Apr 15 02:21:20 PM PDT 24
Peak memory 216180 kb
Host smart-4396093b-149b-42db-88e0-0e4b35184ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589297692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2589297692
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2586349295
Short name T357
Test name
Test status
Simulation time 73418735 ps
CPU time 1.07 seconds
Started Apr 15 02:21:22 PM PDT 24
Finished Apr 15 02:21:23 PM PDT 24
Peak memory 218844 kb
Host smart-c0975faa-cd1d-4289-9762-b0ed3304a0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586349295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2586349295
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3673382928
Short name T682
Test name
Test status
Simulation time 81637457 ps
CPU time 3.02 seconds
Started Apr 15 02:21:22 PM PDT 24
Finished Apr 15 02:21:25 PM PDT 24
Peak memory 218392 kb
Host smart-f4c127be-9c43-4851-89aa-530ce6ed80be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673382928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3673382928
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3458187442
Short name T561
Test name
Test status
Simulation time 172127445 ps
CPU time 2.54 seconds
Started Apr 15 02:21:19 PM PDT 24
Finished Apr 15 02:21:22 PM PDT 24
Peak memory 219340 kb
Host smart-a8a58b20-0cd0-434c-86e9-2a0a24f268ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458187442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3458187442
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3757849692
Short name T463
Test name
Test status
Simulation time 51400028 ps
CPU time 1.14 seconds
Started Apr 15 02:21:18 PM PDT 24
Finished Apr 15 02:21:19 PM PDT 24
Peak memory 216308 kb
Host smart-3e350b4e-1a8d-461d-bd91-5b7f8cab1d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757849692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3757849692
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1951714217
Short name T384
Test name
Test status
Simulation time 40907287 ps
CPU time 1.5 seconds
Started Apr 15 02:21:19 PM PDT 24
Finished Apr 15 02:21:21 PM PDT 24
Peak memory 217612 kb
Host smart-761e5673-b520-45df-835d-fcac73888847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951714217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1951714217
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.31266969
Short name T359
Test name
Test status
Simulation time 71231424 ps
CPU time 2.46 seconds
Started Apr 15 02:21:17 PM PDT 24
Finished Apr 15 02:21:20 PM PDT 24
Peak memory 217460 kb
Host smart-50fe1ebd-b8ab-4a0e-9a8c-a7fedd0c9a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31266969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.31266969
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3499758345
Short name T215
Test name
Test status
Simulation time 68232291 ps
CPU time 1.77 seconds
Started Apr 15 02:21:21 PM PDT 24
Finished Apr 15 02:21:23 PM PDT 24
Peak memory 218548 kb
Host smart-519be4ee-8842-4407-a781-685ff7cdb0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499758345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3499758345
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4290693058
Short name T544
Test name
Test status
Simulation time 25814990 ps
CPU time 1.22 seconds
Started Apr 15 02:19:11 PM PDT 24
Finished Apr 15 02:19:13 PM PDT 24
Peak memory 215264 kb
Host smart-9d7d33ac-8733-4cf7-8ede-78068bf67d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290693058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4290693058
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3227406191
Short name T810
Test name
Test status
Simulation time 42811773 ps
CPU time 0.85 seconds
Started Apr 15 02:19:05 PM PDT 24
Finished Apr 15 02:19:07 PM PDT 24
Peak memory 206284 kb
Host smart-61d3c05c-399c-4a78-93ce-f00266e751f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227406191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3227406191
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2497439653
Short name T184
Test name
Test status
Simulation time 10973322 ps
CPU time 0.85 seconds
Started Apr 15 02:19:04 PM PDT 24
Finished Apr 15 02:19:06 PM PDT 24
Peak memory 215624 kb
Host smart-ec3b6723-be40-41e4-9cc7-46e47d0af467
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497439653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2497439653
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.4232624163
Short name T4
Test name
Test status
Simulation time 36307123 ps
CPU time 1 seconds
Started Apr 15 02:19:12 PM PDT 24
Finished Apr 15 02:19:13 PM PDT 24
Peak memory 216480 kb
Host smart-07f716a4-c26d-4c5c-9e7c-8b9b7ec3dc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232624163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4232624163
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3679893478
Short name T347
Test name
Test status
Simulation time 86824041 ps
CPU time 2.72 seconds
Started Apr 15 02:19:07 PM PDT 24
Finished Apr 15 02:19:11 PM PDT 24
Peak memory 218272 kb
Host smart-caa837bb-5a21-47cf-878e-946b7fbcb49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679893478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3679893478
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3698395069
Short name T638
Test name
Test status
Simulation time 32297941 ps
CPU time 0.83 seconds
Started Apr 15 02:19:04 PM PDT 24
Finished Apr 15 02:19:05 PM PDT 24
Peak memory 215212 kb
Host smart-691dbcb7-0466-4213-b7d8-0b12bf3d96e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698395069 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3698395069
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3569061941
Short name T827
Test name
Test status
Simulation time 28048393 ps
CPU time 0.93 seconds
Started Apr 15 02:19:01 PM PDT 24
Finished Apr 15 02:19:02 PM PDT 24
Peak memory 214904 kb
Host smart-f290b9a7-49e2-4358-9008-52e0c1e2eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569061941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3569061941
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3167390032
Short name T154
Test name
Test status
Simulation time 394626047 ps
CPU time 6.96 seconds
Started Apr 15 02:19:03 PM PDT 24
Finished Apr 15 02:19:11 PM PDT 24
Peak memory 217576 kb
Host smart-810594f7-c68b-4d97-8e6d-a2afb599bda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167390032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3167390032
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.110836744
Short name T831
Test name
Test status
Simulation time 108373104031 ps
CPU time 1256.16 seconds
Started Apr 15 02:19:14 PM PDT 24
Finished Apr 15 02:40:10 PM PDT 24
Peak memory 222276 kb
Host smart-9c344341-a023-47d9-9874-e3ba6e3d4c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110836744 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.110836744
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2362538247
Short name T254
Test name
Test status
Simulation time 70662452 ps
CPU time 1.37 seconds
Started Apr 15 02:21:22 PM PDT 24
Finished Apr 15 02:21:23 PM PDT 24
Peak memory 217496 kb
Host smart-594fec18-5218-49e4-9ab4-364f8b057d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362538247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2362538247
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1280495528
Short name T700
Test name
Test status
Simulation time 73476112 ps
CPU time 2.53 seconds
Started Apr 15 02:21:21 PM PDT 24
Finished Apr 15 02:21:24 PM PDT 24
Peak memory 217668 kb
Host smart-cbcb4310-12bb-4cd3-9efa-39afc817d4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280495528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1280495528
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1989158558
Short name T523
Test name
Test status
Simulation time 245280830 ps
CPU time 3.73 seconds
Started Apr 15 02:21:21 PM PDT 24
Finished Apr 15 02:21:25 PM PDT 24
Peak memory 219236 kb
Host smart-3893f752-9b2f-4a4b-9243-95a88b08196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989158558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1989158558
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.291117698
Short name T784
Test name
Test status
Simulation time 69707662 ps
CPU time 1.4 seconds
Started Apr 15 02:21:18 PM PDT 24
Finished Apr 15 02:21:20 PM PDT 24
Peak memory 217308 kb
Host smart-2482af44-0c0d-4aee-b64e-963dd3fd13e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291117698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.291117698
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.737441814
Short name T751
Test name
Test status
Simulation time 38835030 ps
CPU time 1.61 seconds
Started Apr 15 02:21:18 PM PDT 24
Finished Apr 15 02:21:20 PM PDT 24
Peak memory 217624 kb
Host smart-9a65be8e-5f42-4e47-aaa4-12f09889b5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737441814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.737441814
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1846869967
Short name T280
Test name
Test status
Simulation time 50132732 ps
CPU time 1.25 seconds
Started Apr 15 02:21:17 PM PDT 24
Finished Apr 15 02:21:19 PM PDT 24
Peak memory 217720 kb
Host smart-e8e5ffcc-5df2-45df-963a-3da26b16dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846869967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1846869967
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1751683810
Short name T405
Test name
Test status
Simulation time 53326071 ps
CPU time 0.99 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 214844 kb
Host smart-3c4c7ac0-4e6e-4ee6-9e29-b69752413318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751683810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1751683810
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3006010422
Short name T655
Test name
Test status
Simulation time 78860125 ps
CPU time 1.91 seconds
Started Apr 15 02:21:23 PM PDT 24
Finished Apr 15 02:21:25 PM PDT 24
Peak memory 216548 kb
Host smart-97f5b88c-6f3e-47b6-8b95-9cbe7e839e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006010422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3006010422
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4161008414
Short name T332
Test name
Test status
Simulation time 67446051 ps
CPU time 1.42 seconds
Started Apr 15 02:21:24 PM PDT 24
Finished Apr 15 02:21:26 PM PDT 24
Peak memory 217684 kb
Host smart-8c2ea0f2-d274-4018-9063-196cc853da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161008414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4161008414
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2505926132
Short name T604
Test name
Test status
Simulation time 88007767 ps
CPU time 1.31 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 216256 kb
Host smart-6e8e485c-4fe4-42c4-aacc-946657310c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505926132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2505926132
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.3051748730
Short name T687
Test name
Test status
Simulation time 97750188 ps
CPU time 0.9 seconds
Started Apr 15 02:19:09 PM PDT 24
Finished Apr 15 02:19:10 PM PDT 24
Peak memory 205764 kb
Host smart-0952180c-1099-413c-8911-28b76dfc4050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051748730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3051748730
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_err.4178347012
Short name T513
Test name
Test status
Simulation time 24423414 ps
CPU time 1.17 seconds
Started Apr 15 02:19:08 PM PDT 24
Finished Apr 15 02:19:10 PM PDT 24
Peak memory 219936 kb
Host smart-8d6b235e-f9cf-4698-9867-40089d70068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178347012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4178347012
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_intr.2502974331
Short name T568
Test name
Test status
Simulation time 40870147 ps
CPU time 1 seconds
Started Apr 15 02:19:06 PM PDT 24
Finished Apr 15 02:19:07 PM PDT 24
Peak memory 223752 kb
Host smart-69e94302-e1ce-43eb-9c8e-a151a38a4dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502974331 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2502974331
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1347297681
Short name T346
Test name
Test status
Simulation time 15400592 ps
CPU time 0.94 seconds
Started Apr 15 02:19:06 PM PDT 24
Finished Apr 15 02:19:07 PM PDT 24
Peak memory 206676 kb
Host smart-a35c51ff-15b0-4298-9d3a-706623e85516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347297681 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1347297681
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2626367633
Short name T227
Test name
Test status
Simulation time 596030194 ps
CPU time 3.08 seconds
Started Apr 15 02:19:13 PM PDT 24
Finished Apr 15 02:19:17 PM PDT 24
Peak memory 216056 kb
Host smart-164e5574-7ef7-400d-8bcc-59a9fd2a23c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626367633 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2626367633
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3480293411
Short name T740
Test name
Test status
Simulation time 1137342364605 ps
CPU time 3107.32 seconds
Started Apr 15 02:19:04 PM PDT 24
Finished Apr 15 03:10:52 PM PDT 24
Peak memory 230208 kb
Host smart-696ed310-e97a-421d-ac80-0d7d81c17507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480293411 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3480293411
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1932316603
Short name T278
Test name
Test status
Simulation time 27996739 ps
CPU time 1.22 seconds
Started Apr 15 02:21:25 PM PDT 24
Finished Apr 15 02:21:27 PM PDT 24
Peak memory 214888 kb
Host smart-84236784-460f-40c7-b834-c6047650de7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932316603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1932316603
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.697200751
Short name T318
Test name
Test status
Simulation time 113203470 ps
CPU time 2.47 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:31 PM PDT 24
Peak memory 217636 kb
Host smart-2bbb674b-0669-4ddb-be32-e8ff9ed291e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697200751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.697200751
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3653648292
Short name T714
Test name
Test status
Simulation time 52694158 ps
CPU time 1.63 seconds
Started Apr 15 02:21:24 PM PDT 24
Finished Apr 15 02:21:26 PM PDT 24
Peak memory 217552 kb
Host smart-81b8ab2b-3763-4111-8f3f-a13d601d2b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653648292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3653648292
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.753273843
Short name T454
Test name
Test status
Simulation time 37406461 ps
CPU time 1.06 seconds
Started Apr 15 02:21:26 PM PDT 24
Finished Apr 15 02:21:27 PM PDT 24
Peak memory 216140 kb
Host smart-a2c7469f-5dcd-4a47-adea-63146b7e9c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753273843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.753273843
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.765530813
Short name T470
Test name
Test status
Simulation time 74059541 ps
CPU time 1.43 seconds
Started Apr 15 02:21:23 PM PDT 24
Finished Apr 15 02:21:25 PM PDT 24
Peak memory 217860 kb
Host smart-730ad56a-044c-477c-8c0c-b7b42267e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765530813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.765530813
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2964147421
Short name T1
Test name
Test status
Simulation time 39862980 ps
CPU time 1.11 seconds
Started Apr 15 02:21:29 PM PDT 24
Finished Apr 15 02:21:31 PM PDT 24
Peak memory 216152 kb
Host smart-ea0de3ce-c92a-4d84-8018-26fce0019e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964147421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2964147421
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.400588722
Short name T333
Test name
Test status
Simulation time 45673184 ps
CPU time 1.77 seconds
Started Apr 15 02:21:21 PM PDT 24
Finished Apr 15 02:21:23 PM PDT 24
Peak memory 219128 kb
Host smart-4c8f98ea-c9ff-4838-be5a-964eed66f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400588722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.400588722
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3420447676
Short name T829
Test name
Test status
Simulation time 58833638 ps
CPU time 2.35 seconds
Started Apr 15 02:21:22 PM PDT 24
Finished Apr 15 02:21:25 PM PDT 24
Peak memory 216764 kb
Host smart-1a621882-25bc-4b36-87a3-d3ebbbc4d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420447676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3420447676
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.4096578778
Short name T516
Test name
Test status
Simulation time 74800071 ps
CPU time 1.35 seconds
Started Apr 15 02:21:26 PM PDT 24
Finished Apr 15 02:21:27 PM PDT 24
Peak memory 217572 kb
Host smart-401fa317-2601-4a6c-a66c-b07fd05e1c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096578778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4096578778
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.71172971
Short name T491
Test name
Test status
Simulation time 68028772 ps
CPU time 1.46 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 219480 kb
Host smart-985254ed-db9b-4feb-82df-a2086cb382b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71172971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.71172971
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2898716055
Short name T17
Test name
Test status
Simulation time 47373745 ps
CPU time 1.18 seconds
Started Apr 15 02:19:10 PM PDT 24
Finished Apr 15 02:19:12 PM PDT 24
Peak memory 215296 kb
Host smart-40971354-8da6-4489-b4ee-42f5846d9670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898716055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2898716055
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1850209751
Short name T372
Test name
Test status
Simulation time 17846368 ps
CPU time 0.81 seconds
Started Apr 15 02:19:10 PM PDT 24
Finished Apr 15 02:19:12 PM PDT 24
Peak memory 205592 kb
Host smart-2f3341be-d775-4c22-9251-f1fb46fb09d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850209751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1850209751
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2398154868
Short name T114
Test name
Test status
Simulation time 14798672 ps
CPU time 0.95 seconds
Started Apr 15 02:19:11 PM PDT 24
Finished Apr 15 02:19:12 PM PDT 24
Peak memory 214960 kb
Host smart-80e24672-98af-4fc2-96e4-0505b3550204
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398154868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2398154868
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2480750141
Short name T354
Test name
Test status
Simulation time 32719647 ps
CPU time 1.14 seconds
Started Apr 15 02:19:14 PM PDT 24
Finished Apr 15 02:19:16 PM PDT 24
Peak memory 216496 kb
Host smart-ad860ceb-ead9-4924-a0c3-2565de374e4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480750141 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2480750141
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2970834590
Short name T488
Test name
Test status
Simulation time 21121711 ps
CPU time 0.85 seconds
Started Apr 15 02:19:06 PM PDT 24
Finished Apr 15 02:19:08 PM PDT 24
Peak memory 217512 kb
Host smart-8a9519ab-ec9f-438d-b125-2522c607ab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970834590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2970834590
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3246697386
Short name T545
Test name
Test status
Simulation time 37798339 ps
CPU time 1.43 seconds
Started Apr 15 02:19:09 PM PDT 24
Finished Apr 15 02:19:11 PM PDT 24
Peak memory 216440 kb
Host smart-2059cf9f-14e9-4884-992e-95fc097f2044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246697386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3246697386
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2606061980
Short name T47
Test name
Test status
Simulation time 34388730 ps
CPU time 0.98 seconds
Started Apr 15 02:19:08 PM PDT 24
Finished Apr 15 02:19:09 PM PDT 24
Peak memory 223648 kb
Host smart-95663036-b777-4c96-b38c-f072c5f65f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606061980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2606061980
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2538534877
Short name T326
Test name
Test status
Simulation time 41939627 ps
CPU time 0.87 seconds
Started Apr 15 02:19:10 PM PDT 24
Finished Apr 15 02:19:11 PM PDT 24
Peak memory 214920 kb
Host smart-eec7c170-d98c-4684-b7cd-9b2aff574076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538534877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2538534877
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1747111138
Short name T701
Test name
Test status
Simulation time 137041413 ps
CPU time 3.01 seconds
Started Apr 15 02:19:09 PM PDT 24
Finished Apr 15 02:19:12 PM PDT 24
Peak memory 214992 kb
Host smart-a7156c04-9cdf-48a7-be20-2b51e167ad9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747111138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1747111138
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.622889604
Short name T204
Test name
Test status
Simulation time 144449721726 ps
CPU time 523.5 seconds
Started Apr 15 02:19:14 PM PDT 24
Finished Apr 15 02:27:58 PM PDT 24
Peak memory 217560 kb
Host smart-5ad54b8b-27ca-41fb-b891-fecbc3d9599d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622889604 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.622889604
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2672871791
Short name T535
Test name
Test status
Simulation time 55749697 ps
CPU time 1.2 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 217500 kb
Host smart-59487603-2a41-4e6f-b20b-953945b4652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672871791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2672871791
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.946641621
Short name T626
Test name
Test status
Simulation time 62947895 ps
CPU time 1.28 seconds
Started Apr 15 02:21:30 PM PDT 24
Finished Apr 15 02:21:32 PM PDT 24
Peak memory 217952 kb
Host smart-bab2b920-1cdc-476f-84a0-ee6ee66e8048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946641621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.946641621
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.4031236130
Short name T711
Test name
Test status
Simulation time 105222513 ps
CPU time 1.13 seconds
Started Apr 15 02:21:29 PM PDT 24
Finished Apr 15 02:21:31 PM PDT 24
Peak memory 216272 kb
Host smart-654901d4-1fd0-4587-b6f2-20767a9f4c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031236130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4031236130
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3015524147
Short name T500
Test name
Test status
Simulation time 101237163 ps
CPU time 1.14 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 218452 kb
Host smart-07ab0054-c6f9-48e1-b425-674a246fea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015524147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3015524147
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.314222841
Short name T660
Test name
Test status
Simulation time 38986934 ps
CPU time 1.75 seconds
Started Apr 15 02:21:30 PM PDT 24
Finished Apr 15 02:21:33 PM PDT 24
Peak memory 217888 kb
Host smart-5ddacd6c-2e5d-4ccd-af8e-803dae131d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314222841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.314222841
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3392963546
Short name T33
Test name
Test status
Simulation time 84545746 ps
CPU time 1.14 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 216220 kb
Host smart-38e5e0d8-cc2c-4cb9-89cc-36eec9aa4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392963546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3392963546
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2687803833
Short name T757
Test name
Test status
Simulation time 179021830 ps
CPU time 1.45 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 216364 kb
Host smart-c453648b-e79e-4cf8-bc34-f5463dc32bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687803833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2687803833
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.399328283
Short name T517
Test name
Test status
Simulation time 102533575 ps
CPU time 1.33 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 217480 kb
Host smart-bdaab78a-7138-4a5d-b147-65cb4afa946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399328283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.399328283
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1120500245
Short name T477
Test name
Test status
Simulation time 34931342 ps
CPU time 1.68 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 217340 kb
Host smart-a169426c-05f6-4efa-9bb7-d5f52db886e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120500245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1120500245
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.539976373
Short name T674
Test name
Test status
Simulation time 43217365 ps
CPU time 1.59 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:31 PM PDT 24
Peak memory 217648 kb
Host smart-32010dda-085e-4c4d-b6b1-8482fc26c3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539976373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.539976373
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4257334729
Short name T273
Test name
Test status
Simulation time 32271220 ps
CPU time 1.3 seconds
Started Apr 15 02:19:15 PM PDT 24
Finished Apr 15 02:19:17 PM PDT 24
Peak memory 215264 kb
Host smart-a96b8765-7f52-4f6b-8b81-4b3e2635bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257334729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4257334729
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4130612750
Short name T526
Test name
Test status
Simulation time 13440916 ps
CPU time 0.87 seconds
Started Apr 15 02:19:18 PM PDT 24
Finished Apr 15 02:19:19 PM PDT 24
Peak memory 205700 kb
Host smart-8f7cf025-6857-4031-be5f-c1089d697a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130612750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4130612750
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.172755185
Short name T541
Test name
Test status
Simulation time 10921811 ps
CPU time 0.86 seconds
Started Apr 15 02:19:13 PM PDT 24
Finished Apr 15 02:19:14 PM PDT 24
Peak memory 215492 kb
Host smart-4af66abf-e7d9-45a4-95cf-1b334c7de0d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172755185 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.172755185
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.3228818021
Short name T71
Test name
Test status
Simulation time 19918765 ps
CPU time 1.25 seconds
Started Apr 15 02:19:13 PM PDT 24
Finished Apr 15 02:19:15 PM PDT 24
Peak memory 229488 kb
Host smart-40b8103a-6295-452f-86df-345bdebbc451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228818021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3228818021
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2433576758
Short name T478
Test name
Test status
Simulation time 71047068 ps
CPU time 1.61 seconds
Started Apr 15 02:19:12 PM PDT 24
Finished Apr 15 02:19:14 PM PDT 24
Peak memory 217524 kb
Host smart-46b53000-9be9-4ff1-b143-4c5a674bbf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433576758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2433576758
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2751240957
Short name T550
Test name
Test status
Simulation time 43821610 ps
CPU time 0.83 seconds
Started Apr 15 02:19:13 PM PDT 24
Finished Apr 15 02:19:15 PM PDT 24
Peak memory 214892 kb
Host smart-09767c03-84c3-4947-8508-9194942fb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751240957 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2751240957
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2062073492
Short name T669
Test name
Test status
Simulation time 21823570 ps
CPU time 0.95 seconds
Started Apr 15 02:19:15 PM PDT 24
Finished Apr 15 02:19:16 PM PDT 24
Peak memory 214828 kb
Host smart-1a3ef222-cb0c-44b7-8d5f-ed467fa19e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062073492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2062073492
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2774154751
Short name T339
Test name
Test status
Simulation time 488019716 ps
CPU time 3.17 seconds
Started Apr 15 02:19:15 PM PDT 24
Finished Apr 15 02:19:18 PM PDT 24
Peak memory 216352 kb
Host smart-3e6987e2-0906-4339-b3f1-d034d41f70bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774154751 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2774154751
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1518052258
Short name T807
Test name
Test status
Simulation time 15431994027 ps
CPU time 202.08 seconds
Started Apr 15 02:19:14 PM PDT 24
Finished Apr 15 02:22:37 PM PDT 24
Peak memory 218852 kb
Host smart-604fc6e5-17d2-441a-9d8d-4446dfd2d17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518052258 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1518052258
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3839874091
Short name T722
Test name
Test status
Simulation time 81466593 ps
CPU time 1.24 seconds
Started Apr 15 02:21:31 PM PDT 24
Finished Apr 15 02:21:32 PM PDT 24
Peak memory 216584 kb
Host smart-6f6f78a7-6678-4aa4-8a51-43873ea9eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839874091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3839874091
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2208790146
Short name T558
Test name
Test status
Simulation time 61734364 ps
CPU time 1.74 seconds
Started Apr 15 02:21:36 PM PDT 24
Finished Apr 15 02:21:39 PM PDT 24
Peak memory 217876 kb
Host smart-edffcd8e-dfb6-431c-a7bc-c169b2e81763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208790146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2208790146
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1880544942
Short name T381
Test name
Test status
Simulation time 139184009 ps
CPU time 1.06 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 218256 kb
Host smart-0bc04ed2-4a70-46e9-953a-b8b0eca6bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880544942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1880544942
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1495012470
Short name T534
Test name
Test status
Simulation time 123659879 ps
CPU time 1.49 seconds
Started Apr 15 02:21:31 PM PDT 24
Finished Apr 15 02:21:33 PM PDT 24
Peak memory 218576 kb
Host smart-e797a183-a81f-4f55-94e1-e96404f2d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495012470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1495012470
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.905452604
Short name T702
Test name
Test status
Simulation time 57583042 ps
CPU time 1.31 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:30 PM PDT 24
Peak memory 217424 kb
Host smart-a8036ab1-5682-40a5-b56f-0f972ea84a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905452604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.905452604
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2060457281
Short name T299
Test name
Test status
Simulation time 50422863 ps
CPU time 1.61 seconds
Started Apr 15 02:21:28 PM PDT 24
Finished Apr 15 02:21:31 PM PDT 24
Peak memory 218784 kb
Host smart-5cef1b6d-0db8-417b-b284-692d87c0c7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060457281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2060457281
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3164076293
Short name T426
Test name
Test status
Simulation time 36964258 ps
CPU time 1.35 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 216340 kb
Host smart-233053a2-6e69-49c4-bb06-e125983dd7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164076293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3164076293
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2054763440
Short name T361
Test name
Test status
Simulation time 47552540 ps
CPU time 1.37 seconds
Started Apr 15 02:21:30 PM PDT 24
Finished Apr 15 02:21:32 PM PDT 24
Peak memory 216296 kb
Host smart-d622e267-dc40-4612-bdce-33581aea6a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054763440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2054763440
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1045553322
Short name T38
Test name
Test status
Simulation time 37194507 ps
CPU time 1.74 seconds
Started Apr 15 02:21:30 PM PDT 24
Finished Apr 15 02:21:32 PM PDT 24
Peak memory 216196 kb
Host smart-8f6ec53b-225d-4495-8d0f-0327d978ca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045553322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1045553322
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1389560611
Short name T774
Test name
Test status
Simulation time 118842838 ps
CPU time 1.13 seconds
Started Apr 15 02:21:27 PM PDT 24
Finished Apr 15 02:21:29 PM PDT 24
Peak memory 219188 kb
Host smart-c1c45c7e-e2f3-4645-ac68-893b9ebc1d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389560611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1389560611
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2802192528
Short name T121
Test name
Test status
Simulation time 90939358 ps
CPU time 1.23 seconds
Started Apr 15 02:19:20 PM PDT 24
Finished Apr 15 02:19:22 PM PDT 24
Peak memory 215288 kb
Host smart-69256cae-f84d-4302-ba88-db2ed8ac6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802192528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2802192528
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2419582621
Short name T417
Test name
Test status
Simulation time 20434057 ps
CPU time 0.96 seconds
Started Apr 15 02:19:20 PM PDT 24
Finished Apr 15 02:19:21 PM PDT 24
Peak memory 206324 kb
Host smart-fd6eb9e2-34ab-459d-abfb-7c82667e1c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419582621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2419582621
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1357488290
Short name T706
Test name
Test status
Simulation time 15099582 ps
CPU time 0.89 seconds
Started Apr 15 02:19:17 PM PDT 24
Finished Apr 15 02:19:19 PM PDT 24
Peak memory 215756 kb
Host smart-225a7c55-2f7c-46ce-bda8-5b1466502948
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357488290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1357488290
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3579939990
Short name T429
Test name
Test status
Simulation time 99843383 ps
CPU time 1.03 seconds
Started Apr 15 02:19:18 PM PDT 24
Finished Apr 15 02:19:20 PM PDT 24
Peak memory 217300 kb
Host smart-c52879c1-7c53-445b-8cba-fe51f3ddbb15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579939990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3579939990
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2949898681
Short name T90
Test name
Test status
Simulation time 28535503 ps
CPU time 1.28 seconds
Started Apr 15 02:19:16 PM PDT 24
Finished Apr 15 02:19:17 PM PDT 24
Peak memory 229492 kb
Host smart-9b4eb8b0-1a94-4a8e-ba91-ae313e515a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949898681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2949898681
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3984625718
Short name T475
Test name
Test status
Simulation time 194098312 ps
CPU time 1.1 seconds
Started Apr 15 02:19:16 PM PDT 24
Finished Apr 15 02:19:18 PM PDT 24
Peak memory 215012 kb
Host smart-920ad9a1-43e0-47cf-b21e-a85544cb3ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984625718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3984625718
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.1439913116
Short name T435
Test name
Test status
Simulation time 47334302 ps
CPU time 0.87 seconds
Started Apr 15 02:19:18 PM PDT 24
Finished Apr 15 02:19:19 PM PDT 24
Peak memory 214876 kb
Host smart-fda66acf-475c-4b2b-9963-9527b924f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439913116 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1439913116
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4198907650
Short name T792
Test name
Test status
Simulation time 1161992080 ps
CPU time 2.69 seconds
Started Apr 15 02:19:20 PM PDT 24
Finished Apr 15 02:19:23 PM PDT 24
Peak memory 214892 kb
Host smart-59e4af14-b14c-4aa2-bd30-14ed59a023c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198907650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4198907650
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.548273674
Short name T403
Test name
Test status
Simulation time 121950413313 ps
CPU time 715.31 seconds
Started Apr 15 02:19:18 PM PDT 24
Finished Apr 15 02:31:14 PM PDT 24
Peak memory 219068 kb
Host smart-6b7491a9-5c79-47bf-8d51-cb056069895f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548273674 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.548273674
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3528439311
Short name T214
Test name
Test status
Simulation time 60245944 ps
CPU time 2.24 seconds
Started Apr 15 02:21:29 PM PDT 24
Finished Apr 15 02:21:32 PM PDT 24
Peak memory 219072 kb
Host smart-4e39a133-454a-42dc-98f3-3c5a75afae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528439311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3528439311
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1054222786
Short name T407
Test name
Test status
Simulation time 288273738 ps
CPU time 3.83 seconds
Started Apr 15 02:21:33 PM PDT 24
Finished Apr 15 02:21:37 PM PDT 24
Peak memory 219204 kb
Host smart-92cdf9d5-d7d5-43d4-8d00-0109bfa57633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054222786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1054222786
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.654186171
Short name T632
Test name
Test status
Simulation time 44861601 ps
CPU time 1.09 seconds
Started Apr 15 02:21:33 PM PDT 24
Finished Apr 15 02:21:34 PM PDT 24
Peak memory 214904 kb
Host smart-61191870-b295-4abd-8d90-d5752564ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654186171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.654186171
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3763310365
Short name T645
Test name
Test status
Simulation time 127140496 ps
CPU time 1.8 seconds
Started Apr 15 02:21:36 PM PDT 24
Finished Apr 15 02:21:39 PM PDT 24
Peak memory 219368 kb
Host smart-f5de0b60-c5bc-4bbb-9833-eeeb3821f0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763310365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3763310365
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.141266188
Short name T11
Test name
Test status
Simulation time 95244682 ps
CPU time 1.11 seconds
Started Apr 15 02:21:31 PM PDT 24
Finished Apr 15 02:21:33 PM PDT 24
Peak memory 217740 kb
Host smart-0bf0f2a4-c364-4969-9ea0-ead7a100a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141266188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.141266188
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2812119074
Short name T828
Test name
Test status
Simulation time 47182075 ps
CPU time 1.5 seconds
Started Apr 15 02:21:33 PM PDT 24
Finished Apr 15 02:21:35 PM PDT 24
Peak memory 217428 kb
Host smart-7f646917-5aed-48e5-b7d2-ab2addda659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812119074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2812119074
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3662425735
Short name T716
Test name
Test status
Simulation time 41729711 ps
CPU time 1.12 seconds
Started Apr 15 02:21:32 PM PDT 24
Finished Apr 15 02:21:33 PM PDT 24
Peak memory 216496 kb
Host smart-755086ca-8f49-4f69-b74f-938dfa9c7c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662425735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3662425735
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3780630036
Short name T378
Test name
Test status
Simulation time 37167270 ps
CPU time 1.44 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:36 PM PDT 24
Peak memory 217268 kb
Host smart-2da851ad-f16b-4d07-8026-b0ef013cf4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780630036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3780630036
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3090352096
Short name T524
Test name
Test status
Simulation time 48088293 ps
CPU time 1.13 seconds
Started Apr 15 02:21:32 PM PDT 24
Finished Apr 15 02:21:34 PM PDT 24
Peak memory 218636 kb
Host smart-2a437c1b-2e1e-475e-bb4b-4a49dd687b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090352096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3090352096
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1150044842
Short name T309
Test name
Test status
Simulation time 37702828 ps
CPU time 1.09 seconds
Started Apr 15 02:19:23 PM PDT 24
Finished Apr 15 02:19:24 PM PDT 24
Peak memory 215400 kb
Host smart-0d278210-c8a1-4911-a58f-acbec17788ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150044842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1150044842
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.886699535
Short name T755
Test name
Test status
Simulation time 29625755 ps
CPU time 0.74 seconds
Started Apr 15 02:19:21 PM PDT 24
Finished Apr 15 02:19:23 PM PDT 24
Peak memory 205236 kb
Host smart-0d12a7cf-f779-40c2-bf13-8f097a731ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886699535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.886699535
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3363495091
Short name T554
Test name
Test status
Simulation time 17653088 ps
CPU time 0.82 seconds
Started Apr 15 02:19:24 PM PDT 24
Finished Apr 15 02:19:26 PM PDT 24
Peak memory 215144 kb
Host smart-2d21fe7e-9603-4a0a-9781-1c921ef83b59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363495091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3363495091
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2415903226
Short name T644
Test name
Test status
Simulation time 19389915 ps
CPU time 1 seconds
Started Apr 15 02:19:20 PM PDT 24
Finished Apr 15 02:19:22 PM PDT 24
Peak memory 217500 kb
Host smart-9a697302-fb96-4c34-b9a7-7269f5ed84e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415903226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2415903226
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2024158537
Short name T713
Test name
Test status
Simulation time 54407364 ps
CPU time 1.19 seconds
Started Apr 15 02:19:25 PM PDT 24
Finished Apr 15 02:19:26 PM PDT 24
Peak memory 216196 kb
Host smart-7a2878ff-087c-4da5-8a19-7ec850dfcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024158537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2024158537
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.3106116165
Short name T650
Test name
Test status
Simulation time 44677989 ps
CPU time 0.92 seconds
Started Apr 15 02:19:23 PM PDT 24
Finished Apr 15 02:19:25 PM PDT 24
Peak memory 214896 kb
Host smart-250d5be8-0ea4-4c88-b95f-0c2f96640b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106116165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3106116165
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1981993328
Short name T691
Test name
Test status
Simulation time 62449897 ps
CPU time 1.52 seconds
Started Apr 15 02:19:24 PM PDT 24
Finished Apr 15 02:19:26 PM PDT 24
Peak memory 216288 kb
Host smart-e4edace3-6ee7-4e47-8377-606ac57a9c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981993328 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1981993328
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3440284709
Short name T194
Test name
Test status
Simulation time 32235239914 ps
CPU time 832.61 seconds
Started Apr 15 02:19:20 PM PDT 24
Finished Apr 15 02:33:14 PM PDT 24
Peak memory 217260 kb
Host smart-a8a069f9-8412-47e6-8d64-477ee287a3e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440284709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3440284709
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2204107987
Short name T549
Test name
Test status
Simulation time 27333799 ps
CPU time 1.14 seconds
Started Apr 15 02:21:35 PM PDT 24
Finished Apr 15 02:21:37 PM PDT 24
Peak memory 216328 kb
Host smart-abd44923-6e2e-4e34-9929-9044ceb84eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204107987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2204107987
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.326700845
Short name T416
Test name
Test status
Simulation time 40139508 ps
CPU time 1.5 seconds
Started Apr 15 02:21:36 PM PDT 24
Finished Apr 15 02:21:39 PM PDT 24
Peak memory 217600 kb
Host smart-b9ed0314-9281-4ed9-b3c6-dc9197858d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326700845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.326700845
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2606211400
Short name T277
Test name
Test status
Simulation time 136886521 ps
CPU time 1.43 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:36 PM PDT 24
Peak memory 216304 kb
Host smart-2e764be5-a8ac-45ce-9e43-aff7cbdfc086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606211400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2606211400
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2792300258
Short name T427
Test name
Test status
Simulation time 94463343 ps
CPU time 1.44 seconds
Started Apr 15 02:21:32 PM PDT 24
Finished Apr 15 02:21:35 PM PDT 24
Peak memory 217896 kb
Host smart-dcd76b43-dc25-4932-83eb-3f333e6a1a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792300258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2792300258
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3538959257
Short name T425
Test name
Test status
Simulation time 35255660 ps
CPU time 1.55 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:36 PM PDT 24
Peak memory 217748 kb
Host smart-48872234-a357-46e3-be4a-91e8fb67f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538959257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3538959257
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2251449189
Short name T597
Test name
Test status
Simulation time 59778318 ps
CPU time 1.58 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:36 PM PDT 24
Peak memory 217748 kb
Host smart-8be83469-62bb-4a98-8758-6b70a8bcce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251449189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2251449189
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3620627013
Short name T56
Test name
Test status
Simulation time 58191229 ps
CPU time 1.09 seconds
Started Apr 15 02:21:32 PM PDT 24
Finished Apr 15 02:21:34 PM PDT 24
Peak memory 217652 kb
Host smart-3f36e1ea-56ba-425d-8e39-9499cf8b8c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620627013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3620627013
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2070789648
Short name T760
Test name
Test status
Simulation time 48887570 ps
CPU time 1.11 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:36 PM PDT 24
Peak memory 216192 kb
Host smart-e197034a-7338-47b1-8aa9-08a13cc12e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070789648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2070789648
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1665925067
Short name T709
Test name
Test status
Simulation time 39785735 ps
CPU time 1.64 seconds
Started Apr 15 02:21:33 PM PDT 24
Finished Apr 15 02:21:35 PM PDT 24
Peak memory 217504 kb
Host smart-d5a7fe89-bff8-4079-b9f0-0837b1204add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665925067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1665925067
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2246564658
Short name T15
Test name
Test status
Simulation time 27376985 ps
CPU time 1.24 seconds
Started Apr 15 02:15:43 PM PDT 24
Finished Apr 15 02:15:45 PM PDT 24
Peak memory 215292 kb
Host smart-488ff475-9320-463c-bafa-d97e661c25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246564658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2246564658
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3403085422
Short name T373
Test name
Test status
Simulation time 28338554 ps
CPU time 0.98 seconds
Started Apr 15 02:15:51 PM PDT 24
Finished Apr 15 02:15:53 PM PDT 24
Peak memory 206608 kb
Host smart-31d4fa95-279d-4ebf-b38d-86f8be2daac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403085422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3403085422
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.683003067
Short name T397
Test name
Test status
Simulation time 36031692 ps
CPU time 0.81 seconds
Started Apr 15 02:15:51 PM PDT 24
Finished Apr 15 02:15:53 PM PDT 24
Peak memory 215604 kb
Host smart-1a0441b8-063b-4f8e-85b6-3d301759bafd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683003067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.683003067
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3134810202
Short name T738
Test name
Test status
Simulation time 43049489 ps
CPU time 1.01 seconds
Started Apr 15 02:15:50 PM PDT 24
Finished Apr 15 02:15:53 PM PDT 24
Peak memory 217456 kb
Host smart-98e24164-e5dd-4308-94d3-1dd827ba4715
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134810202 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3134810202
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.601958873
Short name T66
Test name
Test status
Simulation time 23658600 ps
CPU time 1.13 seconds
Started Apr 15 02:15:43 PM PDT 24
Finished Apr 15 02:15:44 PM PDT 24
Peak memory 219040 kb
Host smart-e5aaceff-a81c-4eed-8ce9-1a42329b4214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601958873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.601958873
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.979229921
Short name T351
Test name
Test status
Simulation time 188057981 ps
CPU time 1.14 seconds
Started Apr 15 02:15:38 PM PDT 24
Finished Apr 15 02:15:40 PM PDT 24
Peak memory 219048 kb
Host smart-8d2ca7d8-d842-4191-b21e-be7667ec9f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979229921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.979229921
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1762106492
Short name T705
Test name
Test status
Simulation time 32698581 ps
CPU time 0.85 seconds
Started Apr 15 02:15:42 PM PDT 24
Finished Apr 15 02:15:43 PM PDT 24
Peak memory 215212 kb
Host smart-d3edc570-1eaf-4594-8afb-b40a0e7b59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762106492 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1762106492
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.3061301026
Short name T471
Test name
Test status
Simulation time 44770770 ps
CPU time 0.85 seconds
Started Apr 15 02:15:39 PM PDT 24
Finished Apr 15 02:15:40 PM PDT 24
Peak memory 214840 kb
Host smart-314506ed-9476-499b-a162-bbe4d2bbd730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061301026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3061301026
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2292734475
Short name T363
Test name
Test status
Simulation time 145839699 ps
CPU time 1.08 seconds
Started Apr 15 02:15:39 PM PDT 24
Finished Apr 15 02:15:40 PM PDT 24
Peak memory 216216 kb
Host smart-08b48b6c-da73-475b-9ec1-84dc96ef86ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292734475 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2292734475
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.279111857
Short name T678
Test name
Test status
Simulation time 56958692463 ps
CPU time 1308.17 seconds
Started Apr 15 02:15:41 PM PDT 24
Finished Apr 15 02:37:29 PM PDT 24
Peak memory 220332 kb
Host smart-1f04c2d7-7a0e-42c8-b919-aea509255a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279111857 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.279111857
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1085504134
Short name T179
Test name
Test status
Simulation time 106785941 ps
CPU time 1.39 seconds
Started Apr 15 02:19:26 PM PDT 24
Finished Apr 15 02:19:27 PM PDT 24
Peak memory 215276 kb
Host smart-decf103d-1dab-4703-b57e-66218e765874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085504134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1085504134
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2114808635
Short name T559
Test name
Test status
Simulation time 53217823 ps
CPU time 0.85 seconds
Started Apr 15 02:19:26 PM PDT 24
Finished Apr 15 02:19:28 PM PDT 24
Peak memory 206584 kb
Host smart-455f2f26-48fa-4c04-b2ca-d975483cd4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114808635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2114808635
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.1193452924
Short name T527
Test name
Test status
Simulation time 22445212 ps
CPU time 1.15 seconds
Started Apr 15 02:19:27 PM PDT 24
Finished Apr 15 02:19:29 PM PDT 24
Peak memory 219020 kb
Host smart-cdae9232-45a3-4910-bd83-70f9f9acb862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193452924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1193452924
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4037617272
Short name T576
Test name
Test status
Simulation time 36140102 ps
CPU time 1.35 seconds
Started Apr 15 02:19:24 PM PDT 24
Finished Apr 15 02:19:26 PM PDT 24
Peak memory 216516 kb
Host smart-4c66b79b-8af5-48e2-8cb9-a90dd66a3618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037617272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4037617272
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1661688548
Short name T59
Test name
Test status
Simulation time 21982070 ps
CPU time 1.06 seconds
Started Apr 15 02:19:24 PM PDT 24
Finished Apr 15 02:19:26 PM PDT 24
Peak memory 215440 kb
Host smart-fd4bc3d8-19df-4567-842b-9a4641b2620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661688548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1661688548
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2817639233
Short name T383
Test name
Test status
Simulation time 25354930 ps
CPU time 0.91 seconds
Started Apr 15 02:19:24 PM PDT 24
Finished Apr 15 02:19:25 PM PDT 24
Peak memory 214912 kb
Host smart-2df92b31-6046-428a-969c-4d58571cd826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817639233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2817639233
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2199470215
Short name T389
Test name
Test status
Simulation time 788631714 ps
CPU time 4.17 seconds
Started Apr 15 02:19:22 PM PDT 24
Finished Apr 15 02:19:27 PM PDT 24
Peak memory 214948 kb
Host smart-c26affd8-eb65-4add-8752-ae5105628272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199470215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2199470215
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3313444933
Short name T203
Test name
Test status
Simulation time 246791604886 ps
CPU time 1239.18 seconds
Started Apr 15 02:19:21 PM PDT 24
Finished Apr 15 02:40:01 PM PDT 24
Peak memory 220788 kb
Host smart-3eeabd1b-23c5-4ed4-8b7b-6e02562844e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313444933 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3313444933
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1568650609
Short name T183
Test name
Test status
Simulation time 25267802 ps
CPU time 1.2 seconds
Started Apr 15 02:19:27 PM PDT 24
Finished Apr 15 02:19:28 PM PDT 24
Peak memory 215256 kb
Host smart-8f2ed6c6-b62a-4aff-b05c-6705bc2a5606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568650609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1568650609
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.355122048
Short name T553
Test name
Test status
Simulation time 49619463 ps
CPU time 0.78 seconds
Started Apr 15 02:19:31 PM PDT 24
Finished Apr 15 02:19:32 PM PDT 24
Peak memory 205432 kb
Host smart-f53a5b25-3118-4cd1-9fe1-57ba73a3a95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355122048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.355122048
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3828077740
Short name T170
Test name
Test status
Simulation time 22791471 ps
CPU time 0.86 seconds
Started Apr 15 02:19:27 PM PDT 24
Finished Apr 15 02:19:28 PM PDT 24
Peak memory 215316 kb
Host smart-f0dad629-7945-4eec-8c2b-994912c03d21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828077740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3828077740
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1860599987
Short name T172
Test name
Test status
Simulation time 138380274 ps
CPU time 1.11 seconds
Started Apr 15 02:19:28 PM PDT 24
Finished Apr 15 02:19:29 PM PDT 24
Peak memory 216036 kb
Host smart-eed0170c-f581-4268-ba85-fb1fcb4abb6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860599987 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1860599987
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.556951131
Short name T617
Test name
Test status
Simulation time 22769004 ps
CPU time 0.9 seconds
Started Apr 15 02:19:25 PM PDT 24
Finished Apr 15 02:19:27 PM PDT 24
Peak memory 217836 kb
Host smart-bcf89de5-1b15-473e-a1a6-9c6eeab8955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556951131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.556951131
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2686085819
Short name T489
Test name
Test status
Simulation time 25528994 ps
CPU time 1.2 seconds
Started Apr 15 02:19:26 PM PDT 24
Finished Apr 15 02:19:27 PM PDT 24
Peak memory 216460 kb
Host smart-6e7e2ce8-6e9c-4c6b-92ab-bf83bb6e2958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686085819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2686085819
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1365490780
Short name T780
Test name
Test status
Simulation time 28953350 ps
CPU time 0.93 seconds
Started Apr 15 02:19:27 PM PDT 24
Finished Apr 15 02:19:29 PM PDT 24
Peak memory 215084 kb
Host smart-984933ff-6e61-4a51-b33c-7e55abbbb538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365490780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1365490780
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1972935099
Short name T490
Test name
Test status
Simulation time 26891534 ps
CPU time 0.94 seconds
Started Apr 15 02:19:26 PM PDT 24
Finished Apr 15 02:19:28 PM PDT 24
Peak memory 206720 kb
Host smart-634f3d79-1895-4a84-81a0-a23174cbec94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972935099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1972935099
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4037110206
Short name T710
Test name
Test status
Simulation time 387894551 ps
CPU time 1.46 seconds
Started Apr 15 02:19:27 PM PDT 24
Finished Apr 15 02:19:29 PM PDT 24
Peak memory 214832 kb
Host smart-0cd5ee85-9a62-48c3-91c4-69e6efcc4040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037110206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4037110206
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2197985037
Short name T619
Test name
Test status
Simulation time 682862337742 ps
CPU time 1571.58 seconds
Started Apr 15 02:19:25 PM PDT 24
Finished Apr 15 02:45:37 PM PDT 24
Peak memory 221548 kb
Host smart-5f60f787-1f4d-442b-bfc2-4a3f9fd87e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197985037 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2197985037
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.2619615145
Short name T622
Test name
Test status
Simulation time 29869354 ps
CPU time 0.84 seconds
Started Apr 15 02:19:41 PM PDT 24
Finished Apr 15 02:19:42 PM PDT 24
Peak memory 205708 kb
Host smart-ed980220-7606-46c0-b557-7411f6a5a851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619615145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2619615145
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1694923560
Short name T119
Test name
Test status
Simulation time 13679853 ps
CPU time 0.92 seconds
Started Apr 15 02:19:38 PM PDT 24
Finished Apr 15 02:19:40 PM PDT 24
Peak memory 215580 kb
Host smart-0eea8e02-86b5-49d7-b3de-84e34b3d75cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694923560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1694923560
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.703929379
Short name T80
Test name
Test status
Simulation time 66922656 ps
CPU time 1.07 seconds
Started Apr 15 02:19:37 PM PDT 24
Finished Apr 15 02:19:39 PM PDT 24
Peak memory 216152 kb
Host smart-42870e79-82cf-410b-af98-3314791e61da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703929379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.703929379
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1739902184
Short name T116
Test name
Test status
Simulation time 18603814 ps
CPU time 1.04 seconds
Started Apr 15 02:19:36 PM PDT 24
Finished Apr 15 02:19:38 PM PDT 24
Peak memory 217624 kb
Host smart-c0f76094-8e19-48ee-8e1c-35628f01d053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739902184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1739902184
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3030223608
Short name T474
Test name
Test status
Simulation time 268191938 ps
CPU time 3.62 seconds
Started Apr 15 02:19:37 PM PDT 24
Finished Apr 15 02:19:41 PM PDT 24
Peak memory 216564 kb
Host smart-b48b8afa-e6f3-42b9-bc5f-b5255ce6b30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030223608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3030223608
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2081394268
Short name T502
Test name
Test status
Simulation time 20338875 ps
CPU time 1.06 seconds
Started Apr 15 02:19:37 PM PDT 24
Finished Apr 15 02:19:39 PM PDT 24
Peak memory 215380 kb
Host smart-587b4a56-d6b4-41ed-9cc8-832b708ba3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081394268 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2081394268
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3154005853
Short name T672
Test name
Test status
Simulation time 19310685 ps
CPU time 0.93 seconds
Started Apr 15 02:19:32 PM PDT 24
Finished Apr 15 02:19:33 PM PDT 24
Peak memory 206676 kb
Host smart-1cb295a9-d15c-4f3c-968a-e7bbd9dddd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154005853 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3154005853
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1717293171
Short name T225
Test name
Test status
Simulation time 422517195 ps
CPU time 4.33 seconds
Started Apr 15 02:19:30 PM PDT 24
Finished Apr 15 02:19:35 PM PDT 24
Peak memory 216408 kb
Host smart-342a3b9b-0cb6-4504-b802-b7e3906c4d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717293171 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1717293171
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1606932864
Short name T818
Test name
Test status
Simulation time 77324282011 ps
CPU time 450.69 seconds
Started Apr 15 02:19:30 PM PDT 24
Finished Apr 15 02:27:01 PM PDT 24
Peak memory 217524 kb
Host smart-ce1d8ea8-2a4a-4208-9d14-3d55a738c6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606932864 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1606932864
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3932516232
Short name T103
Test name
Test status
Simulation time 92194126 ps
CPU time 1.12 seconds
Started Apr 15 02:19:38 PM PDT 24
Finished Apr 15 02:19:41 PM PDT 24
Peak memory 215204 kb
Host smart-2ea7c6b5-4793-43e7-9c22-b73a4a99a62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932516232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3932516232
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.264025399
Short name T765
Test name
Test status
Simulation time 52124672 ps
CPU time 0.85 seconds
Started Apr 15 02:19:39 PM PDT 24
Finished Apr 15 02:19:40 PM PDT 24
Peak memory 205684 kb
Host smart-b16ac0f0-9136-4f74-a5da-872a23d3d69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264025399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.264025399
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3391790004
Short name T555
Test name
Test status
Simulation time 60994787 ps
CPU time 0.81 seconds
Started Apr 15 02:19:39 PM PDT 24
Finished Apr 15 02:19:41 PM PDT 24
Peak memory 215200 kb
Host smart-f1c0ebe8-f46c-4425-bba2-951b831de277
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391790004 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3391790004
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.4204569742
Short name T747
Test name
Test status
Simulation time 21913435 ps
CPU time 1.24 seconds
Started Apr 15 02:19:35 PM PDT 24
Finished Apr 15 02:19:36 PM PDT 24
Peak memory 230948 kb
Host smart-83ce1f8d-5474-4cd1-8c3e-b4ce78ba664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204569742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.4204569742
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.559265303
Short name T317
Test name
Test status
Simulation time 491434826 ps
CPU time 4.13 seconds
Started Apr 15 02:19:36 PM PDT 24
Finished Apr 15 02:19:41 PM PDT 24
Peak memory 217644 kb
Host smart-fcfe6358-141a-4660-9b4f-f94842b02b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559265303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.559265303
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.711445885
Short name T778
Test name
Test status
Simulation time 26706611 ps
CPU time 0.88 seconds
Started Apr 15 02:19:36 PM PDT 24
Finished Apr 15 02:19:37 PM PDT 24
Peak memory 215268 kb
Host smart-9eefb9d9-7c1f-4c30-bd2f-5f42a76e799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711445885 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.711445885
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3548356562
Short name T601
Test name
Test status
Simulation time 27751551 ps
CPU time 0.92 seconds
Started Apr 15 02:19:36 PM PDT 24
Finished Apr 15 02:19:38 PM PDT 24
Peak memory 214912 kb
Host smart-4c1a4381-d84c-48d2-83b5-2633c4bd03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548356562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3548356562
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2604816319
Short name T457
Test name
Test status
Simulation time 254813382 ps
CPU time 5.18 seconds
Started Apr 15 02:19:37 PM PDT 24
Finished Apr 15 02:19:43 PM PDT 24
Peak memory 215016 kb
Host smart-1c50795c-6e16-418b-8b5d-e54c44128ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604816319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2604816319
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.253926925
Short name T640
Test name
Test status
Simulation time 47128376657 ps
CPU time 536.21 seconds
Started Apr 15 02:19:36 PM PDT 24
Finished Apr 15 02:28:32 PM PDT 24
Peak memory 223392 kb
Host smart-2d2e9bf9-e9fd-4649-9a5f-dc9100c5dfaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253926925 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.253926925
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2247205927
Short name T180
Test name
Test status
Simulation time 96395822 ps
CPU time 1.18 seconds
Started Apr 15 02:19:39 PM PDT 24
Finished Apr 15 02:19:41 PM PDT 24
Peak memory 215316 kb
Host smart-fe8a10b9-f21a-4c28-9291-25adcc0bdfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247205927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2247205927
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3401094067
Short name T795
Test name
Test status
Simulation time 35824710 ps
CPU time 0.94 seconds
Started Apr 15 02:19:44 PM PDT 24
Finished Apr 15 02:19:46 PM PDT 24
Peak memory 205776 kb
Host smart-dcb41df1-5027-451c-a145-4f103be45c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401094067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3401094067
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3947209974
Short name T109
Test name
Test status
Simulation time 10963955 ps
CPU time 0.86 seconds
Started Apr 15 02:19:41 PM PDT 24
Finished Apr 15 02:19:43 PM PDT 24
Peak memory 215672 kb
Host smart-093bb602-baa6-4080-bcfb-8fc5d4316722
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947209974 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3947209974
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.804244997
Short name T168
Test name
Test status
Simulation time 125482855 ps
CPU time 1.1 seconds
Started Apr 15 02:19:41 PM PDT 24
Finished Apr 15 02:19:42 PM PDT 24
Peak memory 216092 kb
Host smart-c04e3702-389d-47f5-91f4-0f4da42da0ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804244997 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.804244997
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2063057491
Short name T67
Test name
Test status
Simulation time 85190500 ps
CPU time 0.97 seconds
Started Apr 15 02:19:41 PM PDT 24
Finished Apr 15 02:19:43 PM PDT 24
Peak memory 218816 kb
Host smart-eca88b5f-ffc3-4a77-a4ea-96b63e74ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063057491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2063057491
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3998134193
Short name T503
Test name
Test status
Simulation time 27227927 ps
CPU time 1.23 seconds
Started Apr 15 02:19:41 PM PDT 24
Finished Apr 15 02:19:42 PM PDT 24
Peak memory 216216 kb
Host smart-ebca4dce-3d9c-4f8b-95a7-fd9365472d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998134193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3998134193
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1199047683
Short name T483
Test name
Test status
Simulation time 39097079 ps
CPU time 0.86 seconds
Started Apr 15 02:19:42 PM PDT 24
Finished Apr 15 02:19:43 PM PDT 24
Peak memory 215012 kb
Host smart-e53dbd06-3d8f-4c13-9faa-84265d8fcb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199047683 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1199047683
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.37089247
Short name T460
Test name
Test status
Simulation time 29954622 ps
CPU time 0.95 seconds
Started Apr 15 02:19:41 PM PDT 24
Finished Apr 15 02:19:42 PM PDT 24
Peak memory 214828 kb
Host smart-8b76ae33-a053-4e7d-a045-5db5af4ab483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37089247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.37089247
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4237979023
Short name T228
Test name
Test status
Simulation time 529101301 ps
CPU time 5.82 seconds
Started Apr 15 02:19:44 PM PDT 24
Finished Apr 15 02:19:50 PM PDT 24
Peak memory 214892 kb
Host smart-48a6bd14-dc46-488f-be91-23a9eb1e405b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237979023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4237979023
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2577187923
Short name T441
Test name
Test status
Simulation time 49275154122 ps
CPU time 588.43 seconds
Started Apr 15 02:19:39 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 217840 kb
Host smart-0d77a611-1db2-4996-b698-49068ccf53f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577187923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2577187923
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.2765535687
Short name T452
Test name
Test status
Simulation time 26157382 ps
CPU time 0.87 seconds
Started Apr 15 02:19:47 PM PDT 24
Finished Apr 15 02:19:48 PM PDT 24
Peak memory 206356 kb
Host smart-f32bef4e-1290-47b5-a335-605a10bfdf77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765535687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2765535687
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.432363816
Short name T677
Test name
Test status
Simulation time 14012814 ps
CPU time 0.88 seconds
Started Apr 15 02:19:47 PM PDT 24
Finished Apr 15 02:19:48 PM PDT 24
Peak memory 215500 kb
Host smart-40f1146c-432a-49c5-bac3-1ea18065f441
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432363816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.432363816
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1291218787
Short name T79
Test name
Test status
Simulation time 200925119 ps
CPU time 1 seconds
Started Apr 15 02:19:44 PM PDT 24
Finished Apr 15 02:19:46 PM PDT 24
Peak memory 216092 kb
Host smart-a783a040-f57a-479b-92ae-cd9e3e127a04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291218787 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1291218787
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4282600137
Short name T806
Test name
Test status
Simulation time 126522808 ps
CPU time 1.02 seconds
Started Apr 15 02:19:46 PM PDT 24
Finished Apr 15 02:19:47 PM PDT 24
Peak memory 219900 kb
Host smart-b9ef3b9e-d1f1-41e3-8167-4550f6c24a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282600137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4282600137
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.262763258
Short name T815
Test name
Test status
Simulation time 44214529 ps
CPU time 1.51 seconds
Started Apr 15 02:19:43 PM PDT 24
Finished Apr 15 02:19:45 PM PDT 24
Peak memory 218944 kb
Host smart-c8f3846b-14c4-4d53-895c-b9d5acf31094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262763258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.262763258
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1155305871
Short name T437
Test name
Test status
Simulation time 24664599 ps
CPU time 1.04 seconds
Started Apr 15 02:19:45 PM PDT 24
Finished Apr 15 02:19:46 PM PDT 24
Peak memory 223648 kb
Host smart-a3ec283d-f554-4c4e-a168-8ad5a756e9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155305871 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1155305871
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1859672294
Short name T548
Test name
Test status
Simulation time 27693287 ps
CPU time 0.89 seconds
Started Apr 15 02:19:43 PM PDT 24
Finished Apr 15 02:19:44 PM PDT 24
Peak memory 214848 kb
Host smart-be08477e-0140-4990-ae8c-5af53951a42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859672294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1859672294
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.205880172
Short name T380
Test name
Test status
Simulation time 136304718082 ps
CPU time 1613.47 seconds
Started Apr 15 02:19:47 PM PDT 24
Finished Apr 15 02:46:41 PM PDT 24
Peak memory 226388 kb
Host smart-ac3b926b-f84a-4029-9240-e4b607ddae01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205880172 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.205880172
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert_test.170360004
Short name T371
Test name
Test status
Simulation time 35660229 ps
CPU time 1.02 seconds
Started Apr 15 02:19:48 PM PDT 24
Finished Apr 15 02:19:49 PM PDT 24
Peak memory 205800 kb
Host smart-a50b4d12-691f-4fe3-a345-90d7f1c378a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170360004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.170360004
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2146271380
Short name T187
Test name
Test status
Simulation time 11128633 ps
CPU time 0.86 seconds
Started Apr 15 02:19:48 PM PDT 24
Finished Apr 15 02:19:50 PM PDT 24
Peak memory 215488 kb
Host smart-4628ba2c-fb47-4bb2-9762-5edfcf3e60db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146271380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2146271380
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2467543797
Short name T512
Test name
Test status
Simulation time 77010534 ps
CPU time 1.2 seconds
Started Apr 15 02:19:59 PM PDT 24
Finished Apr 15 02:20:01 PM PDT 24
Peak memory 216148 kb
Host smart-e3e6ee15-27b5-4654-a598-0e2b4993256c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467543797 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2467543797
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2689743298
Short name T117
Test name
Test status
Simulation time 18882823 ps
CPU time 1.02 seconds
Started Apr 15 02:19:49 PM PDT 24
Finished Apr 15 02:19:51 PM PDT 24
Peak memory 217828 kb
Host smart-984d50a4-1fd7-4cc6-827c-44c5b8c7463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689743298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2689743298
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3498459947
Short name T315
Test name
Test status
Simulation time 34871342 ps
CPU time 1.26 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 216488 kb
Host smart-01a47f9e-d6b6-4552-8a6f-8fe4e0b7c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498459947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3498459947
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.462907998
Short name T603
Test name
Test status
Simulation time 38184972 ps
CPU time 0.88 seconds
Started Apr 15 02:19:59 PM PDT 24
Finished Apr 15 02:20:01 PM PDT 24
Peak memory 215432 kb
Host smart-50cebe0e-0b97-45a9-bb0a-e7e050eabb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462907998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.462907998
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3767575912
Short name T649
Test name
Test status
Simulation time 23267913 ps
CPU time 0.97 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:00 PM PDT 24
Peak memory 214920 kb
Host smart-f70834ed-7c0e-41f9-8012-562245a3a63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767575912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3767575912
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3208666381
Short name T695
Test name
Test status
Simulation time 295399597 ps
CPU time 5.91 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:05 PM PDT 24
Peak memory 216424 kb
Host smart-a69bc292-03be-408c-8ed0-56f737acc6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208666381 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3208666381
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1177897966
Short name T369
Test name
Test status
Simulation time 65388081249 ps
CPU time 890.68 seconds
Started Apr 15 02:19:45 PM PDT 24
Finished Apr 15 02:34:36 PM PDT 24
Peak memory 218656 kb
Host smart-aae2a9bc-9149-4fe3-9a74-a6588b78ad09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177897966 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1177897966
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1751035506
Short name T263
Test name
Test status
Simulation time 26709660 ps
CPU time 1.26 seconds
Started Apr 15 02:19:50 PM PDT 24
Finished Apr 15 02:19:52 PM PDT 24
Peak memory 215280 kb
Host smart-9f25fb46-7152-490d-bd93-81bf42d013f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751035506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1751035506
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1631186916
Short name T40
Test name
Test status
Simulation time 21751350 ps
CPU time 0.81 seconds
Started Apr 15 02:19:46 PM PDT 24
Finished Apr 15 02:19:48 PM PDT 24
Peak memory 206572 kb
Host smart-324bff26-2d7f-4688-a7e8-c4599d7a6dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631186916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1631186916
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.588795471
Short name T69
Test name
Test status
Simulation time 112160198 ps
CPU time 1.21 seconds
Started Apr 15 02:19:57 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 216136 kb
Host smart-76d797b3-da57-4d5a-af2b-f5e7c3340fe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588795471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.588795471
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4026286261
Short name T100
Test name
Test status
Simulation time 23176345 ps
CPU time 0.93 seconds
Started Apr 15 02:19:49 PM PDT 24
Finished Apr 15 02:19:50 PM PDT 24
Peak memory 217844 kb
Host smart-cbb4cc8c-e12f-473b-a26e-e866b3ba47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026286261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4026286261
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.378475035
Short name T484
Test name
Test status
Simulation time 46763525 ps
CPU time 1.66 seconds
Started Apr 15 02:19:59 PM PDT 24
Finished Apr 15 02:20:02 PM PDT 24
Peak memory 216296 kb
Host smart-66d6ea09-ef78-4a59-ae60-d5b6c2d643ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378475035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.378475035
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2628374561
Short name T725
Test name
Test status
Simulation time 24864837 ps
CPU time 0.9 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 215112 kb
Host smart-cbcb2b54-94ee-4364-abd0-a7874c8eeb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628374561 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2628374561
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1556416222
Short name T528
Test name
Test status
Simulation time 18701036 ps
CPU time 0.91 seconds
Started Apr 15 02:19:50 PM PDT 24
Finished Apr 15 02:19:51 PM PDT 24
Peak memory 214872 kb
Host smart-e5bef7c3-9502-4d2b-98cd-e4af8a403f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556416222 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1556416222
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1906079417
Short name T692
Test name
Test status
Simulation time 169006266 ps
CPU time 1.93 seconds
Started Apr 15 02:19:48 PM PDT 24
Finished Apr 15 02:19:51 PM PDT 24
Peak memory 214808 kb
Host smart-ef819eae-c98f-4599-90f3-5423f722484c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906079417 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1906079417
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3885553900
Short name T24
Test name
Test status
Simulation time 40631356191 ps
CPU time 910.91 seconds
Started Apr 15 02:19:48 PM PDT 24
Finished Apr 15 02:34:59 PM PDT 24
Peak memory 216928 kb
Host smart-7c4d69a6-fb22-48d6-904d-d72502447006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885553900 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3885553900
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2708741429
Short name T495
Test name
Test status
Simulation time 47941134 ps
CPU time 1.15 seconds
Started Apr 15 02:19:47 PM PDT 24
Finished Apr 15 02:19:49 PM PDT 24
Peak memory 215236 kb
Host smart-920ab5b2-ad69-4d6c-a5d6-adfb4280fe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708741429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2708741429
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3351602508
Short name T501
Test name
Test status
Simulation time 108289379 ps
CPU time 2.16 seconds
Started Apr 15 02:19:55 PM PDT 24
Finished Apr 15 02:19:58 PM PDT 24
Peak memory 206636 kb
Host smart-37891a13-b2f2-40e0-94b3-164ba31a1595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351602508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3351602508
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1970571982
Short name T421
Test name
Test status
Simulation time 28476370 ps
CPU time 0.78 seconds
Started Apr 15 02:19:51 PM PDT 24
Finished Apr 15 02:19:52 PM PDT 24
Peak memory 215172 kb
Host smart-2a83d4ff-61e5-4695-a2ed-a7c66ea7de8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970571982 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1970571982
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3246129580
Short name T519
Test name
Test status
Simulation time 36613217 ps
CPU time 0.97 seconds
Started Apr 15 02:19:51 PM PDT 24
Finished Apr 15 02:19:52 PM PDT 24
Peak memory 230788 kb
Host smart-a42e2488-332d-45ef-8746-d7a16a396d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246129580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3246129580
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2060883233
Short name T298
Test name
Test status
Simulation time 247514190 ps
CPU time 1.68 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:01 PM PDT 24
Peak memory 216492 kb
Host smart-faa9b0d1-5200-4bda-ba8c-95efa7199334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060883233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2060883233
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1707462560
Short name T60
Test name
Test status
Simulation time 28928097 ps
CPU time 0.81 seconds
Started Apr 15 02:19:48 PM PDT 24
Finished Apr 15 02:19:50 PM PDT 24
Peak memory 215316 kb
Host smart-00b6e5ac-ef9f-4b67-83d3-b9cbe922fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707462560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1707462560
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.833987003
Short name T321
Test name
Test status
Simulation time 22198304 ps
CPU time 0.92 seconds
Started Apr 15 02:19:50 PM PDT 24
Finished Apr 15 02:19:51 PM PDT 24
Peak memory 214868 kb
Host smart-68d9a527-c7c2-4fc9-9a79-0e18b650352d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833987003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.833987003
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.78800728
Short name T493
Test name
Test status
Simulation time 621014794 ps
CPU time 3.44 seconds
Started Apr 15 02:19:49 PM PDT 24
Finished Apr 15 02:19:54 PM PDT 24
Peak memory 219396 kb
Host smart-beea4fde-1db1-49ee-9a73-9579f676faf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78800728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.78800728
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1315150698
Short name T370
Test name
Test status
Simulation time 3614197942 ps
CPU time 92.9 seconds
Started Apr 15 02:19:49 PM PDT 24
Finished Apr 15 02:21:23 PM PDT 24
Peak memory 216784 kb
Host smart-18e8b854-2a24-49e3-9ad5-aeced6b4b062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315150698 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1315150698
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2849004898
Short name T306
Test name
Test status
Simulation time 45198054 ps
CPU time 1.2 seconds
Started Apr 15 02:19:52 PM PDT 24
Finished Apr 15 02:19:53 PM PDT 24
Peak memory 215288 kb
Host smart-28143949-c32a-4812-8b3e-a8b2393829cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849004898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2849004898
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2897747355
Short name T356
Test name
Test status
Simulation time 29414075 ps
CPU time 0.89 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:19:54 PM PDT 24
Peak memory 205844 kb
Host smart-a8241888-2bd6-4a84-8b32-043d2036e49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897747355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2897747355
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.4249758991
Short name T762
Test name
Test status
Simulation time 53061522 ps
CPU time 0.8 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:19:55 PM PDT 24
Peak memory 215256 kb
Host smart-19e1e2e1-42b2-4931-81f0-61f3d85238c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249758991 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.4249758991
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.309675765
Short name T385
Test name
Test status
Simulation time 27290968 ps
CPU time 0.85 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:19:55 PM PDT 24
Peak memory 217432 kb
Host smart-4f3092ee-678f-405c-a13d-f1ac5fc2df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309675765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.309675765
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1121456716
Short name T794
Test name
Test status
Simulation time 36382046 ps
CPU time 1.14 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:19:55 PM PDT 24
Peak memory 216336 kb
Host smart-21826b61-4e47-4311-b5fb-5065178373a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121456716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1121456716
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3091953898
Short name T646
Test name
Test status
Simulation time 128670693 ps
CPU time 0.81 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:19:55 PM PDT 24
Peak memory 215016 kb
Host smart-75321510-1e7d-4876-a7a0-b0903acc823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091953898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3091953898
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1104618403
Short name T533
Test name
Test status
Simulation time 19146276 ps
CPU time 0.92 seconds
Started Apr 15 02:19:51 PM PDT 24
Finished Apr 15 02:19:52 PM PDT 24
Peak memory 214916 kb
Host smart-0666836e-fbbb-4dc5-9a3b-bb508646a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104618403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1104618403
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.550218123
Short name T223
Test name
Test status
Simulation time 304560038 ps
CPU time 5.67 seconds
Started Apr 15 02:19:50 PM PDT 24
Finished Apr 15 02:19:56 PM PDT 24
Peak memory 216104 kb
Host smart-2efdae00-908c-4e46-9bc8-d674a710e95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550218123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.550218123
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.404693918
Short name T575
Test name
Test status
Simulation time 29332282755 ps
CPU time 529.44 seconds
Started Apr 15 02:19:54 PM PDT 24
Finished Apr 15 02:28:44 PM PDT 24
Peak memory 220540 kb
Host smart-28d1d2c3-0f31-4948-a642-c1c6ceba18bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404693918 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.404693918
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.965237608
Short name T679
Test name
Test status
Simulation time 79035254 ps
CPU time 1.14 seconds
Started Apr 15 02:16:05 PM PDT 24
Finished Apr 15 02:16:07 PM PDT 24
Peak memory 215272 kb
Host smart-ba04fd21-948a-41be-9db7-4c1550cbcbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965237608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.965237608
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.309572208
Short name T699
Test name
Test status
Simulation time 16901359 ps
CPU time 0.94 seconds
Started Apr 15 02:16:15 PM PDT 24
Finished Apr 15 02:16:17 PM PDT 24
Peak memory 206276 kb
Host smart-8debd646-bc89-44dd-8de5-73c8553250dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309572208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.309572208
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1396415089
Short name T329
Test name
Test status
Simulation time 32927101 ps
CPU time 0.8 seconds
Started Apr 15 02:16:09 PM PDT 24
Finished Apr 15 02:16:10 PM PDT 24
Peak memory 215212 kb
Host smart-324728ac-e122-43b9-a127-b7112a4cd365
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396415089 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1396415089
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1664309173
Short name T37
Test name
Test status
Simulation time 138385376 ps
CPU time 1 seconds
Started Apr 15 02:16:10 PM PDT 24
Finished Apr 15 02:16:11 PM PDT 24
Peak memory 216212 kb
Host smart-ca5dc0e8-7599-4e19-9ae2-32104717ae6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664309173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1664309173
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.261936760
Short name T745
Test name
Test status
Simulation time 20450613 ps
CPU time 1.19 seconds
Started Apr 15 02:16:10 PM PDT 24
Finished Apr 15 02:16:11 PM PDT 24
Peak memory 232076 kb
Host smart-83ef31ce-5205-4f82-a4b0-8fb909c2ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261936760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.261936760
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1150819458
Short name T772
Test name
Test status
Simulation time 42992936 ps
CPU time 1.09 seconds
Started Apr 15 02:16:19 PM PDT 24
Finished Apr 15 02:16:21 PM PDT 24
Peak memory 216332 kb
Host smart-37e59ce0-e5ee-4a0a-b4fe-8663feae3752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150819458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1150819458
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.4209532072
Short name T537
Test name
Test status
Simulation time 21125103 ps
CPU time 1.07 seconds
Started Apr 15 02:16:04 PM PDT 24
Finished Apr 15 02:16:06 PM PDT 24
Peak memory 215084 kb
Host smart-5ed71187-7871-4b8f-abf3-82082800d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209532072 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.4209532072
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.573045786
Short name T667
Test name
Test status
Simulation time 22821904 ps
CPU time 0.91 seconds
Started Apr 15 02:15:59 PM PDT 24
Finished Apr 15 02:16:01 PM PDT 24
Peak memory 206712 kb
Host smart-7c5929c6-7070-4f5b-97c8-f4de0e62e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573045786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.573045786
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3978999158
Short name T19
Test name
Test status
Simulation time 755263081 ps
CPU time 3.52 seconds
Started Apr 15 02:16:09 PM PDT 24
Finished Apr 15 02:16:13 PM PDT 24
Peak memory 234568 kb
Host smart-96c5c22d-b54a-47b2-a5ed-6134f6e37a18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978999158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3978999158
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1376169306
Short name T352
Test name
Test status
Simulation time 19848254 ps
CPU time 0.9 seconds
Started Apr 15 02:15:57 PM PDT 24
Finished Apr 15 02:15:58 PM PDT 24
Peak memory 214868 kb
Host smart-ee592b35-3d0f-414b-a0c4-878343875747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376169306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1376169306
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3670040793
Short name T565
Test name
Test status
Simulation time 240243541 ps
CPU time 2.86 seconds
Started Apr 15 02:16:02 PM PDT 24
Finished Apr 15 02:16:05 PM PDT 24
Peak memory 216072 kb
Host smart-9c08bfbb-0837-4c92-a0a9-a0107d21aa65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670040793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3670040793
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert_test.2096585545
Short name T447
Test name
Test status
Simulation time 26474668 ps
CPU time 0.88 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:19:58 PM PDT 24
Peak memory 205672 kb
Host smart-4e70764e-7002-4af6-a476-593fd0cf4590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096585545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2096585545
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4119883620
Short name T557
Test name
Test status
Simulation time 15968405 ps
CPU time 0.84 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:19:58 PM PDT 24
Peak memory 215484 kb
Host smart-13473f24-24eb-4624-8322-cb0244fb3ed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119883620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4119883620
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2564799676
Short name T92
Test name
Test status
Simulation time 135792752 ps
CPU time 1.04 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:19:57 PM PDT 24
Peak memory 217356 kb
Host smart-1230b2ea-c8b6-4c11-bf27-3aaa9c54dbbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564799676 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2564799676
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1192994800
Short name T164
Test name
Test status
Simulation time 19609164 ps
CPU time 1.09 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:19:58 PM PDT 24
Peak memory 232320 kb
Host smart-2aef2303-62e4-488b-8e5a-ccf6a5744ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192994800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1192994800
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2192328547
Short name T520
Test name
Test status
Simulation time 397122168 ps
CPU time 1.28 seconds
Started Apr 15 02:19:55 PM PDT 24
Finished Apr 15 02:19:57 PM PDT 24
Peak memory 217648 kb
Host smart-6bfe5134-b853-440f-b41b-85d002c2ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192328547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2192328547
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.157795020
Short name T128
Test name
Test status
Simulation time 38158567 ps
CPU time 0.91 seconds
Started Apr 15 02:19:54 PM PDT 24
Finished Apr 15 02:19:55 PM PDT 24
Peak memory 215252 kb
Host smart-5bca6b86-3d71-4e0e-b22a-f25025f97a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157795020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.157795020
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3412307360
Short name T396
Test name
Test status
Simulation time 49510587 ps
CPU time 0.95 seconds
Started Apr 15 02:19:54 PM PDT 24
Finished Apr 15 02:19:56 PM PDT 24
Peak memory 214872 kb
Host smart-b534f66d-13d5-4c27-80de-72f5862bb9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412307360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3412307360
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.328112601
Short name T224
Test name
Test status
Simulation time 137974855 ps
CPU time 2.94 seconds
Started Apr 15 02:19:52 PM PDT 24
Finished Apr 15 02:19:56 PM PDT 24
Peak memory 216444 kb
Host smart-2f9fb4ab-5e7d-43bf-8088-f86ebb80a72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328112601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.328112601
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.810085221
Short name T25
Test name
Test status
Simulation time 31560905733 ps
CPU time 543.41 seconds
Started Apr 15 02:19:53 PM PDT 24
Finished Apr 15 02:28:57 PM PDT 24
Peak memory 217288 kb
Host smart-17423983-ddb7-4236-9ed5-81f4dbf90ab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810085221 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.810085221
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3860598750
Short name T308
Test name
Test status
Simulation time 172229449 ps
CPU time 1.18 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 215276 kb
Host smart-0b6aaf15-382d-42e1-96d4-6266aaba9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860598750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3860598750
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3181836404
Short name T572
Test name
Test status
Simulation time 17852139 ps
CPU time 0.8 seconds
Started Apr 15 02:19:55 PM PDT 24
Finished Apr 15 02:19:56 PM PDT 24
Peak memory 205452 kb
Host smart-0178f341-6a8d-4516-9a6a-24566c46c0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181836404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3181836404
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3141150468
Short name T465
Test name
Test status
Simulation time 27686454 ps
CPU time 0.86 seconds
Started Apr 15 02:20:00 PM PDT 24
Finished Apr 15 02:20:01 PM PDT 24
Peak memory 215220 kb
Host smart-298d13a4-e1bf-46e6-b3f1-06defc0b0add
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141150468 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3141150468
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2841191882
Short name T87
Test name
Test status
Simulation time 41553555 ps
CPU time 1.28 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:20:00 PM PDT 24
Peak memory 216052 kb
Host smart-0ac45ee1-778b-42f9-a613-cdebb64ff6d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841191882 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2841191882
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3573432854
Short name T157
Test name
Test status
Simulation time 19510364 ps
CPU time 1.11 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:19:58 PM PDT 24
Peak memory 217820 kb
Host smart-589a88cb-b99e-4a4e-821b-450d84b597f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573432854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3573432854
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2264834612
Short name T788
Test name
Test status
Simulation time 40758588 ps
CPU time 1.62 seconds
Started Apr 15 02:19:57 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 219108 kb
Host smart-ce32cf7f-3e86-432a-a106-6eeb6c074f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264834612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2264834612
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3964636890
Short name T376
Test name
Test status
Simulation time 20905465 ps
CPU time 1.2 seconds
Started Apr 15 02:19:57 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 223692 kb
Host smart-cfed987a-1058-4466-99b0-fd427b3e6b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964636890 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3964636890
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4033655922
Short name T330
Test name
Test status
Simulation time 48983878 ps
CPU time 0.88 seconds
Started Apr 15 02:19:58 PM PDT 24
Finished Apr 15 02:19:59 PM PDT 24
Peak memory 214844 kb
Host smart-44d8abed-ace4-4d04-b24f-268ef14b0cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033655922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4033655922
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2329738554
Short name T648
Test name
Test status
Simulation time 562738881 ps
CPU time 3.16 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:20:00 PM PDT 24
Peak memory 216372 kb
Host smart-32d5a673-a983-430a-a167-13312ca2f008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329738554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2329738554
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3746779323
Short name T698
Test name
Test status
Simulation time 571552352339 ps
CPU time 1549.77 seconds
Started Apr 15 02:19:56 PM PDT 24
Finished Apr 15 02:45:47 PM PDT 24
Peak memory 222832 kb
Host smart-392558a2-0b52-4f9a-8032-7d11775fa45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746779323 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3746779323
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.534479780
Short name T120
Test name
Test status
Simulation time 120945206 ps
CPU time 1.24 seconds
Started Apr 15 02:20:01 PM PDT 24
Finished Apr 15 02:20:03 PM PDT 24
Peak memory 215216 kb
Host smart-dcb9f081-f09c-4621-92d0-6e19e16668e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534479780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.534479780
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2935660210
Short name T720
Test name
Test status
Simulation time 48456913 ps
CPU time 0.86 seconds
Started Apr 15 02:20:04 PM PDT 24
Finished Apr 15 02:20:06 PM PDT 24
Peak memory 205744 kb
Host smart-9bb1ed3d-91ff-4cfb-9948-9f93f77cc251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935660210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2935660210
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3139623848
Short name T759
Test name
Test status
Simulation time 16306512 ps
CPU time 0.87 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:03 PM PDT 24
Peak memory 215280 kb
Host smart-dc0678a3-71d1-4907-a6c4-d7ee8bc6ea72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139623848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3139623848
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.907050856
Short name T786
Test name
Test status
Simulation time 221939176 ps
CPU time 1.15 seconds
Started Apr 15 02:20:01 PM PDT 24
Finished Apr 15 02:20:02 PM PDT 24
Peak memory 216120 kb
Host smart-f989b854-8841-4c2a-b742-19226e88d411
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907050856 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.907050856
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2602296748
Short name T732
Test name
Test status
Simulation time 65198648 ps
CPU time 0.98 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:03 PM PDT 24
Peak memory 230752 kb
Host smart-95bf1e11-944e-4af0-b167-5c14b4169be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602296748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2602296748
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2953210184
Short name T776
Test name
Test status
Simulation time 51501365 ps
CPU time 1.55 seconds
Started Apr 15 02:20:01 PM PDT 24
Finished Apr 15 02:20:03 PM PDT 24
Peak memory 216484 kb
Host smart-515055e4-9155-4385-a5c9-ec4786f4b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953210184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2953210184
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.269489928
Short name T464
Test name
Test status
Simulation time 25305358 ps
CPU time 1.02 seconds
Started Apr 15 02:20:00 PM PDT 24
Finished Apr 15 02:20:01 PM PDT 24
Peak memory 223760 kb
Host smart-9a6122b8-3a1f-4bb7-a816-f6ad23766b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269489928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.269489928
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.428008274
Short name T419
Test name
Test status
Simulation time 26432414 ps
CPU time 0.97 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 214964 kb
Host smart-4e523601-30b9-4a44-a532-0211e69b270d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428008274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.428008274
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.4041342120
Short name T284
Test name
Test status
Simulation time 137157931 ps
CPU time 1.15 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 216268 kb
Host smart-a947915a-0717-4515-85d8-331f5298f5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041342120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4041342120
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1901175789
Short name T205
Test name
Test status
Simulation time 555059714828 ps
CPU time 1210.7 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:40:13 PM PDT 24
Peak memory 221792 kb
Host smart-ad953052-9617-43f5-bd38-edec3cff9443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901175789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1901175789
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3292821502
Short name T826
Test name
Test status
Simulation time 217312206 ps
CPU time 1.29 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 215292 kb
Host smart-9c3dcb63-8780-4606-8ac9-19b2a6bb6439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292821502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3292821502
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.356621552
Short name T594
Test name
Test status
Simulation time 59181669 ps
CPU time 0.87 seconds
Started Apr 15 02:20:07 PM PDT 24
Finished Apr 15 02:20:08 PM PDT 24
Peak memory 206336 kb
Host smart-155d614f-744e-445c-84ba-eb586c080b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356621552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.356621552
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2620877065
Short name T345
Test name
Test status
Simulation time 30519067 ps
CPU time 1.21 seconds
Started Apr 15 02:20:03 PM PDT 24
Finished Apr 15 02:20:05 PM PDT 24
Peak memory 216156 kb
Host smart-5059b92f-171f-441d-9342-d4227190a466
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620877065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2620877065
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.434996089
Short name T160
Test name
Test status
Simulation time 25809602 ps
CPU time 1.12 seconds
Started Apr 15 02:20:00 PM PDT 24
Finished Apr 15 02:20:02 PM PDT 24
Peak memory 219048 kb
Host smart-c34b37bc-d33c-45fa-a6ec-c05325730da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434996089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.434996089
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2473032417
Short name T302
Test name
Test status
Simulation time 45024047 ps
CPU time 1.23 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 218808 kb
Host smart-dbc4c475-cb1a-4797-b811-3b8aa779ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473032417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2473032417
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3180766418
Short name T771
Test name
Test status
Simulation time 36653534 ps
CPU time 1.03 seconds
Started Apr 15 02:20:03 PM PDT 24
Finished Apr 15 02:20:04 PM PDT 24
Peak memory 223712 kb
Host smart-a982bf7d-d6bd-4158-b0f4-46cc3872b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180766418 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3180766418
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.53145877
Short name T319
Test name
Test status
Simulation time 17139274 ps
CPU time 0.99 seconds
Started Apr 15 02:20:01 PM PDT 24
Finished Apr 15 02:20:03 PM PDT 24
Peak memory 214924 kb
Host smart-9aeba2c1-a619-4588-bd1e-863b500825f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53145877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.53145877
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3047700597
Short name T255
Test name
Test status
Simulation time 709824219 ps
CPU time 4.11 seconds
Started Apr 15 02:20:02 PM PDT 24
Finished Apr 15 02:20:06 PM PDT 24
Peak memory 216032 kb
Host smart-5bda57ff-a43a-4f05-a9e4-aefe6dc8bed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047700597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3047700597
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2258970200
Short name T192
Test name
Test status
Simulation time 66031587484 ps
CPU time 1082.39 seconds
Started Apr 15 02:20:03 PM PDT 24
Finished Apr 15 02:38:06 PM PDT 24
Peak memory 222056 kb
Host smart-e7838559-9fe4-4fb4-b7d5-6b9c5bff3a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258970200 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2258970200
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3292490082
Short name T595
Test name
Test status
Simulation time 84143404 ps
CPU time 1.2 seconds
Started Apr 15 02:20:15 PM PDT 24
Finished Apr 15 02:20:16 PM PDT 24
Peak memory 215304 kb
Host smart-dc868a23-8f6d-4491-91f8-2c3847506ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292490082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3292490082
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3957874963
Short name T377
Test name
Test status
Simulation time 32332043 ps
CPU time 0.95 seconds
Started Apr 15 02:20:09 PM PDT 24
Finished Apr 15 02:20:11 PM PDT 24
Peak memory 206372 kb
Host smart-b22436d8-4646-4c65-b912-2147fb7f7cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957874963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3957874963
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2563657959
Short name T775
Test name
Test status
Simulation time 53904004 ps
CPU time 0.81 seconds
Started Apr 15 02:20:13 PM PDT 24
Finished Apr 15 02:20:14 PM PDT 24
Peak memory 215396 kb
Host smart-2018fcb1-41a6-4d19-9078-453a1a9594d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563657959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2563657959
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1110737717
Short name T175
Test name
Test status
Simulation time 92970166 ps
CPU time 1.01 seconds
Started Apr 15 02:20:08 PM PDT 24
Finished Apr 15 02:20:10 PM PDT 24
Peak memory 216304 kb
Host smart-c862b405-1bb4-4e85-aadb-7a9c4eaab906
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110737717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1110737717
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1279127235
Short name T89
Test name
Test status
Simulation time 74997330 ps
CPU time 1.16 seconds
Started Apr 15 02:20:09 PM PDT 24
Finished Apr 15 02:20:10 PM PDT 24
Peak memory 229504 kb
Host smart-af2953c2-15d8-4735-9de3-16f9404a7415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279127235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1279127235
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_intr.2035228924
Short name T610
Test name
Test status
Simulation time 27298758 ps
CPU time 0.92 seconds
Started Apr 15 02:20:12 PM PDT 24
Finished Apr 15 02:20:13 PM PDT 24
Peak memory 215148 kb
Host smart-da592d4e-d827-43d8-88bc-c65c4c067e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035228924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2035228924
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.691778939
Short name T834
Test name
Test status
Simulation time 18620406 ps
CPU time 0.91 seconds
Started Apr 15 02:20:05 PM PDT 24
Finished Apr 15 02:20:06 PM PDT 24
Peak memory 214888 kb
Host smart-ec3b42e6-59b6-4b0b-b6a8-2f9fad98672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691778939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.691778939
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1756192630
Short name T728
Test name
Test status
Simulation time 285447050 ps
CPU time 3.15 seconds
Started Apr 15 02:20:04 PM PDT 24
Finished Apr 15 02:20:08 PM PDT 24
Peak memory 216336 kb
Host smart-a579381b-3a60-4137-a496-e6555421c521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756192630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1756192630
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.310733303
Short name T556
Test name
Test status
Simulation time 88452776373 ps
CPU time 1035.65 seconds
Started Apr 15 02:20:06 PM PDT 24
Finished Apr 15 02:37:22 PM PDT 24
Peak memory 220756 kb
Host smart-c7ed9e96-babe-4c45-b263-7ed728c18eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310733303 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.310733303
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.3938236926
Short name T504
Test name
Test status
Simulation time 56125525 ps
CPU time 0.91 seconds
Started Apr 15 02:20:12 PM PDT 24
Finished Apr 15 02:20:14 PM PDT 24
Peak memory 206604 kb
Host smart-a33c83ee-f715-496e-aa8a-2acb93dfb3d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938236926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3938236926
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4221688344
Short name T367
Test name
Test status
Simulation time 36206420 ps
CPU time 0.83 seconds
Started Apr 15 02:20:16 PM PDT 24
Finished Apr 15 02:20:18 PM PDT 24
Peak memory 215488 kb
Host smart-94334b80-ecf6-4b42-85a2-3d5038ff90a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221688344 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4221688344
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.365247492
Short name T166
Test name
Test status
Simulation time 59826014 ps
CPU time 1.18 seconds
Started Apr 15 02:20:15 PM PDT 24
Finished Apr 15 02:20:16 PM PDT 24
Peak memory 216104 kb
Host smart-7c557ba6-da37-4c1c-9add-09108ef32cc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365247492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.365247492
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.723558093
Short name T105
Test name
Test status
Simulation time 19064270 ps
CPU time 1.04 seconds
Started Apr 15 02:20:12 PM PDT 24
Finished Apr 15 02:20:13 PM PDT 24
Peak memory 217672 kb
Host smart-6b994011-b65b-419c-b138-98470182a57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723558093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.723558093
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.384598795
Short name T614
Test name
Test status
Simulation time 41010552 ps
CPU time 0.99 seconds
Started Apr 15 02:20:07 PM PDT 24
Finished Apr 15 02:20:09 PM PDT 24
Peak memory 216332 kb
Host smart-171f81c9-de77-403b-83bd-5e4d5986f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384598795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.384598795
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.744942462
Short name T393
Test name
Test status
Simulation time 34131264 ps
CPU time 0.85 seconds
Started Apr 15 02:20:14 PM PDT 24
Finished Apr 15 02:20:16 PM PDT 24
Peak memory 215132 kb
Host smart-3a17a960-453a-4f83-95d7-6c446a549e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744942462 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.744942462
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1558100455
Short name T656
Test name
Test status
Simulation time 17667674 ps
CPU time 0.96 seconds
Started Apr 15 02:20:12 PM PDT 24
Finished Apr 15 02:20:13 PM PDT 24
Peak memory 214920 kb
Host smart-bfc75ac0-4911-40d7-9616-992b156704e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558100455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1558100455
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3528508752
Short name T686
Test name
Test status
Simulation time 872745159 ps
CPU time 4.72 seconds
Started Apr 15 02:20:09 PM PDT 24
Finished Apr 15 02:20:14 PM PDT 24
Peak memory 216300 kb
Host smart-fb56197a-752c-4111-b313-744b5537b166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528508752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3528508752
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.3385735489
Short name T769
Test name
Test status
Simulation time 27621533 ps
CPU time 1.22 seconds
Started Apr 15 02:20:17 PM PDT 24
Finished Apr 15 02:20:18 PM PDT 24
Peak memory 215312 kb
Host smart-a6258dde-fc27-4118-a5d2-5c2bd82e8e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385735489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3385735489
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2993979502
Short name T328
Test name
Test status
Simulation time 45771933 ps
CPU time 0.88 seconds
Started Apr 15 02:20:13 PM PDT 24
Finished Apr 15 02:20:14 PM PDT 24
Peak memory 206284 kb
Host smart-4394bf6c-951c-42c6-8e38-fed5e9b4beab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993979502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2993979502
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1580721012
Short name T158
Test name
Test status
Simulation time 17104450 ps
CPU time 0.84 seconds
Started Apr 15 02:20:18 PM PDT 24
Finished Apr 15 02:20:20 PM PDT 24
Peak memory 215496 kb
Host smart-b025d0fc-e964-4a5c-8195-798fd302f689
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580721012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1580721012
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3432439489
Short name T188
Test name
Test status
Simulation time 145699898 ps
CPU time 1.07 seconds
Started Apr 15 02:20:14 PM PDT 24
Finished Apr 15 02:20:15 PM PDT 24
Peak memory 216324 kb
Host smart-4fe0af80-96c2-457d-89fb-1c5c02c64a75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432439489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3432439489
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.451484014
Short name T7
Test name
Test status
Simulation time 30889040 ps
CPU time 1.01 seconds
Started Apr 15 02:20:17 PM PDT 24
Finished Apr 15 02:20:19 PM PDT 24
Peak memory 218924 kb
Host smart-f8d776bc-97c4-4823-bf7c-81fb9e804a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451484014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.451484014
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1143195449
Short name T411
Test name
Test status
Simulation time 28255547 ps
CPU time 1.23 seconds
Started Apr 15 02:20:18 PM PDT 24
Finished Apr 15 02:20:20 PM PDT 24
Peak memory 216280 kb
Host smart-1aeb14c3-97aa-4b54-aec7-56e350859f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143195449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1143195449
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3814468886
Short name T525
Test name
Test status
Simulation time 22679441 ps
CPU time 1.06 seconds
Started Apr 15 02:20:16 PM PDT 24
Finished Apr 15 02:20:17 PM PDT 24
Peak memory 215024 kb
Host smart-de9c8fcd-be62-4e6a-afd3-3554ccde4d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814468886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3814468886
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1120516379
Short name T201
Test name
Test status
Simulation time 18566847 ps
CPU time 1.05 seconds
Started Apr 15 02:20:12 PM PDT 24
Finished Apr 15 02:20:13 PM PDT 24
Peak memory 214948 kb
Host smart-d297909e-a413-4c9e-95bd-a7b19009c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120516379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1120516379
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2020124947
Short name T226
Test name
Test status
Simulation time 1253660190 ps
CPU time 3.05 seconds
Started Apr 15 02:20:16 PM PDT 24
Finished Apr 15 02:20:19 PM PDT 24
Peak memory 216052 kb
Host smart-6e047b2e-94f4-4dba-adc3-6d242809c32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020124947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2020124947
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.5772591
Short name T467
Test name
Test status
Simulation time 432498683403 ps
CPU time 1097.43 seconds
Started Apr 15 02:20:14 PM PDT 24
Finished Apr 15 02:38:32 PM PDT 24
Peak memory 221648 kb
Host smart-9c3738dd-55b1-4b9f-b119-ffdc23367b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5772591 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.5772591
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1500257836
Short name T145
Test name
Test status
Simulation time 44894981 ps
CPU time 1.25 seconds
Started Apr 15 02:20:21 PM PDT 24
Finished Apr 15 02:20:23 PM PDT 24
Peak memory 215192 kb
Host smart-e5ef85e9-fbd5-4985-b06f-25b9154c5164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500257836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1500257836
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.502981623
Short name T434
Test name
Test status
Simulation time 20857877 ps
CPU time 1.01 seconds
Started Apr 15 02:20:22 PM PDT 24
Finished Apr 15 02:20:23 PM PDT 24
Peak memory 206576 kb
Host smart-55305b08-dc1a-4f38-842e-4f77777a0ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502981623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.502981623
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4137925730
Short name T156
Test name
Test status
Simulation time 19808357 ps
CPU time 0.89 seconds
Started Apr 15 02:20:18 PM PDT 24
Finished Apr 15 02:20:19 PM PDT 24
Peak memory 215672 kb
Host smart-63b0f435-fdf8-453f-a1dd-61b55f75d7c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137925730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4137925730
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.27411316
Short name T779
Test name
Test status
Simulation time 142203893 ps
CPU time 1.04 seconds
Started Apr 15 02:20:20 PM PDT 24
Finished Apr 15 02:20:21 PM PDT 24
Peak memory 219800 kb
Host smart-0142454e-8dd7-4cbb-bc11-522553e72578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27411316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.27411316
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3669678136
Short name T281
Test name
Test status
Simulation time 36273381 ps
CPU time 1.47 seconds
Started Apr 15 02:20:15 PM PDT 24
Finished Apr 15 02:20:17 PM PDT 24
Peak memory 216312 kb
Host smart-5cd13a9f-92d0-4528-939d-67c2db6637b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669678136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3669678136
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1692894200
Short name T216
Test name
Test status
Simulation time 36202101 ps
CPU time 1.03 seconds
Started Apr 15 02:20:20 PM PDT 24
Finished Apr 15 02:20:21 PM PDT 24
Peak memory 223720 kb
Host smart-641ab428-bab9-4dc0-8c2d-b5fe43c9e0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692894200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1692894200
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2968888800
Short name T736
Test name
Test status
Simulation time 27688689 ps
CPU time 0.87 seconds
Started Apr 15 02:20:13 PM PDT 24
Finished Apr 15 02:20:14 PM PDT 24
Peak memory 214880 kb
Host smart-c764e65f-d1b8-4457-b4d6-6d247758af6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968888800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2968888800
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2946390090
Short name T560
Test name
Test status
Simulation time 629654447 ps
CPU time 4.43 seconds
Started Apr 15 02:20:17 PM PDT 24
Finished Apr 15 02:20:22 PM PDT 24
Peak memory 216380 kb
Host smart-daba1bab-21cf-4051-8319-4e72938ebc62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946390090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2946390090
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3544140194
Short name T808
Test name
Test status
Simulation time 20666653725 ps
CPU time 530.22 seconds
Started Apr 15 02:20:24 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 223200 kb
Host smart-08859810-b383-4f88-8ea6-92fb9ba65758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544140194 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3544140194
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1328292583
Short name T307
Test name
Test status
Simulation time 28713209 ps
CPU time 1.13 seconds
Started Apr 15 02:20:21 PM PDT 24
Finished Apr 15 02:20:23 PM PDT 24
Peak memory 215292 kb
Host smart-5b0d8e95-6dd7-4cdd-b34e-b8be4b44d978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328292583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1328292583
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3745457198
Short name T581
Test name
Test status
Simulation time 50513099 ps
CPU time 0.89 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:25 PM PDT 24
Peak memory 205720 kb
Host smart-ce869c95-f76b-4560-aaa4-ee72e3176942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745457198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3745457198
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_err.3080035645
Short name T676
Test name
Test status
Simulation time 29435669 ps
CPU time 1.23 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:24 PM PDT 24
Peak memory 218964 kb
Host smart-cb000903-350b-4ff6-922c-512fa47a8a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080035645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3080035645
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2951165768
Short name T487
Test name
Test status
Simulation time 51555074 ps
CPU time 0.98 seconds
Started Apr 15 02:20:20 PM PDT 24
Finished Apr 15 02:20:21 PM PDT 24
Peak memory 216312 kb
Host smart-180f9dda-76f1-48bd-9d0d-e1e829ec18f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951165768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2951165768
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2285150117
Short name T3
Test name
Test status
Simulation time 32177125 ps
CPU time 0.88 seconds
Started Apr 15 02:20:21 PM PDT 24
Finished Apr 15 02:20:22 PM PDT 24
Peak memory 215364 kb
Host smart-1ec48034-0332-40e1-8a09-784b0f2e0d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285150117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2285150117
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.916580483
Short name T415
Test name
Test status
Simulation time 18933035 ps
CPU time 1 seconds
Started Apr 15 02:20:18 PM PDT 24
Finished Apr 15 02:20:20 PM PDT 24
Peak memory 214924 kb
Host smart-a2497dcf-c7f8-4bef-9a69-f54ff39d2b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916580483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.916580483
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3369843603
Short name T445
Test name
Test status
Simulation time 1140647806 ps
CPU time 2.85 seconds
Started Apr 15 02:20:18 PM PDT 24
Finished Apr 15 02:20:21 PM PDT 24
Peak memory 214904 kb
Host smart-e06822d4-3f03-4477-9a62-c381827cab19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369843603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3369843603
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2856896051
Short name T193
Test name
Test status
Simulation time 73394521189 ps
CPU time 915.46 seconds
Started Apr 15 02:20:18 PM PDT 24
Finished Apr 15 02:35:34 PM PDT 24
Peak memory 221412 kb
Host smart-23e9def7-cc65-4e5e-ae22-2a3ce7c64a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856896051 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2856896051
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1198104228
Short name T657
Test name
Test status
Simulation time 28693542 ps
CPU time 1.24 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:25 PM PDT 24
Peak memory 215296 kb
Host smart-d27da60c-2c1e-49e8-95b1-aa717eec9050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198104228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1198104228
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2300771982
Short name T584
Test name
Test status
Simulation time 24279919 ps
CPU time 0.84 seconds
Started Apr 15 02:20:27 PM PDT 24
Finished Apr 15 02:20:28 PM PDT 24
Peak memory 205744 kb
Host smart-5cb3829d-7a0a-40c3-a8f8-b7da13471559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300771982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2300771982
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1632990994
Short name T789
Test name
Test status
Simulation time 11447604 ps
CPU time 0.84 seconds
Started Apr 15 02:20:21 PM PDT 24
Finished Apr 15 02:20:22 PM PDT 24
Peak memory 215184 kb
Host smart-88f6f74b-f17e-42f3-940b-1e1bb144dff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632990994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1632990994
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2224623178
Short name T344
Test name
Test status
Simulation time 193273605 ps
CPU time 1.19 seconds
Started Apr 15 02:20:22 PM PDT 24
Finished Apr 15 02:20:23 PM PDT 24
Peak memory 216176 kb
Host smart-32651428-e3f8-43f6-a013-7c34b7dbbc7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224623178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2224623178
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2348210701
Short name T630
Test name
Test status
Simulation time 18778900 ps
CPU time 0.99 seconds
Started Apr 15 02:20:21 PM PDT 24
Finished Apr 15 02:20:23 PM PDT 24
Peak memory 217720 kb
Host smart-cf6d5e30-007d-4efb-872e-5771e1a9e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348210701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2348210701
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1359245469
Short name T133
Test name
Test status
Simulation time 46759363 ps
CPU time 1.3 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:25 PM PDT 24
Peak memory 216380 kb
Host smart-ceff60e6-571d-4d1c-a1fd-62864cef5bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359245469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1359245469
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2341496711
Short name T492
Test name
Test status
Simulation time 26045410 ps
CPU time 1.1 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:24 PM PDT 24
Peak memory 223652 kb
Host smart-fba0cfeb-476f-4a0c-9239-83276c08b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341496711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2341496711
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2483694037
Short name T681
Test name
Test status
Simulation time 179282658 ps
CPU time 0.99 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:25 PM PDT 24
Peak memory 214820 kb
Host smart-c6fa84b9-2a19-48d9-b970-e49bbc1b7452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483694037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2483694037
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3409242367
Short name T546
Test name
Test status
Simulation time 50733785 ps
CPU time 1.43 seconds
Started Apr 15 02:20:23 PM PDT 24
Finished Apr 15 02:20:25 PM PDT 24
Peak memory 217500 kb
Host smart-436b0842-bcc4-4184-afba-153f09cab537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409242367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3409242367
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.802343418
Short name T694
Test name
Test status
Simulation time 29150401419 ps
CPU time 208.85 seconds
Started Apr 15 02:20:21 PM PDT 24
Finished Apr 15 02:23:51 PM PDT 24
Peak memory 220572 kb
Host smart-3dac636c-d804-4987-9443-0417ddafb490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802343418 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.802343418
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4150276600
Short name T589
Test name
Test status
Simulation time 31029956 ps
CPU time 1.29 seconds
Started Apr 15 02:16:15 PM PDT 24
Finished Apr 15 02:16:17 PM PDT 24
Peak memory 215232 kb
Host smart-18099562-2dd2-478f-a064-4ab6eac1fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150276600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4150276600
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2723030888
Short name T735
Test name
Test status
Simulation time 23730914 ps
CPU time 0.85 seconds
Started Apr 15 02:16:27 PM PDT 24
Finished Apr 15 02:16:29 PM PDT 24
Peak memory 205752 kb
Host smart-f5e65eca-481d-4f35-bb0d-8fa89a2b0a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723030888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2723030888
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2519938661
Short name T719
Test name
Test status
Simulation time 25923857 ps
CPU time 0.75 seconds
Started Apr 15 02:16:20 PM PDT 24
Finished Apr 15 02:16:21 PM PDT 24
Peak memory 215492 kb
Host smart-345d9074-c97f-407b-b5ee-97203bd4d96f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519938661 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2519938661
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.2472286047
Short name T803
Test name
Test status
Simulation time 22653135 ps
CPU time 0.98 seconds
Started Apr 15 02:16:18 PM PDT 24
Finished Apr 15 02:16:19 PM PDT 24
Peak memory 230960 kb
Host smart-66ae1a63-4b4b-4e70-9376-78dace4f2ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472286047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2472286047
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3736890570
Short name T190
Test name
Test status
Simulation time 58510005 ps
CPU time 1.1 seconds
Started Apr 15 02:16:15 PM PDT 24
Finished Apr 15 02:16:16 PM PDT 24
Peak memory 216500 kb
Host smart-41fef91b-4fb9-496d-8ff3-7aa3afef074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736890570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3736890570
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2540470819
Short name T131
Test name
Test status
Simulation time 25657498 ps
CPU time 0.93 seconds
Started Apr 15 02:16:14 PM PDT 24
Finished Apr 15 02:16:15 PM PDT 24
Peak memory 215388 kb
Host smart-558428a6-e393-47a1-a3c7-7e531e572229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540470819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2540470819
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3027651269
Short name T304
Test name
Test status
Simulation time 29518733 ps
CPU time 0.95 seconds
Started Apr 15 02:16:17 PM PDT 24
Finished Apr 15 02:16:19 PM PDT 24
Peak memory 206620 kb
Host smart-42c64d2f-9ba8-4450-865c-e384c09efd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027651269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3027651269
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3601857215
Short name T642
Test name
Test status
Simulation time 50367610 ps
CPU time 0.93 seconds
Started Apr 15 02:16:15 PM PDT 24
Finished Apr 15 02:16:16 PM PDT 24
Peak memory 214932 kb
Host smart-db4ebe24-2302-4b89-a91f-b8a06ab7f9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601857215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3601857215
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.7493477
Short name T634
Test name
Test status
Simulation time 283511620 ps
CPU time 3.5 seconds
Started Apr 15 02:16:17 PM PDT 24
Finished Apr 15 02:16:22 PM PDT 24
Peak memory 214892 kb
Host smart-38ef7094-39b7-47e9-b675-31a21f72dae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7493477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.7493477
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1111514810
Short name T498
Test name
Test status
Simulation time 32079755584 ps
CPU time 704.12 seconds
Started Apr 15 02:16:14 PM PDT 24
Finished Apr 15 02:27:59 PM PDT 24
Peak memory 217572 kb
Host smart-c91bed9c-b722-424d-90d2-8e0bb014fc58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111514810 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1111514810
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1742981965
Short name T761
Test name
Test status
Simulation time 28679060 ps
CPU time 0.82 seconds
Started Apr 15 02:20:27 PM PDT 24
Finished Apr 15 02:20:29 PM PDT 24
Peak memory 217292 kb
Host smart-e27d5456-00a0-4713-8995-dfa0f69a1d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742981965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1742981965
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2734883875
Short name T132
Test name
Test status
Simulation time 50556591 ps
CPU time 1.49 seconds
Started Apr 15 02:20:25 PM PDT 24
Finished Apr 15 02:20:27 PM PDT 24
Peak memory 217400 kb
Host smart-52d87ea1-272c-4f0e-a231-01766728c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734883875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2734883875
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2271139495
Short name T414
Test name
Test status
Simulation time 21527303 ps
CPU time 1.21 seconds
Started Apr 15 02:20:25 PM PDT 24
Finished Apr 15 02:20:27 PM PDT 24
Peak memory 229368 kb
Host smart-e930b42a-8793-428b-985a-72538202ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271139495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2271139495
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2856621016
Short name T820
Test name
Test status
Simulation time 68646688 ps
CPU time 1.18 seconds
Started Apr 15 02:20:27 PM PDT 24
Finished Apr 15 02:20:29 PM PDT 24
Peak memory 218936 kb
Host smart-85f6e12c-76bc-4a8b-acf7-2d41ba3e9cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856621016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2856621016
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3449433653
Short name T573
Test name
Test status
Simulation time 24154508 ps
CPU time 0.87 seconds
Started Apr 15 02:20:25 PM PDT 24
Finished Apr 15 02:20:26 PM PDT 24
Peak memory 217528 kb
Host smart-7433efea-cf44-41f9-8188-3cfb04ce2eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449433653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3449433653
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2878044915
Short name T140
Test name
Test status
Simulation time 61003591 ps
CPU time 1.24 seconds
Started Apr 15 02:20:27 PM PDT 24
Finished Apr 15 02:20:29 PM PDT 24
Peak memory 216364 kb
Host smart-442e59b9-2759-4ae5-b0bf-b430ea3090a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878044915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2878044915
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.403437646
Short name T115
Test name
Test status
Simulation time 22380942 ps
CPU time 0.91 seconds
Started Apr 15 02:20:29 PM PDT 24
Finished Apr 15 02:20:31 PM PDT 24
Peak memory 217588 kb
Host smart-812cee42-306b-4628-b2af-2d2610121992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403437646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.403437646
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.1028588017
Short name T177
Test name
Test status
Simulation time 51487302 ps
CPU time 0.82 seconds
Started Apr 15 02:20:26 PM PDT 24
Finished Apr 15 02:20:27 PM PDT 24
Peak memory 217620 kb
Host smart-81d326f1-db31-4d42-9b2c-8345a0e7e18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028588017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1028588017
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3250748724
Short name T506
Test name
Test status
Simulation time 52204866 ps
CPU time 1.62 seconds
Started Apr 15 02:20:26 PM PDT 24
Finished Apr 15 02:20:28 PM PDT 24
Peak memory 217564 kb
Host smart-50387d3c-989c-4a00-ac3f-39895967b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250748724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3250748724
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2513031234
Short name T505
Test name
Test status
Simulation time 37303409 ps
CPU time 1.03 seconds
Started Apr 15 02:20:28 PM PDT 24
Finished Apr 15 02:20:30 PM PDT 24
Peak memory 219788 kb
Host smart-5c623ea9-2437-49df-ad9d-ffb70daaaef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513031234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2513031234
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3421315696
Short name T276
Test name
Test status
Simulation time 77711197 ps
CPU time 1.06 seconds
Started Apr 15 02:20:26 PM PDT 24
Finished Apr 15 02:20:28 PM PDT 24
Peak memory 216252 kb
Host smart-a5213da2-3a1a-424b-b366-322437e33824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421315696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3421315696
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1007246356
Short name T93
Test name
Test status
Simulation time 35471280 ps
CPU time 1 seconds
Started Apr 15 02:20:25 PM PDT 24
Finished Apr 15 02:20:27 PM PDT 24
Peak memory 232124 kb
Host smart-628b4ec3-3784-4870-8410-9e97283bdff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007246356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1007246356
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3731121170
Short name T664
Test name
Test status
Simulation time 160418543 ps
CPU time 3.11 seconds
Started Apr 15 02:20:25 PM PDT 24
Finished Apr 15 02:20:29 PM PDT 24
Peak memory 217816 kb
Host smart-9898c544-e2ce-43bb-87b7-94c7ff5a5b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731121170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3731121170
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2023046182
Short name T46
Test name
Test status
Simulation time 18308438 ps
CPU time 1.17 seconds
Started Apr 15 02:20:26 PM PDT 24
Finished Apr 15 02:20:28 PM PDT 24
Peak memory 230996 kb
Host smart-3579f643-c838-45ba-a909-9e170b9ddd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023046182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2023046182
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2992691001
Short name T586
Test name
Test status
Simulation time 88509377 ps
CPU time 1.17 seconds
Started Apr 15 02:20:25 PM PDT 24
Finished Apr 15 02:20:27 PM PDT 24
Peak memory 216348 kb
Host smart-9075001b-e1af-46af-96fa-9f6c00e29fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992691001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2992691001
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2541413432
Short name T111
Test name
Test status
Simulation time 22952654 ps
CPU time 0.9 seconds
Started Apr 15 02:20:28 PM PDT 24
Finished Apr 15 02:20:30 PM PDT 24
Peak memory 217604 kb
Host smart-baf9e0e8-799d-49e6-933e-7da29c0add46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541413432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2541413432
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4256060018
Short name T670
Test name
Test status
Simulation time 32828163 ps
CPU time 1.33 seconds
Started Apr 15 02:20:28 PM PDT 24
Finished Apr 15 02:20:30 PM PDT 24
Peak memory 216060 kb
Host smart-e53c86b4-5b8c-4847-99ff-4206e95e308d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256060018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4256060018
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.119115953
Short name T51
Test name
Test status
Simulation time 19724623 ps
CPU time 1.16 seconds
Started Apr 15 02:20:30 PM PDT 24
Finished Apr 15 02:20:32 PM PDT 24
Peak memory 230988 kb
Host smart-213e0b87-6de9-4fb9-b537-17ff6d95488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119115953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.119115953
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2462384834
Short name T424
Test name
Test status
Simulation time 58252844 ps
CPU time 1.53 seconds
Started Apr 15 02:20:28 PM PDT 24
Finished Apr 15 02:20:30 PM PDT 24
Peak memory 217464 kb
Host smart-55ae22f7-af8a-45f8-a9a8-7b18056abc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462384834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2462384834
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4030072399
Short name T783
Test name
Test status
Simulation time 94841320 ps
CPU time 1.22 seconds
Started Apr 15 02:16:31 PM PDT 24
Finished Apr 15 02:16:33 PM PDT 24
Peak memory 215280 kb
Host smart-94d25703-d2a4-4427-92ed-3e36636837b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030072399 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4030072399
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1814290323
Short name T322
Test name
Test status
Simulation time 73105048 ps
CPU time 0.83 seconds
Started Apr 15 02:16:40 PM PDT 24
Finished Apr 15 02:16:41 PM PDT 24
Peak memory 206592 kb
Host smart-5627ffb6-8ae3-4e7e-9ca8-213fd41d0514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814290323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1814290323
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2933965989
Short name T95
Test name
Test status
Simulation time 80617252 ps
CPU time 0.84 seconds
Started Apr 15 02:16:36 PM PDT 24
Finished Apr 15 02:16:37 PM PDT 24
Peak memory 215000 kb
Host smart-252964c3-8e09-4451-891f-152945d999b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933965989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2933965989
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1006609215
Short name T668
Test name
Test status
Simulation time 38059830 ps
CPU time 1.4 seconds
Started Apr 15 02:16:40 PM PDT 24
Finished Apr 15 02:16:41 PM PDT 24
Peak memory 216216 kb
Host smart-d9360655-d15b-4f3d-9852-3ad0a11ff1b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006609215 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1006609215
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1731265337
Short name T627
Test name
Test status
Simulation time 39075163 ps
CPU time 0.81 seconds
Started Apr 15 02:16:37 PM PDT 24
Finished Apr 15 02:16:38 PM PDT 24
Peak memory 217364 kb
Host smart-afc8051f-2d18-49d2-900d-ca691ef352cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731265337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1731265337
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.342603403
Short name T580
Test name
Test status
Simulation time 75644713 ps
CPU time 1.08 seconds
Started Apr 15 02:16:28 PM PDT 24
Finished Apr 15 02:16:29 PM PDT 24
Peak memory 216212 kb
Host smart-2957dc1b-a99f-4568-b527-aa9085a1961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342603403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.342603403
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3785026288
Short name T832
Test name
Test status
Simulation time 81109475 ps
CPU time 0.9 seconds
Started Apr 15 02:16:31 PM PDT 24
Finished Apr 15 02:16:33 PM PDT 24
Peak memory 223508 kb
Host smart-dffbf075-5cd5-416b-9f46-f2689aa57054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785026288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3785026288
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1793572157
Short name T55
Test name
Test status
Simulation time 57151386 ps
CPU time 0.92 seconds
Started Apr 15 02:16:28 PM PDT 24
Finished Apr 15 02:16:29 PM PDT 24
Peak memory 206640 kb
Host smart-03bd0a5c-2f41-4baa-bef1-7ca876e39367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793572157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1793572157
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3679671406
Short name T661
Test name
Test status
Simulation time 48716176 ps
CPU time 0.88 seconds
Started Apr 15 02:16:28 PM PDT 24
Finished Apr 15 02:16:29 PM PDT 24
Peak memory 214928 kb
Host smart-109df49b-4567-49ce-9149-4432484e5a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679671406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3679671406
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2954058062
Short name T153
Test name
Test status
Simulation time 639305890 ps
CPU time 3.21 seconds
Started Apr 15 02:16:28 PM PDT 24
Finished Apr 15 02:16:32 PM PDT 24
Peak memory 216124 kb
Host smart-ee124c82-6014-49b7-bf80-0f33564de21e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954058062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2954058062
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.822289834
Short name T206
Test name
Test status
Simulation time 60156878208 ps
CPU time 1273.57 seconds
Started Apr 15 02:16:28 PM PDT 24
Finished Apr 15 02:37:42 PM PDT 24
Peak memory 220724 kb
Host smart-02b05d43-a007-4236-9412-551d7f933f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822289834 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.822289834
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.4076698192
Short name T726
Test name
Test status
Simulation time 63018487 ps
CPU time 1.11 seconds
Started Apr 15 02:20:32 PM PDT 24
Finished Apr 15 02:20:34 PM PDT 24
Peak memory 229312 kb
Host smart-78cc9bcd-b1f2-4cbc-914d-3a9a428d44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076698192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.4076698192
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1359012481
Short name T353
Test name
Test status
Simulation time 89843282 ps
CPU time 1.37 seconds
Started Apr 15 02:20:31 PM PDT 24
Finished Apr 15 02:20:33 PM PDT 24
Peak memory 217908 kb
Host smart-7d86dd27-75f9-454e-9452-fbd1f5608829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359012481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1359012481
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3399075070
Short name T45
Test name
Test status
Simulation time 20213514 ps
CPU time 1.21 seconds
Started Apr 15 02:20:33 PM PDT 24
Finished Apr 15 02:20:35 PM PDT 24
Peak memory 232556 kb
Host smart-96e05d22-eb58-4061-800a-8c75fbbbd090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399075070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3399075070
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3631924050
Short name T325
Test name
Test status
Simulation time 49055321 ps
CPU time 1.56 seconds
Started Apr 15 02:20:33 PM PDT 24
Finished Apr 15 02:20:35 PM PDT 24
Peak memory 218780 kb
Host smart-cd086f1e-354f-4f8b-ade4-6ca7757ed2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631924050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3631924050
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2800996051
Short name T97
Test name
Test status
Simulation time 26067312 ps
CPU time 0.91 seconds
Started Apr 15 02:20:29 PM PDT 24
Finished Apr 15 02:20:31 PM PDT 24
Peak memory 217856 kb
Host smart-2ffc6108-9d43-496e-84f8-58597be6dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800996051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2800996051
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.627597578
Short name T364
Test name
Test status
Simulation time 81969524 ps
CPU time 1.06 seconds
Started Apr 15 02:20:31 PM PDT 24
Finished Apr 15 02:20:33 PM PDT 24
Peak memory 216152 kb
Host smart-af0746d9-3934-4f38-9ce0-6d2876c8cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627597578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.627597578
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2181944339
Short name T767
Test name
Test status
Simulation time 24500925 ps
CPU time 1.09 seconds
Started Apr 15 02:20:33 PM PDT 24
Finished Apr 15 02:20:35 PM PDT 24
Peak memory 230908 kb
Host smart-bb9aa974-ee8f-41c9-8502-7da444a7f6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181944339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2181944339
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1902108775
Short name T375
Test name
Test status
Simulation time 28689720 ps
CPU time 1.19 seconds
Started Apr 15 02:20:31 PM PDT 24
Finished Apr 15 02:20:33 PM PDT 24
Peak memory 217476 kb
Host smart-fd679331-c89d-4c4a-9f92-6196e3d27e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902108775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1902108775
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.94751461
Short name T616
Test name
Test status
Simulation time 22020352 ps
CPU time 1.13 seconds
Started Apr 15 02:20:34 PM PDT 24
Finished Apr 15 02:20:36 PM PDT 24
Peak memory 219112 kb
Host smart-f84a515e-9d7a-42e7-abef-35cf39d16940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94751461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.94751461
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3087446257
Short name T141
Test name
Test status
Simulation time 248439483 ps
CPU time 1.16 seconds
Started Apr 15 02:20:32 PM PDT 24
Finished Apr 15 02:20:34 PM PDT 24
Peak memory 216392 kb
Host smart-c0f0704a-792c-4a57-89e8-21ab2fad7da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087446257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3087446257
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.159287051
Short name T697
Test name
Test status
Simulation time 18351186 ps
CPU time 1.03 seconds
Started Apr 15 02:20:30 PM PDT 24
Finished Apr 15 02:20:32 PM PDT 24
Peak memory 217820 kb
Host smart-80e61ae4-2e13-42e5-b5ff-9fb11e45f285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159287051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.159287051
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3522722980
Short name T659
Test name
Test status
Simulation time 38525959 ps
CPU time 1.37 seconds
Started Apr 15 02:20:31 PM PDT 24
Finished Apr 15 02:20:33 PM PDT 24
Peak memory 216268 kb
Host smart-c81d13aa-df31-4287-bd33-568ab9d49f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522722980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3522722980
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2952027330
Short name T70
Test name
Test status
Simulation time 97374056 ps
CPU time 0.99 seconds
Started Apr 15 02:20:32 PM PDT 24
Finished Apr 15 02:20:34 PM PDT 24
Peak memory 218952 kb
Host smart-f7949429-c9e6-43d5-ad3f-a727e5214292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952027330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2952027330
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2823302944
Short name T798
Test name
Test status
Simulation time 33919344 ps
CPU time 1.51 seconds
Started Apr 15 02:20:33 PM PDT 24
Finished Apr 15 02:20:35 PM PDT 24
Peak memory 217328 kb
Host smart-86e013af-b9d8-43e6-8efc-fa6dc05fd4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823302944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2823302944
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2689813473
Short name T763
Test name
Test status
Simulation time 28831674 ps
CPU time 0.89 seconds
Started Apr 15 02:20:33 PM PDT 24
Finished Apr 15 02:20:35 PM PDT 24
Peak memory 217592 kb
Host smart-6e5ce1e3-42fb-4119-b89d-9cc4b08b5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689813473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2689813473
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2005250063
Short name T30
Test name
Test status
Simulation time 43219953 ps
CPU time 1.29 seconds
Started Apr 15 02:20:31 PM PDT 24
Finished Apr 15 02:20:33 PM PDT 24
Peak memory 216192 kb
Host smart-f8375cde-33ff-4e63-9f3d-fb7161642329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005250063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2005250063
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3630397508
Short name T104
Test name
Test status
Simulation time 24225511 ps
CPU time 0.92 seconds
Started Apr 15 02:20:31 PM PDT 24
Finished Apr 15 02:20:33 PM PDT 24
Peak memory 217580 kb
Host smart-46ddc119-a12e-499e-9098-52cd939c18b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630397508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3630397508
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.679036892
Short name T374
Test name
Test status
Simulation time 43861098 ps
CPU time 1.52 seconds
Started Apr 15 02:20:33 PM PDT 24
Finished Apr 15 02:20:35 PM PDT 24
Peak memory 218924 kb
Host smart-a5f9e680-5724-445a-bd6a-26576c04dd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679036892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.679036892
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.159722126
Short name T98
Test name
Test status
Simulation time 37668390 ps
CPU time 1.04 seconds
Started Apr 15 02:20:37 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 232076 kb
Host smart-c3a1c41f-5c91-4b60-9fda-3541f41a90d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159722126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.159722126
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3688563721
Short name T422
Test name
Test status
Simulation time 56907780 ps
CPU time 1.43 seconds
Started Apr 15 02:20:36 PM PDT 24
Finished Apr 15 02:20:38 PM PDT 24
Peak memory 217748 kb
Host smart-43c097b5-350e-4e8d-afb1-69506a79f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688563721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3688563721
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3449136784
Short name T181
Test name
Test status
Simulation time 46452960 ps
CPU time 1.18 seconds
Started Apr 15 02:16:45 PM PDT 24
Finished Apr 15 02:16:47 PM PDT 24
Peak memory 215264 kb
Host smart-9b967934-a1d6-4bc5-843a-f93c0e526808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449136784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3449136784
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1116453570
Short name T468
Test name
Test status
Simulation time 51454595 ps
CPU time 0.88 seconds
Started Apr 15 02:16:52 PM PDT 24
Finished Apr 15 02:16:53 PM PDT 24
Peak memory 206540 kb
Host smart-8dfe2ab8-3682-4350-9f39-a965843b3e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116453570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1116453570
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3921592519
Short name T824
Test name
Test status
Simulation time 24390950 ps
CPU time 0.83 seconds
Started Apr 15 02:16:52 PM PDT 24
Finished Apr 15 02:16:53 PM PDT 24
Peak memory 215384 kb
Host smart-94a49491-d449-48e5-abb1-6a148a7ca4f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921592519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3921592519
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3507199490
Short name T482
Test name
Test status
Simulation time 39055532 ps
CPU time 1.17 seconds
Started Apr 15 02:16:48 PM PDT 24
Finished Apr 15 02:16:50 PM PDT 24
Peak memory 216008 kb
Host smart-aa0e8c2e-7873-447d-93e4-891000a76b85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507199490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3507199490
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.906700012
Short name T81
Test name
Test status
Simulation time 22801063 ps
CPU time 1.1 seconds
Started Apr 15 02:16:49 PM PDT 24
Finished Apr 15 02:16:50 PM PDT 24
Peak memory 217644 kb
Host smart-86f918a3-ac74-44cb-ac8a-2e63a3302bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906700012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.906700012
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3591528028
Short name T529
Test name
Test status
Simulation time 57182254 ps
CPU time 1.32 seconds
Started Apr 15 02:16:43 PM PDT 24
Finished Apr 15 02:16:44 PM PDT 24
Peak memory 217788 kb
Host smart-15d31a90-9d6c-47f8-8a4e-16316adc38af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591528028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3591528028
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3306625928
Short name T744
Test name
Test status
Simulation time 73398361 ps
CPU time 0.82 seconds
Started Apr 15 02:16:45 PM PDT 24
Finished Apr 15 02:16:47 PM PDT 24
Peak memory 214888 kb
Host smart-4867f00f-d81d-4eeb-b297-1a9eb6fc38ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306625928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3306625928
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.609139822
Short name T310
Test name
Test status
Simulation time 28804243 ps
CPU time 0.88 seconds
Started Apr 15 02:16:46 PM PDT 24
Finished Apr 15 02:16:48 PM PDT 24
Peak memory 206616 kb
Host smart-ab4aa40c-f2f7-4b70-a5a4-d403cb79e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609139822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.609139822
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2260414935
Short name T451
Test name
Test status
Simulation time 17594686 ps
CPU time 0.95 seconds
Started Apr 15 02:16:45 PM PDT 24
Finished Apr 15 02:16:47 PM PDT 24
Peak memory 214876 kb
Host smart-44688711-540f-49db-90b1-313789b26276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260414935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2260414935
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4094013263
Short name T135
Test name
Test status
Simulation time 579209955 ps
CPU time 1.91 seconds
Started Apr 15 02:16:45 PM PDT 24
Finished Apr 15 02:16:48 PM PDT 24
Peak memory 214860 kb
Host smart-0196ca91-b21e-4e2c-9391-492fbc8d6ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094013263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4094013263
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.4070411657
Short name T197
Test name
Test status
Simulation time 230013640689 ps
CPU time 1443.23 seconds
Started Apr 15 02:16:43 PM PDT 24
Finished Apr 15 02:40:47 PM PDT 24
Peak memory 225572 kb
Host smart-85847658-73f8-4889-99ff-e54103805680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070411657 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.4070411657
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3150555861
Short name T472
Test name
Test status
Simulation time 19869701 ps
CPU time 1 seconds
Started Apr 15 02:20:38 PM PDT 24
Finished Apr 15 02:20:40 PM PDT 24
Peak memory 217688 kb
Host smart-940de45b-578b-4470-9bc8-98d617cd69c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150555861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3150555861
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3953018259
Short name T704
Test name
Test status
Simulation time 111218262 ps
CPU time 1.63 seconds
Started Apr 15 02:20:35 PM PDT 24
Finished Apr 15 02:20:37 PM PDT 24
Peak memory 217884 kb
Host smart-617e9382-e2b1-4cb0-8869-01306b0f3094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953018259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3953018259
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3699939017
Short name T551
Test name
Test status
Simulation time 45360223 ps
CPU time 1.2 seconds
Started Apr 15 02:20:37 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 224092 kb
Host smart-2c148d06-af7e-4411-bcb1-e6834373bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699939017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3699939017
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1849875811
Short name T514
Test name
Test status
Simulation time 129871426 ps
CPU time 3.32 seconds
Started Apr 15 02:20:35 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 217912 kb
Host smart-53834c04-e6fc-4178-a5e6-e37c4c7a3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849875811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1849875811
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2457472089
Short name T777
Test name
Test status
Simulation time 27850494 ps
CPU time 0.85 seconds
Started Apr 15 02:20:38 PM PDT 24
Finished Apr 15 02:20:40 PM PDT 24
Peak memory 217584 kb
Host smart-acc73489-0caa-45a9-86d5-df5be84f0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457472089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2457472089
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4003465915
Short name T335
Test name
Test status
Simulation time 55465877 ps
CPU time 1.14 seconds
Started Apr 15 02:20:34 PM PDT 24
Finished Apr 15 02:20:36 PM PDT 24
Peak memory 217600 kb
Host smart-aaff333f-e8a0-4988-b70d-83b67f2f0968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003465915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4003465915
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3146209517
Short name T439
Test name
Test status
Simulation time 42022973 ps
CPU time 1.21 seconds
Started Apr 15 02:20:38 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 231984 kb
Host smart-68c36a8e-2944-4e84-8479-dfaf4e0043aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146209517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3146209517
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1713661340
Short name T432
Test name
Test status
Simulation time 28092187 ps
CPU time 1.19 seconds
Started Apr 15 02:20:35 PM PDT 24
Finished Apr 15 02:20:37 PM PDT 24
Peak memory 217496 kb
Host smart-6205c0d7-e5ac-405b-bed3-44a056028789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713661340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1713661340
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3912199237
Short name T418
Test name
Test status
Simulation time 58146491 ps
CPU time 1.08 seconds
Started Apr 15 02:20:34 PM PDT 24
Finished Apr 15 02:20:36 PM PDT 24
Peak memory 218968 kb
Host smart-b2b61f16-9f2a-41e2-9902-b2273cec8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912199237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3912199237
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1222949519
Short name T34
Test name
Test status
Simulation time 36063466 ps
CPU time 1.33 seconds
Started Apr 15 02:20:35 PM PDT 24
Finished Apr 15 02:20:37 PM PDT 24
Peak memory 217428 kb
Host smart-c4a3c95b-9df7-402f-988f-d3a5f228f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222949519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1222949519
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2664727748
Short name T73
Test name
Test status
Simulation time 25464924 ps
CPU time 1 seconds
Started Apr 15 02:20:37 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 218960 kb
Host smart-da68954d-7134-45dc-bef6-3366995da251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664727748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2664727748
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1977401031
Short name T394
Test name
Test status
Simulation time 235764650 ps
CPU time 1.56 seconds
Started Apr 15 02:20:34 PM PDT 24
Finished Apr 15 02:20:36 PM PDT 24
Peak memory 217684 kb
Host smart-73a7cfda-dbc1-4ffd-ba6a-983e1e20966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977401031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1977401031
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2810439762
Short name T430
Test name
Test status
Simulation time 196300230 ps
CPU time 1.03 seconds
Started Apr 15 02:20:37 PM PDT 24
Finished Apr 15 02:20:38 PM PDT 24
Peak memory 232432 kb
Host smart-aac1876f-4128-46e3-a7b5-65b70386aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810439762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2810439762
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1717710395
Short name T816
Test name
Test status
Simulation time 42418269 ps
CPU time 1.55 seconds
Started Apr 15 02:20:36 PM PDT 24
Finished Apr 15 02:20:38 PM PDT 24
Peak memory 217424 kb
Host smart-dbaea566-4577-4eb6-933b-a7a749962a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717710395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1717710395
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2299807076
Short name T583
Test name
Test status
Simulation time 25064327 ps
CPU time 0.92 seconds
Started Apr 15 02:20:35 PM PDT 24
Finished Apr 15 02:20:37 PM PDT 24
Peak memory 217896 kb
Host smart-3dced582-623e-4ff0-b261-063185f5f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299807076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2299807076
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3942699081
Short name T764
Test name
Test status
Simulation time 90679630 ps
CPU time 1.21 seconds
Started Apr 15 02:20:34 PM PDT 24
Finished Apr 15 02:20:36 PM PDT 24
Peak memory 216248 kb
Host smart-d9cb097b-fd30-4c35-98e1-73c7862a4a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942699081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3942699081
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.543671391
Short name T94
Test name
Test status
Simulation time 53849034 ps
CPU time 1.18 seconds
Started Apr 15 02:20:37 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 224084 kb
Host smart-b6038d3d-4f15-48c5-a4b0-2fd09f3237fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543671391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.543671391
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2247653263
Short name T303
Test name
Test status
Simulation time 73675278 ps
CPU time 1.84 seconds
Started Apr 15 02:20:36 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 217640 kb
Host smart-e7f89314-4d6e-4fed-afe7-dc89e5fb0228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247653263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2247653263
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1915342724
Short name T476
Test name
Test status
Simulation time 26683027 ps
CPU time 1.1 seconds
Started Apr 15 02:20:36 PM PDT 24
Finished Apr 15 02:20:37 PM PDT 24
Peak memory 230932 kb
Host smart-ded4fcde-1b25-456c-b391-2b41ce6c3e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915342724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1915342724
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1056102614
Short name T479
Test name
Test status
Simulation time 56535051 ps
CPU time 1.79 seconds
Started Apr 15 02:20:37 PM PDT 24
Finished Apr 15 02:20:39 PM PDT 24
Peak memory 217420 kb
Host smart-ae2a0804-3131-494b-8896-c19fee0fede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056102614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1056102614
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.692395302
Short name T663
Test name
Test status
Simulation time 127624020 ps
CPU time 1.1 seconds
Started Apr 15 02:16:57 PM PDT 24
Finished Apr 15 02:16:58 PM PDT 24
Peak memory 215252 kb
Host smart-4b755ad4-a253-44c0-b080-e5fd7e3bd671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692395302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.692395302
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3833835214
Short name T382
Test name
Test status
Simulation time 14335212 ps
CPU time 0.91 seconds
Started Apr 15 02:17:02 PM PDT 24
Finished Apr 15 02:17:03 PM PDT 24
Peak memory 205752 kb
Host smart-437eefab-0a9f-435a-af2b-4332149f2657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833835214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3833835214
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1942333250
Short name T666
Test name
Test status
Simulation time 23883371 ps
CPU time 0.85 seconds
Started Apr 15 02:16:59 PM PDT 24
Finished Apr 15 02:17:00 PM PDT 24
Peak memory 215480 kb
Host smart-05af6e86-71fb-4ad7-b210-38d189bc9d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942333250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1942333250
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1796131817
Short name T455
Test name
Test status
Simulation time 46096650 ps
CPU time 1.56 seconds
Started Apr 15 02:17:01 PM PDT 24
Finished Apr 15 02:17:03 PM PDT 24
Peak memory 215916 kb
Host smart-47684132-7939-48ff-bde5-30f7fadce23f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796131817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1796131817
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.701162809
Short name T446
Test name
Test status
Simulation time 32841132 ps
CPU time 0.77 seconds
Started Apr 15 02:16:55 PM PDT 24
Finished Apr 15 02:16:56 PM PDT 24
Peak memory 217324 kb
Host smart-a3fb88c9-e58a-4eae-88e2-ed50d02a5720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701162809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.701162809
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.4077684304
Short name T628
Test name
Test status
Simulation time 25088245 ps
CPU time 1.1 seconds
Started Apr 15 02:16:52 PM PDT 24
Finished Apr 15 02:16:54 PM PDT 24
Peak memory 216400 kb
Host smart-bc1ae0de-c4c9-4a6f-a9c3-f669c4681dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077684304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.4077684304
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2708470798
Short name T124
Test name
Test status
Simulation time 20577243 ps
CPU time 1.03 seconds
Started Apr 15 02:16:52 PM PDT 24
Finished Apr 15 02:16:54 PM PDT 24
Peak memory 215368 kb
Host smart-4b3346ba-4d96-4d56-a34a-5e18d01d12ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708470798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2708470798
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.3472504801
Short name T496
Test name
Test status
Simulation time 125973506 ps
CPU time 0.84 seconds
Started Apr 15 02:16:52 PM PDT 24
Finished Apr 15 02:16:53 PM PDT 24
Peak memory 214588 kb
Host smart-835eeea3-0b79-40a5-b1f1-3d949c1300b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472504801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3472504801
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3886710102
Short name T685
Test name
Test status
Simulation time 467441360 ps
CPU time 4.82 seconds
Started Apr 15 02:16:55 PM PDT 24
Finished Apr 15 02:17:00 PM PDT 24
Peak memory 216068 kb
Host smart-793529fd-7968-45a5-9be4-808c53168c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886710102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3886710102
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3649666143
Short name T787
Test name
Test status
Simulation time 127562540275 ps
CPU time 998.18 seconds
Started Apr 15 02:16:51 PM PDT 24
Finished Apr 15 02:33:29 PM PDT 24
Peak memory 220648 kb
Host smart-64fa0729-0066-4cc4-8266-d55551cfcd1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649666143 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3649666143
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2061546619
Short name T50
Test name
Test status
Simulation time 31905787 ps
CPU time 1.03 seconds
Started Apr 15 02:20:41 PM PDT 24
Finished Apr 15 02:20:42 PM PDT 24
Peak memory 232176 kb
Host smart-0a64391d-3d3c-44c5-883a-db31c3c1914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061546619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2061546619
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3497796032
Short name T423
Test name
Test status
Simulation time 37144187 ps
CPU time 1.16 seconds
Started Apr 15 02:20:40 PM PDT 24
Finished Apr 15 02:20:42 PM PDT 24
Peak memory 216132 kb
Host smart-4a127d78-0cb4-4ee6-bb6d-de38d894bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497796032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3497796032
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1393650467
Short name T508
Test name
Test status
Simulation time 29568983 ps
CPU time 0.85 seconds
Started Apr 15 02:20:41 PM PDT 24
Finished Apr 15 02:20:43 PM PDT 24
Peak memory 217596 kb
Host smart-35df274c-a5ba-44b5-97ea-3e60bb75fe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393650467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1393650467
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1406074702
Short name T368
Test name
Test status
Simulation time 123520879 ps
CPU time 1.09 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 216512 kb
Host smart-c3c2850d-d6b6-4757-81d1-8629b8039201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406074702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1406074702
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3822449511
Short name T217
Test name
Test status
Simulation time 20332840 ps
CPU time 1.06 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 218964 kb
Host smart-d0043202-c6ec-4aa1-a7cf-5591ece1455e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822449511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3822449511
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3828229900
Short name T585
Test name
Test status
Simulation time 77663165 ps
CPU time 1.72 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:42 PM PDT 24
Peak memory 217484 kb
Host smart-1d671ada-8f81-4e3f-8a83-2b9a01e00c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828229900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3828229900
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1675694476
Short name T82
Test name
Test status
Simulation time 33777968 ps
CPU time 0.99 seconds
Started Apr 15 02:20:41 PM PDT 24
Finished Apr 15 02:20:42 PM PDT 24
Peak memory 229432 kb
Host smart-0766e73c-87e7-4220-a92f-b4a86eca882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675694476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1675694476
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2796462589
Short name T449
Test name
Test status
Simulation time 40809828 ps
CPU time 1.28 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 216416 kb
Host smart-e2683079-44b4-49c1-ad73-1afe8a72d0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796462589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2796462589
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.994090796
Short name T83
Test name
Test status
Simulation time 101642468 ps
CPU time 1.05 seconds
Started Apr 15 02:20:42 PM PDT 24
Finished Apr 15 02:20:43 PM PDT 24
Peak memory 229720 kb
Host smart-91e03a8f-c49a-45eb-b783-6ad4c3e3c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994090796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.994090796
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.672709415
Short name T629
Test name
Test status
Simulation time 92005655 ps
CPU time 1.09 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 216364 kb
Host smart-792b3650-6ee2-44d9-b69a-59f4349ec2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672709415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.672709415
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3440678706
Short name T13
Test name
Test status
Simulation time 23395616 ps
CPU time 1.03 seconds
Started Apr 15 02:20:44 PM PDT 24
Finished Apr 15 02:20:46 PM PDT 24
Peak memory 230928 kb
Host smart-f665588c-08c4-4f4f-85b6-a54ec983d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440678706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3440678706
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2186729351
Short name T144
Test name
Test status
Simulation time 127409053 ps
CPU time 1.08 seconds
Started Apr 15 02:20:38 PM PDT 24
Finished Apr 15 02:20:40 PM PDT 24
Peak memory 216372 kb
Host smart-11787e36-ef61-47bf-9b07-04f30a73f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186729351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2186729351
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2870361371
Short name T173
Test name
Test status
Simulation time 28011161 ps
CPU time 0.92 seconds
Started Apr 15 02:20:43 PM PDT 24
Finished Apr 15 02:20:44 PM PDT 24
Peak memory 217988 kb
Host smart-0771d08e-9cb0-40cc-b9c5-cc471bad433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870361371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2870361371
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2922617930
Short name T178
Test name
Test status
Simulation time 78283297 ps
CPU time 1.44 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 217264 kb
Host smart-98fc9aaa-e831-44bb-ae68-629bad156327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922617930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2922617930
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1464745104
Short name T74
Test name
Test status
Simulation time 25184795 ps
CPU time 1.08 seconds
Started Apr 15 02:20:39 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 229280 kb
Host smart-882f9359-eec1-4373-a524-ac4a59305b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464745104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1464745104
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3685556812
Short name T497
Test name
Test status
Simulation time 49071459 ps
CPU time 2.09 seconds
Started Apr 15 02:20:38 PM PDT 24
Finished Apr 15 02:20:41 PM PDT 24
Peak memory 216660 kb
Host smart-498a7d2c-57f5-4ce3-a4bd-1c869eca3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685556812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3685556812
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.11039824
Short name T63
Test name
Test status
Simulation time 38505252 ps
CPU time 1.02 seconds
Started Apr 15 02:20:43 PM PDT 24
Finished Apr 15 02:20:44 PM PDT 24
Peak memory 229372 kb
Host smart-97e5f308-167b-4d74-8a12-1c396cb71b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11039824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.11039824
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3435805930
Short name T289
Test name
Test status
Simulation time 44388575 ps
CPU time 1.21 seconds
Started Apr 15 02:20:42 PM PDT 24
Finished Apr 15 02:20:43 PM PDT 24
Peak memory 216164 kb
Host smart-5e615e29-d08f-40e7-ae29-2df7526ae64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435805930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3435805930
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2451718648
Short name T727
Test name
Test status
Simulation time 28640099 ps
CPU time 1.25 seconds
Started Apr 15 02:20:45 PM PDT 24
Finished Apr 15 02:20:46 PM PDT 24
Peak memory 228404 kb
Host smart-a657f016-c74e-4edf-a187-c26f0b56f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451718648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2451718648
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1216461376
Short name T522
Test name
Test status
Simulation time 38316546 ps
CPU time 1.26 seconds
Started Apr 15 02:20:43 PM PDT 24
Finished Apr 15 02:20:45 PM PDT 24
Peak memory 216244 kb
Host smart-3c80cd3e-a309-4424-8e00-bc9963c59f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216461376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1216461376
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.3522936366
Short name T515
Test name
Test status
Simulation time 106103537 ps
CPU time 0.89 seconds
Started Apr 15 02:17:12 PM PDT 24
Finished Apr 15 02:17:13 PM PDT 24
Peak memory 205776 kb
Host smart-8b581d26-09b8-4355-82fb-17aac7785812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522936366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3522936366
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2755901134
Short name T733
Test name
Test status
Simulation time 14774732 ps
CPU time 0.92 seconds
Started Apr 15 02:17:15 PM PDT 24
Finished Apr 15 02:17:16 PM PDT 24
Peak memory 214956 kb
Host smart-0389c576-da26-45ee-9c32-b05eb5851348
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755901134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2755901134
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.2202978451
Short name T562
Test name
Test status
Simulation time 30156914 ps
CPU time 1.1 seconds
Started Apr 15 02:17:11 PM PDT 24
Finished Apr 15 02:17:13 PM PDT 24
Peak memory 232236 kb
Host smart-7bc7abe1-555c-4449-a1ff-4cd88da8b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202978451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2202978451
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1717081400
Short name T199
Test name
Test status
Simulation time 58128277 ps
CPU time 1.49 seconds
Started Apr 15 02:17:05 PM PDT 24
Finished Apr 15 02:17:06 PM PDT 24
Peak memory 216840 kb
Host smart-1d8e61a0-7d68-4922-93af-480d61bb363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717081400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1717081400
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2188279600
Short name T343
Test name
Test status
Simulation time 22662627 ps
CPU time 1.11 seconds
Started Apr 15 02:17:09 PM PDT 24
Finished Apr 15 02:17:11 PM PDT 24
Peak memory 215196 kb
Host smart-0d9d6d9d-a840-45cd-863a-0e195e4c3d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188279600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2188279600
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.335999644
Short name T305
Test name
Test status
Simulation time 16874421 ps
CPU time 0.96 seconds
Started Apr 15 02:16:59 PM PDT 24
Finished Apr 15 02:17:01 PM PDT 24
Peak memory 206708 kb
Host smart-7dd1633e-3b09-44c6-b249-ee48246cfae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335999644 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.335999644
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2987250004
Short name T791
Test name
Test status
Simulation time 41724065 ps
CPU time 0.89 seconds
Started Apr 15 02:17:00 PM PDT 24
Finished Apr 15 02:17:02 PM PDT 24
Peak memory 214924 kb
Host smart-100ed274-ff6b-4e92-8a2f-d0e5c689aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987250004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2987250004
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2351246021
Short name T138
Test name
Test status
Simulation time 258351612 ps
CPU time 2.04 seconds
Started Apr 15 02:17:05 PM PDT 24
Finished Apr 15 02:17:08 PM PDT 24
Peak memory 216168 kb
Host smart-1ddc4af9-dbd6-4ccc-bdbd-90a521646e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351246021 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2351246021
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3659171032
Short name T652
Test name
Test status
Simulation time 47315479089 ps
CPU time 1005.24 seconds
Started Apr 15 02:17:04 PM PDT 24
Finished Apr 15 02:33:50 PM PDT 24
Peak memory 218188 kb
Host smart-353a8689-3e31-468f-b7ab-d97d657290af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659171032 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3659171032
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2638657418
Short name T721
Test name
Test status
Simulation time 20405333 ps
CPU time 1.12 seconds
Started Apr 15 02:20:46 PM PDT 24
Finished Apr 15 02:20:48 PM PDT 24
Peak memory 218984 kb
Host smart-b5052a51-cd30-4d0c-966d-87deaba51fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638657418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2638657418
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.518653654
Short name T658
Test name
Test status
Simulation time 102260652 ps
CPU time 1.18 seconds
Started Apr 15 02:20:46 PM PDT 24
Finished Apr 15 02:20:48 PM PDT 24
Peak memory 216464 kb
Host smart-8ca660dc-fdf8-4f86-98b5-94a80bd1ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518653654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.518653654
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.1043515589
Short name T6
Test name
Test status
Simulation time 31014470 ps
CPU time 0.91 seconds
Started Apr 15 02:20:48 PM PDT 24
Finished Apr 15 02:20:49 PM PDT 24
Peak memory 218928 kb
Host smart-ccba37bc-77a2-4c8f-97e4-16e976ce57e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043515589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1043515589
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4143438466
Short name T773
Test name
Test status
Simulation time 87742360 ps
CPU time 1.19 seconds
Started Apr 15 02:20:44 PM PDT 24
Finished Apr 15 02:20:46 PM PDT 24
Peak memory 217912 kb
Host smart-938f4728-cf83-4387-8b83-796397abf2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143438466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4143438466
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2847825951
Short name T159
Test name
Test status
Simulation time 34820378 ps
CPU time 1.07 seconds
Started Apr 15 02:20:51 PM PDT 24
Finished Apr 15 02:20:53 PM PDT 24
Peak memory 219988 kb
Host smart-6daa2832-9e3b-4a8f-afbb-24cc40ee666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847825951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2847825951
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3465644437
Short name T485
Test name
Test status
Simulation time 78860373 ps
CPU time 1.15 seconds
Started Apr 15 02:20:42 PM PDT 24
Finished Apr 15 02:20:44 PM PDT 24
Peak memory 216448 kb
Host smart-728ed997-aaab-410b-8e07-e3f135dcd6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465644437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3465644437
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1944368324
Short name T420
Test name
Test status
Simulation time 61134200 ps
CPU time 0.97 seconds
Started Apr 15 02:20:50 PM PDT 24
Finished Apr 15 02:20:51 PM PDT 24
Peak memory 217924 kb
Host smart-d7721b62-1e37-4db2-abaf-cfda729e7bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944368324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1944368324
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2147639205
Short name T398
Test name
Test status
Simulation time 36072598 ps
CPU time 1.6 seconds
Started Apr 15 02:20:50 PM PDT 24
Finished Apr 15 02:20:53 PM PDT 24
Peak memory 217596 kb
Host smart-b017814b-ddd1-47c5-b6b2-3e3fc3b3d2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147639205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2147639205
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4178169387
Short name T433
Test name
Test status
Simulation time 19499611 ps
CPU time 1.08 seconds
Started Apr 15 02:21:16 PM PDT 24
Finished Apr 15 02:21:18 PM PDT 24
Peak memory 217808 kb
Host smart-0c94c4f4-0346-4306-a391-f3a95532ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178169387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4178169387
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1226716365
Short name T599
Test name
Test status
Simulation time 94031397 ps
CPU time 1.41 seconds
Started Apr 15 02:20:49 PM PDT 24
Finished Apr 15 02:20:51 PM PDT 24
Peak memory 217668 kb
Host smart-2682f6bb-b399-4b80-bf75-802b1f6f61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226716365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1226716365
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.880798097
Short name T77
Test name
Test status
Simulation time 57185711 ps
CPU time 0.95 seconds
Started Apr 15 02:20:48 PM PDT 24
Finished Apr 15 02:20:49 PM PDT 24
Peak memory 219024 kb
Host smart-bfac346d-a648-4942-80e2-a3ea20b0f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880798097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.880798097
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1340970076
Short name T570
Test name
Test status
Simulation time 50606898 ps
CPU time 1.82 seconds
Started Apr 15 02:20:48 PM PDT 24
Finished Apr 15 02:20:50 PM PDT 24
Peak memory 217696 kb
Host smart-a93c7513-0821-4d56-8bbc-e78316ef259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340970076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1340970076
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.148514230
Short name T323
Test name
Test status
Simulation time 37531342 ps
CPU time 0.84 seconds
Started Apr 15 02:20:49 PM PDT 24
Finished Apr 15 02:20:51 PM PDT 24
Peak memory 217384 kb
Host smart-9492c9ae-99ee-4738-8afd-3422f8470684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148514230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.148514230
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3904264531
Short name T12
Test name
Test status
Simulation time 25061613 ps
CPU time 1.12 seconds
Started Apr 15 02:20:50 PM PDT 24
Finished Apr 15 02:20:52 PM PDT 24
Peak memory 218632 kb
Host smart-58e919d1-0257-44bb-b829-a1c1d738b13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904264531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3904264531
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2818705818
Short name T99
Test name
Test status
Simulation time 32322088 ps
CPU time 1.17 seconds
Started Apr 15 02:20:48 PM PDT 24
Finished Apr 15 02:20:49 PM PDT 24
Peak memory 218864 kb
Host smart-adb3e516-1af3-4d21-ac21-684e5ed5a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818705818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2818705818
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4272375504
Short name T36
Test name
Test status
Simulation time 188953582 ps
CPU time 2.56 seconds
Started Apr 15 02:20:50 PM PDT 24
Finished Apr 15 02:20:53 PM PDT 24
Peak memory 217564 kb
Host smart-b30e957e-a5d2-4501-b2c7-7cfc4f4646ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272375504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4272375504
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1508005830
Short name T530
Test name
Test status
Simulation time 75279097 ps
CPU time 1.19 seconds
Started Apr 15 02:20:50 PM PDT 24
Finished Apr 15 02:20:52 PM PDT 24
Peak memory 233032 kb
Host smart-15ff8064-e48a-4d44-ac10-5821a07381d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508005830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1508005830
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3270397451
Short name T400
Test name
Test status
Simulation time 83749515 ps
CPU time 1.14 seconds
Started Apr 15 02:20:48 PM PDT 24
Finished Apr 15 02:20:50 PM PDT 24
Peak memory 218040 kb
Host smart-a313fbcd-40ea-4fc5-a3ad-945beacc3083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270397451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3270397451
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.891471345
Short name T167
Test name
Test status
Simulation time 32245800 ps
CPU time 0.88 seconds
Started Apr 15 02:20:49 PM PDT 24
Finished Apr 15 02:20:51 PM PDT 24
Peak memory 217676 kb
Host smart-b7990179-b77f-4bde-8895-e978b79566c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891471345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.891471345
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1865746882
Short name T688
Test name
Test status
Simulation time 82696804 ps
CPU time 1.14 seconds
Started Apr 15 02:20:53 PM PDT 24
Finished Apr 15 02:20:55 PM PDT 24
Peak memory 216276 kb
Host smart-253d2451-cff4-4dc0-b92f-16f6c578730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865746882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1865746882
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%