Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 8212 1 T16 214 T17 85 T18 245
all_values[1] 8212 1 T16 214 T17 85 T18 245


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8568 1 T16 219 T17 97 T18 236
auto[1] 7856 1 T16 209 T17 73 T18 254


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6442 1 T16 135 T17 68 T18 190
auto[1] 9982 1 T16 293 T17 102 T18 300


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9749 1 T16 229 T17 104 T18 282
auto[1] 6675 1 T16 199 T17 66 T18 208


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1687 1 T16 35 T17 18 T18 47
all_values[0] auto[0] auto[0] auto[1] 858 1 T16 35 T17 8 T18 24
all_values[0] auto[0] auto[1] auto[0] 1502 1 T16 30 T17 14 T18 40
all_values[0] auto[0] auto[1] auto[1] 815 1 T16 11 T17 9 T18 24
all_values[0] auto[1] auto[0] auto[1] 1745 1 T16 55 T17 20 T18 48
all_values[0] auto[1] auto[1] auto[1] 1605 1 T16 48 T17 16 T18 62
all_values[1] auto[0] auto[0] auto[0] 1714 1 T16 29 T17 18 T18 50
all_values[1] auto[0] auto[0] auto[1] 823 1 T16 19 T17 10 T18 22
all_values[1] auto[0] auto[1] auto[0] 1539 1 T16 41 T17 18 T18 53
all_values[1] auto[0] auto[1] auto[1] 811 1 T16 29 T17 9 T18 22
all_values[1] auto[1] auto[0] auto[1] 1741 1 T16 46 T17 23 T18 45
all_values[1] auto[1] auto[1] auto[1] 1584 1 T16 50 T17 7 T18 53


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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