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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.66 98.27 93.71 96.79 80.92 96.87 96.58 92.46


Total test records in report: 968
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T788 /workspace/coverage/default/114.edn_genbits.936900572 Apr 16 03:06:28 PM PDT 24 Apr 16 03:06:31 PM PDT 24 28367535 ps
T789 /workspace/coverage/default/174.edn_genbits.1333232961 Apr 16 03:06:46 PM PDT 24 Apr 16 03:06:48 PM PDT 24 34589839 ps
T790 /workspace/coverage/default/204.edn_genbits.3410076485 Apr 16 03:07:02 PM PDT 24 Apr 16 03:07:04 PM PDT 24 41014603 ps
T791 /workspace/coverage/default/38.edn_genbits.1043243835 Apr 16 03:04:39 PM PDT 24 Apr 16 03:04:41 PM PDT 24 28687977 ps
T792 /workspace/coverage/default/45.edn_alert_test.3641114790 Apr 16 03:05:19 PM PDT 24 Apr 16 03:05:20 PM PDT 24 72894272 ps
T793 /workspace/coverage/default/128.edn_genbits.2371790335 Apr 16 03:06:28 PM PDT 24 Apr 16 03:06:30 PM PDT 24 37706582 ps
T794 /workspace/coverage/default/291.edn_genbits.3850121666 Apr 16 03:07:35 PM PDT 24 Apr 16 03:07:38 PM PDT 24 39947927 ps
T795 /workspace/coverage/default/34.edn_smoke.677808107 Apr 16 03:04:19 PM PDT 24 Apr 16 03:04:21 PM PDT 24 26671996 ps
T796 /workspace/coverage/default/19.edn_genbits.293804210 Apr 16 03:03:09 PM PDT 24 Apr 16 03:03:10 PM PDT 24 34684826 ps
T797 /workspace/coverage/default/257.edn_genbits.3271638483 Apr 16 03:07:16 PM PDT 24 Apr 16 03:07:18 PM PDT 24 68019061 ps
T798 /workspace/coverage/default/47.edn_alert.2314236326 Apr 16 03:05:22 PM PDT 24 Apr 16 03:05:23 PM PDT 24 76184175 ps
T799 /workspace/coverage/default/150.edn_genbits.2280333128 Apr 16 03:06:37 PM PDT 24 Apr 16 03:06:39 PM PDT 24 36647108 ps
T800 /workspace/coverage/default/9.edn_disable_auto_req_mode.4126459038 Apr 16 03:02:02 PM PDT 24 Apr 16 03:02:04 PM PDT 24 21114647 ps
T801 /workspace/coverage/default/25.edn_alert_test.1093416215 Apr 16 03:03:38 PM PDT 24 Apr 16 03:03:40 PM PDT 24 36564734 ps
T282 /workspace/coverage/default/122.edn_genbits.438856734 Apr 16 03:06:28 PM PDT 24 Apr 16 03:06:31 PM PDT 24 58889362 ps
T802 /workspace/coverage/default/48.edn_stress_all.3940339590 Apr 16 03:05:29 PM PDT 24 Apr 16 03:05:31 PM PDT 24 642793537 ps
T803 /workspace/coverage/default/65.edn_genbits.422731662 Apr 16 03:05:47 PM PDT 24 Apr 16 03:05:49 PM PDT 24 53757203 ps
T804 /workspace/coverage/default/16.edn_smoke.535125889 Apr 16 03:02:46 PM PDT 24 Apr 16 03:02:48 PM PDT 24 48823551 ps
T805 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3331205608 Apr 16 03:05:27 PM PDT 24 Apr 16 03:21:02 PM PDT 24 101462911188 ps
T806 /workspace/coverage/default/61.edn_err.3700841631 Apr 16 03:05:49 PM PDT 24 Apr 16 03:05:51 PM PDT 24 21177863 ps
T807 /workspace/coverage/default/245.edn_genbits.1182836782 Apr 16 03:07:16 PM PDT 24 Apr 16 03:07:18 PM PDT 24 55567598 ps
T808 /workspace/coverage/default/179.edn_genbits.4119113659 Apr 16 03:06:54 PM PDT 24 Apr 16 03:06:57 PM PDT 24 360657883 ps
T809 /workspace/coverage/default/40.edn_stress_all.440837559 Apr 16 03:04:50 PM PDT 24 Apr 16 03:04:54 PM PDT 24 248351123 ps
T810 /workspace/coverage/default/13.edn_genbits.3223069942 Apr 16 03:02:27 PM PDT 24 Apr 16 03:02:29 PM PDT 24 100818446 ps
T811 /workspace/coverage/default/4.edn_genbits.3104270793 Apr 16 03:01:24 PM PDT 24 Apr 16 03:01:26 PM PDT 24 29323943 ps
T812 /workspace/coverage/default/37.edn_disable_auto_req_mode.3163311457 Apr 16 03:04:42 PM PDT 24 Apr 16 03:04:45 PM PDT 24 28879701 ps
T813 /workspace/coverage/default/57.edn_genbits.2297356455 Apr 16 03:05:47 PM PDT 24 Apr 16 03:05:49 PM PDT 24 76719094 ps
T814 /workspace/coverage/default/278.edn_genbits.1558355930 Apr 16 03:07:28 PM PDT 24 Apr 16 03:07:30 PM PDT 24 33985254 ps
T815 /workspace/coverage/default/9.edn_intr.3465765164 Apr 16 03:02:05 PM PDT 24 Apr 16 03:02:07 PM PDT 24 25242291 ps
T52 /workspace/coverage/default/1.edn_sec_cm.235544128 Apr 16 03:01:07 PM PDT 24 Apr 16 03:01:16 PM PDT 24 1565276554 ps
T816 /workspace/coverage/default/155.edn_genbits.503596542 Apr 16 03:06:48 PM PDT 24 Apr 16 03:06:50 PM PDT 24 77986476 ps
T62 /workspace/coverage/default/85.edn_err.2749164045 Apr 16 03:06:08 PM PDT 24 Apr 16 03:06:10 PM PDT 24 33470408 ps
T817 /workspace/coverage/default/13.edn_disable.3048865430 Apr 16 03:02:28 PM PDT 24 Apr 16 03:02:30 PM PDT 24 39729951 ps
T818 /workspace/coverage/default/41.edn_intr.3281548912 Apr 16 03:04:54 PM PDT 24 Apr 16 03:04:56 PM PDT 24 21943797 ps
T819 /workspace/coverage/default/45.edn_intr.2185824279 Apr 16 03:05:13 PM PDT 24 Apr 16 03:05:14 PM PDT 24 59357359 ps
T820 /workspace/coverage/default/43.edn_alert_test.3029677891 Apr 16 03:05:07 PM PDT 24 Apr 16 03:05:09 PM PDT 24 19840424 ps
T821 /workspace/coverage/default/4.edn_intr.3487155336 Apr 16 03:01:23 PM PDT 24 Apr 16 03:01:25 PM PDT 24 27111176 ps
T822 /workspace/coverage/default/175.edn_genbits.378871700 Apr 16 03:06:47 PM PDT 24 Apr 16 03:06:49 PM PDT 24 22698178 ps
T823 /workspace/coverage/default/23.edn_err.731743437 Apr 16 03:03:28 PM PDT 24 Apr 16 03:03:30 PM PDT 24 18543896 ps
T824 /workspace/coverage/default/275.edn_genbits.3892413786 Apr 16 03:07:28 PM PDT 24 Apr 16 03:09:43 PM PDT 24 10461903251 ps
T825 /workspace/coverage/default/3.edn_smoke.3881593578 Apr 16 03:01:12 PM PDT 24 Apr 16 03:01:14 PM PDT 24 18256764 ps
T826 /workspace/coverage/default/1.edn_disable.2622264781 Apr 16 03:01:06 PM PDT 24 Apr 16 03:01:07 PM PDT 24 11038540 ps
T827 /workspace/coverage/default/44.edn_genbits.3427873136 Apr 16 03:05:09 PM PDT 24 Apr 16 03:05:10 PM PDT 24 70195666 ps
T828 /workspace/coverage/default/202.edn_genbits.3907737310 Apr 16 03:06:56 PM PDT 24 Apr 16 03:06:59 PM PDT 24 49785679 ps
T829 /workspace/coverage/default/47.edn_alert_test.458796728 Apr 16 03:05:21 PM PDT 24 Apr 16 03:05:22 PM PDT 24 44876361 ps
T830 /workspace/coverage/default/266.edn_genbits.2873333145 Apr 16 03:07:21 PM PDT 24 Apr 16 03:07:24 PM PDT 24 314740702 ps
T831 /workspace/coverage/default/254.edn_genbits.1198106297 Apr 16 03:07:17 PM PDT 24 Apr 16 03:07:19 PM PDT 24 96264118 ps
T832 /workspace/coverage/default/51.edn_err.3711700835 Apr 16 03:05:40 PM PDT 24 Apr 16 03:05:42 PM PDT 24 26917947 ps
T833 /workspace/coverage/default/28.edn_alert_test.3142269973 Apr 16 03:03:55 PM PDT 24 Apr 16 03:03:57 PM PDT 24 22800089 ps
T834 /workspace/coverage/default/176.edn_genbits.4260357078 Apr 16 03:06:47 PM PDT 24 Apr 16 03:06:49 PM PDT 24 99128963 ps
T835 /workspace/coverage/default/28.edn_disable_auto_req_mode.650889562 Apr 16 03:04:39 PM PDT 24 Apr 16 03:04:41 PM PDT 24 126390546 ps
T836 /workspace/coverage/default/70.edn_err.256088977 Apr 16 03:05:53 PM PDT 24 Apr 16 03:05:55 PM PDT 24 24131406 ps
T837 /workspace/coverage/default/7.edn_stress_all.2559888758 Apr 16 03:01:44 PM PDT 24 Apr 16 03:01:52 PM PDT 24 394547338 ps
T838 /workspace/coverage/cover_reg_top/25.edn_intr_test.1722698310 Apr 16 02:38:34 PM PDT 24 Apr 16 02:38:42 PM PDT 24 52724128 ps
T839 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2606268874 Apr 16 02:38:27 PM PDT 24 Apr 16 02:38:39 PM PDT 24 112307105 ps
T840 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2914323669 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 16423838 ps
T841 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3921941291 Apr 16 02:38:28 PM PDT 24 Apr 16 02:38:41 PM PDT 24 303314654 ps
T198 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1398930115 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:29 PM PDT 24 39871397 ps
T842 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2647146981 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:40 PM PDT 24 74722095 ps
T843 /workspace/coverage/cover_reg_top/2.edn_intr_test.3149393063 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:16 PM PDT 24 26649680 ps
T844 /workspace/coverage/cover_reg_top/48.edn_intr_test.764298837 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:32 PM PDT 24 13277204 ps
T223 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1361005802 Apr 16 02:38:12 PM PDT 24 Apr 16 02:38:15 PM PDT 24 111150458 ps
T845 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.824677827 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:18 PM PDT 24 20785637 ps
T846 /workspace/coverage/cover_reg_top/16.edn_intr_test.1549690689 Apr 16 02:38:30 PM PDT 24 Apr 16 02:38:39 PM PDT 24 45684183 ps
T224 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3504509827 Apr 16 02:38:26 PM PDT 24 Apr 16 02:38:34 PM PDT 24 41098212 ps
T225 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.593039733 Apr 16 02:38:16 PM PDT 24 Apr 16 02:38:18 PM PDT 24 89495583 ps
T199 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3270846098 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:31 PM PDT 24 53533488 ps
T847 /workspace/coverage/cover_reg_top/42.edn_intr_test.412264341 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 31164763 ps
T848 /workspace/coverage/cover_reg_top/49.edn_intr_test.4100057009 Apr 16 02:38:37 PM PDT 24 Apr 16 02:38:43 PM PDT 24 22474253 ps
T229 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.591151178 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:18 PM PDT 24 313682964 ps
T849 /workspace/coverage/cover_reg_top/44.edn_intr_test.924276443 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:40 PM PDT 24 23266831 ps
T230 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1895206881 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:22 PM PDT 24 80411814 ps
T850 /workspace/coverage/cover_reg_top/45.edn_intr_test.1163940163 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:43 PM PDT 24 14389549 ps
T851 /workspace/coverage/cover_reg_top/7.edn_tl_errors.258382704 Apr 16 02:38:22 PM PDT 24 Apr 16 02:38:26 PM PDT 24 229737584 ps
T220 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3173493894 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:20 PM PDT 24 31908971 ps
T221 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3882330403 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:17 PM PDT 24 43274326 ps
T852 /workspace/coverage/cover_reg_top/11.edn_intr_test.1875879928 Apr 16 02:38:26 PM PDT 24 Apr 16 02:38:34 PM PDT 24 37482009 ps
T200 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.299548826 Apr 16 02:37:40 PM PDT 24 Apr 16 02:37:42 PM PDT 24 30723065 ps
T232 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4032484501 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:44 PM PDT 24 266977567 ps
T233 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3695098949 Apr 16 02:38:14 PM PDT 24 Apr 16 02:38:17 PM PDT 24 110999739 ps
T201 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2952359836 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:17 PM PDT 24 32590702 ps
T853 /workspace/coverage/cover_reg_top/14.edn_intr_test.2962433906 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:30 PM PDT 24 125699974 ps
T222 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2687615163 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:21 PM PDT 24 51636761 ps
T854 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1881016028 Apr 16 02:38:21 PM PDT 24 Apr 16 02:38:25 PM PDT 24 68920796 ps
T855 /workspace/coverage/cover_reg_top/1.edn_intr_test.502255755 Apr 16 02:37:38 PM PDT 24 Apr 16 02:37:40 PM PDT 24 14924749 ps
T856 /workspace/coverage/cover_reg_top/30.edn_intr_test.3361083338 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 24294235 ps
T202 /workspace/coverage/cover_reg_top/3.edn_csr_rw.4197533513 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:17 PM PDT 24 28084115 ps
T857 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2592732509 Apr 16 02:38:17 PM PDT 24 Apr 16 02:38:20 PM PDT 24 68147440 ps
T858 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1810183983 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:33 PM PDT 24 98891045 ps
T203 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1775306908 Apr 16 02:37:40 PM PDT 24 Apr 16 02:37:42 PM PDT 24 69957090 ps
T215 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1775425868 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:24 PM PDT 24 106494989 ps
T204 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2717418376 Apr 16 02:38:17 PM PDT 24 Apr 16 02:38:22 PM PDT 24 60757420 ps
T205 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2282517454 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 33195124 ps
T859 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3589731524 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:32 PM PDT 24 152310474 ps
T860 /workspace/coverage/cover_reg_top/22.edn_intr_test.1365287561 Apr 16 02:38:34 PM PDT 24 Apr 16 02:38:42 PM PDT 24 53076237 ps
T216 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.687892019 Apr 16 02:38:26 PM PDT 24 Apr 16 02:38:34 PM PDT 24 21210066 ps
T206 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1654187606 Apr 16 02:37:41 PM PDT 24 Apr 16 02:37:43 PM PDT 24 33045001 ps
T217 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2404654644 Apr 16 02:37:42 PM PDT 24 Apr 16 02:37:44 PM PDT 24 73027193 ps
T207 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1801663485 Apr 16 02:37:39 PM PDT 24 Apr 16 02:37:43 PM PDT 24 235496025 ps
T861 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2352498070 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:40 PM PDT 24 96409368 ps
T862 /workspace/coverage/cover_reg_top/33.edn_intr_test.605202811 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 50183948 ps
T218 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1586853509 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:22 PM PDT 24 22543022 ps
T863 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3654147886 Apr 16 02:38:27 PM PDT 24 Apr 16 02:38:37 PM PDT 24 29890172 ps
T864 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.618074451 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:40 PM PDT 24 36160504 ps
T865 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1719574923 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:29 PM PDT 24 73436555 ps
T866 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2470797386 Apr 16 02:38:26 PM PDT 24 Apr 16 02:38:34 PM PDT 24 28764174 ps
T208 /workspace/coverage/cover_reg_top/6.edn_csr_rw.4266522782 Apr 16 02:38:22 PM PDT 24 Apr 16 02:38:25 PM PDT 24 25919495 ps
T231 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3965967711 Apr 16 02:38:21 PM PDT 24 Apr 16 02:38:25 PM PDT 24 608218997 ps
T209 /workspace/coverage/cover_reg_top/1.edn_csr_rw.476313213 Apr 16 02:38:12 PM PDT 24 Apr 16 02:38:13 PM PDT 24 11994746 ps
T867 /workspace/coverage/cover_reg_top/37.edn_intr_test.139635023 Apr 16 02:38:37 PM PDT 24 Apr 16 02:38:43 PM PDT 24 45301651 ps
T219 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3696878910 Apr 16 02:38:27 PM PDT 24 Apr 16 02:38:36 PM PDT 24 86681823 ps
T868 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2805354442 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:25 PM PDT 24 557131110 ps
T869 /workspace/coverage/cover_reg_top/35.edn_intr_test.369198121 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:43 PM PDT 24 12493120 ps
T870 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.161184395 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:33 PM PDT 24 27339930 ps
T871 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4067600564 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:30 PM PDT 24 33357317 ps
T872 /workspace/coverage/cover_reg_top/13.edn_intr_test.580020377 Apr 16 02:38:28 PM PDT 24 Apr 16 02:38:37 PM PDT 24 98813204 ps
T873 /workspace/coverage/cover_reg_top/11.edn_tl_errors.202539056 Apr 16 02:38:28 PM PDT 24 Apr 16 02:38:38 PM PDT 24 160202408 ps
T874 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3156743047 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:40 PM PDT 24 59038643 ps
T875 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1080887936 Apr 16 02:38:17 PM PDT 24 Apr 16 02:38:20 PM PDT 24 77706714 ps
T876 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1125080724 Apr 16 02:38:22 PM PDT 24 Apr 16 02:38:25 PM PDT 24 74301786 ps
T877 /workspace/coverage/cover_reg_top/38.edn_intr_test.58705844 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 16553111 ps
T878 /workspace/coverage/cover_reg_top/40.edn_intr_test.3485969323 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 26413091 ps
T879 /workspace/coverage/cover_reg_top/10.edn_intr_test.3068727543 Apr 16 02:38:23 PM PDT 24 Apr 16 02:38:28 PM PDT 24 71192145 ps
T880 /workspace/coverage/cover_reg_top/26.edn_intr_test.3305857920 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 170999828 ps
T881 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.322247441 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:29 PM PDT 24 198961551 ps
T882 /workspace/coverage/cover_reg_top/4.edn_intr_test.1956977051 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:20 PM PDT 24 49819718 ps
T883 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3237729119 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 36155607 ps
T884 /workspace/coverage/cover_reg_top/32.edn_intr_test.1473238311 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 30539438 ps
T885 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3053693527 Apr 16 02:38:14 PM PDT 24 Apr 16 02:38:15 PM PDT 24 60089001 ps
T886 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2292132453 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:20 PM PDT 24 33898400 ps
T887 /workspace/coverage/cover_reg_top/24.edn_intr_test.428117093 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:43 PM PDT 24 16564339 ps
T888 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4228121153 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:21 PM PDT 24 142516804 ps
T889 /workspace/coverage/cover_reg_top/36.edn_intr_test.450922723 Apr 16 02:38:37 PM PDT 24 Apr 16 02:38:43 PM PDT 24 14695405 ps
T890 /workspace/coverage/cover_reg_top/31.edn_intr_test.3136714404 Apr 16 02:38:34 PM PDT 24 Apr 16 02:38:42 PM PDT 24 43422428 ps
T891 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3867224520 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:38 PM PDT 24 108079597 ps
T892 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1667923192 Apr 16 02:38:11 PM PDT 24 Apr 16 02:38:13 PM PDT 24 74346311 ps
T893 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3346836121 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:34 PM PDT 24 341386520 ps
T894 /workspace/coverage/cover_reg_top/19.edn_csr_rw.645092448 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 31478455 ps
T895 /workspace/coverage/cover_reg_top/39.edn_intr_test.462322865 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:43 PM PDT 24 27684647 ps
T896 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1079317122 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:17 PM PDT 24 492785054 ps
T234 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.508500217 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:25 PM PDT 24 137924302 ps
T897 /workspace/coverage/cover_reg_top/29.edn_intr_test.2045939541 Apr 16 02:38:38 PM PDT 24 Apr 16 02:38:43 PM PDT 24 16715805 ps
T898 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.327803993 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:22 PM PDT 24 187164470 ps
T899 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3001858558 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:22 PM PDT 24 41117919 ps
T900 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1422987681 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:23 PM PDT 24 37437781 ps
T901 /workspace/coverage/cover_reg_top/15.edn_csr_rw.49280163 Apr 16 02:38:32 PM PDT 24 Apr 16 02:38:40 PM PDT 24 29642127 ps
T902 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3034776813 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:24 PM PDT 24 70003034 ps
T903 /workspace/coverage/cover_reg_top/17.edn_intr_test.3426000694 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:39 PM PDT 24 11459642 ps
T904 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3330212888 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:39 PM PDT 24 52069331 ps
T905 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.509838890 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:24 PM PDT 24 148139169 ps
T906 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2919626813 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:22 PM PDT 24 17686727 ps
T907 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.50259228 Apr 16 02:38:32 PM PDT 24 Apr 16 02:38:41 PM PDT 24 17710806 ps
T908 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1424483883 Apr 16 02:38:16 PM PDT 24 Apr 16 02:38:18 PM PDT 24 33430270 ps
T909 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1841560543 Apr 16 02:38:22 PM PDT 24 Apr 16 02:38:25 PM PDT 24 15257411 ps
T210 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.576284859 Apr 16 02:38:16 PM PDT 24 Apr 16 02:38:19 PM PDT 24 74953737 ps
T910 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2364951669 Apr 16 02:38:30 PM PDT 24 Apr 16 02:38:39 PM PDT 24 33431576 ps
T911 /workspace/coverage/cover_reg_top/21.edn_intr_test.1287615478 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:43 PM PDT 24 15817224 ps
T912 /workspace/coverage/cover_reg_top/6.edn_intr_test.1470350268 Apr 16 02:38:27 PM PDT 24 Apr 16 02:38:35 PM PDT 24 44799944 ps
T913 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1866241767 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:23 PM PDT 24 21002287 ps
T914 /workspace/coverage/cover_reg_top/9.edn_intr_test.3192927195 Apr 16 02:38:21 PM PDT 24 Apr 16 02:38:24 PM PDT 24 16298528 ps
T915 /workspace/coverage/cover_reg_top/28.edn_intr_test.324370533 Apr 16 02:38:35 PM PDT 24 Apr 16 02:38:42 PM PDT 24 43458457 ps
T916 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4222296369 Apr 16 02:38:17 PM PDT 24 Apr 16 02:38:20 PM PDT 24 49390049 ps
T917 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.551708699 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:29 PM PDT 24 53119800 ps
T918 /workspace/coverage/cover_reg_top/17.edn_tl_errors.767023721 Apr 16 02:38:32 PM PDT 24 Apr 16 02:38:41 PM PDT 24 55280542 ps
T214 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.471576129 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:20 PM PDT 24 905133734 ps
T919 /workspace/coverage/cover_reg_top/23.edn_intr_test.1896724145 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 13959669 ps
T920 /workspace/coverage/cover_reg_top/46.edn_intr_test.1883116828 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 15941489 ps
T921 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2417335397 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:34 PM PDT 24 110509718 ps
T922 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2450784757 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:17 PM PDT 24 33976784 ps
T923 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1677831771 Apr 16 02:38:26 PM PDT 24 Apr 16 02:38:33 PM PDT 24 27685151 ps
T924 /workspace/coverage/cover_reg_top/41.edn_intr_test.627569143 Apr 16 02:38:34 PM PDT 24 Apr 16 02:38:41 PM PDT 24 12971853 ps
T925 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3568776711 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 120736726 ps
T926 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1775132588 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:39 PM PDT 24 201016824 ps
T927 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3650354070 Apr 16 02:38:11 PM PDT 24 Apr 16 02:38:13 PM PDT 24 39072751 ps
T928 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3267694238 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:21 PM PDT 24 15645379 ps
T929 /workspace/coverage/cover_reg_top/15.edn_intr_test.1029668860 Apr 16 02:38:28 PM PDT 24 Apr 16 02:38:37 PM PDT 24 47433201 ps
T930 /workspace/coverage/cover_reg_top/8.edn_intr_test.3588794936 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 14610545 ps
T931 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2570034583 Apr 16 02:38:12 PM PDT 24 Apr 16 02:38:14 PM PDT 24 14437753 ps
T932 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3626991170 Apr 16 02:37:40 PM PDT 24 Apr 16 02:37:42 PM PDT 24 62711454 ps
T933 /workspace/coverage/cover_reg_top/20.edn_intr_test.3468247267 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 14726068 ps
T934 /workspace/coverage/cover_reg_top/19.edn_intr_test.803994953 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:40 PM PDT 24 11464246 ps
T935 /workspace/coverage/cover_reg_top/12.edn_intr_test.3542382191 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:30 PM PDT 24 15043510 ps
T936 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1168814941 Apr 16 02:38:23 PM PDT 24 Apr 16 02:38:26 PM PDT 24 14502860 ps
T937 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3929742354 Apr 16 02:38:16 PM PDT 24 Apr 16 02:38:18 PM PDT 24 299648384 ps
T938 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.605063418 Apr 16 02:38:18 PM PDT 24 Apr 16 02:38:21 PM PDT 24 51871416 ps
T939 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1412115958 Apr 16 02:37:40 PM PDT 24 Apr 16 02:37:45 PM PDT 24 116508131 ps
T940 /workspace/coverage/cover_reg_top/5.edn_intr_test.220438393 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 37154952 ps
T941 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.415934699 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:32 PM PDT 24 68783942 ps
T942 /workspace/coverage/cover_reg_top/7.edn_intr_test.3170049410 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 12633876 ps
T943 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2305548131 Apr 16 02:38:27 PM PDT 24 Apr 16 02:38:36 PM PDT 24 78869149 ps
T211 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1852901045 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:31 PM PDT 24 14546794 ps
T944 /workspace/coverage/cover_reg_top/17.edn_csr_rw.552286842 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:38 PM PDT 24 41691529 ps
T945 /workspace/coverage/cover_reg_top/27.edn_intr_test.902139750 Apr 16 02:38:32 PM PDT 24 Apr 16 02:38:40 PM PDT 24 11354928 ps
T946 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4276555718 Apr 16 02:37:41 PM PDT 24 Apr 16 02:37:44 PM PDT 24 462755145 ps
T947 /workspace/coverage/cover_reg_top/43.edn_intr_test.1676523890 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:43 PM PDT 24 30821544 ps
T948 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4050948964 Apr 16 02:38:33 PM PDT 24 Apr 16 02:38:41 PM PDT 24 37656764 ps
T212 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1481054793 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:38 PM PDT 24 27020838 ps
T949 /workspace/coverage/cover_reg_top/5.edn_csr_rw.97677786 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:22 PM PDT 24 42714231 ps
T950 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3749191594 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:29 PM PDT 24 37949250 ps
T951 /workspace/coverage/cover_reg_top/18.edn_intr_test.314151311 Apr 16 02:38:30 PM PDT 24 Apr 16 02:38:38 PM PDT 24 11742831 ps
T952 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3148866103 Apr 16 02:38:28 PM PDT 24 Apr 16 02:38:37 PM PDT 24 51163537 ps
T953 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1554857690 Apr 16 02:38:25 PM PDT 24 Apr 16 02:38:31 PM PDT 24 16213721 ps
T954 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3295308012 Apr 16 02:38:31 PM PDT 24 Apr 16 02:38:41 PM PDT 24 128586556 ps
T955 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3093112761 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:24 PM PDT 24 189240601 ps
T956 /workspace/coverage/cover_reg_top/16.edn_csr_rw.113113901 Apr 16 02:38:30 PM PDT 24 Apr 16 02:38:38 PM PDT 24 14926814 ps
T957 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3941761747 Apr 16 02:38:15 PM PDT 24 Apr 16 02:38:20 PM PDT 24 177197953 ps
T958 /workspace/coverage/cover_reg_top/0.edn_intr_test.192442753 Apr 16 02:38:12 PM PDT 24 Apr 16 02:38:13 PM PDT 24 14111670 ps
T959 /workspace/coverage/cover_reg_top/3.edn_intr_test.2289960136 Apr 16 02:38:19 PM PDT 24 Apr 16 02:38:22 PM PDT 24 12621203 ps
T960 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.710574789 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 182691292 ps
T961 /workspace/coverage/cover_reg_top/47.edn_intr_test.3675689084 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:30 PM PDT 24 26205685 ps
T962 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3641030351 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 21531114 ps
T963 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.834232614 Apr 16 02:38:20 PM PDT 24 Apr 16 02:38:23 PM PDT 24 18922927 ps
T964 /workspace/coverage/cover_reg_top/34.edn_intr_test.1224296993 Apr 16 02:38:36 PM PDT 24 Apr 16 02:38:42 PM PDT 24 21665654 ps
T965 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4088505024 Apr 16 02:37:40 PM PDT 24 Apr 16 02:37:42 PM PDT 24 58932493 ps
T966 /workspace/coverage/cover_reg_top/1.edn_tl_errors.108723981 Apr 16 02:37:39 PM PDT 24 Apr 16 02:37:42 PM PDT 24 129927810 ps
T213 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1023642876 Apr 16 02:38:24 PM PDT 24 Apr 16 02:38:30 PM PDT 24 11908862 ps
T967 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4114598502 Apr 16 02:38:29 PM PDT 24 Apr 16 02:38:39 PM PDT 24 269272490 ps
T968 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4016004992 Apr 16 02:38:30 PM PDT 24 Apr 16 02:38:39 PM PDT 24 95347657 ps

Test location /workspace/coverage/default/281.edn_genbits.1212375873
Short name T19
Test name
Test status
Simulation time 315637401 ps
CPU time 4.33 seconds
Started Apr 16 03:07:27 PM PDT 24
Finished Apr 16 03:07:32 PM PDT 24
Peak memory 219556 kb
Host smart-c7cc7d04-80e8-465e-8670-cf8a4a54256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212375873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1212375873
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3748592839
Short name T16
Test name
Test status
Simulation time 1146672483312 ps
CPU time 1887.2 seconds
Started Apr 16 03:01:53 PM PDT 24
Finished Apr 16 03:33:22 PM PDT 24
Peak memory 224684 kb
Host smart-7a9cbf47-ca0a-4760-8b82-7f088dae498e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748592839 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3748592839
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_err.2953939165
Short name T45
Test name
Test status
Simulation time 24036694 ps
CPU time 1.04 seconds
Started Apr 16 03:03:23 PM PDT 24
Finished Apr 16 03:03:25 PM PDT 24
Peak memory 230980 kb
Host smart-c401c838-a705-405a-b02a-550fa73fac71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953939165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2953939165
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/46.edn_alert.626272841
Short name T99
Test name
Test status
Simulation time 53028771 ps
CPU time 1.15 seconds
Started Apr 16 03:05:24 PM PDT 24
Finished Apr 16 03:05:26 PM PDT 24
Peak memory 215280 kb
Host smart-b33a6815-20b2-4570-b5e1-be54c7e41a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626272841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.626272841
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1452554552
Short name T14
Test name
Test status
Simulation time 1503818687 ps
CPU time 6.01 seconds
Started Apr 16 03:01:16 PM PDT 24
Finished Apr 16 03:01:23 PM PDT 24
Peak memory 235656 kb
Host smart-809a5aad-153a-443d-8b94-6479a76016ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452554552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1452554552
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/227.edn_genbits.746434107
Short name T34
Test name
Test status
Simulation time 85828267 ps
CPU time 1.4 seconds
Started Apr 16 03:07:06 PM PDT 24
Finished Apr 16 03:07:08 PM PDT 24
Peak memory 217948 kb
Host smart-948a6cf7-59d1-4408-98f6-f8c0c56c3743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746434107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.746434107
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable.1580930497
Short name T116
Test name
Test status
Simulation time 11379059 ps
CPU time 0.86 seconds
Started Apr 16 03:02:21 PM PDT 24
Finished Apr 16 03:02:23 PM PDT 24
Peak memory 215432 kb
Host smart-bb3bb740-2185-41d9-b7c6-f3ad19000765
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580930497 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1580930497
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/5.edn_alert.3464593403
Short name T40
Test name
Test status
Simulation time 27170823 ps
CPU time 1.31 seconds
Started Apr 16 03:01:33 PM PDT 24
Finished Apr 16 03:01:35 PM PDT 24
Peak memory 215248 kb
Host smart-f9f4a89a-7ab6-4bdb-a811-53a448886c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464593403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3464593403
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/32.edn_intr.2783312062
Short name T21
Test name
Test status
Simulation time 34702159 ps
CPU time 0.87 seconds
Started Apr 16 03:04:14 PM PDT 24
Finished Apr 16 03:04:16 PM PDT 24
Peak memory 215216 kb
Host smart-6bc81243-8cd7-4b2c-93d8-d3c58b33395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783312062 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2783312062
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1242682147
Short name T17
Test name
Test status
Simulation time 67124893893 ps
CPU time 1065.28 seconds
Started Apr 16 03:01:40 PM PDT 24
Finished Apr 16 03:19:26 PM PDT 24
Peak memory 220236 kb
Host smart-2f5e77bb-91c8-4e9b-8fe8-4b25ebdbb13c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242682147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1242682147
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2446035224
Short name T69
Test name
Test status
Simulation time 66444301 ps
CPU time 1.2 seconds
Started Apr 16 03:03:27 PM PDT 24
Finished Apr 16 03:03:29 PM PDT 24
Peak memory 216076 kb
Host smart-2d735477-0df4-41cc-9798-cb2900474ecb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446035224 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2446035224
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_regwen.2970129171
Short name T54
Test name
Test status
Simulation time 43947163 ps
CPU time 0.92 seconds
Started Apr 16 03:01:23 PM PDT 24
Finished Apr 16 03:01:25 PM PDT 24
Peak memory 206648 kb
Host smart-cbe48513-66a5-4064-b66f-96b0277cafa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970129171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2970129171
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/33.edn_alert.2644516653
Short name T121
Test name
Test status
Simulation time 267838761 ps
CPU time 1.3 seconds
Started Apr 16 03:04:20 PM PDT 24
Finished Apr 16 03:04:22 PM PDT 24
Peak memory 215296 kb
Host smart-496acf70-5132-49b5-a21a-b633d392ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644516653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2644516653
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/7.edn_intr.2065382596
Short name T1
Test name
Test status
Simulation time 34808834 ps
CPU time 0.99 seconds
Started Apr 16 03:01:46 PM PDT 24
Finished Apr 16 03:01:48 PM PDT 24
Peak memory 223672 kb
Host smart-e377181d-3f85-41d2-995b-9755350ed23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065382596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2065382596
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2952359836
Short name T201
Test name
Test status
Simulation time 32590702 ps
CPU time 0.82 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:17 PM PDT 24
Peak memory 206072 kb
Host smart-a0a95ded-ca41-4e2f-ac1e-4449389ccebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952359836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2952359836
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1361005802
Short name T223
Test name
Test status
Simulation time 111150458 ps
CPU time 2.53 seconds
Started Apr 16 02:38:12 PM PDT 24
Finished Apr 16 02:38:15 PM PDT 24
Peak memory 206140 kb
Host smart-80ecaadd-f87b-4b93-a824-8794a89a6528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361005802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1361005802
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_disable.2622264781
Short name T826
Test name
Test status
Simulation time 11038540 ps
CPU time 0.83 seconds
Started Apr 16 03:01:06 PM PDT 24
Finished Apr 16 03:01:07 PM PDT 24
Peak memory 215516 kb
Host smart-9f43d15e-a921-44b3-b537-a4518cb74ef5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622264781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2622264781
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3363990186
Short name T86
Test name
Test status
Simulation time 26902868 ps
CPU time 0.97 seconds
Started Apr 16 03:04:33 PM PDT 24
Finished Apr 16 03:04:35 PM PDT 24
Peak memory 216132 kb
Host smart-a9960b21-2731-4284-be8e-c5fd450f0074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363990186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3363990186
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_disable.4061511121
Short name T109
Test name
Test status
Simulation time 15788461 ps
CPU time 0.82 seconds
Started Apr 16 03:04:31 PM PDT 24
Finished Apr 16 03:04:33 PM PDT 24
Peak memory 215464 kb
Host smart-86d4c874-59b8-43c7-a7e2-a05e68929bdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061511121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4061511121
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/13.edn_intr.1029029208
Short name T59
Test name
Test status
Simulation time 55143068 ps
CPU time 0.88 seconds
Started Apr 16 03:02:27 PM PDT 24
Finished Apr 16 03:02:29 PM PDT 24
Peak memory 215184 kb
Host smart-00ad85ba-5914-4ffd-9915-547b6be0948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029029208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1029029208
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/12.edn_alert.333072163
Short name T151
Test name
Test status
Simulation time 84159102 ps
CPU time 1.3 seconds
Started Apr 16 03:02:20 PM PDT 24
Finished Apr 16 03:02:22 PM PDT 24
Peak memory 215296 kb
Host smart-e601d752-e1a5-492c-b829-44b57ef38308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333072163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.333072163
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/18.edn_genbits.2687023483
Short name T228
Test name
Test status
Simulation time 53290110 ps
CPU time 1.41 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:03:00 PM PDT 24
Peak memory 217504 kb
Host smart-8c0cbfd7-2454-4210-bd36-5efe8de9f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687023483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2687023483
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.397156508
Short name T178
Test name
Test status
Simulation time 65287478 ps
CPU time 1.36 seconds
Started Apr 16 03:07:14 PM PDT 24
Finished Apr 16 03:07:16 PM PDT 24
Peak memory 217496 kb
Host smart-ee1244c4-4492-46e4-914f-7ab290a49afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397156508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.397156508
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.3106193165
Short name T104
Test name
Test status
Simulation time 25141273 ps
CPU time 1.19 seconds
Started Apr 16 03:00:55 PM PDT 24
Finished Apr 16 03:00:57 PM PDT 24
Peak memory 215324 kb
Host smart-7e638e27-4f96-4568-b6f3-dabf9a99bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106193165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3106193165
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3492010249
Short name T235
Test name
Test status
Simulation time 90700357 ps
CPU time 1.03 seconds
Started Apr 16 03:03:44 PM PDT 24
Finished Apr 16 03:03:46 PM PDT 24
Peak memory 216248 kb
Host smart-7cf28b3a-29c0-4daf-87e9-c196b337b682
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492010249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3492010249
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/89.edn_genbits.2842612846
Short name T169
Test name
Test status
Simulation time 46904531 ps
CPU time 1.16 seconds
Started Apr 16 03:06:06 PM PDT 24
Finished Apr 16 03:06:08 PM PDT 24
Peak memory 219028 kb
Host smart-5a1319ee-cbb0-4483-9172-769514bdc45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842612846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2842612846
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/90.edn_genbits.278957130
Short name T311
Test name
Test status
Simulation time 96703176 ps
CPU time 1.3 seconds
Started Apr 16 03:06:08 PM PDT 24
Finished Apr 16 03:06:10 PM PDT 24
Peak memory 218900 kb
Host smart-051e9877-9af6-40ed-8fe2-2050dd686e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278957130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.278957130
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_disable.2016748569
Short name T118
Test name
Test status
Simulation time 33562306 ps
CPU time 0.86 seconds
Started Apr 16 03:05:34 PM PDT 24
Finished Apr 16 03:05:35 PM PDT 24
Peak memory 215624 kb
Host smart-e51e9588-1ffd-45c7-b30d-33500df838b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016748569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2016748569
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.415354174
Short name T176
Test name
Test status
Simulation time 37627433 ps
CPU time 0.84 seconds
Started Apr 16 03:02:26 PM PDT 24
Finished Apr 16 03:02:27 PM PDT 24
Peak memory 215012 kb
Host smart-318de720-a02c-42eb-9145-5fdfb04247ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415354174 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.415354174
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable.251872436
Short name T136
Test name
Test status
Simulation time 34770749 ps
CPU time 0.81 seconds
Started Apr 16 03:01:47 PM PDT 24
Finished Apr 16 03:01:48 PM PDT 24
Peak memory 215484 kb
Host smart-ae58bd34-bbd7-482d-a9bf-9d5650986f31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251872436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.251872436
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2898784565
Short name T90
Test name
Test status
Simulation time 136867708 ps
CPU time 1.09 seconds
Started Apr 16 03:03:18 PM PDT 24
Finished Apr 16 03:03:20 PM PDT 24
Peak memory 216136 kb
Host smart-52010633-ee05-4558-ba02-3cc2a63b87e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898784565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2898784565
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3541899069
Short name T71
Test name
Test status
Simulation time 48260896 ps
CPU time 1.1 seconds
Started Apr 16 03:04:03 PM PDT 24
Finished Apr 16 03:04:04 PM PDT 24
Peak memory 216216 kb
Host smart-03781dd2-0272-472b-97a1-0926e23246a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541899069 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3541899069
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_disable.516087253
Short name T141
Test name
Test status
Simulation time 13709701 ps
CPU time 0.95 seconds
Started Apr 16 03:05:02 PM PDT 24
Finished Apr 16 03:05:04 PM PDT 24
Peak memory 215620 kb
Host smart-145840b5-0a69-40e0-9115-3c1b62db3a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516087253 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.516087253
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1826271597
Short name T74
Test name
Test status
Simulation time 144141468 ps
CPU time 1.2 seconds
Started Apr 16 03:01:50 PM PDT 24
Finished Apr 16 03:01:53 PM PDT 24
Peak memory 216148 kb
Host smart-9d6b6bfc-0850-4706-8071-6ed98b2e0f53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826271597 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1826271597
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert_test.4243992442
Short name T156
Test name
Test status
Simulation time 14779442 ps
CPU time 0.89 seconds
Started Apr 16 03:02:18 PM PDT 24
Finished Apr 16 03:02:20 PM PDT 24
Peak memory 206348 kb
Host smart-23b8e8e0-cbd7-49dc-8924-bfe0766461e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243992442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4243992442
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_genbits.3369694153
Short name T28
Test name
Test status
Simulation time 97211273 ps
CPU time 1.34 seconds
Started Apr 16 03:04:45 PM PDT 24
Finished Apr 16 03:04:48 PM PDT 24
Peak memory 217664 kb
Host smart-9699e6a4-b273-4170-8372-11b2d16510c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369694153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3369694153
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.4262179948
Short name T238
Test name
Test status
Simulation time 30335199 ps
CPU time 0.97 seconds
Started Apr 16 03:01:14 PM PDT 24
Finished Apr 16 03:01:15 PM PDT 24
Peak memory 206664 kb
Host smart-cdd9178d-353a-422c-8dd3-021a372cc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262179948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4262179948
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3550785242
Short name T18
Test name
Test status
Simulation time 113780568438 ps
CPU time 644.88 seconds
Started Apr 16 03:05:28 PM PDT 24
Finished Apr 16 03:16:13 PM PDT 24
Peak memory 220456 kb
Host smart-f316cd4b-84ad-434f-be81-582e4d5b71be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550785242 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3550785242
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_err.3721536153
Short name T5
Test name
Test status
Simulation time 25153836 ps
CPU time 0.96 seconds
Started Apr 16 03:04:12 PM PDT 24
Finished Apr 16 03:04:14 PM PDT 24
Peak memory 218996 kb
Host smart-017a0d85-87ca-4379-9f12-83f0ea134aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721536153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3721536153
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/26.edn_alert.3367840881
Short name T120
Test name
Test status
Simulation time 23706851 ps
CPU time 1.21 seconds
Started Apr 16 03:03:42 PM PDT 24
Finished Apr 16 03:03:44 PM PDT 24
Peak memory 215292 kb
Host smart-7857cc97-a4d1-4548-9ab9-05cc58a7d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367840881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3367840881
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/38.edn_intr.1915064258
Short name T25
Test name
Test status
Simulation time 21796969 ps
CPU time 1.09 seconds
Started Apr 16 03:04:45 PM PDT 24
Finished Apr 16 03:04:48 PM PDT 24
Peak memory 215512 kb
Host smart-0dea3076-25a2-4ef7-8645-a4d585e7d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915064258 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1915064258
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/158.edn_genbits.3124143142
Short name T280
Test name
Test status
Simulation time 137735906 ps
CPU time 3.33 seconds
Started Apr 16 03:06:42 PM PDT 24
Finished Apr 16 03:06:47 PM PDT 24
Peak memory 218320 kb
Host smart-57417604-cc5b-4971-aa88-bbc35dcc1f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124143142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3124143142
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_genbits.2259433071
Short name T272
Test name
Test status
Simulation time 238887699 ps
CPU time 1.68 seconds
Started Apr 16 03:06:12 PM PDT 24
Finished Apr 16 03:06:15 PM PDT 24
Peak memory 216432 kb
Host smart-7cae1642-3544-40cd-a34e-292a4ac4b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259433071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2259433071
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.299548826
Short name T200
Test name
Test status
Simulation time 30723065 ps
CPU time 1.18 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 206084 kb
Host smart-91dc685b-8e99-487b-b0f3-92d2afeb1751
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299548826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.299548826
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/15.edn_err.2760773022
Short name T6
Test name
Test status
Simulation time 26875572 ps
CPU time 1.2 seconds
Started Apr 16 03:02:40 PM PDT 24
Finished Apr 16 03:02:42 PM PDT 24
Peak memory 216476 kb
Host smart-217d5210-0e28-450e-8e20-c46b70c199ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760773022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2760773022
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4016004992
Short name T968
Test name
Test status
Simulation time 95347657 ps
CPU time 1.65 seconds
Started Apr 16 02:38:30 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 206124 kb
Host smart-d46a2f59-f441-46a2-bcf8-632d033ba28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016004992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4016004992
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1399616274
Short name T105
Test name
Test status
Simulation time 47118174 ps
CPU time 1.1 seconds
Started Apr 16 03:00:34 PM PDT 24
Finished Apr 16 03:00:35 PM PDT 24
Peak memory 215368 kb
Host smart-75f8244d-50f3-4d8a-aa7a-1cd213a36751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399616274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1399616274
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_genbits.610727640
Short name T372
Test name
Test status
Simulation time 51370308 ps
CPU time 1.13 seconds
Started Apr 16 03:00:32 PM PDT 24
Finished Apr 16 03:00:34 PM PDT 24
Peak memory 216084 kb
Host smart-f1755b5c-cfb2-4dbb-905a-a4795d6fc941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610727640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.610727640
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_genbits.454255925
Short name T259
Test name
Test status
Simulation time 79351786 ps
CPU time 1.43 seconds
Started Apr 16 03:00:48 PM PDT 24
Finished Apr 16 03:00:50 PM PDT 24
Peak memory 217760 kb
Host smart-e7a9eda1-e94e-4ce1-9e1a-329ec41d52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454255925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.454255925
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.210449426
Short name T599
Test name
Test status
Simulation time 47635116 ps
CPU time 1.59 seconds
Started Apr 16 03:06:29 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 216060 kb
Host smart-41891dcd-7d05-419e-830b-baa935cc9b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210449426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.210449426
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3385371876
Short name T227
Test name
Test status
Simulation time 22434134 ps
CPU time 1.17 seconds
Started Apr 16 03:06:29 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 216344 kb
Host smart-47146f0a-b8c8-4103-a880-9994d26a5da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385371876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3385371876
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.371909096
Short name T269
Test name
Test status
Simulation time 31435689 ps
CPU time 1.37 seconds
Started Apr 16 03:02:17 PM PDT 24
Finished Apr 16 03:02:19 PM PDT 24
Peak memory 217540 kb
Host smart-bea5f2b0-3b74-4157-833b-d335673dd2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371909096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.371909096
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3479422725
Short name T276
Test name
Test status
Simulation time 46320910 ps
CPU time 1.69 seconds
Started Apr 16 03:06:32 PM PDT 24
Finished Apr 16 03:06:35 PM PDT 24
Peak memory 217644 kb
Host smart-e9bc6c70-23d5-48fe-b301-9dba612eda47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479422725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3479422725
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3915802013
Short name T735
Test name
Test status
Simulation time 42350414 ps
CPU time 1.06 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:41 PM PDT 24
Peak memory 216172 kb
Host smart-55fe2b86-e689-47bc-973a-7280dfa6543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915802013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3915802013
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1386415233
Short name T20
Test name
Test status
Simulation time 50745155 ps
CPU time 1.26 seconds
Started Apr 16 03:06:43 PM PDT 24
Finished Apr 16 03:06:45 PM PDT 24
Peak memory 218840 kb
Host smart-7d099716-aac4-4fe3-8771-ad3fceedd5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386415233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1386415233
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1688546716
Short name T247
Test name
Test status
Simulation time 51248407 ps
CPU time 1.22 seconds
Started Apr 16 03:03:39 PM PDT 24
Finished Apr 16 03:03:41 PM PDT 24
Peak memory 215272 kb
Host smart-cb663ff6-1efc-468c-ac0f-46df5242514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688546716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1688546716
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert.3524171981
Short name T8
Test name
Test status
Simulation time 92376428 ps
CPU time 1.13 seconds
Started Apr 16 03:03:58 PM PDT 24
Finished Apr 16 03:03:59 PM PDT 24
Peak memory 215276 kb
Host smart-3252b6d0-8c0f-458e-8799-43c99e129651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524171981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3524171981
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/3.edn_genbits.543837569
Short name T279
Test name
Test status
Simulation time 177820492 ps
CPU time 1.37 seconds
Started Apr 16 03:01:12 PM PDT 24
Finished Apr 16 03:01:14 PM PDT 24
Peak memory 217544 kb
Host smart-e21c6a0e-37b5-48a6-b552-4fbc3bd611a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543837569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.543837569
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1637812235
Short name T60
Test name
Test status
Simulation time 27614140 ps
CPU time 0.98 seconds
Started Apr 16 03:04:00 PM PDT 24
Finished Apr 16 03:04:02 PM PDT 24
Peak memory 215400 kb
Host smart-eb69f16d-6003-4474-bd4c-5aec521ef937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637812235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1637812235
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/14.edn_alert.2719725542
Short name T703
Test name
Test status
Simulation time 49477030 ps
CPU time 1.19 seconds
Started Apr 16 03:02:39 PM PDT 24
Finished Apr 16 03:02:41 PM PDT 24
Peak memory 215356 kb
Host smart-55c4dae1-acc2-41cb-b3c2-2f8123354c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719725542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2719725542
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1801663485
Short name T207
Test name
Test status
Simulation time 235496025 ps
CPU time 3.16 seconds
Started Apr 16 02:37:39 PM PDT 24
Finished Apr 16 02:37:43 PM PDT 24
Peak memory 206092 kb
Host smart-e33f9e6c-b0cf-44a6-8b3e-92703520f012
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801663485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1801663485
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1654187606
Short name T206
Test name
Test status
Simulation time 33045001 ps
CPU time 0.95 seconds
Started Apr 16 02:37:41 PM PDT 24
Finished Apr 16 02:37:43 PM PDT 24
Peak memory 206056 kb
Host smart-a5c09209-d051-49a9-91dc-6599251f666a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654187606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1654187606
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3650354070
Short name T927
Test name
Test status
Simulation time 39072751 ps
CPU time 1.61 seconds
Started Apr 16 02:38:11 PM PDT 24
Finished Apr 16 02:38:13 PM PDT 24
Peak memory 214372 kb
Host smart-75734c3e-342c-473b-9aad-ead5ec045e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650354070 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3650354070
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2570034583
Short name T931
Test name
Test status
Simulation time 14437753 ps
CPU time 0.87 seconds
Started Apr 16 02:38:12 PM PDT 24
Finished Apr 16 02:38:14 PM PDT 24
Peak memory 206028 kb
Host smart-9605fdb7-a5ae-488b-b0ad-4eec135892c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570034583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2570034583
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.192442753
Short name T958
Test name
Test status
Simulation time 14111670 ps
CPU time 0.87 seconds
Started Apr 16 02:38:12 PM PDT 24
Finished Apr 16 02:38:13 PM PDT 24
Peak memory 206008 kb
Host smart-d4070a5f-0901-4676-9466-815a0df0af6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192442753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.192442753
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2404654644
Short name T217
Test name
Test status
Simulation time 73027193 ps
CPU time 1.34 seconds
Started Apr 16 02:37:42 PM PDT 24
Finished Apr 16 02:37:44 PM PDT 24
Peak memory 206120 kb
Host smart-a9462e97-4261-44d3-b95d-96ee24c9120b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404654644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2404654644
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4276555718
Short name T946
Test name
Test status
Simulation time 462755145 ps
CPU time 2.28 seconds
Started Apr 16 02:37:41 PM PDT 24
Finished Apr 16 02:37:44 PM PDT 24
Peak memory 214368 kb
Host smart-34261586-74ec-4d87-b358-56bf9ddadb48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276555718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4276555718
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3626991170
Short name T932
Test name
Test status
Simulation time 62711454 ps
CPU time 1.48 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 206084 kb
Host smart-3ae711cb-0939-46ca-8f61-4b224e463ff7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626991170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3626991170
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1412115958
Short name T939
Test name
Test status
Simulation time 116508131 ps
CPU time 3.23 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:45 PM PDT 24
Peak memory 206064 kb
Host smart-4a2d33b4-7158-49b4-89b1-e48194645297
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412115958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1412115958
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1775306908
Short name T203
Test name
Test status
Simulation time 69957090 ps
CPU time 0.93 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 206044 kb
Host smart-1969c2fd-e772-4526-a403-f6959cb2371d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775306908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1775306908
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1079317122
Short name T896
Test name
Test status
Simulation time 492785054 ps
CPU time 1.43 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:17 PM PDT 24
Peak memory 216724 kb
Host smart-0d8d8d78-3f36-445b-8fae-ce95d610c34c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079317122 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1079317122
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.476313213
Short name T209
Test name
Test status
Simulation time 11994746 ps
CPU time 0.82 seconds
Started Apr 16 02:38:12 PM PDT 24
Finished Apr 16 02:38:13 PM PDT 24
Peak memory 206012 kb
Host smart-dd964a51-903b-4a3d-b22c-541f3659cdc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476313213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.476313213
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.502255755
Short name T855
Test name
Test status
Simulation time 14924749 ps
CPU time 0.85 seconds
Started Apr 16 02:37:38 PM PDT 24
Finished Apr 16 02:37:40 PM PDT 24
Peak memory 206012 kb
Host smart-dbf3a22b-80d2-4a99-a2f9-c0d13eb252c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502255755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.502255755
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4088505024
Short name T965
Test name
Test status
Simulation time 58932493 ps
CPU time 1.38 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 206132 kb
Host smart-10308319-2a61-4eb1-b6a4-2319ef29a5dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088505024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4088505024
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.108723981
Short name T966
Test name
Test status
Simulation time 129927810 ps
CPU time 2.55 seconds
Started Apr 16 02:37:39 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 214436 kb
Host smart-22523211-ab08-4584-94c8-acb6a2a9272c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108723981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.108723981
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1667923192
Short name T892
Test name
Test status
Simulation time 74346311 ps
CPU time 1.45 seconds
Started Apr 16 02:38:11 PM PDT 24
Finished Apr 16 02:38:13 PM PDT 24
Peak memory 206100 kb
Host smart-b19b23e8-d99d-492f-9134-b97337ee3bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667923192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1667923192
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2914323669
Short name T840
Test name
Test status
Simulation time 16423838 ps
CPU time 1.01 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206228 kb
Host smart-ef9c9239-3f69-4e8f-bb3f-abe15ea33900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914323669 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2914323669
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3568776711
Short name T925
Test name
Test status
Simulation time 120736726 ps
CPU time 0.89 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206056 kb
Host smart-e85d1943-e02c-4154-a32b-75428fdf7d15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568776711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3568776711
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3068727543
Short name T879
Test name
Test status
Simulation time 71192145 ps
CPU time 0.86 seconds
Started Apr 16 02:38:23 PM PDT 24
Finished Apr 16 02:38:28 PM PDT 24
Peak memory 205968 kb
Host smart-3e84b397-7474-407c-8ba9-a197f5e29d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068727543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3068727543
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4228121153
Short name T888
Test name
Test status
Simulation time 142516804 ps
CPU time 1.41 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:21 PM PDT 24
Peak memory 206088 kb
Host smart-e3676874-65f2-4711-a5bb-e49c6516c66a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228121153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4228121153
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3093112761
Short name T955
Test name
Test status
Simulation time 189240601 ps
CPU time 2.12 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:24 PM PDT 24
Peak memory 222608 kb
Host smart-dc47c129-e306-470b-8fdb-4fdf98e79461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093112761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3093112761
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3965967711
Short name T231
Test name
Test status
Simulation time 608218997 ps
CPU time 2.45 seconds
Started Apr 16 02:38:21 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 206144 kb
Host smart-a035d882-9dae-4ffd-aa1e-0a94da2414a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965967711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3965967711
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3148866103
Short name T952
Test name
Test status
Simulation time 51163537 ps
CPU time 1.54 seconds
Started Apr 16 02:38:28 PM PDT 24
Finished Apr 16 02:38:37 PM PDT 24
Peak memory 214376 kb
Host smart-b7253e06-dcba-4cfc-a393-bc2ddba416ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148866103 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3148866103
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1398930115
Short name T198
Test name
Test status
Simulation time 39871397 ps
CPU time 0.79 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:29 PM PDT 24
Peak memory 205980 kb
Host smart-7ea1a7bb-a681-421a-9099-4dfcf917f312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398930115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1398930115
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1875879928
Short name T852
Test name
Test status
Simulation time 37482009 ps
CPU time 0.82 seconds
Started Apr 16 02:38:26 PM PDT 24
Finished Apr 16 02:38:34 PM PDT 24
Peak memory 205888 kb
Host smart-a4921f64-cd90-4c99-b94d-ef4da24722b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875879928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1875879928
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3270846098
Short name T199
Test name
Test status
Simulation time 53533488 ps
CPU time 1.08 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:31 PM PDT 24
Peak memory 206160 kb
Host smart-51de5589-1acc-407a-bb96-6191f108101b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270846098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3270846098
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.202539056
Short name T873
Test name
Test status
Simulation time 160202408 ps
CPU time 2.01 seconds
Started Apr 16 02:38:28 PM PDT 24
Finished Apr 16 02:38:38 PM PDT 24
Peak memory 214420 kb
Host smart-76b055ec-1876-47aa-a9b9-47ebc2e2636a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202539056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.202539056
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3589731524
Short name T859
Test name
Test status
Simulation time 152310474 ps
CPU time 2.33 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:32 PM PDT 24
Peak memory 214328 kb
Host smart-e2f40a8b-362c-448a-b4b7-b2570a7fdd43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589731524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3589731524
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2470797386
Short name T866
Test name
Test status
Simulation time 28764174 ps
CPU time 1.42 seconds
Started Apr 16 02:38:26 PM PDT 24
Finished Apr 16 02:38:34 PM PDT 24
Peak memory 222568 kb
Host smart-bcc8d93a-f235-42b1-a709-c7ff7e7c771a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470797386 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2470797386
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1168814941
Short name T936
Test name
Test status
Simulation time 14502860 ps
CPU time 0.88 seconds
Started Apr 16 02:38:23 PM PDT 24
Finished Apr 16 02:38:26 PM PDT 24
Peak memory 206004 kb
Host smart-6572d9ce-3659-4757-a9e9-fbf2685079d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168814941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1168814941
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3542382191
Short name T935
Test name
Test status
Simulation time 15043510 ps
CPU time 0.88 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:30 PM PDT 24
Peak memory 205976 kb
Host smart-7eac809c-7872-4054-aba8-43e9f203f754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542382191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3542382191
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4067600564
Short name T871
Test name
Test status
Simulation time 33357317 ps
CPU time 1.08 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:30 PM PDT 24
Peak memory 206176 kb
Host smart-bd9882fa-a56c-46b7-b71c-6eb57803e695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067600564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4067600564
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2352498070
Short name T861
Test name
Test status
Simulation time 96409368 ps
CPU time 3.37 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 214356 kb
Host smart-89585ed2-2dec-4fdc-bf1d-608a25ac199a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352498070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2352498070
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.322247441
Short name T881
Test name
Test status
Simulation time 198961551 ps
CPU time 1.59 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:29 PM PDT 24
Peak memory 206140 kb
Host smart-567e6583-7d36-4656-9d8a-bd073cddb51d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322247441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.322247441
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3867224520
Short name T891
Test name
Test status
Simulation time 108079597 ps
CPU time 1.14 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:38 PM PDT 24
Peak memory 222572 kb
Host smart-04a8c676-339d-43ab-9b6d-5cb3aa10a205
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867224520 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3867224520
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1023642876
Short name T213
Test name
Test status
Simulation time 11908862 ps
CPU time 0.85 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:30 PM PDT 24
Peak memory 206112 kb
Host smart-7c20c26d-1d8b-44be-8b90-264a1c73efda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023642876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1023642876
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.580020377
Short name T872
Test name
Test status
Simulation time 98813204 ps
CPU time 0.81 seconds
Started Apr 16 02:38:28 PM PDT 24
Finished Apr 16 02:38:37 PM PDT 24
Peak memory 206012 kb
Host smart-db768ebd-5944-4992-aeab-d07d715298d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580020377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.580020377
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3749191594
Short name T950
Test name
Test status
Simulation time 37949250 ps
CPU time 1.1 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:29 PM PDT 24
Peak memory 206124 kb
Host smart-6856364b-d454-4017-84b0-3ba19249f345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749191594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3749191594
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1810183983
Short name T858
Test name
Test status
Simulation time 98891045 ps
CPU time 2.88 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:33 PM PDT 24
Peak memory 214688 kb
Host smart-c59d2ca3-59ce-40cd-8543-4b162ff27580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810183983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1810183983
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3504509827
Short name T224
Test name
Test status
Simulation time 41098212 ps
CPU time 1.5 seconds
Started Apr 16 02:38:26 PM PDT 24
Finished Apr 16 02:38:34 PM PDT 24
Peak memory 206084 kb
Host smart-6028850b-332f-40fe-b110-1348d0977ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504509827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3504509827
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.161184395
Short name T870
Test name
Test status
Simulation time 27339930 ps
CPU time 1.71 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:33 PM PDT 24
Peak memory 214412 kb
Host smart-0a3e31a3-918b-45b8-b138-62c63783bdb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161184395 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.161184395
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1852901045
Short name T211
Test name
Test status
Simulation time 14546794 ps
CPU time 0.94 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:31 PM PDT 24
Peak memory 206080 kb
Host smart-4dbec318-465c-419e-a401-36ff4601e5c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852901045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1852901045
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2962433906
Short name T853
Test name
Test status
Simulation time 125699974 ps
CPU time 0.85 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:30 PM PDT 24
Peak memory 206008 kb
Host smart-b860b2e9-6766-492b-b3c4-a0aec76e4cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962433906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2962433906
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2305548131
Short name T943
Test name
Test status
Simulation time 78869149 ps
CPU time 1.12 seconds
Started Apr 16 02:38:27 PM PDT 24
Finished Apr 16 02:38:36 PM PDT 24
Peak memory 206136 kb
Host smart-7191196e-fc68-464b-b7bc-a3357c1d0bb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305548131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2305548131
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2417335397
Short name T921
Test name
Test status
Simulation time 110509718 ps
CPU time 4.1 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:34 PM PDT 24
Peak memory 214464 kb
Host smart-dff60e29-5702-4d27-a794-1b6fcfa1e411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417335397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2417335397
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3346836121
Short name T893
Test name
Test status
Simulation time 341386520 ps
CPU time 2.37 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:34 PM PDT 24
Peak memory 206144 kb
Host smart-b80392e6-288b-46d0-8662-2546adb802e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346836121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3346836121
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1677831771
Short name T923
Test name
Test status
Simulation time 27685151 ps
CPU time 1.42 seconds
Started Apr 16 02:38:26 PM PDT 24
Finished Apr 16 02:38:33 PM PDT 24
Peak memory 218008 kb
Host smart-7c12ff06-cf27-4565-a815-0d7c78afa7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677831771 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1677831771
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.49280163
Short name T901
Test name
Test status
Simulation time 29642127 ps
CPU time 0.84 seconds
Started Apr 16 02:38:32 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 206024 kb
Host smart-4d4932b6-de10-447f-8883-0fd2315fc9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49280163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.49280163
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1029668860
Short name T929
Test name
Test status
Simulation time 47433201 ps
CPU time 0.79 seconds
Started Apr 16 02:38:28 PM PDT 24
Finished Apr 16 02:38:37 PM PDT 24
Peak memory 205884 kb
Host smart-2de70c71-b63b-497e-b7a7-d6aa66d365c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029668860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1029668860
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.687892019
Short name T216
Test name
Test status
Simulation time 21210066 ps
CPU time 1.19 seconds
Started Apr 16 02:38:26 PM PDT 24
Finished Apr 16 02:38:34 PM PDT 24
Peak memory 206160 kb
Host smart-5001130c-da90-4e6e-a864-99a6654467eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687892019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.687892019
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3295308012
Short name T954
Test name
Test status
Simulation time 128586556 ps
CPU time 2.43 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 214456 kb
Host smart-a4093f73-b2ef-4fc7-b87d-91f9bcc4b49f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295308012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3295308012
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.4114598502
Short name T967
Test name
Test status
Simulation time 269272490 ps
CPU time 1.56 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 206224 kb
Host smart-a753fb83-232f-4c07-a2f9-3f5657dd9fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114598502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.4114598502
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.618074451
Short name T864
Test name
Test status
Simulation time 36160504 ps
CPU time 1.61 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 214388 kb
Host smart-d12cff99-6b18-4f23-b3d8-c39376e09940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618074451 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.618074451
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.113113901
Short name T956
Test name
Test status
Simulation time 14926814 ps
CPU time 0.92 seconds
Started Apr 16 02:38:30 PM PDT 24
Finished Apr 16 02:38:38 PM PDT 24
Peak memory 206096 kb
Host smart-6b8b404e-17a6-4caf-8115-2fa79392fbbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113113901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.113113901
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1549690689
Short name T846
Test name
Test status
Simulation time 45684183 ps
CPU time 0.83 seconds
Started Apr 16 02:38:30 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 206028 kb
Host smart-f6f28160-ad05-411b-95bd-80bed26d79f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549690689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1549690689
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2364951669
Short name T910
Test name
Test status
Simulation time 33431576 ps
CPU time 1.37 seconds
Started Apr 16 02:38:30 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 206132 kb
Host smart-df08d0e0-1278-49c5-9fa8-a21a7c6b2284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364951669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2364951669
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3921941291
Short name T841
Test name
Test status
Simulation time 303314654 ps
CPU time 3.93 seconds
Started Apr 16 02:38:28 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 218016 kb
Host smart-42fd1e96-8821-4d55-8478-1548cc96762d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921941291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3921941291
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1775132588
Short name T926
Test name
Test status
Simulation time 201016824 ps
CPU time 1.69 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 206124 kb
Host smart-5904b2f1-9e3c-4735-a4fa-d56ce421a718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775132588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1775132588
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3654147886
Short name T863
Test name
Test status
Simulation time 29890172 ps
CPU time 1.96 seconds
Started Apr 16 02:38:27 PM PDT 24
Finished Apr 16 02:38:37 PM PDT 24
Peak memory 214408 kb
Host smart-5cd7fe9b-4e0d-4c9e-9211-fa2f32371d11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654147886 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3654147886
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.552286842
Short name T944
Test name
Test status
Simulation time 41691529 ps
CPU time 0.88 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:38 PM PDT 24
Peak memory 205984 kb
Host smart-489409b5-85ad-46fd-bccc-5f95150377fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552286842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.552286842
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3426000694
Short name T903
Test name
Test status
Simulation time 11459642 ps
CPU time 0.83 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 206004 kb
Host smart-2a8437f8-7bfe-497b-8492-6717c57023aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426000694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3426000694
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4050948964
Short name T948
Test name
Test status
Simulation time 37656764 ps
CPU time 1.13 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 206092 kb
Host smart-246f4a49-788d-4649-ae0f-3adb787a94c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050948964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4050948964
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.767023721
Short name T918
Test name
Test status
Simulation time 55280542 ps
CPU time 1.79 seconds
Started Apr 16 02:38:32 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 214496 kb
Host smart-d0298c00-390d-4641-8a57-5de1f83320b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767023721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.767023721
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3156743047
Short name T874
Test name
Test status
Simulation time 59038643 ps
CPU time 1.84 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 206132 kb
Host smart-560ceb3b-703d-4d3f-84d4-611520fecc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156743047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3156743047
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2647146981
Short name T842
Test name
Test status
Simulation time 74722095 ps
CPU time 1.45 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 214424 kb
Host smart-3a6a3f54-d759-4d5e-84b3-85b1f7e44642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647146981 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2647146981
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1481054793
Short name T212
Test name
Test status
Simulation time 27020838 ps
CPU time 0.9 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:38 PM PDT 24
Peak memory 206096 kb
Host smart-cce912ae-581e-4471-8852-842d9b429635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481054793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1481054793
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.314151311
Short name T951
Test name
Test status
Simulation time 11742831 ps
CPU time 0.92 seconds
Started Apr 16 02:38:30 PM PDT 24
Finished Apr 16 02:38:38 PM PDT 24
Peak memory 205972 kb
Host smart-63cc8bbc-5d60-4b4a-ae14-18b325ce2a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314151311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.314151311
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2282517454
Short name T205
Test name
Test status
Simulation time 33195124 ps
CPU time 1.39 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 206092 kb
Host smart-69e41933-78d3-4acb-9c15-a6023092eed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282517454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2282517454
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2606268874
Short name T839
Test name
Test status
Simulation time 112307105 ps
CPU time 4 seconds
Started Apr 16 02:38:27 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 214332 kb
Host smart-40bdd202-fbee-49db-89f4-f174ca09b864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606268874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2606268874
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.50259228
Short name T907
Test name
Test status
Simulation time 17710806 ps
CPU time 1.06 seconds
Started Apr 16 02:38:32 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 206228 kb
Host smart-7f809221-efe6-4970-96c0-27718643fca5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50259228 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.50259228
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.645092448
Short name T894
Test name
Test status
Simulation time 31478455 ps
CPU time 0.89 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 206048 kb
Host smart-7be24749-b1f1-4496-bd46-3023474abf85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645092448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.645092448
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.803994953
Short name T934
Test name
Test status
Simulation time 11464246 ps
CPU time 0.82 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 206000 kb
Host smart-daab0e64-01fa-447d-b165-439beb51868b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803994953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.803994953
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3237729119
Short name T883
Test name
Test status
Simulation time 36155607 ps
CPU time 1.1 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 206148 kb
Host smart-fe55535d-0524-4787-9385-675a8908a0a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237729119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3237729119
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3330212888
Short name T904
Test name
Test status
Simulation time 52069331 ps
CPU time 1.89 seconds
Started Apr 16 02:38:29 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 214364 kb
Host smart-7c0b305c-b385-4298-a18d-30d8c53b50a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330212888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3330212888
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4032484501
Short name T232
Test name
Test status
Simulation time 266977567 ps
CPU time 4.86 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:44 PM PDT 24
Peak memory 206108 kb
Host smart-bf744943-fac5-42fe-8bb6-85cfc1da9937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032484501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.4032484501
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.576284859
Short name T210
Test name
Test status
Simulation time 74953737 ps
CPU time 1.55 seconds
Started Apr 16 02:38:16 PM PDT 24
Finished Apr 16 02:38:19 PM PDT 24
Peak memory 206088 kb
Host smart-204b1976-2790-491e-a56f-db8d71550572
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576284859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.576284859
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2717418376
Short name T204
Test name
Test status
Simulation time 60757420 ps
CPU time 3.27 seconds
Started Apr 16 02:38:17 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 206120 kb
Host smart-9922de20-38e4-4c45-89e3-362c968d23d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717418376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2717418376
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3882330403
Short name T221
Test name
Test status
Simulation time 43274326 ps
CPU time 0.82 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:17 PM PDT 24
Peak memory 206056 kb
Host smart-d13fa23b-6c4e-40e3-b5c0-f5d947cc539f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882330403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3882330403
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1424483883
Short name T908
Test name
Test status
Simulation time 33430270 ps
CPU time 0.88 seconds
Started Apr 16 02:38:16 PM PDT 24
Finished Apr 16 02:38:18 PM PDT 24
Peak memory 206108 kb
Host smart-3ff35269-a2af-4cfb-a885-b01e44523d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424483883 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1424483883
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2292132453
Short name T886
Test name
Test status
Simulation time 33898400 ps
CPU time 0.8 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 205980 kb
Host smart-968eb468-5eef-4ddc-bb4a-bda925fd2225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292132453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2292132453
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3149393063
Short name T843
Test name
Test status
Simulation time 26649680 ps
CPU time 0.76 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:16 PM PDT 24
Peak memory 205904 kb
Host smart-36699612-d24b-4382-8f88-e26d3bf8df2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149393063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3149393063
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1080887936
Short name T875
Test name
Test status
Simulation time 77706714 ps
CPU time 1.01 seconds
Started Apr 16 02:38:17 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 206148 kb
Host smart-02a3cbfd-9c98-4316-8acf-e1682c32d3e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080887936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1080887936
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4222296369
Short name T916
Test name
Test status
Simulation time 49390049 ps
CPU time 1.92 seconds
Started Apr 16 02:38:17 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 214440 kb
Host smart-963d246c-9e9a-4b25-a8b6-19294bd8af6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222296369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4222296369
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.593039733
Short name T225
Test name
Test status
Simulation time 89495583 ps
CPU time 1.58 seconds
Started Apr 16 02:38:16 PM PDT 24
Finished Apr 16 02:38:18 PM PDT 24
Peak memory 206196 kb
Host smart-56a504ff-fa54-4a58-801a-ea51eb287602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593039733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.593039733
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3468247267
Short name T933
Test name
Test status
Simulation time 14726068 ps
CPU time 0.89 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 206028 kb
Host smart-0b76a46f-fdc7-437b-8e70-670b9565bc0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468247267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3468247267
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1287615478
Short name T911
Test name
Test status
Simulation time 15817224 ps
CPU time 0.88 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 205916 kb
Host smart-8b8f36aa-e9f0-4c2b-bde7-4152f7d4f68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287615478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1287615478
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1365287561
Short name T860
Test name
Test status
Simulation time 53076237 ps
CPU time 0.89 seconds
Started Apr 16 02:38:34 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 206000 kb
Host smart-18be3ceb-de60-4277-8441-d66ccaef2a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365287561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1365287561
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1896724145
Short name T919
Test name
Test status
Simulation time 13959669 ps
CPU time 0.87 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 205964 kb
Host smart-c81935bc-9bc0-4078-9c5d-9ec78cfe6a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896724145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1896724145
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.428117093
Short name T887
Test name
Test status
Simulation time 16564339 ps
CPU time 0.79 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 205992 kb
Host smart-0f1d4488-778b-4c56-a0a7-b0f513d089ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428117093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.428117093
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1722698310
Short name T838
Test name
Test status
Simulation time 52724128 ps
CPU time 0.88 seconds
Started Apr 16 02:38:34 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 205976 kb
Host smart-ffff7bc5-cd2b-4096-b8d1-9f5b190414a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722698310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1722698310
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3305857920
Short name T880
Test name
Test status
Simulation time 170999828 ps
CPU time 0.89 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 205948 kb
Host smart-f5ca0500-23bb-4876-a141-f786803c9e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305857920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3305857920
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.902139750
Short name T945
Test name
Test status
Simulation time 11354928 ps
CPU time 0.83 seconds
Started Apr 16 02:38:32 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 206004 kb
Host smart-63041c4b-43c1-4827-9c53-84754b463026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902139750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.902139750
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.324370533
Short name T915
Test name
Test status
Simulation time 43458457 ps
CPU time 0.84 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 205988 kb
Host smart-a5e5c321-fd26-4a9a-9435-38df5bef6d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324370533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.324370533
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2045939541
Short name T897
Test name
Test status
Simulation time 16715805 ps
CPU time 0.86 seconds
Started Apr 16 02:38:38 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 205916 kb
Host smart-d47d190b-a218-45f7-8664-2c4746150700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045939541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2045939541
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1422987681
Short name T900
Test name
Test status
Simulation time 37437781 ps
CPU time 1.54 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206124 kb
Host smart-45e277ba-aeaf-40a6-a23d-6bd93df4c091
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422987681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1422987681
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3941761747
Short name T957
Test name
Test status
Simulation time 177197953 ps
CPU time 4.85 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 206088 kb
Host smart-0b84f0b1-2459-43e5-bfbb-fa195d5e38a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941761747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3941761747
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3173493894
Short name T220
Test name
Test status
Simulation time 31908971 ps
CPU time 0.93 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 206084 kb
Host smart-52b99ece-27fc-493e-a431-1995fe552771
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173493894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3173493894
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1866241767
Short name T913
Test name
Test status
Simulation time 21002287 ps
CPU time 1.13 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 214368 kb
Host smart-89d1e4f4-b636-4921-96c7-6146ead4afdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866241767 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1866241767
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4197533513
Short name T202
Test name
Test status
Simulation time 28084115 ps
CPU time 0.87 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:17 PM PDT 24
Peak memory 206092 kb
Host smart-f87ad9db-8806-44e9-8eee-fda4d0d2ff56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197533513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4197533513
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2289960136
Short name T959
Test name
Test status
Simulation time 12621203 ps
CPU time 0.82 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 205972 kb
Host smart-3df5aabd-73d3-438b-8dd5-8acf9751a74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289960136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2289960136
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3641030351
Short name T962
Test name
Test status
Simulation time 21531114 ps
CPU time 1.16 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206020 kb
Host smart-c49b5901-f2eb-4880-9989-42013e31fc13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641030351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3641030351
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2805354442
Short name T868
Test name
Test status
Simulation time 557131110 ps
CPU time 3.05 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 214372 kb
Host smart-82e50693-541b-4a18-9859-d72beb93e13f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805354442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2805354442
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1895206881
Short name T230
Test name
Test status
Simulation time 80411814 ps
CPU time 2.4 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 206140 kb
Host smart-172fdd8f-ab01-4cd3-95fd-ed500f74da47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895206881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1895206881
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3361083338
Short name T856
Test name
Test status
Simulation time 24294235 ps
CPU time 0.87 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 205976 kb
Host smart-495d5826-9068-4d63-9ab6-5839ac33f0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361083338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3361083338
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3136714404
Short name T890
Test name
Test status
Simulation time 43422428 ps
CPU time 0.83 seconds
Started Apr 16 02:38:34 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 206000 kb
Host smart-f2b301ed-4f6a-45a9-878b-92d6e0d861f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136714404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3136714404
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1473238311
Short name T884
Test name
Test status
Simulation time 30539438 ps
CPU time 0.78 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 205896 kb
Host smart-2367565e-2836-45b4-a092-0beda2c9af31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473238311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1473238311
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.605202811
Short name T862
Test name
Test status
Simulation time 50183948 ps
CPU time 0.87 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 206040 kb
Host smart-3a3aeb5f-6ceb-406a-ad24-f59f56e7d5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605202811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.605202811
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1224296993
Short name T964
Test name
Test status
Simulation time 21665654 ps
CPU time 0.81 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 205852 kb
Host smart-e4053138-319a-4828-b67d-5344ca6a8672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224296993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1224296993
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.369198121
Short name T869
Test name
Test status
Simulation time 12493120 ps
CPU time 0.97 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 205972 kb
Host smart-379df414-a128-4ee7-b0fc-585483d1d9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369198121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.369198121
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.450922723
Short name T889
Test name
Test status
Simulation time 14695405 ps
CPU time 0.86 seconds
Started Apr 16 02:38:37 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 206032 kb
Host smart-39c20e38-96d0-4815-b540-49b2017d5d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450922723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.450922723
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.139635023
Short name T867
Test name
Test status
Simulation time 45301651 ps
CPU time 0.84 seconds
Started Apr 16 02:38:37 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 206032 kb
Host smart-8147fb1f-c682-497a-afde-ac92bf669a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139635023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.139635023
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.58705844
Short name T877
Test name
Test status
Simulation time 16553111 ps
CPU time 0.9 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 205984 kb
Host smart-ca7a24b2-f4b9-4334-9b0b-748f1241c8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58705844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.58705844
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.462322865
Short name T895
Test name
Test status
Simulation time 27684647 ps
CPU time 0.82 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 205992 kb
Host smart-337d1fab-7111-496e-bc1d-38d06f2d6a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462322865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.462322865
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.605063418
Short name T938
Test name
Test status
Simulation time 51871416 ps
CPU time 1.03 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:21 PM PDT 24
Peak memory 206088 kb
Host smart-fdba3226-edc5-487d-a776-9ac2bbd21db1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605063418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.605063418
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.471576129
Short name T214
Test name
Test status
Simulation time 905133734 ps
CPU time 3.54 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 206132 kb
Host smart-196d363e-e5f3-4067-8a74-e483c0fe3e40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471576129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.471576129
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3053693527
Short name T885
Test name
Test status
Simulation time 60089001 ps
CPU time 0.97 seconds
Started Apr 16 02:38:14 PM PDT 24
Finished Apr 16 02:38:15 PM PDT 24
Peak memory 206020 kb
Host smart-2ffd6d19-2753-415c-85e0-e59506bb73ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053693527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3053693527
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3001858558
Short name T899
Test name
Test status
Simulation time 41117919 ps
CPU time 1.52 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 214352 kb
Host smart-3ad17947-5223-4dd8-a2e0-4545529d4ab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001858558 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3001858558
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1956977051
Short name T882
Test name
Test status
Simulation time 49819718 ps
CPU time 0.77 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 205924 kb
Host smart-d52cfdfb-d9a9-49d1-bbfd-57b2690e0453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956977051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1956977051
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1586853509
Short name T218
Test name
Test status
Simulation time 22543022 ps
CPU time 1.12 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 206124 kb
Host smart-d7e34117-3919-4258-9852-9dc211616dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586853509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1586853509
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3929742354
Short name T937
Test name
Test status
Simulation time 299648384 ps
CPU time 1.56 seconds
Started Apr 16 02:38:16 PM PDT 24
Finished Apr 16 02:38:18 PM PDT 24
Peak memory 214400 kb
Host smart-3bb6bd50-7cb2-4784-baba-9b21ed96cd66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929742354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3929742354
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.591151178
Short name T229
Test name
Test status
Simulation time 313682964 ps
CPU time 2.24 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:18 PM PDT 24
Peak memory 206008 kb
Host smart-92effdee-276c-4519-97f1-2aa2b406014c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591151178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.591151178
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3485969323
Short name T878
Test name
Test status
Simulation time 26413091 ps
CPU time 0.89 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 205940 kb
Host smart-d43a3652-d5eb-4cb4-a9e4-5cde20ce4859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485969323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3485969323
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.627569143
Short name T924
Test name
Test status
Simulation time 12971853 ps
CPU time 0.88 seconds
Started Apr 16 02:38:34 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 205980 kb
Host smart-5f32b5c2-3aaf-4a9f-89a9-7f9a53553366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627569143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.627569143
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.412264341
Short name T847
Test name
Test status
Simulation time 31164763 ps
CPU time 0.93 seconds
Started Apr 16 02:38:35 PM PDT 24
Finished Apr 16 02:38:42 PM PDT 24
Peak memory 206004 kb
Host smart-8ff16822-ab5b-4d63-933b-414c7fe07bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412264341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.412264341
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1676523890
Short name T947
Test name
Test status
Simulation time 30821544 ps
CPU time 0.81 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 205940 kb
Host smart-87d6b1bd-1b8a-4130-aca4-7040e69be67a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676523890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1676523890
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.924276443
Short name T849
Test name
Test status
Simulation time 23266831 ps
CPU time 0.86 seconds
Started Apr 16 02:38:31 PM PDT 24
Finished Apr 16 02:38:40 PM PDT 24
Peak memory 206072 kb
Host smart-39360074-0974-4d5e-b7e7-81e7fa73c303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924276443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.924276443
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1163940163
Short name T850
Test name
Test status
Simulation time 14389549 ps
CPU time 0.9 seconds
Started Apr 16 02:38:36 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 206060 kb
Host smart-68996c1c-de0b-4259-a372-a3fc051ecab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163940163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1163940163
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1883116828
Short name T920
Test name
Test status
Simulation time 15941489 ps
CPU time 0.9 seconds
Started Apr 16 02:38:33 PM PDT 24
Finished Apr 16 02:38:41 PM PDT 24
Peak memory 205972 kb
Host smart-7c8a3d80-0559-4511-8552-758bb1588960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883116828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1883116828
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3675689084
Short name T961
Test name
Test status
Simulation time 26205685 ps
CPU time 0.86 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:30 PM PDT 24
Peak memory 206000 kb
Host smart-0a51e319-47e7-4e56-9d1e-f5f5d0f7cdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675689084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3675689084
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.764298837
Short name T844
Test name
Test status
Simulation time 13277204 ps
CPU time 0.9 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:32 PM PDT 24
Peak memory 206008 kb
Host smart-d5ab77e0-a3f4-4245-a382-23466d09bc1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764298837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.764298837
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4100057009
Short name T848
Test name
Test status
Simulation time 22474253 ps
CPU time 0.85 seconds
Started Apr 16 02:38:37 PM PDT 24
Finished Apr 16 02:38:43 PM PDT 24
Peak memory 206028 kb
Host smart-75bc04eb-b0de-4f41-8e98-2c21e8198189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100057009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4100057009
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.824677827
Short name T845
Test name
Test status
Simulation time 20785637 ps
CPU time 1.31 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:18 PM PDT 24
Peak memory 214436 kb
Host smart-79faa20d-3710-4fc0-b8fe-6347860e8c73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824677827 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.824677827
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.97677786
Short name T949
Test name
Test status
Simulation time 42714231 ps
CPU time 0.87 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 206028 kb
Host smart-9634ac4b-42c7-470a-8355-de7ee58e250d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97677786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.97677786
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.220438393
Short name T940
Test name
Test status
Simulation time 37154952 ps
CPU time 0.77 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 205828 kb
Host smart-38f067b9-bffc-4e19-aba4-d4b7477d21c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220438393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.220438393
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2450784757
Short name T922
Test name
Test status
Simulation time 33976784 ps
CPU time 1.06 seconds
Started Apr 16 02:38:15 PM PDT 24
Finished Apr 16 02:38:17 PM PDT 24
Peak memory 206128 kb
Host smart-62371383-9185-47f7-98db-0f2a176f456e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450784757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2450784757
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2592732509
Short name T857
Test name
Test status
Simulation time 68147440 ps
CPU time 1.52 seconds
Started Apr 16 02:38:17 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 214480 kb
Host smart-0c668ded-0968-404c-afd9-8fa60a2e6666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592732509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2592732509
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3695098949
Short name T233
Test name
Test status
Simulation time 110999739 ps
CPU time 2.74 seconds
Started Apr 16 02:38:14 PM PDT 24
Finished Apr 16 02:38:17 PM PDT 24
Peak memory 206224 kb
Host smart-8c71c49e-469a-4173-ba68-8430726d3cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695098949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3695098949
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2919626813
Short name T906
Test name
Test status
Simulation time 17686727 ps
CPU time 0.99 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 206124 kb
Host smart-4c614e4d-32c8-4746-95b8-da6ee692a1c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919626813 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2919626813
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.4266522782
Short name T208
Test name
Test status
Simulation time 25919495 ps
CPU time 0.85 seconds
Started Apr 16 02:38:22 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 206040 kb
Host smart-ba342049-5fd3-4eec-8740-d73625868cd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266522782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4266522782
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1470350268
Short name T912
Test name
Test status
Simulation time 44799944 ps
CPU time 0.81 seconds
Started Apr 16 02:38:27 PM PDT 24
Finished Apr 16 02:38:35 PM PDT 24
Peak memory 206012 kb
Host smart-152fb4f6-7143-452d-bd65-15b4b06bca01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470350268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1470350268
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3696878910
Short name T219
Test name
Test status
Simulation time 86681823 ps
CPU time 1.34 seconds
Started Apr 16 02:38:27 PM PDT 24
Finished Apr 16 02:38:36 PM PDT 24
Peak memory 206156 kb
Host smart-aa8ee64d-9779-42ec-906b-8f283f2cbba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696878910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3696878910
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1719574923
Short name T865
Test name
Test status
Simulation time 73436555 ps
CPU time 1.37 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:29 PM PDT 24
Peak memory 214380 kb
Host smart-6f727ce0-0584-4e99-b9e5-8760adadfce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719574923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1719574923
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.327803993
Short name T898
Test name
Test status
Simulation time 187164470 ps
CPU time 1.42 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 206176 kb
Host smart-473e2b1d-2695-4110-958d-a3d7941ea1df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327803993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.327803993
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.551708699
Short name T917
Test name
Test status
Simulation time 53119800 ps
CPU time 1.26 seconds
Started Apr 16 02:38:24 PM PDT 24
Finished Apr 16 02:38:29 PM PDT 24
Peak memory 214452 kb
Host smart-fee7152b-0f0e-4d9d-a7d3-1b71ff9da35a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551708699 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.551708699
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1841560543
Short name T909
Test name
Test status
Simulation time 15257411 ps
CPU time 0.94 seconds
Started Apr 16 02:38:22 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 206044 kb
Host smart-dc8d9649-da73-4a68-86cf-882431e28540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841560543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1841560543
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3170049410
Short name T942
Test name
Test status
Simulation time 12633876 ps
CPU time 0.86 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 205980 kb
Host smart-63db8800-4aa2-4429-86e0-8d2f9d0c2f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170049410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3170049410
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.834232614
Short name T963
Test name
Test status
Simulation time 18922927 ps
CPU time 1.04 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206160 kb
Host smart-fc398d37-2d4c-4316-8d43-652c26aea251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834232614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.834232614
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.258382704
Short name T851
Test name
Test status
Simulation time 229737584 ps
CPU time 2.39 seconds
Started Apr 16 02:38:22 PM PDT 24
Finished Apr 16 02:38:26 PM PDT 24
Peak memory 214368 kb
Host smart-c2496718-4e27-4669-867e-c04842a3a9bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258382704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.258382704
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.509838890
Short name T905
Test name
Test status
Simulation time 148139169 ps
CPU time 2.13 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:24 PM PDT 24
Peak memory 206212 kb
Host smart-8ff9a3d5-7f03-4107-81b6-9339413fe4de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509838890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.509838890
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.415934699
Short name T941
Test name
Test status
Simulation time 68783942 ps
CPU time 1.17 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:32 PM PDT 24
Peak memory 214436 kb
Host smart-7335da30-81e6-4c0b-b49b-fd7f98cd65f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415934699 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.415934699
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2687615163
Short name T222
Test name
Test status
Simulation time 51636761 ps
CPU time 0.94 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:21 PM PDT 24
Peak memory 206052 kb
Host smart-c4f6066e-125a-4bbb-b2ff-df37237cf505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687615163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2687615163
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3588794936
Short name T930
Test name
Test status
Simulation time 14610545 ps
CPU time 0.83 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206028 kb
Host smart-39b8ee35-16c0-4050-88dc-0ea9cda3ead6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588794936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3588794936
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3267694238
Short name T928
Test name
Test status
Simulation time 15645379 ps
CPU time 0.99 seconds
Started Apr 16 02:38:18 PM PDT 24
Finished Apr 16 02:38:21 PM PDT 24
Peak memory 206120 kb
Host smart-fff8793a-491b-487b-a344-a1fbdec60e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267694238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3267694238
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3034776813
Short name T902
Test name
Test status
Simulation time 70003034 ps
CPU time 2.56 seconds
Started Apr 16 02:38:19 PM PDT 24
Finished Apr 16 02:38:24 PM PDT 24
Peak memory 214436 kb
Host smart-8bdfa2f3-86d6-4f7f-838c-c3acde869dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034776813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3034776813
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.508500217
Short name T234
Test name
Test status
Simulation time 137924302 ps
CPU time 3.15 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 206108 kb
Host smart-47cfff4b-5a09-4c1e-b804-2b5db669b3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508500217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.508500217
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1125080724
Short name T876
Test name
Test status
Simulation time 74301786 ps
CPU time 1.02 seconds
Started Apr 16 02:38:22 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 214396 kb
Host smart-caa146ab-9fd7-494b-a7ac-27801211fd47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125080724 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1125080724
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1554857690
Short name T953
Test name
Test status
Simulation time 16213721 ps
CPU time 0.93 seconds
Started Apr 16 02:38:25 PM PDT 24
Finished Apr 16 02:38:31 PM PDT 24
Peak memory 206024 kb
Host smart-69a2528c-9520-4f3e-993e-c173dc98dcee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554857690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1554857690
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3192927195
Short name T914
Test name
Test status
Simulation time 16298528 ps
CPU time 0.92 seconds
Started Apr 16 02:38:21 PM PDT 24
Finished Apr 16 02:38:24 PM PDT 24
Peak memory 206008 kb
Host smart-ec6e6517-5606-4e70-b697-1375754ace31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192927195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3192927195
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1775425868
Short name T215
Test name
Test status
Simulation time 106494989 ps
CPU time 1.45 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:24 PM PDT 24
Peak memory 206232 kb
Host smart-5eab9630-3f06-4b6e-927e-63a1013c1935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775425868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1775425868
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1881016028
Short name T854
Test name
Test status
Simulation time 68920796 ps
CPU time 2.52 seconds
Started Apr 16 02:38:21 PM PDT 24
Finished Apr 16 02:38:25 PM PDT 24
Peak memory 214424 kb
Host smart-a8a35683-754f-4f00-88d0-bfdf90c49abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881016028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1881016028
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.710574789
Short name T960
Test name
Test status
Simulation time 182691292 ps
CPU time 1.64 seconds
Started Apr 16 02:38:20 PM PDT 24
Finished Apr 16 02:38:23 PM PDT 24
Peak memory 206208 kb
Host smart-a9d052f8-aab9-4ba4-9ea9-bb609bdbfb02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710574789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.710574789
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.395938211
Short name T719
Test name
Test status
Simulation time 53403022 ps
CPU time 0.9 seconds
Started Apr 16 03:00:49 PM PDT 24
Finished Apr 16 03:00:50 PM PDT 24
Peak memory 206532 kb
Host smart-42834b5d-ff01-4036-9aa9-7769b359a95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395938211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.395938211
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3586781426
Short name T337
Test name
Test status
Simulation time 19187316 ps
CPU time 0.89 seconds
Started Apr 16 03:00:34 PM PDT 24
Finished Apr 16 03:00:36 PM PDT 24
Peak memory 215156 kb
Host smart-778ef793-c290-4d1a-90a3-e23d688a136e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586781426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3586781426
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3044678810
Short name T317
Test name
Test status
Simulation time 66296131 ps
CPU time 1.03 seconds
Started Apr 16 03:00:40 PM PDT 24
Finished Apr 16 03:00:42 PM PDT 24
Peak memory 216080 kb
Host smart-447143ac-6b1c-47e0-8e3d-3248827aa48a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044678810 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3044678810
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1020461867
Short name T143
Test name
Test status
Simulation time 76958378 ps
CPU time 1.34 seconds
Started Apr 16 03:00:31 PM PDT 24
Finished Apr 16 03:00:33 PM PDT 24
Peak memory 231908 kb
Host smart-694639d1-a82e-4fd7-aaf0-accda7154f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020461867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1020461867
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1574795012
Short name T643
Test name
Test status
Simulation time 23195676 ps
CPU time 1.17 seconds
Started Apr 16 03:00:34 PM PDT 24
Finished Apr 16 03:00:35 PM PDT 24
Peak memory 223636 kb
Host smart-1a545835-34e6-460a-8827-ad8f18bcc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574795012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1574795012
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2475574357
Short name T603
Test name
Test status
Simulation time 25026385 ps
CPU time 0.85 seconds
Started Apr 16 03:00:33 PM PDT 24
Finished Apr 16 03:00:34 PM PDT 24
Peak memory 206568 kb
Host smart-8242914c-5d4b-4d7b-a72e-b66f32b94b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475574357 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2475574357
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.239820087
Short name T15
Test name
Test status
Simulation time 620275881 ps
CPU time 6.4 seconds
Started Apr 16 03:00:47 PM PDT 24
Finished Apr 16 03:00:54 PM PDT 24
Peak memory 236608 kb
Host smart-c64412df-4ba8-4fa9-96ae-fcd68f1709b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239820087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.239820087
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1259513682
Short name T580
Test name
Test status
Simulation time 42414668 ps
CPU time 0.85 seconds
Started Apr 16 03:00:29 PM PDT 24
Finished Apr 16 03:00:31 PM PDT 24
Peak memory 214896 kb
Host smart-13348582-f917-4a6e-ab0a-78137fc6d93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259513682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1259513682
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1216714463
Short name T780
Test name
Test status
Simulation time 1390244123 ps
CPU time 5.04 seconds
Started Apr 16 03:00:34 PM PDT 24
Finished Apr 16 03:00:40 PM PDT 24
Peak memory 214904 kb
Host smart-09751e33-e09a-4274-800b-dcfb3e35faa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216714463 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1216714463
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1063490542
Short name T424
Test name
Test status
Simulation time 35052906358 ps
CPU time 777.78 seconds
Started Apr 16 03:00:36 PM PDT 24
Finished Apr 16 03:13:34 PM PDT 24
Peak memory 218432 kb
Host smart-01106c12-ad07-48f5-ade9-7cff3411626b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063490542 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1063490542
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.3069495181
Short name T510
Test name
Test status
Simulation time 69935066 ps
CPU time 0.77 seconds
Started Apr 16 03:01:05 PM PDT 24
Finished Apr 16 03:01:06 PM PDT 24
Peak memory 205356 kb
Host smart-831a0b8e-9a26-4d74-8b73-e1aa67dbe8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069495181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3069495181
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3143171159
Short name T465
Test name
Test status
Simulation time 225803542 ps
CPU time 1.26 seconds
Started Apr 16 03:01:05 PM PDT 24
Finished Apr 16 03:01:07 PM PDT 24
Peak memory 215984 kb
Host smart-6b05ced7-ec20-4d12-8cd8-4bd4c9aeea2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143171159 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3143171159
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2004734116
Short name T94
Test name
Test status
Simulation time 30773624 ps
CPU time 1.34 seconds
Started Apr 16 03:00:58 PM PDT 24
Finished Apr 16 03:01:00 PM PDT 24
Peak memory 224020 kb
Host smart-84fd1371-6c63-41ea-8b02-0e15079c06f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004734116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2004734116
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.3081394916
Short name T714
Test name
Test status
Simulation time 23714369 ps
CPU time 1.01 seconds
Started Apr 16 03:00:57 PM PDT 24
Finished Apr 16 03:00:59 PM PDT 24
Peak memory 215148 kb
Host smart-fc64fc53-7a80-48e8-870e-44121f5f6bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081394916 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3081394916
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.769647427
Short name T240
Test name
Test status
Simulation time 17743136 ps
CPU time 0.94 seconds
Started Apr 16 03:00:48 PM PDT 24
Finished Apr 16 03:00:49 PM PDT 24
Peak memory 206704 kb
Host smart-68e05e61-2145-4662-b585-87854bae873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769647427 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.769647427
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.235544128
Short name T52
Test name
Test status
Simulation time 1565276554 ps
CPU time 8.76 seconds
Started Apr 16 03:01:07 PM PDT 24
Finished Apr 16 03:01:16 PM PDT 24
Peak memory 234372 kb
Host smart-2bbdde7d-c2b6-4a6d-9fab-3e71a89cedf5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235544128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.235544128
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.719354166
Short name T457
Test name
Test status
Simulation time 17197918 ps
CPU time 1.01 seconds
Started Apr 16 03:00:48 PM PDT 24
Finished Apr 16 03:00:49 PM PDT 24
Peak memory 214888 kb
Host smart-c019a875-1e83-49ac-ac12-2abc64f11563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719354166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.719354166
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2868112855
Short name T740
Test name
Test status
Simulation time 552943570 ps
CPU time 3.51 seconds
Started Apr 16 03:00:47 PM PDT 24
Finished Apr 16 03:00:51 PM PDT 24
Peak memory 214864 kb
Host smart-7a5fbec8-f9f4-48ca-a3d7-b2ba3fcff2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868112855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2868112855
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3412185889
Short name T663
Test name
Test status
Simulation time 68919560558 ps
CPU time 756.97 seconds
Started Apr 16 03:00:55 PM PDT 24
Finished Apr 16 03:13:32 PM PDT 24
Peak memory 218576 kb
Host smart-a75726f9-6a69-49ef-9de7-0a550b7bb143
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412185889 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3412185889
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1812094568
Short name T249
Test name
Test status
Simulation time 27536961 ps
CPU time 1.22 seconds
Started Apr 16 03:02:12 PM PDT 24
Finished Apr 16 03:02:14 PM PDT 24
Peak memory 215240 kb
Host smart-df9b6405-ddc0-4c4f-9c2b-cc6b0a838603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812094568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1812094568
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.1511066878
Short name T619
Test name
Test status
Simulation time 10797561 ps
CPU time 0.88 seconds
Started Apr 16 03:02:16 PM PDT 24
Finished Apr 16 03:02:17 PM PDT 24
Peak memory 215148 kb
Host smart-74d1194a-4046-497a-a8ed-8c48485fce47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511066878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1511066878
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1251427721
Short name T85
Test name
Test status
Simulation time 140421821 ps
CPU time 1.02 seconds
Started Apr 16 03:02:18 PM PDT 24
Finished Apr 16 03:02:19 PM PDT 24
Peak memory 215976 kb
Host smart-48aa20fc-904a-4488-ae72-279315a14e96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251427721 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1251427721
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2600749304
Short name T393
Test name
Test status
Simulation time 37425141 ps
CPU time 1.16 seconds
Started Apr 16 03:02:14 PM PDT 24
Finished Apr 16 03:02:16 PM PDT 24
Peak memory 217776 kb
Host smart-7f763240-fcc9-495a-ad5a-0a5f0e231246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600749304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2600749304
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3422086056
Short name T707
Test name
Test status
Simulation time 61442351 ps
CPU time 1.4 seconds
Started Apr 16 03:02:09 PM PDT 24
Finished Apr 16 03:02:11 PM PDT 24
Peak memory 217392 kb
Host smart-d77d3026-510f-4201-9849-dde915f457a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422086056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3422086056
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2158991258
Short name T348
Test name
Test status
Simulation time 24918392 ps
CPU time 1.22 seconds
Started Apr 16 03:02:12 PM PDT 24
Finished Apr 16 03:02:14 PM PDT 24
Peak memory 223640 kb
Host smart-82b0d420-4112-4bdd-83a8-0f7f76351599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158991258 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2158991258
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2492677367
Short name T720
Test name
Test status
Simulation time 150037593 ps
CPU time 0.95 seconds
Started Apr 16 03:02:12 PM PDT 24
Finished Apr 16 03:02:14 PM PDT 24
Peak memory 214852 kb
Host smart-b4d92ead-9cbf-42de-b667-2917181d6422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492677367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2492677367
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2326595452
Short name T335
Test name
Test status
Simulation time 131933180 ps
CPU time 1.42 seconds
Started Apr 16 03:02:12 PM PDT 24
Finished Apr 16 03:02:15 PM PDT 24
Peak memory 216392 kb
Host smart-20f2fe40-10c3-4533-99c0-bf9ef147188c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326595452 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2326595452
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2662464557
Short name T189
Test name
Test status
Simulation time 61258669836 ps
CPU time 376.15 seconds
Started Apr 16 03:02:09 PM PDT 24
Finished Apr 16 03:08:26 PM PDT 24
Peak memory 223300 kb
Host smart-d2a12f02-0e48-4a40-92dd-e080eb37fe79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662464557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2662464557
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.346569441
Short name T649
Test name
Test status
Simulation time 126888374 ps
CPU time 1.4 seconds
Started Apr 16 03:06:29 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 217680 kb
Host smart-86ef8180-1cf4-4bfd-9e06-c4fed559ed60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346569441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.346569441
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3256817288
Short name T639
Test name
Test status
Simulation time 103989155 ps
CPU time 1.6 seconds
Started Apr 16 03:06:29 PM PDT 24
Finished Apr 16 03:06:32 PM PDT 24
Peak memory 216288 kb
Host smart-38d4fbcf-b512-475a-a21e-6dc493515b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256817288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3256817288
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.736720511
Short name T250
Test name
Test status
Simulation time 105496400 ps
CPU time 2.31 seconds
Started Apr 16 03:06:24 PM PDT 24
Finished Apr 16 03:06:27 PM PDT 24
Peak memory 217652 kb
Host smart-6bcf6cfb-e92e-40ad-b21b-3e6dabfc35e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736720511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.736720511
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1164019664
Short name T567
Test name
Test status
Simulation time 30844524 ps
CPU time 1.22 seconds
Started Apr 16 03:06:23 PM PDT 24
Finished Apr 16 03:06:26 PM PDT 24
Peak memory 217204 kb
Host smart-7874acd9-514e-4a08-84dd-b81a0f41092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164019664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1164019664
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3156309550
Short name T171
Test name
Test status
Simulation time 129962603 ps
CPU time 1.34 seconds
Started Apr 16 03:06:22 PM PDT 24
Finished Apr 16 03:06:24 PM PDT 24
Peak memory 218208 kb
Host smart-fd70e806-f606-4689-822e-013d60ac1282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156309550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3156309550
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.4005711267
Short name T650
Test name
Test status
Simulation time 53364414 ps
CPU time 1.34 seconds
Started Apr 16 03:06:23 PM PDT 24
Finished Apr 16 03:06:25 PM PDT 24
Peak memory 219196 kb
Host smart-6da23f8c-b8ce-4004-9770-b59b50591de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005711267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4005711267
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1178485977
Short name T776
Test name
Test status
Simulation time 89017315 ps
CPU time 1.15 seconds
Started Apr 16 03:06:22 PM PDT 24
Finished Apr 16 03:06:24 PM PDT 24
Peak memory 216360 kb
Host smart-7fbd58ce-2fbb-4e72-ab9c-c94c2739a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178485977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1178485977
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2718543497
Short name T563
Test name
Test status
Simulation time 111205000 ps
CPU time 1.8 seconds
Started Apr 16 03:06:23 PM PDT 24
Finished Apr 16 03:06:25 PM PDT 24
Peak memory 219020 kb
Host smart-9cc3ea8a-3e56-494e-937d-3ac19f73344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718543497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2718543497
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1830092858
Short name T466
Test name
Test status
Simulation time 27195006 ps
CPU time 1.18 seconds
Started Apr 16 03:02:20 PM PDT 24
Finished Apr 16 03:02:22 PM PDT 24
Peak memory 215280 kb
Host smart-d41326c1-3850-4ed9-ab88-ebbc198911fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830092858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1830092858
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1165647367
Short name T598
Test name
Test status
Simulation time 33756317 ps
CPU time 0.79 seconds
Started Apr 16 03:02:18 PM PDT 24
Finished Apr 16 03:02:20 PM PDT 24
Peak memory 206176 kb
Host smart-339f67eb-1cc4-4ce6-a60c-cd49dd774672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165647367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1165647367
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.4027314395
Short name T674
Test name
Test status
Simulation time 33864972 ps
CPU time 1.33 seconds
Started Apr 16 03:02:19 PM PDT 24
Finished Apr 16 03:02:22 PM PDT 24
Peak memory 229276 kb
Host smart-190c132c-f287-4670-b66c-04ef6dcf0384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027314395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4027314395
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.155708576
Short name T316
Test name
Test status
Simulation time 24121151 ps
CPU time 1.12 seconds
Started Apr 16 03:02:21 PM PDT 24
Finished Apr 16 03:02:23 PM PDT 24
Peak memory 215204 kb
Host smart-d7d4bc48-8b5b-4e0d-a4d2-4c23fc5a8286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155708576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.155708576
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2259976926
Short name T472
Test name
Test status
Simulation time 68654561 ps
CPU time 0.98 seconds
Started Apr 16 03:02:13 PM PDT 24
Finished Apr 16 03:02:15 PM PDT 24
Peak memory 214840 kb
Host smart-ebbf23e7-6516-4136-853e-ce689304cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259976926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2259976926
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3944371243
Short name T497
Test name
Test status
Simulation time 82598086 ps
CPU time 1.43 seconds
Started Apr 16 03:02:17 PM PDT 24
Finished Apr 16 03:02:20 PM PDT 24
Peak memory 217624 kb
Host smart-03cf9c12-0e62-4e62-9073-ae4dc9f41dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944371243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3944371243
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3563002206
Short name T699
Test name
Test status
Simulation time 40486185732 ps
CPU time 657.23 seconds
Started Apr 16 03:02:21 PM PDT 24
Finished Apr 16 03:13:19 PM PDT 24
Peak memory 223288 kb
Host smart-f6c2984f-6448-4502-895b-c94d30397f29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563002206 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3563002206
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2690558563
Short name T633
Test name
Test status
Simulation time 83189719 ps
CPU time 1.03 seconds
Started Apr 16 03:06:23 PM PDT 24
Finished Apr 16 03:06:25 PM PDT 24
Peak memory 217300 kb
Host smart-3c75c31e-6803-4533-9675-e63d44f1d45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690558563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2690558563
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1406113623
Short name T577
Test name
Test status
Simulation time 76419510 ps
CPU time 1.76 seconds
Started Apr 16 03:06:25 PM PDT 24
Finished Apr 16 03:06:28 PM PDT 24
Peak memory 217468 kb
Host smart-52beb4e0-baf0-4601-8d72-220e976fe8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406113623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1406113623
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.252682593
Short name T251
Test name
Test status
Simulation time 82563354 ps
CPU time 1.4 seconds
Started Apr 16 03:06:23 PM PDT 24
Finished Apr 16 03:06:26 PM PDT 24
Peak memory 217928 kb
Host smart-a597d7de-274c-4fc1-a523-370139be37cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252682593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.252682593
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.737944357
Short name T679
Test name
Test status
Simulation time 104344816 ps
CPU time 1.59 seconds
Started Apr 16 03:06:22 PM PDT 24
Finished Apr 16 03:06:24 PM PDT 24
Peak memory 217928 kb
Host smart-fd840e53-646c-4871-b1dc-64ec03b11d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737944357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.737944357
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.936900572
Short name T788
Test name
Test status
Simulation time 28367535 ps
CPU time 1.26 seconds
Started Apr 16 03:06:28 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 216368 kb
Host smart-59e9bdb9-bdd4-4e37-a826-c7a110b45eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936900572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.936900572
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3500807298
Short name T446
Test name
Test status
Simulation time 59993568 ps
CPU time 1.1 seconds
Started Apr 16 03:06:25 PM PDT 24
Finished Apr 16 03:06:27 PM PDT 24
Peak memory 216252 kb
Host smart-662b222a-b8c0-4155-819e-804c348ade50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500807298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3500807298
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4219097003
Short name T641
Test name
Test status
Simulation time 97415633 ps
CPU time 1.21 seconds
Started Apr 16 03:06:32 PM PDT 24
Finished Apr 16 03:06:33 PM PDT 24
Peak memory 217440 kb
Host smart-3ca0afa5-6cdc-460d-a574-5387f0d6e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219097003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4219097003
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3422277446
Short name T492
Test name
Test status
Simulation time 151375153 ps
CPU time 1.27 seconds
Started Apr 16 03:06:26 PM PDT 24
Finished Apr 16 03:06:29 PM PDT 24
Peak memory 216604 kb
Host smart-09795731-074d-4b72-a4e9-eceed255d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422277446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3422277446
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.4097490216
Short name T694
Test name
Test status
Simulation time 70002806 ps
CPU time 1.43 seconds
Started Apr 16 03:06:27 PM PDT 24
Finished Apr 16 03:06:29 PM PDT 24
Peak memory 216728 kb
Host smart-bcd27379-3543-4722-8c64-0ba825d24577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097490216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4097490216
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2860367716
Short name T168
Test name
Test status
Simulation time 49401958 ps
CPU time 1.42 seconds
Started Apr 16 03:06:28 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 216428 kb
Host smart-1c7b56b3-f297-41ba-b0ba-254ff4e8ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860367716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2860367716
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2821716036
Short name T303
Test name
Test status
Simulation time 45292832 ps
CPU time 0.82 seconds
Started Apr 16 03:02:26 PM PDT 24
Finished Apr 16 03:02:27 PM PDT 24
Peak memory 206348 kb
Host smart-2ec1a1d1-616d-466b-bf29-40894ef88ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821716036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2821716036
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1934074594
Short name T617
Test name
Test status
Simulation time 64740172 ps
CPU time 1.19 seconds
Started Apr 16 03:02:29 PM PDT 24
Finished Apr 16 03:02:31 PM PDT 24
Peak memory 217460 kb
Host smart-0b362297-a2ae-48d2-be51-1e0f367b03e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934074594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1934074594
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.233768269
Short name T84
Test name
Test status
Simulation time 39899164 ps
CPU time 0.88 seconds
Started Apr 16 03:02:19 PM PDT 24
Finished Apr 16 03:02:21 PM PDT 24
Peak memory 218848 kb
Host smart-b300c1df-6053-4a43-b369-f1b22d96b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233768269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.233768269
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2001136593
Short name T562
Test name
Test status
Simulation time 26408536 ps
CPU time 1.26 seconds
Started Apr 16 03:02:21 PM PDT 24
Finished Apr 16 03:02:23 PM PDT 24
Peak memory 216276 kb
Host smart-5048569f-61f7-4dac-88a9-52cfe4902179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001136593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2001136593
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3219732126
Short name T486
Test name
Test status
Simulation time 27666374 ps
CPU time 1.01 seconds
Started Apr 16 03:02:22 PM PDT 24
Finished Apr 16 03:02:24 PM PDT 24
Peak memory 215392 kb
Host smart-fcc00318-39a0-41c8-bb54-971da7157689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219732126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3219732126
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2932649027
Short name T295
Test name
Test status
Simulation time 25559592 ps
CPU time 0.91 seconds
Started Apr 16 03:02:24 PM PDT 24
Finished Apr 16 03:02:25 PM PDT 24
Peak memory 214880 kb
Host smart-7c124b81-4a63-49f5-8448-e3b5906f9da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932649027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2932649027
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2685547669
Short name T629
Test name
Test status
Simulation time 879135769 ps
CPU time 4.09 seconds
Started Apr 16 03:02:22 PM PDT 24
Finished Apr 16 03:02:27 PM PDT 24
Peak memory 214920 kb
Host smart-a6e2964f-d57a-42ee-bc86-dce96c3250f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685547669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2685547669
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1590968176
Short name T731
Test name
Test status
Simulation time 167657647943 ps
CPU time 1030.41 seconds
Started Apr 16 03:02:22 PM PDT 24
Finished Apr 16 03:19:33 PM PDT 24
Peak memory 220312 kb
Host smart-25d4f0b4-45ea-4584-a401-0842ee5f6a62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590968176 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1590968176
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.518602671
Short name T319
Test name
Test status
Simulation time 286650809 ps
CPU time 3.33 seconds
Started Apr 16 03:06:28 PM PDT 24
Finished Apr 16 03:06:33 PM PDT 24
Peak memory 216648 kb
Host smart-5f0868cb-730d-47fa-814b-38c842df3fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518602671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.518602671
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1723900988
Short name T315
Test name
Test status
Simulation time 223724705 ps
CPU time 3.39 seconds
Started Apr 16 03:06:27 PM PDT 24
Finished Apr 16 03:06:32 PM PDT 24
Peak memory 216252 kb
Host smart-90727971-d1d5-43fd-b6b9-e7515313dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723900988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1723900988
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.438856734
Short name T282
Test name
Test status
Simulation time 58889362 ps
CPU time 1.66 seconds
Started Apr 16 03:06:28 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 218952 kb
Host smart-5ef7d99a-a597-40d2-b05b-993de049995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438856734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.438856734
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.785740472
Short name T367
Test name
Test status
Simulation time 35265965 ps
CPU time 1.36 seconds
Started Apr 16 03:06:27 PM PDT 24
Finished Apr 16 03:06:30 PM PDT 24
Peak memory 217264 kb
Host smart-9521b492-d26a-4828-816f-531c9d8da3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785740472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.785740472
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1719738187
Short name T520
Test name
Test status
Simulation time 101651625 ps
CPU time 1.5 seconds
Started Apr 16 03:06:29 PM PDT 24
Finished Apr 16 03:06:31 PM PDT 24
Peak memory 218152 kb
Host smart-fd5ccbb3-a9b3-4492-a039-be512ed26ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719738187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1719738187
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2631484498
Short name T355
Test name
Test status
Simulation time 147877236 ps
CPU time 3.15 seconds
Started Apr 16 03:06:27 PM PDT 24
Finished Apr 16 03:06:32 PM PDT 24
Peak memory 217416 kb
Host smart-206531a2-cccf-442b-bc56-bada646f769f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631484498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2631484498
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.219944453
Short name T734
Test name
Test status
Simulation time 50493197 ps
CPU time 1.07 seconds
Started Apr 16 03:06:32 PM PDT 24
Finished Apr 16 03:06:33 PM PDT 24
Peak memory 214860 kb
Host smart-7d7cd8f6-f9f0-47cb-9e96-5a5b83e499bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219944453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.219944453
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2615980014
Short name T705
Test name
Test status
Simulation time 118874917 ps
CPU time 1.65 seconds
Started Apr 16 03:06:27 PM PDT 24
Finished Apr 16 03:06:30 PM PDT 24
Peak memory 217888 kb
Host smart-fc6f18d8-6884-4342-a2fe-be1a5e2dae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615980014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2615980014
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2371790335
Short name T793
Test name
Test status
Simulation time 37706582 ps
CPU time 1.37 seconds
Started Apr 16 03:06:28 PM PDT 24
Finished Apr 16 03:06:30 PM PDT 24
Peak memory 216252 kb
Host smart-7d72ce19-1d6c-469e-ae7e-9a1064051b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371790335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2371790335
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.4201174316
Short name T572
Test name
Test status
Simulation time 130335285 ps
CPU time 2.29 seconds
Started Apr 16 03:06:33 PM PDT 24
Finished Apr 16 03:06:36 PM PDT 24
Peak memory 219128 kb
Host smart-af9b932b-c5f4-4936-83bf-de9215a6daec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201174316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4201174316
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2018673074
Short name T170
Test name
Test status
Simulation time 76843530 ps
CPU time 1.09 seconds
Started Apr 16 03:02:27 PM PDT 24
Finished Apr 16 03:02:29 PM PDT 24
Peak memory 215320 kb
Host smart-0db04491-7cf6-47dd-8da3-2e81e731a37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018673074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2018673074
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2969338744
Short name T784
Test name
Test status
Simulation time 16935394 ps
CPU time 0.88 seconds
Started Apr 16 03:02:32 PM PDT 24
Finished Apr 16 03:02:34 PM PDT 24
Peak memory 205736 kb
Host smart-c83ab2f2-1f34-4233-9c61-129a53cc7a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969338744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2969338744
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3048865430
Short name T817
Test name
Test status
Simulation time 39729951 ps
CPU time 0.92 seconds
Started Apr 16 03:02:28 PM PDT 24
Finished Apr 16 03:02:30 PM PDT 24
Peak memory 215196 kb
Host smart-a65826e7-dce3-4e86-89e8-f9eab49a8cf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048865430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3048865430
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1999104679
Short name T682
Test name
Test status
Simulation time 36676507 ps
CPU time 1.27 seconds
Started Apr 16 03:02:28 PM PDT 24
Finished Apr 16 03:02:30 PM PDT 24
Peak memory 216168 kb
Host smart-031a209f-ce11-41e7-af72-d1f0079bf941
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999104679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1999104679
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.879978045
Short name T78
Test name
Test status
Simulation time 23731120 ps
CPU time 1.13 seconds
Started Apr 16 03:02:26 PM PDT 24
Finished Apr 16 03:02:28 PM PDT 24
Peak memory 219752 kb
Host smart-e8c724ac-2212-431a-aedb-ac8dbbc84871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879978045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.879978045
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3223069942
Short name T810
Test name
Test status
Simulation time 100818446 ps
CPU time 1.46 seconds
Started Apr 16 03:02:27 PM PDT 24
Finished Apr 16 03:02:29 PM PDT 24
Peak memory 217876 kb
Host smart-9cd7433c-285d-493a-acf4-6d2393e2c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223069942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3223069942
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.4159854298
Short name T341
Test name
Test status
Simulation time 39068671 ps
CPU time 0.87 seconds
Started Apr 16 03:02:26 PM PDT 24
Finished Apr 16 03:02:28 PM PDT 24
Peak memory 214820 kb
Host smart-32cf99c9-b36e-4cd6-896b-17e87d119a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159854298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4159854298
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.198063243
Short name T691
Test name
Test status
Simulation time 119170588 ps
CPU time 1.63 seconds
Started Apr 16 03:02:27 PM PDT 24
Finished Apr 16 03:02:30 PM PDT 24
Peak memory 214788 kb
Host smart-b9f74635-a4a8-4ae7-a872-a1736bf50a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198063243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.198063243
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1336838119
Short name T190
Test name
Test status
Simulation time 37931353030 ps
CPU time 214.63 seconds
Started Apr 16 03:02:27 PM PDT 24
Finished Apr 16 03:06:03 PM PDT 24
Peak memory 218200 kb
Host smart-e8f67495-2049-4a2f-8ad1-0bb4cdc9dcfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336838119 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1336838119
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2865887581
Short name T573
Test name
Test status
Simulation time 71697215 ps
CPU time 2.45 seconds
Started Apr 16 03:06:33 PM PDT 24
Finished Apr 16 03:06:36 PM PDT 24
Peak memory 217616 kb
Host smart-29c2d5de-fc75-4c62-8479-4d187e4b16c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865887581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2865887581
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1994703640
Short name T443
Test name
Test status
Simulation time 87203778 ps
CPU time 1.13 seconds
Started Apr 16 03:06:33 PM PDT 24
Finished Apr 16 03:06:34 PM PDT 24
Peak memory 216360 kb
Host smart-606e8141-66e9-48be-9b65-5440e74477ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994703640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1994703640
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3489394405
Short name T652
Test name
Test status
Simulation time 75165603 ps
CPU time 2.76 seconds
Started Apr 16 03:06:35 PM PDT 24
Finished Apr 16 03:06:39 PM PDT 24
Peak memory 219148 kb
Host smart-081f10c6-9f60-4649-9296-a623d444825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489394405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3489394405
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3244068423
Short name T423
Test name
Test status
Simulation time 52678847 ps
CPU time 1.34 seconds
Started Apr 16 03:06:34 PM PDT 24
Finished Apr 16 03:06:36 PM PDT 24
Peak memory 217512 kb
Host smart-45ee44ce-eb6a-4013-9e0b-77864df855cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244068423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3244068423
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.385322684
Short name T252
Test name
Test status
Simulation time 82002505 ps
CPU time 1.1 seconds
Started Apr 16 03:06:34 PM PDT 24
Finished Apr 16 03:06:36 PM PDT 24
Peak memory 216304 kb
Host smart-463d29dc-042a-40d5-96c7-db9d68ec762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385322684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.385322684
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.339569551
Short name T733
Test name
Test status
Simulation time 280512243 ps
CPU time 1.2 seconds
Started Apr 16 03:06:38 PM PDT 24
Finished Apr 16 03:06:40 PM PDT 24
Peak memory 216504 kb
Host smart-8611a67c-60e2-4154-a1d5-a0876f64a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339569551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.339569551
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1122663553
Short name T379
Test name
Test status
Simulation time 67092174 ps
CPU time 1.12 seconds
Started Apr 16 03:06:38 PM PDT 24
Finished Apr 16 03:06:40 PM PDT 24
Peak memory 216240 kb
Host smart-1cf9fec7-f313-4177-a433-9a74d5914d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122663553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1122663553
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1359388753
Short name T600
Test name
Test status
Simulation time 30751646 ps
CPU time 1.17 seconds
Started Apr 16 03:06:38 PM PDT 24
Finished Apr 16 03:06:40 PM PDT 24
Peak memory 216028 kb
Host smart-a8096e54-7878-4c7f-9c7a-52022416c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359388753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1359388753
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.355174144
Short name T403
Test name
Test status
Simulation time 41521823 ps
CPU time 1.46 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 217320 kb
Host smart-453f1695-cf74-4aae-bd57-3d0d3939a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355174144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.355174144
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.839769390
Short name T431
Test name
Test status
Simulation time 66076931 ps
CPU time 0.82 seconds
Started Apr 16 03:02:40 PM PDT 24
Finished Apr 16 03:02:42 PM PDT 24
Peak memory 205552 kb
Host smart-a503cd13-bb10-4bef-afb5-60ff28706ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839769390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.839769390
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2291240761
Short name T421
Test name
Test status
Simulation time 40362790 ps
CPU time 0.81 seconds
Started Apr 16 03:02:43 PM PDT 24
Finished Apr 16 03:02:44 PM PDT 24
Peak memory 215268 kb
Host smart-bea7aefa-4536-4805-9a4a-634bc489091b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291240761 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2291240761
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.690659767
Short name T514
Test name
Test status
Simulation time 27469884 ps
CPU time 1.15 seconds
Started Apr 16 03:02:38 PM PDT 24
Finished Apr 16 03:02:40 PM PDT 24
Peak memory 215976 kb
Host smart-a49b1d27-b1e4-45ae-8dbb-c8ebc0b2e8bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690659767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.690659767
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2416165270
Short name T774
Test name
Test status
Simulation time 20025936 ps
CPU time 1.11 seconds
Started Apr 16 03:02:40 PM PDT 24
Finished Apr 16 03:02:42 PM PDT 24
Peak memory 230908 kb
Host smart-fdf44f8d-4d11-44c8-81c5-c60a636c9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416165270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2416165270
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.855089963
Short name T404
Test name
Test status
Simulation time 44585691 ps
CPU time 1.08 seconds
Started Apr 16 03:02:31 PM PDT 24
Finished Apr 16 03:02:33 PM PDT 24
Peak memory 214872 kb
Host smart-6d4a5517-98fd-4f97-9df0-ec538b999cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855089963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.855089963
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.401247287
Short name T321
Test name
Test status
Simulation time 37653073 ps
CPU time 0.95 seconds
Started Apr 16 03:02:43 PM PDT 24
Finished Apr 16 03:02:45 PM PDT 24
Peak memory 215128 kb
Host smart-87d5f8a3-59e9-491b-b33f-9807bbe6acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401247287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.401247287
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1935487891
Short name T585
Test name
Test status
Simulation time 30674202 ps
CPU time 0.89 seconds
Started Apr 16 03:02:34 PM PDT 24
Finished Apr 16 03:02:35 PM PDT 24
Peak memory 214764 kb
Host smart-9ecb0f11-cbee-492f-8b10-5dcd59adbc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935487891 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1935487891
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.4098273875
Short name T504
Test name
Test status
Simulation time 248481693 ps
CPU time 2.99 seconds
Started Apr 16 03:02:39 PM PDT 24
Finished Apr 16 03:02:43 PM PDT 24
Peak memory 216168 kb
Host smart-b458d769-76ee-4979-8971-50dba8b386a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098273875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.4098273875
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.706176769
Short name T766
Test name
Test status
Simulation time 55026480676 ps
CPU time 710.91 seconds
Started Apr 16 03:02:41 PM PDT 24
Finished Apr 16 03:14:33 PM PDT 24
Peak memory 218184 kb
Host smart-7b3e8d32-0dfb-430b-a784-bf92662dabde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706176769 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.706176769
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1192080379
Short name T751
Test name
Test status
Simulation time 70173371 ps
CPU time 1.12 seconds
Started Apr 16 03:06:40 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 216180 kb
Host smart-2fd5cabf-f92e-415f-b8f7-677eaf251d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192080379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1192080379
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1222277017
Short name T395
Test name
Test status
Simulation time 47624779 ps
CPU time 1.24 seconds
Started Apr 16 03:06:38 PM PDT 24
Finished Apr 16 03:06:40 PM PDT 24
Peak memory 217732 kb
Host smart-d7d5d23d-f9f9-460c-8758-0bf0038a9057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222277017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1222277017
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2265552476
Short name T300
Test name
Test status
Simulation time 35958420 ps
CPU time 1.33 seconds
Started Apr 16 03:06:40 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 217376 kb
Host smart-da7e1831-7135-4233-a531-e500e9419690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265552476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2265552476
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1631350120
Short name T2
Test name
Test status
Simulation time 69691416 ps
CPU time 1.47 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:41 PM PDT 24
Peak memory 217448 kb
Host smart-5f7e175b-db8a-41fd-9ea3-d0033d41abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631350120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1631350120
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3168702744
Short name T628
Test name
Test status
Simulation time 42457317 ps
CPU time 1.84 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 217532 kb
Host smart-010a17f5-4715-43e2-b483-0704761bdc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168702744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3168702744
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3940701673
Short name T364
Test name
Test status
Simulation time 79524858 ps
CPU time 1.23 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:41 PM PDT 24
Peak memory 217736 kb
Host smart-c20bd926-119d-4893-8dfa-6a81ca58a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940701673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3940701673
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2880439199
Short name T610
Test name
Test status
Simulation time 64928600 ps
CPU time 1.3 seconds
Started Apr 16 03:06:40 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 218876 kb
Host smart-dc0366b0-4200-4c81-b7e5-3c9350fd58dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880439199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2880439199
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1917824934
Short name T24
Test name
Test status
Simulation time 93665342 ps
CPU time 1.18 seconds
Started Apr 16 03:06:40 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 216212 kb
Host smart-27f63bf6-97c3-4d78-9d2d-4042f2672b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917824934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1917824934
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3009626515
Short name T517
Test name
Test status
Simulation time 171367134 ps
CPU time 1.3 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:41 PM PDT 24
Peak memory 216272 kb
Host smart-663b2526-5a1d-4bd9-bdcd-a45cd419f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009626515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3009626515
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3751826926
Short name T697
Test name
Test status
Simulation time 29408942 ps
CPU time 1.33 seconds
Started Apr 16 03:02:38 PM PDT 24
Finished Apr 16 03:02:40 PM PDT 24
Peak memory 215264 kb
Host smart-842f253c-8b3b-40e3-ac25-43a53614d1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751826926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3751826926
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4128384778
Short name T531
Test name
Test status
Simulation time 93022311 ps
CPU time 0.89 seconds
Started Apr 16 03:02:45 PM PDT 24
Finished Apr 16 03:02:46 PM PDT 24
Peak memory 205540 kb
Host smart-a58dfa2e-9453-4570-a752-72fba2ca9bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128384778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4128384778
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2335294862
Short name T534
Test name
Test status
Simulation time 42682071 ps
CPU time 0.87 seconds
Started Apr 16 03:02:40 PM PDT 24
Finished Apr 16 03:02:42 PM PDT 24
Peak memory 215140 kb
Host smart-3cc747df-3e2b-408a-b1f3-b0a6aab6fb93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335294862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2335294862
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.209154296
Short name T425
Test name
Test status
Simulation time 76743606 ps
CPU time 1.09 seconds
Started Apr 16 03:02:46 PM PDT 24
Finished Apr 16 03:02:48 PM PDT 24
Peak memory 217540 kb
Host smart-9494ebce-5dac-407f-8d3c-3d6a172b33c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209154296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.209154296
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_genbits.3707680322
Short name T469
Test name
Test status
Simulation time 64348655 ps
CPU time 1.06 seconds
Started Apr 16 03:02:40 PM PDT 24
Finished Apr 16 03:02:42 PM PDT 24
Peak memory 216160 kb
Host smart-171ce992-1527-47ad-a533-479696218f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707680322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3707680322
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3285905924
Short name T352
Test name
Test status
Simulation time 58168617 ps
CPU time 0.95 seconds
Started Apr 16 03:02:40 PM PDT 24
Finished Apr 16 03:02:42 PM PDT 24
Peak memory 223460 kb
Host smart-6b82a418-53a4-4e89-9acd-613680075014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285905924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3285905924
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.323189145
Short name T476
Test name
Test status
Simulation time 19911814 ps
CPU time 1.01 seconds
Started Apr 16 03:02:43 PM PDT 24
Finished Apr 16 03:02:45 PM PDT 24
Peak memory 214868 kb
Host smart-429aaf6a-063c-4cbf-b822-fcb26a4e14ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323189145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.323189145
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2784626741
Short name T197
Test name
Test status
Simulation time 238872592 ps
CPU time 1.44 seconds
Started Apr 16 03:02:38 PM PDT 24
Finished Apr 16 03:02:40 PM PDT 24
Peak memory 214820 kb
Host smart-9b82d659-1293-4ff6-ac8a-3c09694112b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784626741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2784626741
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3254744855
Short name T541
Test name
Test status
Simulation time 147712295033 ps
CPU time 1324.01 seconds
Started Apr 16 03:02:37 PM PDT 24
Finished Apr 16 03:24:41 PM PDT 24
Peak memory 224668 kb
Host smart-2da973d9-21c1-466e-8a31-15d298c39df7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254744855 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3254744855
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2280333128
Short name T799
Test name
Test status
Simulation time 36647108 ps
CPU time 1.37 seconds
Started Apr 16 03:06:37 PM PDT 24
Finished Apr 16 03:06:39 PM PDT 24
Peak memory 216348 kb
Host smart-e67d2d76-ae0b-4370-adfb-2faa951f80f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280333128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2280333128
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1972565970
Short name T500
Test name
Test status
Simulation time 66980621 ps
CPU time 1.24 seconds
Started Apr 16 03:06:38 PM PDT 24
Finished Apr 16 03:06:40 PM PDT 24
Peak memory 217296 kb
Host smart-83d761e2-06b1-4cd2-9c57-e517e799e7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972565970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1972565970
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.924774932
Short name T262
Test name
Test status
Simulation time 51219191 ps
CPU time 1.29 seconds
Started Apr 16 03:06:39 PM PDT 24
Finished Apr 16 03:06:42 PM PDT 24
Peak memory 216284 kb
Host smart-89fa7c35-0cca-46d0-93a4-29447278dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924774932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.924774932
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.4269196162
Short name T480
Test name
Test status
Simulation time 46024435 ps
CPU time 0.93 seconds
Started Apr 16 03:06:43 PM PDT 24
Finished Apr 16 03:06:45 PM PDT 24
Peak memory 216092 kb
Host smart-1c428320-abd8-4c71-b496-aa4089a85189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269196162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4269196162
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2092322520
Short name T474
Test name
Test status
Simulation time 121137261 ps
CPU time 1.01 seconds
Started Apr 16 03:06:43 PM PDT 24
Finished Apr 16 03:06:46 PM PDT 24
Peak memory 216324 kb
Host smart-2ffb3dd7-4f38-42c0-953e-10bdc74e2482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092322520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2092322520
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.503596542
Short name T816
Test name
Test status
Simulation time 77986476 ps
CPU time 1.23 seconds
Started Apr 16 03:06:48 PM PDT 24
Finished Apr 16 03:06:50 PM PDT 24
Peak memory 216076 kb
Host smart-c9d13a11-073b-4ddd-be47-1341b5ef428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503596542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.503596542
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.242384575
Short name T314
Test name
Test status
Simulation time 158667609 ps
CPU time 3.2 seconds
Started Apr 16 03:06:48 PM PDT 24
Finished Apr 16 03:06:52 PM PDT 24
Peak memory 216548 kb
Host smart-28378930-af45-4f7c-bcbd-e6e35300c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242384575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.242384575
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1643507564
Short name T414
Test name
Test status
Simulation time 34358934 ps
CPU time 1.37 seconds
Started Apr 16 03:06:41 PM PDT 24
Finished Apr 16 03:06:44 PM PDT 24
Peak memory 217372 kb
Host smart-00478454-90d7-4273-ab5e-cea7976ffee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643507564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1643507564
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3006132864
Short name T566
Test name
Test status
Simulation time 59615469 ps
CPU time 1.68 seconds
Started Apr 16 03:06:42 PM PDT 24
Finished Apr 16 03:06:45 PM PDT 24
Peak memory 217528 kb
Host smart-677bc21e-c93b-4c86-8cd0-2df8de9b8ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006132864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3006132864
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2360270513
Short name T155
Test name
Test status
Simulation time 30759325 ps
CPU time 1.25 seconds
Started Apr 16 03:02:50 PM PDT 24
Finished Apr 16 03:02:52 PM PDT 24
Peak memory 215236 kb
Host smart-e9a64697-4b0f-4077-8790-be33f75c743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360270513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2360270513
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.4234359537
Short name T437
Test name
Test status
Simulation time 14827730 ps
CPU time 0.86 seconds
Started Apr 16 03:02:50 PM PDT 24
Finished Apr 16 03:02:51 PM PDT 24
Peak memory 206592 kb
Host smart-43a92bec-2e8a-4dd3-861e-6c3e5ac23525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234359537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.4234359537
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3195858010
Short name T509
Test name
Test status
Simulation time 26936897 ps
CPU time 0.8 seconds
Started Apr 16 03:02:54 PM PDT 24
Finished Apr 16 03:02:56 PM PDT 24
Peak memory 215456 kb
Host smart-ee5c95dd-ac1e-4c93-857e-7f46f4feae9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195858010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3195858010
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2337084578
Short name T692
Test name
Test status
Simulation time 93690882 ps
CPU time 1.03 seconds
Started Apr 16 03:02:51 PM PDT 24
Finished Apr 16 03:02:52 PM PDT 24
Peak memory 217456 kb
Host smart-16ec6176-ef8b-4a07-8f62-658701a48814
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337084578 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2337084578
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3999929592
Short name T594
Test name
Test status
Simulation time 23164690 ps
CPU time 0.88 seconds
Started Apr 16 03:02:51 PM PDT 24
Finished Apr 16 03:02:52 PM PDT 24
Peak memory 217600 kb
Host smart-e50f408f-b85f-4fe0-a2e0-5e25954bd663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999929592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3999929592
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.47791387
Short name T388
Test name
Test status
Simulation time 336322698 ps
CPU time 4.26 seconds
Started Apr 16 03:02:44 PM PDT 24
Finished Apr 16 03:02:49 PM PDT 24
Peak memory 217508 kb
Host smart-6b580b6c-7e20-4305-99ea-ffe7f7a33bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47791387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.47791387
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3191862825
Short name T494
Test name
Test status
Simulation time 30875979 ps
CPU time 0.88 seconds
Started Apr 16 03:02:45 PM PDT 24
Finished Apr 16 03:02:47 PM PDT 24
Peak memory 215008 kb
Host smart-3c43e642-f251-4bfa-892a-e7f09e4634ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191862825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3191862825
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.535125889
Short name T804
Test name
Test status
Simulation time 48823551 ps
CPU time 0.94 seconds
Started Apr 16 03:02:46 PM PDT 24
Finished Apr 16 03:02:48 PM PDT 24
Peak memory 214824 kb
Host smart-fb517fa1-cf60-4ff0-9e79-feb310f2b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535125889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.535125889
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4025365709
Short name T194
Test name
Test status
Simulation time 2702407762 ps
CPU time 3.93 seconds
Started Apr 16 03:02:44 PM PDT 24
Finished Apr 16 03:02:49 PM PDT 24
Peak memory 216168 kb
Host smart-93a7f262-8219-4ed0-ba24-90806cba37bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025365709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4025365709
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3106022486
Short name T467
Test name
Test status
Simulation time 795637119860 ps
CPU time 1112.43 seconds
Started Apr 16 03:02:46 PM PDT 24
Finished Apr 16 03:21:20 PM PDT 24
Peak memory 223288 kb
Host smart-34a694f5-f8f6-42ae-81a7-a9b63030855d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106022486 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3106022486
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.4113912455
Short name T604
Test name
Test status
Simulation time 42606778 ps
CPU time 1.11 seconds
Started Apr 16 03:06:41 PM PDT 24
Finished Apr 16 03:06:43 PM PDT 24
Peak memory 217524 kb
Host smart-3efb0107-fc2c-4911-a7c0-30e2c1bc10c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113912455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4113912455
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3384374630
Short name T618
Test name
Test status
Simulation time 51731233 ps
CPU time 1.47 seconds
Started Apr 16 03:06:41 PM PDT 24
Finished Apr 16 03:06:44 PM PDT 24
Peak memory 217608 kb
Host smart-f8db1e3d-ca39-4cf8-97a1-2fdc3a0ae022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384374630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3384374630
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.205789717
Short name T655
Test name
Test status
Simulation time 28770583 ps
CPU time 1.26 seconds
Started Apr 16 03:06:43 PM PDT 24
Finished Apr 16 03:06:45 PM PDT 24
Peak memory 216312 kb
Host smart-d5faee9a-fd7c-48cb-be16-f04f4c29225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205789717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.205789717
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1844051794
Short name T309
Test name
Test status
Simulation time 32482424 ps
CPU time 1.27 seconds
Started Apr 16 03:06:41 PM PDT 24
Finished Apr 16 03:06:44 PM PDT 24
Peak memory 216200 kb
Host smart-224a06c9-f7dc-48d6-90e5-0b04c4aaaec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844051794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1844051794
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.6022066
Short name T38
Test name
Test status
Simulation time 40575098 ps
CPU time 1.63 seconds
Started Apr 16 03:06:41 PM PDT 24
Finished Apr 16 03:06:44 PM PDT 24
Peak memory 217452 kb
Host smart-00951b38-6d33-40bc-a1e2-4567c8f86071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6022066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.6022066
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.1610187952
Short name T456
Test name
Test status
Simulation time 51333252 ps
CPU time 1.59 seconds
Started Apr 16 03:06:48 PM PDT 24
Finished Apr 16 03:06:50 PM PDT 24
Peak memory 217428 kb
Host smart-ef7458e1-6814-4748-bfb9-b12252113736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610187952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1610187952
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2841524262
Short name T648
Test name
Test status
Simulation time 33319843 ps
CPU time 1.35 seconds
Started Apr 16 03:06:44 PM PDT 24
Finished Apr 16 03:06:46 PM PDT 24
Peak memory 217548 kb
Host smart-b6d2417d-65ef-4e17-81f1-7885cd9b288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841524262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2841524262
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1051471329
Short name T10
Test name
Test status
Simulation time 38363393 ps
CPU time 1.1 seconds
Started Apr 16 03:06:43 PM PDT 24
Finished Apr 16 03:06:46 PM PDT 24
Peak memory 218712 kb
Host smart-093dfb9e-97b1-48d3-9fb7-4f7e4e0e5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051471329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1051471329
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.514667556
Short name T764
Test name
Test status
Simulation time 116840624 ps
CPU time 1.05 seconds
Started Apr 16 03:06:42 PM PDT 24
Finished Apr 16 03:06:44 PM PDT 24
Peak memory 216368 kb
Host smart-9cb4a5f2-652a-4097-b16d-24fc1812e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514667556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.514667556
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1345487237
Short name T667
Test name
Test status
Simulation time 24958860 ps
CPU time 1.17 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:02:59 PM PDT 24
Peak memory 215276 kb
Host smart-e54f77d7-0554-43be-a31f-a9e973478829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345487237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1345487237
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3675496715
Short name T287
Test name
Test status
Simulation time 26818017 ps
CPU time 0.78 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:02:59 PM PDT 24
Peak memory 205332 kb
Host smart-af938766-eb64-41d7-a27e-88ec82524d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675496715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3675496715
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.796125949
Short name T623
Test name
Test status
Simulation time 150042223 ps
CPU time 0.88 seconds
Started Apr 16 03:02:56 PM PDT 24
Finished Apr 16 03:02:58 PM PDT 24
Peak memory 215008 kb
Host smart-ac53c9a6-fc04-4f4a-a478-66b6ea585f50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796125949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.796125949
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.2239372834
Short name T129
Test name
Test status
Simulation time 36826176 ps
CPU time 0.98 seconds
Started Apr 16 03:02:59 PM PDT 24
Finished Apr 16 03:03:01 PM PDT 24
Peak memory 217696 kb
Host smart-017cd45f-76bf-43a2-9bcb-440eb8a94bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239372834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2239372834
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3298213524
Short name T559
Test name
Test status
Simulation time 120306527 ps
CPU time 2.41 seconds
Started Apr 16 03:02:49 PM PDT 24
Finished Apr 16 03:02:52 PM PDT 24
Peak memory 217792 kb
Host smart-f580f37a-7f53-49a0-baef-ee60b9088520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298213524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3298213524
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3470114402
Short name T322
Test name
Test status
Simulation time 20466081 ps
CPU time 1.09 seconds
Started Apr 16 03:03:00 PM PDT 24
Finished Apr 16 03:03:01 PM PDT 24
Peak memory 215048 kb
Host smart-9b7e054f-cef9-4d5b-a2b1-cbbf29b03739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470114402 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3470114402
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.252353277
Short name T768
Test name
Test status
Simulation time 16667250 ps
CPU time 0.99 seconds
Started Apr 16 03:02:50 PM PDT 24
Finished Apr 16 03:02:51 PM PDT 24
Peak memory 214872 kb
Host smart-a27d1df4-4656-4fa3-be29-6d597abb745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252353277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.252353277
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3501385774
Short name T374
Test name
Test status
Simulation time 26039171 ps
CPU time 1.09 seconds
Started Apr 16 03:03:01 PM PDT 24
Finished Apr 16 03:03:03 PM PDT 24
Peak memory 205780 kb
Host smart-21cd093a-68d2-4a59-a434-b17329bdb2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501385774 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3501385774
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3294614915
Short name T579
Test name
Test status
Simulation time 45163925996 ps
CPU time 991.71 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:19:30 PM PDT 24
Peak memory 218112 kb
Host smart-07a98c91-327a-40a4-97cd-96299b0d3c6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294614915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3294614915
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1257801870
Short name T381
Test name
Test status
Simulation time 53121575 ps
CPU time 1.22 seconds
Started Apr 16 03:06:43 PM PDT 24
Finished Apr 16 03:06:46 PM PDT 24
Peak memory 218776 kb
Host smart-bb07cee3-cbbf-4725-be8a-99e23aa89ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257801870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1257801870
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3257626895
Short name T305
Test name
Test status
Simulation time 61552151 ps
CPU time 1.45 seconds
Started Apr 16 03:06:48 PM PDT 24
Finished Apr 16 03:06:50 PM PDT 24
Peak memory 217476 kb
Host smart-b3817321-0f13-45d1-bdd8-8529a670ded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257626895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3257626895
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.484468252
Short name T302
Test name
Test status
Simulation time 113079128 ps
CPU time 1 seconds
Started Apr 16 03:06:45 PM PDT 24
Finished Apr 16 03:06:47 PM PDT 24
Peak memory 214868 kb
Host smart-871eb7b9-e419-4462-a8bb-fcde65c244a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484468252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.484468252
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2161588576
Short name T349
Test name
Test status
Simulation time 113918698 ps
CPU time 1.22 seconds
Started Apr 16 03:06:47 PM PDT 24
Finished Apr 16 03:06:49 PM PDT 24
Peak memory 217588 kb
Host smart-28d088d4-a1d3-4efd-aa5d-70498a7f6a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161588576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2161588576
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1333232961
Short name T789
Test name
Test status
Simulation time 34589839 ps
CPU time 1.31 seconds
Started Apr 16 03:06:46 PM PDT 24
Finished Apr 16 03:06:48 PM PDT 24
Peak memory 217532 kb
Host smart-35949935-d830-4b3e-a2b8-3ee83b921230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333232961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1333232961
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.378871700
Short name T822
Test name
Test status
Simulation time 22698178 ps
CPU time 1.11 seconds
Started Apr 16 03:06:47 PM PDT 24
Finished Apr 16 03:06:49 PM PDT 24
Peak memory 216436 kb
Host smart-a36628a5-9d6f-4dff-a94c-463d8227163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378871700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.378871700
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.4260357078
Short name T834
Test name
Test status
Simulation time 99128963 ps
CPU time 1.01 seconds
Started Apr 16 03:06:47 PM PDT 24
Finished Apr 16 03:06:49 PM PDT 24
Peak memory 216152 kb
Host smart-5878bdc6-76cb-4fae-8a6e-61fff30de90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260357078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4260357078
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.801512404
Short name T417
Test name
Test status
Simulation time 206968710 ps
CPU time 2.22 seconds
Started Apr 16 03:06:47 PM PDT 24
Finished Apr 16 03:06:50 PM PDT 24
Peak memory 217516 kb
Host smart-1b649d13-1429-4ce5-b0a6-e9c43d33b87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801512404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.801512404
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1602971167
Short name T539
Test name
Test status
Simulation time 56873311 ps
CPU time 1.55 seconds
Started Apr 16 03:06:47 PM PDT 24
Finished Apr 16 03:06:50 PM PDT 24
Peak memory 217616 kb
Host smart-4780437b-afbd-4f3d-accb-58cc93ecaa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602971167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1602971167
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.4119113659
Short name T808
Test name
Test status
Simulation time 360657883 ps
CPU time 2.65 seconds
Started Apr 16 03:06:54 PM PDT 24
Finished Apr 16 03:06:57 PM PDT 24
Peak memory 217608 kb
Host smart-39c68dea-e586-4e7d-ae30-29243c672820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119113659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4119113659
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2206270175
Short name T39
Test name
Test status
Simulation time 32369177 ps
CPU time 1.14 seconds
Started Apr 16 03:02:59 PM PDT 24
Finished Apr 16 03:03:00 PM PDT 24
Peak memory 215256 kb
Host smart-32f23eb0-1bb4-4b6c-a860-c17b1de81cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206270175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2206270175
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2844044034
Short name T713
Test name
Test status
Simulation time 16478889 ps
CPU time 0.93 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:06 PM PDT 24
Peak memory 206612 kb
Host smart-a2bc5dba-834b-4d93-ba24-37816f1ca84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844044034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2844044034
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2471241324
Short name T760
Test name
Test status
Simulation time 61167318 ps
CPU time 0.78 seconds
Started Apr 16 03:02:56 PM PDT 24
Finished Apr 16 03:02:57 PM PDT 24
Peak memory 215456 kb
Host smart-e6fe8fca-2e2c-473b-b31a-af9ca8f976cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471241324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2471241324
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3484591749
Short name T522
Test name
Test status
Simulation time 116015909 ps
CPU time 1.17 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:03:00 PM PDT 24
Peak memory 218272 kb
Host smart-0b428604-f635-4e73-be23-6e5e8737000d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484591749 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3484591749
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3515276560
Short name T334
Test name
Test status
Simulation time 27665669 ps
CPU time 1.23 seconds
Started Apr 16 03:02:59 PM PDT 24
Finished Apr 16 03:03:01 PM PDT 24
Peak memory 219200 kb
Host smart-aed61d95-337d-40dd-b918-768d97cd2c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515276560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3515276560
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.1216289223
Short name T602
Test name
Test status
Simulation time 47689371 ps
CPU time 0.77 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:03:00 PM PDT 24
Peak memory 215252 kb
Host smart-e733b874-d660-484f-bd7e-449d30e9e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216289223 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1216289223
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.874072234
Short name T449
Test name
Test status
Simulation time 18639158 ps
CPU time 1.02 seconds
Started Apr 16 03:03:00 PM PDT 24
Finished Apr 16 03:03:01 PM PDT 24
Peak memory 214900 kb
Host smart-d0478cd0-ab59-4c1e-b8f2-c5db8a65e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874072234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.874072234
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2426890385
Short name T193
Test name
Test status
Simulation time 259839887 ps
CPU time 4.75 seconds
Started Apr 16 03:03:02 PM PDT 24
Finished Apr 16 03:03:07 PM PDT 24
Peak memory 214900 kb
Host smart-c0acbbe4-ad2f-47ed-b945-0b453504d714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426890385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2426890385
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1220315415
Short name T150
Test name
Test status
Simulation time 81546923778 ps
CPU time 1892.77 seconds
Started Apr 16 03:02:58 PM PDT 24
Finished Apr 16 03:34:32 PM PDT 24
Peak memory 225172 kb
Host smart-d5b094b3-382c-4def-88ee-bccda3863835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220315415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1220315415
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.615940322
Short name T429
Test name
Test status
Simulation time 52728165 ps
CPU time 1.37 seconds
Started Apr 16 03:06:53 PM PDT 24
Finished Apr 16 03:06:56 PM PDT 24
Peak memory 216436 kb
Host smart-0e9b3430-2769-4dc9-9910-afe3ccd60086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615940322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.615940322
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3281992994
Short name T237
Test name
Test status
Simulation time 48567097 ps
CPU time 1.35 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:58 PM PDT 24
Peak memory 217452 kb
Host smart-cab6494c-b513-40e3-982b-76783512f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281992994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3281992994
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1602060553
Short name T657
Test name
Test status
Simulation time 50005419 ps
CPU time 1.25 seconds
Started Apr 16 03:06:52 PM PDT 24
Finished Apr 16 03:06:55 PM PDT 24
Peak memory 216332 kb
Host smart-0abf1446-7c2c-401f-925d-8d84b9cbb3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602060553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1602060553
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3124752687
Short name T236
Test name
Test status
Simulation time 29861239 ps
CPU time 1.3 seconds
Started Apr 16 03:06:53 PM PDT 24
Finished Apr 16 03:06:56 PM PDT 24
Peak memory 217876 kb
Host smart-44dba562-b368-4b7b-a7ad-b5e083cb45a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124752687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3124752687
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2494049689
Short name T775
Test name
Test status
Simulation time 28338418 ps
CPU time 1.13 seconds
Started Apr 16 03:06:51 PM PDT 24
Finished Apr 16 03:06:53 PM PDT 24
Peak memory 218764 kb
Host smart-6093ac7d-441e-49ea-8152-f2d91f8349b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494049689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2494049689
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3644443882
Short name T284
Test name
Test status
Simulation time 38008831 ps
CPU time 1.35 seconds
Started Apr 16 03:06:55 PM PDT 24
Finished Apr 16 03:06:57 PM PDT 24
Peak memory 216404 kb
Host smart-05fd5c8f-c66a-4c36-b049-e5f5bbf3ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644443882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3644443882
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2699490050
Short name T383
Test name
Test status
Simulation time 151148243 ps
CPU time 3.42 seconds
Started Apr 16 03:06:53 PM PDT 24
Finished Apr 16 03:06:58 PM PDT 24
Peak memory 217456 kb
Host smart-552c65ef-4bf0-434c-8747-0c262757c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699490050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2699490050
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2899084215
Short name T270
Test name
Test status
Simulation time 55700284 ps
CPU time 1.7 seconds
Started Apr 16 03:06:54 PM PDT 24
Finished Apr 16 03:06:56 PM PDT 24
Peak memory 217524 kb
Host smart-58708195-3059-48ed-827e-28acbc512611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899084215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2899084215
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1682466169
Short name T271
Test name
Test status
Simulation time 34957524 ps
CPU time 1.5 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:58 PM PDT 24
Peak memory 217512 kb
Host smart-0ce4868d-3de5-4a7f-a323-fd031d68b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682466169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1682466169
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.781535248
Short name T258
Test name
Test status
Simulation time 88533629 ps
CPU time 1.51 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:59 PM PDT 24
Peak memory 217440 kb
Host smart-a1b607fd-9b06-4bc7-ab28-90d835b33bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781535248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.781535248
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.158532858
Short name T550
Test name
Test status
Simulation time 39766273 ps
CPU time 1.16 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:06 PM PDT 24
Peak memory 215280 kb
Host smart-a60b5d4c-4400-4f5d-8673-49fe1fe1f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158532858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.158532858
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.633884694
Short name T607
Test name
Test status
Simulation time 82681275 ps
CPU time 0.93 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:05 PM PDT 24
Peak memory 206540 kb
Host smart-86ea03dc-4c7e-4ff0-af1d-d631887101ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633884694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.633884694
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1022547420
Short name T297
Test name
Test status
Simulation time 107948140 ps
CPU time 0.78 seconds
Started Apr 16 03:03:02 PM PDT 24
Finished Apr 16 03:03:04 PM PDT 24
Peak memory 215192 kb
Host smart-5cc3cba8-9214-498d-a8cb-80d4b72144b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022547420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1022547420
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.233917063
Short name T398
Test name
Test status
Simulation time 78415681 ps
CPU time 0.82 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:06 PM PDT 24
Peak memory 217496 kb
Host smart-c58db2f8-0633-403a-8b25-b4d27c9dbb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233917063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.233917063
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.293804210
Short name T796
Test name
Test status
Simulation time 34684826 ps
CPU time 1.32 seconds
Started Apr 16 03:03:09 PM PDT 24
Finished Apr 16 03:03:10 PM PDT 24
Peak memory 217292 kb
Host smart-87bafe73-639f-4068-a6b7-70efb59aa502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293804210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.293804210
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3122438774
Short name T451
Test name
Test status
Simulation time 24727142 ps
CPU time 1.08 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:06 PM PDT 24
Peak memory 215056 kb
Host smart-6e34c8c3-873c-4c37-adbc-612002c3aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122438774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3122438774
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3837156100
Short name T422
Test name
Test status
Simulation time 47055230 ps
CPU time 0.93 seconds
Started Apr 16 03:03:03 PM PDT 24
Finished Apr 16 03:03:05 PM PDT 24
Peak memory 214896 kb
Host smart-2460d8bb-dcef-4c3f-a4c4-8838776b3929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837156100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3837156100
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2110972334
Short name T686
Test name
Test status
Simulation time 208852559 ps
CPU time 2.75 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:08 PM PDT 24
Peak memory 216496 kb
Host smart-e2a3a6a5-42ef-4ad2-8c86-2912734c3271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110972334 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2110972334
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.881664822
Short name T702
Test name
Test status
Simulation time 59475262256 ps
CPU time 1579.49 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:29:24 PM PDT 24
Peak memory 224288 kb
Host smart-dd389bf1-241c-432f-b69c-5b0f75f59110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881664822 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.881664822
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.4156278382
Short name T787
Test name
Test status
Simulation time 60760566 ps
CPU time 1.25 seconds
Started Apr 16 03:06:57 PM PDT 24
Finished Apr 16 03:06:59 PM PDT 24
Peak memory 216276 kb
Host smart-1f9cd67e-63f7-4561-8445-d91dafb884d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156278382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4156278382
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3037730327
Short name T616
Test name
Test status
Simulation time 37256296 ps
CPU time 1.43 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:59 PM PDT 24
Peak memory 216272 kb
Host smart-b4b9f579-32f0-43f5-9017-ed05a708108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037730327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3037730327
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2586846868
Short name T264
Test name
Test status
Simulation time 52825130 ps
CPU time 1.6 seconds
Started Apr 16 03:06:55 PM PDT 24
Finished Apr 16 03:06:58 PM PDT 24
Peak memory 217604 kb
Host smart-7a5435ef-74b6-4e35-b5f4-9d925b1ed204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586846868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2586846868
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3111298478
Short name T458
Test name
Test status
Simulation time 32587564 ps
CPU time 0.99 seconds
Started Apr 16 03:06:55 PM PDT 24
Finished Apr 16 03:06:57 PM PDT 24
Peak memory 216272 kb
Host smart-7c5d95d5-8815-49eb-8362-14cb62e1b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111298478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3111298478
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2671431366
Short name T670
Test name
Test status
Simulation time 186601358 ps
CPU time 1.07 seconds
Started Apr 16 03:06:59 PM PDT 24
Finished Apr 16 03:07:01 PM PDT 24
Peak memory 216332 kb
Host smart-408306cb-8097-4b3d-99cd-4b6098946899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671431366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2671431366
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2872001963
Short name T482
Test name
Test status
Simulation time 112783842 ps
CPU time 2.17 seconds
Started Apr 16 03:06:59 PM PDT 24
Finished Apr 16 03:07:02 PM PDT 24
Peak memory 217800 kb
Host smart-66dc4ccb-0a6c-4702-97ae-9bd22da92e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872001963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2872001963
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.261337349
Short name T377
Test name
Test status
Simulation time 29586154 ps
CPU time 1.3 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:58 PM PDT 24
Peak memory 217596 kb
Host smart-72207022-e33e-4b28-a781-eb398a3bbff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261337349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.261337349
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4149962415
Short name T491
Test name
Test status
Simulation time 51686434 ps
CPU time 1.06 seconds
Started Apr 16 03:06:59 PM PDT 24
Finished Apr 16 03:07:01 PM PDT 24
Peak memory 216548 kb
Host smart-672b85da-7983-45a5-94d5-e4ce11ba24d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149962415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4149962415
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.573353717
Short name T592
Test name
Test status
Simulation time 87353653 ps
CPU time 1.86 seconds
Started Apr 16 03:06:59 PM PDT 24
Finished Apr 16 03:07:02 PM PDT 24
Peak memory 217716 kb
Host smart-b64c5584-48cd-4188-bfab-b9082f60e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573353717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.573353717
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.854258311
Short name T380
Test name
Test status
Simulation time 32661334 ps
CPU time 1.44 seconds
Started Apr 16 03:06:57 PM PDT 24
Finished Apr 16 03:06:59 PM PDT 24
Peak memory 216616 kb
Host smart-ad80822c-9c89-40fb-bccb-e2b7148dc382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854258311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.854258311
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2278775553
Short name T167
Test name
Test status
Simulation time 83274583 ps
CPU time 1.17 seconds
Started Apr 16 03:01:06 PM PDT 24
Finished Apr 16 03:01:08 PM PDT 24
Peak memory 215264 kb
Host smart-812e2dfc-b553-43a5-896f-d49619680146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278775553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2278775553
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2899625254
Short name T293
Test name
Test status
Simulation time 18469902 ps
CPU time 0.93 seconds
Started Apr 16 03:01:12 PM PDT 24
Finished Apr 16 03:01:13 PM PDT 24
Peak memory 205768 kb
Host smart-d2ee0fbb-da1e-4f38-ae8b-fc04961e389c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899625254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2899625254
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2511929826
Short name T93
Test name
Test status
Simulation time 38304410 ps
CPU time 0.86 seconds
Started Apr 16 03:01:11 PM PDT 24
Finished Apr 16 03:01:13 PM PDT 24
Peak memory 214984 kb
Host smart-1a87f95f-66c6-4841-90a0-683a123e9d5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511929826 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2511929826
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3265592085
Short name T139
Test name
Test status
Simulation time 38600859 ps
CPU time 1.08 seconds
Started Apr 16 03:01:12 PM PDT 24
Finished Apr 16 03:01:13 PM PDT 24
Peak memory 215928 kb
Host smart-d864cec4-b00c-4ec9-9f15-dca1087fc3c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265592085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3265592085
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3726121352
Short name T140
Test name
Test status
Simulation time 36295156 ps
CPU time 1.09 seconds
Started Apr 16 03:01:08 PM PDT 24
Finished Apr 16 03:01:10 PM PDT 24
Peak memory 218932 kb
Host smart-c75b5236-f9e7-4a69-ba83-00f33ffe22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726121352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3726121352
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.174864800
Short name T676
Test name
Test status
Simulation time 218025425 ps
CPU time 1.16 seconds
Started Apr 16 03:01:06 PM PDT 24
Finished Apr 16 03:01:07 PM PDT 24
Peak memory 216068 kb
Host smart-bee55a9a-37e6-435d-99d5-6675860b28a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174864800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.174864800
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1738851140
Short name T124
Test name
Test status
Simulation time 33060606 ps
CPU time 0.87 seconds
Started Apr 16 03:01:07 PM PDT 24
Finished Apr 16 03:01:09 PM PDT 24
Peak memory 215220 kb
Host smart-70af76fe-2db2-48f7-a9f4-21b957caa391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738851140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1738851140
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2856860410
Short name T244
Test name
Test status
Simulation time 27414396 ps
CPU time 0.92 seconds
Started Apr 16 03:01:07 PM PDT 24
Finished Apr 16 03:01:08 PM PDT 24
Peak memory 206688 kb
Host smart-bf3e50b3-6690-472d-9c5e-5b30c2234300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856860410 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2856860410
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2900447320
Short name T51
Test name
Test status
Simulation time 367578809 ps
CPU time 5.51 seconds
Started Apr 16 03:01:12 PM PDT 24
Finished Apr 16 03:01:18 PM PDT 24
Peak memory 237012 kb
Host smart-06cea0cf-83a2-473a-86ce-25538190eeb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900447320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2900447320
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1834770498
Short name T460
Test name
Test status
Simulation time 27753605 ps
CPU time 0.94 seconds
Started Apr 16 03:01:06 PM PDT 24
Finished Apr 16 03:01:07 PM PDT 24
Peak memory 214864 kb
Host smart-dce328b1-4229-48da-acac-03ff919de64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834770498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1834770498
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.141575197
Short name T338
Test name
Test status
Simulation time 68344108 ps
CPU time 1.83 seconds
Started Apr 16 03:01:06 PM PDT 24
Finished Apr 16 03:01:08 PM PDT 24
Peak memory 217480 kb
Host smart-1cd0b195-10be-41cd-842c-91a92a7190af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141575197 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.141575197
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1595129289
Short name T147
Test name
Test status
Simulation time 401897843873 ps
CPU time 1953.84 seconds
Started Apr 16 03:01:07 PM PDT 24
Finished Apr 16 03:33:42 PM PDT 24
Peak memory 225508 kb
Host smart-00ca4819-73dc-4f03-8496-34160bd1e6f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595129289 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1595129289
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1399879402
Short name T164
Test name
Test status
Simulation time 86994535 ps
CPU time 1.27 seconds
Started Apr 16 03:03:08 PM PDT 24
Finished Apr 16 03:03:10 PM PDT 24
Peak memory 215264 kb
Host smart-3ce4ac58-89f7-46f9-b548-fe1603767b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399879402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1399879402
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1977429940
Short name T329
Test name
Test status
Simulation time 17274650 ps
CPU time 0.9 seconds
Started Apr 16 03:03:19 PM PDT 24
Finished Apr 16 03:03:20 PM PDT 24
Peak memory 205728 kb
Host smart-46955750-459c-4439-9515-25ef13819119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977429940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1977429940
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3809051568
Short name T370
Test name
Test status
Simulation time 35867069 ps
CPU time 0.79 seconds
Started Apr 16 03:03:19 PM PDT 24
Finished Apr 16 03:03:20 PM PDT 24
Peak memory 215200 kb
Host smart-7abddd0a-a18b-40c6-8111-360ef006131c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809051568 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3809051568
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2241524477
Short name T3
Test name
Test status
Simulation time 34179964 ps
CPU time 0.99 seconds
Started Apr 16 03:03:10 PM PDT 24
Finished Apr 16 03:03:12 PM PDT 24
Peak memory 229240 kb
Host smart-e30a6d1d-e346-4efc-b89c-d21e4dc4cc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241524477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2241524477
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3986942271
Short name T260
Test name
Test status
Simulation time 50564077 ps
CPU time 1.45 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:07 PM PDT 24
Peak memory 216392 kb
Host smart-39aa7524-878f-4467-9f8b-d32e79b5cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986942271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3986942271
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.403571440
Short name T47
Test name
Test status
Simulation time 21703454 ps
CPU time 1.17 seconds
Started Apr 16 03:03:11 PM PDT 24
Finished Apr 16 03:03:13 PM PDT 24
Peak memory 223648 kb
Host smart-07849972-9590-4db1-8c18-f71c31a85b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403571440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.403571440
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2902883793
Short name T362
Test name
Test status
Simulation time 57038854 ps
CPU time 0.89 seconds
Started Apr 16 03:03:04 PM PDT 24
Finished Apr 16 03:03:05 PM PDT 24
Peak memory 214736 kb
Host smart-7c6b3796-1444-4bf5-bb21-b86a4ff3f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902883793 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2902883793
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1619050704
Short name T145
Test name
Test status
Simulation time 238722078 ps
CPU time 4.6 seconds
Started Apr 16 03:03:07 PM PDT 24
Finished Apr 16 03:03:12 PM PDT 24
Peak memory 214908 kb
Host smart-3312da0f-b2fb-4cae-86a6-4bbb75b8f30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619050704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1619050704
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3888825353
Short name T184
Test name
Test status
Simulation time 354517338162 ps
CPU time 1957.35 seconds
Started Apr 16 03:03:10 PM PDT 24
Finished Apr 16 03:35:49 PM PDT 24
Peak memory 223868 kb
Host smart-4d73343e-d431-439e-94e8-1bca825a9994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888825353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3888825353
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.55736514
Short name T36
Test name
Test status
Simulation time 44118611 ps
CPU time 1.35 seconds
Started Apr 16 03:06:57 PM PDT 24
Finished Apr 16 03:07:00 PM PDT 24
Peak memory 218736 kb
Host smart-932ed101-2315-4dcc-a732-4439fb744159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55736514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.55736514
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1136616824
Short name T725
Test name
Test status
Simulation time 58064401 ps
CPU time 1.7 seconds
Started Apr 16 03:06:55 PM PDT 24
Finished Apr 16 03:06:57 PM PDT 24
Peak memory 217316 kb
Host smart-bc27b981-6adf-4312-ad1b-d55526720940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136616824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1136616824
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3907737310
Short name T828
Test name
Test status
Simulation time 49785679 ps
CPU time 1.16 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:59 PM PDT 24
Peak memory 216120 kb
Host smart-27b99f2c-ddfb-4c70-a028-6a7a829b1567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907737310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3907737310
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4193921497
Short name T253
Test name
Test status
Simulation time 38166457 ps
CPU time 1.34 seconds
Started Apr 16 03:06:56 PM PDT 24
Finished Apr 16 03:06:58 PM PDT 24
Peak memory 216284 kb
Host smart-6fa31d8e-ec4c-459c-a516-bbf86ce25589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193921497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4193921497
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3410076485
Short name T790
Test name
Test status
Simulation time 41014603 ps
CPU time 1.56 seconds
Started Apr 16 03:07:02 PM PDT 24
Finished Apr 16 03:07:04 PM PDT 24
Peak memory 217712 kb
Host smart-e1b1e54d-b3ca-43cb-a51a-540c492ca1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410076485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3410076485
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2728095308
Short name T331
Test name
Test status
Simulation time 42849851 ps
CPU time 1.18 seconds
Started Apr 16 03:07:02 PM PDT 24
Finished Apr 16 03:07:04 PM PDT 24
Peak memory 217352 kb
Host smart-55f2431c-f088-441c-9baf-4b510aa06077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728095308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2728095308
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3567142923
Short name T409
Test name
Test status
Simulation time 151504388 ps
CPU time 1.33 seconds
Started Apr 16 03:07:05 PM PDT 24
Finished Apr 16 03:07:07 PM PDT 24
Peak memory 217760 kb
Host smart-e3148871-13be-47ec-9d53-9063617cb8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567142923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3567142923
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2723024965
Short name T163
Test name
Test status
Simulation time 104300078 ps
CPU time 1.1 seconds
Started Apr 16 03:07:02 PM PDT 24
Finished Apr 16 03:07:04 PM PDT 24
Peak memory 216252 kb
Host smart-aeb99d17-727a-4032-8fad-cefec798bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723024965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2723024965
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3179255572
Short name T653
Test name
Test status
Simulation time 53749057 ps
CPU time 1.06 seconds
Started Apr 16 03:07:02 PM PDT 24
Finished Apr 16 03:07:04 PM PDT 24
Peak memory 216456 kb
Host smart-f0ccb2f8-1b7a-407e-9e32-c73e00b1fcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179255572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3179255572
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.365501426
Short name T357
Test name
Test status
Simulation time 50347291 ps
CPU time 1.2 seconds
Started Apr 16 03:07:01 PM PDT 24
Finished Apr 16 03:07:03 PM PDT 24
Peak memory 216012 kb
Host smart-f9c8e191-3f7d-4f12-8962-880e91ea61b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365501426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.365501426
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4109597629
Short name T245
Test name
Test status
Simulation time 44084594 ps
CPU time 1.2 seconds
Started Apr 16 03:03:17 PM PDT 24
Finished Apr 16 03:03:19 PM PDT 24
Peak memory 215324 kb
Host smart-123e9f8d-80e8-46d3-9aa9-051392089ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109597629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4109597629
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3883307408
Short name T687
Test name
Test status
Simulation time 74203060 ps
CPU time 0.93 seconds
Started Apr 16 03:03:16 PM PDT 24
Finished Apr 16 03:03:17 PM PDT 24
Peak memory 205736 kb
Host smart-60bd5803-f784-466c-bb6b-65c13c2d6f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883307408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3883307408
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1741292167
Short name T545
Test name
Test status
Simulation time 11869198 ps
CPU time 0.87 seconds
Started Apr 16 03:03:16 PM PDT 24
Finished Apr 16 03:03:17 PM PDT 24
Peak memory 215236 kb
Host smart-7b5e7b61-7aca-4c1f-8196-675411eb9ded
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741292167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1741292167
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.2840032954
Short name T737
Test name
Test status
Simulation time 25896297 ps
CPU time 0.84 seconds
Started Apr 16 03:03:17 PM PDT 24
Finished Apr 16 03:03:19 PM PDT 24
Peak memory 217504 kb
Host smart-6716a625-dd70-466d-9ee5-81dfc160241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840032954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2840032954
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3820137905
Short name T461
Test name
Test status
Simulation time 55921981 ps
CPU time 0.99 seconds
Started Apr 16 03:03:16 PM PDT 24
Finished Apr 16 03:03:18 PM PDT 24
Peak memory 217676 kb
Host smart-27b8da78-40ae-4ca5-a9e1-1521c8b02127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820137905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3820137905
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3527640738
Short name T730
Test name
Test status
Simulation time 25268229 ps
CPU time 1.01 seconds
Started Apr 16 03:03:17 PM PDT 24
Finished Apr 16 03:03:18 PM PDT 24
Peak memory 215072 kb
Host smart-e05bbe7d-cd9f-4f64-8a6a-ebfcec3f3cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527640738 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3527640738
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.304877190
Short name T665
Test name
Test status
Simulation time 17737939 ps
CPU time 1.01 seconds
Started Apr 16 03:03:15 PM PDT 24
Finished Apr 16 03:03:16 PM PDT 24
Peak memory 214904 kb
Host smart-c309d51f-d6e1-466d-b479-d98c357602a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304877190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.304877190
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2866140167
Short name T413
Test name
Test status
Simulation time 788422120 ps
CPU time 5.02 seconds
Started Apr 16 03:03:16 PM PDT 24
Finished Apr 16 03:03:22 PM PDT 24
Peak memory 216080 kb
Host smart-4d13d271-f1fe-45b7-851c-b3dba15d858e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866140167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2866140167
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.538056661
Short name T767
Test name
Test status
Simulation time 160948573100 ps
CPU time 475.49 seconds
Started Apr 16 03:03:15 PM PDT 24
Finished Apr 16 03:11:11 PM PDT 24
Peak memory 218584 kb
Host smart-2ed648ec-ac42-4eab-9735-79e264331f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538056661 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.538056661
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.97604613
Short name T179
Test name
Test status
Simulation time 759531673 ps
CPU time 6.77 seconds
Started Apr 16 03:07:00 PM PDT 24
Finished Apr 16 03:07:07 PM PDT 24
Peak memory 216420 kb
Host smart-9330402b-f963-4dec-b75f-21252aedd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97604613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.97604613
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1172409036
Short name T274
Test name
Test status
Simulation time 48494652 ps
CPU time 1.18 seconds
Started Apr 16 03:07:01 PM PDT 24
Finished Apr 16 03:07:03 PM PDT 24
Peak memory 217460 kb
Host smart-042a1beb-ba54-46cc-8c12-19be2ae21a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172409036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1172409036
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3201026155
Short name T273
Test name
Test status
Simulation time 50096295 ps
CPU time 1.35 seconds
Started Apr 16 03:07:01 PM PDT 24
Finished Apr 16 03:07:04 PM PDT 24
Peak memory 216356 kb
Host smart-72e9adc4-ddc0-4ddb-aa50-004e8a8e7060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201026155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3201026155
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1775823332
Short name T35
Test name
Test status
Simulation time 28727195 ps
CPU time 1.07 seconds
Started Apr 16 03:07:06 PM PDT 24
Finished Apr 16 03:07:08 PM PDT 24
Peak memory 216156 kb
Host smart-f220f126-1a52-4bad-aa10-6ad40e619e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775823332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1775823332
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.474220996
Short name T666
Test name
Test status
Simulation time 33271884 ps
CPU time 1.39 seconds
Started Apr 16 03:07:09 PM PDT 24
Finished Apr 16 03:07:11 PM PDT 24
Peak memory 217472 kb
Host smart-ea9e6ae1-0ade-4be5-8197-a30bba0ba5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474220996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.474220996
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2129360507
Short name T477
Test name
Test status
Simulation time 54420446 ps
CPU time 1.09 seconds
Started Apr 16 03:07:09 PM PDT 24
Finished Apr 16 03:07:11 PM PDT 24
Peak memory 216400 kb
Host smart-9a51aeeb-5885-410d-b404-5e91332fba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129360507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2129360507
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2702463140
Short name T605
Test name
Test status
Simulation time 89702822 ps
CPU time 1.45 seconds
Started Apr 16 03:07:09 PM PDT 24
Finished Apr 16 03:07:11 PM PDT 24
Peak memory 217740 kb
Host smart-c0a20799-9add-487a-8005-0baf7a89fdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702463140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2702463140
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.488248222
Short name T642
Test name
Test status
Simulation time 54404405 ps
CPU time 1.43 seconds
Started Apr 16 03:07:05 PM PDT 24
Finished Apr 16 03:07:08 PM PDT 24
Peak memory 217752 kb
Host smart-3b279e22-4962-490b-b192-0ee31ba8154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488248222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.488248222
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.556990703
Short name T721
Test name
Test status
Simulation time 63422389 ps
CPU time 1.24 seconds
Started Apr 16 03:07:09 PM PDT 24
Finished Apr 16 03:07:11 PM PDT 24
Peak memory 218484 kb
Host smart-9dfa5587-2e32-4814-840c-c801b5980d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556990703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.556990703
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2522954962
Short name T742
Test name
Test status
Simulation time 68297290 ps
CPU time 1.29 seconds
Started Apr 16 03:07:08 PM PDT 24
Finished Apr 16 03:07:11 PM PDT 24
Peak memory 217796 kb
Host smart-1363b5e4-9dbc-4d80-96f9-2041b6aec35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522954962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2522954962
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2272382481
Short name T710
Test name
Test status
Simulation time 24005548 ps
CPU time 1.15 seconds
Started Apr 16 03:03:26 PM PDT 24
Finished Apr 16 03:03:28 PM PDT 24
Peak memory 215248 kb
Host smart-2b058559-3021-4391-accf-a94c76dd5cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272382481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2272382481
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1086661577
Short name T358
Test name
Test status
Simulation time 14157220 ps
CPU time 0.89 seconds
Started Apr 16 03:03:22 PM PDT 24
Finished Apr 16 03:03:24 PM PDT 24
Peak memory 206400 kb
Host smart-36dd2b8b-d510-4216-a28f-1287437701a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086661577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1086661577
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1133818367
Short name T166
Test name
Test status
Simulation time 24520074 ps
CPU time 0.85 seconds
Started Apr 16 03:03:26 PM PDT 24
Finished Apr 16 03:03:28 PM PDT 24
Peak memory 215564 kb
Host smart-3896c5dc-df98-41a7-b208-26e1a13775c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133818367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1133818367
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.323529123
Short name T574
Test name
Test status
Simulation time 106818037 ps
CPU time 0.93 seconds
Started Apr 16 03:03:22 PM PDT 24
Finished Apr 16 03:03:24 PM PDT 24
Peak memory 216096 kb
Host smart-be3bc43a-83b8-40ad-b327-22e0b7e58960
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323529123 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.323529123
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.3176883546
Short name T455
Test name
Test status
Simulation time 77272141 ps
CPU time 1.12 seconds
Started Apr 16 03:03:26 PM PDT 24
Finished Apr 16 03:03:27 PM PDT 24
Peak memory 214952 kb
Host smart-9e3fe551-02ef-4a24-b1c5-653f77665cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176883546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3176883546
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.281100791
Short name T43
Test name
Test status
Simulation time 23096114 ps
CPU time 0.96 seconds
Started Apr 16 03:03:22 PM PDT 24
Finished Apr 16 03:03:24 PM PDT 24
Peak memory 215500 kb
Host smart-ba824f3e-df26-4bb5-930c-89aba61798d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281100791 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.281100791
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3708542132
Short name T389
Test name
Test status
Simulation time 18798861 ps
CPU time 1.02 seconds
Started Apr 16 03:03:15 PM PDT 24
Finished Apr 16 03:03:17 PM PDT 24
Peak memory 214880 kb
Host smart-bbf4be27-e09d-4852-94bb-480e5ec6f736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708542132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3708542132
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2725024481
Short name T708
Test name
Test status
Simulation time 218891497 ps
CPU time 2.69 seconds
Started Apr 16 03:03:22 PM PDT 24
Finished Apr 16 03:03:25 PM PDT 24
Peak memory 216312 kb
Host smart-62e8c5d0-af04-4b16-99a3-f55a34d4dfd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725024481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2725024481
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4001189446
Short name T191
Test name
Test status
Simulation time 326740030352 ps
CPU time 1938.25 seconds
Started Apr 16 03:03:24 PM PDT 24
Finished Apr 16 03:35:43 PM PDT 24
Peak memory 225148 kb
Host smart-f9f5da2a-2dff-4c3f-8e0f-5057171839bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001189446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4001189446
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3952036486
Short name T746
Test name
Test status
Simulation time 36150144 ps
CPU time 1.36 seconds
Started Apr 16 03:07:06 PM PDT 24
Finished Apr 16 03:07:09 PM PDT 24
Peak memory 217608 kb
Host smart-29069193-b031-4099-aeb4-53afcc7fd4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952036486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3952036486
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.784884387
Short name T292
Test name
Test status
Simulation time 60357073 ps
CPU time 1.39 seconds
Started Apr 16 03:07:10 PM PDT 24
Finished Apr 16 03:07:12 PM PDT 24
Peak memory 217688 kb
Host smart-9d430dd8-e9a2-4db4-8c5e-5c8a39f43460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784884387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.784884387
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.590740721
Short name T586
Test name
Test status
Simulation time 735500350 ps
CPU time 5.23 seconds
Started Apr 16 03:07:08 PM PDT 24
Finished Apr 16 03:07:14 PM PDT 24
Peak memory 216696 kb
Host smart-97b314e7-3af0-40f0-a2f8-4f0aa791a2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590740721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.590740721
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4221798472
Short name T392
Test name
Test status
Simulation time 77925756 ps
CPU time 1.03 seconds
Started Apr 16 03:07:10 PM PDT 24
Finished Apr 16 03:07:12 PM PDT 24
Peak memory 216164 kb
Host smart-8e30e152-2af8-485f-b1e2-09bb79aee503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221798472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4221798472
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4083671722
Short name T376
Test name
Test status
Simulation time 78474369 ps
CPU time 1.16 seconds
Started Apr 16 03:07:07 PM PDT 24
Finished Apr 16 03:07:09 PM PDT 24
Peak memory 216492 kb
Host smart-e59b9b3e-5d22-4136-9283-79f76c60d456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083671722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4083671722
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4122780203
Short name T538
Test name
Test status
Simulation time 33452993 ps
CPU time 1.31 seconds
Started Apr 16 03:07:05 PM PDT 24
Finished Apr 16 03:07:07 PM PDT 24
Peak memory 216696 kb
Host smart-9a22cd79-8b15-4321-911d-d6433647e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122780203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4122780203
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1927823087
Short name T420
Test name
Test status
Simulation time 40689204 ps
CPU time 1.03 seconds
Started Apr 16 03:07:08 PM PDT 24
Finished Apr 16 03:07:10 PM PDT 24
Peak memory 214924 kb
Host smart-5ef5a4de-7aad-4dc1-951b-b1ad6950dd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927823087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1927823087
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1457261633
Short name T261
Test name
Test status
Simulation time 44940660 ps
CPU time 1.43 seconds
Started Apr 16 03:07:08 PM PDT 24
Finished Apr 16 03:07:11 PM PDT 24
Peak memory 217252 kb
Host smart-b8933717-1ff4-4654-b8dd-1da077141bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457261633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1457261633
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1795251447
Short name T498
Test name
Test status
Simulation time 131330199 ps
CPU time 1.17 seconds
Started Apr 16 03:07:14 PM PDT 24
Finished Apr 16 03:07:16 PM PDT 24
Peak memory 216268 kb
Host smart-9048c483-2cd7-4d56-9b86-36b2112cc500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795251447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1795251447
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.211898042
Short name T241
Test name
Test status
Simulation time 43108541 ps
CPU time 1.19 seconds
Started Apr 16 03:03:28 PM PDT 24
Finished Apr 16 03:03:30 PM PDT 24
Peak memory 215276 kb
Host smart-86d9524b-8215-431c-8c74-78251f01b797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211898042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.211898042
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3668140681
Short name T683
Test name
Test status
Simulation time 22547867 ps
CPU time 0.84 seconds
Started Apr 16 03:03:26 PM PDT 24
Finished Apr 16 03:03:27 PM PDT 24
Peak memory 205544 kb
Host smart-9456b2d7-41eb-4995-9c67-db5107b9badc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668140681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3668140681
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.470258781
Short name T724
Test name
Test status
Simulation time 45989203 ps
CPU time 0.83 seconds
Started Apr 16 03:03:27 PM PDT 24
Finished Apr 16 03:03:29 PM PDT 24
Peak memory 215272 kb
Host smart-cb83ea8c-17be-4556-bdf7-a3497962f3c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470258781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.470258781
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.731743437
Short name T823
Test name
Test status
Simulation time 18543896 ps
CPU time 1.02 seconds
Started Apr 16 03:03:28 PM PDT 24
Finished Apr 16 03:03:30 PM PDT 24
Peak memory 217544 kb
Host smart-ce17ec96-7d56-499e-9ab5-1a23026b0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731743437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.731743437
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.861603691
Short name T27
Test name
Test status
Simulation time 33372010 ps
CPU time 1.38 seconds
Started Apr 16 03:03:23 PM PDT 24
Finished Apr 16 03:03:25 PM PDT 24
Peak memory 217468 kb
Host smart-941eeb74-3715-46dd-a33b-e317cf462303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861603691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.861603691
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3243192040
Short name T664
Test name
Test status
Simulation time 20894272 ps
CPU time 1.14 seconds
Started Apr 16 03:03:25 PM PDT 24
Finished Apr 16 03:03:27 PM PDT 24
Peak memory 223676 kb
Host smart-b0b80491-25d6-4c33-b2d8-75a7b29de285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243192040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3243192040
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1729897079
Short name T668
Test name
Test status
Simulation time 29210565 ps
CPU time 0.9 seconds
Started Apr 16 03:03:22 PM PDT 24
Finished Apr 16 03:03:23 PM PDT 24
Peak memory 214896 kb
Host smart-7d375e42-78af-41af-aa69-61a8370a2f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729897079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1729897079
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.6234369
Short name T547
Test name
Test status
Simulation time 396054106 ps
CPU time 7.17 seconds
Started Apr 16 03:03:22 PM PDT 24
Finished Apr 16 03:03:30 PM PDT 24
Peak memory 216412 kb
Host smart-a931a038-c2fb-4dc3-a66e-1c18f7baba9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6234369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.6234369
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2735411266
Short name T499
Test name
Test status
Simulation time 42146583054 ps
CPU time 286.18 seconds
Started Apr 16 03:03:23 PM PDT 24
Finished Apr 16 03:08:10 PM PDT 24
Peak memory 217260 kb
Host smart-4ffc27fe-bdc9-49f3-88cc-d0d45590bcbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735411266 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2735411266
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2596094523
Short name T419
Test name
Test status
Simulation time 159972179 ps
CPU time 1.37 seconds
Started Apr 16 03:07:14 PM PDT 24
Finished Apr 16 03:07:16 PM PDT 24
Peak memory 216224 kb
Host smart-2c82bd14-a30d-4d77-9973-0409cb4c1d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596094523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2596094523
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1826822639
Short name T281
Test name
Test status
Simulation time 70717499 ps
CPU time 1.36 seconds
Started Apr 16 03:07:12 PM PDT 24
Finished Apr 16 03:07:14 PM PDT 24
Peak memory 219080 kb
Host smart-4fd89ab1-e321-489b-b4e0-b8082055275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826822639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1826822639
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2158200109
Short name T275
Test name
Test status
Simulation time 65725417 ps
CPU time 1.21 seconds
Started Apr 16 03:07:13 PM PDT 24
Finished Apr 16 03:07:15 PM PDT 24
Peak memory 217728 kb
Host smart-2f1c5d3f-5c32-476b-bf12-3e685b3ccb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158200109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2158200109
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3947306200
Short name T488
Test name
Test status
Simulation time 111995585 ps
CPU time 1.7 seconds
Started Apr 16 03:07:15 PM PDT 24
Finished Apr 16 03:07:17 PM PDT 24
Peak memory 217856 kb
Host smart-8c5d93e8-310c-4c05-b425-82fe8bdb47f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947306200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3947306200
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3137036210
Short name T177
Test name
Test status
Simulation time 91858715 ps
CPU time 1.13 seconds
Started Apr 16 03:07:13 PM PDT 24
Finished Apr 16 03:07:15 PM PDT 24
Peak memory 216068 kb
Host smart-d6330bf2-dea8-4583-9817-f15ca1fac401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137036210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3137036210
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1680132667
Short name T475
Test name
Test status
Simulation time 129866901 ps
CPU time 1 seconds
Started Apr 16 03:07:14 PM PDT 24
Finished Apr 16 03:07:15 PM PDT 24
Peak memory 216228 kb
Host smart-c41d546d-e1fb-4906-bc29-1311642745ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680132667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1680132667
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4275630450
Short name T37
Test name
Test status
Simulation time 72667971 ps
CPU time 1.84 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:20 PM PDT 24
Peak memory 218924 kb
Host smart-34e763de-dc77-4c74-9be4-f50babba93a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275630450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4275630450
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2620205404
Short name T290
Test name
Test status
Simulation time 389710273 ps
CPU time 3.67 seconds
Started Apr 16 03:07:19 PM PDT 24
Finished Apr 16 03:07:23 PM PDT 24
Peak memory 217500 kb
Host smart-aa39a0b3-8e74-4c95-b40b-e13f84d09f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620205404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2620205404
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2669831335
Short name T637
Test name
Test status
Simulation time 90152787 ps
CPU time 1.32 seconds
Started Apr 16 03:07:14 PM PDT 24
Finished Apr 16 03:07:15 PM PDT 24
Peak memory 217644 kb
Host smart-d734c851-a0e9-4e98-a9cb-798b50a6ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669831335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2669831335
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3108398983
Short name T246
Test name
Test status
Simulation time 24854410 ps
CPU time 1.18 seconds
Started Apr 16 03:03:31 PM PDT 24
Finished Apr 16 03:03:33 PM PDT 24
Peak memory 215280 kb
Host smart-0782d97c-c9ff-46ee-8799-c07324bf725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108398983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3108398983
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3360252550
Short name T532
Test name
Test status
Simulation time 45441079 ps
CPU time 0.85 seconds
Started Apr 16 03:03:39 PM PDT 24
Finished Apr 16 03:03:41 PM PDT 24
Peak memory 206312 kb
Host smart-0639faf0-4093-4b13-915a-122c767583a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360252550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3360252550
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2715758214
Short name T750
Test name
Test status
Simulation time 23167591 ps
CPU time 0.84 seconds
Started Apr 16 03:03:31 PM PDT 24
Finished Apr 16 03:03:32 PM PDT 24
Peak memory 215476 kb
Host smart-cab522b0-c8c3-41fc-8dae-589618fe4ce6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715758214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2715758214
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1142642771
Short name T727
Test name
Test status
Simulation time 30611677 ps
CPU time 1 seconds
Started Apr 16 03:03:39 PM PDT 24
Finished Apr 16 03:03:41 PM PDT 24
Peak memory 216020 kb
Host smart-3a01dee2-7151-401c-a2f5-e16dc5211ceb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142642771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1142642771
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.315370860
Short name T636
Test name
Test status
Simulation time 24057140 ps
CPU time 1.05 seconds
Started Apr 16 03:03:30 PM PDT 24
Finished Apr 16 03:03:32 PM PDT 24
Peak memory 232128 kb
Host smart-5d87fe96-15a5-475a-b969-548223eb2d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315370860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.315370860
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.866077150
Short name T777
Test name
Test status
Simulation time 63247589 ps
CPU time 1.56 seconds
Started Apr 16 03:03:27 PM PDT 24
Finished Apr 16 03:03:30 PM PDT 24
Peak memory 217840 kb
Host smart-33187d29-96e5-48d6-9497-f33880cc711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866077150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.866077150
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3624732574
Short name T525
Test name
Test status
Simulation time 72812170 ps
CPU time 0.95 seconds
Started Apr 16 03:03:33 PM PDT 24
Finished Apr 16 03:03:34 PM PDT 24
Peak memory 223520 kb
Host smart-ab4ff1a5-fbf6-4e25-b5a3-d2f75699a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624732574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3624732574
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.140131815
Short name T478
Test name
Test status
Simulation time 24151644 ps
CPU time 0.88 seconds
Started Apr 16 03:03:26 PM PDT 24
Finished Apr 16 03:03:27 PM PDT 24
Peak memory 214852 kb
Host smart-fe487bcd-864c-40dd-95be-2e22e60cd98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140131815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.140131815
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3631252761
Short name T561
Test name
Test status
Simulation time 45441609 ps
CPU time 1.58 seconds
Started Apr 16 03:03:32 PM PDT 24
Finished Apr 16 03:03:34 PM PDT 24
Peak memory 214884 kb
Host smart-736c601e-af48-49ec-a898-4600162ddad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631252761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3631252761
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1443529044
Short name T709
Test name
Test status
Simulation time 52484080676 ps
CPU time 1203.21 seconds
Started Apr 16 03:03:31 PM PDT 24
Finished Apr 16 03:23:35 PM PDT 24
Peak memory 219216 kb
Host smart-665cd552-79be-456c-b16f-ae86d61b3512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443529044 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1443529044
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2494909011
Short name T557
Test name
Test status
Simulation time 49006065 ps
CPU time 1.71 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:20 PM PDT 24
Peak memory 217676 kb
Host smart-bf184785-d68f-4518-8e28-bdd67a4e8d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494909011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2494909011
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3327542913
Short name T640
Test name
Test status
Simulation time 127730079 ps
CPU time 1.32 seconds
Started Apr 16 03:07:21 PM PDT 24
Finished Apr 16 03:07:23 PM PDT 24
Peak memory 214848 kb
Host smart-aec3d76e-0b04-4b1c-9950-1939c3802232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327542913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3327542913
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1127692595
Short name T672
Test name
Test status
Simulation time 86749269 ps
CPU time 1.29 seconds
Started Apr 16 03:07:20 PM PDT 24
Finished Apr 16 03:07:22 PM PDT 24
Peak memory 218016 kb
Host smart-b643965b-f88e-42cc-8c83-23348f0ce2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127692595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1127692595
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.509400343
Short name T671
Test name
Test status
Simulation time 59463491 ps
CPU time 1.29 seconds
Started Apr 16 03:07:20 PM PDT 24
Finished Apr 16 03:07:22 PM PDT 24
Peak memory 217400 kb
Host smart-88f47493-a389-494e-98f8-3c83bb952820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509400343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.509400343
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.903178791
Short name T468
Test name
Test status
Simulation time 52473943 ps
CPU time 1.07 seconds
Started Apr 16 03:07:16 PM PDT 24
Finished Apr 16 03:07:18 PM PDT 24
Peak memory 218376 kb
Host smart-299cfce8-b98c-4f36-a967-590ebf5fe51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903178791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.903178791
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1182836782
Short name T807
Test name
Test status
Simulation time 55567598 ps
CPU time 1.38 seconds
Started Apr 16 03:07:16 PM PDT 24
Finished Apr 16 03:07:18 PM PDT 24
Peak memory 218028 kb
Host smart-7d30e300-ec3b-4329-99df-adf316d32d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182836782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1182836782
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3837745131
Short name T452
Test name
Test status
Simulation time 92698267 ps
CPU time 1.2 seconds
Started Apr 16 03:07:20 PM PDT 24
Finished Apr 16 03:07:22 PM PDT 24
Peak memory 216324 kb
Host smart-2d657930-cec5-4e85-b3b9-e7fdebbe9fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837745131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3837745131
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1446721502
Short name T688
Test name
Test status
Simulation time 97304459 ps
CPU time 1.13 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:19 PM PDT 24
Peak memory 216476 kb
Host smart-dbb1558a-8cf5-4ba8-8487-1b4d7cfb7256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446721502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1446721502
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2439549943
Short name T339
Test name
Test status
Simulation time 58365709 ps
CPU time 0.93 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:18 PM PDT 24
Peak memory 216296 kb
Host smart-baa12c99-7653-4439-a51e-7d1c6800ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439549943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2439549943
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.530744434
Short name T552
Test name
Test status
Simulation time 38773123 ps
CPU time 1.11 seconds
Started Apr 16 03:07:19 PM PDT 24
Finished Apr 16 03:07:21 PM PDT 24
Peak memory 218768 kb
Host smart-d626bf2f-f19a-467a-b285-6781a4b907a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530744434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.530744434
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.1093416215
Short name T801
Test name
Test status
Simulation time 36564734 ps
CPU time 0.84 seconds
Started Apr 16 03:03:38 PM PDT 24
Finished Apr 16 03:03:40 PM PDT 24
Peak memory 205496 kb
Host smart-79116b82-81d9-4978-a4a6-cba85c02b74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093416215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1093416215
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3735945999
Short name T659
Test name
Test status
Simulation time 67032243 ps
CPU time 0.83 seconds
Started Apr 16 03:03:38 PM PDT 24
Finished Apr 16 03:03:39 PM PDT 24
Peak memory 215188 kb
Host smart-dee11e69-4bb0-4836-ad05-00f1e164590f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735945999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3735945999
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.1464030693
Short name T46
Test name
Test status
Simulation time 76862545 ps
CPU time 0.95 seconds
Started Apr 16 03:03:37 PM PDT 24
Finished Apr 16 03:03:39 PM PDT 24
Peak memory 230728 kb
Host smart-2d58629f-0691-423c-82af-1a039ba04062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464030693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1464030693
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1509511458
Short name T543
Test name
Test status
Simulation time 41264883 ps
CPU time 1.44 seconds
Started Apr 16 03:03:37 PM PDT 24
Finished Apr 16 03:03:39 PM PDT 24
Peak memory 216212 kb
Host smart-552aa9af-f943-4b2e-b544-4812cc3da6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509511458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1509511458
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.380688623
Short name T630
Test name
Test status
Simulation time 23719263 ps
CPU time 0.9 seconds
Started Apr 16 03:03:37 PM PDT 24
Finished Apr 16 03:03:38 PM PDT 24
Peak memory 215400 kb
Host smart-60503987-a445-45de-83fc-ced847bb03e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380688623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.380688623
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.551895970
Short name T296
Test name
Test status
Simulation time 27938541 ps
CPU time 0.93 seconds
Started Apr 16 03:03:38 PM PDT 24
Finished Apr 16 03:03:40 PM PDT 24
Peak memory 214860 kb
Host smart-484ae2fe-a98c-4e69-acda-7457ff83c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551895970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.551895970
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2283707304
Short name T399
Test name
Test status
Simulation time 1587223971 ps
CPU time 4.9 seconds
Started Apr 16 03:03:37 PM PDT 24
Finished Apr 16 03:03:43 PM PDT 24
Peak memory 215976 kb
Host smart-33868b30-7d2a-45a8-b353-7567c9f2c88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283707304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2283707304
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3793636010
Short name T187
Test name
Test status
Simulation time 26455241794 ps
CPU time 300.02 seconds
Started Apr 16 03:03:37 PM PDT 24
Finished Apr 16 03:08:38 PM PDT 24
Peak memory 223324 kb
Host smart-9f6c4efe-2391-4225-9499-41d3092c3022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793636010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3793636010
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.4290857945
Short name T345
Test name
Test status
Simulation time 55377324 ps
CPU time 1.21 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:19 PM PDT 24
Peak memory 216184 kb
Host smart-3d1f5e50-a4fd-4ce2-94c6-d7b6143f1b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290857945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.4290857945
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1744924357
Short name T285
Test name
Test status
Simulation time 66534007 ps
CPU time 1.35 seconds
Started Apr 16 03:07:18 PM PDT 24
Finished Apr 16 03:07:20 PM PDT 24
Peak memory 217456 kb
Host smart-521f8d6f-1f22-4a60-bd9f-fc0bb0b89f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744924357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1744924357
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.526075340
Short name T255
Test name
Test status
Simulation time 75064385 ps
CPU time 1.43 seconds
Started Apr 16 03:07:16 PM PDT 24
Finished Apr 16 03:07:19 PM PDT 24
Peak memory 216340 kb
Host smart-2491eb3e-571b-484a-a0f8-f08a3d449fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526075340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.526075340
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2293555210
Short name T263
Test name
Test status
Simulation time 108111767 ps
CPU time 1.1 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:19 PM PDT 24
Peak memory 216104 kb
Host smart-19ad7e61-f943-4a34-bfdc-d3f954e51422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293555210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2293555210
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1198106297
Short name T831
Test name
Test status
Simulation time 96264118 ps
CPU time 0.98 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:19 PM PDT 24
Peak memory 216232 kb
Host smart-42d3a51d-4a7a-4b80-bc3c-88e59357dd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198106297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1198106297
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3043625215
Short name T11
Test name
Test status
Simulation time 67542065 ps
CPU time 1.39 seconds
Started Apr 16 03:07:17 PM PDT 24
Finished Apr 16 03:07:20 PM PDT 24
Peak memory 218964 kb
Host smart-c30fa602-676e-4315-8a67-61966c9f255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043625215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3043625215
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3228985801
Short name T277
Test name
Test status
Simulation time 31626966 ps
CPU time 1.3 seconds
Started Apr 16 03:07:16 PM PDT 24
Finished Apr 16 03:07:18 PM PDT 24
Peak memory 217500 kb
Host smart-58d21b8b-0b1f-4fc5-be08-95bb23422108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228985801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3228985801
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3271638483
Short name T797
Test name
Test status
Simulation time 68019061 ps
CPU time 1.23 seconds
Started Apr 16 03:07:16 PM PDT 24
Finished Apr 16 03:07:18 PM PDT 24
Peak memory 217800 kb
Host smart-6f44c0cc-3b87-4ad5-b7d1-23bf32101c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271638483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3271638483
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1020237940
Short name T441
Test name
Test status
Simulation time 41365725 ps
CPU time 1.39 seconds
Started Apr 16 03:07:20 PM PDT 24
Finished Apr 16 03:07:22 PM PDT 24
Peak memory 214792 kb
Host smart-4021e1f6-a7f6-4cd9-8b64-0fbc5785764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020237940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1020237940
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.224830609
Short name T744
Test name
Test status
Simulation time 92960416 ps
CPU time 1.14 seconds
Started Apr 16 03:07:18 PM PDT 24
Finished Apr 16 03:07:20 PM PDT 24
Peak memory 216372 kb
Host smart-ee10f22a-9e62-41cf-acf4-488458474ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224830609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.224830609
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.2065195754
Short name T464
Test name
Test status
Simulation time 26006144 ps
CPU time 0.9 seconds
Started Apr 16 03:03:42 PM PDT 24
Finished Apr 16 03:03:43 PM PDT 24
Peak memory 206280 kb
Host smart-2b4891c9-0ee6-46e5-ae48-bccab722291f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065195754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2065195754
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4157221489
Short name T98
Test name
Test status
Simulation time 38005249 ps
CPU time 0.8 seconds
Started Apr 16 03:03:43 PM PDT 24
Finished Apr 16 03:03:44 PM PDT 24
Peak memory 215460 kb
Host smart-76f249f6-45de-457c-9df1-9a527fda8f71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157221489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4157221489
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.4217012899
Short name T29
Test name
Test status
Simulation time 49613603 ps
CPU time 1.15 seconds
Started Apr 16 03:03:44 PM PDT 24
Finished Apr 16 03:03:46 PM PDT 24
Peak memory 229344 kb
Host smart-fff57f55-005f-4334-bea5-2b5aa317c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217012899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4217012899
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.609445702
Short name T773
Test name
Test status
Simulation time 66383989 ps
CPU time 1.3 seconds
Started Apr 16 03:03:44 PM PDT 24
Finished Apr 16 03:03:46 PM PDT 24
Peak memory 218320 kb
Host smart-04777057-bbe6-4f9e-a5dd-dda5fac770dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609445702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.609445702
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.696168023
Short name T172
Test name
Test status
Simulation time 21868894 ps
CPU time 1.06 seconds
Started Apr 16 03:03:41 PM PDT 24
Finished Apr 16 03:03:43 PM PDT 24
Peak memory 215096 kb
Host smart-e5865a2e-d3d2-47d8-8257-6cbfaeaebd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696168023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.696168023
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.644908966
Short name T435
Test name
Test status
Simulation time 26704947 ps
CPU time 0.93 seconds
Started Apr 16 03:03:36 PM PDT 24
Finished Apr 16 03:03:38 PM PDT 24
Peak memory 214800 kb
Host smart-31ace036-1063-4dda-90c0-0fb7e2aca4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644908966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.644908966
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2071430308
Short name T675
Test name
Test status
Simulation time 230374468 ps
CPU time 4.93 seconds
Started Apr 16 03:03:49 PM PDT 24
Finished Apr 16 03:03:55 PM PDT 24
Peak memory 217476 kb
Host smart-72024c47-3173-4157-be7a-d46049e02b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071430308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2071430308
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4201537056
Short name T589
Test name
Test status
Simulation time 253070216692 ps
CPU time 1590.87 seconds
Started Apr 16 03:03:44 PM PDT 24
Finished Apr 16 03:30:16 PM PDT 24
Peak memory 226364 kb
Host smart-cef12415-038f-49eb-9196-f98447462a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201537056 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4201537056
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3016664261
Short name T391
Test name
Test status
Simulation time 101500043 ps
CPU time 1.25 seconds
Started Apr 16 03:07:16 PM PDT 24
Finished Apr 16 03:07:18 PM PDT 24
Peak memory 217896 kb
Host smart-cea23c6f-ddf3-4135-816a-a73c6e911c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016664261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3016664261
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1054825863
Short name T622
Test name
Test status
Simulation time 39141838 ps
CPU time 1.09 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:25 PM PDT 24
Peak memory 216208 kb
Host smart-f61f7f2d-ab3c-4446-8ef4-9ef3f01c0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054825863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1054825863
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3197264431
Short name T44
Test name
Test status
Simulation time 368427492 ps
CPU time 1.06 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:24 PM PDT 24
Peak memory 216308 kb
Host smart-095cdb9f-ad31-4e38-8b26-ca4d86b64945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197264431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3197264431
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.484098476
Short name T344
Test name
Test status
Simulation time 38683905 ps
CPU time 1.5 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:25 PM PDT 24
Peak memory 217636 kb
Host smart-d3528bba-1125-4b21-b1d7-140b28ed692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484098476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.484098476
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.81653644
Short name T656
Test name
Test status
Simulation time 47937427 ps
CPU time 1.14 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:25 PM PDT 24
Peak memory 217472 kb
Host smart-30c57f0e-7445-4b69-b60f-0c9799e2bd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81653644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.81653644
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3795563361
Short name T704
Test name
Test status
Simulation time 172238168 ps
CPU time 2.83 seconds
Started Apr 16 03:07:24 PM PDT 24
Finished Apr 16 03:07:28 PM PDT 24
Peak memory 219152 kb
Host smart-061d576b-bad3-4e59-9a65-e2e5f34571d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795563361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3795563361
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2873333145
Short name T830
Test name
Test status
Simulation time 314740702 ps
CPU time 1.67 seconds
Started Apr 16 03:07:21 PM PDT 24
Finished Apr 16 03:07:24 PM PDT 24
Peak memory 218936 kb
Host smart-aeab4877-ceba-4f4c-9a59-7954aefd06ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873333145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2873333145
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1089499603
Short name T411
Test name
Test status
Simulation time 56477704 ps
CPU time 1.03 seconds
Started Apr 16 03:07:22 PM PDT 24
Finished Apr 16 03:07:24 PM PDT 24
Peak memory 217636 kb
Host smart-0ca5f51c-61eb-43b5-b336-f55bfc9f17ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089499603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1089499603
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1740268238
Short name T627
Test name
Test status
Simulation time 141926836 ps
CPU time 1.2 seconds
Started Apr 16 03:07:22 PM PDT 24
Finished Apr 16 03:07:24 PM PDT 24
Peak memory 217520 kb
Host smart-2f6fd5f7-55ef-4c8e-8663-e6363d188a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740268238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1740268238
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.905687699
Short name T267
Test name
Test status
Simulation time 118390700 ps
CPU time 2.48 seconds
Started Apr 16 03:07:22 PM PDT 24
Finished Apr 16 03:07:25 PM PDT 24
Peak memory 216432 kb
Host smart-68849f3d-465a-4d99-aa77-ca783f99a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905687699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.905687699
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.764262284
Short name T152
Test name
Test status
Simulation time 48552791 ps
CPU time 1.17 seconds
Started Apr 16 03:03:47 PM PDT 24
Finished Apr 16 03:03:49 PM PDT 24
Peak memory 215204 kb
Host smart-c0e21ef0-9202-4e6c-b0f0-f9d3255d313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764262284 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.764262284
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4020231986
Short name T513
Test name
Test status
Simulation time 26441393 ps
CPU time 0.9 seconds
Started Apr 16 03:03:48 PM PDT 24
Finished Apr 16 03:03:49 PM PDT 24
Peak memory 206456 kb
Host smart-84f237a5-5959-4c2b-9995-a5a82853a898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020231986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4020231986
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1772436418
Short name T97
Test name
Test status
Simulation time 12220878 ps
CPU time 0.88 seconds
Started Apr 16 03:03:48 PM PDT 24
Finished Apr 16 03:03:50 PM PDT 24
Peak memory 215672 kb
Host smart-0cd3b9d3-9d61-492d-a57f-ea40b8c88e5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772436418 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1772436418
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1533150906
Short name T560
Test name
Test status
Simulation time 33283998 ps
CPU time 1.2 seconds
Started Apr 16 03:03:47 PM PDT 24
Finished Apr 16 03:03:49 PM PDT 24
Peak memory 215920 kb
Host smart-e3a12a99-fd15-4048-a605-91d67b662a87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533150906 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1533150906
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2679902786
Short name T624
Test name
Test status
Simulation time 37820973 ps
CPU time 1.19 seconds
Started Apr 16 03:03:47 PM PDT 24
Finished Apr 16 03:03:49 PM PDT 24
Peak memory 230948 kb
Host smart-152e5125-055e-43bb-a0ab-46a8064d780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679902786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2679902786
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.846761450
Short name T427
Test name
Test status
Simulation time 29034776 ps
CPU time 1.25 seconds
Started Apr 16 03:03:41 PM PDT 24
Finished Apr 16 03:03:43 PM PDT 24
Peak memory 217340 kb
Host smart-f63bbeb6-7925-4470-8169-2e7560e61e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846761450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.846761450
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.659424779
Short name T523
Test name
Test status
Simulation time 22251662 ps
CPU time 1.05 seconds
Started Apr 16 03:03:48 PM PDT 24
Finished Apr 16 03:03:50 PM PDT 24
Peak memory 215056 kb
Host smart-66916343-ad6a-4275-a331-0ae73f0edca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659424779 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.659424779
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.438820232
Short name T782
Test name
Test status
Simulation time 92399380 ps
CPU time 0.9 seconds
Started Apr 16 03:03:44 PM PDT 24
Finished Apr 16 03:03:46 PM PDT 24
Peak memory 214848 kb
Host smart-4620dfef-4d24-4b90-83e0-4a96ae2af4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438820232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.438820232
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.910550766
Short name T463
Test name
Test status
Simulation time 383224875 ps
CPU time 6.96 seconds
Started Apr 16 03:03:43 PM PDT 24
Finished Apr 16 03:03:51 PM PDT 24
Peak memory 218688 kb
Host smart-72914d85-04cd-4056-9720-7d699afe4e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910550766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.910550766
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.4042552423
Short name T149
Test name
Test status
Simulation time 335093750902 ps
CPU time 1855.1 seconds
Started Apr 16 03:03:41 PM PDT 24
Finished Apr 16 03:34:37 PM PDT 24
Peak memory 225656 kb
Host smart-1a7a4e50-cd43-4079-b532-4ae1791fb9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042552423 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.4042552423
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1672909630
Short name T470
Test name
Test status
Simulation time 430976190 ps
CPU time 3.19 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:26 PM PDT 24
Peak memory 216440 kb
Host smart-7a8c3936-2015-4aee-b93e-b945a7b129b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672909630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1672909630
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1466353491
Short name T506
Test name
Test status
Simulation time 28489129 ps
CPU time 1.26 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:25 PM PDT 24
Peak memory 216344 kb
Host smart-f394c98a-4614-4e63-88bc-9bf57d97a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466353491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1466353491
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.162469901
Short name T299
Test name
Test status
Simulation time 30585028 ps
CPU time 1.24 seconds
Started Apr 16 03:07:21 PM PDT 24
Finished Apr 16 03:07:23 PM PDT 24
Peak memory 218640 kb
Host smart-4931581c-c5dd-4b02-b146-c3b6d566d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162469901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.162469901
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2628968936
Short name T146
Test name
Test status
Simulation time 32518289 ps
CPU time 1.28 seconds
Started Apr 16 03:07:23 PM PDT 24
Finished Apr 16 03:07:25 PM PDT 24
Peak memory 217452 kb
Host smart-242ac9a5-eda5-4772-a900-a69d9e1526aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628968936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2628968936
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1061593475
Short name T584
Test name
Test status
Simulation time 57273831 ps
CPU time 1.63 seconds
Started Apr 16 03:07:30 PM PDT 24
Finished Apr 16 03:07:32 PM PDT 24
Peak memory 219276 kb
Host smart-255e5e9d-72e6-4b19-b4b3-bbc4899b66d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061593475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1061593475
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3892413786
Short name T824
Test name
Test status
Simulation time 10461903251 ps
CPU time 133.54 seconds
Started Apr 16 03:07:28 PM PDT 24
Finished Apr 16 03:09:43 PM PDT 24
Peak memory 217676 kb
Host smart-3f748ae8-e61b-48b8-a316-d571ac96803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892413786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3892413786
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.309176269
Short name T555
Test name
Test status
Simulation time 33943427 ps
CPU time 1.31 seconds
Started Apr 16 03:07:28 PM PDT 24
Finished Apr 16 03:07:30 PM PDT 24
Peak memory 216428 kb
Host smart-6ea8c500-941a-4693-9800-245653e38357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309176269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.309176269
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1059036804
Short name T294
Test name
Test status
Simulation time 193789899 ps
CPU time 1.06 seconds
Started Apr 16 03:07:28 PM PDT 24
Finished Apr 16 03:07:30 PM PDT 24
Peak memory 216264 kb
Host smart-afe02697-a8bd-4339-b46a-a1e24bbd8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059036804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1059036804
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1558355930
Short name T814
Test name
Test status
Simulation time 33985254 ps
CPU time 1.27 seconds
Started Apr 16 03:07:28 PM PDT 24
Finished Apr 16 03:07:30 PM PDT 24
Peak memory 216500 kb
Host smart-369d731c-ef78-4531-aec2-3af3442281dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558355930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1558355930
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1599405555
Short name T278
Test name
Test status
Simulation time 37247145 ps
CPU time 1.44 seconds
Started Apr 16 03:07:30 PM PDT 24
Finished Apr 16 03:07:32 PM PDT 24
Peak memory 216324 kb
Host smart-934419ba-b040-4e8d-b5e7-cb04f6c424ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599405555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1599405555
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1864877
Short name T239
Test name
Test status
Simulation time 26992175 ps
CPU time 1.23 seconds
Started Apr 16 03:03:53 PM PDT 24
Finished Apr 16 03:03:55 PM PDT 24
Peak memory 215272 kb
Host smart-aae583ca-a867-4298-8766-61a9e5d0ae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1864877
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3142269973
Short name T833
Test name
Test status
Simulation time 22800089 ps
CPU time 0.88 seconds
Started Apr 16 03:03:55 PM PDT 24
Finished Apr 16 03:03:57 PM PDT 24
Peak memory 205792 kb
Host smart-1673a32d-704f-409f-9b5f-8841b1c4207d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142269973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3142269973
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.675074386
Short name T711
Test name
Test status
Simulation time 11137388 ps
CPU time 0.86 seconds
Started Apr 16 03:03:54 PM PDT 24
Finished Apr 16 03:03:56 PM PDT 24
Peak memory 215212 kb
Host smart-9ff51709-af67-4478-b6e8-6a77b1d06eab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675074386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.675074386
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.650889562
Short name T835
Test name
Test status
Simulation time 126390546 ps
CPU time 1.04 seconds
Started Apr 16 03:04:39 PM PDT 24
Finished Apr 16 03:04:41 PM PDT 24
Peak memory 216020 kb
Host smart-f35a41c0-52cd-48a4-b349-b4c241a0cc4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650889562 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.650889562
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2819296986
Short name T736
Test name
Test status
Simulation time 110217186 ps
CPU time 1.05 seconds
Started Apr 16 03:03:52 PM PDT 24
Finished Apr 16 03:03:54 PM PDT 24
Peak memory 229276 kb
Host smart-b3cffea3-5062-46d9-8739-33dfff27ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819296986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2819296986
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2179908727
Short name T450
Test name
Test status
Simulation time 93722524 ps
CPU time 1.19 seconds
Started Apr 16 03:03:53 PM PDT 24
Finished Apr 16 03:03:55 PM PDT 24
Peak memory 216044 kb
Host smart-8c9b1c08-6609-4cd7-9f72-773e33cc9f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179908727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2179908727
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4130041279
Short name T50
Test name
Test status
Simulation time 20943959 ps
CPU time 1.15 seconds
Started Apr 16 03:03:53 PM PDT 24
Finished Apr 16 03:03:56 PM PDT 24
Peak memory 224180 kb
Host smart-c80060a9-5ce1-4c54-960b-9d122eeb6e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130041279 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4130041279
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3530176693
Short name T405
Test name
Test status
Simulation time 96280913 ps
CPU time 0.87 seconds
Started Apr 16 03:03:45 PM PDT 24
Finished Apr 16 03:03:47 PM PDT 24
Peak memory 214852 kb
Host smart-1b37a707-b4c9-4e69-a07f-fd1386cacac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530176693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3530176693
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.738828365
Short name T369
Test name
Test status
Simulation time 41539942 ps
CPU time 1.05 seconds
Started Apr 16 03:03:53 PM PDT 24
Finished Apr 16 03:03:55 PM PDT 24
Peak memory 214848 kb
Host smart-216f87bc-7d29-40ec-a8be-07c19e7e844f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738828365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.738828365
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1587592059
Short name T620
Test name
Test status
Simulation time 324785655893 ps
CPU time 2190.56 seconds
Started Apr 16 03:03:54 PM PDT 24
Finished Apr 16 03:40:26 PM PDT 24
Peak memory 228404 kb
Host smart-78655a81-8067-4aef-b8fc-3b11c4442e18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587592059 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1587592059
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.344039146
Short name T717
Test name
Test status
Simulation time 80856549 ps
CPU time 1.21 seconds
Started Apr 16 03:07:27 PM PDT 24
Finished Apr 16 03:07:29 PM PDT 24
Peak memory 217712 kb
Host smart-f7ca3b59-aa7a-45c4-acc7-31b740a46398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344039146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.344039146
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2507107114
Short name T408
Test name
Test status
Simulation time 34088541 ps
CPU time 1.32 seconds
Started Apr 16 03:07:37 PM PDT 24
Finished Apr 16 03:07:40 PM PDT 24
Peak memory 217684 kb
Host smart-bd87682f-9a35-45b5-99b2-f7556f24c497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507107114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2507107114
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.982114808
Short name T701
Test name
Test status
Simulation time 31989747 ps
CPU time 1.05 seconds
Started Apr 16 03:07:36 PM PDT 24
Finished Apr 16 03:07:39 PM PDT 24
Peak memory 218540 kb
Host smart-18c387be-b774-4fee-9700-7945637e7233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982114808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.982114808
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2506394966
Short name T9
Test name
Test status
Simulation time 46872182 ps
CPU time 1.2 seconds
Started Apr 16 03:07:32 PM PDT 24
Finished Apr 16 03:07:33 PM PDT 24
Peak memory 216444 kb
Host smart-bba8ae75-c17a-447f-97f0-2d8190b838dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506394966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2506394966
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.684590765
Short name T723
Test name
Test status
Simulation time 54542996 ps
CPU time 1.18 seconds
Started Apr 16 03:07:31 PM PDT 24
Finished Apr 16 03:07:32 PM PDT 24
Peak memory 217536 kb
Host smart-0d6b5985-3325-42e7-8343-3c6d3076534e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684590765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.684590765
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2049751120
Short name T373
Test name
Test status
Simulation time 138888332 ps
CPU time 1.61 seconds
Started Apr 16 03:07:33 PM PDT 24
Finished Apr 16 03:07:35 PM PDT 24
Peak memory 217688 kb
Host smart-c173f18c-5950-4e46-be3e-0d3e37094214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049751120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2049751120
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1449485750
Short name T265
Test name
Test status
Simulation time 99880121 ps
CPU time 1.47 seconds
Started Apr 16 03:07:33 PM PDT 24
Finished Apr 16 03:07:36 PM PDT 24
Peak memory 217812 kb
Host smart-a8490bce-f99d-422f-bac7-b99e857b5290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449485750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1449485750
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3930618921
Short name T442
Test name
Test status
Simulation time 150498472 ps
CPU time 1.23 seconds
Started Apr 16 03:07:33 PM PDT 24
Finished Apr 16 03:07:35 PM PDT 24
Peak memory 216196 kb
Host smart-8b15acc6-cde4-4e3b-a7b8-f40b09c8cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930618921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3930618921
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4156362401
Short name T351
Test name
Test status
Simulation time 38550572 ps
CPU time 1.4 seconds
Started Apr 16 03:07:35 PM PDT 24
Finished Apr 16 03:07:37 PM PDT 24
Peak memory 218188 kb
Host smart-d60ea586-3d5c-42ff-a6f3-d0b475994a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156362401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4156362401
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3901766383
Short name T536
Test name
Test status
Simulation time 15140786 ps
CPU time 0.78 seconds
Started Apr 16 03:04:00 PM PDT 24
Finished Apr 16 03:04:02 PM PDT 24
Peak memory 205476 kb
Host smart-e977ba73-fd04-41c9-86fc-98f243044b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901766383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3901766383
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3054705131
Short name T108
Test name
Test status
Simulation time 31483410 ps
CPU time 0.85 seconds
Started Apr 16 03:04:03 PM PDT 24
Finished Apr 16 03:04:04 PM PDT 24
Peak memory 215620 kb
Host smart-98974f23-2625-4451-966e-1a1552c8a3d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054705131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3054705131
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.3758266469
Short name T397
Test name
Test status
Simulation time 62035547 ps
CPU time 0.98 seconds
Started Apr 16 03:04:00 PM PDT 24
Finished Apr 16 03:04:02 PM PDT 24
Peak memory 219924 kb
Host smart-39aba996-72cd-4228-8ddb-872b543edf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758266469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3758266469
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.379963437
Short name T268
Test name
Test status
Simulation time 38664512 ps
CPU time 1.12 seconds
Started Apr 16 03:03:59 PM PDT 24
Finished Apr 16 03:04:01 PM PDT 24
Peak memory 216160 kb
Host smart-dc4fc87e-cd02-4f11-b9bb-6f9aba3bc660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379963437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.379963437
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.3827796153
Short name T647
Test name
Test status
Simulation time 19347927 ps
CPU time 0.94 seconds
Started Apr 16 03:03:58 PM PDT 24
Finished Apr 16 03:03:59 PM PDT 24
Peak memory 214900 kb
Host smart-16d0d80f-f624-42d4-b6a0-4c4ed2806e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827796153 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3827796153
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1211005008
Short name T700
Test name
Test status
Simulation time 122398126 ps
CPU time 1.12 seconds
Started Apr 16 03:04:00 PM PDT 24
Finished Apr 16 03:04:02 PM PDT 24
Peak memory 205468 kb
Host smart-f69f48e0-1a45-40b4-9b91-001fcd91704e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211005008 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1211005008
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2232586015
Short name T548
Test name
Test status
Simulation time 38378381344 ps
CPU time 490.6 seconds
Started Apr 16 03:03:59 PM PDT 24
Finished Apr 16 03:12:11 PM PDT 24
Peak memory 217916 kb
Host smart-ee037b5b-9d04-4d81-bec7-960364729115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232586015 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2232586015
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1418034182
Short name T529
Test name
Test status
Simulation time 36392456 ps
CPU time 1.26 seconds
Started Apr 16 03:07:33 PM PDT 24
Finished Apr 16 03:07:35 PM PDT 24
Peak memory 216608 kb
Host smart-0eabda13-3086-4eed-905c-58110996fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418034182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1418034182
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3850121666
Short name T794
Test name
Test status
Simulation time 39947927 ps
CPU time 1.35 seconds
Started Apr 16 03:07:35 PM PDT 24
Finished Apr 16 03:07:38 PM PDT 24
Peak memory 217300 kb
Host smart-59001354-9df8-4306-b1e7-8772fe744be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850121666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3850121666
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3961052577
Short name T527
Test name
Test status
Simulation time 53181616 ps
CPU time 1.72 seconds
Started Apr 16 03:07:32 PM PDT 24
Finished Apr 16 03:07:34 PM PDT 24
Peak memory 217356 kb
Host smart-1c03a6bf-8552-4452-8737-8f2129c8f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961052577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3961052577
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.826392469
Short name T553
Test name
Test status
Simulation time 49175411 ps
CPU time 1.2 seconds
Started Apr 16 03:07:36 PM PDT 24
Finished Apr 16 03:07:38 PM PDT 24
Peak memory 216380 kb
Host smart-faca7330-0533-4009-897b-66ef8b6dd86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826392469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.826392469
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3140653435
Short name T361
Test name
Test status
Simulation time 77584351 ps
CPU time 1.24 seconds
Started Apr 16 03:07:35 PM PDT 24
Finished Apr 16 03:07:37 PM PDT 24
Peak memory 215520 kb
Host smart-87a00d83-c63c-4f7f-9939-a5b512bebbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140653435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3140653435
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1363403229
Short name T680
Test name
Test status
Simulation time 113422746 ps
CPU time 1.62 seconds
Started Apr 16 03:07:37 PM PDT 24
Finished Apr 16 03:07:40 PM PDT 24
Peak memory 217540 kb
Host smart-6cd30b34-955b-4182-a74a-564881550eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363403229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1363403229
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.787040514
Short name T673
Test name
Test status
Simulation time 52699445 ps
CPU time 1.19 seconds
Started Apr 16 03:07:35 PM PDT 24
Finished Apr 16 03:07:37 PM PDT 24
Peak memory 216984 kb
Host smart-51e76606-d022-4c6a-ba55-94905184113a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787040514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.787040514
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.107886625
Short name T593
Test name
Test status
Simulation time 60009017 ps
CPU time 1.96 seconds
Started Apr 16 03:07:35 PM PDT 24
Finished Apr 16 03:07:38 PM PDT 24
Peak memory 217456 kb
Host smart-47392a66-5153-49ca-9d03-73937b966e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107886625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.107886625
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1507986919
Short name T416
Test name
Test status
Simulation time 100058717 ps
CPU time 1.26 seconds
Started Apr 16 03:07:33 PM PDT 24
Finished Apr 16 03:07:35 PM PDT 24
Peak memory 216180 kb
Host smart-8cfe2d66-f03f-465c-bd98-920ecdc23733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507986919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1507986919
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3303054721
Short name T350
Test name
Test status
Simulation time 33501536 ps
CPU time 1.32 seconds
Started Apr 16 03:07:33 PM PDT 24
Finished Apr 16 03:07:35 PM PDT 24
Peak memory 216440 kb
Host smart-b3aaacb9-22e1-40ad-b4c5-f413aea97177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303054721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3303054721
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3285484450
Short name T332
Test name
Test status
Simulation time 25096296 ps
CPU time 1.2 seconds
Started Apr 16 03:01:13 PM PDT 24
Finished Apr 16 03:01:15 PM PDT 24
Peak memory 215272 kb
Host smart-a12d7ea2-2455-4c60-9028-a59b4c1b31b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285484450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3285484450
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3814984548
Short name T533
Test name
Test status
Simulation time 49008181 ps
CPU time 0.9 seconds
Started Apr 16 03:01:19 PM PDT 24
Finished Apr 16 03:01:21 PM PDT 24
Peak memory 206340 kb
Host smart-52fb6a62-5e4a-49ad-af0e-47aee7977622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814984548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3814984548
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3238361732
Short name T479
Test name
Test status
Simulation time 22160536 ps
CPU time 0.79 seconds
Started Apr 16 03:01:18 PM PDT 24
Finished Apr 16 03:01:20 PM PDT 24
Peak memory 215476 kb
Host smart-bb70d5c7-ecf4-4462-b9ee-846cf8ee0074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238361732 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3238361732
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1423664662
Short name T503
Test name
Test status
Simulation time 50108707 ps
CPU time 1.4 seconds
Started Apr 16 03:01:18 PM PDT 24
Finished Apr 16 03:01:20 PM PDT 24
Peak memory 216196 kb
Host smart-c80a4fdf-a8c5-4118-a290-2ae7e9dd6d65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423664662 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1423664662
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1521957802
Short name T134
Test name
Test status
Simulation time 25503777 ps
CPU time 0.9 seconds
Started Apr 16 03:01:18 PM PDT 24
Finished Apr 16 03:01:20 PM PDT 24
Peak memory 217720 kb
Host smart-395e6a95-65d0-4b38-90c2-ed7dd46839ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521957802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1521957802
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_intr.1923006735
Short name T445
Test name
Test status
Simulation time 47445742 ps
CPU time 0.86 seconds
Started Apr 16 03:01:15 PM PDT 24
Finished Apr 16 03:01:16 PM PDT 24
Peak memory 215012 kb
Host smart-f774d90b-ecbe-4d98-9eec-7ac79b60c149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923006735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1923006735
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.3881593578
Short name T825
Test name
Test status
Simulation time 18256764 ps
CPU time 1 seconds
Started Apr 16 03:01:12 PM PDT 24
Finished Apr 16 03:01:14 PM PDT 24
Peak memory 214864 kb
Host smart-ff175bb5-46f9-41f0-9732-b2fa8dd782bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881593578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3881593578
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4201022022
Short name T192
Test name
Test status
Simulation time 302647363 ps
CPU time 5.69 seconds
Started Apr 16 03:01:13 PM PDT 24
Finished Apr 16 03:01:19 PM PDT 24
Peak memory 214860 kb
Host smart-506789c8-259e-4ba6-84f1-6ad0aa715623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201022022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4201022022
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2102572845
Short name T540
Test name
Test status
Simulation time 135993867524 ps
CPU time 706.6 seconds
Started Apr 16 03:01:14 PM PDT 24
Finished Apr 16 03:13:01 PM PDT 24
Peak memory 220496 kb
Host smart-f1512bfb-f9f0-404b-b5f8-edd5ca806292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102572845 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2102572845
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.603508602
Short name T755
Test name
Test status
Simulation time 48456412 ps
CPU time 1.14 seconds
Started Apr 16 03:04:06 PM PDT 24
Finished Apr 16 03:04:09 PM PDT 24
Peak memory 215224 kb
Host smart-a0907b21-6a18-4a24-8bc8-92673660e8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603508602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.603508602
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3898409253
Short name T415
Test name
Test status
Simulation time 50041414 ps
CPU time 0.9 seconds
Started Apr 16 03:04:06 PM PDT 24
Finished Apr 16 03:04:08 PM PDT 24
Peak memory 206300 kb
Host smart-40f37180-ac0c-44ff-9ecc-dee0a8f4defb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898409253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3898409253
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1175227589
Short name T115
Test name
Test status
Simulation time 13538217 ps
CPU time 0.89 seconds
Started Apr 16 03:04:06 PM PDT 24
Finished Apr 16 03:04:08 PM PDT 24
Peak memory 215656 kb
Host smart-3cfec0da-e008-4dfa-84b6-c91d1898ae54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175227589 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1175227589
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1616455824
Short name T741
Test name
Test status
Simulation time 25111282 ps
CPU time 1.05 seconds
Started Apr 16 03:04:07 PM PDT 24
Finished Apr 16 03:04:10 PM PDT 24
Peak memory 217432 kb
Host smart-7a0c1a65-4a51-4f4f-98d1-bcb96667c741
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616455824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1616455824
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2257864872
Short name T661
Test name
Test status
Simulation time 48874121 ps
CPU time 0.86 seconds
Started Apr 16 03:04:08 PM PDT 24
Finished Apr 16 03:04:11 PM PDT 24
Peak memory 217728 kb
Host smart-7dd604a2-5890-4a79-adae-959c5dc5d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257864872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2257864872
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2383788273
Short name T588
Test name
Test status
Simulation time 132679261 ps
CPU time 1.23 seconds
Started Apr 16 03:04:03 PM PDT 24
Finished Apr 16 03:04:05 PM PDT 24
Peak memory 217688 kb
Host smart-74474f55-ddbf-40ea-bc47-31c46f43c6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383788273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2383788273
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.222681844
Short name T61
Test name
Test status
Simulation time 33377583 ps
CPU time 0.9 seconds
Started Apr 16 03:04:07 PM PDT 24
Finished Apr 16 03:04:10 PM PDT 24
Peak memory 215260 kb
Host smart-f29ec02c-d784-48ed-919a-ac8b1d431cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222681844 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.222681844
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3054044436
Short name T346
Test name
Test status
Simulation time 17347979 ps
CPU time 0.97 seconds
Started Apr 16 03:04:00 PM PDT 24
Finished Apr 16 03:04:02 PM PDT 24
Peak memory 214928 kb
Host smart-35b58acc-d0be-48a3-89d6-fbbe306178b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054044436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3054044436
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1610669427
Short name T196
Test name
Test status
Simulation time 533037375 ps
CPU time 3.4 seconds
Started Apr 16 03:03:58 PM PDT 24
Finished Apr 16 03:04:02 PM PDT 24
Peak memory 214872 kb
Host smart-b9b55fc7-49cf-4faf-b613-91ff4184b33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610669427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1610669427
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3306263719
Short name T632
Test name
Test status
Simulation time 30325289729 ps
CPU time 349.72 seconds
Started Apr 16 03:04:08 PM PDT 24
Finished Apr 16 03:10:00 PM PDT 24
Peak memory 218048 kb
Host smart-b934a440-d10c-4764-9792-1ab7b2e297a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306263719 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3306263719
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1774741091
Short name T698
Test name
Test status
Simulation time 222598382 ps
CPU time 1.1 seconds
Started Apr 16 03:04:07 PM PDT 24
Finished Apr 16 03:04:09 PM PDT 24
Peak memory 215252 kb
Host smart-2c55c019-1cc9-40d6-86eb-344e106952bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774741091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1774741091
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1910615567
Short name T693
Test name
Test status
Simulation time 51946122 ps
CPU time 0.83 seconds
Started Apr 16 03:04:08 PM PDT 24
Finished Apr 16 03:04:10 PM PDT 24
Peak memory 206320 kb
Host smart-024e806e-921d-4961-990a-fbffed476065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910615567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1910615567
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3195597087
Short name T658
Test name
Test status
Simulation time 17198138 ps
CPU time 0.82 seconds
Started Apr 16 03:04:08 PM PDT 24
Finished Apr 16 03:04:10 PM PDT 24
Peak memory 215144 kb
Host smart-2f52d9a2-ef08-4c49-bd05-c69a4e0262da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195597087 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3195597087
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.2751874831
Short name T101
Test name
Test status
Simulation time 54556138 ps
CPU time 1.07 seconds
Started Apr 16 03:04:06 PM PDT 24
Finished Apr 16 03:04:09 PM PDT 24
Peak memory 218660 kb
Host smart-26774098-20b5-481a-8780-b394f1b18141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751874831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2751874831
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1608614802
Short name T511
Test name
Test status
Simulation time 57975200 ps
CPU time 1.64 seconds
Started Apr 16 03:04:09 PM PDT 24
Finished Apr 16 03:04:12 PM PDT 24
Peak memory 217428 kb
Host smart-5b8bf90a-98a6-4bd1-a99b-e30b3aabf72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608614802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1608614802
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2319089286
Short name T58
Test name
Test status
Simulation time 30160521 ps
CPU time 0.86 seconds
Started Apr 16 03:04:06 PM PDT 24
Finished Apr 16 03:04:08 PM PDT 24
Peak memory 215264 kb
Host smart-129b0e1b-d7ed-40d5-9196-efdbb244d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319089286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2319089286
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2691261441
Short name T313
Test name
Test status
Simulation time 27812631 ps
CPU time 0.92 seconds
Started Apr 16 03:04:07 PM PDT 24
Finished Apr 16 03:04:10 PM PDT 24
Peak memory 214924 kb
Host smart-30a8ff67-eb2a-4a05-882b-87ba21032399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691261441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2691261441
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2384469841
Short name T677
Test name
Test status
Simulation time 346353922 ps
CPU time 3.93 seconds
Started Apr 16 03:04:10 PM PDT 24
Finished Apr 16 03:04:15 PM PDT 24
Peak memory 214872 kb
Host smart-a45f0bcc-8518-4845-ab82-88c69446f2e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384469841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2384469841
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2261927252
Short name T551
Test name
Test status
Simulation time 70858022546 ps
CPU time 1492.56 seconds
Started Apr 16 03:04:06 PM PDT 24
Finished Apr 16 03:29:00 PM PDT 24
Peak memory 224408 kb
Host smart-e9f33a6b-9cd9-42c4-8132-fc86f43c0e34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261927252 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2261927252
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.713739535
Short name T685
Test name
Test status
Simulation time 94314638 ps
CPU time 1.21 seconds
Started Apr 16 03:04:15 PM PDT 24
Finished Apr 16 03:04:16 PM PDT 24
Peak memory 215252 kb
Host smart-1d75a9f1-a5a9-4eb1-a456-11bea15c13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713739535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.713739535
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2734177838
Short name T438
Test name
Test status
Simulation time 64327368 ps
CPU time 0.82 seconds
Started Apr 16 03:04:14 PM PDT 24
Finished Apr 16 03:04:15 PM PDT 24
Peak memory 206160 kb
Host smart-51fc4725-5ef6-44a5-8b72-3c5fb06875c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734177838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2734177838
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2320938130
Short name T22
Test name
Test status
Simulation time 12712965 ps
CPU time 0.89 seconds
Started Apr 16 03:04:17 PM PDT 24
Finished Apr 16 03:04:18 PM PDT 24
Peak memory 215172 kb
Host smart-f832408f-d6cc-4692-9523-a53d5cf082c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320938130 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2320938130
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.692596923
Short name T70
Test name
Test status
Simulation time 31931691 ps
CPU time 1.22 seconds
Started Apr 16 03:04:13 PM PDT 24
Finished Apr 16 03:04:15 PM PDT 24
Peak memory 216048 kb
Host smart-5add0e33-08e2-443c-b847-84642aaf00d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692596923 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.692596923
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.780931930
Short name T33
Test name
Test status
Simulation time 105943698 ps
CPU time 1.38 seconds
Started Apr 16 03:04:08 PM PDT 24
Finished Apr 16 03:04:11 PM PDT 24
Peak memory 216288 kb
Host smart-619c1a55-b741-4fb3-9792-0eb6c005bf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780931930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.780931930
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_smoke.3209775027
Short name T519
Test name
Test status
Simulation time 71503695 ps
CPU time 0.87 seconds
Started Apr 16 03:04:07 PM PDT 24
Finished Apr 16 03:04:09 PM PDT 24
Peak memory 215156 kb
Host smart-ebe5011f-a7f5-46fa-8803-817140b56755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209775027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3209775027
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3467599650
Short name T575
Test name
Test status
Simulation time 318715594 ps
CPU time 2.52 seconds
Started Apr 16 03:04:13 PM PDT 24
Finished Apr 16 03:04:16 PM PDT 24
Peak memory 216404 kb
Host smart-35b4b5c5-41b4-4132-815e-a440e0eae708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467599650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3467599650
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2968849854
Short name T182
Test name
Test status
Simulation time 61889375196 ps
CPU time 1412.19 seconds
Started Apr 16 03:04:14 PM PDT 24
Finished Apr 16 03:27:47 PM PDT 24
Peak memory 238864 kb
Host smart-d94cf954-fd48-453b-ae15-e4aed4b5f1d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968849854 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2968849854
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.3531324882
Short name T753
Test name
Test status
Simulation time 21640372 ps
CPU time 0.82 seconds
Started Apr 16 03:04:19 PM PDT 24
Finished Apr 16 03:04:21 PM PDT 24
Peak memory 206612 kb
Host smart-9bad70b2-ae14-4cf5-b647-b7f62a8265e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531324882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3531324882
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.680126779
Short name T521
Test name
Test status
Simulation time 32806852 ps
CPU time 0.8 seconds
Started Apr 16 03:04:21 PM PDT 24
Finished Apr 16 03:04:22 PM PDT 24
Peak memory 215228 kb
Host smart-36225f89-1533-4715-a9f6-3f0320b5ee63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680126779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.680126779
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2259612247
Short name T65
Test name
Test status
Simulation time 371166052 ps
CPU time 1.1 seconds
Started Apr 16 03:04:20 PM PDT 24
Finished Apr 16 03:04:22 PM PDT 24
Peak memory 216096 kb
Host smart-8f1b1293-8151-4e15-87b8-f5cafbab4a9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259612247 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2259612247
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3417770984
Short name T571
Test name
Test status
Simulation time 23038082 ps
CPU time 0.93 seconds
Started Apr 16 03:04:21 PM PDT 24
Finished Apr 16 03:04:22 PM PDT 24
Peak memory 217692 kb
Host smart-a11af9ad-4002-4f33-9fa3-8af30c61a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417770984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3417770984
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2646639947
Short name T365
Test name
Test status
Simulation time 21188619 ps
CPU time 1.1 seconds
Started Apr 16 03:04:21 PM PDT 24
Finished Apr 16 03:04:22 PM PDT 24
Peak memory 216476 kb
Host smart-ee0b7ab4-5b75-48ec-8ddb-87367a833f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646639947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2646639947
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3250983625
Short name T375
Test name
Test status
Simulation time 29851776 ps
CPU time 0.98 seconds
Started Apr 16 03:04:22 PM PDT 24
Finished Apr 16 03:04:24 PM PDT 24
Peak memory 223520 kb
Host smart-5b67fdc0-8884-421c-8d01-329a7d89d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250983625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3250983625
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3366781414
Short name T473
Test name
Test status
Simulation time 17898199 ps
CPU time 0.96 seconds
Started Apr 16 03:04:13 PM PDT 24
Finished Apr 16 03:04:15 PM PDT 24
Peak memory 214844 kb
Host smart-ef1efb76-96ee-40f4-86ed-1190480de585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366781414 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3366781414
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3199606906
Short name T462
Test name
Test status
Simulation time 268772036 ps
CPU time 5.15 seconds
Started Apr 16 03:04:20 PM PDT 24
Finished Apr 16 03:04:25 PM PDT 24
Peak memory 216128 kb
Host smart-f634c01c-0b11-4b0f-9c4a-89df4b8ed4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199606906 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3199606906
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3331591082
Short name T181
Test name
Test status
Simulation time 75229699520 ps
CPU time 964.62 seconds
Started Apr 16 03:04:20 PM PDT 24
Finished Apr 16 03:20:26 PM PDT 24
Peak memory 221756 kb
Host smart-31f24985-af61-4530-8d4a-312dc3fd4293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331591082 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3331591082
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.717495517
Short name T757
Test name
Test status
Simulation time 55618259 ps
CPU time 1.26 seconds
Started Apr 16 03:04:25 PM PDT 24
Finished Apr 16 03:04:27 PM PDT 24
Peak memory 215256 kb
Host smart-ad496336-4c77-4c5c-8eef-02421528751a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717495517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.717495517
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4131122193
Short name T512
Test name
Test status
Simulation time 13774912 ps
CPU time 0.85 seconds
Started Apr 16 03:04:28 PM PDT 24
Finished Apr 16 03:04:30 PM PDT 24
Peak memory 205748 kb
Host smart-edae3385-763d-44fc-b8fe-8f66a1fdd8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131122193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4131122193
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3393166766
Short name T615
Test name
Test status
Simulation time 39257045 ps
CPU time 0.85 seconds
Started Apr 16 03:04:28 PM PDT 24
Finished Apr 16 03:04:29 PM PDT 24
Peak memory 214956 kb
Host smart-88425a0b-a82b-489f-8853-018268d8f4d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393166766 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3393166766
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2453127230
Short name T447
Test name
Test status
Simulation time 71004020 ps
CPU time 1.06 seconds
Started Apr 16 03:04:27 PM PDT 24
Finished Apr 16 03:04:28 PM PDT 24
Peak memory 217316 kb
Host smart-cfe69a64-c184-4739-921f-ab0ce10a0230
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453127230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2453127230
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2740600744
Short name T689
Test name
Test status
Simulation time 24280778 ps
CPU time 0.92 seconds
Started Apr 16 03:04:25 PM PDT 24
Finished Apr 16 03:04:27 PM PDT 24
Peak memory 217876 kb
Host smart-ecb47c64-d833-40d5-a609-c5693c176dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740600744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2740600744
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2549307765
Short name T439
Test name
Test status
Simulation time 33981287 ps
CPU time 1.24 seconds
Started Apr 16 03:04:22 PM PDT 24
Finished Apr 16 03:04:24 PM PDT 24
Peak memory 217240 kb
Host smart-a6bd4843-8a1a-43d5-b905-da4cd18383cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549307765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2549307765
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3625138224
Short name T471
Test name
Test status
Simulation time 22534320 ps
CPU time 1.19 seconds
Started Apr 16 03:04:21 PM PDT 24
Finished Apr 16 03:04:23 PM PDT 24
Peak memory 223708 kb
Host smart-8c51112f-8851-453f-8f51-1f8b45c7928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625138224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3625138224
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.677808107
Short name T795
Test name
Test status
Simulation time 26671996 ps
CPU time 0.91 seconds
Started Apr 16 03:04:19 PM PDT 24
Finished Apr 16 03:04:21 PM PDT 24
Peak memory 214900 kb
Host smart-6bbd081c-fe8f-41c0-8387-3a34b905dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677808107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.677808107
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3537961569
Short name T570
Test name
Test status
Simulation time 127455478 ps
CPU time 2.89 seconds
Started Apr 16 03:04:19 PM PDT 24
Finished Apr 16 03:04:22 PM PDT 24
Peak memory 214900 kb
Host smart-a04e05c3-d07e-472b-8370-f46f29b4c834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537961569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3537961569
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3272602256
Short name T401
Test name
Test status
Simulation time 117856198439 ps
CPU time 1344.96 seconds
Started Apr 16 03:04:22 PM PDT 24
Finished Apr 16 03:26:48 PM PDT 24
Peak memory 223332 kb
Host smart-971ed245-43bb-4acc-95aa-705ff02de65f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272602256 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3272602256
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2606304388
Short name T13
Test name
Test status
Simulation time 78858137 ps
CPU time 1.12 seconds
Started Apr 16 03:04:27 PM PDT 24
Finished Apr 16 03:04:29 PM PDT 24
Peak memory 215292 kb
Host smart-32695649-9de7-4111-a2a4-f6ba5202a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606304388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2606304388
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.4091867271
Short name T382
Test name
Test status
Simulation time 29076266 ps
CPU time 1.1 seconds
Started Apr 16 03:04:32 PM PDT 24
Finished Apr 16 03:04:34 PM PDT 24
Peak memory 205700 kb
Host smart-d37ee1e9-9463-4b7c-b4f6-bcc894c9cf94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091867271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4091867271
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_err.189886142
Short name T75
Test name
Test status
Simulation time 38008687 ps
CPU time 1.16 seconds
Started Apr 16 03:04:31 PM PDT 24
Finished Apr 16 03:04:33 PM PDT 24
Peak memory 229444 kb
Host smart-6b114a2b-dcea-4b71-a83d-950b8256f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189886142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.189886142
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3155321262
Short name T752
Test name
Test status
Simulation time 50764674 ps
CPU time 1.14 seconds
Started Apr 16 03:04:25 PM PDT 24
Finished Apr 16 03:04:27 PM PDT 24
Peak memory 216096 kb
Host smart-39cb4ea4-cd5d-4457-939a-02a40e9dacf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155321262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3155321262
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3481603886
Short name T148
Test name
Test status
Simulation time 39362906 ps
CPU time 0.89 seconds
Started Apr 16 03:04:28 PM PDT 24
Finished Apr 16 03:04:29 PM PDT 24
Peak memory 215108 kb
Host smart-3d93321c-5ca6-4b8d-b639-46873538065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481603886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3481603886
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3979890349
Short name T354
Test name
Test status
Simulation time 29659761 ps
CPU time 0.91 seconds
Started Apr 16 03:04:29 PM PDT 24
Finished Apr 16 03:04:30 PM PDT 24
Peak memory 214888 kb
Host smart-dfc777f4-45bc-443c-a2c3-726fefaf335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979890349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3979890349
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2300102720
Short name T590
Test name
Test status
Simulation time 180416243 ps
CPU time 3.79 seconds
Started Apr 16 03:04:28 PM PDT 24
Finished Apr 16 03:04:32 PM PDT 24
Peak memory 214892 kb
Host smart-94d870cf-49fc-4c71-bca9-e54315eeb3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300102720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2300102720
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4235834995
Short name T771
Test name
Test status
Simulation time 255420563127 ps
CPU time 1606.1 seconds
Started Apr 16 03:04:28 PM PDT 24
Finished Apr 16 03:31:15 PM PDT 24
Peak memory 226144 kb
Host smart-70567f1c-26f3-4ea7-9db2-3027bc68c876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235834995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4235834995
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.45069791
Short name T495
Test name
Test status
Simulation time 51807934 ps
CPU time 1.25 seconds
Started Apr 16 03:04:33 PM PDT 24
Finished Apr 16 03:04:35 PM PDT 24
Peak memory 215260 kb
Host smart-d806d282-d352-4131-b1b7-b21de9542f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45069791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.45069791
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.305341665
Short name T715
Test name
Test status
Simulation time 22436761 ps
CPU time 0.86 seconds
Started Apr 16 03:04:36 PM PDT 24
Finished Apr 16 03:04:38 PM PDT 24
Peak memory 206580 kb
Host smart-6913f9da-c217-469b-a37b-6e81b1ae3469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305341665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.305341665
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1531099019
Short name T125
Test name
Test status
Simulation time 20337499 ps
CPU time 0.83 seconds
Started Apr 16 03:04:31 PM PDT 24
Finished Apr 16 03:04:32 PM PDT 24
Peak memory 215484 kb
Host smart-f50ff1f2-689a-4d5d-b601-71cbc4183570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531099019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1531099019
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.3387581686
Short name T72
Test name
Test status
Simulation time 20487022 ps
CPU time 1.15 seconds
Started Apr 16 03:04:31 PM PDT 24
Finished Apr 16 03:04:33 PM PDT 24
Peak memory 219176 kb
Host smart-aa5e99e5-f6d0-47de-9f90-f85883c3fa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387581686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3387581686
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1946657429
Short name T662
Test name
Test status
Simulation time 51314145 ps
CPU time 1.28 seconds
Started Apr 16 03:04:33 PM PDT 24
Finished Apr 16 03:04:35 PM PDT 24
Peak memory 217644 kb
Host smart-6ac45e04-9a0a-4317-b578-9f92644b7813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946657429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1946657429
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1213791305
Short name T57
Test name
Test status
Simulation time 38333465 ps
CPU time 0.87 seconds
Started Apr 16 03:04:31 PM PDT 24
Finished Apr 16 03:04:33 PM PDT 24
Peak memory 215192 kb
Host smart-2b09f451-2ba8-486f-a8ae-c391a6ead34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213791305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1213791305
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3112459219
Short name T407
Test name
Test status
Simulation time 14865790 ps
CPU time 0.99 seconds
Started Apr 16 03:04:30 PM PDT 24
Finished Apr 16 03:04:32 PM PDT 24
Peak memory 214884 kb
Host smart-6027b593-b868-4a53-958e-fe8e3528a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112459219 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3112459219
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1607617854
Short name T644
Test name
Test status
Simulation time 740530158 ps
CPU time 6.14 seconds
Started Apr 16 03:04:33 PM PDT 24
Finished Apr 16 03:04:40 PM PDT 24
Peak memory 216208 kb
Host smart-048ab058-dabd-41ee-9f40-19cbca96b5a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607617854 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1607617854
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2536131086
Short name T188
Test name
Test status
Simulation time 1671083435505 ps
CPU time 2584.48 seconds
Started Apr 16 03:04:31 PM PDT 24
Finished Apr 16 03:47:36 PM PDT 24
Peak memory 225024 kb
Host smart-f36d8384-2ed3-4a83-8232-dadec9ef5ab2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536131086 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2536131086
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3719617417
Short name T175
Test name
Test status
Simulation time 26124031 ps
CPU time 1.29 seconds
Started Apr 16 03:04:35 PM PDT 24
Finished Apr 16 03:04:36 PM PDT 24
Peak memory 215276 kb
Host smart-c42bd01d-1639-4e1b-91ab-29ca5274cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719617417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3719617417
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2399239814
Short name T286
Test name
Test status
Simulation time 17329804 ps
CPU time 0.93 seconds
Started Apr 16 03:04:38 PM PDT 24
Finished Apr 16 03:04:40 PM PDT 24
Peak memory 206340 kb
Host smart-74738938-ffdd-4ff0-a9f3-bde8dc030473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399239814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2399239814
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.356914780
Short name T110
Test name
Test status
Simulation time 11087319 ps
CPU time 0.85 seconds
Started Apr 16 03:04:33 PM PDT 24
Finished Apr 16 03:04:35 PM PDT 24
Peak memory 215444 kb
Host smart-7bae29ec-3a8c-4dc7-b7a6-b40953319260
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356914780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.356914780
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3163311457
Short name T812
Test name
Test status
Simulation time 28879701 ps
CPU time 1.08 seconds
Started Apr 16 03:04:42 PM PDT 24
Finished Apr 16 03:04:45 PM PDT 24
Peak memory 217140 kb
Host smart-0b56d39d-9732-4567-b21b-4b26f58129b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163311457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3163311457
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2915127289
Short name T528
Test name
Test status
Simulation time 23370759 ps
CPU time 1.1 seconds
Started Apr 16 03:04:36 PM PDT 24
Finished Apr 16 03:04:38 PM PDT 24
Peak memory 229160 kb
Host smart-2de47118-c32a-4aac-a756-40c3ac106ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915127289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2915127289
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2402056314
Short name T609
Test name
Test status
Simulation time 77045753 ps
CPU time 1.39 seconds
Started Apr 16 03:04:38 PM PDT 24
Finished Apr 16 03:04:40 PM PDT 24
Peak memory 217608 kb
Host smart-a18414c0-1a1b-4e85-93d4-c3f14f97d5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402056314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2402056314
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1515853315
Short name T144
Test name
Test status
Simulation time 46171996 ps
CPU time 0.81 seconds
Started Apr 16 03:04:36 PM PDT 24
Finished Apr 16 03:04:37 PM PDT 24
Peak memory 215096 kb
Host smart-962fad09-6b85-40fc-aae9-1512c8166165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515853315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1515853315
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3618360372
Short name T448
Test name
Test status
Simulation time 32526788 ps
CPU time 0.93 seconds
Started Apr 16 03:04:34 PM PDT 24
Finished Apr 16 03:04:35 PM PDT 24
Peak memory 214844 kb
Host smart-f413cf99-d0c1-4479-a147-73a2bbcd8233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618360372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3618360372
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3623212744
Short name T712
Test name
Test status
Simulation time 210703205 ps
CPU time 4.51 seconds
Started Apr 16 03:04:33 PM PDT 24
Finished Apr 16 03:04:38 PM PDT 24
Peak memory 216232 kb
Host smart-4c9d3898-4817-4232-87e2-c3e7db399bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623212744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3623212744
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4231607411
Short name T183
Test name
Test status
Simulation time 29039703980 ps
CPU time 648.32 seconds
Started Apr 16 03:04:38 PM PDT 24
Finished Apr 16 03:15:27 PM PDT 24
Peak memory 220612 kb
Host smart-8e28c8ca-b9cf-46e7-8c13-8222869aed2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231607411 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4231607411
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1900081162
Short name T12
Test name
Test status
Simulation time 25841806 ps
CPU time 1.26 seconds
Started Apr 16 03:04:45 PM PDT 24
Finished Apr 16 03:04:48 PM PDT 24
Peak memory 215284 kb
Host smart-7f30d61e-bf55-4265-8b43-32884f0a6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900081162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1900081162
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.289995027
Short name T626
Test name
Test status
Simulation time 66825270 ps
CPU time 1.65 seconds
Started Apr 16 03:04:45 PM PDT 24
Finished Apr 16 03:04:49 PM PDT 24
Peak memory 205836 kb
Host smart-70aabe9b-1cbb-4918-9e7d-9c71b80b6813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289995027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.289995027
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1549894712
Short name T126
Test name
Test status
Simulation time 12077000 ps
CPU time 0.84 seconds
Started Apr 16 03:04:46 PM PDT 24
Finished Apr 16 03:04:49 PM PDT 24
Peak memory 215480 kb
Host smart-12a0cf4b-b83e-45b3-9ea9-3ac28cac587c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549894712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1549894712
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.4045167660
Short name T489
Test name
Test status
Simulation time 20745004 ps
CPU time 0.9 seconds
Started Apr 16 03:04:44 PM PDT 24
Finished Apr 16 03:04:46 PM PDT 24
Peak memory 217724 kb
Host smart-8a765253-9a09-46b3-8c44-90ffcd7d13c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045167660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4045167660
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1043243835
Short name T791
Test name
Test status
Simulation time 28687977 ps
CPU time 1.27 seconds
Started Apr 16 03:04:39 PM PDT 24
Finished Apr 16 03:04:41 PM PDT 24
Peak memory 217524 kb
Host smart-cf87587e-78ea-4b15-86d9-9ab8dce45aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043243835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1043243835
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.652367528
Short name T706
Test name
Test status
Simulation time 34649875 ps
CPU time 0.84 seconds
Started Apr 16 03:04:38 PM PDT 24
Finished Apr 16 03:04:40 PM PDT 24
Peak memory 214692 kb
Host smart-e9c71b90-43a3-4164-acc6-37c93cb0c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652367528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.652367528
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2133504499
Short name T695
Test name
Test status
Simulation time 97437082 ps
CPU time 2.45 seconds
Started Apr 16 03:04:42 PM PDT 24
Finished Apr 16 03:04:46 PM PDT 24
Peak memory 216132 kb
Host smart-852110b5-918c-4393-b1ac-78fe83b42d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133504499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2133504499
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2784940617
Short name T635
Test name
Test status
Simulation time 31978616796 ps
CPU time 737.35 seconds
Started Apr 16 03:04:39 PM PDT 24
Finished Apr 16 03:16:58 PM PDT 24
Peak memory 220884 kb
Host smart-7f7e18cd-ab6b-4a6c-a571-6cbe8734d8f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784940617 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2784940617
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3757039103
Short name T122
Test name
Test status
Simulation time 69816145 ps
CPU time 1.06 seconds
Started Apr 16 03:04:44 PM PDT 24
Finished Apr 16 03:04:47 PM PDT 24
Peak memory 215264 kb
Host smart-2bc26371-a195-43eb-8a85-bebaa15090e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757039103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3757039103
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3409798979
Short name T308
Test name
Test status
Simulation time 16321265 ps
CPU time 0.95 seconds
Started Apr 16 03:04:44 PM PDT 24
Finished Apr 16 03:04:47 PM PDT 24
Peak memory 206280 kb
Host smart-9de080dc-5e44-4f3a-a63a-415ee2a074d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409798979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3409798979
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1119655418
Short name T595
Test name
Test status
Simulation time 25457791 ps
CPU time 0.86 seconds
Started Apr 16 03:04:46 PM PDT 24
Finished Apr 16 03:04:48 PM PDT 24
Peak memory 215448 kb
Host smart-93550b42-d892-4591-8240-1a072305c409
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119655418 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1119655418
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.3073355097
Short name T606
Test name
Test status
Simulation time 48972661 ps
CPU time 0.96 seconds
Started Apr 16 03:04:45 PM PDT 24
Finished Apr 16 03:04:48 PM PDT 24
Peak memory 219156 kb
Host smart-4599a215-a002-4a5d-bf65-0ce02a6277c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073355097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3073355097
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2583584985
Short name T283
Test name
Test status
Simulation time 75087946 ps
CPU time 1.19 seconds
Started Apr 16 03:04:44 PM PDT 24
Finished Apr 16 03:04:47 PM PDT 24
Peak memory 218432 kb
Host smart-24a314e5-35f8-4b03-9b82-f03c2ee58c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583584985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2583584985
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1748251781
Short name T568
Test name
Test status
Simulation time 23100880 ps
CPU time 1.05 seconds
Started Apr 16 03:04:45 PM PDT 24
Finished Apr 16 03:04:48 PM PDT 24
Peak memory 215140 kb
Host smart-1f86dcce-793a-4f0c-bef2-614c215be40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748251781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1748251781
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1114874119
Short name T312
Test name
Test status
Simulation time 26638167 ps
CPU time 0.93 seconds
Started Apr 16 03:04:46 PM PDT 24
Finished Apr 16 03:04:49 PM PDT 24
Peak memory 206696 kb
Host smart-4cdcbe3e-6c0c-4876-a617-b711d528b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114874119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1114874119
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3126122810
Short name T483
Test name
Test status
Simulation time 140222010 ps
CPU time 3.37 seconds
Started Apr 16 03:04:46 PM PDT 24
Finished Apr 16 03:04:51 PM PDT 24
Peak memory 219128 kb
Host smart-40d5d8a5-1d48-4b8a-a668-2fe10952adcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126122810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3126122810
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2856687452
Short name T770
Test name
Test status
Simulation time 112805851979 ps
CPU time 1189.1 seconds
Started Apr 16 03:04:44 PM PDT 24
Finished Apr 16 03:24:35 PM PDT 24
Peak memory 223292 kb
Host smart-3d5ddd90-4d7b-4eba-907d-17308ba682d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856687452 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2856687452
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3864012957
Short name T100
Test name
Test status
Simulation time 22849830 ps
CPU time 1.18 seconds
Started Apr 16 03:01:24 PM PDT 24
Finished Apr 16 03:01:26 PM PDT 24
Peak memory 215272 kb
Host smart-5ba07ae6-de42-446d-a0c0-327ae1dd77f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864012957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3864012957
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3807265657
Short name T326
Test name
Test status
Simulation time 19408578 ps
CPU time 0.9 seconds
Started Apr 16 03:01:32 PM PDT 24
Finished Apr 16 03:01:34 PM PDT 24
Peak memory 205732 kb
Host smart-ff791b1e-1efa-4869-b59d-dbbd13962d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807265657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3807265657
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.328591231
Short name T132
Test name
Test status
Simulation time 16136031 ps
CPU time 0.83 seconds
Started Apr 16 03:01:27 PM PDT 24
Finished Apr 16 03:01:29 PM PDT 24
Peak memory 215584 kb
Host smart-0c0d3f6e-46c7-4e6e-9bac-ae9eaba93470
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328591231 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.328591231
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3759404303
Short name T582
Test name
Test status
Simulation time 106429469 ps
CPU time 1.09 seconds
Started Apr 16 03:01:29 PM PDT 24
Finished Apr 16 03:01:31 PM PDT 24
Peak memory 215968 kb
Host smart-9ee423cb-f19b-492c-bf9a-297fa7a9890e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759404303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3759404303
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2708715632
Short name T83
Test name
Test status
Simulation time 19625311 ps
CPU time 1.19 seconds
Started Apr 16 03:01:29 PM PDT 24
Finished Apr 16 03:01:31 PM PDT 24
Peak memory 230924 kb
Host smart-bb57a84f-83be-4cc5-85ec-9e2e564b4b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708715632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2708715632
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3104270793
Short name T811
Test name
Test status
Simulation time 29323943 ps
CPU time 1.42 seconds
Started Apr 16 03:01:24 PM PDT 24
Finished Apr 16 03:01:26 PM PDT 24
Peak memory 217532 kb
Host smart-c45619be-3007-4637-a96a-0243a30020eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104270793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3104270793
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3487155336
Short name T821
Test name
Test status
Simulation time 27111176 ps
CPU time 0.94 seconds
Started Apr 16 03:01:23 PM PDT 24
Finished Apr 16 03:01:25 PM PDT 24
Peak memory 215196 kb
Host smart-f2c0e3ca-59a4-4471-8676-8a22f1cfd3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487155336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3487155336
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1296197185
Short name T4
Test name
Test status
Simulation time 1742782904 ps
CPU time 5.88 seconds
Started Apr 16 03:01:31 PM PDT 24
Finished Apr 16 03:01:37 PM PDT 24
Peak memory 236420 kb
Host smart-791344f1-c4dd-40b4-a485-5f2f3c79e19c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296197185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1296197185
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1571330834
Short name T390
Test name
Test status
Simulation time 29644877 ps
CPU time 0.94 seconds
Started Apr 16 03:01:19 PM PDT 24
Finished Apr 16 03:01:20 PM PDT 24
Peak memory 214920 kb
Host smart-7c32e977-af84-4746-b5af-14658043a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571330834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1571330834
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3869722083
Short name T128
Test name
Test status
Simulation time 363239133 ps
CPU time 6.84 seconds
Started Apr 16 03:01:28 PM PDT 24
Finished Apr 16 03:01:35 PM PDT 24
Peak memory 219392 kb
Host smart-7cce4ba2-95d9-486a-8116-3d70d52f1219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869722083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3869722083
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4215376928
Short name T368
Test name
Test status
Simulation time 84272660496 ps
CPU time 573.2 seconds
Started Apr 16 03:01:23 PM PDT 24
Finished Apr 16 03:10:57 PM PDT 24
Peak memory 218972 kb
Host smart-ccded692-08a8-412e-9c2d-8fee9292445c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215376928 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4215376928
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.471707815
Short name T153
Test name
Test status
Simulation time 105107746 ps
CPU time 1.32 seconds
Started Apr 16 03:04:49 PM PDT 24
Finished Apr 16 03:04:51 PM PDT 24
Peak memory 215284 kb
Host smart-64b1ebfd-55bf-498c-ba3a-fcf279753040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471707815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.471707815
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2253769287
Short name T41
Test name
Test status
Simulation time 13833143 ps
CPU time 0.85 seconds
Started Apr 16 03:04:52 PM PDT 24
Finished Apr 16 03:04:53 PM PDT 24
Peak memory 205660 kb
Host smart-edbd7afb-aa5a-47d0-9407-0c2ca4cc1915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253769287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2253769287
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3218593700
Short name T114
Test name
Test status
Simulation time 43323408 ps
CPU time 0.86 seconds
Started Apr 16 03:04:54 PM PDT 24
Finished Apr 16 03:04:55 PM PDT 24
Peak memory 215452 kb
Host smart-349a51fa-8584-4d05-b5f9-3d871bfd0c6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218593700 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3218593700
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1008199486
Short name T340
Test name
Test status
Simulation time 282897484 ps
CPU time 1.07 seconds
Started Apr 16 03:04:54 PM PDT 24
Finished Apr 16 03:04:56 PM PDT 24
Peak memory 215984 kb
Host smart-c66fb6de-1678-4a21-951c-f8c7b2d3ee7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008199486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1008199486
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1729047085
Short name T565
Test name
Test status
Simulation time 43039544 ps
CPU time 1.09 seconds
Started Apr 16 03:04:49 PM PDT 24
Finished Apr 16 03:04:51 PM PDT 24
Peak memory 215196 kb
Host smart-ce800a00-ee7e-4c7e-a52f-10759a3fe8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729047085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1729047085
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.2444512162
Short name T484
Test name
Test status
Simulation time 71347136 ps
CPU time 0.84 seconds
Started Apr 16 03:04:54 PM PDT 24
Finished Apr 16 03:04:56 PM PDT 24
Peak memory 214884 kb
Host smart-8995cd05-2a4c-40d7-bfee-3fed54d475a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444512162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2444512162
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2003264352
Short name T621
Test name
Test status
Simulation time 36149580 ps
CPU time 0.88 seconds
Started Apr 16 03:04:47 PM PDT 24
Finished Apr 16 03:04:49 PM PDT 24
Peak memory 214852 kb
Host smart-69c8ec51-8231-47ff-bbb3-2be49e3b79cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003264352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2003264352
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.440837559
Short name T809
Test name
Test status
Simulation time 248351123 ps
CPU time 3.16 seconds
Started Apr 16 03:04:50 PM PDT 24
Finished Apr 16 03:04:54 PM PDT 24
Peak memory 216204 kb
Host smart-99095bac-2bfa-4a90-91e8-ae34dbc9a778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440837559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.440837559
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1263411878
Short name T502
Test name
Test status
Simulation time 171066842869 ps
CPU time 1107.97 seconds
Started Apr 16 03:04:50 PM PDT 24
Finished Apr 16 03:23:19 PM PDT 24
Peak memory 223604 kb
Host smart-5d9cb820-72a7-42a4-9621-e72e57c53bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263411878 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1263411878
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3898137057
Short name T154
Test name
Test status
Simulation time 44071194 ps
CPU time 1.19 seconds
Started Apr 16 03:04:58 PM PDT 24
Finished Apr 16 03:05:00 PM PDT 24
Peak memory 215244 kb
Host smart-2b27b1a9-cd58-470e-8b49-3e0fff3bde43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898137057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3898137057
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3383438794
Short name T535
Test name
Test status
Simulation time 13349022 ps
CPU time 0.86 seconds
Started Apr 16 03:04:57 PM PDT 24
Finished Apr 16 03:04:58 PM PDT 24
Peak memory 205620 kb
Host smart-af056f0e-79ee-4e52-9756-9e3ca5c14ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383438794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3383438794
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2476876583
Short name T654
Test name
Test status
Simulation time 13994014 ps
CPU time 0.92 seconds
Started Apr 16 03:04:55 PM PDT 24
Finished Apr 16 03:04:57 PM PDT 24
Peak memory 215316 kb
Host smart-f2d465c5-ddcd-4de6-afa2-fc81c3672546
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476876583 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2476876583
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1873857983
Short name T716
Test name
Test status
Simulation time 27968021 ps
CPU time 1.07 seconds
Started Apr 16 03:04:56 PM PDT 24
Finished Apr 16 03:04:58 PM PDT 24
Peak memory 217200 kb
Host smart-58b06c52-dfa9-4f02-81b4-e50b9e6609f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873857983 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1873857983
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1718003774
Short name T612
Test name
Test status
Simulation time 57424465 ps
CPU time 0.89 seconds
Started Apr 16 03:04:55 PM PDT 24
Finished Apr 16 03:04:57 PM PDT 24
Peak memory 217636 kb
Host smart-7babeaf8-5dd6-47e5-a5b1-baa0d54b8d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718003774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1718003774
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3798264136
Short name T496
Test name
Test status
Simulation time 38015398 ps
CPU time 1.13 seconds
Started Apr 16 03:04:51 PM PDT 24
Finished Apr 16 03:04:53 PM PDT 24
Peak memory 217696 kb
Host smart-8811b578-2ab5-4737-be96-ab0d2110858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798264136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3798264136
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3281548912
Short name T818
Test name
Test status
Simulation time 21943797 ps
CPU time 1.02 seconds
Started Apr 16 03:04:54 PM PDT 24
Finished Apr 16 03:04:56 PM PDT 24
Peak memory 215676 kb
Host smart-86ca1223-8a9d-4264-a984-f4656a8db78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281548912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3281548912
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2546628791
Short name T459
Test name
Test status
Simulation time 18026698 ps
CPU time 1 seconds
Started Apr 16 03:04:50 PM PDT 24
Finished Apr 16 03:04:52 PM PDT 24
Peak memory 214852 kb
Host smart-0f4b0716-baf5-4d63-a932-3195c19cb645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546628791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2546628791
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3648377620
Short name T347
Test name
Test status
Simulation time 327809874 ps
CPU time 3.63 seconds
Started Apr 16 03:04:50 PM PDT 24
Finished Apr 16 03:04:55 PM PDT 24
Peak memory 216068 kb
Host smart-4d5dabf8-b33e-4a4a-858c-a4318276b8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648377620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3648377620
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3530769177
Short name T186
Test name
Test status
Simulation time 155081079918 ps
CPU time 1716.77 seconds
Started Apr 16 03:04:53 PM PDT 24
Finished Apr 16 03:33:31 PM PDT 24
Peak memory 223940 kb
Host smart-578661de-4e66-42b7-bdd4-d084fc9f43cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530769177 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3530769177
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1816625704
Short name T601
Test name
Test status
Simulation time 49651452 ps
CPU time 1.27 seconds
Started Apr 16 03:05:00 PM PDT 24
Finished Apr 16 03:05:02 PM PDT 24
Peak memory 215292 kb
Host smart-a00dbf7a-f218-4b2c-bc35-bf81f399e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816625704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1816625704
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1061989761
Short name T696
Test name
Test status
Simulation time 27835447 ps
CPU time 0.93 seconds
Started Apr 16 03:05:00 PM PDT 24
Finished Apr 16 03:05:02 PM PDT 24
Peak memory 206336 kb
Host smart-c18b1c04-955a-49ce-a8c0-dea978c3e7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061989761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1061989761
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3867479997
Short name T728
Test name
Test status
Simulation time 56406249 ps
CPU time 1.19 seconds
Started Apr 16 03:05:01 PM PDT 24
Finished Apr 16 03:05:03 PM PDT 24
Peak memory 216088 kb
Host smart-560bd6d0-e5b5-408e-9bc5-84d08f9938dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867479997 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3867479997
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3073415995
Short name T95
Test name
Test status
Simulation time 19954226 ps
CPU time 1.15 seconds
Started Apr 16 03:05:02 PM PDT 24
Finished Apr 16 03:05:04 PM PDT 24
Peak memory 217660 kb
Host smart-617e50de-4d66-4352-a9f8-84037386faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073415995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3073415995
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.713349134
Short name T378
Test name
Test status
Simulation time 74444825 ps
CPU time 1.12 seconds
Started Apr 16 03:04:54 PM PDT 24
Finished Apr 16 03:04:56 PM PDT 24
Peak memory 216116 kb
Host smart-91675e43-a42e-4b15-b631-26a316c6ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713349134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.713349134
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.686977282
Short name T325
Test name
Test status
Simulation time 30746168 ps
CPU time 1.12 seconds
Started Apr 16 03:05:03 PM PDT 24
Finished Apr 16 03:05:05 PM PDT 24
Peak memory 223652 kb
Host smart-4cfa41f8-e25c-4ed2-9b01-46cb205b92b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686977282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.686977282
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3902541662
Short name T554
Test name
Test status
Simulation time 23218827 ps
CPU time 0.87 seconds
Started Apr 16 03:04:55 PM PDT 24
Finished Apr 16 03:04:57 PM PDT 24
Peak memory 214852 kb
Host smart-4c7aff0f-bcfd-4b06-b382-a1cc42b5b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902541662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3902541662
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.935765425
Short name T783
Test name
Test status
Simulation time 196930532 ps
CPU time 2.6 seconds
Started Apr 16 03:04:56 PM PDT 24
Finished Apr 16 03:04:59 PM PDT 24
Peak memory 214844 kb
Host smart-0b10abfa-739d-4337-932f-9232bee03fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935765425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.935765425
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2054866008
Short name T180
Test name
Test status
Simulation time 159056055916 ps
CPU time 1004.11 seconds
Started Apr 16 03:04:54 PM PDT 24
Finished Apr 16 03:21:39 PM PDT 24
Peak memory 222692 kb
Host smart-df187eb0-3962-4d25-a384-c79b2e3150e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054866008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2054866008
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1864243621
Short name T485
Test name
Test status
Simulation time 48445050 ps
CPU time 1.2 seconds
Started Apr 16 03:05:07 PM PDT 24
Finished Apr 16 03:05:10 PM PDT 24
Peak memory 215292 kb
Host smart-d5127595-7b2b-448c-9f67-f1f70a8c2b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864243621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1864243621
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3029677891
Short name T820
Test name
Test status
Simulation time 19840424 ps
CPU time 0.83 seconds
Started Apr 16 03:05:07 PM PDT 24
Finished Apr 16 03:05:09 PM PDT 24
Peak memory 205764 kb
Host smart-8cce622e-aa84-44f2-a665-f189a9a4669d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029677891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3029677891
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1028002730
Short name T718
Test name
Test status
Simulation time 21886331 ps
CPU time 0.87 seconds
Started Apr 16 03:05:06 PM PDT 24
Finished Apr 16 03:05:08 PM PDT 24
Peak memory 215484 kb
Host smart-41d34ee1-5fb3-4108-a2b2-fa065249bd57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028002730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1028002730
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1759143083
Short name T63
Test name
Test status
Simulation time 24946599 ps
CPU time 0.99 seconds
Started Apr 16 03:05:06 PM PDT 24
Finished Apr 16 03:05:07 PM PDT 24
Peak memory 217628 kb
Host smart-0316a868-997f-404f-82df-078abd16cdf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759143083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1759143083
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1971963518
Short name T310
Test name
Test status
Simulation time 23443933 ps
CPU time 0.91 seconds
Started Apr 16 03:05:06 PM PDT 24
Finished Apr 16 03:05:08 PM PDT 24
Peak memory 217520 kb
Host smart-9d106e9b-b85e-44fb-8dc1-fd881348eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971963518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1971963518
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1235513880
Short name T256
Test name
Test status
Simulation time 34980738 ps
CPU time 1.3 seconds
Started Apr 16 03:05:08 PM PDT 24
Finished Apr 16 03:05:10 PM PDT 24
Peak memory 216312 kb
Host smart-00217422-16d6-4f8d-9442-20c87bd74f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235513880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1235513880
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.903561606
Short name T158
Test name
Test status
Simulation time 38382855 ps
CPU time 0.76 seconds
Started Apr 16 03:05:06 PM PDT 24
Finished Apr 16 03:05:07 PM PDT 24
Peak memory 215228 kb
Host smart-f0df8a5b-74af-4857-96a2-0a6390d15dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903561606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.903561606
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.495898733
Short name T336
Test name
Test status
Simulation time 17392889 ps
CPU time 0.92 seconds
Started Apr 16 03:05:03 PM PDT 24
Finished Apr 16 03:05:05 PM PDT 24
Peak memory 214904 kb
Host smart-2e554583-6b65-485e-b1e4-316ee127259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495898733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.495898733
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2280079413
Short name T749
Test name
Test status
Simulation time 909025565 ps
CPU time 4.75 seconds
Started Apr 16 03:05:08 PM PDT 24
Finished Apr 16 03:05:13 PM PDT 24
Peak memory 219076 kb
Host smart-c3405b7c-d119-4a04-8a4c-1ebb1e7687e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280079413 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2280079413
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.845100861
Short name T508
Test name
Test status
Simulation time 75667007803 ps
CPU time 745.72 seconds
Started Apr 16 03:05:07 PM PDT 24
Finished Apr 16 03:17:34 PM PDT 24
Peak memory 221308 kb
Host smart-d596f666-66c8-47ee-bc1e-dee4911c30c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845100861 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.845100861
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3250239310
Short name T161
Test name
Test status
Simulation time 23392363 ps
CPU time 1.23 seconds
Started Apr 16 03:05:12 PM PDT 24
Finished Apr 16 03:05:14 PM PDT 24
Peak memory 215276 kb
Host smart-f5142093-32a1-4439-9cff-10b3ccfa1e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250239310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3250239310
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2079133754
Short name T779
Test name
Test status
Simulation time 32207301 ps
CPU time 0.79 seconds
Started Apr 16 03:05:12 PM PDT 24
Finished Apr 16 03:05:13 PM PDT 24
Peak memory 205052 kb
Host smart-1a8498f1-ea08-4c02-8b3d-e54f26b45f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079133754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2079133754
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.800354502
Short name T137
Test name
Test status
Simulation time 40005890 ps
CPU time 0.79 seconds
Started Apr 16 03:05:13 PM PDT 24
Finished Apr 16 03:05:14 PM PDT 24
Peak memory 215452 kb
Host smart-60017147-bfef-4b2f-9edf-53d7bedd6165
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800354502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.800354502
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1952930571
Short name T660
Test name
Test status
Simulation time 28931103 ps
CPU time 1.03 seconds
Started Apr 16 03:05:11 PM PDT 24
Finished Apr 16 03:05:13 PM PDT 24
Peak memory 216220 kb
Host smart-023b645f-3bd0-4b1e-b6c5-344a8d83d5db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952930571 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1952930571
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3592641347
Short name T48
Test name
Test status
Simulation time 102830720 ps
CPU time 0.97 seconds
Started Apr 16 03:05:14 PM PDT 24
Finished Apr 16 03:05:16 PM PDT 24
Peak memory 230928 kb
Host smart-26e47007-070a-4cae-b029-c51fb40571ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592641347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3592641347
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3427873136
Short name T827
Test name
Test status
Simulation time 70195666 ps
CPU time 0.97 seconds
Started Apr 16 03:05:09 PM PDT 24
Finished Apr 16 03:05:10 PM PDT 24
Peak memory 214944 kb
Host smart-f889ce30-e4f7-4638-aa02-8ac02df1dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427873136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3427873136
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4206453240
Short name T785
Test name
Test status
Simulation time 21645782 ps
CPU time 1.1 seconds
Started Apr 16 03:05:05 PM PDT 24
Finished Apr 16 03:05:07 PM PDT 24
Peak memory 215424 kb
Host smart-acbdd5a2-1d71-445e-8245-80d990716c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206453240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4206453240
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3979756614
Short name T729
Test name
Test status
Simulation time 48467415 ps
CPU time 0.86 seconds
Started Apr 16 03:05:09 PM PDT 24
Finished Apr 16 03:05:11 PM PDT 24
Peak memory 214908 kb
Host smart-6a35ad4f-4117-4604-8291-e6b539ee99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979756614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3979756614
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1354945052
Short name T759
Test name
Test status
Simulation time 166724702 ps
CPU time 3.4 seconds
Started Apr 16 03:05:09 PM PDT 24
Finished Apr 16 03:05:13 PM PDT 24
Peak memory 216120 kb
Host smart-ec119fff-9f44-4407-a5a7-0e336df74073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354945052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1354945052
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3638794194
Short name T363
Test name
Test status
Simulation time 17376146278 ps
CPU time 407.85 seconds
Started Apr 16 03:05:07 PM PDT 24
Finished Apr 16 03:11:55 PM PDT 24
Peak memory 219676 kb
Host smart-e52cd164-6b19-464e-b7d2-3809d6940586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638794194 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3638794194
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3125644679
Short name T756
Test name
Test status
Simulation time 84684155 ps
CPU time 1.29 seconds
Started Apr 16 03:05:11 PM PDT 24
Finished Apr 16 03:05:13 PM PDT 24
Peak memory 215236 kb
Host smart-733616b4-5d26-44cb-b4c3-3b135b8989ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125644679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3125644679
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3641114790
Short name T792
Test name
Test status
Simulation time 72894272 ps
CPU time 0.86 seconds
Started Apr 16 03:05:19 PM PDT 24
Finished Apr 16 03:05:20 PM PDT 24
Peak memory 205728 kb
Host smart-f38359e9-26c4-4317-901e-1a893a3ff74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641114790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3641114790
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.885162091
Short name T119
Test name
Test status
Simulation time 168006365 ps
CPU time 0.85 seconds
Started Apr 16 03:05:18 PM PDT 24
Finished Apr 16 03:05:19 PM PDT 24
Peak memory 215596 kb
Host smart-cd57496d-fdc8-449d-ae45-e0717371a5a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885162091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.885162091
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3236655237
Short name T80
Test name
Test status
Simulation time 23228981 ps
CPU time 1 seconds
Started Apr 16 03:05:18 PM PDT 24
Finished Apr 16 03:05:19 PM PDT 24
Peak memory 216032 kb
Host smart-973ca0c3-c4eb-4001-bf96-7a898c1e4151
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236655237 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3236655237
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3734429818
Short name T772
Test name
Test status
Simulation time 23510085 ps
CPU time 0.98 seconds
Started Apr 16 03:05:12 PM PDT 24
Finished Apr 16 03:05:14 PM PDT 24
Peak memory 217524 kb
Host smart-cfc51cb6-958a-4709-98e0-759842aa2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734429818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3734429818
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.227233849
Short name T307
Test name
Test status
Simulation time 30142494 ps
CPU time 1.2 seconds
Started Apr 16 03:05:10 PM PDT 24
Finished Apr 16 03:05:12 PM PDT 24
Peak memory 216472 kb
Host smart-9af50de6-d658-4f06-94d1-4daa6575d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227233849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.227233849
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2185824279
Short name T819
Test name
Test status
Simulation time 59357359 ps
CPU time 0.85 seconds
Started Apr 16 03:05:13 PM PDT 24
Finished Apr 16 03:05:14 PM PDT 24
Peak memory 215032 kb
Host smart-3586660b-8f42-4edf-82f8-5636310f3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185824279 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2185824279
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3572932268
Short name T678
Test name
Test status
Simulation time 44732971 ps
CPU time 0.91 seconds
Started Apr 16 03:05:11 PM PDT 24
Finished Apr 16 03:05:12 PM PDT 24
Peak memory 214968 kb
Host smart-e0ec325a-7902-4349-988e-a782ca51e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572932268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3572932268
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1962681982
Short name T195
Test name
Test status
Simulation time 1026782379 ps
CPU time 5.03 seconds
Started Apr 16 03:05:11 PM PDT 24
Finished Apr 16 03:05:17 PM PDT 24
Peak memory 214872 kb
Host smart-2099b4c9-1e9f-4617-b08d-fe6c65b4cc97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962681982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1962681982
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1325721098
Short name T638
Test name
Test status
Simulation time 17157988105 ps
CPU time 435.6 seconds
Started Apr 16 03:05:11 PM PDT 24
Finished Apr 16 03:12:27 PM PDT 24
Peak memory 216680 kb
Host smart-75f8fa21-6b98-4b8f-9f45-1476ad0dc18c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325721098 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1325721098
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.2920489898
Short name T42
Test name
Test status
Simulation time 50736662 ps
CPU time 0.86 seconds
Started Apr 16 03:05:25 PM PDT 24
Finished Apr 16 03:05:26 PM PDT 24
Peak memory 206556 kb
Host smart-457b68d7-57fa-4765-acf9-0fbcf1aea0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920489898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2920489898
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3015272034
Short name T32
Test name
Test status
Simulation time 11685730 ps
CPU time 0.89 seconds
Started Apr 16 03:05:22 PM PDT 24
Finished Apr 16 03:05:23 PM PDT 24
Peak memory 215628 kb
Host smart-36815cdc-00b6-4889-9053-cfa06443b2b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015272034 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3015272034
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3327556259
Short name T87
Test name
Test status
Simulation time 36837908 ps
CPU time 1.16 seconds
Started Apr 16 03:05:25 PM PDT 24
Finished Apr 16 03:05:26 PM PDT 24
Peak memory 216072 kb
Host smart-08bef69c-44b4-4f27-85ee-7055c893a4c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327556259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3327556259
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.651348739
Short name T430
Test name
Test status
Simulation time 20414937 ps
CPU time 1.04 seconds
Started Apr 16 03:05:24 PM PDT 24
Finished Apr 16 03:05:25 PM PDT 24
Peak memory 217884 kb
Host smart-98250705-4476-4c66-bc70-889af24b0b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651348739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.651348739
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2896193185
Short name T651
Test name
Test status
Simulation time 37714100 ps
CPU time 1.52 seconds
Started Apr 16 03:05:17 PM PDT 24
Finished Apr 16 03:05:19 PM PDT 24
Peak memory 216472 kb
Host smart-94966501-bbd2-4267-8480-fe15dc991d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896193185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2896193185
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1602547759
Short name T327
Test name
Test status
Simulation time 105037605 ps
CPU time 0.82 seconds
Started Apr 16 03:05:21 PM PDT 24
Finished Apr 16 03:05:22 PM PDT 24
Peak memory 214976 kb
Host smart-df4bb7d1-b3dc-4016-930f-5c16879806ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602547759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1602547759
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.724253668
Short name T481
Test name
Test status
Simulation time 188812347 ps
CPU time 0.93 seconds
Started Apr 16 03:05:16 PM PDT 24
Finished Apr 16 03:05:18 PM PDT 24
Peak memory 214836 kb
Host smart-06b0d1c7-5eaa-4910-b555-9cf160d17683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724253668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.724253668
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.276152878
Short name T254
Test name
Test status
Simulation time 38213619 ps
CPU time 1.31 seconds
Started Apr 16 03:05:17 PM PDT 24
Finished Apr 16 03:05:19 PM PDT 24
Peak memory 216220 kb
Host smart-ed958536-45d6-4cb3-9378-8efad5351558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276152878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.276152878
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2933448593
Short name T396
Test name
Test status
Simulation time 58440487888 ps
CPU time 369.72 seconds
Started Apr 16 03:05:18 PM PDT 24
Finished Apr 16 03:11:28 PM PDT 24
Peak memory 218672 kb
Host smart-558ff589-e109-48c1-9701-232fc6e756cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933448593 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2933448593
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2314236326
Short name T798
Test name
Test status
Simulation time 76184175 ps
CPU time 1.14 seconds
Started Apr 16 03:05:22 PM PDT 24
Finished Apr 16 03:05:23 PM PDT 24
Peak memory 215280 kb
Host smart-d2119e78-1bac-42b9-8f64-fa7b973f81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314236326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2314236326
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.458796728
Short name T829
Test name
Test status
Simulation time 44876361 ps
CPU time 0.85 seconds
Started Apr 16 03:05:21 PM PDT 24
Finished Apr 16 03:05:22 PM PDT 24
Peak memory 206276 kb
Host smart-95e33cee-ac7b-4f3b-8cb5-846e85e949a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458796728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.458796728
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3275351453
Short name T515
Test name
Test status
Simulation time 19562369 ps
CPU time 0.86 seconds
Started Apr 16 03:05:22 PM PDT 24
Finished Apr 16 03:05:23 PM PDT 24
Peak memory 215176 kb
Host smart-a0b9a481-4e5d-4297-8424-c6afb3774c4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275351453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3275351453
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.1284064567
Short name T96
Test name
Test status
Simulation time 43402890 ps
CPU time 0.94 seconds
Started Apr 16 03:05:25 PM PDT 24
Finished Apr 16 03:05:26 PM PDT 24
Peak memory 230912 kb
Host smart-5cea6fdb-6cf1-479d-88f9-7e19e0dcf0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284064567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1284064567
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1383821250
Short name T31
Test name
Test status
Simulation time 114766491 ps
CPU time 1.12 seconds
Started Apr 16 03:05:25 PM PDT 24
Finished Apr 16 03:05:27 PM PDT 24
Peak memory 216256 kb
Host smart-6736ea5b-9048-4f93-922b-23fa3815fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383821250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1383821250
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3396550715
Short name T174
Test name
Test status
Simulation time 21921210 ps
CPU time 1 seconds
Started Apr 16 03:05:22 PM PDT 24
Finished Apr 16 03:05:23 PM PDT 24
Peak memory 215192 kb
Host smart-51d62590-d87b-4399-a597-aaf3a201b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396550715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3396550715
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3541492909
Short name T306
Test name
Test status
Simulation time 21547874 ps
CPU time 0.93 seconds
Started Apr 16 03:05:24 PM PDT 24
Finished Apr 16 03:05:26 PM PDT 24
Peak memory 214904 kb
Host smart-c6e37ebb-c0b1-497f-ad4a-944fd7cb1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541492909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3541492909
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2217962416
Short name T330
Test name
Test status
Simulation time 886274835 ps
CPU time 2.94 seconds
Started Apr 16 03:05:27 PM PDT 24
Finished Apr 16 03:05:30 PM PDT 24
Peak memory 216420 kb
Host smart-7b9938da-6b35-436c-bea2-fe8ad350aef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217962416 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2217962416
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3331205608
Short name T805
Test name
Test status
Simulation time 101462911188 ps
CPU time 934.12 seconds
Started Apr 16 03:05:27 PM PDT 24
Finished Apr 16 03:21:02 PM PDT 24
Peak memory 223320 kb
Host smart-23f22360-797b-419c-b3e8-722cdb90cdf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331205608 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3331205608
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3584758693
Short name T248
Test name
Test status
Simulation time 26835753 ps
CPU time 1.26 seconds
Started Apr 16 03:05:26 PM PDT 24
Finished Apr 16 03:05:28 PM PDT 24
Peak memory 215304 kb
Host smart-ff9f831c-5241-4be0-8f66-2b1afd16030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584758693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3584758693
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3125193051
Short name T444
Test name
Test status
Simulation time 132466246 ps
CPU time 0.84 seconds
Started Apr 16 03:05:26 PM PDT 24
Finished Apr 16 03:05:28 PM PDT 24
Peak memory 206200 kb
Host smart-f9dc126d-b90d-4e25-8037-7f84165bacae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125193051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3125193051
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2859060855
Short name T669
Test name
Test status
Simulation time 14553195 ps
CPU time 0.91 seconds
Started Apr 16 03:05:25 PM PDT 24
Finished Apr 16 03:05:27 PM PDT 24
Peak memory 215164 kb
Host smart-efc23d59-0e55-49ad-a5ba-b3654e6931a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859060855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2859060855
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.2906894136
Short name T298
Test name
Test status
Simulation time 22289160 ps
CPU time 0.9 seconds
Started Apr 16 03:05:26 PM PDT 24
Finished Apr 16 03:05:27 PM PDT 24
Peak memory 217184 kb
Host smart-d2e6d2c8-8819-4897-bb8d-386efc902396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906894136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2906894136
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2358012563
Short name T173
Test name
Test status
Simulation time 410474631 ps
CPU time 1.36 seconds
Started Apr 16 03:05:27 PM PDT 24
Finished Apr 16 03:05:29 PM PDT 24
Peak memory 217512 kb
Host smart-0852fac4-2a43-4955-9fa5-e8cebed85eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358012563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2358012563
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.587655180
Short name T53
Test name
Test status
Simulation time 28708246 ps
CPU time 0.89 seconds
Started Apr 16 03:05:28 PM PDT 24
Finished Apr 16 03:05:30 PM PDT 24
Peak memory 215388 kb
Host smart-62f28877-3955-48f2-a645-9ad4858c8aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587655180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.587655180
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.459393737
Short name T353
Test name
Test status
Simulation time 15640668 ps
CPU time 0.94 seconds
Started Apr 16 03:05:25 PM PDT 24
Finished Apr 16 03:05:27 PM PDT 24
Peak memory 214820 kb
Host smart-b44f04f6-8292-426b-b360-b345a12104c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459393737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.459393737
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3940339590
Short name T802
Test name
Test status
Simulation time 642793537 ps
CPU time 1.76 seconds
Started Apr 16 03:05:29 PM PDT 24
Finished Apr 16 03:05:31 PM PDT 24
Peak memory 214932 kb
Host smart-98f51eca-9fa2-45cc-a47e-b999f7eabc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940339590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3940339590
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.2031243920
Short name T162
Test name
Test status
Simulation time 50244924 ps
CPU time 1.23 seconds
Started Apr 16 03:05:33 PM PDT 24
Finished Apr 16 03:05:35 PM PDT 24
Peak memory 215268 kb
Host smart-aa57b03f-b6fd-484a-83d3-d816b6d5249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031243920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2031243920
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2355181916
Short name T546
Test name
Test status
Simulation time 30131357 ps
CPU time 0.91 seconds
Started Apr 16 03:05:34 PM PDT 24
Finished Apr 16 03:05:35 PM PDT 24
Peak memory 205752 kb
Host smart-ec4bed8c-6a7e-4109-919d-cf660f5ead55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355181916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2355181916
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2125486152
Short name T564
Test name
Test status
Simulation time 89901452 ps
CPU time 1.05 seconds
Started Apr 16 03:05:32 PM PDT 24
Finished Apr 16 03:05:33 PM PDT 24
Peak memory 217272 kb
Host smart-413ff6c3-a9db-41d2-8965-403456a6ecc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125486152 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2125486152
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.275249836
Short name T135
Test name
Test status
Simulation time 32035340 ps
CPU time 0.88 seconds
Started Apr 16 03:05:32 PM PDT 24
Finished Apr 16 03:05:34 PM PDT 24
Peak memory 216500 kb
Host smart-997667f1-7ca9-4e12-8736-f03f662904db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275249836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.275249836
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2238962141
Short name T681
Test name
Test status
Simulation time 44431262 ps
CPU time 1.06 seconds
Started Apr 16 03:05:34 PM PDT 24
Finished Apr 16 03:05:36 PM PDT 24
Peak memory 216072 kb
Host smart-ef8dc0c7-0b81-4ea2-be08-9a3bfd336f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238962141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2238962141
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3629182968
Short name T762
Test name
Test status
Simulation time 31137922 ps
CPU time 0.82 seconds
Started Apr 16 03:05:33 PM PDT 24
Finished Apr 16 03:05:34 PM PDT 24
Peak memory 215212 kb
Host smart-6fd388df-d74d-4e42-aa6e-4da6d1434b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629182968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3629182968
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2712156127
Short name T426
Test name
Test status
Simulation time 53722618 ps
CPU time 0.96 seconds
Started Apr 16 03:05:34 PM PDT 24
Finished Apr 16 03:05:35 PM PDT 24
Peak memory 214880 kb
Host smart-02ab2424-9c17-40cf-959b-03c85cf0c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712156127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2712156127
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.429963545
Short name T778
Test name
Test status
Simulation time 751761681 ps
CPU time 4.49 seconds
Started Apr 16 03:05:33 PM PDT 24
Finished Apr 16 03:05:38 PM PDT 24
Peak memory 216312 kb
Host smart-76278f2a-1ddd-4e7f-bedb-f6b304587ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429963545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.429963545
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2660768183
Short name T185
Test name
Test status
Simulation time 82234616766 ps
CPU time 734.96 seconds
Started Apr 16 03:05:34 PM PDT 24
Finished Apr 16 03:17:50 PM PDT 24
Peak memory 223284 kb
Host smart-6e17e419-60f3-4e38-8893-60e9284cf34d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660768183 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2660768183
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.2404973690
Short name T763
Test name
Test status
Simulation time 121618736 ps
CPU time 0.81 seconds
Started Apr 16 03:01:40 PM PDT 24
Finished Apr 16 03:01:42 PM PDT 24
Peak memory 205236 kb
Host smart-91226818-8e78-45b2-a2d1-40dbeb70d067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404973690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2404973690
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.686392255
Short name T131
Test name
Test status
Simulation time 13467471 ps
CPU time 0.92 seconds
Started Apr 16 03:01:40 PM PDT 24
Finished Apr 16 03:01:42 PM PDT 24
Peak memory 215644 kb
Host smart-c320c028-c464-43bc-85c5-853bd9b84469
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686392255 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.686392255
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1483984798
Short name T493
Test name
Test status
Simulation time 27030867 ps
CPU time 1.07 seconds
Started Apr 16 03:01:41 PM PDT 24
Finished Apr 16 03:01:43 PM PDT 24
Peak memory 217452 kb
Host smart-8473e812-5794-4934-a30c-b5ba8a43ccb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483984798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1483984798
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3229949745
Short name T576
Test name
Test status
Simulation time 39912753 ps
CPU time 1.09 seconds
Started Apr 16 03:01:34 PM PDT 24
Finished Apr 16 03:01:35 PM PDT 24
Peak memory 216560 kb
Host smart-85958809-e262-4ca4-8eb7-49868750dee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229949745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3229949745
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3074014652
Short name T328
Test name
Test status
Simulation time 79091167 ps
CPU time 1.1 seconds
Started Apr 16 03:01:32 PM PDT 24
Finished Apr 16 03:01:34 PM PDT 24
Peak memory 216312 kb
Host smart-74eefa76-d46a-459d-a634-7d54abb77cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074014652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3074014652
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.627555172
Short name T743
Test name
Test status
Simulation time 98099793 ps
CPU time 0.83 seconds
Started Apr 16 03:01:35 PM PDT 24
Finished Apr 16 03:01:36 PM PDT 24
Peak memory 214936 kb
Host smart-7554b201-b839-447e-80f9-86cef4ea313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627555172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.627555172
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2920554282
Short name T55
Test name
Test status
Simulation time 36255960 ps
CPU time 0.88 seconds
Started Apr 16 03:01:31 PM PDT 24
Finished Apr 16 03:01:33 PM PDT 24
Peak memory 206672 kb
Host smart-967283a3-477e-4021-836b-71281b8b3f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920554282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2920554282
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.705973340
Short name T591
Test name
Test status
Simulation time 19674024 ps
CPU time 0.97 seconds
Started Apr 16 03:01:31 PM PDT 24
Finished Apr 16 03:01:33 PM PDT 24
Peak memory 215000 kb
Host smart-c3cee717-f538-473a-a1dd-2340eb970a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705973340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.705973340
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3915739438
Short name T386
Test name
Test status
Simulation time 971543142 ps
CPU time 2.7 seconds
Started Apr 16 03:01:35 PM PDT 24
Finished Apr 16 03:01:39 PM PDT 24
Peak memory 216160 kb
Host smart-8502e98c-c507-41c0-a4d4-6ce38f4dad29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915739438 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3915739438
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.212238678
Short name T343
Test name
Test status
Simulation time 67370911827 ps
CPU time 442.37 seconds
Started Apr 16 03:01:35 PM PDT 24
Finished Apr 16 03:08:58 PM PDT 24
Peak memory 218088 kb
Host smart-07916d78-7a7f-4406-94da-78a0a09f5c1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212238678 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.212238678
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3633552649
Short name T505
Test name
Test status
Simulation time 19246469 ps
CPU time 1.02 seconds
Started Apr 16 03:05:33 PM PDT 24
Finished Apr 16 03:05:35 PM PDT 24
Peak memory 217748 kb
Host smart-4a731ca7-939c-41ca-b097-f3b03c1ee734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633552649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3633552649
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2417137521
Short name T323
Test name
Test status
Simulation time 141430964 ps
CPU time 2.63 seconds
Started Apr 16 03:05:31 PM PDT 24
Finished Apr 16 03:05:34 PM PDT 24
Peak memory 218972 kb
Host smart-1ba14496-43aa-4439-a397-4183b33c971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417137521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2417137521
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3711700835
Short name T832
Test name
Test status
Simulation time 26917947 ps
CPU time 0.82 seconds
Started Apr 16 03:05:40 PM PDT 24
Finished Apr 16 03:05:42 PM PDT 24
Peak memory 217232 kb
Host smart-c985008e-a7a2-4ae3-a63d-eebeeaa3ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711700835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3711700835
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.296456256
Short name T454
Test name
Test status
Simulation time 38711608 ps
CPU time 1.36 seconds
Started Apr 16 03:05:33 PM PDT 24
Finished Apr 16 03:05:35 PM PDT 24
Peak memory 216368 kb
Host smart-d0e2acb4-fbd9-4efd-937c-c9613f480f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296456256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.296456256
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3721261704
Short name T371
Test name
Test status
Simulation time 18903477 ps
CPU time 1.06 seconds
Started Apr 16 03:05:36 PM PDT 24
Finished Apr 16 03:05:38 PM PDT 24
Peak memory 217764 kb
Host smart-8df5e0df-9a2f-4a10-a63c-376d63abbdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721261704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3721261704
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2856292554
Short name T544
Test name
Test status
Simulation time 44269076 ps
CPU time 1.2 seconds
Started Apr 16 03:05:39 PM PDT 24
Finished Apr 16 03:05:41 PM PDT 24
Peak memory 214848 kb
Host smart-b9acdd6b-b027-4d4e-bd6b-ea174f935f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856292554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2856292554
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.4219289937
Short name T81
Test name
Test status
Simulation time 25058481 ps
CPU time 1.07 seconds
Started Apr 16 03:05:39 PM PDT 24
Finished Apr 16 03:05:40 PM PDT 24
Peak memory 230960 kb
Host smart-e9086ac7-3598-456b-9b81-599f185ce6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219289937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4219289937
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3500755005
Short name T320
Test name
Test status
Simulation time 41271550 ps
CPU time 1.15 seconds
Started Apr 16 03:05:38 PM PDT 24
Finished Apr 16 03:05:40 PM PDT 24
Peak memory 216320 kb
Host smart-39248ff3-7ab8-465e-a031-b65c880b7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500755005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3500755005
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2943537503
Short name T26
Test name
Test status
Simulation time 26287907 ps
CPU time 0.86 seconds
Started Apr 16 03:05:36 PM PDT 24
Finished Apr 16 03:05:37 PM PDT 24
Peak memory 217676 kb
Host smart-e144c0f4-2f41-4e35-a23a-7b6440b328c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943537503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2943537503
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.633867982
Short name T549
Test name
Test status
Simulation time 88042791 ps
CPU time 2.86 seconds
Started Apr 16 03:05:37 PM PDT 24
Finished Apr 16 03:05:40 PM PDT 24
Peak memory 217488 kb
Host smart-126618d8-56b0-457f-91d9-a7b1b1bb85b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633867982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.633867982
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1127156255
Short name T722
Test name
Test status
Simulation time 19054598 ps
CPU time 1.06 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:49 PM PDT 24
Peak memory 217632 kb
Host smart-1b6337fb-02ce-44fa-b960-0ba759dc7ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127156255 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1127156255
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2472392269
Short name T406
Test name
Test status
Simulation time 59784532 ps
CPU time 1.48 seconds
Started Apr 16 03:05:39 PM PDT 24
Finished Apr 16 03:05:41 PM PDT 24
Peak memory 218428 kb
Host smart-4079ab81-4118-44cb-97ac-75be809f523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472392269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2472392269
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3249239743
Short name T138
Test name
Test status
Simulation time 28630914 ps
CPU time 1.21 seconds
Started Apr 16 03:05:44 PM PDT 24
Finished Apr 16 03:05:46 PM PDT 24
Peak memory 218764 kb
Host smart-1ce1b254-e3c8-4e63-804b-20d40aa1a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249239743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3249239743
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2708241204
Short name T266
Test name
Test status
Simulation time 35707116 ps
CPU time 1.28 seconds
Started Apr 16 03:05:43 PM PDT 24
Finished Apr 16 03:05:45 PM PDT 24
Peak memory 218544 kb
Host smart-69dd12b8-5e5f-4b2d-b1cd-4b4c9bc48cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708241204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2708241204
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2942396015
Short name T142
Test name
Test status
Simulation time 41756490 ps
CPU time 1.04 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:48 PM PDT 24
Peak memory 219100 kb
Host smart-bf2fe81a-afec-47db-a669-ba2ba7bd43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942396015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2942396015
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2297356455
Short name T813
Test name
Test status
Simulation time 76719094 ps
CPU time 1.26 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:49 PM PDT 24
Peak memory 217440 kb
Host smart-1b52efeb-58c0-4137-aaaf-734694216605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297356455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2297356455
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1332476917
Short name T384
Test name
Test status
Simulation time 34265328 ps
CPU time 0.92 seconds
Started Apr 16 03:05:41 PM PDT 24
Finished Apr 16 03:05:42 PM PDT 24
Peak memory 219080 kb
Host smart-f5cf9e15-3d3e-4310-93db-8f1783886b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332476917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1332476917
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4139392266
Short name T30
Test name
Test status
Simulation time 42900820 ps
CPU time 1.52 seconds
Started Apr 16 03:05:42 PM PDT 24
Finished Apr 16 03:05:44 PM PDT 24
Peak memory 216268 kb
Host smart-641dcebd-db7e-473b-9cfb-bdc6eb9b1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139392266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4139392266
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2117387815
Short name T524
Test name
Test status
Simulation time 171969999 ps
CPU time 0.92 seconds
Started Apr 16 03:05:42 PM PDT 24
Finished Apr 16 03:05:44 PM PDT 24
Peak memory 219792 kb
Host smart-bcda9c2a-8841-4af1-95c0-eefc9e5d54e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117387815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2117387815
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.238981068
Short name T385
Test name
Test status
Simulation time 119880959 ps
CPU time 1.49 seconds
Started Apr 16 03:05:44 PM PDT 24
Finished Apr 16 03:05:46 PM PDT 24
Peak memory 217944 kb
Host smart-57055f02-4b28-4525-b065-1d9310d54f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238981068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.238981068
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2795099421
Short name T103
Test name
Test status
Simulation time 49667041 ps
CPU time 1.13 seconds
Started Apr 16 03:01:45 PM PDT 24
Finished Apr 16 03:01:46 PM PDT 24
Peak memory 214596 kb
Host smart-a32d4f44-1275-4898-a5b2-465b8755e6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795099421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2795099421
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3825643
Short name T324
Test name
Test status
Simulation time 40429724 ps
CPU time 0.81 seconds
Started Apr 16 03:01:49 PM PDT 24
Finished Apr 16 03:01:51 PM PDT 24
Peak memory 205468 kb
Host smart-013ee998-4bb6-487a-b745-f1025cf98b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3825643
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_err.2688351960
Short name T436
Test name
Test status
Simulation time 23770379 ps
CPU time 1.09 seconds
Started Apr 16 03:01:44 PM PDT 24
Finished Apr 16 03:01:46 PM PDT 24
Peak memory 217760 kb
Host smart-03826320-a8dc-427f-8fad-6aeb061fc7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688351960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2688351960
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.833934461
Short name T333
Test name
Test status
Simulation time 96090208 ps
CPU time 1.5 seconds
Started Apr 16 03:01:41 PM PDT 24
Finished Apr 16 03:01:43 PM PDT 24
Peak memory 218048 kb
Host smart-ef2b8a1c-3310-49ca-a9ac-afb5b112b826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833934461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.833934461
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2612344938
Short name T360
Test name
Test status
Simulation time 30595424 ps
CPU time 1.13 seconds
Started Apr 16 03:01:42 PM PDT 24
Finished Apr 16 03:01:44 PM PDT 24
Peak memory 223648 kb
Host smart-c3c8ee9b-34dd-443d-a419-e73602c5d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612344938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2612344938
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2731341222
Short name T242
Test name
Test status
Simulation time 16086947 ps
CPU time 0.96 seconds
Started Apr 16 03:01:42 PM PDT 24
Finished Apr 16 03:01:44 PM PDT 24
Peak memory 206696 kb
Host smart-1f4ecfaa-889e-4e3e-95b6-223427807cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731341222 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2731341222
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3641736507
Short name T690
Test name
Test status
Simulation time 53088522 ps
CPU time 0.92 seconds
Started Apr 16 03:01:43 PM PDT 24
Finished Apr 16 03:01:44 PM PDT 24
Peak memory 214904 kb
Host smart-dbf2d262-fa4f-44a4-a2dd-c9b7fe368417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641736507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3641736507
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.354492115
Short name T127
Test name
Test status
Simulation time 2561468785 ps
CPU time 4.42 seconds
Started Apr 16 03:01:45 PM PDT 24
Finished Apr 16 03:01:50 PM PDT 24
Peak memory 215436 kb
Host smart-0151f582-e32e-45d7-934b-731e5401ec89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354492115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.354492115
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.2316912682
Short name T739
Test name
Test status
Simulation time 57859716 ps
CPU time 0.83 seconds
Started Apr 16 03:05:42 PM PDT 24
Finished Apr 16 03:05:43 PM PDT 24
Peak memory 217444 kb
Host smart-d8032550-ae7c-4f5a-9a46-d5b48194875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316912682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2316912682
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.132600714
Short name T432
Test name
Test status
Simulation time 79705999 ps
CPU time 1.35 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:49 PM PDT 24
Peak memory 218000 kb
Host smart-cdd8ab7c-86d0-489a-82e1-9b7b538f3432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132600714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.132600714
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3700841631
Short name T806
Test name
Test status
Simulation time 21177863 ps
CPU time 1.08 seconds
Started Apr 16 03:05:49 PM PDT 24
Finished Apr 16 03:05:51 PM PDT 24
Peak memory 231048 kb
Host smart-05f4bf07-77f3-41ba-8362-529e0895b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700841631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3700841631
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3577961945
Short name T412
Test name
Test status
Simulation time 58673151 ps
CPU time 1.06 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:49 PM PDT 24
Peak memory 216348 kb
Host smart-7237b72d-850a-4d9c-b618-555a57d29bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577961945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3577961945
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1742655399
Short name T558
Test name
Test status
Simulation time 43125086 ps
CPU time 0.93 seconds
Started Apr 16 03:05:45 PM PDT 24
Finished Apr 16 03:05:47 PM PDT 24
Peak memory 230740 kb
Host smart-77578bd9-302e-4805-ae4e-e245033da7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742655399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1742655399
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1040388112
Short name T537
Test name
Test status
Simulation time 48577520 ps
CPU time 1.23 seconds
Started Apr 16 03:05:46 PM PDT 24
Finished Apr 16 03:05:48 PM PDT 24
Peak memory 217748 kb
Host smart-e90d8e55-b7db-4a28-81ec-c7353676909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040388112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1040388112
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1832997859
Short name T66
Test name
Test status
Simulation time 25538653 ps
CPU time 1.1 seconds
Started Apr 16 03:05:48 PM PDT 24
Finished Apr 16 03:05:50 PM PDT 24
Peak memory 219720 kb
Host smart-0ca815a7-ebaf-47bc-a2ff-4d002744e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832997859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1832997859
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3039772682
Short name T159
Test name
Test status
Simulation time 39900522 ps
CPU time 1.09 seconds
Started Apr 16 03:05:48 PM PDT 24
Finished Apr 16 03:05:50 PM PDT 24
Peak memory 217548 kb
Host smart-92f13144-021f-47d4-9c04-301433667013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039772682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3039772682
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.352909321
Short name T387
Test name
Test status
Simulation time 18637980 ps
CPU time 1.15 seconds
Started Apr 16 03:05:48 PM PDT 24
Finished Apr 16 03:05:50 PM PDT 24
Peak memory 230944 kb
Host smart-fea27471-04d2-45ab-aca1-b0e27cecf790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352909321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.352909321
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3635287346
Short name T7
Test name
Test status
Simulation time 50541051 ps
CPU time 1.08 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:49 PM PDT 24
Peak memory 217676 kb
Host smart-46e127f7-ae1b-4305-bff8-a0383e86a280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635287346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3635287346
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3714805105
Short name T758
Test name
Test status
Simulation time 68673605 ps
CPU time 0.84 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:48 PM PDT 24
Peak memory 217344 kb
Host smart-13229ade-228e-499b-9894-743530528458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714805105 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3714805105
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.422731662
Short name T803
Test name
Test status
Simulation time 53757203 ps
CPU time 1.2 seconds
Started Apr 16 03:05:47 PM PDT 24
Finished Apr 16 03:05:49 PM PDT 24
Peak memory 216340 kb
Host smart-ad2b3061-4f75-4d04-a921-fc98ae6c5574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422731662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.422731662
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.4070876730
Short name T501
Test name
Test status
Simulation time 30531107 ps
CPU time 1.31 seconds
Started Apr 16 03:05:49 PM PDT 24
Finished Apr 16 03:05:51 PM PDT 24
Peak memory 224324 kb
Host smart-5d60012c-8533-4efe-9e19-ada3a716af31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070876730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4070876730
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3441857790
Short name T611
Test name
Test status
Simulation time 233178019 ps
CPU time 1.18 seconds
Started Apr 16 03:05:48 PM PDT 24
Finished Apr 16 03:05:50 PM PDT 24
Peak memory 216212 kb
Host smart-9a9f3ef1-2a9f-4e23-b6ae-6b0824f6157d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441857790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3441857790
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3229002780
Short name T433
Test name
Test status
Simulation time 28777058 ps
CPU time 0.85 seconds
Started Apr 16 03:05:50 PM PDT 24
Finished Apr 16 03:05:51 PM PDT 24
Peak memory 217348 kb
Host smart-0060b994-d780-4373-9a73-2b21a6f1df28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229002780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3229002780
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1376866861
Short name T342
Test name
Test status
Simulation time 48870603 ps
CPU time 1.59 seconds
Started Apr 16 03:05:48 PM PDT 24
Finished Apr 16 03:05:50 PM PDT 24
Peak memory 216436 kb
Host smart-31eb514c-105d-443a-8340-c6b83684fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376866861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1376866861
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.266252709
Short name T88
Test name
Test status
Simulation time 27036006 ps
CPU time 1.24 seconds
Started Apr 16 03:05:52 PM PDT 24
Finished Apr 16 03:05:54 PM PDT 24
Peak memory 216536 kb
Host smart-d7cf03c6-3972-4cd0-82f4-474f67a064dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266252709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.266252709
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2059677131
Short name T257
Test name
Test status
Simulation time 39301059 ps
CPU time 1.39 seconds
Started Apr 16 03:05:53 PM PDT 24
Finished Apr 16 03:05:55 PM PDT 24
Peak memory 217256 kb
Host smart-e5aad7a7-5811-422c-8630-1291e2427408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059677131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2059677131
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3705838256
Short name T76
Test name
Test status
Simulation time 54082385 ps
CPU time 1.08 seconds
Started Apr 16 03:05:50 PM PDT 24
Finished Apr 16 03:05:52 PM PDT 24
Peak memory 229208 kb
Host smart-d8d5f80a-9dda-4088-aa69-50310a687cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705838256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3705838256
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1125206408
Short name T556
Test name
Test status
Simulation time 43635742 ps
CPU time 1.15 seconds
Started Apr 16 03:05:51 PM PDT 24
Finished Apr 16 03:05:53 PM PDT 24
Peak memory 217664 kb
Host smart-7c40c74b-799c-4c90-a73a-c81b03ca5cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125206408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1125206408
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2181996732
Short name T765
Test name
Test status
Simulation time 49219517 ps
CPU time 1.19 seconds
Started Apr 16 03:01:45 PM PDT 24
Finished Apr 16 03:01:46 PM PDT 24
Peak memory 215268 kb
Host smart-be0870c7-3ae3-491b-b6c0-1b3b88cebf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181996732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2181996732
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4232809309
Short name T288
Test name
Test status
Simulation time 24303066 ps
CPU time 0.85 seconds
Started Apr 16 03:01:52 PM PDT 24
Finished Apr 16 03:01:54 PM PDT 24
Peak memory 205732 kb
Host smart-eebe8d80-074e-44b6-b7a1-1cc447189274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232809309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4232809309
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3174182729
Short name T356
Test name
Test status
Simulation time 13555553 ps
CPU time 0.9 seconds
Started Apr 16 03:01:52 PM PDT 24
Finished Apr 16 03:01:54 PM PDT 24
Peak memory 215636 kb
Host smart-92f181dd-7b49-4678-b1e2-38e99aac2c10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174182729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3174182729
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.4074309101
Short name T111
Test name
Test status
Simulation time 23355859 ps
CPU time 1.01 seconds
Started Apr 16 03:01:46 PM PDT 24
Finished Apr 16 03:01:48 PM PDT 24
Peak memory 230920 kb
Host smart-87f6cf8e-8913-444e-9ffb-20027019b02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074309101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4074309101
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1345952794
Short name T490
Test name
Test status
Simulation time 54822995 ps
CPU time 1.25 seconds
Started Apr 16 03:01:49 PM PDT 24
Finished Apr 16 03:01:51 PM PDT 24
Peak memory 217148 kb
Host smart-761eabe2-0781-4026-aac2-1f1c4d140524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345952794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1345952794
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.2651356672
Short name T738
Test name
Test status
Simulation time 24753580 ps
CPU time 0.96 seconds
Started Apr 16 03:01:48 PM PDT 24
Finished Apr 16 03:01:50 PM PDT 24
Peak memory 206684 kb
Host smart-2fabb0a5-b585-4199-a8d1-875758bb71a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651356672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2651356672
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1839383619
Short name T394
Test name
Test status
Simulation time 23509879 ps
CPU time 0.83 seconds
Started Apr 16 03:01:45 PM PDT 24
Finished Apr 16 03:01:46 PM PDT 24
Peak memory 214800 kb
Host smart-863f6918-6a0d-49cb-bed0-df8ae6c1dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839383619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1839383619
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2559888758
Short name T837
Test name
Test status
Simulation time 394547338 ps
CPU time 7.09 seconds
Started Apr 16 03:01:44 PM PDT 24
Finished Apr 16 03:01:52 PM PDT 24
Peak memory 214896 kb
Host smart-2d7718b0-fe66-4720-b70d-cd72f2573aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559888758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2559888758
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3784580957
Short name T530
Test name
Test status
Simulation time 73253052068 ps
CPU time 1371.35 seconds
Started Apr 16 03:01:47 PM PDT 24
Finished Apr 16 03:24:39 PM PDT 24
Peak memory 223996 kb
Host smart-0cc2bd1c-4ea3-421f-b89b-445cca159a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784580957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3784580957
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.256088977
Short name T836
Test name
Test status
Simulation time 24131406 ps
CPU time 0.99 seconds
Started Apr 16 03:05:53 PM PDT 24
Finished Apr 16 03:05:55 PM PDT 24
Peak memory 218744 kb
Host smart-3b000a38-0558-458c-b086-a2b08f5b16c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256088977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.256088977
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2383047170
Short name T587
Test name
Test status
Simulation time 114243525 ps
CPU time 1.18 seconds
Started Apr 16 03:05:51 PM PDT 24
Finished Apr 16 03:05:53 PM PDT 24
Peak memory 216436 kb
Host smart-a4e56a2e-4c70-4d64-9b1d-3265f5825c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383047170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2383047170
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2831579324
Short name T23
Test name
Test status
Simulation time 52927836 ps
CPU time 0.81 seconds
Started Apr 16 03:05:57 PM PDT 24
Finished Apr 16 03:05:58 PM PDT 24
Peak memory 217308 kb
Host smart-b51c316c-cfd3-4ec5-9d7f-6c77bfa66ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831579324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2831579324
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.352079882
Short name T291
Test name
Test status
Simulation time 26133983 ps
CPU time 1.18 seconds
Started Apr 16 03:05:52 PM PDT 24
Finished Apr 16 03:05:53 PM PDT 24
Peak memory 216224 kb
Host smart-2c33eab0-dd6a-4b69-9440-4fb3f35aa490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352079882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.352079882
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2195324303
Short name T157
Test name
Test status
Simulation time 19147781 ps
CPU time 1.03 seconds
Started Apr 16 03:05:58 PM PDT 24
Finished Apr 16 03:05:59 PM PDT 24
Peak memory 217784 kb
Host smart-e8a06818-36b5-48b1-ae69-caf1f832757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195324303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2195324303
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1711688479
Short name T428
Test name
Test status
Simulation time 44492556 ps
CPU time 1.68 seconds
Started Apr 16 03:05:58 PM PDT 24
Finished Apr 16 03:06:00 PM PDT 24
Peak memory 217548 kb
Host smart-072a1e6f-9900-4a3e-990b-b167c2aae69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711688479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1711688479
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1794066289
Short name T596
Test name
Test status
Simulation time 24934662 ps
CPU time 0.94 seconds
Started Apr 16 03:05:56 PM PDT 24
Finished Apr 16 03:05:57 PM PDT 24
Peak memory 217720 kb
Host smart-e3205ad3-5f6b-466d-82fc-d011d4641b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794066289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1794066289
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.273289403
Short name T634
Test name
Test status
Simulation time 132814781 ps
CPU time 2.92 seconds
Started Apr 16 03:06:00 PM PDT 24
Finished Apr 16 03:06:04 PM PDT 24
Peak memory 218732 kb
Host smart-7bf22002-396a-46c0-9fcb-a6b80a15df49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273289403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.273289403
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1697989039
Short name T113
Test name
Test status
Simulation time 21218625 ps
CPU time 0.9 seconds
Started Apr 16 03:05:59 PM PDT 24
Finished Apr 16 03:06:01 PM PDT 24
Peak memory 217656 kb
Host smart-d7c270d2-2068-4dd7-8fb9-3ae8cd0d3700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697989039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1697989039
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1669753110
Short name T754
Test name
Test status
Simulation time 114053544 ps
CPU time 1.56 seconds
Started Apr 16 03:06:00 PM PDT 24
Finished Apr 16 03:06:02 PM PDT 24
Peak memory 218024 kb
Host smart-a8c76cd0-2204-4165-a257-eece28bd9d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669753110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1669753110
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1257199976
Short name T130
Test name
Test status
Simulation time 19384777 ps
CPU time 1.03 seconds
Started Apr 16 03:05:57 PM PDT 24
Finished Apr 16 03:05:58 PM PDT 24
Peak memory 217736 kb
Host smart-c794a468-2b9b-45ad-82aa-6260b48cff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257199976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1257199976
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.653218629
Short name T453
Test name
Test status
Simulation time 67321200 ps
CPU time 1.11 seconds
Started Apr 16 03:05:59 PM PDT 24
Finished Apr 16 03:06:01 PM PDT 24
Peak memory 217636 kb
Host smart-1f780860-5a8e-4969-8651-4ab3208ff8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653218629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.653218629
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3370012048
Short name T318
Test name
Test status
Simulation time 20725208 ps
CPU time 0.91 seconds
Started Apr 16 03:05:57 PM PDT 24
Finished Apr 16 03:05:59 PM PDT 24
Peak memory 217596 kb
Host smart-bc9cd08d-98b4-408b-859a-d78bb6dcf970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370012048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3370012048
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2458907838
Short name T631
Test name
Test status
Simulation time 55422167 ps
CPU time 2.02 seconds
Started Apr 16 03:05:56 PM PDT 24
Finished Apr 16 03:05:59 PM PDT 24
Peak memory 219156 kb
Host smart-c5a056d2-b274-4f5a-941b-e9ed4ec08c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458907838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2458907838
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2283143144
Short name T77
Test name
Test status
Simulation time 60049002 ps
CPU time 1.01 seconds
Started Apr 16 03:06:01 PM PDT 24
Finished Apr 16 03:06:03 PM PDT 24
Peak memory 218872 kb
Host smart-c682270f-158c-4ba4-ad01-b798397893b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283143144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2283143144
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3698754842
Short name T366
Test name
Test status
Simulation time 48693332 ps
CPU time 1.69 seconds
Started Apr 16 03:06:03 PM PDT 24
Finished Apr 16 03:06:05 PM PDT 24
Peak memory 217464 kb
Host smart-bd6c6000-1161-4cf3-a2dd-aeee243ce4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698754842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3698754842
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.798627772
Short name T49
Test name
Test status
Simulation time 63091782 ps
CPU time 1.16 seconds
Started Apr 16 03:06:02 PM PDT 24
Finished Apr 16 03:06:04 PM PDT 24
Peak memory 229488 kb
Host smart-59db7cd6-76b2-445e-874d-75e2e9f1c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798627772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.798627772
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3378854610
Short name T769
Test name
Test status
Simulation time 2314616974 ps
CPU time 62.6 seconds
Started Apr 16 03:06:02 PM PDT 24
Finished Apr 16 03:07:06 PM PDT 24
Peak memory 217652 kb
Host smart-410a616f-e93b-4041-bfda-cd0d637a0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378854610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3378854610
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1576772547
Short name T79
Test name
Test status
Simulation time 35161873 ps
CPU time 1.18 seconds
Started Apr 16 03:06:03 PM PDT 24
Finished Apr 16 03:06:05 PM PDT 24
Peak memory 229356 kb
Host smart-44c98179-4ebb-4326-afbc-15ef12e44dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576772547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1576772547
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.216231244
Short name T786
Test name
Test status
Simulation time 41209074 ps
CPU time 1.41 seconds
Started Apr 16 03:06:02 PM PDT 24
Finished Apr 16 03:06:04 PM PDT 24
Peak memory 217268 kb
Host smart-f5bfdcc9-695c-4efa-9f2f-39d20d4c045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216231244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.216231244
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2367102693
Short name T608
Test name
Test status
Simulation time 277387785 ps
CPU time 1.41 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:05 PM PDT 24
Peak memory 215272 kb
Host smart-39af5db5-7ea0-49bb-86da-27dd1eeac8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367102693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2367102693
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3269631785
Short name T289
Test name
Test status
Simulation time 90544904 ps
CPU time 1.01 seconds
Started Apr 16 03:02:00 PM PDT 24
Finished Apr 16 03:02:02 PM PDT 24
Peak memory 206528 kb
Host smart-3c06c384-59fa-4e95-b165-08b51fd272d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269631785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3269631785
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2201503404
Short name T684
Test name
Test status
Simulation time 29997537 ps
CPU time 0.84 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:04 PM PDT 24
Peak memory 215020 kb
Host smart-2b7cfae6-e0c3-4431-ad8d-3ee47d461dce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201503404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2201503404
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3753000170
Short name T64
Test name
Test status
Simulation time 54760569 ps
CPU time 0.97 seconds
Started Apr 16 03:01:56 PM PDT 24
Finished Apr 16 03:01:57 PM PDT 24
Peak memory 215196 kb
Host smart-18cce709-9a0d-424d-ace5-58770c958569
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753000170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3753000170
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3561094067
Short name T123
Test name
Test status
Simulation time 118366402 ps
CPU time 1.03 seconds
Started Apr 16 03:01:58 PM PDT 24
Finished Apr 16 03:02:00 PM PDT 24
Peak memory 219784 kb
Host smart-1dfa1245-197f-4688-aa73-63cc09a94677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561094067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3561094067
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.4041200544
Short name T781
Test name
Test status
Simulation time 103898992 ps
CPU time 1.41 seconds
Started Apr 16 03:01:50 PM PDT 24
Finished Apr 16 03:01:52 PM PDT 24
Peak memory 218708 kb
Host smart-d7b6f560-7c50-46c7-ad7e-743abf130f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041200544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.4041200544
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.560400487
Short name T761
Test name
Test status
Simulation time 22197177 ps
CPU time 1.12 seconds
Started Apr 16 03:01:53 PM PDT 24
Finished Apr 16 03:01:55 PM PDT 24
Peak memory 215480 kb
Host smart-feb7966c-2620-4099-86e6-cf3edbd5496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560400487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.560400487
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.556931155
Short name T243
Test name
Test status
Simulation time 30004560 ps
CPU time 0.93 seconds
Started Apr 16 03:01:51 PM PDT 24
Finished Apr 16 03:01:54 PM PDT 24
Peak memory 206572 kb
Host smart-fd692392-a7f6-4067-a6ca-51d8ded13ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556931155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.556931155
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3403895570
Short name T410
Test name
Test status
Simulation time 23050887 ps
CPU time 0.96 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:04 PM PDT 24
Peak memory 206640 kb
Host smart-257181e0-678e-4468-8384-32e0a8b93437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403895570 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3403895570
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3034355464
Short name T613
Test name
Test status
Simulation time 77742526 ps
CPU time 2.09 seconds
Started Apr 16 03:01:52 PM PDT 24
Finished Apr 16 03:01:56 PM PDT 24
Peak memory 216132 kb
Host smart-f739ff38-9485-4a5f-842c-bb11640bd61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034355464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3034355464
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_err.4264933031
Short name T745
Test name
Test status
Simulation time 45542419 ps
CPU time 0.83 seconds
Started Apr 16 03:06:02 PM PDT 24
Finished Apr 16 03:06:03 PM PDT 24
Peak memory 217520 kb
Host smart-c29ce015-1399-447f-9d3c-a13b378ad564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264933031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4264933031
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.105426616
Short name T583
Test name
Test status
Simulation time 52853080 ps
CPU time 1.77 seconds
Started Apr 16 03:06:04 PM PDT 24
Finished Apr 16 03:06:06 PM PDT 24
Peak memory 217492 kb
Host smart-5b797cb5-8c5c-4358-b776-36af9167759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105426616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.105426616
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2175670485
Short name T133
Test name
Test status
Simulation time 184471451 ps
CPU time 0.96 seconds
Started Apr 16 03:06:05 PM PDT 24
Finished Apr 16 03:06:06 PM PDT 24
Peak memory 218856 kb
Host smart-ede4c07a-27d0-457c-9aeb-525162d4d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175670485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2175670485
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1027899125
Short name T359
Test name
Test status
Simulation time 114928587 ps
CPU time 2.45 seconds
Started Apr 16 03:06:03 PM PDT 24
Finished Apr 16 03:06:06 PM PDT 24
Peak memory 218428 kb
Host smart-b96d2936-b361-4f8e-acc1-7f4f4967b2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027899125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1027899125
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1731595130
Short name T434
Test name
Test status
Simulation time 24903571 ps
CPU time 1.19 seconds
Started Apr 16 03:06:01 PM PDT 24
Finished Apr 16 03:06:03 PM PDT 24
Peak memory 217784 kb
Host smart-d0f83c7d-506b-4edf-8190-76e0064cace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731595130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1731595130
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3591641658
Short name T402
Test name
Test status
Simulation time 87106392 ps
CPU time 1.27 seconds
Started Apr 16 03:06:01 PM PDT 24
Finished Apr 16 03:06:03 PM PDT 24
Peak memory 216472 kb
Host smart-321a0876-b657-4cb4-89a8-11e7a78254f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591641658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3591641658
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3877820328
Short name T107
Test name
Test status
Simulation time 24241140 ps
CPU time 1.06 seconds
Started Apr 16 03:06:01 PM PDT 24
Finished Apr 16 03:06:03 PM PDT 24
Peak memory 217708 kb
Host smart-a4abc4fd-948f-423b-9918-cc0d7fa672d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877820328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3877820328
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2437253224
Short name T440
Test name
Test status
Simulation time 62395965 ps
CPU time 1.79 seconds
Started Apr 16 03:06:02 PM PDT 24
Finished Apr 16 03:06:05 PM PDT 24
Peak memory 217472 kb
Host smart-b74864f0-60e9-42a0-a76e-2c818ecd8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437253224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2437253224
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2462975984
Short name T92
Test name
Test status
Simulation time 29861466 ps
CPU time 1.33 seconds
Started Apr 16 03:06:07 PM PDT 24
Finished Apr 16 03:06:08 PM PDT 24
Peak memory 224008 kb
Host smart-7bd00df3-b19d-48ac-bb21-afafdd4fd5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462975984 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2462975984
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3492485537
Short name T646
Test name
Test status
Simulation time 39623502 ps
CPU time 1.54 seconds
Started Apr 16 03:06:03 PM PDT 24
Finished Apr 16 03:06:05 PM PDT 24
Peak memory 217528 kb
Host smart-237872f9-9e49-4056-9c7b-24469d8ce0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492485537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3492485537
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2749164045
Short name T62
Test name
Test status
Simulation time 33470408 ps
CPU time 1.03 seconds
Started Apr 16 03:06:08 PM PDT 24
Finished Apr 16 03:06:10 PM PDT 24
Peak memory 229404 kb
Host smart-dc5e0057-5401-4715-91c2-18232dcc9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749164045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2749164045
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3501001636
Short name T747
Test name
Test status
Simulation time 153311366 ps
CPU time 1.32 seconds
Started Apr 16 03:06:05 PM PDT 24
Finished Apr 16 03:06:07 PM PDT 24
Peak memory 216308 kb
Host smart-6022f647-3dbf-42ab-a0f0-e951c1df9648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501001636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3501001636
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1101594405
Short name T102
Test name
Test status
Simulation time 18676254 ps
CPU time 1.08 seconds
Started Apr 16 03:06:07 PM PDT 24
Finished Apr 16 03:06:09 PM PDT 24
Peak memory 217792 kb
Host smart-4cc3a1d6-6ea9-477b-8840-0dda990c4fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101594405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1101594405
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2078813144
Short name T526
Test name
Test status
Simulation time 60109787 ps
CPU time 1.5 seconds
Started Apr 16 03:06:07 PM PDT 24
Finished Apr 16 03:06:10 PM PDT 24
Peak memory 216408 kb
Host smart-b9459085-adad-401f-aa48-76cd628e6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078813144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2078813144
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1354186678
Short name T518
Test name
Test status
Simulation time 61913823 ps
CPU time 0.99 seconds
Started Apr 16 03:06:08 PM PDT 24
Finished Apr 16 03:06:10 PM PDT 24
Peak memory 230864 kb
Host smart-9e36d271-e48b-452a-a6ba-3d30cc64c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354186678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1354186678
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3278330835
Short name T578
Test name
Test status
Simulation time 34357310 ps
CPU time 1.46 seconds
Started Apr 16 03:06:09 PM PDT 24
Finished Apr 16 03:06:11 PM PDT 24
Peak memory 218984 kb
Host smart-fe63a68d-4f91-4155-9564-5d82f2e595be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278330835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3278330835
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.319206922
Short name T112
Test name
Test status
Simulation time 23036288 ps
CPU time 0.89 seconds
Started Apr 16 03:06:08 PM PDT 24
Finished Apr 16 03:06:09 PM PDT 24
Peak memory 217744 kb
Host smart-c8cf5de3-8929-4147-805b-217050933fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319206922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.319206922
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1105770417
Short name T301
Test name
Test status
Simulation time 55601110 ps
CPU time 1.22 seconds
Started Apr 16 03:06:07 PM PDT 24
Finished Apr 16 03:06:09 PM PDT 24
Peak memory 217532 kb
Host smart-374f8b46-2f9e-49ad-950b-06079f6aa203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105770417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1105770417
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3177246495
Short name T67
Test name
Test status
Simulation time 49790894 ps
CPU time 1.11 seconds
Started Apr 16 03:06:09 PM PDT 24
Finished Apr 16 03:06:11 PM PDT 24
Peak memory 229260 kb
Host smart-b9f5333d-77be-4a6e-8d7d-64b8cb2d2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177246495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3177246495
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.1031994468
Short name T226
Test name
Test status
Simulation time 57826049 ps
CPU time 1.19 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:04 PM PDT 24
Peak memory 215276 kb
Host smart-d80558fc-5c97-4aaf-bff0-656372a2e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031994468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1031994468
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3936077008
Short name T542
Test name
Test status
Simulation time 188754135 ps
CPU time 0.99 seconds
Started Apr 16 03:02:08 PM PDT 24
Finished Apr 16 03:02:10 PM PDT 24
Peak memory 205728 kb
Host smart-66330a72-9c62-417f-a171-9c526a75c1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936077008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3936077008
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1541787689
Short name T165
Test name
Test status
Simulation time 37399863 ps
CPU time 0.85 seconds
Started Apr 16 03:02:03 PM PDT 24
Finished Apr 16 03:02:05 PM PDT 24
Peak memory 215600 kb
Host smart-05780b68-6a55-41ac-8943-125597ce76da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541787689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1541787689
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4126459038
Short name T800
Test name
Test status
Simulation time 21114647 ps
CPU time 1.07 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:04 PM PDT 24
Peak memory 217232 kb
Host smart-3e4e4f0e-26ac-43a4-8a45-28a109e8d6bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126459038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4126459038
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1477316189
Short name T516
Test name
Test status
Simulation time 33080632 ps
CPU time 1.11 seconds
Started Apr 16 03:02:03 PM PDT 24
Finished Apr 16 03:02:05 PM PDT 24
Peak memory 216576 kb
Host smart-76094551-9f9a-4ada-b001-d25684a676a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477316189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1477316189
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3084702017
Short name T726
Test name
Test status
Simulation time 74511363 ps
CPU time 2.39 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:05 PM PDT 24
Peak memory 217808 kb
Host smart-6c68de66-492a-425d-bb9b-005744dac4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084702017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3084702017
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3465765164
Short name T815
Test name
Test status
Simulation time 25242291 ps
CPU time 0.95 seconds
Started Apr 16 03:02:05 PM PDT 24
Finished Apr 16 03:02:07 PM PDT 24
Peak memory 215188 kb
Host smart-67a364cd-a56d-4f32-9733-1f07f7a6c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465765164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3465765164
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2135555484
Short name T56
Test name
Test status
Simulation time 35591872 ps
CPU time 0.95 seconds
Started Apr 16 03:02:02 PM PDT 24
Finished Apr 16 03:02:04 PM PDT 24
Peak memory 206692 kb
Host smart-5d4f6263-bf11-442e-818b-cde2956761d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135555484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2135555484
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2289484883
Short name T487
Test name
Test status
Simulation time 102228070 ps
CPU time 0.95 seconds
Started Apr 16 03:02:00 PM PDT 24
Finished Apr 16 03:02:02 PM PDT 24
Peak memory 214864 kb
Host smart-1fbfb087-18ab-4905-b9e6-7b38202ab531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289484883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2289484883
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2817241300
Short name T597
Test name
Test status
Simulation time 548341674 ps
CPU time 5.31 seconds
Started Apr 16 03:01:58 PM PDT 24
Finished Apr 16 03:02:05 PM PDT 24
Peak memory 216132 kb
Host smart-eab310a5-7767-429a-9800-602947814267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817241300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2817241300
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.870992119
Short name T581
Test name
Test status
Simulation time 121083893918 ps
CPU time 752.75 seconds
Started Apr 16 03:02:04 PM PDT 24
Finished Apr 16 03:14:38 PM PDT 24
Peak memory 220204 kb
Host smart-0f106ddc-e44e-4550-b149-9e7e42f88854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870992119 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.870992119
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1474720955
Short name T73
Test name
Test status
Simulation time 20980129 ps
CPU time 1.12 seconds
Started Apr 16 03:06:08 PM PDT 24
Finished Apr 16 03:06:10 PM PDT 24
Peak memory 218980 kb
Host smart-e8b11be8-5d30-4549-b509-f90f56d98c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474720955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1474720955
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.589550525
Short name T89
Test name
Test status
Simulation time 48220330 ps
CPU time 1.03 seconds
Started Apr 16 03:06:12 PM PDT 24
Finished Apr 16 03:06:14 PM PDT 24
Peak memory 229404 kb
Host smart-a8541ff1-ffc6-476a-9dcc-2ab6ae7e580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589550525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.589550525
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.4232352388
Short name T117
Test name
Test status
Simulation time 28619101 ps
CPU time 0.86 seconds
Started Apr 16 03:06:11 PM PDT 24
Finished Apr 16 03:06:13 PM PDT 24
Peak memory 217456 kb
Host smart-f37c2d73-8e04-4a6a-be91-80783b854d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232352388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4232352388
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2960509953
Short name T748
Test name
Test status
Simulation time 85687987 ps
CPU time 1.19 seconds
Started Apr 16 03:06:12 PM PDT 24
Finished Apr 16 03:06:14 PM PDT 24
Peak memory 216260 kb
Host smart-c66522a1-dd41-4925-a74d-c029a85f6e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960509953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2960509953
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3830000262
Short name T68
Test name
Test status
Simulation time 32303086 ps
CPU time 1.08 seconds
Started Apr 16 03:06:17 PM PDT 24
Finished Apr 16 03:06:19 PM PDT 24
Peak memory 218904 kb
Host smart-da873013-e0e1-4398-b5d4-720e34137778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830000262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3830000262
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3581682271
Short name T304
Test name
Test status
Simulation time 29752767 ps
CPU time 1.24 seconds
Started Apr 16 03:06:10 PM PDT 24
Finished Apr 16 03:06:11 PM PDT 24
Peak memory 217588 kb
Host smart-e63eea71-ebbc-4dac-a991-34b3012a1e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581682271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3581682271
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.279239052
Short name T91
Test name
Test status
Simulation time 23650303 ps
CPU time 0.93 seconds
Started Apr 16 03:06:20 PM PDT 24
Finished Apr 16 03:06:21 PM PDT 24
Peak memory 217580 kb
Host smart-58a94fb8-653d-4ece-8c22-42246a6ab925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279239052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.279239052
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4186381201
Short name T569
Test name
Test status
Simulation time 148314219 ps
CPU time 1.49 seconds
Started Apr 16 03:06:18 PM PDT 24
Finished Apr 16 03:06:21 PM PDT 24
Peak memory 217976 kb
Host smart-e266ec90-37f7-45e7-869d-474fa061f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186381201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4186381201
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.338706509
Short name T732
Test name
Test status
Simulation time 34164905 ps
CPU time 1.41 seconds
Started Apr 16 03:06:19 PM PDT 24
Finished Apr 16 03:06:21 PM PDT 24
Peak memory 233316 kb
Host smart-c183865a-8303-41e4-bf8d-24d11533906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338706509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.338706509
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.929071692
Short name T625
Test name
Test status
Simulation time 49629147 ps
CPU time 1.61 seconds
Started Apr 16 03:06:17 PM PDT 24
Finished Apr 16 03:06:20 PM PDT 24
Peak memory 216316 kb
Host smart-190756ca-84f5-4376-8934-493ff3e34b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929071692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.929071692
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3825585471
Short name T400
Test name
Test status
Simulation time 24477515 ps
CPU time 0.91 seconds
Started Apr 16 03:06:17 PM PDT 24
Finished Apr 16 03:06:18 PM PDT 24
Peak memory 217508 kb
Host smart-78b5ec73-848e-4295-815b-db4edf29c28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825585471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3825585471
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1966752109
Short name T418
Test name
Test status
Simulation time 59284808 ps
CPU time 1.53 seconds
Started Apr 16 03:06:17 PM PDT 24
Finished Apr 16 03:06:19 PM PDT 24
Peak memory 217816 kb
Host smart-cfa0b99c-1b8e-4bcf-b557-f5110b6a1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966752109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1966752109
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1462911864
Short name T82
Test name
Test status
Simulation time 24951155 ps
CPU time 1.24 seconds
Started Apr 16 03:06:16 PM PDT 24
Finished Apr 16 03:06:18 PM PDT 24
Peak memory 232404 kb
Host smart-8c0db729-b5ed-41db-bf8e-7c11b836dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462911864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1462911864
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.174749255
Short name T160
Test name
Test status
Simulation time 75668233 ps
CPU time 2.64 seconds
Started Apr 16 03:06:18 PM PDT 24
Finished Apr 16 03:06:21 PM PDT 24
Peak memory 219320 kb
Host smart-b6922b5a-54bf-4e83-8d92-cc683034d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174749255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.174749255
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1550544259
Short name T614
Test name
Test status
Simulation time 28815118 ps
CPU time 0.87 seconds
Started Apr 16 03:06:18 PM PDT 24
Finished Apr 16 03:06:20 PM PDT 24
Peak memory 217300 kb
Host smart-346902ff-b3c9-4b37-9afb-44572f2432b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550544259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1550544259
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1334877877
Short name T645
Test name
Test status
Simulation time 111006821 ps
CPU time 1.14 seconds
Started Apr 16 03:06:17 PM PDT 24
Finished Apr 16 03:06:18 PM PDT 24
Peak memory 217764 kb
Host smart-569580d6-fe4f-470d-ace3-1634349d20e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334877877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1334877877
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.740466849
Short name T106
Test name
Test status
Simulation time 18872256 ps
CPU time 1.09 seconds
Started Apr 16 03:06:23 PM PDT 24
Finished Apr 16 03:06:25 PM PDT 24
Peak memory 217588 kb
Host smart-1e150dcf-8a6c-46f1-b5f1-1d8b2f441392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740466849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.740466849
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3256866619
Short name T507
Test name
Test status
Simulation time 142871260 ps
CPU time 1.06 seconds
Started Apr 16 03:06:22 PM PDT 24
Finished Apr 16 03:06:24 PM PDT 24
Peak memory 216244 kb
Host smart-47bf9efb-1d63-42a2-b09e-fc55de1afd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256866619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3256866619
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%